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-rw-r--r--arch/powerpc/sysdev/qe_lib/qe.c14
-rw-r--r--include/asm-powerpc/qe.h94
2 files changed, 56 insertions, 52 deletions
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 3d57d3835b04..1df3b4a6832f 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -167,19 +167,20 @@ unsigned int get_brg_clk(void)
167 167
168/* Program the BRG to the given sampling rate and multiplier 168/* Program the BRG to the given sampling rate and multiplier
169 * 169 *
170 * @brg: the BRG, 1-16 170 * @brg: the BRG, QE_BRG1 - QE_BRG16
171 * @rate: the desired sampling rate 171 * @rate: the desired sampling rate
172 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or 172 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
173 * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01, 173 * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
174 * then 'multiplier' should be 8. 174 * then 'multiplier' should be 8.
175 *
176 * Also note that the value programmed into the BRGC register must be even.
177 */ 175 */
178void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier) 176int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
179{ 177{
180 u32 divisor, tempval; 178 u32 divisor, tempval;
181 u32 div16 = 0; 179 u32 div16 = 0;
182 180
181 if ((brg < QE_BRG1) || (brg > QE_BRG16))
182 return -EINVAL;
183
183 divisor = get_brg_clk() / (rate * multiplier); 184 divisor = get_brg_clk() / (rate * multiplier);
184 185
185 if (divisor > QE_BRGC_DIVISOR_MAX + 1) { 186 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
@@ -196,8 +197,11 @@ void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier)
196 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | 197 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
197 QE_BRGC_ENABLE | div16; 198 QE_BRGC_ENABLE | div16;
198 199
199 out_be32(&qe_immr->brg.brgc[brg - 1], tempval); 200 out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
201
202 return 0;
200} 203}
204EXPORT_SYMBOL(qe_setbrg);
201 205
202/* Initialize SNUMs (thread serial numbers) according to 206/* Initialize SNUMs (thread serial numbers) according to
203 * QE Module Control chapter, SNUM table 207 * QE Module Control chapter, SNUM table
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 0dabe46a29d2..bcf60bef6524 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -28,6 +28,52 @@
28#define MEM_PART_SECONDARY 1 28#define MEM_PART_SECONDARY 1
29#define MEM_PART_MURAM 2 29#define MEM_PART_MURAM 2
30 30
31/* Clocks and BRGs */
32enum qe_clock {
33 QE_CLK_NONE = 0,
34 QE_BRG1, /* Baud Rate Generator 1 */
35 QE_BRG2, /* Baud Rate Generator 2 */
36 QE_BRG3, /* Baud Rate Generator 3 */
37 QE_BRG4, /* Baud Rate Generator 4 */
38 QE_BRG5, /* Baud Rate Generator 5 */
39 QE_BRG6, /* Baud Rate Generator 6 */
40 QE_BRG7, /* Baud Rate Generator 7 */
41 QE_BRG8, /* Baud Rate Generator 8 */
42 QE_BRG9, /* Baud Rate Generator 9 */
43 QE_BRG10, /* Baud Rate Generator 10 */
44 QE_BRG11, /* Baud Rate Generator 11 */
45 QE_BRG12, /* Baud Rate Generator 12 */
46 QE_BRG13, /* Baud Rate Generator 13 */
47 QE_BRG14, /* Baud Rate Generator 14 */
48 QE_BRG15, /* Baud Rate Generator 15 */
49 QE_BRG16, /* Baud Rate Generator 16 */
50 QE_CLK1, /* Clock 1 */
51 QE_CLK2, /* Clock 2 */
52 QE_CLK3, /* Clock 3 */
53 QE_CLK4, /* Clock 4 */
54 QE_CLK5, /* Clock 5 */
55 QE_CLK6, /* Clock 6 */
56 QE_CLK7, /* Clock 7 */
57 QE_CLK8, /* Clock 8 */
58 QE_CLK9, /* Clock 9 */
59 QE_CLK10, /* Clock 10 */
60 QE_CLK11, /* Clock 11 */
61 QE_CLK12, /* Clock 12 */
62 QE_CLK13, /* Clock 13 */
63 QE_CLK14, /* Clock 14 */
64 QE_CLK15, /* Clock 15 */
65 QE_CLK16, /* Clock 16 */
66 QE_CLK17, /* Clock 17 */
67 QE_CLK18, /* Clock 18 */
68 QE_CLK19, /* Clock 19 */
69 QE_CLK20, /* Clock 20 */
70 QE_CLK21, /* Clock 21 */
71 QE_CLK22, /* Clock 22 */
72 QE_CLK23, /* Clock 23 */
73 QE_CLK24, /* Clock 24 */
74 QE_CLK_DUMMY
75};
76
31/* Export QE common operations */ 77/* Export QE common operations */
32extern void qe_reset(void); 78extern void qe_reset(void);
33extern int par_io_init(struct device_node *np); 79extern int par_io_init(struct device_node *np);
@@ -38,7 +84,7 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
38 84
39/* QE internal API */ 85/* QE internal API */
40int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 86int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
41void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier); 87int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
42int qe_get_snum(void); 88int qe_get_snum(void);
43void qe_put_snum(u8 snum); 89void qe_put_snum(u8 snum);
44unsigned long qe_muram_alloc(int size, int align); 90unsigned long qe_muram_alloc(int size, int align);
@@ -129,52 +175,6 @@ enum comm_dir {
129 COMM_DIR_RX_AND_TX = 3 175 COMM_DIR_RX_AND_TX = 3
130}; 176};
131 177
132/* Clocks and BRGs */
133enum qe_clock {
134 QE_CLK_NONE = 0,
135 QE_BRG1, /* Baud Rate Generator 1 */
136 QE_BRG2, /* Baud Rate Generator 2 */
137 QE_BRG3, /* Baud Rate Generator 3 */
138 QE_BRG4, /* Baud Rate Generator 4 */
139 QE_BRG5, /* Baud Rate Generator 5 */
140 QE_BRG6, /* Baud Rate Generator 6 */
141 QE_BRG7, /* Baud Rate Generator 7 */
142 QE_BRG8, /* Baud Rate Generator 8 */
143 QE_BRG9, /* Baud Rate Generator 9 */
144 QE_BRG10, /* Baud Rate Generator 10 */
145 QE_BRG11, /* Baud Rate Generator 11 */
146 QE_BRG12, /* Baud Rate Generator 12 */
147 QE_BRG13, /* Baud Rate Generator 13 */
148 QE_BRG14, /* Baud Rate Generator 14 */
149 QE_BRG15, /* Baud Rate Generator 15 */
150 QE_BRG16, /* Baud Rate Generator 16 */
151 QE_CLK1, /* Clock 1 */
152 QE_CLK2, /* Clock 2 */
153 QE_CLK3, /* Clock 3 */
154 QE_CLK4, /* Clock 4 */
155 QE_CLK5, /* Clock 5 */
156 QE_CLK6, /* Clock 6 */
157 QE_CLK7, /* Clock 7 */
158 QE_CLK8, /* Clock 8 */
159 QE_CLK9, /* Clock 9 */
160 QE_CLK10, /* Clock 10 */
161 QE_CLK11, /* Clock 11 */
162 QE_CLK12, /* Clock 12 */
163 QE_CLK13, /* Clock 13 */
164 QE_CLK14, /* Clock 14 */
165 QE_CLK15, /* Clock 15 */
166 QE_CLK16, /* Clock 16 */
167 QE_CLK17, /* Clock 17 */
168 QE_CLK18, /* Clock 18 */
169 QE_CLK19, /* Clock 19 */
170 QE_CLK20, /* Clock 20 */
171 QE_CLK21, /* Clock 21 */
172 QE_CLK22, /* Clock 22 */
173 QE_CLK23, /* Clock 23 */
174 QE_CLK24, /* Clock 24 */
175 QE_CLK_DUMMY,
176};
177
178/* QE CMXUCR Registers. 178/* QE CMXUCR Registers.
179 * There are two UCCs represented in each of the four CMXUCR registers. 179 * There are two UCCs represented in each of the four CMXUCR registers.
180 * These values are for the UCC in the LSBs 180 * These values are for the UCC in the LSBs
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 20:14:10 -0500