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-rw-r--r--drivers/i2c/busses/i2c-imx.c86
-rw-r--r--drivers/i2c/busses/i2c-mpc.c10
2 files changed, 59 insertions, 37 deletions
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 4afba3ec2a61..e3654d683e15 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -120,19 +120,26 @@ struct imx_i2c_struct {
120 wait_queue_head_t queue; 120 wait_queue_head_t queue;
121 unsigned long i2csr; 121 unsigned long i2csr;
122 unsigned int disable_delay; 122 unsigned int disable_delay;
123 int stopped;
124 unsigned int ifdr; /* IMX_I2C_IFDR */
123}; 125};
124 126
125/** Functions for IMX I2C adapter driver *************************************** 127/** Functions for IMX I2C adapter driver ***************************************
126*******************************************************************************/ 128*******************************************************************************/
127 129
128static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx) 130static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
129{ 131{
130 unsigned long orig_jiffies = jiffies; 132 unsigned long orig_jiffies = jiffies;
133 unsigned int temp;
131 134
132 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 135 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
133 136
134 /* wait for bus not busy */ 137 while (1) {
135 while (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_IBB) { 138 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
139 if (for_busy && (temp & I2SR_IBB))
140 break;
141 if (!for_busy && !(temp & I2SR_IBB))
142 break;
136 if (signal_pending(current)) { 143 if (signal_pending(current)) {
137 dev_dbg(&i2c_imx->adapter.dev, 144 dev_dbg(&i2c_imx->adapter.dev,
138 "<%s> I2C Interrupted\n", __func__); 145 "<%s> I2C Interrupted\n", __func__);
@@ -179,41 +186,62 @@ static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
179 return 0; 186 return 0;
180} 187}
181 188
182static void i2c_imx_start(struct imx_i2c_struct *i2c_imx) 189static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
183{ 190{
184 unsigned int temp = 0; 191 unsigned int temp = 0;
192 int result;
185 193
186 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 194 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
187 195
196 clk_enable(i2c_imx->clk);
197 writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
188 /* Enable I2C controller */ 198 /* Enable I2C controller */
199 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
189 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR); 200 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
201
202 /* Wait controller to be stable */
203 udelay(50);
204
190 /* Start I2C transaction */ 205 /* Start I2C transaction */
191 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 206 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
192 temp |= I2CR_MSTA; 207 temp |= I2CR_MSTA;
193 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 208 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
209 result = i2c_imx_bus_busy(i2c_imx, 1);
210 if (result)
211 return result;
212 i2c_imx->stopped = 0;
213
194 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 214 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
195 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 215 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
216 return result;
196} 217}
197 218
198static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) 219static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
199{ 220{
200 unsigned int temp = 0; 221 unsigned int temp = 0;
201 222
202 /* Stop I2C transaction */ 223 if (!i2c_imx->stopped) {
203 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 224 /* Stop I2C transaction */
204 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 225 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
205 temp &= ~I2CR_MSTA; 226 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
206 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 227 temp &= ~(I2CR_MSTA | I2CR_MTX);
207 /* setup chip registers to defaults */ 228 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
208 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR); 229 i2c_imx->stopped = 1;
209 writeb(0, i2c_imx->base + IMX_I2C_I2SR); 230 }
210 /* 231 if (cpu_is_mx1()) {
211 * This delay caused by an i.MXL hardware bug. 232 /*
212 * If no (or too short) delay, no "STOP" bit will be generated. 233 * This delay caused by an i.MXL hardware bug.
213 */ 234 * If no (or too short) delay, no "STOP" bit will be generated.
214 udelay(i2c_imx->disable_delay); 235 */
236 udelay(i2c_imx->disable_delay);
237 }
238
239 if (!i2c_imx->stopped)
240 i2c_imx_bus_busy(i2c_imx, 0);
241
215 /* Disable I2C controller */ 242 /* Disable I2C controller */
216 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 243 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
244 clk_disable(i2c_imx->clk);
217} 245}
218 246
219static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 247static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
@@ -233,8 +261,8 @@ static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
233 else 261 else
234 for (i = 0; i2c_clk_div[i][0] < div; i++); 262 for (i = 0; i2c_clk_div[i][0] < div; i++);
235 263
236 /* Write divider value to register */ 264 /* Store divider value */
237 writeb(i2c_clk_div[i][1], i2c_imx->base + IMX_I2C_IFDR); 265 i2c_imx->ifdr = i2c_clk_div[i][1];
238 266
239 /* 267 /*
240 * There dummy delay is calculated. 268 * There dummy delay is calculated.
@@ -341,11 +369,15 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
341 if (result) 369 if (result)
342 return result; 370 return result;
343 if (i == (msgs->len - 1)) { 371 if (i == (msgs->len - 1)) {
372 /* It must generate STOP before read I2DR to prevent
373 controller from generating another clock cycle */
344 dev_dbg(&i2c_imx->adapter.dev, 374 dev_dbg(&i2c_imx->adapter.dev,
345 "<%s> clear MSTA\n", __func__); 375 "<%s> clear MSTA\n", __func__);
346 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 376 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
347 temp &= ~I2CR_MSTA; 377 temp &= ~(I2CR_MSTA | I2CR_MTX);
348 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 378 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
379 i2c_imx_bus_busy(i2c_imx, 0);
380 i2c_imx->stopped = 1;
349 } else if (i == (msgs->len - 2)) { 381 } else if (i == (msgs->len - 2)) {
350 dev_dbg(&i2c_imx->adapter.dev, 382 dev_dbg(&i2c_imx->adapter.dev,
351 "<%s> set TXAK\n", __func__); 383 "<%s> set TXAK\n", __func__);
@@ -370,14 +402,11 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
370 402
371 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 403 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
372 404
373 /* Check if i2c bus is not busy */ 405 /* Start I2C transfer */
374 result = i2c_imx_bus_busy(i2c_imx); 406 result = i2c_imx_start(i2c_imx);
375 if (result) 407 if (result)
376 goto fail0; 408 goto fail0;
377 409
378 /* Start I2C transfer */
379 i2c_imx_start(i2c_imx);
380
381 /* read/write data */ 410 /* read/write data */
382 for (i = 0; i < num; i++) { 411 for (i = 0; i < num; i++) {
383 if (i) { 412 if (i) {
@@ -386,6 +415,9 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
386 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 415 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
387 temp |= I2CR_RSTA; 416 temp |= I2CR_RSTA;
388 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 417 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
418 result = i2c_imx_bus_busy(i2c_imx, 1);
419 if (result)
420 goto fail0;
389 } 421 }
390 dev_dbg(&i2c_imx->adapter.dev, 422 dev_dbg(&i2c_imx->adapter.dev,
391 "<%s> transfer message: %d\n", __func__, i); 423 "<%s> transfer message: %d\n", __func__, i);
@@ -500,7 +532,6 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
500 dev_err(&pdev->dev, "can't get I2C clock\n"); 532 dev_err(&pdev->dev, "can't get I2C clock\n");
501 goto fail3; 533 goto fail3;
502 } 534 }
503 clk_enable(i2c_imx->clk);
504 535
505 /* Request IRQ */ 536 /* Request IRQ */
506 ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx); 537 ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx);
@@ -549,7 +580,6 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
549fail5: 580fail5:
550 free_irq(i2c_imx->irq, i2c_imx); 581 free_irq(i2c_imx->irq, i2c_imx);
551fail4: 582fail4:
552 clk_disable(i2c_imx->clk);
553 clk_put(i2c_imx->clk); 583 clk_put(i2c_imx->clk);
554fail3: 584fail3:
555 release_mem_region(i2c_imx->res->start, resource_size(res)); 585 release_mem_region(i2c_imx->res->start, resource_size(res));
@@ -586,8 +616,6 @@ static int __exit i2c_imx_remove(struct platform_device *pdev)
586 if (pdata && pdata->exit) 616 if (pdata && pdata->exit)
587 pdata->exit(&pdev->dev); 617 pdata->exit(&pdev->dev);
588 618
589 /* Disable I2C clock */
590 clk_disable(i2c_imx->clk);
591 clk_put(i2c_imx->clk); 619 clk_put(i2c_imx->clk);
592 620
593 release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res)); 621 release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index d325e86e3103..f627001108b8 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -365,9 +365,6 @@ static int mpc_write(struct mpc_i2c *i2c, int target,
365 unsigned timeout = i2c->adap.timeout; 365 unsigned timeout = i2c->adap.timeout;
366 u32 flags = restart ? CCR_RSTA : 0; 366 u32 flags = restart ? CCR_RSTA : 0;
367 367
368 /* Start with MEN */
369 if (!restart)
370 writeccr(i2c, CCR_MEN);
371 /* Start as master */ 368 /* Start as master */
372 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); 369 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
373 /* Write target byte */ 370 /* Write target byte */
@@ -396,9 +393,6 @@ static int mpc_read(struct mpc_i2c *i2c, int target,
396 int i, result; 393 int i, result;
397 u32 flags = restart ? CCR_RSTA : 0; 394 u32 flags = restart ? CCR_RSTA : 0;
398 395
399 /* Start with MEN */
400 if (!restart)
401 writeccr(i2c, CCR_MEN);
402 /* Switch to read - restart */ 396 /* Switch to read - restart */
403 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); 397 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
404 /* Write target address byte - this time with the read flag set */ 398 /* Write target address byte - this time with the read flag set */
@@ -425,9 +419,9 @@ static int mpc_read(struct mpc_i2c *i2c, int target,
425 /* Generate txack on next to last byte */ 419 /* Generate txack on next to last byte */
426 if (i == length - 2) 420 if (i == length - 2)
427 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK); 421 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
428 /* Generate stop on last byte */ 422 /* Do not generate stop on last byte */
429 if (i == length - 1) 423 if (i == length - 1)
430 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK); 424 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX);
431 data[i] = readb(i2c->base + MPC_I2C_DR); 425 data[i] = readb(i2c->base + MPC_I2C_DR);
432 } 426 }
433 427