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-rw-r--r--drivers/infiniband/hw/mthca/mthca_qp.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_qp.c b/drivers/infiniband/hw/mthca/mthca_qp.c
index 84056a8b794e..3543299ecb15 100644
--- a/drivers/infiniband/hw/mthca/mthca_qp.c
+++ b/drivers/infiniband/hw/mthca/mthca_qp.c
@@ -764,8 +764,6 @@ int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
764 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE | 764 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
765 MTHCA_QP_OPTPAR_RRE | 765 MTHCA_QP_OPTPAR_RRE |
766 MTHCA_QP_OPTPAR_RAE); 766 MTHCA_QP_OPTPAR_RAE);
767
768 qp->atomic_rd_en = attr->qp_access_flags;
769 } 767 }
770 768
771 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 769 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
@@ -801,8 +799,6 @@ int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
801 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 799 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
802 800
803 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX); 801 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
804
805 qp->resp_depth = attr->max_dest_rd_atomic;
806 } 802 }
807 803
808 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC); 804 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
@@ -844,8 +840,13 @@ int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
844 err = -EINVAL; 840 err = -EINVAL;
845 } 841 }
846 842
847 if (!err) 843 if (!err) {
848 qp->state = new_state; 844 qp->state = new_state;
845 if (attr_mask & IB_QP_ACCESS_FLAGS)
846 qp->atomic_rd_en = attr->qp_access_flags;
847 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
848 qp->resp_depth = attr->max_dest_rd_atomic;
849 }
849 850
850 mthca_free_mailbox(dev, mailbox); 851 mthca_free_mailbox(dev, mailbox);
851 852