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-rw-r--r--arch/powerpc/kernel/legacy_serial.c4
-rw-r--r--arch/powerpc/kernel/nvram_64.c3
-rw-r--r--arch/powerpc/kernel/process.c6
-rw-r--r--arch/powerpc/kernel/setup_32.c2
-rw-r--r--arch/powerpc/lib/sstep.c2
-rw-r--r--arch/powerpc/platforms/powermac/bootx_init.c2
-rw-r--r--arch/powerpc/platforms/powermac/nvram.c12
-rw-r--r--arch/powerpc/platforms/powermac/udbg_scc.c2
8 files changed, 19 insertions, 14 deletions
diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c
index c7a799a09516..09d9c825fa9c 100644
--- a/arch/powerpc/kernel/legacy_serial.c
+++ b/arch/powerpc/kernel/legacy_serial.c
@@ -37,7 +37,7 @@ static int legacy_serial_console = -1;
37static int __init add_legacy_port(struct device_node *np, int want_index, 37static int __init add_legacy_port(struct device_node *np, int want_index,
38 int iotype, phys_addr_t base, 38 int iotype, phys_addr_t base,
39 phys_addr_t taddr, unsigned long irq, 39 phys_addr_t taddr, unsigned long irq,
40 unsigned int flags) 40 upf_t flags)
41{ 41{
42 u32 *clk, *spd, clock = BASE_BAUD * 16; 42 u32 *clk, *spd, clock = BASE_BAUD * 16;
43 int index; 43 int index;
@@ -113,7 +113,7 @@ static int __init add_legacy_soc_port(struct device_node *np,
113{ 113{
114 phys_addr_t addr; 114 phys_addr_t addr;
115 u32 *addrp; 115 u32 *addrp;
116 unsigned int flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; 116 upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
117 117
118 /* We only support ports that have a clock frequency properly 118 /* We only support ports that have a clock frequency properly
119 * encoded in the device-tree. 119 * encoded in the device-tree.
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index fd7db8d542db..6c3989f6247d 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
@@ -174,8 +174,9 @@ static int dev_nvram_ioctl(struct inode *inode, struct file *file,
174 return 0; 174 return 0;
175 } 175 }
176#endif /* CONFIG_PPC_PMAC */ 176#endif /* CONFIG_PPC_PMAC */
177 default:
178 return -EINVAL;
177 } 179 }
178 return -EINVAL;
179} 180}
180 181
181struct file_operations nvram_fops = { 182struct file_operations nvram_fops = {
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index f698aa77127e..995b14688d3a 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -362,7 +362,11 @@ static void show_instructions(struct pt_regs *regs)
362 if (!(i % 8)) 362 if (!(i % 8))
363 printk("\n"); 363 printk("\n");
364 364
365 if (BAD_PC(pc) || __get_user(instr, (unsigned int *)pc)) { 365 /* We use __get_user here *only* to avoid an OOPS on a
366 * bad address because the pc *should* only be a
367 * kernel address.
368 */
369 if (BAD_PC(pc) || __get_user(instr, (unsigned int __user *)pc)) {
366 printk("XXXXXXXX "); 370 printk("XXXXXXXX ");
367 } else { 371 } else {
368 if (regs->nip == pc) 372 if (regs->nip == pc)
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index dc2770df25b3..676f894c3380 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -111,7 +111,7 @@ unsigned long __init early_init(unsigned long dt_ptr)
111 111
112 /* First zero the BSS -- use memset_io, some platforms don't have 112 /* First zero the BSS -- use memset_io, some platforms don't have
113 * caches on yet */ 113 * caches on yet */
114 memset_io(PTRRELOC(&__bss_start), 0, _end - __bss_start); 114 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, _end - __bss_start);
115 115
116 /* 116 /*
117 * Identify the CPU type and fix up code sections 117 * Identify the CPU type and fix up code sections
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 666c2aa55016..c251d9936612 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -18,7 +18,7 @@ extern char system_call_common[];
18 18
19#ifdef CONFIG_PPC64 19#ifdef CONFIG_PPC64
20/* Bits in SRR1 that are copied from MSR */ 20/* Bits in SRR1 that are copied from MSR */
21#define MSR_MASK 0xffffffff87c0ffff 21#define MSR_MASK 0xffffffff87c0ffffUL
22#else 22#else
23#define MSR_MASK 0x87c0ffff 23#define MSR_MASK 0x87c0ffff
24#endif 24#endif
diff --git a/arch/powerpc/platforms/powermac/bootx_init.c b/arch/powerpc/platforms/powermac/bootx_init.c
index fa8b4d7b5ded..a94571be65ca 100644
--- a/arch/powerpc/platforms/powermac/bootx_init.c
+++ b/arch/powerpc/platforms/powermac/bootx_init.c
@@ -493,7 +493,7 @@ void __init bootx_init(unsigned long r3, unsigned long r4)
493 && (strcmp(model, "iMac,1") == 0 493 && (strcmp(model, "iMac,1") == 0
494 || strcmp(model, "PowerMac1,1") == 0)) { 494 || strcmp(model, "PowerMac1,1") == 0)) {
495 bootx_printf("iMac,1 detected, shutting down USB \n"); 495 bootx_printf("iMac,1 detected, shutting down USB \n");
496 out_le32((unsigned *)0x80880008, 1); /* XXX */ 496 out_le32((unsigned __iomem *)0x80880008, 1); /* XXX */
497 } 497 }
498 } 498 }
499 499
diff --git a/arch/powerpc/platforms/powermac/nvram.c b/arch/powerpc/platforms/powermac/nvram.c
index 5fd28995c74c..3aa3477b86f7 100644
--- a/arch/powerpc/platforms/powermac/nvram.c
+++ b/arch/powerpc/platforms/powermac/nvram.c
@@ -74,7 +74,7 @@ struct core99_header {
74 * Read and write the non-volatile RAM on PowerMacs and CHRP machines. 74 * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
75 */ 75 */
76static int nvram_naddrs; 76static int nvram_naddrs;
77static volatile unsigned char *nvram_data; 77static volatile unsigned char __iomem *nvram_data;
78static int is_core_99; 78static int is_core_99;
79static int core99_bank = 0; 79static int core99_bank = 0;
80static int nvram_partitions[3]; 80static int nvram_partitions[3];
@@ -148,7 +148,7 @@ static ssize_t core99_nvram_size(void)
148} 148}
149 149
150#ifdef CONFIG_PPC32 150#ifdef CONFIG_PPC32
151static volatile unsigned char *nvram_addr; 151static volatile unsigned char __iomem *nvram_addr;
152static int nvram_mult; 152static int nvram_mult;
153 153
154static unsigned char direct_nvram_read_byte(int addr) 154static unsigned char direct_nvram_read_byte(int addr)
@@ -285,7 +285,7 @@ static int sm_erase_bank(int bank)
285 int stat, i; 285 int stat, i;
286 unsigned long timeout; 286 unsigned long timeout;
287 287
288 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE; 288 u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
289 289
290 DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank); 290 DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
291 291
@@ -317,7 +317,7 @@ static int sm_write_bank(int bank, u8* datas)
317 int i, stat = 0; 317 int i, stat = 0;
318 unsigned long timeout; 318 unsigned long timeout;
319 319
320 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE; 320 u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
321 321
322 DBG("nvram: Sharp/Micron Writing bank %d...\n", bank); 322 DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
323 323
@@ -352,7 +352,7 @@ static int amd_erase_bank(int bank)
352 int i, stat = 0; 352 int i, stat = 0;
353 unsigned long timeout; 353 unsigned long timeout;
354 354
355 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE; 355 u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
356 356
357 DBG("nvram: AMD Erasing bank %d...\n", bank); 357 DBG("nvram: AMD Erasing bank %d...\n", bank);
358 358
@@ -399,7 +399,7 @@ static int amd_write_bank(int bank, u8* datas)
399 int i, stat = 0; 399 int i, stat = 0;
400 unsigned long timeout; 400 unsigned long timeout;
401 401
402 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE; 402 u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
403 403
404 DBG("nvram: AMD Writing bank %d...\n", bank); 404 DBG("nvram: AMD Writing bank %d...\n", bank);
405 405
diff --git a/arch/powerpc/platforms/powermac/udbg_scc.c b/arch/powerpc/platforms/powermac/udbg_scc.c
index c4352a8db644..b4fa9f03b461 100644
--- a/arch/powerpc/platforms/powermac/udbg_scc.c
+++ b/arch/powerpc/platforms/powermac/udbg_scc.c
@@ -116,7 +116,7 @@ void udbg_scc_init(int force_scc)
116 /* Setup for 57600 8N1 */ 116 /* Setup for 57600 8N1 */
117 if (ch == ch_a) 117 if (ch == ch_a)
118 addr += 0x20; 118 addr += 0x20;
119 sccc = (volatile u8 * __iomem) ioremap(addr & PAGE_MASK, PAGE_SIZE) ; 119 sccc = ioremap(addr & PAGE_MASK, PAGE_SIZE) ;
120 sccc += addr & ~PAGE_MASK; 120 sccc += addr & ~PAGE_MASK;
121 sccd = sccc + 0x10; 121 sccd = sccc + 0x10;
122 122