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-rw-r--r--arch/arm/mach-pxa/Kconfig9
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/pcm990-baseboard.c330
-rw-r--r--include/asm-arm/arch-pxa/pcm990_baseboard.h275
4 files changed, 615 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 958303c100b0..e5b7063ed818 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -130,6 +130,15 @@ config MACH_PCM027
130 130
131endchoice 131endchoice
132 132
133choice
134 prompt "Used baseboard"
135 depends on MACH_PCM027
136
137config MACH_PCM990_BASEBOARD
138 bool "PHYTEC PCM-990 development board"
139
140endchoice
141
133if PXA_SHARPSL 142if PXA_SHARPSL
134 143
135choice 144choice
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 61d301805c80..1af56805b954 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o sp
21obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o 21obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o
22obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o 22obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o
23obj-$(CONFIG_MACH_PCM027) += pcm027.o 23obj-$(CONFIG_MACH_PCM027) += pcm027.o
24obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o
24obj-$(CONFIG_MACH_TOSA) += tosa.o 25obj-$(CONFIG_MACH_TOSA) += tosa.o
25obj-$(CONFIG_MACH_EM_X270) += em-x270.o 26obj-$(CONFIG_MACH_EM_X270) += em-x270.o
26obj-$(CONFIG_MACH_MAGICIAN) += magician.o 27obj-$(CONFIG_MACH_MAGICIAN) += magician.o
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
new file mode 100644
index 000000000000..3dda16a20049
--- /dev/null
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -0,0 +1,330 @@
1/*
2 * arch/arm/mach-pxa/pcm990-baseboard.c
3 * Support for the Phytec phyCORE-PXA270 Development Platform (PCM-990).
4 *
5 * Refer
6 * http://www.phytec.com/products/rdk/ARM-XScale/phyCORE-XScale-PXA270.html
7 * for additional hardware info
8 *
9 * Author: Juergen Kilb
10 * Created: April 05, 2005
11 * Copyright: Phytec Messtechnik GmbH
12 * e-Mail: armlinux@phytec.de
13 *
14 * based on Intel Mainstone Board
15 *
16 * Copyright 2007 Juergen Beisert @ Pengutronix (j.beisert@pengutronix.de)
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/ide.h>
26#include <asm/mach/map.h>
27#include <asm/arch/pxa-regs.h>
28#include <asm/arch/mmc.h>
29#include <asm/arch/ohci.h>
30#include <asm/arch/pcm990_baseboard.h>
31
32/*
33 * The PCM-990 development baseboard uses PCM-027's hardeware in the
34 * following way:
35 *
36 * - LCD support is in use
37 * - GPIO16 is output for back light on/off with PWM
38 * - GPIO58 ... GPIO73 are outputs for display data
39 * - GPIO74 is output output for LCDFCLK
40 * - GPIO75 is output for LCDLCLK
41 * - GPIO76 is output for LCDPCLK
42 * - GPIO77 is output for LCDBIAS
43 * - MMC support is in use
44 * - GPIO32 is output for MMCCLK
45 * - GPIO92 is MMDAT0
46 * - GPIO109 is MMDAT1
47 * - GPIO110 is MMCS0
48 * - GPIO111 is MMCS1
49 * - GPIO112 is MMCMD
50 * - IDE/CF card is in use
51 * - GPIO48 is output /POE
52 * - GPIO49 is output /PWE
53 * - GPIO50 is output /PIOR
54 * - GPIO51 is output /PIOW
55 * - GPIO54 is output /PCE2
56 * - GPIO55 is output /PREG
57 * - GPIO56 is input /PWAIT
58 * - GPIO57 is output /PIOS16
59 * - GPIO79 is output PSKTSEL
60 * - GPIO85 is output /PCE1
61 * - FFUART is in use
62 * - GPIO34 is input FFRXD
63 * - GPIO35 is input FFCTS
64 * - GPIO36 is input FFDCD
65 * - GPIO37 is input FFDSR
66 * - GPIO38 is input FFRI
67 * - GPIO39 is output FFTXD
68 * - GPIO40 is output FFDTR
69 * - GPIO41 is output FFRTS
70 * - BTUART is in use
71 * - GPIO42 is input BTRXD
72 * - GPIO43 is output BTTXD
73 * - GPIO44 is input BTCTS
74 * - GPIO45 is output BTRTS
75 * - IRUART is in use
76 * - GPIO46 is input STDRXD
77 * - GPIO47 is output STDTXD
78 * - AC97 is in use*)
79 * - GPIO28 is input AC97CLK
80 * - GPIO29 is input AC97DatIn
81 * - GPIO30 is output AC97DatO
82 * - GPIO31 is output AC97SYNC
83 * - GPIO113 is output AC97_RESET
84 * - SSP is in use
85 * - GPIO23 is output SSPSCLK
86 * - GPIO24 is output chip select to Max7301
87 * - GPIO25 is output SSPTXD
88 * - GPIO26 is input SSPRXD
89 * - GPIO27 is input for Max7301 IRQ
90 * - GPIO53 is input SSPSYSCLK
91 * - SSP3 is in use
92 * - GPIO81 is output SSPTXD3
93 * - GPIO82 is input SSPRXD3
94 * - GPIO83 is output SSPSFRM
95 * - GPIO84 is output SSPCLK3
96 *
97 * Otherwise claimed GPIOs:
98 * GPIO1 -> IRQ from user switch
99 * GPIO9 -> IRQ from power management
100 * GPIO10 -> IRQ from WML9712 AC97 controller
101 * GPIO11 -> IRQ from IDE controller
102 * GPIO12 -> IRQ from CF controller
103 * GPIO13 -> IRQ from CF controller
104 * GPIO14 -> GPIO free
105 * GPIO15 -> /CS1 selects baseboard's Control CPLD (U7, 16 bit wide data path)
106 * GPIO19 -> GPIO free
107 * GPIO20 -> /SDCS2
108 * GPIO21 -> /CS3 PC card socket select
109 * GPIO33 -> /CS5 network controller select
110 * GPIO78 -> /CS2 (16 bit wide data path)
111 * GPIO80 -> /CS4 (16 bit wide data path)
112 * GPIO86 -> GPIO free
113 * GPIO87 -> GPIO free
114 * GPIO90 -> LED0 on CPU module
115 * GPIO91 -> LED1 on CPI module
116 * GPIO117 -> SCL
117 * GPIO118 -> SDA
118 */
119
120static unsigned long pcm990_irq_enabled;
121
122static void pcm990_mask_ack_irq(unsigned int irq)
123{
124 int pcm990_irq = (irq - PCM027_IRQ(0));
125 PCM990_INTMSKENA = (pcm990_irq_enabled &= ~(1 << pcm990_irq));
126}
127
128static void pcm990_unmask_irq(unsigned int irq)
129{
130 int pcm990_irq = (irq - PCM027_IRQ(0));
131 /* the irq can be acknowledged only if deasserted, so it's done here */
132 PCM990_INTSETCLR |= 1 << pcm990_irq;
133 PCM990_INTMSKENA = (pcm990_irq_enabled |= (1 << pcm990_irq));
134}
135
136static struct irq_chip pcm990_irq_chip = {
137 .mask_ack = pcm990_mask_ack_irq,
138 .unmask = pcm990_unmask_irq,
139};
140
141static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc)
142{
143 unsigned long pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
144
145 do {
146 GEDR(PCM990_CTRL_INT_IRQ_GPIO) =
147 GPIO_bit(PCM990_CTRL_INT_IRQ_GPIO);
148 if (likely(pending)) {
149 irq = PCM027_IRQ(0) + __ffs(pending);
150 desc = irq_desc + irq;
151 desc_handle_irq(irq, desc);
152 }
153 pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
154 } while (pending);
155}
156
157static void __init pcm990_init_irq(void)
158{
159 int irq;
160
161 /* setup extra PCM990 irqs */
162 for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
163 set_irq_chip(irq, &pcm990_irq_chip);
164 set_irq_handler(irq, handle_level_irq);
165 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
166 }
167
168 PCM990_INTMSKENA = 0x00; /* disable all Interrupts */
169 PCM990_INTSETCLR = 0xFF;
170
171 set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
172 set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
173}
174
175static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
176 void *data)
177{
178 int err;
179
180 /*
181 * enable GPIO for PXA27x MMC controller
182 */
183 pxa_gpio_mode(GPIO32_MMCCLK_MD);
184 pxa_gpio_mode(GPIO112_MMCCMD_MD);
185 pxa_gpio_mode(GPIO92_MMCDAT0_MD);
186 pxa_gpio_mode(GPIO109_MMCDAT1_MD);
187 pxa_gpio_mode(GPIO110_MMCDAT2_MD);
188 pxa_gpio_mode(GPIO111_MMCDAT3_MD);
189
190 err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, IRQF_DISABLED,
191 "MMC card detect", data);
192 if (err)
193 printk(KERN_ERR "pcm990_mci_init: MMC/SD: can't request MMC "
194 "card detect IRQ\n");
195
196 return err;
197}
198
199static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
200{
201 struct pxamci_platform_data *p_d = dev->platform_data;
202
203 if ((1 << vdd) & p_d->ocr_mask)
204 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) =
205 PCM990_CTRL_MMC2PWR;
206 else
207 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) =
208 ~PCM990_CTRL_MMC2PWR;
209}
210
211static void pcm990_mci_exit(struct device *dev, void *data)
212{
213 free_irq(PCM027_MMCDET_IRQ, data);
214}
215
216#define MSECS_PER_JIFFY (1000/HZ)
217
218static struct pxamci_platform_data pcm990_mci_platform_data = {
219 .detect_delay = 250 / MSECS_PER_JIFFY,
220 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
221 .init = pcm990_mci_init,
222 .setpower = pcm990_mci_setpower,
223 .exit = pcm990_mci_exit,
224};
225
226/*
227 * init OHCI hardware to work with
228 *
229 * Note: Only USB port 1 (host only) is connected
230 *
231 * GPIO88 (USBHPWR#1): overcurrent in, overcurrent when low
232 * GPIO89 (USBHPEN#1): power-on out, on when low
233 */
234static int pcm990_ohci_init(struct device *dev)
235{
236 pxa_gpio_mode(PCM990_USB_OVERCURRENT);
237 pxa_gpio_mode(PCM990_USB_PWR_EN);
238 /*
239 * disable USB port 2 and 3
240 * power sense is active low
241 */
242 UHCHR = ((UHCHR) | UHCHR_PCPL | UHCHR_PSPL | UHCHR_SSEP2 |
243 UHCHR_SSEP3) & ~(UHCHR_SSEP1 | UHCHR_SSE);
244 /*
245 * wait 10ms after Power on
246 * overcurrent per port
247 * power switch per port
248 */
249 UHCRHDA = (5<<24) | (1<<11) | (1<<8); /* FIXME: Required? */
250
251 return 0;
252}
253
254static struct pxaohci_platform_data pcm990_ohci_platform_data = {
255 .port_mode = PMM_PERPORT_MODE,
256 .init = pcm990_ohci_init,
257 .exit = NULL,
258};
259
260/*
261 * AC97 support
262 * Note: The connected AC97 mixer also reports interrupts at PCM990_AC97_IRQ
263 */
264static struct resource pxa27x_ac97_resources[] = {
265 [0] = {
266 .start = 0x40500000,
267 .end = 0x40500000 + 0xfff,
268 .flags = IORESOURCE_MEM,
269 },
270 [1] = {
271 .start = IRQ_AC97,
272 .end = IRQ_AC97,
273 .flags = IORESOURCE_IRQ,
274 },
275};
276
277static u64 pxa_ac97_dmamask = 0xffffffffUL;
278
279static struct platform_device pxa27x_device_ac97 = {
280 .name = "pxa2xx-ac97",
281 .id = -1,
282 .dev = {
283 .dma_mask = &pxa_ac97_dmamask,
284 .coherent_dma_mask = 0xffffffff,
285 },
286 .num_resources = ARRAY_SIZE(pxa27x_ac97_resources),
287 .resource = pxa27x_ac97_resources,
288};
289
290/*
291 * enable generic access to the base board control CPLDs U6 and U7
292 */
293static struct map_desc pcm990_io_desc[] __initdata = {
294 {
295 .virtual = PCM990_CTRL_BASE,
296 .pfn = __phys_to_pfn(PCM990_CTRL_PHYS),
297 .length = PCM990_CTRL_SIZE,
298 .type = MT_DEVICE /* CPLD */
299 }, {
300 .virtual = PCM990_CF_PLD_BASE,
301 .pfn = __phys_to_pfn(PCM990_CF_PLD_PHYS),
302 .length = PCM990_CF_PLD_SIZE,
303 .type = MT_DEVICE /* CPLD */
304 }
305};
306
307/*
308 * system init for baseboard usage. Will be called by pcm027 init.
309 *
310 * Add platform devices present on this baseboard and init
311 * them from CPU side as far as required to use them later on
312 */
313void __init pcm990_baseboard_init(void)
314{
315 /* register CPLD access */
316 iotable_init(pcm990_io_desc, ARRAY_SIZE(pcm990_io_desc));
317
318 /* register CPLD's IRQ controller */
319 pcm990_init_irq();
320
321 platform_device_register(&pxa27x_device_ac97);
322
323 /* MMC */
324 pxa_set_mci_info(&pcm990_mci_platform_data);
325
326 /* USB host */
327 pxa_set_ohci_info(&pcm990_ohci_platform_data);
328
329 printk(KERN_INFO"PCM-990 Evaluation baseboard initialized\n");
330}
diff --git a/include/asm-arm/arch-pxa/pcm990_baseboard.h b/include/asm-arm/arch-pxa/pcm990_baseboard.h
new file mode 100644
index 000000000000..b699d0d7bdb2
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pcm990_baseboard.h
@@ -0,0 +1,275 @@
1/*
2 * include/asm-arm/arch-pxa/pcm990_baseboard.h
3 *
4 * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
5 * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <asm/arch/pcm027.h>
23
24/*
25 * definitions relevant only when the PCM-990
26 * development base board is in use
27 */
28
29/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
30#define PCM990_CTRL_INT_IRQ_GPIO 9
31#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
32#define PCM990_CTRL_INT_IRQ_EDGE IRQT_RISING
33#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
34#define PCM990_CTRL_BASE 0xea000000
35#define PCM990_CTRL_SIZE (1*1024*1024)
36
37#define PCM990_CTRL_PWR_IRQ_GPIO 14
38#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
39#define PCM990_CTRL_PWR_IRQ_EDGE IRQT_RISING
40
41/* visible CPLD (U7) registers */
42#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
43#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
44#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
45#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
46
47#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
48#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
49#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
50#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
51
52#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
53#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
54#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */
55#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */
56
57#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */
58#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */
59#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */
60#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */
61#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */
62
63#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */
64#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */
65
66#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */
67#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */
68#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */
69#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */
70#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */
71
72#define PCM990_CTRL_REG6 0x000C /* Interrupt Clear REGISTER */
73#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */
74#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */
75#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */
76#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */
77
78#define PCM990_CTRL_REG7 0x000E /* Interrupt Enable REGISTER */
79#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */
80#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */
81#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */
82#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */
83
84#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */
85#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */
86#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */
87#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */
88#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */
89
90#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */
91#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */
92#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */
93#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */
94
95#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */
96#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */
97#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */
98
99#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */
100#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */
101#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */
102#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */
103#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */
104
105#define PCM990_CTRL_P2V(x) ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
106#define PCM990_CTRL_V2P(x) ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
107
108#ifndef __ASSEMBLY__
109# define __PCM990_CTRL_REG(x) \
110 (*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
111#else
112# define __PCM990_CTRL_REG(x) PCM990_CTRL_P2V(x)
113#endif
114
115#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
116#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
117#define PCM990_CTRL0 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
118#define PCM990_CTRL1 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
119#define PCM990_CTRL2 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
120#define PCM990_CTRL3 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
121#define PCM990_CTRL4 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
122#define PCM990_CTRL5 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
123#define PCM990_CTRL6 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
124#define PCM990_CTRL7 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
125#define PCM990_CTRL8 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
126#define PCM990_CTRL9 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
127#define PCM990_CTRL10 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
128#define PCM990_CTRL11 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
129
130
131/*
132 * IDE
133 */
134#define PCM990_IDE_IRQ_GPIO 13
135#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
136#define PCM990_IDE_IRQ_EDGE IRQT_RISING
137#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
138#define PCM990_IDE_PLD_BASE 0xee000000
139#define PCM990_IDE_PLD_SIZE (1*1024*1024)
140
141/* visible CPLD (U6) registers */
142#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */
143#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */
144#define PCM990_IDE_STBY 0x0008 /* R System StandBy */
145
146#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */
147#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */
148#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */
149#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */
150
151#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */
152#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */
153#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */
154#define PCM990_IDE_RDY 0x0008 /* RDY */
155
156#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */
157#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */
158#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */
159#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */
160
161#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */
162#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */
163#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */
164#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */
165
166#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
167#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
168
169#ifndef __ASSEMBLY__
170# define __PCM990_IDE_PLD_REG(x) \
171 (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
172#else
173# define __PCM990_IDE_PLD_REG(x) PCM990_IDE_PLD_P2V(x)
174#endif
175
176#define PCM990_IDE0 \
177 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
178#define PCM990_IDE1 \
179 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
180#define PCM990_IDE2 \
181 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
182#define PCM990_IDE3 \
183 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
184#define PCM990_IDE4 \
185 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
186
187/*
188 * Compact Flash
189 */
190#define PCM990_CF_IRQ_GPIO 11
191#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO)
192#define PCM990_CF_IRQ_EDGE IRQT_RISING
193
194#define PCM990_CF_CD_GPIO 12
195#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO)
196#define PCM990_CF_CD_EDGE IRQT_RISING
197
198#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
199#define PCM990_CF_PLD_BASE 0xef000000
200#define PCM990_CF_PLD_SIZE (1*1024*1024)
201#define PCM990_CF_PLD_P2V(x) ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
202#define PCM990_CF_PLD_V2P(x) ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
203
204/* visible CPLD (U6) registers */
205#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */
206#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */
207#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */
208#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */
209#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */
210
211#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */
212#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */
213#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */
214
215#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */
216#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */
217#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */
218#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */
219
220#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */
221#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */
222#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */
223#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */
224#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */
225
226#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */
227#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */
228#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
229#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */
230#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */
231
232#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */
233#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */
234#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */
235#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */
236#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */
237
238#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */
239#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */
240#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */
241
242#ifndef __ASSEMBLY__
243# define __PCM990_CF_PLD_REG(x) \
244 (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
245#else
246# define __PCM990_CF_PLD_REG(x) PCM990_CF_PLD_P2V(x)
247#endif
248
249#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
250#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
251#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
252#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
253#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
254#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
255#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
256
257/*
258 * Wolfson AC97 Touch
259 */
260#define PCM990_AC97_IRQ_GPIO 10
261#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
262#define PCM990_AC97_IRQ_EDGE IRQT_RISING
263
264/*
265 * MMC phyCORE
266 */
267#define PCM990_MMC0_IRQ_GPIO 9
268#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
269#define PCM990_MMC0_IRQ_EDGE IRQT_FALLING
270
271/*
272 * USB phyCore
273 */
274#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
275#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 05:18:44 -0500