aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-at91/Kconfig3
-rw-r--r--arch/arm/mach-at91/Makefile1
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c341
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c634
-rw-r--r--arch/arm/mach-at91/generic.h2
-rw-r--r--arch/arm/mm/Kconfig4
-rw-r--r--drivers/usb/gadget/Kconfig2
-rw-r--r--include/asm-arm/arch-at91/at91sam9rl.h110
-rw-r--r--include/asm-arm/arch-at91/at91sam9rl_matrix.h96
-rw-r--r--include/asm-arm/arch-at91/cpu.h9
-rw-r--r--include/asm-arm/arch-at91/hardware.h2
-rw-r--r--include/asm-arm/arch-at91/timex.h5
-rw-r--r--include/asm-avr32/arch-at32ap/cpu.h1
13 files changed, 1207 insertions, 3 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 018d637f87fc..1ba120c5cd0c 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -17,6 +17,9 @@ config ARCH_AT91SAM9261
17config ARCH_AT91SAM9263 17config ARCH_AT91SAM9263
18 bool "AT91SAM9263" 18 bool "AT91SAM9263"
19 19
20config ARCH_AT91SAM9RL
21 bool "AT91SAM9RL"
22
20endchoice 23endchoice
21 24
22# ---------------------------------------------------------- 25# ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index a412ae18a421..66d79e6c68a3 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devic
14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o 14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o 15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o 16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
17obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o
17 18
18# AT91RM9200 board-specific support 19# AT91RM9200 board-specific support
19obj-$(CONFIG_MACH_ONEARM) += board-1arm.o 20obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
new file mode 100644
index 000000000000..4813a35f6cf5
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -0,0 +1,341 @@
1/*
2 * arch/arm/mach-at91/at91sam9rl.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 */
11
12#include <linux/module.h>
13
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16#include <asm/arch/cpu.h>
17#include <asm/arch/at91sam9rl.h>
18#include <asm/arch/at91_pmc.h>
19#include <asm/arch/at91_rstc.h>
20
21#include "generic.h"
22#include "clock.h"
23
24static struct map_desc at91sam9rl_io_desc[] __initdata = {
25 {
26 .virtual = AT91_VA_BASE_SYS,
27 .pfn = __phys_to_pfn(AT91_BASE_SYS),
28 .length = SZ_16K,
29 .type = MT_DEVICE,
30 },
31};
32
33static struct map_desc at91sam9rl_sram_desc[] __initdata = {
34 {
35 .pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
36 .type = MT_DEVICE,
37 }
38};
39
40/* --------------------------------------------------------------------
41 * Clocks
42 * -------------------------------------------------------------------- */
43
44/*
45 * The peripheral clocks.
46 */
47static struct clk pioA_clk = {
48 .name = "pioA_clk",
49 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk pioB_clk = {
53 .name = "pioB_clk",
54 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk pioC_clk = {
58 .name = "pioC_clk",
59 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62static struct clk pioD_clk = {
63 .name = "pioD_clk",
64 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
65 .type = CLK_TYPE_PERIPHERAL,
66};
67static struct clk usart0_clk = {
68 .name = "usart0_clk",
69 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
70 .type = CLK_TYPE_PERIPHERAL,
71};
72static struct clk usart1_clk = {
73 .name = "usart1_clk",
74 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
75 .type = CLK_TYPE_PERIPHERAL,
76};
77static struct clk usart2_clk = {
78 .name = "usart2_clk",
79 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
80 .type = CLK_TYPE_PERIPHERAL,
81};
82static struct clk usart3_clk = {
83 .name = "usart3_clk",
84 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk mmc_clk = {
88 .name = "mci_clk",
89 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk twi0_clk = {
93 .name = "twi0_clk",
94 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
95 .type = CLK_TYPE_PERIPHERAL,
96};
97static struct clk twi1_clk = {
98 .name = "twi1_clk",
99 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
100 .type = CLK_TYPE_PERIPHERAL,
101};
102static struct clk spi_clk = {
103 .name = "spi_clk",
104 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk ssc0_clk = {
108 .name = "ssc0_clk",
109 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
110 .type = CLK_TYPE_PERIPHERAL,
111};
112static struct clk ssc1_clk = {
113 .name = "ssc1_clk",
114 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk tc0_clk = {
118 .name = "tc0_clk",
119 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk tc1_clk = {
123 .name = "tc1_clk",
124 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk tc2_clk = {
128 .name = "tc2_clk",
129 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk pwmc_clk = {
133 .name = "pwmc_clk",
134 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137static struct clk tsc_clk = {
138 .name = "tsc_clk",
139 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
140 .type = CLK_TYPE_PERIPHERAL,
141};
142static struct clk dma_clk = {
143 .name = "dma_clk",
144 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
145 .type = CLK_TYPE_PERIPHERAL,
146};
147static struct clk udphs_clk = {
148 .name = "udphs_clk",
149 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
150 .type = CLK_TYPE_PERIPHERAL,
151};
152static struct clk lcdc_clk = {
153 .name = "lcdc_clk",
154 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
155 .type = CLK_TYPE_PERIPHERAL,
156};
157static struct clk ac97_clk = {
158 .name = "ac97_clk",
159 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
160 .type = CLK_TYPE_PERIPHERAL,
161};
162
163static struct clk *periph_clocks[] __initdata = {
164 &pioA_clk,
165 &pioB_clk,
166 &pioC_clk,
167 &pioD_clk,
168 &usart0_clk,
169 &usart1_clk,
170 &usart2_clk,
171 &usart3_clk,
172 &mmc_clk,
173 &twi0_clk,
174 &twi1_clk,
175 &spi_clk,
176 &ssc0_clk,
177 &ssc1_clk,
178 &tc0_clk,
179 &tc1_clk,
180 &tc2_clk,
181 &pwmc_clk,
182 &tsc_clk,
183 &dma_clk,
184 &udphs_clk,
185 &lcdc_clk,
186 &ac97_clk,
187 // irq0
188};
189
190/*
191 * The two programmable clocks.
192 * You must configure pin multiplexing to bring these signals out.
193 */
194static struct clk pck0 = {
195 .name = "pck0",
196 .pmc_mask = AT91_PMC_PCK0,
197 .type = CLK_TYPE_PROGRAMMABLE,
198 .id = 0,
199};
200static struct clk pck1 = {
201 .name = "pck1",
202 .pmc_mask = AT91_PMC_PCK1,
203 .type = CLK_TYPE_PROGRAMMABLE,
204 .id = 1,
205};
206
207static void __init at91sam9rl_register_clocks(void)
208{
209 int i;
210
211 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
212 clk_register(periph_clocks[i]);
213
214 clk_register(&pck0);
215 clk_register(&pck1);
216}
217
218/* --------------------------------------------------------------------
219 * GPIO
220 * -------------------------------------------------------------------- */
221
222static struct at91_gpio_bank at91sam9rl_gpio[] = {
223 {
224 .id = AT91SAM9RL_ID_PIOA,
225 .offset = AT91_PIOA,
226 .clock = &pioA_clk,
227 }, {
228 .id = AT91SAM9RL_ID_PIOB,
229 .offset = AT91_PIOB,
230 .clock = &pioB_clk,
231 }, {
232 .id = AT91SAM9RL_ID_PIOC,
233 .offset = AT91_PIOC,
234 .clock = &pioC_clk,
235 }, {
236 .id = AT91SAM9RL_ID_PIOD,
237 .offset = AT91_PIOD,
238 .clock = &pioD_clk,
239 }
240};
241
242static void at91sam9rl_reset(void)
243{
244 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
245}
246
247
248/* --------------------------------------------------------------------
249 * AT91SAM9RL processor initialization
250 * -------------------------------------------------------------------- */
251
252void __init at91sam9rl_initialize(unsigned long main_clock)
253{
254 unsigned long cidr, sram_size;
255
256 /* Map peripherals */
257 iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc));
258
259 cidr = at91_sys_read(AT91_DBGU_CIDR);
260
261 switch (cidr & AT91_CIDR_SRAMSIZ) {
262 case AT91_CIDR_SRAMSIZ_32K:
263 sram_size = 2 * SZ_16K;
264 break;
265 case AT91_CIDR_SRAMSIZ_16K:
266 default:
267 sram_size = SZ_16K;
268 }
269
270 at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
271 at91sam9rl_sram_desc->length = sram_size;
272
273 /* Map SRAM */
274 iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
275
276 at91_arch_reset = at91sam9rl_reset;
277 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
278
279 /* Init clock subsystem */
280 at91_clock_init(main_clock);
281
282 /* Register the processor-specific clocks */
283 at91sam9rl_register_clocks();
284
285 /* Register GPIO subsystem */
286 at91_gpio_init(at91sam9rl_gpio, 4);
287}
288
289/* --------------------------------------------------------------------
290 * Interrupt initialization
291 * -------------------------------------------------------------------- */
292
293/*
294 * The default interrupt priority levels (0 = lowest, 7 = highest).
295 */
296static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
297 7, /* Advanced Interrupt Controller */
298 7, /* System Peripherals */
299 1, /* Parallel IO Controller A */
300 1, /* Parallel IO Controller B */
301 1, /* Parallel IO Controller C */
302 1, /* Parallel IO Controller D */
303 5, /* USART 0 */
304 5, /* USART 1 */
305 5, /* USART 2 */
306 5, /* USART 3 */
307 0, /* Multimedia Card Interface */
308 6, /* Two-Wire Interface 0 */
309 6, /* Two-Wire Interface 1 */
310 5, /* Serial Peripheral Interface */
311 4, /* Serial Synchronous Controller 0 */
312 4, /* Serial Synchronous Controller 1 */
313 0, /* Timer Counter 0 */
314 0, /* Timer Counter 1 */
315 0, /* Timer Counter 2 */
316 0,
317 0, /* Touch Screen Controller */
318 0, /* DMA Controller */
319 2, /* USB Device High speed port */
320 2, /* LCD Controller */
321 6, /* AC97 Controller */
322 0,
323 0,
324 0,
325 0,
326 0,
327 0,
328 0, /* Advanced Interrupt Controller */
329};
330
331void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS])
332{
333 if (!priority)
334 priority = at91sam9rl_default_irq_priority;
335
336 /* Initialize the AIC interrupt controller */
337 at91_aic_init(priority);
338
339 /* Enable GPIO interrupts */
340 at91_gpio_irq_setup();
341}
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
new file mode 100644
index 000000000000..e775aa65bb63
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -0,0 +1,634 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9#include <asm/mach/arch.h>
10#include <asm/mach/map.h>
11
12#include <linux/platform_device.h>
13#include <linux/fb.h>
14
15#include <video/atmel_lcdc.h>
16
17#include <asm/arch/board.h>
18#include <asm/arch/gpio.h>
19#include <asm/arch/at91sam9rl.h>
20#include <asm/arch/at91sam9rl_matrix.h>
21#include <asm/arch/at91sam926x_mc.h>
22
23#include "generic.h"
24
25#define SZ_512 0x00000200
26#define SZ_256 0x00000100
27#define SZ_16 0x00000010
28
29
30/* --------------------------------------------------------------------
31 * MMC / SD
32 * -------------------------------------------------------------------- */
33
34#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
35static u64 mmc_dmamask = 0xffffffffUL;
36static struct at91_mmc_data mmc_data;
37
38static struct resource mmc_resources[] = {
39 [0] = {
40 .start = AT91SAM9RL_BASE_MCI,
41 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
42 .flags = IORESOURCE_MEM,
43 },
44 [1] = {
45 .start = AT91SAM9RL_ID_MCI,
46 .end = AT91SAM9RL_ID_MCI,
47 .flags = IORESOURCE_IRQ,
48 },
49};
50
51static struct platform_device at91sam9rl_mmc_device = {
52 .name = "at91_mci",
53 .id = -1,
54 .dev = {
55 .dma_mask = &mmc_dmamask,
56 .coherent_dma_mask = 0xffffffff,
57 .platform_data = &mmc_data,
58 },
59 .resource = mmc_resources,
60 .num_resources = ARRAY_SIZE(mmc_resources),
61};
62
63void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
64{
65 if (!data)
66 return;
67
68 /* input/irq */
69 if (data->det_pin) {
70 at91_set_gpio_input(data->det_pin, 1);
71 at91_set_deglitch(data->det_pin, 1);
72 }
73 if (data->wp_pin)
74 at91_set_gpio_input(data->wp_pin, 1);
75 if (data->vcc_pin)
76 at91_set_gpio_output(data->vcc_pin, 0);
77
78 /* CLK */
79 at91_set_A_periph(AT91_PIN_PA2, 0);
80
81 /* CMD */
82 at91_set_A_periph(AT91_PIN_PA1, 1);
83
84 /* DAT0, maybe DAT1..DAT3 */
85 at91_set_A_periph(AT91_PIN_PA0, 1);
86 if (data->wire4) {
87 at91_set_A_periph(AT91_PIN_PA3, 1);
88 at91_set_A_periph(AT91_PIN_PA4, 1);
89 at91_set_A_periph(AT91_PIN_PA5, 1);
90 }
91
92 mmc_data = *data;
93 platform_device_register(&at91sam9rl_mmc_device);
94}
95#else
96void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
97#endif
98
99
100/* --------------------------------------------------------------------
101 * NAND / SmartMedia
102 * -------------------------------------------------------------------- */
103
104#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
105static struct at91_nand_data nand_data;
106
107#define NAND_BASE AT91_CHIPSELECT_3
108
109static struct resource nand_resources[] = {
110 {
111 .start = NAND_BASE,
112 .end = NAND_BASE + SZ_256M - 1,
113 .flags = IORESOURCE_MEM,
114 }
115};
116
117static struct platform_device at91_nand_device = {
118 .name = "at91_nand",
119 .id = -1,
120 .dev = {
121 .platform_data = &nand_data,
122 },
123 .resource = nand_resources,
124 .num_resources = ARRAY_SIZE(nand_resources),
125};
126
127void __init at91_add_device_nand(struct at91_nand_data *data)
128{
129 unsigned long csa;
130
131 if (!data)
132 return;
133
134 csa = at91_sys_read(AT91_MATRIX_EBICSA);
135 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
136
137 /* set the bus interface characteristics */
138 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
139 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
140
141 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
142 | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
143
144 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
145
146 at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
147
148 /* enable pin */
149 if (data->enable_pin)
150 at91_set_gpio_output(data->enable_pin, 1);
151
152 /* ready/busy pin */
153 if (data->rdy_pin)
154 at91_set_gpio_input(data->rdy_pin, 1);
155
156 /* card detect pin */
157 if (data->det_pin)
158 at91_set_gpio_input(data->det_pin, 1);
159
160 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
161 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
162
163 nand_data = *data;
164 platform_device_register(&at91_nand_device);
165}
166
167#else
168void __init at91_add_device_nand(struct at91_nand_data *data) {}
169#endif
170
171
172/* --------------------------------------------------------------------
173 * TWI (i2c)
174 * -------------------------------------------------------------------- */
175
176#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
177
178static struct resource twi_resources[] = {
179 [0] = {
180 .start = AT91SAM9RL_BASE_TWI0,
181 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
182 .flags = IORESOURCE_MEM,
183 },
184 [1] = {
185 .start = AT91SAM9RL_ID_TWI0,
186 .end = AT91SAM9RL_ID_TWI0,
187 .flags = IORESOURCE_IRQ,
188 },
189};
190
191static struct platform_device at91sam9rl_twi_device = {
192 .name = "at91_i2c",
193 .id = -1,
194 .resource = twi_resources,
195 .num_resources = ARRAY_SIZE(twi_resources),
196};
197
198void __init at91_add_device_i2c(void)
199{
200 /* pins used for TWI interface */
201 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
202 at91_set_multi_drive(AT91_PIN_PA23, 1);
203
204 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
205 at91_set_multi_drive(AT91_PIN_PA24, 1);
206
207 platform_device_register(&at91sam9rl_twi_device);
208}
209#else
210void __init at91_add_device_i2c(void) {}
211#endif
212
213
214/* --------------------------------------------------------------------
215 * SPI
216 * -------------------------------------------------------------------- */
217
218#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
219static u64 spi_dmamask = 0xffffffffUL;
220
221static struct resource spi_resources[] = {
222 [0] = {
223 .start = AT91SAM9RL_BASE_SPI,
224 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
225 .flags = IORESOURCE_MEM,
226 },
227 [1] = {
228 .start = AT91SAM9RL_ID_SPI,
229 .end = AT91SAM9RL_ID_SPI,
230 .flags = IORESOURCE_IRQ,
231 },
232};
233
234static struct platform_device at91sam9rl_spi_device = {
235 .name = "atmel_spi",
236 .id = 0,
237 .dev = {
238 .dma_mask = &spi_dmamask,
239 .coherent_dma_mask = 0xffffffff,
240 },
241 .resource = spi_resources,
242 .num_resources = ARRAY_SIZE(spi_resources),
243};
244
245static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
246
247
248void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
249{
250 int i;
251 unsigned long cs_pin;
252
253 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
254 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
255 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
256
257 /* Enable SPI chip-selects */
258 for (i = 0; i < nr_devices; i++) {
259 if (devices[i].controller_data)
260 cs_pin = (unsigned long) devices[i].controller_data;
261 else
262 cs_pin = spi_standard_cs[devices[i].chip_select];
263
264 /* enable chip-select pin */
265 at91_set_gpio_output(cs_pin, 1);
266
267 /* pass chip-select pin to driver */
268 devices[i].controller_data = (void *) cs_pin;
269 }
270
271 spi_register_board_info(devices, nr_devices);
272 platform_device_register(&at91sam9rl_spi_device);
273}
274#else
275void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
276#endif
277
278
279/* --------------------------------------------------------------------
280 * LCD Controller
281 * -------------------------------------------------------------------- */
282
283#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
284static u64 lcdc_dmamask = 0xffffffffUL;
285static struct atmel_lcdfb_info lcdc_data;
286
287static struct resource lcdc_resources[] = {
288 [0] = {
289 .start = AT91SAM9RL_LCDC_BASE,
290 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
291 .flags = IORESOURCE_MEM,
292 },
293 [1] = {
294 .start = AT91SAM9RL_ID_LCDC,
295 .end = AT91SAM9RL_ID_LCDC,
296 .flags = IORESOURCE_IRQ,
297 },
298#if defined(CONFIG_FB_INTSRAM)
299 [2] = {
300 .start = AT91SAM9RL_SRAM_BASE,
301 .end = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
302 .flags = IORESOURCE_MEM,
303 },
304#endif
305};
306
307static struct platform_device at91_lcdc_device = {
308 .name = "atmel_lcdfb",
309 .id = 0,
310 .dev = {
311 .dma_mask = &lcdc_dmamask,
312 .coherent_dma_mask = 0xffffffff,
313 .platform_data = &lcdc_data,
314 },
315 .resource = lcdc_resources,
316 .num_resources = ARRAY_SIZE(lcdc_resources),
317};
318
319void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
320{
321 if (!data) {
322 return;
323 }
324
325 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
326 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
327 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
328 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
329 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
330 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
331 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
332 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
333 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
334 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
335 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
336 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
337 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
338 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
339 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
340 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
341 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
342 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
343 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
344 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
345 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
346
347 lcdc_data = *data;
348 platform_device_register(&at91_lcdc_device);
349}
350#else
351void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
352#endif
353
354
355/* --------------------------------------------------------------------
356 * LEDs
357 * -------------------------------------------------------------------- */
358
359#if defined(CONFIG_LEDS)
360u8 at91_leds_cpu;
361u8 at91_leds_timer;
362
363void __init at91_init_leds(u8 cpu_led, u8 timer_led)
364{
365 /* Enable GPIO to access the LEDs */
366 at91_set_gpio_output(cpu_led, 1);
367 at91_set_gpio_output(timer_led, 1);
368
369 at91_leds_cpu = cpu_led;
370 at91_leds_timer = timer_led;
371}
372#else
373void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
374#endif
375
376
377/* --------------------------------------------------------------------
378 * UART
379 * -------------------------------------------------------------------- */
380
381#if defined(CONFIG_SERIAL_ATMEL)
382static struct resource dbgu_resources[] = {
383 [0] = {
384 .start = AT91_VA_BASE_SYS + AT91_DBGU,
385 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
389 .start = AT91_ID_SYS,
390 .end = AT91_ID_SYS,
391 .flags = IORESOURCE_IRQ,
392 },
393};
394
395static struct atmel_uart_data dbgu_data = {
396 .use_dma_tx = 0,
397 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
398 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
399};
400
401static struct platform_device at91sam9rl_dbgu_device = {
402 .name = "atmel_usart",
403 .id = 0,
404 .dev = {
405 .platform_data = &dbgu_data,
406 .coherent_dma_mask = 0xffffffff,
407 },
408 .resource = dbgu_resources,
409 .num_resources = ARRAY_SIZE(dbgu_resources),
410};
411
412static inline void configure_dbgu_pins(void)
413{
414 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
415 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
416}
417
418static struct resource uart0_resources[] = {
419 [0] = {
420 .start = AT91SAM9RL_BASE_US0,
421 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
422 .flags = IORESOURCE_MEM,
423 },
424 [1] = {
425 .start = AT91SAM9RL_ID_US0,
426 .end = AT91SAM9RL_ID_US0,
427 .flags = IORESOURCE_IRQ,
428 },
429};
430
431static struct atmel_uart_data uart0_data = {
432 .use_dma_tx = 1,
433 .use_dma_rx = 1,
434};
435
436static struct platform_device at91sam9rl_uart0_device = {
437 .name = "atmel_usart",
438 .id = 1,
439 .dev = {
440 .platform_data = &uart0_data,
441 .coherent_dma_mask = 0xffffffff,
442 },
443 .resource = uart0_resources,
444 .num_resources = ARRAY_SIZE(uart0_resources),
445};
446
447static inline void configure_usart0_pins(void)
448{
449 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
450 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
451 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
452 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
453}
454
455static struct resource uart1_resources[] = {
456 [0] = {
457 .start = AT91SAM9RL_BASE_US1,
458 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
459 .flags = IORESOURCE_MEM,
460 },
461 [1] = {
462 .start = AT91SAM9RL_ID_US1,
463 .end = AT91SAM9RL_ID_US1,
464 .flags = IORESOURCE_IRQ,
465 },
466};
467
468static struct atmel_uart_data uart1_data = {
469 .use_dma_tx = 1,
470 .use_dma_rx = 1,
471};
472
473static struct platform_device at91sam9rl_uart1_device = {
474 .name = "atmel_usart",
475 .id = 2,
476 .dev = {
477 .platform_data = &uart1_data,
478 .coherent_dma_mask = 0xffffffff,
479 },
480 .resource = uart1_resources,
481 .num_resources = ARRAY_SIZE(uart1_resources),
482};
483
484static inline void configure_usart1_pins(void)
485{
486 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
487 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
488}
489
490static struct resource uart2_resources[] = {
491 [0] = {
492 .start = AT91SAM9RL_BASE_US2,
493 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
494 .flags = IORESOURCE_MEM,
495 },
496 [1] = {
497 .start = AT91SAM9RL_ID_US2,
498 .end = AT91SAM9RL_ID_US2,
499 .flags = IORESOURCE_IRQ,
500 },
501};
502
503static struct atmel_uart_data uart2_data = {
504 .use_dma_tx = 1,
505 .use_dma_rx = 1,
506};
507
508static struct platform_device at91sam9rl_uart2_device = {
509 .name = "atmel_usart",
510 .id = 3,
511 .dev = {
512 .platform_data = &uart2_data,
513 .coherent_dma_mask = 0xffffffff,
514 },
515 .resource = uart2_resources,
516 .num_resources = ARRAY_SIZE(uart2_resources),
517};
518
519static inline void configure_usart2_pins(void)
520{
521 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
522 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
523}
524
525static struct resource uart3_resources[] = {
526 [0] = {
527 .start = AT91SAM9RL_BASE_US3,
528 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
529 .flags = IORESOURCE_MEM,
530 },
531 [1] = {
532 .start = AT91SAM9RL_ID_US3,
533 .end = AT91SAM9RL_ID_US3,
534 .flags = IORESOURCE_IRQ,
535 },
536};
537
538static struct atmel_uart_data uart3_data = {
539 .use_dma_tx = 1,
540 .use_dma_rx = 1,
541};
542
543static struct platform_device at91sam9rl_uart3_device = {
544 .name = "atmel_usart",
545 .id = 4,
546 .dev = {
547 .platform_data = &uart3_data,
548 .coherent_dma_mask = 0xffffffff,
549 },
550 .resource = uart3_resources,
551 .num_resources = ARRAY_SIZE(uart3_resources),
552};
553
554static inline void configure_usart3_pins(void)
555{
556 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
557 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
558}
559
560struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
561struct platform_device *atmel_default_console_device; /* the serial console device */
562
563void __init at91_init_serial(struct at91_uart_config *config)
564{
565 int i;
566
567 /* Fill in list of supported UARTs */
568 for (i = 0; i < config->nr_tty; i++) {
569 switch (config->tty_map[i]) {
570 case 0:
571 configure_usart0_pins();
572 at91_uarts[i] = &at91sam9rl_uart0_device;
573 at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
574 break;
575 case 1:
576 configure_usart1_pins();
577 at91_uarts[i] = &at91sam9rl_uart1_device;
578 at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
579 break;
580 case 2:
581 configure_usart2_pins();
582 at91_uarts[i] = &at91sam9rl_uart2_device;
583 at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
584 break;
585 case 3:
586 configure_usart3_pins();
587 at91_uarts[i] = &at91sam9rl_uart3_device;
588 at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
589 break;
590 case 4:
591 configure_dbgu_pins();
592 at91_uarts[i] = &at91sam9rl_dbgu_device;
593 at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
594 break;
595 default:
596 continue;
597 }
598 at91_uarts[i]->id = i; /* update ID number to mapped ID */
599 }
600
601 /* Set serial console device */
602 if (config->console_tty < ATMEL_MAX_UART)
603 atmel_default_console_device = at91_uarts[config->console_tty];
604 if (!atmel_default_console_device)
605 printk(KERN_INFO "AT91: No default serial console defined.\n");
606}
607
608void __init at91_add_device_serial(void)
609{
610 int i;
611
612 for (i = 0; i < ATMEL_MAX_UART; i++) {
613 if (at91_uarts[i])
614 platform_device_register(at91_uarts[i]);
615 }
616}
617#else
618void __init at91_init_serial(struct at91_uart_config *config) {}
619void __init at91_add_device_serial(void) {}
620#endif
621
622
623/* -------------------------------------------------------------------- */
624
625/*
626 * These devices are always present and don't need any board-specific
627 * setup.
628 */
629static int __init at91_add_standard_devices(void)
630{
631 return 0;
632}
633
634arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index bda26221c522..68ed71a3e6c6 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -13,12 +13,14 @@ extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned shor
13extern void __init at91sam9260_initialize(unsigned long main_clock); 13extern void __init at91sam9260_initialize(unsigned long main_clock);
14extern void __init at91sam9261_initialize(unsigned long main_clock); 14extern void __init at91sam9261_initialize(unsigned long main_clock);
15extern void __init at91sam9263_initialize(unsigned long main_clock); 15extern void __init at91sam9263_initialize(unsigned long main_clock);
16extern void __init at91sam9rl_initialize(unsigned long main_clock);
16 17
17 /* Interrupts */ 18 /* Interrupts */
18extern void __init at91rm9200_init_interrupts(unsigned int priority[]); 19extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
19extern void __init at91sam9260_init_interrupts(unsigned int priority[]); 20extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
20extern void __init at91sam9261_init_interrupts(unsigned int priority[]); 21extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
21extern void __init at91sam9263_init_interrupts(unsigned int priority[]); 22extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
23extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
22extern void __init at91_aic_init(unsigned int priority[]); 24extern void __init at91_aic_init(unsigned int priority[]);
23 25
24 /* Timer */ 26 /* Timer */
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 2900e59395a5..b8320a12e6b7 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -171,8 +171,8 @@ config CPU_ARM925T
171# ARM926T 171# ARM926T
172config CPU_ARM926T 172config CPU_ARM926T
173 bool "Support ARM926T processor" 173 bool "Support ARM926T processor"
174 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX || ARCH_DAVINCI 174 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
175 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX || ARCH_DAVINCI 175 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
176 select CPU_32v5 176 select CPU_32v5
177 select CPU_ABRT_EV5TJ 177 select CPU_ABRT_EV5TJ
178 select CPU_CACHE_VIVT 178 select CPU_CACHE_VIVT
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 8065f2b53701..f771a7cae9ec 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -210,7 +210,7 @@ config USB_OTG
210 210
211config USB_GADGET_AT91 211config USB_GADGET_AT91
212 boolean "AT91 USB Device Port" 212 boolean "AT91 USB Device Port"
213 depends on ARCH_AT91 213 depends on ARCH_AT91 && !ARCH_AT91SAM9RL
214 select USB_GADGET_SELECTED 214 select USB_GADGET_SELECTED
215 help 215 help
216 Many Atmel AT91 processors (such as the AT91RM2000) have a 216 Many Atmel AT91 processors (such as the AT91RM2000) have a
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
new file mode 100644
index 000000000000..8a9708a370c6
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -0,0 +1,110 @@
1/*
2 * include/asm-arm/arch-at91/at91sam9260.h
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * Common definitions.
7 * Based on AT91SAM9RL datasheet revision A. (Preliminary)
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14#ifndef AT91SAM9RL_H
15#define AT91SAM9RL_H
16
17/*
18 * Peripheral identifiers/interrupts.
19 */
20#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
21#define AT91_ID_SYS 1 /* System Controller */
22#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
23#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
24#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
25#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
26#define AT91SAM9RL_ID_US0 6 /* USART 0 */
27#define AT91SAM9RL_ID_US1 7 /* USART 1 */
28#define AT91SAM9RL_ID_US2 8 /* USART 2 */
29#define AT91SAM9RL_ID_US3 9 /* USART 3 */
30#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
31#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
32#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
33#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
34#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
35#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
36#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
37#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
38#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
39#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
40#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
41#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
42#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
43#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
44#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
45#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
46
47
48/*
49 * User Peripheral physical base addresses.
50 */
51#define AT91SAM9RL_BASE_TCB0 0xfffa0000
52#define AT91SAM9RL_BASE_TC0 0xfffa0000
53#define AT91SAM9RL_BASE_TC1 0xfffa0040
54#define AT91SAM9RL_BASE_TC2 0xfffa0080
55#define AT91SAM9RL_BASE_MCI 0xfffa4000
56#define AT91SAM9RL_BASE_TWI0 0xfffa8000
57#define AT91SAM9RL_BASE_TWI1 0xfffac000
58#define AT91SAM9RL_BASE_US0 0xfffb0000
59#define AT91SAM9RL_BASE_US1 0xfffb4000
60#define AT91SAM9RL_BASE_US2 0xfffb8000
61#define AT91SAM9RL_BASE_US3 0xfffbc000
62#define AT91SAM9RL_BASE_SSC0 0xfffc0000
63#define AT91SAM9RL_BASE_SSC1 0xfffc4000
64#define AT91SAM9RL_BASE_PWMC 0xfffc8000
65#define AT91SAM9RL_BASE_SPI 0xfffcc000
66#define AT91SAM9RL_BASE_TSC 0xfffd0000
67#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
68#define AT91SAM9RL_BASE_AC97C 0xfffd8000
69#define AT91_BASE_SYS 0xffffc000
70
71
72/*
73 * System Peripherals (offset from AT91_BASE_SYS)
74 */
75#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
76#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
77#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
78#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
79#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
80#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
81#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
82#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
83#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
84#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
85#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
86#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
87#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
88#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
89#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
90#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
91#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
92#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
93#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
95#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
96
97
98/*
99 * Internal Memory.
100 */
101#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
102#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
103
104#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
105#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
106
107#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
108#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */
109
110#endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
new file mode 100644
index 000000000000..b15f11b7c08d
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
@@ -0,0 +1,96 @@
1/*
2 * include/asm-arm/arch-at91/at91sam9rl_matrix.h
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9RL datasheet revision A. (Preliminary)
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14#ifndef AT91SAM9RL_MATRIX_H
15#define AT91SAM9RL_MATRIX_H
16
17#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
18#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
19#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
20#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
21#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
22#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
23#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
24#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
25#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
26#define AT91_MATRIX_ULBT_FOUR (2 << 0)
27#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
28#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
29
30#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
31#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
32#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
33#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
34#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
35#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
39#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
40#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
41#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
42#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45
46#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
52#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
53#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
54#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
55#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
56#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
57#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
58
59#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
60#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
61#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
62#define AT91_MATRIX_RCB2 (1 << 2)
63#define AT91_MATRIX_RCB3 (1 << 3)
64#define AT91_MATRIX_RCB4 (1 << 4)
65#define AT91_MATRIX_RCB5 (1 << 5)
66
67#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
68#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
69#define AT91_MATRIX_ITCM_0 (0 << 0)
70#define AT91_MATRIX_ITCM_16 (5 << 0)
71#define AT91_MATRIX_ITCM_32 (6 << 0)
72#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
73#define AT91_MATRIX_DTCM_0 (0 << 4)
74#define AT91_MATRIX_DTCM_16 (5 << 4)
75#define AT91_MATRIX_DTCM_32 (6 << 4)
76
77#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
78#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
79#define AT91_MATRIX_CS1A_SMC (0 << 1)
80#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
81#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
82#define AT91_MATRIX_CS3A_SMC (0 << 3)
83#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
84#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
85#define AT91_MATRIX_CS4A_SMC (0 << 4)
86#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
87#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
88#define AT91_MATRIX_CS5A_SMC (0 << 5)
89#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
90#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
91#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
92#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
93#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
94
95
96#endif
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 7ef4eebe9f8e..ef93c30a9c5f 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -26,6 +26,8 @@
26#define ARCH_ID_AT91SAM9XE256 0x329a93a0 26#define ARCH_ID_AT91SAM9XE256 0x329a93a0
27#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 27#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
28 28
29#define ARCH_ID_AT91SAM9RL64 0x019b03a0
30
29static inline unsigned long at91_cpu_identify(void) 31static inline unsigned long at91_cpu_identify(void)
30{ 32{
31 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); 33 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
@@ -68,6 +70,13 @@ static inline unsigned long at91_arch_identify(void)
68#define cpu_is_at91sam9263() (0) 70#define cpu_is_at91sam9263() (0)
69#endif 71#endif
70 72
73#ifdef CONFIG_ARCH_AT91SAM9RL
74#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
75#else
76#define cpu_is_at91sam9rl() (0)
77#endif
78
79
71/* 80/*
72 * Since this is ARM, we will never run on any AVR32 CPU. But these 81 * Since this is ARM, we will never run on any AVR32 CPU. But these
73 * definitions may reduce clutter in common drivers. 82 * definitions may reduce clutter in common drivers.
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 28133e0154dd..0e51ad224eaa 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -24,6 +24,8 @@
24#include <asm/arch/at91sam9261.h> 24#include <asm/arch/at91sam9261.h>
25#elif defined(CONFIG_ARCH_AT91SAM9263) 25#elif defined(CONFIG_ARCH_AT91SAM9263)
26#include <asm/arch/at91sam9263.h> 26#include <asm/arch/at91sam9263.h>
27#elif defined(CONFIG_ARCH_AT91SAM9RL)
28#include <asm/arch/at91sam9rl.h>
27#else 29#else
28#error "Unsupported AT91 processor" 30#error "Unsupported AT91 processor"
29#endif 31#endif
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index f41636d607a2..2df1ee12dfb7 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -37,6 +37,11 @@
37#define AT91SAM9_MASTER_CLOCK 99959500 37#define AT91SAM9_MASTER_CLOCK 99959500
38#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 38#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
39 39
40#elif defined(CONFIG_ARCH_AT91SAM9RL)
41
42#define AT91SAM9_MASTER_CLOCK 100000000
43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
44
40#endif 45#endif
41 46
42#endif 47#endif
diff --git a/include/asm-avr32/arch-at32ap/cpu.h b/include/asm-avr32/arch-at32ap/cpu.h
index 2bdc5bd6f793..a762f42cbb71 100644
--- a/include/asm-avr32/arch-at32ap/cpu.h
+++ b/include/asm-avr32/arch-at32ap/cpu.h
@@ -29,5 +29,6 @@
29#define cpu_is_at91sam9260() (0) 29#define cpu_is_at91sam9260() (0)
30#define cpu_is_at91sam9261() (0) 30#define cpu_is_at91sam9261() (0)
31#define cpu_is_at91sam9263() (0) 31#define cpu_is_at91sam9263() (0)
32#define cpu_is_at91sam9rl() (0)
32 33
33#endif /* __ASM_ARCH_CPU_H */ 34#endif /* __ASM_ARCH_CPU_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 09:55:14 -0500