71 files changed, 3340 insertions, 965 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0d8fac3b0371..d7c0984d4a86 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -354,6 +354,7 @@ config ARCH_SA1100
 config ARCH_S3C2410
        bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
        select GENERIC_GPIO
+        select GENERIC_TIME
        help
          Samsung S3C2410X CPU based systems, such as the Simtec Electronics
          BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ab9f2d4bd04e..00ea4305ad5d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -47,8 +47,13 @@ comma = ,
 # Note that GCC does not numerically define an architecture version
 # macro, but instead defines a whole series of macros which makes
 # testing for a specific architecture or later rather impossible.
+arch-$(CONFIG_CPU_32v7)         :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a)
 arch-$(CONFIG_CPU_32v6)         :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
+# Only override the compiler option if ARMv6. The ARMv6K extensions are
+# always available in ARMv7
+ifeq ($(CONFIG_CPU_32v6),y)
 arch-$(CONFIG_CPU_32v6K)        :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
+endif
 arch-$(CONFIG_CPU_32v5)         :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
 arch-$(CONFIG_CPU_32v4T)        :=-D__LINUX_ARM_ARCH__=4 -march=armv4t
 arch-$(CONFIG_CPU_32v4)         :=-D__LINUX_ARM_ARCH__=4 -march=armv4
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 8781aaeb576b..ab1b17d35bd3 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -22,6 +22,7 @@ comment "OMAP Board Type"
 config MACH_OMAP_INNOVATOR
        bool "TI Innovator"
        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
+        select OMAP_MCBSP
        help
          TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
          have such a board.
@@ -29,6 +30,7 @@ config MACH_OMAP_INNOVATOR
 config MACH_OMAP_H2
        bool "TI H2 Support"
        depends on ARCH_OMAP1 && ARCH_OMAP16XX
+        select OMAP_MCBSP
        help
          TI OMAP 1610/1611B H2 board support. Say Y here if you have such
          a board.
@@ -36,6 +38,7 @@ config MACH_OMAP_H2
 config MACH_OMAP_H3
        bool "TI H3 Support"
        depends on ARCH_OMAP1 && ARCH_OMAP16XX
+        select GPIOEXPANDER_OMAP
        help
          TI OMAP 1710 H3 board support. Say Y here if you have such
          a board.
@@ -43,7 +46,7 @@ config MACH_OMAP_H3
 config MACH_OMAP_OSK
        bool "TI OSK Support"
        depends on ARCH_OMAP1 && ARCH_OMAP16XX
-        select TPS65010
+        select OMAP_MCBSP
        help
          TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here
          if you have such a board.
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 7165f74f78da..a8b9a00cea22 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -37,4 +37,3 @@ led-$(CONFIG_MACH_OMAP_INNOVATOR)	+= leds-innovator.o
 led-$(CONFIG_MACH_OMAP_PERSEUS2)        += leds-h2p2-debug.o
 led-$(CONFIG_MACH_OMAP_OSK)             += leds-osk.o
 obj-$(CONFIG_LEDS)                      += $(led-y)
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 62e42c7a628e..f65baa95986e 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -246,7 +246,7 @@ static void __init fsample_init_smc91x(void)
        mdelay(50);
 }
-void omap_fsample_init_irq(void)
+static void __init omap_fsample_init_irq(void)
 {
        omap1_init_common_hw();
        omap_init_irq();
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 9d2346fb68f4..7b260b7c537b 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -455,7 +455,7 @@ static void __init h3_init_smc91x(void)
        }
 }
-void h3_init_irq(void)
+static void __init h3_init_irq(void)
 {
        omap1_init_common_hw();
        omap_init_irq();
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index cb00530ad279..7e63a41e37c6 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -308,7 +308,7 @@ static void __init innovator_init_smc91x(void)
        }
 }
-void innovator_init_irq(void)
+static void __init innovator_init_irq(void)
 {
        omap1_init_common_hw();
        omap_init_irq();
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index fa4be962df67..1d5c8d509722 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -246,7 +246,7 @@ static void __init perseus2_init_smc91x(void)
        mdelay(50);
 }
-void omap_perseus2_init_irq(void)
+static void __init omap_perseus2_init_irq(void)
 {
        omap1_init_common_hw();
        omap_init_irq();
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 6dcd10ab4496..da8a3ac47e13 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -24,35 +24,6 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/gpio.h>
-#if     defined(CONFIG_OMAP1610_IR) || defined(CONFIG_OMAP161O_IR_MODULE)
-static u64 irda_dmamask = 0xffffffff;
-static struct platform_device omap1610ir_device = {
-        .name = "omap1610-ir",
-        .id = -1,
-        .dev = {
-                .dma_mask       = &irda_dmamask,
-        },
-};
-static void omap_init_irda(void)
-{
-        /* FIXME define and use a boot tag, members something like:
-         *  u8          uart;           // uart1, or uart3
-         * ... but driver only handles uart3 for now
-         *  s16         fir_sel;        // gpio for SIR vs FIR
-         * ... may prefer a callback for SIR/MIR/FIR mode select;
-         * while h2 uses a GPIO, H3 uses a gpio expander
-         */
-        if (machine_is_omap_h2()
-                        || machine_is_omap_h3())
-                (void) platform_device_register(&omap1610ir_device);
-}
-#else
-static inline void omap_init_irda(void) {}
-#endif
 /*-------------------------------------------------------------------------*/
 #if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE)
@@ -90,6 +61,45 @@ static void omap_init_rtc(void)
 static inline void omap_init_rtc(void) {}
 #endif
+#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
+#if defined(CONFIG_ARCH_OMAP15XX)
+#  define OMAP1_MBOX_SIZE       0x23
+#  define INT_DSP_MAILBOX1      INT_1510_DSP_MAILBOX1
+#elif defined(CONFIG_ARCH_OMAP16XX)
+#  define OMAP1_MBOX_SIZE       0x2f
+#  define INT_DSP_MAILBOX1      INT_1610_DSP_MAILBOX1
+#endif
+#define OMAP1_MBOX_BASE         IO_ADDRESS(OMAP16XX_MAILBOX_BASE)
+static struct resource mbox_resources[] = {
+        {
+                .start          = OMAP1_MBOX_BASE,
+                .end            = OMAP1_MBOX_BASE + OMAP1_MBOX_SIZE,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = INT_DSP_MAILBOX1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device mbox_device = {
+        .name           = "mailbox",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(mbox_resources),
+        .resource       = mbox_resources,
+};
+static inline void omap_init_mbox(void)
+{
+        platform_device_register(&mbox_device);
+}
+#else
+static inline void omap_init_mbox(void) { }
+#endif
 #if defined(CONFIG_OMAP_STI)
 #define OMAP1_STI_BASE          IO_ADDRESS(0xfffea000)
@@ -154,7 +164,8 @@ static int __init omap1_init_devices(void)
        /* please keep these calls, and their implementations above,
         * in alphabetical order so they're easier to sort through.
         */
-        omap_init_irda();
+        omap_init_mbox();
        omap_init_rtc();
        omap_init_sti();
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index fab8b0b27cfb..81c4e738506c 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -17,11 +17,11 @@
 #include <asm/io.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/tc.h>
-#include <asm/arch/omapfb.h>
 extern int omap1_clk_init(void);
 extern void omap_check_revision(void);
 extern void omap_sram_init(void);
+extern void omapfb_reserve_sdram(void);
 /*
 * The machine specific code may provide the extra mapping besides the
@@ -121,7 +121,7 @@ void __init omap1_map_common_io(void)
 #endif
        omap_sram_init();
-        omapfb_reserve_mem();
+        omapfb_reserve_sdram();
 }
 /*
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
new file mode 100644
index 000000000000..d3abf5609902
--- /dev/null
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -0,0 +1,206 @@
+/*
+ * Mailbox reservation modules for DSP
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/resource.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/irqs.h>
+#include <asm/io.h>
+#define MAILBOX_ARM2DSP1                0x00
+#define MAILBOX_ARM2DSP1b               0x04
+#define MAILBOX_DSP2ARM1                0x08
+#define MAILBOX_DSP2ARM1b               0x0c
+#define MAILBOX_DSP2ARM2                0x10
+#define MAILBOX_DSP2ARM2b               0x14
+#define MAILBOX_ARM2DSP1_Flag           0x18
+#define MAILBOX_DSP2ARM1_Flag           0x1c
+#define MAILBOX_DSP2ARM2_Flag           0x20
+unsigned long mbox_base;
+struct omap_mbox1_fifo {
+        unsigned long cmd;
+        unsigned long data;
+        unsigned long flag;
+};
+struct omap_mbox1_priv {
+        struct omap_mbox1_fifo tx_fifo;
+        struct omap_mbox1_fifo rx_fifo;
+};
+static inline int mbox_read_reg(unsigned int reg)
+{
+        return __raw_readw(mbox_base + reg);
+}
+static inline void mbox_write_reg(unsigned int val, unsigned int reg)
+{
+        __raw_writew(val, mbox_base + reg);
+}
+/* msg */
+static inline mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox)
+{
+        struct omap_mbox1_fifo *fifo =
+                &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
+        mbox_msg_t msg;
+        msg = mbox_read_reg(fifo->data);
+        msg |= ((mbox_msg_t) mbox_read_reg(fifo->cmd)) << 16;
+        return msg;
+}
+static inline void
+omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
+{
+        struct omap_mbox1_fifo *fifo =
+                &((struct omap_mbox1_priv *)mbox->priv)->tx_fifo;
+        mbox_write_reg(msg & 0xffff, fifo->data);
+        mbox_write_reg(msg >> 16, fifo->cmd);
+}
+static inline int omap1_mbox_fifo_empty(struct omap_mbox *mbox)
+{
+        return 0;
+}
+static inline int omap1_mbox_fifo_full(struct omap_mbox *mbox)
+{
+        struct omap_mbox1_fifo *fifo =
+                &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
+        return (mbox_read_reg(fifo->flag));
+}
+/* irq */
+static inline void
+omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
+{
+        if (irq == IRQ_RX)
+                enable_irq(mbox->irq);
+}
+static inline void
+omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
+{
+        if (irq == IRQ_RX)
+                disable_irq(mbox->irq);
+}
+static inline int
+omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
+{
+        if (irq == IRQ_TX)
+                return 0;
+        return 1;
+}
+static struct omap_mbox_ops omap1_mbox_ops = {
+        .type           = OMAP_MBOX_TYPE1,
+        .fifo_read      = omap1_mbox_fifo_read,
+        .fifo_write     = omap1_mbox_fifo_write,
+        .fifo_empty     = omap1_mbox_fifo_empty,
+        .fifo_full      = omap1_mbox_fifo_full,
+        .enable_irq     = omap1_mbox_enable_irq,
+        .disable_irq    = omap1_mbox_disable_irq,
+        .is_irq         = omap1_mbox_is_irq,
+};
+/* FIXME: the following struct should be created automatically by the user id */
+/* DSP */
+static struct omap_mbox1_priv omap1_mbox_dsp_priv = {
+        .tx_fifo = {
+                .cmd    = MAILBOX_ARM2DSP1b,
+                .data   = MAILBOX_ARM2DSP1,
+                .flag   = MAILBOX_ARM2DSP1_Flag,
+        },
+        .rx_fifo = {
+                .cmd    = MAILBOX_DSP2ARM1b,
+                .data   = MAILBOX_DSP2ARM1,
+                .flag   = MAILBOX_DSP2ARM1_Flag,
+        },
+};
+struct omap_mbox mbox_dsp_info = {
+        .name   = "dsp",
+        .ops    = &omap1_mbox_ops,
+        .priv   = &omap1_mbox_dsp_priv,
+};
+EXPORT_SYMBOL(mbox_dsp_info);
+static int __init omap1_mbox_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+        int ret = 0;
+        if (pdev->num_resources != 2) {
+                dev_err(&pdev->dev, "invalid number of resources: %d\n",
+                        pdev->num_resources);
+                return -ENODEV;
+        }
+        /* MBOX base */
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (unlikely(!res)) {
+                dev_err(&pdev->dev, "invalid mem resource\n");
+                return -ENODEV;
+        }
+        mbox_base = res->start;
+        /* DSP IRQ */
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (unlikely(!res)) {
+                dev_err(&pdev->dev, "invalid irq resource\n");
+                return -ENODEV;
+        }
+        mbox_dsp_info.irq = res->start;
+        ret = omap_mbox_register(&mbox_dsp_info);
+        return ret;
+}
+static int omap1_mbox_remove(struct platform_device *pdev)
+{
+        omap_mbox_unregister(&mbox_dsp_info);
+        return 0;
+}
+static struct platform_driver omap1_mbox_driver = {
+        .probe  = omap1_mbox_probe,
+        .remove = omap1_mbox_remove,
+        .driver = {
+                .name   = "mailbox",
+        },
+};
+static int __init omap1_mbox_init(void)
+{
+        return platform_driver_register(&omap1_mbox_driver);
+}
+static void __exit omap1_mbox_exit(void)
+{
+        platform_driver_unregister(&omap1_mbox_driver);
+}
+module_init(omap1_mbox_init);
+module_exit(omap1_mbox_exit);
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index aab97ccf1e63..7393109f5c30 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -9,6 +9,7 @@ config ARCH_OMAP2420
        bool "OMAP2420 support"
        depends on ARCH_OMAP24XX
        select OMAP_DM_TIMER
+        select ARCH_OMAP_OTG
 comment "OMAP Board Type"
        depends on ARCH_OMAP2
@@ -20,6 +21,7 @@ config MACH_OMAP_GENERIC
 config MACH_OMAP_H4
        bool "OMAP 2420 H4 board"
        depends on ARCH_OMAP2 && ARCH_OMAP24XX
+        select OMAP_DEBUG_LEDS if LEDS || LEDS_OMAP_DEBUG
 config MACH_OMAP_APOLLON
        bool "OMAP 2420 Apollon board"
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 1e7ed6d22ca9..452193f01531 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -266,12 +266,26 @@ static struct platform_device h4_lcd_device = {
        .id             = -1,
 };
+static struct resource h4_led_resources[] = {
+        [0] = {
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device h4_led_device = {
+        .name           = "omap_dbg_led",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(h4_led_resources),
+        .resource       = h4_led_resources,
+};
 static struct platform_device *h4_devices[] __initdata = {
        &h4_smc91x_device,
        &h4_flash_device,
        &h4_irda_device,
        &h4_kp_device,
        &h4_lcd_device,
+        &h4_led_device,
 };
 static inline void __init h4_init_smc91x(void)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index aa4322451e8b..52ec2f2d6360 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -24,7 +24,7 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/gpio.h>
-#if     defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
+#if     defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
 #define OMAP2_I2C_BASE2         0x48072000
 #define OMAP2_I2C_INT2          57
@@ -42,8 +42,8 @@ static struct resource i2c_resources2[] = {
 };
 static struct platform_device omap_i2c_device2 = {
-        .name           = "i2c_omap",
+        .name           = "i2c_omap",
-        .id             = 2,
+        .id             = 2,
        .num_resources  = ARRAY_SIZE(i2c_resources2),
        .resource       = i2c_resources2,
 };
@@ -66,6 +66,40 @@ static void omap_init_i2c(void) {}
 #endif
+#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
+#define OMAP2_MBOX_BASE         IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
+static struct resource mbox_resources[] = {
+        {
+                .start          = OMAP2_MBOX_BASE,
+                .end            = OMAP2_MBOX_BASE + 0x11f,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = INT_24XX_MAIL_U0_MPU,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = INT_24XX_MAIL_U3_MPU,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device mbox_device = {
+        .name           = "mailbox",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(mbox_resources),
+        .resource       = mbox_resources,
+};
+static inline void omap_init_mbox(void)
+{
+        platform_device_register(&mbox_device);
+}
+#else
+static inline void omap_init_mbox(void) { }
+#endif
 #if defined(CONFIG_OMAP_STI)
 #define OMAP2_STI_BASE          IO_ADDRESS(0x48068000)
@@ -111,29 +145,45 @@ static inline void omap_init_sti(void) {}
 #define OMAP2_MCSPI1_BASE               0x48098000
 #define OMAP2_MCSPI2_BASE               0x4809a000
-/* FIXME: use resources instead */
 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
-        .base           = io_p2v(OMAP2_MCSPI1_BASE),
        .num_cs         = 4,
 };
+static struct resource omap2_mcspi1_resources[] = {
+        {
+                .start          = OMAP2_MCSPI1_BASE,
+                .end            = OMAP2_MCSPI1_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
 struct platform_device omap2_mcspi1 = {
        .name           = "omap2_mcspi",
        .id             = 1,
+        .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
+        .resource       = omap2_mcspi1_resources,
        .dev            = {
                .platform_data = &omap2_mcspi1_config,
        },
 };
 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
-        .base           = io_p2v(OMAP2_MCSPI2_BASE),
        .num_cs         = 2,
 };
+static struct resource omap2_mcspi2_resources[] = {
+        {
+                .start          = OMAP2_MCSPI2_BASE,
+                .end            = OMAP2_MCSPI2_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
 struct platform_device omap2_mcspi2 = {
        .name           = "omap2_mcspi",
        .id             = 2,
+        .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
+        .resource       = omap2_mcspi2_resources,
        .dev            = {
                .platform_data = &omap2_mcspi2_config,
        },
@@ -157,10 +207,10 @@ static int __init omap2_init_devices(void)
         * in alphabetical order so they're easier to sort through.
         */
        omap_init_i2c();
+        omap_init_mbox();
        omap_init_mcspi();
        omap_init_sti();
        return 0;
 }
 arch_initcall(omap2_init_devices);
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index d8f57824423f..54c836a98456 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -246,14 +246,22 @@ static int gpmc_cs_mem_enabled(int cs)
        return l & (1 << 6);
 }
-static void gpmc_cs_set_reserved(int cs, int reserved)
+int gpmc_cs_set_reserved(int cs, int reserved)
 {
+        if (cs > GPMC_CS_NUM)
+                return -ENODEV;
        gpmc_cs_map &= ~(1 << cs);
        gpmc_cs_map |= (reserved ? 1 : 0) << cs;
+        return 0;
 }
-static int gpmc_cs_reserved(int cs)
+int gpmc_cs_reserved(int cs)
 {
+        if (cs > GPMC_CS_NUM)
+                return -ENODEV;
        return gpmc_cs_map & (1 << cs);
 }
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index a0728c33e5d9..82dc70f6b779 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -27,6 +27,7 @@ extern void omap_sram_init(void);
 extern int omap2_clk_init(void);
 extern void omap2_check_revision(void);
 extern void gpmc_init(void);
+extern void omapfb_reserve_sdram(void);
 /*
 * The machine specific code may provide the extra mapping besides the
@@ -40,9 +41,21 @@ static struct map_desc omap2_io_desc[] __initdata = {
                .type           = MT_DEVICE
        },
        {
-                .virtual        = L4_24XX_VIRT,
+                .virtual        = DSP_MEM_24XX_VIRT,
-                .pfn            = __phys_to_pfn(L4_24XX_PHYS),
+                .pfn            = __phys_to_pfn(DSP_MEM_24XX_PHYS),
-                .length         = L4_24XX_SIZE,
+                .length         = DSP_MEM_24XX_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = DSP_IPI_24XX_VIRT,
+                .pfn            = __phys_to_pfn(DSP_IPI_24XX_PHYS),
+                .length         = DSP_IPI_24XX_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = DSP_MMU_24XX_VIRT,
+                .pfn            = __phys_to_pfn(DSP_MMU_24XX_PHYS),
+                .length         = DSP_MMU_24XX_SIZE,
                .type           = MT_DEVICE
        }
 };
@@ -60,7 +73,7 @@ void __init omap2_map_common_io(void)
        omap2_check_revision();
        omap_sram_init();
-        omapfb_reserve_mem();
+        omapfb_reserve_sdram();
 }
 void __init omap2_init_common_hw(void)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
new file mode 100644
index 000000000000..b03cd06e055b
--- /dev/null
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -0,0 +1,318 @@
+/*
+ * Mailbox reservation modules for OMAP2
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *        and  Paul Mundt <paul.mundt@nokia.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/irqs.h>
+#include <asm/io.h>
+#define MAILBOX_REVISION                0x00
+#define MAILBOX_SYSCONFIG               0x10
+#define MAILBOX_SYSSTATUS               0x14
+#define MAILBOX_MESSAGE_0               0x40
+#define MAILBOX_MESSAGE_1               0x44
+#define MAILBOX_MESSAGE_2               0x48
+#define MAILBOX_MESSAGE_3               0x4c
+#define MAILBOX_MESSAGE_4               0x50
+#define MAILBOX_MESSAGE_5               0x54
+#define MAILBOX_FIFOSTATUS_0            0x80
+#define MAILBOX_FIFOSTATUS_1            0x84
+#define MAILBOX_FIFOSTATUS_2            0x88
+#define MAILBOX_FIFOSTATUS_3            0x8c
+#define MAILBOX_FIFOSTATUS_4            0x90
+#define MAILBOX_FIFOSTATUS_5            0x94
+#define MAILBOX_MSGSTATUS_0             0xc0
+#define MAILBOX_MSGSTATUS_1             0xc4
+#define MAILBOX_MSGSTATUS_2             0xc8
+#define MAILBOX_MSGSTATUS_3             0xcc
+#define MAILBOX_MSGSTATUS_4             0xd0
+#define MAILBOX_MSGSTATUS_5             0xd4
+#define MAILBOX_IRQSTATUS_0             0x100
+#define MAILBOX_IRQENABLE_0             0x104
+#define MAILBOX_IRQSTATUS_1             0x108
+#define MAILBOX_IRQENABLE_1             0x10c
+#define MAILBOX_IRQSTATUS_2             0x110
+#define MAILBOX_IRQENABLE_2             0x114
+#define MAILBOX_IRQSTATUS_3             0x118
+#define MAILBOX_IRQENABLE_3             0x11c
+static unsigned long mbox_base;
+#define MAILBOX_IRQ_NOTFULL(n)          (1 << (2 * (n) + 1))
+#define MAILBOX_IRQ_NEWMSG(n)           (1 << (2 * (n)))
+struct omap_mbox2_fifo {
+        unsigned long msg;
+        unsigned long fifo_stat;
+        unsigned long msg_stat;
+};
+struct omap_mbox2_priv {
+        struct omap_mbox2_fifo tx_fifo;
+        struct omap_mbox2_fifo rx_fifo;
+        unsigned long irqenable;
+        unsigned long irqstatus;
+        u32 newmsg_bit;
+        u32 notfull_bit;
+};
+static struct clk *mbox_ick_handle;
+static inline unsigned int mbox_read_reg(unsigned int reg)
+{
+        return __raw_readl(mbox_base + reg);
+}
+static inline void mbox_write_reg(unsigned int val, unsigned int reg)
+{
+        __raw_writel(val, mbox_base + reg);
+}
+/* Mailbox H/W preparations */
+static inline int omap2_mbox_startup(struct omap_mbox *mbox)
+{
+        unsigned int l;
+        mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
+        if (IS_ERR(mbox_ick_handle)) {
+                printk("Could not get mailboxes_ick\n");
+                return -ENODEV;
+        }
+        clk_enable(mbox_ick_handle);
+        /* set smart-idle & autoidle */
+        l = mbox_read_reg(MAILBOX_SYSCONFIG);
+        l |= 0x00000011;
+        mbox_write_reg(l, MAILBOX_SYSCONFIG);
+        return 0;
+}
+static inline void omap2_mbox_shutdown(struct omap_mbox *mbox)
+{
+        clk_disable(mbox_ick_handle);
+        clk_put(mbox_ick_handle);
+}
+/* Mailbox FIFO handle functions */
+static inline mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
+{
+        struct omap_mbox2_fifo *fifo =
+                &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
+        return (mbox_msg_t) mbox_read_reg(fifo->msg);
+}
+static inline void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
+{
+        struct omap_mbox2_fifo *fifo =
+                &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
+        mbox_write_reg(msg, fifo->msg);
+}
+static inline int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
+{
+        struct omap_mbox2_fifo *fifo =
+                &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
+        return (mbox_read_reg(fifo->msg_stat) == 0);
+}
+static inline int omap2_mbox_fifo_full(struct omap_mbox *mbox)
+{
+        struct omap_mbox2_fifo *fifo =
+                &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
+        return (mbox_read_reg(fifo->fifo_stat));
+}
+/* Mailbox IRQ handle functions */
+static inline void omap2_mbox_enable_irq(struct omap_mbox *mbox,
+                omap_mbox_type_t irq)
+{
+        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
+        l = mbox_read_reg(p->irqenable);
+        l |= bit;
+        mbox_write_reg(l, p->irqenable);
+}
+static inline void omap2_mbox_disable_irq(struct omap_mbox *mbox,
+                omap_mbox_type_t irq)
+{
+        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
+        l = mbox_read_reg(p->irqenable);
+        l &= ~bit;
+        mbox_write_reg(l, p->irqenable);
+}
+static inline void omap2_mbox_ack_irq(struct omap_mbox *mbox,
+                omap_mbox_type_t irq)
+{
+        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
+        mbox_write_reg(bit, p->irqstatus);
+}
+static inline int omap2_mbox_is_irq(struct omap_mbox *mbox,
+                omap_mbox_type_t irq)
+{
+        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
+        u32 enable = mbox_read_reg(p->irqenable);
+        u32 status = mbox_read_reg(p->irqstatus);
+        return (enable & status & bit);
+}
+static struct omap_mbox_ops omap2_mbox_ops = {
+        .type           = OMAP_MBOX_TYPE2,
+        .startup        = omap2_mbox_startup,
+        .shutdown       = omap2_mbox_shutdown,
+        .fifo_read      = omap2_mbox_fifo_read,
+        .fifo_write     = omap2_mbox_fifo_write,
+        .fifo_empty     = omap2_mbox_fifo_empty,
+        .fifo_full      = omap2_mbox_fifo_full,
+        .enable_irq     = omap2_mbox_enable_irq,
+        .disable_irq    = omap2_mbox_disable_irq,
+        .ack_irq        = omap2_mbox_ack_irq,
+        .is_irq         = omap2_mbox_is_irq,
+};
+/*
+ * MAILBOX 0: ARM -> DSP,
+ * MAILBOX 1: ARM <- DSP.
+ * MAILBOX 2: ARM -> IVA,
+ * MAILBOX 3: ARM <- IVA.
+ */
+/* FIXME: the following structs should be filled automatically by the user id */
+/* DSP */
+static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
+        .tx_fifo = {
+                .msg            = MAILBOX_MESSAGE_0,
+                .fifo_stat      = MAILBOX_FIFOSTATUS_0,
+        },
+        .rx_fifo = {
+                .msg            = MAILBOX_MESSAGE_1,
+                .msg_stat       = MAILBOX_MSGSTATUS_1,
+        },
+        .irqenable      = MAILBOX_IRQENABLE_0,
+        .irqstatus      = MAILBOX_IRQSTATUS_0,
+        .notfull_bit    = MAILBOX_IRQ_NOTFULL(0),
+        .newmsg_bit     = MAILBOX_IRQ_NEWMSG(1),
+};
+struct omap_mbox mbox_dsp_info = {
+        .name   = "dsp",
+        .ops    = &omap2_mbox_ops,
+        .priv   = &omap2_mbox_dsp_priv,
+};
+EXPORT_SYMBOL(mbox_dsp_info);
+/* IVA */
+static struct omap_mbox2_priv omap2_mbox_iva_priv = {
+        .tx_fifo = {
+                .msg            = MAILBOX_MESSAGE_2,
+                .fifo_stat      = MAILBOX_FIFOSTATUS_2,
+        },
+        .rx_fifo = {
+                .msg            = MAILBOX_MESSAGE_3,
+                .msg_stat       = MAILBOX_MSGSTATUS_3,
+        },
+        .irqenable      = MAILBOX_IRQENABLE_3,
+        .irqstatus      = MAILBOX_IRQSTATUS_3,
+        .notfull_bit    = MAILBOX_IRQ_NOTFULL(2),
+        .newmsg_bit     = MAILBOX_IRQ_NEWMSG(3),
+};
+static struct omap_mbox mbox_iva_info = {
+        .name   = "iva",
+        .ops    = &omap2_mbox_ops,
+        .priv   = &omap2_mbox_iva_priv,
+};
+static int __init omap2_mbox_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+        int ret = 0;
+        if (pdev->num_resources != 3) {
+                dev_err(&pdev->dev, "invalid number of resources: %d\n",
+                        pdev->num_resources);
+                return -ENODEV;
+        }
+        /* MBOX base */
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (unlikely(!res)) {
+                dev_err(&pdev->dev, "invalid mem resource\n");
+                return -ENODEV;
+        }
+        mbox_base = res->start;
+        /* DSP IRQ */
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (unlikely(!res)) {
+                dev_err(&pdev->dev, "invalid irq resource\n");
+                return -ENODEV;
+        }
+        mbox_dsp_info.irq = res->start;
+        ret = omap_mbox_register(&mbox_dsp_info);
+        /* IVA IRQ */
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+        if (unlikely(!res)) {
+                dev_err(&pdev->dev, "invalid irq resource\n");
+                return -ENODEV;
+        }
+        mbox_iva_info.irq = res->start;
+        ret = omap_mbox_register(&mbox_iva_info);
+        return ret;
+}
+static int omap2_mbox_remove(struct platform_device *pdev)
+{
+        omap_mbox_unregister(&mbox_dsp_info);
+        return 0;
+}
+static struct platform_driver omap2_mbox_driver = {
+        .probe = omap2_mbox_probe,
+        .remove = omap2_mbox_remove,
+        .driver = {
+                .name = "mailbox",
+        },
+};
+static int __init omap2_mbox_init(void)
+{
+        return platform_driver_register(&omap2_mbox_driver);
+}
+static void __exit omap2_mbox_exit(void)
+{
+        platform_driver_unregister(&omap2_mbox_driver);
+}
+module_init(omap2_mbox_init);
+module_exit(omap2_mbox_exit);
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e684e9b38216..b81391a4e374 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -366,6 +366,19 @@ config CPU_32v6K
          enabled will not boot on processors with do not support these
          instructions.
+# ARMv7
+config CPU_V7
+        bool "Support ARM V7 processor"
+        depends on ARCH_INTEGRATOR
+        select CPU_32v6K
+        select CPU_32v7
+        select CPU_ABRT_EV7
+        select CPU_CACHE_V7
+        select CPU_CACHE_VIPT
+        select CPU_CP15_MMU
+        select CPU_COPY_V6 if MMU
+        select CPU_TLB_V6 if MMU
 # Figure out what processor architecture version we should be using.
 # This defines the compiler instruction set which depends on the machine type.
 config CPU_32v3
@@ -391,6 +404,9 @@ config CPU_32v5
 config CPU_32v6
        bool
+config CPU_32v7
+        bool
 # The abort model
 config CPU_ABRT_NOMMU
        bool
@@ -413,6 +429,9 @@ config CPU_ABRT_EV5TJ
 config CPU_ABRT_EV6
        bool
+config CPU_ABRT_EV7
+        bool
 # The cache model
 config CPU_CACHE_V3
        bool
@@ -429,6 +448,9 @@ config CPU_CACHE_V4WB
 config CPU_CACHE_V6
        bool
+config CPU_CACHE_V7
+        bool
 config CPU_CACHE_VIVT
        bool
@@ -503,7 +525,7 @@ comment "Processor Features"
 config ARM_THUMB
        bool "Support Thumb user binaries"
-        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
+        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7
        default y
        help
          Say Y if you want to include kernel support for running user space
@@ -578,9 +600,15 @@ config CPU_CACHE_ROUND_ROBIN
          Say Y here to use the predictable round-robin cache replacement
          policy.  Unless you specifically require this or are unsure, say N.
+config CPU_L2CACHE_DISABLE
+        bool "Disable level 2 cache"
+        depends on CPU_V7
+        help
+          Say Y here to disable the level 2 cache.  If unsure, say N.
 config CPU_BPREDICT_DISABLE
        bool "Disable branch prediction"
-        depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3
+        depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
        help
          Say Y here to disable branch prediction.  If unsure, say N.
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 2f8b95947774..b5bd335ff14a 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -24,12 +24,14 @@ obj-$(CONFIG_CPU_ABRT_LV4T)	+= abort-lv4t.o
 obj-$(CONFIG_CPU_ABRT_EV5T)     += abort-ev5t.o
 obj-$(CONFIG_CPU_ABRT_EV5TJ)    += abort-ev5tj.o
 obj-$(CONFIG_CPU_ABRT_EV6)      += abort-ev6.o
+obj-$(CONFIG_CPU_ABRT_EV7)      += abort-ev7.o
 obj-$(CONFIG_CPU_CACHE_V3)      += cache-v3.o
 obj-$(CONFIG_CPU_CACHE_V4)      += cache-v4.o
 obj-$(CONFIG_CPU_CACHE_V4WT)    += cache-v4wt.o
 obj-$(CONFIG_CPU_CACHE_V4WB)    += cache-v4wb.o
 obj-$(CONFIG_CPU_CACHE_V6)      += cache-v6.o
+obj-$(CONFIG_CPU_CACHE_V7)      += cache-v7.o
 obj-$(CONFIG_CPU_COPY_V3)       += copypage-v3.o
 obj-$(CONFIG_CPU_COPY_V4WT)     += copypage-v4wt.o
@@ -66,5 +68,6 @@ obj-$(CONFIG_CPU_SA1100)	+= proc-sa1100.o
 obj-$(CONFIG_CPU_XSCALE)        += proc-xscale.o
 obj-$(CONFIG_CPU_XSC3)          += proc-xsc3.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
+obj-$(CONFIG_CPU_V7)            += proc-v7.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
new file mode 100644
index 000000000000..eb90bce38e14
--- /dev/null
+++ b/arch/arm/mm/abort-ev7.S
@@ -0,0 +1,32 @@
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+/*
+ * Function: v7_early_abort
+ *
+ * Params  : r2 = address of aborted instruction
+ *         : r3 = saved SPSR
+ *
+ * Returns : r0 = address of abort
+ *         : r1 = FSR, bit 11 = write
+ *         : r2-r8 = corrupted
+ *         : r9 = preserved
+ *         : sp = pointer to registers
+ *
+ * Purpose : obtain information about current aborted instruction.
+ */
+        .align  5
+ENTRY(v7_early_abort)
+        /*
+         * The effect of data aborts on on the exclusive access monitor are
+         * UNPREDICTABLE. Do a CLREX to clear the state
+         */
+        clrex
+        mrc     p15, 0, r1, c5, c0, 0           @ get FSR
+        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
+        /*
+         * V6 code adjusts the returned DFSR.
+         * New designs should not need to patch up faults.
+         */
+        mov     pc, lr
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
new file mode 100644
index 000000000000..35ffc4d95997
--- /dev/null
+++ b/arch/arm/mm/cache-v7.S
@@ -0,0 +1,253 @@
+/*
+ *  linux/arch/arm/mm/cache-v7.S
+ *
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *  Copyright (C) 2005 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7 processor support.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+#include "proc-macros.S"
+/*
+ *      v7_flush_dcache_all()
+ *
+ *      Flush the whole D-cache.
+ *
+ *      Corrupted registers: r0-r5, r7, r9-r11
+ *
+ *      - mm    - mm_struct describing address space
+ */
+ENTRY(v7_flush_dcache_all)
+        mrc     p15, 1, r0, c0, c0, 1           @ read clidr
+        ands    r3, r0, #0x7000000              @ extract loc from clidr
+        mov     r3, r3, lsr #23                 @ left align loc bit field
+        beq     finished                        @ if loc is 0, then no need to clean
+        mov     r10, #0                         @ start clean at cache level 0
+loop1:
+        add     r2, r10, r10, lsr #1            @ work out 3x current cache level
+        mov     r1, r0, lsr r2                  @ extract cache type bits from clidr
+        and     r1, r1, #7                      @ mask of the bits for current cache only
+        cmp     r1, #2                          @ see what cache we have at this level
+        blt     skip                            @ skip if no cache, or just i-cache
+        mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
+        isb                                     @ isb to sych the new cssr&csidr
+        mrc     p15, 1, r1, c0, c0, 0           @ read the new csidr
+        and     r2, r1, #7                      @ extract the length of the cache lines
+        add     r2, r2, #4                      @ add 4 (line length offset)
+        ldr     r4, =0x3ff
+        ands    r4, r4, r1, lsr #3              @ find maximum number on the way size
+        clz     r5, r4                          @ find bit position of way size increment
+        ldr     r7, =0x7fff
+        ands    r7, r7, r1, lsr #13             @ extract max number of the index size
+loop2:
+        mov     r9, r4                          @ create working copy of max way size
+loop3:
+        orr     r11, r10, r9, lsl r5            @ factor way and cache number into r11
+        orr     r11, r11, r7, lsl r2            @ factor index number into r11
+        mcr     p15, 0, r11, c7, c14, 2         @ clean & invalidate by set/way
+        subs    r9, r9, #1                      @ decrement the way
+        bge     loop3
+        subs    r7, r7, #1                      @ decrement the index
+        bge     loop2
+skip:
+        add     r10, r10, #2                    @ increment cache number
+        cmp     r3, r10
+        bgt     loop1
+finished:
+        mov     r10, #0                         @ swith back to cache level 0
+        mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
+        isb
+        mov     pc, lr
+/*
+ *      v7_flush_cache_all()
+ *
+ *      Flush the entire cache system.
+ *  The data cache flush is now achieved using atomic clean / invalidates
+ *  working outwards from L1 cache. This is done using Set/Way based cache
+ *  maintainance instructions.
+ *  The instruction cache can still be invalidated back to the point of
+ *  unification in a single instruction.
+ *
+ */
+ENTRY(v7_flush_kern_cache_all)
+        stmfd   sp!, {r4-r5, r7, r9-r11, lr}
+        bl      v7_flush_dcache_all
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
+        ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
+        mov     pc, lr
+/*
+ *      v7_flush_cache_all()
+ *
+ *      Flush all TLB entries in a particular address space
+ *
+ *      - mm    - mm_struct describing address space
+ */
+ENTRY(v7_flush_user_cache_all)
+        /*FALLTHROUGH*/
+/*
+ *      v7_flush_cache_range(start, end, flags)
+ *
+ *      Flush a range of TLB entries in the specified address space.
+ *
+ *      - start - start address (may not be aligned)
+ *      - end   - end address (exclusive, may not be aligned)
+ *      - flags - vm_area_struct flags describing address space
+ *
+ *      It is assumed that:
+ *      - we have a VIPT cache.
+ */
+ENTRY(v7_flush_user_cache_range)
+        mov     pc, lr
+/*
+ *      v7_coherent_kern_range(start,end)
+ *
+ *      Ensure that the I and D caches are coherent within specified
+ *      region.  This is typically used when code has been written to
+ *      a memory region, and will be executed.
+ *
+ *      - start   - virtual start address of region
+ *      - end     - virtual end address of region
+ *
+ *      It is assumed that:
+ *      - the Icache does not read data from the write buffer
+ */
+ENTRY(v7_coherent_kern_range)
+        /* FALLTHROUGH */
+/*
+ *      v7_coherent_user_range(start,end)
+ *
+ *      Ensure that the I and D caches are coherent within specified
+ *      region.  This is typically used when code has been written to
+ *      a memory region, and will be executed.
+ *
+ *      - start   - virtual start address of region
+ *      - end     - virtual end address of region
+ *
+ *      It is assumed that:
+ *      - the Icache does not read data from the write buffer
+ */
+ENTRY(v7_coherent_user_range)
+        dcache_line_size r2, r3
+        sub     r3, r2, #1
+        bic     r0, r0, r3
+1:      mcr     p15, 0, r0, c7, c11, 1          @ clean D line to the point of unification
+        dsb
+        mcr     p15, 0, r0, c7, c5, 1           @ invalidate I line
+        add     r0, r0, r2
+        cmp     r0, r1
+        blo     1b
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
+        dsb
+        isb
+        mov     pc, lr
+/*
+ *      v7_flush_kern_dcache_page(kaddr)
+ *
+ *      Ensure that the data held in the page kaddr is written back
+ *      to the page in question.
+ *
+ *      - kaddr   - kernel address (guaranteed to be page aligned)
+ */
+ENTRY(v7_flush_kern_dcache_page)
+        dcache_line_size r2, r3
+        add     r1, r0, #PAGE_SZ
+1:
+        mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line / unified line
+        add     r0, r0, r2
+        cmp     r0, r1
+        blo     1b
+        dsb
+        mov     pc, lr
+/*
+ *      v7_dma_inv_range(start,end)
+ *
+ *      Invalidate the data cache within the specified region; we will
+ *      be performing a DMA operation in this region and we want to
+ *      purge old data in the cache.
+ *
+ *      - start   - virtual start address of region
+ *      - end     - virtual end address of region
+ */
+ENTRY(v7_dma_inv_range)
+        dcache_line_size r2, r3
+        sub     r3, r2, #1
+        tst     r0, r3
+        bic     r0, r0, r3
+        mcrne   p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
+        tst     r1, r3
+        bic     r1, r1, r3
+        mcrne   p15, 0, r1, c7, c14, 1          @ clean & invalidate D / U line
+1:
+        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D / U line
+        add     r0, r0, r2
+        cmp     r0, r1
+        blo     1b
+        dsb
+        mov     pc, lr
+/*
+ *      v7_dma_clean_range(start,end)
+ *      - start   - virtual start address of region
+ *      - end     - virtual end address of region
+ */
+ENTRY(v7_dma_clean_range)
+        dcache_line_size r2, r3
+        sub     r3, r2, #1
+        bic     r0, r0, r3
+1:
+        mcr     p15, 0, r0, c7, c10, 1          @ clean D / U line
+        add     r0, r0, r2
+        cmp     r0, r1
+        blo     1b
+        dsb
+        mov     pc, lr
+/*
+ *      v7_dma_flush_range(start,end)
+ *      - start   - virtual start address of region
+ *      - end     - virtual end address of region
+ */
+ENTRY(v7_dma_flush_range)
+        dcache_line_size r2, r3
+        sub     r3, r2, #1
+        bic     r0, r0, r3
+1:
+        mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
+        add     r0, r0, r2
+        cmp     r0, r1
+        blo     1b
+        dsb
+        mov     pc, lr
+        __INITDATA
+        .type   v7_cache_fns, #object
+ENTRY(v7_cache_fns)
+        .long   v7_flush_kern_cache_all
+        .long   v7_flush_user_cache_all
+        .long   v7_flush_user_cache_range
+        .long   v7_coherent_kern_range
+        .long   v7_coherent_user_range
+        .long   v7_flush_kern_dcache_page
+        .long   v7_dma_inv_range
+        .long   v7_dma_clean_range
+        .long   v7_dma_flush_range
+        .size   v7_cache_fns, . - v7_cache_fns
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 930c04c4f53c..fc84fcc74380 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -49,6 +49,13 @@ void __new_context(struct mm_struct *mm)
                    : "r" (0));
                isb();
                flush_tlb_all();
+                if (icache_is_vivt_asid_tagged()) {
+                        asm("mcr        p15, 0, %0, c7, c5, 0   @ invalidate I-cache\n"
+                            "mcr        p15, 0, %0, c7, c5, 6   @ flush BTAC/BTB\n"
+                            :
+                            : "r" (0));
+                        dsb();
+                }
        }
        spin_unlock(&cpu_asid_lock);
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 9e2c89eb2115..b13150052a76 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -59,3 +59,15 @@
        .word   \ucset
 #endif
        .endm
+/*
+ * cache_line_size - get the cache line size from the CSIDR register
+ * (available on ARMv7+). It assumes that the CSSR register was configured
+ * to access the L1 data cache CSIDR.
+ */
+        .macro  dcache_line_size, reg, tmp
+        mrc     p15, 1, \tmp, c0, c0, 0         @ read CSIDR
+        and     \tmp, \tmp, #7                  @ cache line size encoding
+        mov     \reg, #16                       @ size offset
+        mov     \reg, \reg, lsl \tmp            @ actual cache line size
+        .endm
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
new file mode 100644
index 000000000000..dd823dd4a374
--- /dev/null
+++ b/arch/arm/mm/proc-v7.S
@@ -0,0 +1,262 @@
+/*
+ *  linux/arch/arm/mm/proc-v7.S
+ *
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7 processor support.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+#include <asm/elf.h>
+#include <asm/pgtable-hwdef.h>
+#include <asm/pgtable.h>
+#include "proc-macros.S"
+#define TTB_C           (1 << 0)
+#define TTB_S           (1 << 1)
+#define TTB_RGN_OC_WT   (2 << 3)
+#define TTB_RGN_OC_WB   (3 << 3)
+ENTRY(cpu_v7_proc_init)
+        mov     pc, lr
+ENTRY(cpu_v7_proc_fin)
+        mov     pc, lr
+/*
+ *      cpu_v7_reset(loc)
+ *
+ *      Perform a soft reset of the system.  Put the CPU into the
+ *      same state as it would be if it had been reset, and branch
+ *      to what would be the reset vector.
+ *
+ *      - loc   - location to jump to for soft reset
+ *
+ *      It is assumed that:
+ */
+        .align  5
+ENTRY(cpu_v7_reset)
+        mov     pc, r0
+/*
+ *      cpu_v7_do_idle()
+ *
+ *      Idle the processor (eg, wait for interrupt).
+ *
+ *      IRQs are already disabled.
+ */
+ENTRY(cpu_v7_do_idle)
+        .long   0xe320f003                      @ ARM V7 WFI instruction
+        mov     pc, lr
+ENTRY(cpu_v7_dcache_clean_area)
+#ifndef TLB_CAN_READ_FROM_L1_CACHE
+        dcache_line_size r2, r3
+1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        add     r0, r0, r2
+        subs    r1, r1, r2
+        bhi     1b
+        dsb
+#endif
+        mov     pc, lr
+/*
+ *      cpu_v7_switch_mm(pgd_phys, tsk)
+ *
+ *      Set the translation table base pointer to be pgd_phys
+ *
+ *      - pgd_phys - physical address of new TTB
+ *
+ *      It is assumed that:
+ *      - we are not using split page tables
+ */
+ENTRY(cpu_v7_switch_mm)
+        mov     r2, #0
+        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
+        orr     r0, r0, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
+        mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
+        isb
+1:      mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
+        isb
+        mcr     p15, 0, r1, c13, c0, 1          @ set context ID
+        isb
+        mov     pc, lr
+/*
+ *      cpu_v7_set_pte_ext(ptep, pte)
+ *
+ *      Set a level 2 translation table entry.
+ *
+ *      - ptep  - pointer to level 2 translation table entry
+ *                (hardware version is stored at -1024 bytes)
+ *      - pte   - PTE value to store
+ *      - ext   - value for extended PTE bits
+ *
+ *      Permissions:
+ *        YUWD  APX AP1 AP0     SVC     User
+ *        0xxx   0   0   0      no acc  no acc
+ *        100x   1   0   1      r/o     no acc
+ *        10x0   1   0   1      r/o     no acc
+ *        1011   0   0   1      r/w     no acc
+ *        110x   0   1   0      r/w     r/o
+ *        11x0   0   1   0      r/w     r/o
+ *        1111   0   1   1      r/w     r/w
+ */
+ENTRY(cpu_v7_set_pte_ext)
+        str     r1, [r0], #-2048                @ linux version
+        bic     r3, r1, #0x000003f0
+        bic     r3, r3, #0x00000003
+        orr     r3, r3, r2
+        orr     r3, r3, #PTE_EXT_AP0 | 2
+        tst     r1, #L_PTE_WRITE
+        tstne   r1, #L_PTE_DIRTY
+        orreq   r3, r3, #PTE_EXT_APX
+        tst     r1, #L_PTE_USER
+        orrne   r3, r3, #PTE_EXT_AP1
+        tstne   r3, #PTE_EXT_APX
+        bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+        tst     r1, #L_PTE_YOUNG
+        biceq   r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
+        tst     r1, #L_PTE_EXEC
+        orreq   r3, r3, #PTE_EXT_XN
+        tst     r1, #L_PTE_PRESENT
+        moveq   r3, #0
+        str     r3, [r0]
+        mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
+        mov     pc, lr
+cpu_v7_name:
+        .ascii  "ARMv7 Processor"
+        .align
+        .section ".text.init", #alloc, #execinstr
+/*
+ *      __v7_setup
+ *
+ *      Initialise TLB, Caches, and MMU state ready to switch the MMU
+ *      on.  Return in r0 the new CP15 C1 control register setting.
+ *
+ *      We automatically detect if we have a Harvard cache, and use the
+ *      Harvard cache control instructions insead of the unified cache
+ *      control instructions.
+ *
+ *      This should be able to cover all ARMv7 cores.
+ *
+ *      It is assumed that:
+ *      - cache type register is implemented
+ */
+__v7_setup:
+        adr     r12, __v7_setup_stack           @ the local stack
+        stmia   r12, {r0-r5, r7, r9, r11, lr}
+        bl      v7_flush_dcache_all
+        ldmia   r12, {r0-r5, r7, r9, r11, lr}
+        mov     r10, #0
+#ifdef HARVARD_CACHE
+        mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
+#endif
+        dsb
+        mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
+        mcr     p15, 0, r10, c2, c0, 2          @ TTB control register
+        orr     r4, r4, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
+        mcr     p15, 0, r4, c2, c0, 0           @ load TTB0
+        mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
+        mov     r10, #0x1f                      @ domains 0, 1 = manager
+        mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
+#ifndef CONFIG_CPU_L2CACHE_DISABLE
+        @ L2 cache configuration in the L2 aux control register
+        mrc     p15, 1, r10, c9, c0, 2
+        bic     r10, r10, #(1 << 16)            @ L2 outer cache
+        mcr     p15, 1, r10, c9, c0, 2
+        @ L2 cache is enabled in the aux control register
+        mrc     p15, 0, r10, c1, c0, 1
+        orr     r10, r10, #2
+        mcr     p15, 0, r10, c1, c0, 1
+#endif
+        mrc     p15, 0, r0, c1, c0, 0           @ read control register
+        ldr     r10, cr1_clear                  @ get mask for bits to clear
+        bic     r0, r0, r10                     @ clear bits them
+        ldr     r10, cr1_set                    @ get mask for bits to set
+        orr     r0, r0, r10                     @ set them
+        mov     pc, lr                          @ return to head.S:__ret
+        /*
+         *         V X F   I D LR
+         * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
+         * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
+         *         0 110       0011 1.00 .111 1101 < we want
+         */
+        .type   cr1_clear, #object
+        .type   cr1_set, #object
+cr1_clear:
+        .word   0x0120c302
+cr1_set:
+        .word   0x00c0387d
+__v7_setup_stack:
+        .space  4 * 11                          @ 11 registers
+        .type   v7_processor_functions, #object
+ENTRY(v7_processor_functions)
+        .word   v7_early_abort
+        .word   cpu_v7_proc_init
+        .word   cpu_v7_proc_fin
+        .word   cpu_v7_reset
+        .word   cpu_v7_do_idle
+        .word   cpu_v7_dcache_clean_area
+        .word   cpu_v7_switch_mm
+        .word   cpu_v7_set_pte_ext
+        .size   v7_processor_functions, . - v7_processor_functions
+        .type   cpu_arch_name, #object
+cpu_arch_name:
+        .asciz  "armv7"
+        .size   cpu_arch_name, . - cpu_arch_name
+        .type   cpu_elf_name, #object
+cpu_elf_name:
+        .asciz  "v7"
+        .size   cpu_elf_name, . - cpu_elf_name
+        .align
+        .section ".proc.info.init", #alloc, #execinstr
+        /*
+         * Match any ARMv7 processor core.
+         */
+        .type   __v7_proc_info, #object
+__v7_proc_info:
+        .long   0x000f0000              @ Required ID value
+        .long   0x000f0000              @ Mask for ID
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_XN | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __v7_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_v7_name
+        .long   v7_processor_functions
+        .long   v6wbi_tlb_fns
+        .long   v6_user_fns
+        .long   v7_cache_fns
+        .size   __v7_proc_info, . - __v7_proc_info
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 9e8d21eca4ec..cfc69f3842fd 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -20,6 +20,11 @@ endchoice
 comment "OMAP Feature Selections"
+config OMAP_DEBUG_LEDS
+        bool
+        help
+          For debug card leds on TI reference boards.
 config OMAP_RESET_CLOCKS
        bool "Reset unused clocks during boot"
        depends on ARCH_OMAP
@@ -58,6 +63,14 @@ config OMAP_MUX_WARNINGS
          to change the pin multiplexing setup.  When there are no warnings
          printed, it's safe to deselect OMAP_MUX for your product.
+config OMAP_MCBSP
+        bool "McBSP support"
+        depends on ARCH_OMAP
+        default y
+        help
+          Say Y here if you want support for the OMAP Multichannel
+          Buffered Serial Port.
 choice
        prompt "System timer"
        default OMAP_MPU_TIMER
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 2896b4546411..41a3c1cf3bd4 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,7 +3,8 @@
 #
 # Common support
-obj-y := common.o sram.o sram-fn.o clock.o devices.o dma.o mux.o gpio.o mcbsp.o usb.o fb.o
+obj-y := common.o sram.o sram-fn.o clock.o devices.o dma.o mux.o gpio.o \
+         usb.o fb.o
 obj-m :=
 obj-n :=
 obj-  :=
@@ -16,4 +17,4 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
 obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
+obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index f1179ad4be1b..0a603242f367 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -33,6 +33,41 @@ static DEFINE_SPINLOCK(clockfw_lock);
 static struct clk_functions *arch_clock;
+#ifdef CONFIG_PM_DEBUG
+static void print_parents(struct clk *clk)
+{
+        struct clk *p;
+        int printed = 0;
+        list_for_each_entry(p, &clocks, node) {
+                if (p->parent == clk && p->usecount) {
+                        if (!clk->usecount && !printed) {
+                                printk("MISMATCH: %s\n", clk->name);
+                                printed = 1;
+                        }
+                        printk("\t%-15s\n", p->name);
+                }
+        }
+}
+void clk_print_usecounts(void)
+{
+        unsigned long flags;
+        struct clk *p;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        list_for_each_entry(p, &clocks, node) {
+                if (p->usecount)
+                        printk("%-15s: %d\n", p->name, p->usecount);
+                print_parents(p);
+        }
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+}
+#endif
 /*-------------------------------------------------------------------------
 * Standard clock functions defined in include/linux/clk.h
 *-------------------------------------------------------------------------*/
@@ -249,6 +284,8 @@ void followparent_recalc(struct clk *clk)
                return;
        clk->rate = clk->parent->rate;
+        if (unlikely(clk->flags & RATE_PROPAGATES))
+                propagate_rate(clk);
 }
 /* Propagate rate to children */
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index fecd3d625995..dd8708ad0a71 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -93,8 +93,12 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
         * in the kernel. */
        for (i = 0; i < omap_board_config_size; i++) {
                if (omap_board_config[i].tag == tag) {
-                        kinfo = &omap_board_config[i];
+                        if (skip == 0) {
-                        break;
+                                kinfo = &omap_board_config[i];
+                                break;
+                        } else {
+                                skip--;
+                        }
                }
        }
        if (kinfo == NULL)
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
new file mode 100644
index 000000000000..9128a80d228f
--- /dev/null
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -0,0 +1,314 @@
+/*
+ * linux/arch/arm/plat-omap/debug-leds.c
+ *
+ * Copyright 2003 by Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+#include <asm/mach-types.h>
+#include <asm/arch/fpga.h>
+#include <asm/arch/gpio.h>
+/* Many OMAP development platforms reuse the same "debug board"; these
+ * platforms include H2, H3, H4, and Perseus2.  There are 16 LEDs on the
+ * debug board (all green), accessed through FPGA registers.
+ *
+ * The "surfer" expansion board and H2 sample board also have two-color
+ * green+red LEDs (in parallel), used here for timer and idle indicators
+ * in preference to the ones on the debug board, for a "Disco LED" effect.
+ *
+ * This driver exports either the original ARM LED API, the new generic
+ * one, or both.
+ */
+static spinlock_t                       lock;
+static struct h2p2_dbg_fpga __iomem     *fpga;
+static u16                              led_state, hw_led_state;
+#ifdef  CONFIG_LEDS_OMAP_DEBUG
+#define new_led_api()   1
+#else
+#define new_led_api()   0
+#endif
+/*-------------------------------------------------------------------------*/
+/* original ARM debug LED API:
+ *  - timer and idle leds (some boards use non-FPGA leds here);
+ *  - up to 4 generic leds, easily accessed in-kernel (any context)
+ */
+#define GPIO_LED_RED            3
+#define GPIO_LED_GREEN          OMAP_MPUIO(4)
+#define LED_STATE_ENABLED       0x01
+#define LED_STATE_CLAIMED       0x02
+#define LED_TIMER_ON            0x04
+#define GPIO_IDLE               GPIO_LED_GREEN
+#define GPIO_TIMER              GPIO_LED_RED
+static void h2p2_dbg_leds_event(led_event_t evt)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&lock, flags);
+        if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
+                goto done;
+        switch (evt) {
+        case led_start:
+                if (fpga)
+                        led_state |= LED_STATE_ENABLED;
+                break;
+        case led_stop:
+        case led_halted:
+                /* all leds off during suspend or shutdown */
+                if (!(machine_is_omap_perseus2() || machine_is_omap_h4())) {
+                        omap_set_gpio_dataout(GPIO_TIMER, 0);
+                        omap_set_gpio_dataout(GPIO_IDLE, 0);
+                }
+                __raw_writew(~0, &fpga->leds);
+                led_state &= ~LED_STATE_ENABLED;
+                goto done;
+        case led_claim:
+                led_state |= LED_STATE_CLAIMED;
+                hw_led_state = 0;
+                break;
+        case led_release:
+                led_state &= ~LED_STATE_CLAIMED;
+                break;
+#ifdef CONFIG_LEDS_TIMER
+        case led_timer:
+                led_state ^= LED_TIMER_ON;
+                if (machine_is_omap_perseus2() || machine_is_omap_h4())
+                        hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
+                else {
+                        omap_set_gpio_dataout(GPIO_TIMER,
+                                        led_state & LED_TIMER_ON);
+                        goto done;
+                }
+                break;
+#endif
+#ifdef CONFIG_LEDS_CPU
+        /* LED lit iff busy */
+        case led_idle_start:
+                if (machine_is_omap_perseus2() || machine_is_omap_h4())
+                        hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
+                else {
+                        omap_set_gpio_dataout(GPIO_IDLE, 1);
+                        goto done;
+                }
+                break;
+        case led_idle_end:
+                if (machine_is_omap_perseus2() || machine_is_omap_h4())
+                        hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
+                else {
+                        omap_set_gpio_dataout(GPIO_IDLE, 0);
+                        goto done;
+                }
+                break;
+#endif
+        case led_green_on:
+                hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
+                break;
+        case led_green_off:
+                hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
+                break;
+        case led_amber_on:
+                hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
+                break;
+        case led_amber_off:
+                hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
+                break;
+        case led_red_on:
+                hw_led_state |= H2P2_DBG_FPGA_LED_RED;
+                break;
+        case led_red_off:
+                hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
+                break;
+        case led_blue_on:
+                hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
+                break;
+        case led_blue_off:
+                hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
+                break;
+        default:
+                break;
+        }
+        /*
+         *  Actually burn the LEDs
+         */
+        if (led_state & LED_STATE_ENABLED)
+                __raw_writew(~hw_led_state, &fpga->leds);
+done:
+        spin_unlock_irqrestore(&lock, flags);
+}
+/*-------------------------------------------------------------------------*/
+/* "new" LED API
+ *  - with syfs access and generic triggering
+ *  - not readily accessible to in-kernel drivers
+ */
+struct dbg_led {
+        struct led_classdev     cdev;
+        u16                     mask;
+};
+static struct dbg_led dbg_leds[] = {
+        /* REVISIT at least H2 uses different timer & cpu leds... */
+#ifndef CONFIG_LEDS_TIMER
+        { .mask = 1 << 0,  .cdev.name =  "d4:green",
+                .cdev.default_trigger = "heartbeat", },
+#endif
+#ifndef CONFIG_LEDS_CPU
+        { .mask = 1 << 1,  .cdev.name =  "d5:green", },         /* !idle */
+#endif
+        { .mask = 1 << 2,  .cdev.name =  "d6:green", },
+        { .mask = 1 << 3,  .cdev.name =  "d7:green", },
+        { .mask = 1 << 4,  .cdev.name =  "d8:green", },
+        { .mask = 1 << 5,  .cdev.name =  "d9:green", },
+        { .mask = 1 << 6,  .cdev.name = "d10:green", },
+        { .mask = 1 << 7,  .cdev.name = "d11:green", },
+        { .mask = 1 << 8,  .cdev.name = "d12:green", },
+        { .mask = 1 << 9,  .cdev.name = "d13:green", },
+        { .mask = 1 << 10, .cdev.name = "d14:green", },
+        { .mask = 1 << 11, .cdev.name = "d15:green", },
+#ifndef CONFIG_LEDS
+        { .mask = 1 << 12, .cdev.name = "d16:green", },
+        { .mask = 1 << 13, .cdev.name = "d17:green", },
+        { .mask = 1 << 14, .cdev.name = "d18:green", },
+        { .mask = 1 << 15, .cdev.name = "d19:green", },
+#endif
+};
+static void
+fpga_led_set(struct led_classdev *cdev, enum led_brightness value)
+{
+        struct dbg_led  *led = container_of(cdev, struct dbg_led, cdev);
+        unsigned long   flags;
+        spin_lock_irqsave(&lock, flags);
+        if (value == LED_OFF)
+                hw_led_state &= ~led->mask;
+        else
+                hw_led_state |= led->mask;
+        __raw_writew(~hw_led_state, &fpga->leds);
+        spin_unlock_irqrestore(&lock, flags);
+}
+static void __init newled_init(struct device *dev)
+{
+        unsigned        i;
+        struct dbg_led  *led;
+        int             status;
+        for (i = 0, led = dbg_leds; i < ARRAY_SIZE(dbg_leds); i++, led++) {
+                led->cdev.brightness_set = fpga_led_set;
+                status = led_classdev_register(dev, &led->cdev);
+                if (status < 0)
+                        break;
+        }
+        return;
+}
+/*-------------------------------------------------------------------------*/
+static int /* __init */ fpga_probe(struct platform_device *pdev)
+{
+        struct resource *iomem;
+        spin_lock_init(&lock);
+        iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!iomem)
+                return -ENODEV;
+        fpga = ioremap(iomem->start, H2P2_DBG_FPGA_SIZE);
+        __raw_writew(~0, &fpga->leds);
+#ifdef  CONFIG_LEDS
+        leds_event = h2p2_dbg_leds_event;
+        leds_event(led_start);
+#endif
+        if (new_led_api()) {
+                newled_init(&pdev->dev);
+        }
+        return 0;
+}
+static int fpga_suspend_late(struct platform_device *pdev, pm_message_t mesg)
+{
+        __raw_writew(~0, &fpga->leds);
+        return 0;
+}
+static int fpga_resume_early(struct platform_device *pdev)
+{
+        __raw_writew(~hw_led_state, &fpga->leds);
+        return 0;
+}
+static struct platform_driver led_driver = {
+        .driver.name    = "omap_dbg_led",
+        .probe          = fpga_probe,
+        .suspend_late   = fpga_suspend_late,
+        .resume_early   = fpga_resume_early,
+};
+static int __init fpga_init(void)
+{
+        if (machine_is_omap_h4()
+                        || machine_is_omap_h3()
+                        || machine_is_omap_h2()
+                        || machine_is_omap_perseus2()
+                        )
+                return platform_driver_register(&led_driver);
+        return 0;
+}
+fs_initcall(fpga_init);
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index eeb33fed6f7c..c5dab1d6417e 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -25,7 +25,71 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/menelaus.h>
-#if     defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
+#if     defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
+#include "../plat-omap/dsp/dsp_common.h"
+static struct dsp_platform_data dsp_pdata = {
+        .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
+};
+static struct resource omap_dsp_resources[] = {
+        {
+                .name   = "dsp_mmu",
+                .start  = -1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device omap_dsp_device = {
+        .name           = "dsp",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(omap_dsp_resources),
+        .resource       = omap_dsp_resources,
+        .dev = {
+                .platform_data = &dsp_pdata,
+        },
+};
+static inline void omap_init_dsp(void)
+{
+        struct resource *res;
+        int irq;
+        if (cpu_is_omap15xx())
+                irq = INT_1510_DSP_MMU;
+        else if (cpu_is_omap16xx())
+                irq = INT_1610_DSP_MMU;
+        else if (cpu_is_omap24xx())
+                irq = INT_24XX_DSP_MMU;
+        res = platform_get_resource_byname(&omap_dsp_device,
+                                           IORESOURCE_IRQ, "dsp_mmu");
+        res->start = irq;
+        platform_device_register(&omap_dsp_device);
+}
+int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
+{
+        static DEFINE_MUTEX(dsp_pdata_lock);
+        mutex_init(&kdev->lock);
+        mutex_lock(&dsp_pdata_lock);
+        list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
+        mutex_unlock(&dsp_pdata_lock);
+        return 0;
+}
+EXPORT_SYMBOL(dsp_kfunc_device_register);
+#else
+static inline void omap_init_dsp(void) { }
+#endif  /* CONFIG_OMAP_DSP */
+/*-------------------------------------------------------------------------*/
+#if     defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
 #define OMAP1_I2C_BASE          0xfffb3800
 #define OMAP2_I2C_BASE1         0x48070000
@@ -48,8 +112,8 @@ static struct resource i2c_resources1[] = {
 /* DMA not used; works around erratum writing to non-empty i2c fifo */
 static struct platform_device omap_i2c_device1 = {
-        .name           = "i2c_omap",
+        .name           = "i2c_omap",
-        .id             = 1,
+        .id             = 1,
        .num_resources  = ARRAY_SIZE(i2c_resources1),
        .resource       = i2c_resources1,
 };
@@ -376,7 +440,7 @@ static inline void omap_init_wdt(void) {}
 /*-------------------------------------------------------------------------*/
-#if     defined(CONFIG_OMAP_RNG) || defined(CONFIG_OMAP_RNG_MODULE)
+#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
 #ifdef CONFIG_ARCH_OMAP24XX
 #define OMAP_RNG_BASE           0x480A0000
@@ -436,6 +500,7 @@ static int __init omap_init_devices(void)
        /* please keep these calls, and their implementations above,
         * in alphabetical order so they're easier to sort through.
         */
+        omap_init_dsp();
        omap_init_i2c();
        omap_init_kp();
        omap_init_mmc();
@@ -446,4 +511,3 @@ static int __init omap_init_devices(void)
        return 0;
 }
 arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index f3f84fbf8b87..2d86b106ff3e 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -925,10 +925,17 @@ static int omap2_dma_handle_ch(int ch)
 {
        u32 status = OMAP_DMA_CSR_REG(ch);
-        if (!status)
+        if (!status) {
+                if (printk_ratelimit())
+                        printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch);
                return 0;
-        if (unlikely(dma_chan[ch].dev_id == -1))
+        }
+        if (unlikely(dma_chan[ch].dev_id == -1)) {
+                if (printk_ratelimit())
+                        printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
+                                        "channel %d\n", status, ch);
                return 0;
+        }
        if (unlikely(status & OMAP_DMA_DROP_IRQ))
                printk(KERN_INFO
                       "DMA synchronization event drop occurred with device "
@@ -959,11 +966,15 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
        int i;
        val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
+        if (val == 0) {
-        for (i = 1; i <= OMAP_LOGICAL_DMA_CH_COUNT; i++) {
+                if (printk_ratelimit())
-                int active = val & (1 << (i - 1));
+                        printk(KERN_WARNING "Spurious DMA IRQ\n");
-                if (active)
+                return IRQ_HANDLED;
-                        omap2_dma_handle_ch(i - 1);
+        }
+        for (i = 0; i < OMAP_LOGICAL_DMA_CH_COUNT && val != 0; i++) {
+                if (val & 1)
+                        omap2_dma_handle_ch(i);
+                val >>= 1;
        }
        return IRQ_HANDLED;
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 659619f235ca..36073dfaa4db 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -372,7 +372,7 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
        /* When the functional clock disappears, too quick writes seem to
         * cause an abort. */
-        __delay(15000);
+        __delay(150000);
 }
 #endif
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index 56acb8720f78..4493bcff5172 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -1,3 +1,26 @@
+/*
+ * File: arch/arm/plat-omap/fb.c
+ *
+ * Framebuffer device registration for TI OMAP platforms
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ * Author: Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -16,6 +39,8 @@
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 static struct omapfb_platform_data omapfb_config;
+static int config_invalid;
+static int configured_regions;
 static u64 omap_fb_dma_mask = ~(u32)0;
@@ -30,39 +55,270 @@ static struct platform_device omap_fb_device = {
        .num_resources = 0,
 };
-/* called from map_io */
+static inline int ranges_overlap(unsigned long start1, unsigned long size1,
-void omapfb_reserve_mem(void)
+                                 unsigned long start2, unsigned long size2)
 {
-        const struct omap_fbmem_config *fbmem_conf;
+        return (start1 >= start2 && start1 < start2 + size2) ||
+               (start2 >= start1 && start2 < start1 + size1);
+}
-        omapfb_config.fbmem.fb_sram_start = omap_fb_sram_start;
+static inline int range_included(unsigned long start1, unsigned long size1,
-        omapfb_config.fbmem.fb_sram_size = omap_fb_sram_size;
+                                 unsigned long start2, unsigned long size2)
+{
+        return start1 >= start2 && start1 + size1 <= start2 + size2;
+}
-        fbmem_conf = omap_get_config(OMAP_TAG_FBMEM, struct omap_fbmem_config);
-        if (fbmem_conf != NULL) {
+/* Check if there is an overlapping region. */
-                /* indicate that the bootloader already initialized the
+static int fbmem_region_reserved(unsigned long start, size_t size)
-                 * fb device, so we'll skip that part in the fb driver
+{
-                 */
+        struct omapfb_mem_region *rg;
-                omapfb_config.fbmem.fb_sdram_start = fbmem_conf->fb_sdram_start;
+        int i;
-                omapfb_config.fbmem.fb_sdram_size = fbmem_conf->fb_sdram_size;
-                if (fbmem_conf->fb_sdram_size) {
+        rg = &omapfb_config.mem_desc.region[0];
-                        pr_info("Reserving %u bytes SDRAM for frame buffer\n",
+        for (i = 0; i < OMAPFB_PLANE_NUM; i++, rg++) {
-                                fbmem_conf->fb_sdram_size);
+                if (!rg->paddr)
-                        reserve_bootmem(fbmem_conf->fb_sdram_start,
+                        /* Empty slot. */
-                                        fbmem_conf->fb_sdram_size);
+                        continue;
+                if (ranges_overlap(start, size, rg->paddr, rg->size))
+                        return 1;
+        }
+        return 0;
+}
+/*
+ * Get the region_idx`th region from board config/ATAG and convert it to
+ * our internal format.
+ */
+static int get_fbmem_region(int region_idx, struct omapfb_mem_region *rg)
+{
+        const struct omap_fbmem_config  *conf;
+        u32                             paddr;
+        conf = omap_get_nr_config(OMAP_TAG_FBMEM,
+                                  struct omap_fbmem_config, region_idx);
+        if (conf == NULL)
+                return -ENOENT;
+        paddr = conf->start;
+        /*
+         * Low bits encode the page allocation mode, if high bits
+         * are zero. Otherwise we need a page aligned fixed
+         * address.
+         */
+        memset(rg, 0, sizeof(*rg));
+        rg->type = paddr & ~PAGE_MASK;
+        rg->paddr = paddr & PAGE_MASK;
+        rg->size = PAGE_ALIGN(conf->size);
+        return 0;
+}
+static int set_fbmem_region_type(struct omapfb_mem_region *rg, int mem_type,
+                                  unsigned long mem_start,
+                                  unsigned long mem_size)
+{
+        /*
+         * Check if the configuration specifies the type explicitly.
+         * type = 0 && paddr = 0, a default don't care case maps to
+         * the SDRAM type.
+         */
+        if (rg->type || (!rg->type && !rg->paddr))
+                return 0;
+        if (ranges_overlap(rg->paddr, rg->size, mem_start, mem_size)) {
+                rg->type = mem_type;
+                return 0;
+        }
+        /* Can't determine it. */
+        return -1;
+}
+static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg,
+                              unsigned long start_avail, unsigned size_avail)
+{
+        unsigned long   paddr = rg->paddr;
+        size_t          size = rg->size;
+        if (rg->type > OMAPFB_MEMTYPE_MAX) {
+                printk(KERN_ERR
+                        "Invalid start address for FB region %d\n", region_idx);
+                return -EINVAL;
+        }
+        if (!rg->size) {
+                printk(KERN_ERR "Zero size for FB region %d\n", region_idx);
+                return -EINVAL;
+        }
+        if (!paddr)
+                /* Allocate this dynamically, leave paddr 0 for now. */
+                return 0;
+        /*
+         * Fixed region for the given RAM range. Check if it's already
+         * reserved by the FB code or someone else.
+         */
+        if (fbmem_region_reserved(paddr, size) ||
+            !range_included(paddr, size, start_avail, size_avail)) {
+                printk(KERN_ERR "Trying to use reserved memory "
+                        "for FB region %d\n", region_idx);
+                return -EINVAL;
+        }
+        return 0;
+}
+/*
+ * Called from map_io. We need to call to this early enough so that we
+ * can reserve the fixed SDRAM regions before VM could get hold of them.
+ */
+void omapfb_reserve_sdram(void)
+{
+        struct bootmem_data     *bdata;
+        unsigned long           sdram_start, sdram_size;
+        unsigned long           reserved;
+        int                     i;
+        if (config_invalid)
+                return;
+        bdata = NODE_DATA(0)->bdata;
+        sdram_start = bdata->node_boot_start;
+        sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
+        reserved = 0;
+        for (i = 0; ; i++) {
+                struct omapfb_mem_region        rg;
+                if (get_fbmem_region(i, &rg) < 0)
+                        break;
+                if (i == OMAPFB_PLANE_NUM) {
+                        printk(KERN_ERR
+                                "Extraneous FB mem configuration entries\n");
+                        config_invalid = 1;
+                        return;
                }
+                /* Check if it's our memory type. */
+                if (set_fbmem_region_type(&rg, OMAPFB_MEMTYPE_SDRAM,
+                                          sdram_start, sdram_size) < 0 ||
+                    (rg.type != OMAPFB_MEMTYPE_SDRAM))
+                        continue;
+                BUG_ON(omapfb_config.mem_desc.region[i].size);
+                if (check_fbmem_region(i, &rg, sdram_start, sdram_size) < 0) {
+                        config_invalid = 1;
+                        return;
+                }
+                if (rg.paddr)
+                        reserve_bootmem(rg.paddr, rg.size);
+                reserved += rg.size;
+                omapfb_config.mem_desc.region[i] = rg;
+                configured_regions++;
        }
+        omapfb_config.mem_desc.region_cnt = i;
+        if (reserved)
+                pr_info("Reserving %lu bytes SDRAM for frame buffer\n",
+                         reserved);
+}
+/*
+ * Called at sram init time, before anything is pushed to the SRAM stack.
+ * Because of the stack scheme, we will allocate everything from the
+ * start of the lowest address region to the end of SRAM. This will also
+ * include padding for page alignment and possible holes between regions.
+ *
+ * As opposed to the SDRAM case, we'll also do any dynamic allocations at
+ * this point, since the driver built as a module would have problem with
+ * freeing / reallocating the regions.
+ */
+unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
+                                  unsigned long sram_vstart,
+                                  unsigned long sram_size,
+                                  unsigned long pstart_avail,
+                                  unsigned long size_avail)
+{
+        struct omapfb_mem_region        rg;
+        unsigned long                   pend_avail;
+        unsigned long                   reserved;
+        int                             i;
+        if (config_invalid)
+                return 0;
+        reserved = 0;
+        pend_avail = pstart_avail + size_avail;
+        for (i = 0; ; i++) {
+                if (get_fbmem_region(i, &rg) < 0)
+                        break;
+                if (i == OMAPFB_PLANE_NUM) {
+                        printk(KERN_ERR
+                                "Extraneous FB mem configuration entries\n");
+                        config_invalid = 1;
+                        return 0;
+                }
+                /* Check if it's our memory type. */
+                if (set_fbmem_region_type(&rg, OMAPFB_MEMTYPE_SRAM,
+                                          sram_pstart, sram_size) < 0 ||
+                    (rg.type != OMAPFB_MEMTYPE_SRAM))
+                        continue;
+                BUG_ON(omapfb_config.mem_desc.region[i].size);
+                if (check_fbmem_region(i, &rg, pstart_avail, size_avail) < 0) {
+                        config_invalid = 1;
+                        return 0;
+                }
+                if (!rg.paddr) {
+                        /* Dynamic allocation */
+                        if ((size_avail & PAGE_MASK) < rg.size) {
+                                printk("Not enough SRAM for FB region %d\n",
+                                        i);
+                                config_invalid = 1;
+                                return 0;
+                        }
+                        size_avail = (size_avail - rg.size) & PAGE_MASK;
+                        rg.paddr = pstart_avail + size_avail;
+                }
+                /* Reserve everything above the start of the region. */
+                if (pend_avail - rg.paddr > reserved)
+                        reserved = pend_avail - rg.paddr;
+                size_avail = pend_avail - reserved - pstart_avail;
+                /*
+                 * We have a kernel mapping for this already, so the
+                 * driver won't have to make one.
+                 */
+                rg.vaddr = (void *)(sram_vstart + rg.paddr - sram_pstart);
+                omapfb_config.mem_desc.region[i] = rg;
+                configured_regions++;
+        }
+        omapfb_config.mem_desc.region_cnt = i;
+        if (reserved)
+                pr_info("Reserving %lu bytes SRAM for frame buffer\n",
+                         reserved);
+        return reserved;
+}
+void omapfb_set_ctrl_platform_data(void *data)
+{
+        omapfb_config.ctrl_platform_data = data;
 }
 static inline int omap_init_fb(void)
 {
        const struct omap_lcd_config *conf;
+        if (config_invalid)
+                return 0;
+        if (configured_regions != omapfb_config.mem_desc.region_cnt) {
+                printk(KERN_ERR "Invalid FB mem configuration entries\n");
+                return 0;
+        }
        conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
-        if (conf == NULL)
+        if (conf == NULL) {
+                if (configured_regions)
+                        /* FB mem config, but no LCD config? */
+                        printk(KERN_ERR "Missing LCD configuration\n");
                return 0;
+        }
        omapfb_config.lcd = *conf;
        return platform_device_register(&omap_fb_device);
@@ -72,7 +328,16 @@ arch_initcall(omap_init_fb);
 #else
-void omapfb_reserve_mem(void) {}
+void omapfb_reserve_sdram(void) {}
+unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
+                                  unsigned long sram_vstart,
+                                  unsigned long sram_size,
+                                  unsigned long start_avail,
+                                  unsigned long size_avail)
+{
+        return 0;
+}
 #endif
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 9dc6d3617bdb..337455dfe64d 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -13,7 +13,6 @@
 #include <linux/init.h>
 #include <linux/module.h>
-#include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/sysdev.h>
 #include <linux/err.h>
@@ -1545,7 +1544,7 @@ void omap2_gpio_resume_after_retention(void)
 * This may get called early from board specific init
 * for boards that have interrupts routed via FPGA.
 */
-int omap_gpio_init(void)
+int __init omap_gpio_init(void)
 {
        if (!initialized)
                return _omap_gpio_init();
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
new file mode 100644
index 000000000000..de7e6ef48bd0
--- /dev/null
+++ b/arch/arm/plat-omap/mailbox.c
@@ -0,0 +1,509 @@
+/*
+ * OMAP mailbox driver
+ *
+ * Copyright (C) 2006 Nokia Corporation. All rights reserved.
+ *
+ * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
+ *              Restructured by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/blkdev.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/arch/mailbox.h>
+#include "mailbox.h"
+static struct omap_mbox *mboxes;
+static DEFINE_RWLOCK(mboxes_lock);
+/* Mailbox Sequence Bit function */
+void omap_mbox_init_seq(struct omap_mbox *mbox)
+{
+        mbox_seq_init(mbox);
+}
+EXPORT_SYMBOL(omap_mbox_init_seq);
+/*
+ * message sender
+ */
+static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg, void *arg)
+{
+        int ret = 0, i = 1000;
+        while (mbox_fifo_full(mbox)) {
+                if (mbox->ops->type == OMAP_MBOX_TYPE2)
+                        return -1;
+                if (--i == 0)
+                        return -1;
+                udelay(1);
+        }
+        if (arg && mbox->txq->callback) {
+                ret = mbox->txq->callback(arg);
+                if (ret)
+                        goto out;
+        }
+        mbox_seq_toggle(mbox, &msg);
+        mbox_fifo_write(mbox, msg);
+ out:
+        return ret;
+}
+int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg, void* arg)
+{
+        struct request *rq;
+        struct request_queue *q = mbox->txq->queue;
+        int ret = 0;
+        rq = blk_get_request(q, WRITE, GFP_ATOMIC);
+        if (unlikely(!rq)) {
+                ret = -ENOMEM;
+                goto fail;
+        }
+        rq->data = (void *)msg;
+        blk_insert_request(q, rq, 0, arg);
+        schedule_work(&mbox->txq->work);
+ fail:
+        return ret;
+}
+EXPORT_SYMBOL(omap_mbox_msg_send);
+static void mbox_tx_work(struct work_struct *work)
+{
+        int ret;
+        struct request *rq;
+        struct omap_mbox_queue *mq = container_of(work,
+                                struct omap_mbox_queue, work);
+        struct omap_mbox *mbox = mq->queue->queuedata;
+        struct request_queue *q = mbox->txq->queue;
+        while (1) {
+                spin_lock(q->queue_lock);
+                rq = elv_next_request(q);
+                spin_unlock(q->queue_lock);
+                if (!rq)
+                        break;
+                ret = __mbox_msg_send(mbox, (mbox_msg_t) rq->data, rq->special);
+                if (ret) {
+                        enable_mbox_irq(mbox, IRQ_TX);
+                        return;
+                }
+                spin_lock(q->queue_lock);
+                blkdev_dequeue_request(rq);
+                end_that_request_last(rq, 0);
+                spin_unlock(q->queue_lock);
+        }
+}
+/*
+ * Message receiver(workqueue)
+ */
+static void mbox_rx_work(struct work_struct *work)
+{
+        struct omap_mbox_queue *mq =
+                        container_of(work, struct omap_mbox_queue, work);
+        struct omap_mbox *mbox = mq->queue->queuedata;
+        struct request_queue *q = mbox->rxq->queue;
+        struct request *rq;
+        mbox_msg_t msg;
+        unsigned long flags;
+        if (mbox->rxq->callback == NULL) {
+                sysfs_notify(&mbox->dev.kobj, NULL, "mbox");
+                return;
+        }
+        while (1) {
+                spin_lock_irqsave(q->queue_lock, flags);
+                rq = elv_next_request(q);
+                spin_unlock_irqrestore(q->queue_lock, flags);
+                if (!rq)
+                        break;
+                msg = (mbox_msg_t) rq->data;
+                spin_lock_irqsave(q->queue_lock, flags);
+                blkdev_dequeue_request(rq);
+                end_that_request_last(rq, 0);
+                spin_unlock_irqrestore(q->queue_lock, flags);
+                mbox->rxq->callback((void *)msg);
+        }
+}
+/*
+ * Mailbox interrupt handler
+ */
+static void mbox_txq_fn(request_queue_t * q)
+{
+}
+static void mbox_rxq_fn(request_queue_t * q)
+{
+}
+static void __mbox_tx_interrupt(struct omap_mbox *mbox)
+{
+        disable_mbox_irq(mbox, IRQ_TX);
+        ack_mbox_irq(mbox, IRQ_TX);
+        schedule_work(&mbox->txq->work);
+}
+static void __mbox_rx_interrupt(struct omap_mbox *mbox)
+{
+        struct request *rq;
+        mbox_msg_t msg;
+        request_queue_t *q = mbox->rxq->queue;
+        disable_mbox_irq(mbox, IRQ_RX);
+        while (!mbox_fifo_empty(mbox)) {
+                rq = blk_get_request(q, WRITE, GFP_ATOMIC);
+                if (unlikely(!rq))
+                        goto nomem;
+                msg = mbox_fifo_read(mbox);
+                rq->data = (void *)msg;
+                if (unlikely(mbox_seq_test(mbox, msg))) {
+                        pr_info("mbox: Illegal seq bit!(%08x)\n", msg);
+                        if (mbox->err_notify)
+                                mbox->err_notify();
+                }
+                blk_insert_request(q, rq, 0, NULL);
+                if (mbox->ops->type == OMAP_MBOX_TYPE1)
+                        break;
+        }
+        /* no more messages in the fifo. clear IRQ source. */
+        ack_mbox_irq(mbox, IRQ_RX);
+        enable_mbox_irq(mbox, IRQ_RX);
+        nomem:
+        schedule_work(&mbox->rxq->work);
+}
+static irqreturn_t mbox_interrupt(int irq, void *p)
+{
+        struct omap_mbox *mbox = (struct omap_mbox *)p;
+        if (is_mbox_irq(mbox, IRQ_TX))
+                __mbox_tx_interrupt(mbox);
+        if (is_mbox_irq(mbox, IRQ_RX))
+                __mbox_rx_interrupt(mbox);
+        return IRQ_HANDLED;
+}
+/*
+ * sysfs files
+ */
+static ssize_t
+omap_mbox_write(struct device *dev, struct device_attribute *attr,
+                const char * buf, size_t count)
+{
+        int ret;
+        mbox_msg_t *p = (mbox_msg_t *)buf;
+        struct omap_mbox *mbox = dev_get_drvdata(dev);
+        for (; count >= sizeof(mbox_msg_t); count -= sizeof(mbox_msg_t)) {
+                ret = omap_mbox_msg_send(mbox, be32_to_cpu(*p), NULL);
+                if (ret)
+                        return -EAGAIN;
+                p++;
+        }
+        return (size_t)((char *)p - buf);
+}
+static ssize_t
+omap_mbox_read(struct device *dev, struct device_attribute *attr, char *buf)
+{
+        unsigned long flags;
+        struct request *rq;
+        mbox_msg_t *p = (mbox_msg_t *) buf;
+        struct omap_mbox *mbox = dev_get_drvdata(dev);
+        struct request_queue *q = mbox->rxq->queue;
+        while (1) {
+                spin_lock_irqsave(q->queue_lock, flags);
+                rq = elv_next_request(q);
+                spin_unlock_irqrestore(q->queue_lock, flags);
+                if (!rq)
+                        break;
+                *p = (mbox_msg_t) rq->data;
+                spin_lock_irqsave(q->queue_lock, flags);
+                blkdev_dequeue_request(rq);
+                end_that_request_last(rq, 0);
+                spin_unlock_irqrestore(q->queue_lock, flags);
+                if (unlikely(mbox_seq_test(mbox, *p))) {
+                        pr_info("mbox: Illegal seq bit!(%08x) ignored\n", *p);
+                        continue;
+                }
+                p++;
+        }
+        pr_debug("%02x %02x %02x %02x\n", buf[0], buf[1], buf[2], buf[3]);
+        return (size_t) ((char *)p - buf);
+}
+static DEVICE_ATTR(mbox, S_IRUGO | S_IWUSR, omap_mbox_read, omap_mbox_write);
+static ssize_t mbox_show(struct class *class, char *buf)
+{
+        return sprintf(buf, "mbox");
+}
+static CLASS_ATTR(mbox, S_IRUGO, mbox_show, NULL);
+static struct class omap_mbox_class = {
+        .name = "omap_mbox",
+};
+static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
+                                        request_fn_proc * proc,
+                                        void (*work) (struct work_struct *))
+{
+        request_queue_t *q;
+        struct omap_mbox_queue *mq;
+        mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
+        if (!mq)
+                return NULL;
+        spin_lock_init(&mq->lock);
+        q = blk_init_queue(proc, &mq->lock);
+        if (!q)
+                goto error;
+        q->queuedata = mbox;
+        mq->queue = q;
+        INIT_WORK(&mq->work, work);
+        return mq;
+error:
+        kfree(mq);
+        return NULL;
+}
+static void mbox_queue_free(struct omap_mbox_queue *q)
+{
+        blk_cleanup_queue(q->queue);
+        kfree(q);
+}
+static int omap_mbox_init(struct omap_mbox *mbox)
+{
+        int ret;
+        struct omap_mbox_queue *mq;
+        if (likely(mbox->ops->startup)) {
+                ret = mbox->ops->startup(mbox);
+                if (unlikely(ret))
+                        return ret;
+        }
+        mbox->dev.class = &omap_mbox_class;
+        strlcpy(mbox->dev.bus_id, mbox->name, KOBJ_NAME_LEN);
+        dev_set_drvdata(&mbox->dev, mbox);
+        ret = device_register(&mbox->dev);
+        if (unlikely(ret))
+                goto fail_device_reg;
+        ret = device_create_file(&mbox->dev, &dev_attr_mbox);
+        if (unlikely(ret)) {
+                printk(KERN_ERR
+                        "device_create_file failed: %d\n", ret);
+                goto fail_create_mbox;
+        }
+        ret = request_irq(mbox->irq, mbox_interrupt, IRQF_DISABLED,
+                                mbox->name, mbox);
+        if (unlikely(ret)) {
+                printk(KERN_ERR
+                        "failed to register mailbox interrupt:%d\n", ret);
+                goto fail_request_irq;
+        }
+        enable_mbox_irq(mbox, IRQ_RX);
+        mq = mbox_queue_alloc(mbox, mbox_txq_fn, mbox_tx_work);
+        if (!mq) {
+                ret = -ENOMEM;
+                goto fail_alloc_txq;
+        }
+        mbox->txq = mq;
+        mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work);
+        if (!mq) {
+                ret = -ENOMEM;
+                goto fail_alloc_rxq;
+        }
+        mbox->rxq = mq;
+        return 0;
+ fail_alloc_rxq:
+        mbox_queue_free(mbox->txq);
+ fail_alloc_txq:
+        free_irq(mbox->irq, mbox);
+ fail_request_irq:
+        device_remove_file(&mbox->dev, &dev_attr_mbox);
+ fail_create_mbox:
+        device_unregister(&mbox->dev);
+ fail_device_reg:
+        if (unlikely(mbox->ops->shutdown))
+                mbox->ops->shutdown(mbox);
+        return ret;
+}
+static void omap_mbox_fini(struct omap_mbox *mbox)
+{
+        mbox_queue_free(mbox->txq);
+        mbox_queue_free(mbox->rxq);
+        free_irq(mbox->irq, mbox);
+        device_remove_file(&mbox->dev, &dev_attr_mbox);
+        class_unregister(&omap_mbox_class);
+        if (unlikely(mbox->ops->shutdown))
+                mbox->ops->shutdown(mbox);
+}
+static struct omap_mbox **find_mboxes(const char *name)
+{
+        struct omap_mbox **p;
+        for (p = &mboxes; *p; p = &(*p)->next) {
+                if (strcmp((*p)->name, name) == 0)
+                        break;
+        }
+        return p;
+}
+struct omap_mbox *omap_mbox_get(const char *name)
+{
+        struct omap_mbox *mbox;
+        int ret;
+        read_lock(&mboxes_lock);
+        mbox = *(find_mboxes(name));
+        if (mbox == NULL) {
+                read_unlock(&mboxes_lock);
+                return ERR_PTR(-ENOENT);
+        }
+        read_unlock(&mboxes_lock);
+        ret = omap_mbox_init(mbox);
+        if (ret)
+                return ERR_PTR(-ENODEV);
+        return mbox;
+}
+EXPORT_SYMBOL(omap_mbox_get);
+void omap_mbox_put(struct omap_mbox *mbox)
+{
+        omap_mbox_fini(mbox);
+}
+EXPORT_SYMBOL(omap_mbox_put);
+int omap_mbox_register(struct omap_mbox *mbox)
+{
+        int ret = 0;
+        struct omap_mbox **tmp;
+        if (!mbox)
+                return -EINVAL;
+        if (mbox->next)
+                return -EBUSY;
+        write_lock(&mboxes_lock);
+        tmp = find_mboxes(mbox->name);
+        if (*tmp)
+                ret = -EBUSY;
+        else
+                *tmp = mbox;
+        write_unlock(&mboxes_lock);
+        return ret;
+}
+EXPORT_SYMBOL(omap_mbox_register);
+int omap_mbox_unregister(struct omap_mbox *mbox)
+{
+        struct omap_mbox **tmp;
+        write_lock(&mboxes_lock);
+        tmp = &mboxes;
+        while (*tmp) {
+                if (mbox == *tmp) {
+                        *tmp = mbox->next;
+                        mbox->next = NULL;
+                        write_unlock(&mboxes_lock);
+                        return 0;
+                }
+                tmp = &(*tmp)->next;
+        }
+        write_unlock(&mboxes_lock);
+        return -EINVAL;
+}
+EXPORT_SYMBOL(omap_mbox_unregister);
+static int __init omap_mbox_class_init(void)
+{
+        int ret = class_register(&omap_mbox_class);
+        if (!ret)
+                ret = class_create_file(&omap_mbox_class, &class_attr_mbox);
+        return ret;
+}
+static void __exit omap_mbox_class_exit(void)
+{
+        class_remove_file(&omap_mbox_class, &class_attr_mbox);
+        class_unregister(&omap_mbox_class);
+}
+subsys_initcall(omap_mbox_class_init);
+module_exit(omap_mbox_class_exit);
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-omap/mailbox.h b/arch/arm/plat-omap/mailbox.h
new file mode 100644
index 000000000000..67c6740b8ad5
--- /dev/null
+++ b/arch/arm/plat-omap/mailbox.h
@@ -0,0 +1,100 @@
+/*
+ * Mailbox internal functions
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ARCH_ARM_PLAT_MAILBOX_H
+#define __ARCH_ARM_PLAT_MAILBOX_H
+/*
+ * Mailbox sequence bit API
+ */
+#if defined(CONFIG_ARCH_OMAP1)
+#  define MBOX_USE_SEQ_BIT
+#elif defined(CONFIG_ARCH_OMAP2)
+#  define MBOX_USE_SEQ_BIT
+#endif
+#ifdef MBOX_USE_SEQ_BIT
+/* seq_rcv should be initialized with any value other than
+ * 0 and 1 << 31, to allow either value for the first
+ * message.  */
+static inline void mbox_seq_init(struct omap_mbox *mbox)
+{
+        /* any value other than 0 and 1 << 31 */
+        mbox->seq_rcv = 0xffffffff;
+}
+static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg)
+{
+        /* add seq_snd to msg */
+        *msg = (*msg & 0x7fffffff) | mbox->seq_snd;
+        /* flip seq_snd */
+        mbox->seq_snd ^= 1 << 31;
+}
+static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg)
+{
+        mbox_msg_t seq = msg & (1 << 31);
+        if (seq == mbox->seq_rcv)
+                return -1;
+        mbox->seq_rcv = seq;
+        return 0;
+}
+#else
+static inline void mbox_seq_init(struct omap_mbox *mbox)
+{
+}
+static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg)
+{
+}
+static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg)
+{
+        return 0;
+}
+#endif
+/* Mailbox FIFO handle functions */
+static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
+{
+        return mbox->ops->fifo_read(mbox);
+}
+static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
+{
+        mbox->ops->fifo_write(mbox, msg);
+}
+static inline int mbox_fifo_empty(struct omap_mbox *mbox)
+{
+        return mbox->ops->fifo_empty(mbox);
+}
+static inline int mbox_fifo_full(struct omap_mbox *mbox)
+{
+        return mbox->ops->fifo_full(mbox);
+}
+/* Mailbox IRQ handle functions */
+static inline void enable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
+{
+        mbox->ops->enable_irq(mbox, irq);
+}
+static inline void disable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
+{
+        mbox->ops->disable_irq(mbox, irq);
+}
+static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
+{
+        if (mbox->ops->ack_irq)
+                mbox->ops->ack_irq(mbox, irq);
+}
+static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
+{
+        return mbox->ops->is_irq(mbox, irq);
+}
+#endif                          /* __ARCH_ARM_PLAT_MAILBOX_H */
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 19014b2ff4c6..bc46f33aede3 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -46,14 +46,19 @@
 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
+static unsigned long omap_sram_start;
 static unsigned long omap_sram_base;
 static unsigned long omap_sram_size;
 static unsigned long omap_sram_ceil;
-unsigned long omap_fb_sram_start;
+extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
-unsigned long omap_fb_sram_size;
+                                         unsigned long sram_vstart,
+                                         unsigned long sram_size,
+                                         unsigned long pstart_avail,
+                                         unsigned long size_avail);
-/* Depending on the target RAMFS firewall setup, the public usable amount of
+/*
+ * Depending on the target RAMFS firewall setup, the public usable amount of
 * SRAM varies.  The default accessable size for all device types is 2k. A GP
 * device allows ARM11 but not other initators for full size. This
 * functionality seems ok until some nice security API happens.
@@ -77,32 +82,6 @@ static int is_sram_locked(void)
                return 1; /* assume locked with no PPA or security driver */
 }
-void get_fb_sram_conf(unsigned long start_avail, unsigned size_avail,
-                      unsigned long *start, unsigned long *size)
-{
-        const struct omap_fbmem_config *fbmem_conf;
-        fbmem_conf = omap_get_config(OMAP_TAG_FBMEM, struct omap_fbmem_config);
-        if (fbmem_conf != NULL) {
-                *start = fbmem_conf->fb_sram_start;
-                *size = fbmem_conf->fb_sram_size;
-        } else {
-                *size = 0;
-                *start = 0;
-        }
-        if (*size && (
-            *start < start_avail ||
-            *start + *size > start_avail + size_avail)) {
-                printk(KERN_ERR "invalid FB SRAM configuration\n");
-                *start = start_avail;
-                *size = size_avail;
-        }
-        if (*size)
-                pr_info("Reserving %lu bytes SRAM for frame buffer\n", *size);
-}
 /*
 * The amount of SRAM depends on the core type.
 * Note that we cannot try to test for SRAM here because writes
@@ -111,16 +90,16 @@ void get_fb_sram_conf(unsigned long start_avail, unsigned size_avail,
 */
 void __init omap_detect_sram(void)
 {
-        unsigned long sram_start;
+        unsigned long reserved;
        if (cpu_is_omap24xx()) {
                if (is_sram_locked()) {
                        omap_sram_base = OMAP2_SRAM_PUB_VA;
-                        sram_start = OMAP2_SRAM_PUB_PA;
+                        omap_sram_start = OMAP2_SRAM_PUB_PA;
                        omap_sram_size = 0x800; /* 2K */
                } else {
                        omap_sram_base = OMAP2_SRAM_VA;
-                        sram_start = OMAP2_SRAM_PA;
+                        omap_sram_start = OMAP2_SRAM_PA;
                        if (cpu_is_omap242x())
                                omap_sram_size = 0xa0000; /* 640K */
                        else if (cpu_is_omap243x())
@@ -128,7 +107,7 @@ void __init omap_detect_sram(void)
                }
        } else {
                omap_sram_base = OMAP1_SRAM_VA;
-                sram_start = OMAP1_SRAM_PA;
+                omap_sram_start = OMAP1_SRAM_PA;
                if (cpu_is_omap730())
                        omap_sram_size = 0x32000;       /* 200K */
@@ -144,12 +123,11 @@ void __init omap_detect_sram(void)
                        omap_sram_size = 0x4000;
                }
        }
-        get_fb_sram_conf(sram_start + SRAM_BOOTLOADER_SZ,
+        reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
-                         omap_sram_size - SRAM_BOOTLOADER_SZ,
+                                       omap_sram_size,
-                         &omap_fb_sram_start, &omap_fb_sram_size);
+                                       omap_sram_start + SRAM_BOOTLOADER_SZ,
-        if (omap_fb_sram_size)
+                                       omap_sram_size - SRAM_BOOTLOADER_SZ);
-                omap_sram_size -= sram_start + omap_sram_size -
+        omap_sram_size -= reserved;
-                                  omap_fb_sram_start;
        omap_sram_ceil = omap_sram_base + omap_sram_size;
 }
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 7e8096809be2..25489aafb113 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -37,9 +37,27 @@
 #include <asm/arch/usb.h>
 #include <asm/arch/board.h>
+#ifdef CONFIG_ARCH_OMAP1
+#define INT_USB_IRQ_GEN         IH2_BASE + 20
+#define INT_USB_IRQ_NISO        IH2_BASE + 30
+#define INT_USB_IRQ_ISO         IH2_BASE + 29
+#define INT_USB_IRQ_HGEN        INT_USB_HHC_1
+#define INT_USB_IRQ_OTG         IH2_BASE + 8
+#else
+#define INT_USB_IRQ_GEN         INT_24XX_USB_IRQ_GEN
+#define INT_USB_IRQ_NISO        INT_24XX_USB_IRQ_NISO
+#define INT_USB_IRQ_ISO         INT_24XX_USB_IRQ_ISO
+#define INT_USB_IRQ_HGEN        INT_24XX_USB_IRQ_HGEN
+#define INT_USB_IRQ_OTG         INT_24XX_USB_IRQ_OTG
+#endif
 /* These routines should handle the standard chip-specific modes
 * for usb0/1/2 ports, covering basic mux and transceiver setup.
- * Call omap_usb_init() once, from INIT_MACHINE().
 *
 * Some board-*.c files will need to set up additional mux options,
 * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
@@ -96,19 +114,26 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 {
        u32     syscon1 = 0;
+        if (cpu_is_omap24xx())
+                CONTROL_DEVCONF_REG &= ~USBT0WRMODEI(USB_BIDIR_TLL);
        if (nwires == 0) {
-                if (!cpu_is_omap15xx()) {
+                if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
                        /* pulldown D+/D- */
                        USB_TRANSCEIVER_CTRL_REG &= ~(3 << 1);
                }
                return 0;
        }
-        if (is_device)
+        if (is_device) {
-                omap_cfg_reg(W4_USB_PUEN);
+                if (cpu_is_omap24xx())
+                        omap_cfg_reg(J20_24XX_USB0_PUEN);
+                else
+                        omap_cfg_reg(W4_USB_PUEN);
+        }
-        /* internal transceiver */
+        /* internal transceiver (unavailable on 17xx, 24xx) */
-        if (nwires == 2) {
+        if (!cpu_class_is_omap2() && nwires == 2) {
                // omap_cfg_reg(P9_USB_DP);
                // omap_cfg_reg(R8_USB_DM);
@@ -136,29 +161,50 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
                return 0;
        }
-        omap_cfg_reg(V6_USB0_TXD);
+        if (cpu_is_omap24xx()) {
-        omap_cfg_reg(W9_USB0_TXEN);
+                omap_cfg_reg(K18_24XX_USB0_DAT);
-        omap_cfg_reg(W5_USB0_SE0);
+                omap_cfg_reg(K19_24XX_USB0_TXEN);
+                omap_cfg_reg(J14_24XX_USB0_SE0);
+                if (nwires != 3)
+                        omap_cfg_reg(J18_24XX_USB0_RCV);
+        } else {
+                omap_cfg_reg(V6_USB0_TXD);
+                omap_cfg_reg(W9_USB0_TXEN);
+                omap_cfg_reg(W5_USB0_SE0);
+                if (nwires != 3)
+                        omap_cfg_reg(Y5_USB0_RCV);
+        }
-        /* NOTE:  SPEED and SUSP aren't configured here */
+        /* NOTE:  SPEED and SUSP aren't configured here.  OTG hosts
+         * may be able to use I2C requests to set those bits along
+         * with VBUS switching and overcurrent detction.
+         */
-        if (nwires != 3)
+        if (cpu_class_is_omap1() && nwires != 6)
-                omap_cfg_reg(Y5_USB0_RCV);
-        if (nwires != 6)
                USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
        switch (nwires) {
        case 3:
                syscon1 = 2;
+                if (cpu_is_omap24xx())
+                        CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR);
                break;
        case 4:
                syscon1 = 1;
+                if (cpu_is_omap24xx())
+                        CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR);
                break;
        case 6:
                syscon1 = 3;
-                omap_cfg_reg(AA9_USB0_VP);
+                if (cpu_is_omap24xx()) {
-                omap_cfg_reg(R9_USB0_VM);
+                        omap_cfg_reg(J19_24XX_USB0_VP);
-                USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+                        omap_cfg_reg(K20_24XX_USB0_VM);
+                        CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_UNIDIR);
+                } else {
+                        omap_cfg_reg(AA9_USB0_VP);
+                        omap_cfg_reg(R9_USB0_VM);
+                        USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+                }
                break;
        default:
                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
@@ -171,14 +217,22 @@ static u32 __init omap_usb1_init(unsigned nwires)
 {
        u32     syscon1 = 0;
-        if (nwires != 6 && !cpu_is_omap15xx())
+        if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
                USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
+        if (cpu_is_omap24xx())
+                CONTROL_DEVCONF_REG &= ~USBT1WRMODEI(USB_BIDIR_TLL);
        if (nwires == 0)
                return 0;
        /* external transceiver */
-        omap_cfg_reg(USB1_TXD);
+        if (cpu_class_is_omap1()) {
-        omap_cfg_reg(USB1_TXEN);
+                omap_cfg_reg(USB1_TXD);
+                omap_cfg_reg(USB1_TXEN);
+                if (nwires != 3)
+                        omap_cfg_reg(USB1_RCV);
+        }
        if (cpu_is_omap15xx()) {
                omap_cfg_reg(USB1_SEO);
                omap_cfg_reg(USB1_SPEED);
@@ -190,20 +244,38 @@ static u32 __init omap_usb1_init(unsigned nwires)
        } else if (cpu_is_omap1710()) {
                omap_cfg_reg(R13_1710_USB1_SE0);
                // SUSP
+        } else if (cpu_is_omap24xx()) {
+                /* NOTE:  board-specific code must set up pin muxing for usb1,
+                 * since each signal could come out on either of two balls.
+                 */
        } else {
-                pr_debug("usb unrecognized\n");
+                pr_debug("usb%d cpu unrecognized\n", 1);
+                return 0;
        }
-        if (nwires != 3)
-                omap_cfg_reg(USB1_RCV);
        switch (nwires) {
+        case 2:
+                if (!cpu_is_omap24xx())
+                        goto bad;
+                /* NOTE: board-specific code must override this setting if
+                 * this TLL link is not using DP/DM
+                 */
+                syscon1 = 1;
+                CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR_TLL);
+                break;
        case 3:
                syscon1 = 2;
+                if (cpu_is_omap24xx())
+                        CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR);
                break;
        case 4:
                syscon1 = 1;
+                if (cpu_is_omap24xx())
+                        CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR);
                break;
        case 6:
+                if (cpu_is_omap24xx())
+                        goto bad;
                syscon1 = 3;
                omap_cfg_reg(USB1_VP);
                omap_cfg_reg(USB1_VM);
@@ -211,6 +283,7 @@ static u32 __init omap_usb1_init(unsigned nwires)
                        USB_TRANSCEIVER_CTRL_REG |= CONF_USB1_UNI_R;
                break;
        default:
+bad:
                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
                        1, nwires);
        }
@@ -221,10 +294,17 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
 {
        u32     syscon1 = 0;
-        /* NOTE erratum: must leave USB2_UNI_R set if usb0 in use */
+        if (cpu_is_omap24xx()) {
+                CONTROL_DEVCONF_REG &= ~(USBT2WRMODEI(USB_BIDIR_TLL)
+                                        | USBT2TLL5PI);
+                alt_pingroup = 0;
+        }
+        /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
        if (alt_pingroup || nwires == 0)
                return 0;
-        if (nwires != 6 && !cpu_is_omap15xx())
+        if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
                USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
        /* external transceiver */
@@ -242,19 +322,54 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
                if (nwires != 3)
                        omap_cfg_reg(Y5_USB2_RCV);
                // FIXME omap_cfg_reg(USB2_SPEED);
+        } else if (cpu_is_omap24xx()) {
+                omap_cfg_reg(Y11_24XX_USB2_DAT);
+                omap_cfg_reg(AA10_24XX_USB2_SE0);
+                if (nwires > 2)
+                        omap_cfg_reg(AA12_24XX_USB2_TXEN);
+                if (nwires > 3)
+                        omap_cfg_reg(AA6_24XX_USB2_RCV);
        } else {
-                pr_debug("usb unrecognized\n");
+                pr_debug("usb%d cpu unrecognized\n", 1);
+                return 0;
        }
-        // omap_cfg_reg(USB2_SUSP);
+        // if (cpu_class_is_omap1()) omap_cfg_reg(USB2_SUSP);
        switch (nwires) {
+        case 2:
+                if (!cpu_is_omap24xx())
+                        goto bad;
+                /* NOTE: board-specific code must override this setting if
+                 * this TLL link is not using DP/DM
+                 */
+                syscon1 = 1;
+                CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR_TLL);
+                break;
        case 3:
                syscon1 = 2;
+                if (cpu_is_omap24xx())
+                        CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR);
                break;
        case 4:
                syscon1 = 1;
+                if (cpu_is_omap24xx())
+                        CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR);
+                break;
+        case 5:
+                if (!cpu_is_omap24xx())
+                        goto bad;
+                omap_cfg_reg(AA4_24XX_USB2_TLLSE0);
+                /* NOTE: board-specific code must override this setting if
+                 * this TLL link is not using DP/DM.  Something must also
+                 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
+                 */
+                syscon1 = 3;
+                CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_UNIDIR_TLL)
+                                        | USBT2TLL5PI;
                break;
        case 6:
+                if (cpu_is_omap24xx())
+                        goto bad;
                syscon1 = 3;
                if (cpu_is_omap15xx()) {
                        omap_cfg_reg(USB2_VP);
@@ -266,6 +381,7 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
                }
                break;
        default:
+bad:
                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
                        2, nwires);
        }
@@ -294,13 +410,13 @@ static struct resource udc_resources[] = {
                .end            = UDC_BASE + 0xff,
                .flags          = IORESOURCE_MEM,
        }, {            /* general IRQ */
-                .start          = IH2_BASE + 20,
+                .start          = INT_USB_IRQ_GEN,
                .flags          = IORESOURCE_IRQ,
        }, {            /* PIO IRQ */
-                .start          = IH2_BASE + 30,
+                .start          = INT_USB_IRQ_NISO,
                .flags          = IORESOURCE_IRQ,
        }, {            /* SOF IRQ */
-                .start          = IH2_BASE + 29,
+                .start          = INT_USB_IRQ_ISO,
                .flags          = IORESOURCE_IRQ,
        },
 };
@@ -329,11 +445,11 @@ static u64 ohci_dmamask = ~(u32)0;
 static struct resource ohci_resources[] = {
        {
                .start  = OMAP_OHCI_BASE,
-                .end    = OMAP_OHCI_BASE + 4096 - 1,
+                .end    = OMAP_OHCI_BASE + 0xff,
                .flags  = IORESOURCE_MEM,
        },
        {
-                .start  = INT_USB_HHC_1,
+                .start  = INT_USB_IRQ_HGEN,
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -361,7 +477,7 @@ static struct resource otg_resources[] = {
                .end            = OTG_BASE + 0xff,
                .flags          = IORESOURCE_MEM,
        }, {
-                .start          = IH2_BASE + 8,
+                .start          = INT_USB_IRQ_OTG,
                .flags          = IORESOURCE_IRQ,
        },
 };
@@ -385,7 +501,7 @@ static struct platform_device otg_device = {
 // FIXME correct answer depends on hmc_mode,
-// as does any nonzero value for config->otg port number
+// as does (on omap1) any nonzero value for config->otg port number
 #ifdef  CONFIG_USB_GADGET_OMAP
 #define is_usb0_device(config)  1
 #else
@@ -426,12 +542,13 @@ omap_otg_init(struct omap_usb_config *config)
        if (config->otg)
                syscon |= OTG_EN;
 #endif
-        pr_debug("USB_TRANSCEIVER_CTRL_REG = %03x\n", USB_TRANSCEIVER_CTRL_REG);
+        if (cpu_class_is_omap1())
+                pr_debug("USB_TRANSCEIVER_CTRL_REG = %03x\n", USB_TRANSCEIVER_CTRL_REG);
        pr_debug("OTG_SYSCON_2_REG = %08x\n", syscon);
        OTG_SYSCON_2_REG = syscon;
        printk("USB: hmc %d", config->hmc_mode);
-        if (alt_pingroup)
+        if (!alt_pingroup)
                printk(", usb2 alt %d wires", config->pins[2]);
        else if (config->pins[0])
                printk(", usb0 %d wires%s", config->pins[0],
@@ -444,10 +561,12 @@ omap_otg_init(struct omap_usb_config *config)
                printk(", Mini-AB on usb%d", config->otg - 1);
        printk("\n");
-        /* leave USB clocks/controllers off until needed */
+        if (cpu_class_is_omap1()) {
-        ULPD_SOFT_REQ_REG &= ~SOFT_USB_CLK_REQ;
+                /* leave USB clocks/controllers off until needed */
-        ULPD_CLOCK_CTRL_REG &= ~USB_MCLK_EN;
+                ULPD_SOFT_REQ_REG &= ~SOFT_USB_CLK_REQ;
-        ULPD_CLOCK_CTRL_REG |= DIS_USB_PVCI_CLK;
+                ULPD_CLOCK_CTRL_REG &= ~USB_MCLK_EN;
+                ULPD_CLOCK_CTRL_REG |= DIS_USB_PVCI_CLK;
+        }
        syscon = OTG_SYSCON_1_REG;
        syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
@@ -585,7 +704,7 @@ omap_usb_init(void)
        }
        platform_data = *config;
-        if (cpu_is_omap730() || cpu_is_omap16xx())
+        if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx())
                omap_otg_init(&platform_data);
        else if (cpu_is_omap15xx())
                omap_1510_usb_init(&platform_data);
diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h
index a12ac8ab2ad0..802891a9cd81 100644
--- a/include/asm-arm/arch-at91/at91rm9200.h
+++ b/include/asm-arm/arch-at91/at91rm9200.h
@@ -107,185 +107,4 @@
 #define AT91RM9200_UHP_BASE     0x00300000      /* USB Host controller */
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-#define AT91_PA0_MISO           (1 <<  0)       /* A: SPI Master-In Slave-Out */
-#define AT91_PA0_PCK3           (1 <<  0)       /* B: PMC Programmable Clock Output 3 */
-#define AT91_PA1_MOSI           (1 <<  1)       /* A: SPI Master-Out Slave-In */
-#define AT91_PA1_PCK0           (1 <<  1)       /* B: PMC Programmable Clock Output 0 */
-#define AT91_PA2_SPCK           (1 <<  2)       /* A: SPI Serial Clock */
-#define AT91_PA2_IRQ4           (1 <<  2)       /* B: External Interrupt 4 */
-#define AT91_PA3_NPCS0          (1 <<  3)       /* A: SPI Peripheral Chip Select 0 */
-#define AT91_PA3_IRQ5           (1 <<  3)       /* B: External Interrupt 5 */
-#define AT91_PA4_NPCS1          (1 <<  4)       /* A: SPI Peripheral Chip Select 1 */
-#define AT91_PA4_PCK1           (1 <<  4)       /* B: PMC Programmable Clock Output 1 */
-#define AT91_PA5_NPCS2          (1 <<  5)       /* A: SPI Peripheral Chip Select 2 */
-#define AT91_PA5_TXD3           (1 <<  5)       /* B: USART Transmit Data 3 */
-#define AT91_PA6_NPCS3          (1 <<  6)       /* A: SPI Peripheral Chip Select 3 */
-#define AT91_PA6_RXD3           (1 <<  6)       /* B: USART Receive Data 3 */
-#define AT91_PA7_ETXCK_EREFCK   (1 <<  7)       /* A: Ethernet Reference Clock / Transmit Clock */
-#define AT91_PA7_PCK2           (1 <<  7)       /* B: PMC Programmable Clock Output 2 */
-#define AT91_PA8_ETXEN          (1 <<  8)       /* A: Ethernet Transmit Enable */
-#define AT91_PA8_MCCDB          (1 <<  8)       /* B: MMC Multimedia Card B Command */
-#define AT91_PA9_ETX0           (1 <<  9)       /* A: Ethernet Transmit Data 0 */
-#define AT91_PA9_MCDB0          (1 <<  9)       /* B: MMC Multimedia Card B Data 0 */
-#define AT91_PA10_ETX1          (1 << 10)       /* A: Ethernet Transmit Data 1 */
-#define AT91_PA10_MCDB1         (1 << 10)       /* B: MMC Multimedia Card B Data 1 */
-#define AT91_PA11_ECRS_ECRSDV   (1 << 11)       /* A: Ethernet Carrier Sense / Data Valid */
-#define AT91_PA11_MCDB2         (1 << 11)       /* B: MMC Multimedia Card B Data 2 */
-#define AT91_PA12_ERX0          (1 << 12)       /* A: Ethernet Receive Data 0 */
-#define AT91_PA12_MCDB3         (1 << 12)       /* B: MMC Multimedia Card B Data 3 */
-#define AT91_PA13_ERX1          (1 << 13)       /* A: Ethernet Receive Data 1 */
-#define AT91_PA13_TCLK0         (1 << 13)       /* B: TC External Clock Input 0 */
-#define AT91_PA14_ERXER         (1 << 14)       /* A: Ethernet Receive Error */
-#define AT91_PA14_TCLK1         (1 << 14)       /* B: TC External Clock Input 1 */
-#define AT91_PA15_EMDC          (1 << 15)       /* A: Ethernet Management Data Clock */
-#define AT91_PA15_TCLK2         (1 << 15)       /* B: TC External Clock Input 2 */
-#define AT91_PA16_EMDIO         (1 << 16)       /* A: Ethernet Management Data I/O */
-#define AT91_PA16_IRQ6          (1 << 16)       /* B: External Interrupt 6 */
-#define AT91_PA17_TXD0          (1 << 17)       /* A: USART Transmit Data 0 */
-#define AT91_PA17_TIOA0         (1 << 17)       /* B: TC I/O Line A 0 */
-#define AT91_PA18_RXD0          (1 << 18)       /* A: USART Receive Data 0 */
-#define AT91_PA18_TIOB0         (1 << 18)       /* B: TC I/O Line B 0 */
-#define AT91_PA19_SCK0          (1 << 19)       /* A: USART Serial Clock 0 */
-#define AT91_PA19_TIOA1         (1 << 19)       /* B: TC I/O Line A 1 */
-#define AT91_PA20_CTS0          (1 << 20)       /* A: USART Clear To Send 0 */
-#define AT91_PA20_TIOB1         (1 << 20)       /* B: TC I/O Line B 1 */
-#define AT91_PA21_RTS0          (1 << 21)       /* A: USART Ready To Send 0 */
-#define AT91_PA21_TIOA2         (1 << 21)       /* B: TC I/O Line A 2 */
-#define AT91_PA22_RXD2          (1 << 22)       /* A: USART Receive Data 2 */
-#define AT91_PA22_TIOB2         (1 << 22)       /* B: TC I/O Line B 2 */
-#define AT91_PA23_TXD2          (1 << 23)       /* A: USART Transmit Data 2 */
-#define AT91_PA23_IRQ3          (1 << 23)       /* B: External Interrupt 3 */
-#define AT91_PA24_SCK2          (1 << 24)       /* A: USART Serial Clock 2 */
-#define AT91_PA24_PCK1          (1 << 24)       /* B: PMC Programmable Clock Output 1 */
-#define AT91_PA25_TWD           (1 << 25)       /* A: TWI Two-wire Serial Data */
-#define AT91_PA25_IRQ2          (1 << 25)       /* B: External Interrupt 2 */
-#define AT91_PA26_TWCK          (1 << 26)       /* A: TWI Two-wire Serial Clock */
-#define AT91_PA26_IRQ1          (1 << 26)       /* B: External Interrupt 1 */
-#define AT91_PA27_MCCK          (1 << 27)       /* A: MMC Multimedia Card Clock */
-#define AT91_PA27_TCLK3         (1 << 27)       /* B: TC External Clock Input 3 */
-#define AT91_PA28_MCCDA         (1 << 28)       /* A: MMC Multimedia Card A Command */
-#define AT91_PA28_TCLK4         (1 << 28)       /* B: TC External Clock Input 4 */
-#define AT91_PA29_MCDA0         (1 << 29)       /* A: MMC Multimedia Card A Data 0 */
-#define AT91_PA29_TCLK5         (1 << 29)       /* B: TC External Clock Input 5 */
-#define AT91_PA30_DRXD          (1 << 30)       /* A: DBGU Receive Data */
-#define AT91_PA30_CTS2          (1 << 30)       /* B: USART Clear To Send 2 */
-#define AT91_PA31_DTXD          (1 << 31)       /* A: DBGU Transmit Data */
-#define AT91_PA31_RTS2          (1 << 31)       /* B: USART Ready To Send 2 */
-#define AT91_PB0_TF0            (1 <<  0)       /* A: SSC Transmit Frame Sync 0 */
-#define AT91_PB0_RTS3           (1 <<  0)       /* B: USART Ready To Send 3 */
-#define AT91_PB1_TK0            (1 <<  1)       /* A: SSC Transmit Clock 0 */
-#define AT91_PB1_CTS3           (1 <<  1)       /* B: USART Clear To Send 3 */
-#define AT91_PB2_TD0            (1 <<  2)       /* A: SSC Transmit Data 0 */
-#define AT91_PB2_SCK3           (1 <<  2)       /* B: USART Serial Clock 3 */
-#define AT91_PB3_RD0            (1 <<  3)       /* A: SSC Receive Data 0 */
-#define AT91_PB3_MCDA1          (1 <<  3)       /* B: MMC Multimedia Card A Data 1 */
-#define AT91_PB4_RK0            (1 <<  4)       /* A: SSC Receive Clock 0 */
-#define AT91_PB4_MCDA2          (1 <<  4)       /* B: MMC Multimedia Card A Data 2 */
-#define AT91_PB5_RF0            (1 <<  5)       /* A: SSC Receive Frame Sync 0 */
-#define AT91_PB5_MCDA3          (1 <<  5)       /* B: MMC Multimedia Card A Data 3 */
-#define AT91_PB6_TF1            (1 <<  6)       /* A: SSC Transmit Frame Sync 1 */
-#define AT91_PB6_TIOA3          (1 <<  6)       /* B: TC I/O Line A 3 */
-#define AT91_PB7_TK1            (1 <<  7)       /* A: SSC Transmit Clock 1 */
-#define AT91_PB7_TIOB3          (1 <<  7)       /* B: TC I/O Line B 3 */
-#define AT91_PB8_TD1            (1 <<  8)       /* A: SSC Transmit Data 1 */
-#define AT91_PB8_TIOA4          (1 <<  8)       /* B: TC I/O Line A 4 */
-#define AT91_PB9_RD1            (1 <<  9)       /* A: SSC Receive Data 1 */
-#define AT91_PB9_TIOB4          (1 <<  9)       /* B: TC I/O Line B 4 */
-#define AT91_PB10_RK1           (1 << 10)       /* A: SSC Receive Clock 1 */
-#define AT91_PB10_TIOA5         (1 << 10)       /* B: TC I/O Line A 5 */
-#define AT91_PB11_RF1           (1 << 11)       /* A: SSC Receive Frame Sync 1 */
-#define AT91_PB11_TIOB5         (1 << 11)       /* B: TC I/O Line B 5 */
-#define AT91_PB12_TF2           (1 << 12)       /* A: SSC Transmit Frame Sync 2 */
-#define AT91_PB12_ETX2          (1 << 12)       /* B: Ethernet Transmit Data 2 */
-#define AT91_PB13_TK2           (1 << 13)       /* A: SSC Transmit Clock 3 */
-#define AT91_PB13_ETX3          (1 << 13)       /* B: Ethernet Transmit Data 3 */
-#define AT91_PB14_TD2           (1 << 14)       /* A: SSC Transmit Data 2 */
-#define AT91_PB14_ETXER         (1 << 14)       /* B: Ethernet Transmit Coding Error */
-#define AT91_PB15_RD2           (1 << 15)       /* A: SSC Receive Data 2 */
-#define AT91_PB15_ERX2          (1 << 15)       /* B: Ethernet Receive Data 2 */
-#define AT91_PB16_RK2           (1 << 16)       /* A: SSC Receive Clock 2 */
-#define AT91_PB16_ERX3          (1 << 16)       /* B: Ethernet Receive Data 3 */
-#define AT91_PB17_RF2           (1 << 17)       /* A: SSC Receive Frame Sync 2 */
-#define AT91_PB17_ERXDV         (1 << 17)       /* B: Ethernet Receive Data Valid */
-#define AT91_PB18_RI1           (1 << 18)       /* A: USART Ring Indicator 1 */
-#define AT91_PB18_ECOL          (1 << 18)       /* B: Ethernet Collision Detected */
-#define AT91_PB19_DTR1          (1 << 19)       /* A: USART Data Terminal Ready 1 */
-#define AT91_PB19_ERXCK         (1 << 19)       /* B: Ethernet Receive Clock */
-#define AT91_PB20_TXD1          (1 << 20)       /* A: USART Transmit Data 1 */
-#define AT91_PB21_RXD1          (1 << 21)       /* A: USART Receive Data 1 */
-#define AT91_PB22_SCK1          (1 << 22)       /* A: USART Serial Clock 1 */
-#define AT91_PB23_DCD1          (1 << 23)       /* A: USART Data Carrier Detect 1 */
-#define AT91_PB24_CTS1          (1 << 24)       /* A: USART Clear To Send 1 */
-#define AT91_PB25_DSR1          (1 << 25)       /* A: USART Data Set Ready 1 */
-#define AT91_PB25_EF100         (1 << 25)       /* B: Ethernet Force 100 Mbit */
-#define AT91_PB26_RTS1          (1 << 26)       /* A: USART Ready To Send 1 */
-#define AT91_PB27_PCK0          (1 << 27)       /* B: PMC Programmable Clock Output 0 */
-#define AT91_PB28_FIQ           (1 << 28)       /* A: Fast Interrupt */
-#define AT91_PB29_IRQ0          (1 << 29)       /* A: External Interrupt 0 */
-#define AT91_PC0_BFCK           (1 <<  0)       /* A: Burst Flash Clock */
-#define AT91_PC1_BFRDY_SMOE     (1 <<  1)       /* A: Burst Flash Ready / SmartMedia Output Enable */
-#define AT91_PC2_BFAVD          (1 <<  2)       /* A: Burst Flash Address Valid */
-#define AT91_PC3_BFBAA_SMWE     (1 <<  3)       /* A: Burst Flash Address Advance / SmartMedia Write Enable */
-#define AT91_PC4_BFOE           (1 <<  4)       /* A: Burst Flash Output Enable */
-#define AT91_PC5_BFWE           (1 <<  5)       /* A: Burst Flash Write Enable */
-#define AT91_PC6_NWAIT          (1 <<  6)       /* A: SMC Wait Signal */
-#define AT91_PC7_A23            (1 <<  7)       /* A: Address Bus 23 */
-#define AT91_PC8_A24            (1 <<  8)       /* A: Address Bus 24 */
-#define AT91_PC9_A25_CFRNW      (1 <<  9)       /* A: Address Bus 25 / Compact Flash Read Not Write */
-#define AT91_PC10_NCS4_CFCS     (1 << 10)       /* A: SMC Chip Select 4 / Compact Flash Chip Select */
-#define AT91_PC11_NCS5_CFCE1    (1 << 11)       /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */
-#define AT91_PC12_NCS6_CFCE2    (1 << 12)       /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */
-#define AT91_PC13_NCS7          (1 << 13)       /* A: Chip Select 7 */
-#define AT91_PD0_ETX0           (1 <<  0)       /* A: Ethernet Transmit Data 0 */
-#define AT91_PD1_ETX1           (1 <<  1)       /* A: Ethernet Transmit Data 1 */
-#define AT91_PD2_ETX2           (1 <<  2)       /* A: Ethernet Transmit Data 2 */
-#define AT91_PD3_ETX3           (1 <<  3)       /* A: Ethernet Transmit Data 3 */
-#define AT91_PD4_ETXEN          (1 <<  4)       /* A: Ethernet Transmit Enable */
-#define AT91_PD5_ETXER          (1 <<  5)       /* A: Ethernet Transmit Coding Error */
-#define AT91_PD6_DTXD           (1 <<  6)       /* A: DBGU Transmit Data */
-#define AT91_PD7_PCK0           (1 <<  7)       /* A: PMC Programmable Clock Output 0 */
-#define AT91_PD7_TSYNC          (1 <<  7)       /* B: ETM Trace Synchronization Signal */
-#define AT91_PD8_PCK1           (1 <<  8)       /* A: PMC Programmable Clock Output 1 */
-#define AT91_PD8_TCLK           (1 <<  8)       /* B: ETM Trace Clock */
-#define AT91_PD9_PCK2           (1 <<  9)       /* A: PMC Programmable Clock Output 2 */
-#define AT91_PD9_TPS0           (1 <<  9)       /* B: ETM Trace ARM Pipeline Status 0 */
-#define AT91_PD10_PCK3          (1 << 10)       /* A: PMC Programmable Clock Output 3 */
-#define AT91_PD10_TPS1          (1 << 10)       /* B: ETM Trace ARM Pipeline Status 1 */
-#define AT91_PD11_TPS2          (1 << 11)       /* B: ETM Trace ARM Pipeline Status 2 */
-#define AT91_PD12_TPK0          (1 << 12)       /* B: ETM Trace Packet Port 0 */
-#define AT91_PD13_TPK1          (1 << 13)       /* B: ETM Trace Packet Port 1 */
-#define AT91_PD14_TPK2          (1 << 14)       /* B: ETM Trace Packet Port 2 */
-#define AT91_PD15_TD0           (1 << 15)       /* A: SSC Transmit Data 0 */
-#define AT91_PD15_TPK3          (1 << 15)       /* B: ETM Trace Packet Port 3 */
-#define AT91_PD16_TD1           (1 << 16)       /* A: SSC Transmit Data 1 */
-#define AT91_PD16_TPK4          (1 << 16)       /* B: ETM Trace Packet Port 4 */
-#define AT91_PD17_TD2           (1 << 17)       /* A: SSC Transmit Data 2 */
-#define AT91_PD17_TPK5          (1 << 17)       /* B: ETM Trace Packet Port 5 */
-#define AT91_PD18_NPCS1         (1 << 18)       /* A: SPI Peripheral Chip Select 1 */
-#define AT91_PD18_TPK6          (1 << 18)       /* B: ETM Trace Packet Port 6 */
-#define AT91_PD19_NPCS2         (1 << 19)       /* A: SPI Peripheral Chip Select 2 */
-#define AT91_PD19_TPK7          (1 << 19)       /* B: ETM Trace Packet Port 7 */
-#define AT91_PD20_NPCS3         (1 << 20)       /* A: SPI Peripheral Chip Select 3 */
-#define AT91_PD20_TPK8          (1 << 20)       /* B: ETM Trace Packet Port 8 */
-#define AT91_PD21_RTS0          (1 << 21)       /* A: USART Ready To Send 0 */
-#define AT91_PD21_TPK9          (1 << 21)       /* B: ETM Trace Packet Port 9 */
-#define AT91_PD22_RTS1          (1 << 22)       /* A: USART Ready To Send 1 */
-#define AT91_PD22_TPK10         (1 << 22)       /* B: ETM Trace Packet Port 10 */
-#define AT91_PD23_RTS2          (1 << 23)       /* A: USART Ready To Send 2 */
-#define AT91_PD23_TPK11         (1 << 23)       /* B: ETM Trace Packet Port 11 */
-#define AT91_PD24_RTS3          (1 << 24)       /* A: USART Ready To Send 3 */
-#define AT91_PD24_TPK12         (1 << 24)       /* B: ETM Trace Packet Port 12 */
-#define AT91_PD25_DTR1          (1 << 25)       /* A: USART Data Terminal Ready 1 */
-#define AT91_PD25_TPK13         (1 << 25)       /* B: ETM Trace Packet Port 13 */
-#define AT91_PD26_TPK14         (1 << 26)       /* B: ETM Trace Packet Port 14 */
-#define AT91_PD27_TPK15         (1 << 27)       /* B: ETM Trace Packet Port 15 */
-#endif
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index 2cadebc36af7..0427f8698c07 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -117,13 +117,4 @@
 #define AT91SAM9XE_SRAM_BASE    0x00300000      /* Internal SRAM base address */
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-// TODO: Add
-#endif
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h
index 01b58ffe2e27..9eb459570330 100644
--- a/include/asm-arm/arch-at91/at91sam9261.h
+++ b/include/asm-arm/arch-at91/at91sam9261.h
@@ -98,195 +98,4 @@
 #define AT91SAM9261_LCDC_BASE   0x00600000      /* LDC controller */
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-#define AT91_PA0_SPI0_MISO      (1 <<  0)       /* A: SPI0 Master In Slave */
-#define AT91_PA0_MCDA0          (1 <<  0)       /* B: Multimedia Card A Data 0 */
-#define AT91_PA1_SPI0_MOSI      (1 <<  1)       /* A: SPI0 Master Out Slave */
-#define AT91_PA1_MCCDA          (1 <<  1)       /* B: Multimedia Card A Command */
-#define AT91_PA2_SPI0_SPCK      (1 <<  2)       /* A: SPI0 Serial Clock */
-#define AT91_PA2_MCCK           (1 <<  2)       /* B: Multimedia Card Clock */
-#define AT91_PA3_SPI0_NPCS0     (1 <<  3)       /* A: SPI0 Peripheral Chip Select 0 */
-#define AT91_PA4_SPI0_NPCS1     (1 <<  4)       /* A: SPI0 Peripheral Chip Select 1 */
-#define AT91_PA4_MCDA1          (1 <<  4)       /* B: Multimedia Card A Data 1 */
-#define AT91_PA5_SPI0_NPCS2     (1 <<  5)       /* A: SPI0 Peripheral Chip Select 2 */
-#define AT91_PA5_MCDA2          (1 <<  5)       /* B: Multimedia Card A Data 2 */
-#define AT91_PA6_SPI0_NPCS3     (1 <<  6)       /* A: SPI0 Peripheral Chip Select 3 */
-#define AT91_PA6_MCDA3          (1 <<  6)       /* B: Multimedia Card A Data 3 */
-#define AT91_PA7_TWD            (1 <<  7)       /* A: TWI Two-wire Serial Data */
-#define AT91_PA7_PCK0           (1 <<  7)       /* B: PMC Programmable clock Output 0 */
-#define AT91_PA8_TWCK           (1 <<  8)       /* A: TWI Two-wire Serial Clock */
-#define AT91_PA8_PCK1           (1 <<  8)       /* B: PMC Programmable clock Output 1 */
-#define AT91_PA9_DRXD           (1 <<  9)       /* A: DBGU Debug Receive Data */
-#define AT91_PA9_PCK2           (1 <<  9)       /* B: PMC Programmable clock Output 2 */
-#define AT91_PA10_DTXD          (1 << 10)       /* A: DBGU Debug Transmit Data */
-#define AT91_PA10_PCK3          (1 << 10)       /* B: PMC Programmable clock Output 3 */
-#define AT91_PA11_TSYNC         (1 << 11)       /* A: Trace Synchronization Signal */
-#define AT91_PA11_SCK1          (1 << 11)       /* B: USART1 Serial Clock */
-#define AT91_PA12_TCLK          (1 << 12)       /* A: Trace Clock */
-#define AT91_PA12_RTS1          (1 << 12)       /* B: USART1 Ready To Send */
-#define AT91_PA13_TPS0          (1 << 13)       /* A: Trace ARM Pipeline Status 0 */
-#define AT91_PA13_CTS1          (1 << 13)       /* B: USART1 Clear To Send */
-#define AT91_PA14_TPS1          (1 << 14)       /* A: Trace ARM Pipeline Status 1 */
-#define AT91_PA14_SCK2          (1 << 14)       /* B: USART2 Serial Clock */
-#define AT91_PA15_TPS2          (1 << 15)       /* A: Trace ARM Pipeline Status 2 */
-#define AT91_PA15_RTS2          (1 << 15)       /* B: USART2 Ready To Send */
-#define AT91_PA16_TPK0          (1 << 16)       /* A: Trace Packet Port 0 */
-#define AT91_PA16_CTS2          (1 << 16)       /* B: USART2 Clear To Send */
-#define AT91_PA17_TPK1          (1 << 17)       /* A: Trace Packet Port 1 */
-#define AT91_PA17_TF1           (1 << 17)       /* B: SSC1 Transmit Frame Sync */
-#define AT91_PA18_TPK2          (1 << 18)       /* A: Trace Packet Port 2 */
-#define AT91_PA18_TK1           (1 << 18)       /* B: SSC1 Transmit Clock */
-#define AT91_PA19_TPK3          (1 << 19)       /* A: Trace Packet Port 3 */
-#define AT91_PA19_TD1           (1 << 19)       /* B: SSC1 Transmit Data */
-#define AT91_PA20_TPK4          (1 << 20)       /* A: Trace Packet Port 4 */
-#define AT91_PA20_RD1           (1 << 20)       /* B: SSC1 Receive Data */
-#define AT91_PA21_TPK5          (1 << 21)       /* A: Trace Packet Port 5 */
-#define AT91_PA21_RK1           (1 << 21)       /* B: SSC1 Receive Clock */
-#define AT91_PA22_TPK6          (1 << 22)       /* A: Trace Packet Port 6 */
-#define AT91_PA22_RF1           (1 << 22)       /* B: SSC1 Receive Frame Sync */
-#define AT91_PA23_TPK7          (1 << 23)       /* A: Trace Packet Port 7 */
-#define AT91_PA23_RTS0          (1 << 23)       /* B: USART0 Ready To Send */
-#define AT91_PA24_TPK8          (1 << 24)       /* A: Trace Packet Port 8 */
-#define AT91_PA24_SPI1_NPCS1    (1 << 24)       /* B: SPI1 Peripheral Chip Select 1 */
-#define AT91_PA25_TPK9          (1 << 25)       /* A: Trace Packet Port 9 */
-#define AT91_PA25_SPI1_NPCS2    (1 << 25)       /* B: SPI1 Peripheral Chip Select 2 */
-#define AT91_PA26_TPK10         (1 << 26)       /* A: Trace Packet Port 10 */
-#define AT91_PA26_SPI1_NPCS3    (1 << 26)       /* B: SPI1 Peripheral Chip Select 3 */
-#define AT91_PA27_TPK11         (1 << 27)       /* A: Trace Packet Port 11 */
-#define AT91_PA27_SPI0_NPCS1    (1 << 27)       /* B: SPI0 Peripheral Chip Select 1 */
-#define AT91_PA28_TPK12         (1 << 28)       /* A: Trace Packet Port 12 */
-#define AT91_PA28_SPI0_NPCS2    (1 << 28)       /* B: SPI0 Peripheral Chip Select 2 */
-#define AT91_PA29_TPK13         (1 << 29)       /* A: Trace Packet Port 13 */
-#define AT91_PA29_SPI0_NPCS3    (1 << 29)       /* B: SPI0 Peripheral Chip Select 3 */
-#define AT91_PA30_TPK14         (1 << 30)       /* A: Trace Packet Port 14 */
-#define AT91_PA30_A23           (1 << 30)       /* B: Address Bus bit 23 */
-#define AT91_PA31_TPK15         (1 << 31)       /* A: Trace Packet Port 15 */
-#define AT91_PA31_A24           (1 << 31)       /* B: Address Bus bit 24 */
-#define AT91_PB0_LCDVSYNC       (1 <<  0)       /* A: LCD Vertical Synchronization */
-#define AT91_PB1_LCDHSYNC       (1 <<  1)       /* A: LCD Horizontal Synchronization */
-#define AT91_PB2_LCDDOTCK       (1 <<  2)       /* A: LCD Dot Clock */
-#define AT91_PB2_PCK0           (1 <<  2)       /* B: PMC Programmable clock Output 0 */
-#define AT91_PB3_LCDDEN         (1 <<  3)       /* A: LCD Data Enable */
-#define AT91_PB4_LCDCC          (1 <<  4)       /* A: LCD Contrast Control */
-#define AT91_PB4_LCDD2          (1 <<  4)       /* B: LCD Data Bus Bit 2 */
-#define AT91_PB5_LCDD0          (1 <<  5)       /* A: LCD Data Bus Bit 0 */
-#define AT91_PB5_LCDD3          (1 <<  5)       /* B: LCD Data Bus Bit 3 */
-#define AT91_PB6_LCDD1          (1 <<  6)       /* A: LCD Data Bus Bit 1 */
-#define AT91_PB6_LCDD4          (1 <<  6)       /* B: LCD Data Bus Bit 4 */
-#define AT91_PB7_LCDD2          (1 <<  7)       /* A: LCD Data Bus Bit 2 */
-#define AT91_PB7_LCDD5          (1 <<  7)       /* B: LCD Data Bus Bit 5 */
-#define AT91_PB8_LCDD3          (1 <<  8)       /* A: LCD Data Bus Bit 3 */
-#define AT91_PB8_LCDD6          (1 <<  8)       /* B: LCD Data Bus Bit 6 */
-#define AT91_PB9_LCDD4          (1 <<  9)       /* A: LCD Data Bus Bit 4 */
-#define AT91_PB9_LCDD7          (1 <<  9)       /* B: LCD Data Bus Bit 7 */
-#define AT91_PB10_LCDD5         (1 << 10)       /* A: LCD Data Bus Bit 5 */
-#define AT91_PB10_LCDD10        (1 << 10)       /* B: LCD Data Bus Bit 10 */
-#define AT91_PB11_LCDD6         (1 << 11)       /* A: LCD Data Bus Bit 6 */
-#define AT91_PB11_LCDD11        (1 << 11)       /* B: LCD Data Bus Bit 11 */
-#define AT91_PB12_LCDD7         (1 << 12)       /* A: LCD Data Bus Bit 7 */
-#define AT91_PB12_LCDD12        (1 << 12)       /* B: LCD Data Bus Bit 12 */
-#define AT91_PB13_LCDD8         (1 << 13)       /* A: LCD Data Bus Bit 8 */
-#define AT91_PB13_LCDD13        (1 << 13)       /* B: LCD Data Bus Bit 13 */
-#define AT91_PB14_LCDD9         (1 << 14)       /* A: LCD Data Bus Bit 9 */
-#define AT91_PB14_LCDD14        (1 << 14)       /* B: LCD Data Bus Bit 14 */
-#define AT91_PB15_LCDD10        (1 << 15)       /* A: LCD Data Bus Bit 10 */
-#define AT91_PB15_LCDD15        (1 << 15)       /* B: LCD Data Bus Bit 15 */
-#define AT91_PB16_LCDD11        (1 << 16)       /* A: LCD Data Bus Bit 11 */
-#define AT91_PB16_LCDD19        (1 << 16)       /* B: LCD Data Bus Bit 19 */
-#define AT91_PB17_LCDD12        (1 << 17)       /* A: LCD Data Bus Bit 12 */
-#define AT91_PB17_LCDD20        (1 << 17)       /* B: LCD Data Bus Bit 20 */
-#define AT91_PB18_LCDD13        (1 << 18)       /* A: LCD Data Bus Bit 13 */
-#define AT91_PB18_LCDD21        (1 << 18)       /* B: LCD Data Bus Bit 21 */
-#define AT91_PB19_LCDD14        (1 << 19)       /* A: LCD Data Bus Bit 14 */
-#define AT91_PB19_LCDD22        (1 << 19)       /* B: LCD Data Bus Bit 22 */
-#define AT91_PB20_LCDD15        (1 << 20)       /* A: LCD Data Bus Bit 15 */
-#define AT91_PB20_LCDD23        (1 << 20)       /* B: LCD Data Bus Bit 23 */
-#define AT91_PB21_TF0           (1 << 21)       /* A: SSC0 Transmit Frame Sync */
-#define AT91_PB21_LCDD16        (1 << 21)       /* B: LCD Data Bus Bit 16 */
-#define AT91_PB22_TK0           (1 << 22)       /* A: SSC0 Transmit Clock */
-#define AT91_PB22_LCDD17        (1 << 22)       /* B: LCD Data Bus Bit 17 */
-#define AT91_PB23_TD0           (1 << 23)       /* A: SSC0 Transmit Data */
-#define AT91_PB23_LCDD18        (1 << 23)       /* B: LCD Data Bus Bit 18 */
-#define AT91_PB24_RD0           (1 << 24)       /* A: SSC0 Receive Data */
-#define AT91_PB24_LCDD19        (1 << 24)       /* B: LCD Data Bus Bit 19 */
-#define AT91_PB25_RK0           (1 << 25)       /* A: SSC0 Receive Clock */
-#define AT91_PB25_LCDD20        (1 << 25)       /* B: LCD Data Bus Bit 20 */
-#define AT91_PB26_RF0           (1 << 26)       /* A: SSC0 Receive Frame Sync */
-#define AT91_PB26_LCDD21        (1 << 26)       /* B: LCD Data Bus Bit 21 */
-#define AT91_PB27_SPI1_NPCS1    (1 << 27)       /* A: SPI1 Peripheral Chip Select 1 */
-#define AT91_PB27_LCDD22        (1 << 27)       /* B: LCD Data Bus Bit 22 */
-#define AT91_PB28_SPI1_NPCS0    (1 << 28)       /* A: SPI1 Peripheral Chip Select 0 */
-#define AT91_PB28_LCDD23        (1 << 28)       /* B: LCD Data Bus Bit 23 */
-#define AT91_PB29_SPI1_SPCK     (1 << 29)       /* A: SPI1 Serial Clock */
-#define AT91_PB29_IRQ2          (1 << 29)       /* B: Interrupt input 2 */
-#define AT91_PB30_SPI1_MISO     (1 << 30)       /* A: SPI1 Master In Slave */
-#define AT91_PB30_IRQ1          (1 << 30)       /* B: Interrupt input 1 */
-#define AT91_PB31_SPI1_MOSI     (1 << 31)       /* A: SPI1 Master Out Slave */
-#define AT91_PB31_PCK2          (1 << 31)       /* B: PMC Programmable clock Output 2 */
-#define AT91_PC0_SMOE           (1 << 0)        /* A: SmartMedia Output Enable */
-#define AT91_PC0_NCS6           (1 << 0)        /* B: Chip Select 6 */
-#define AT91_PC1_SMWE           (1 << 1)        /* A: SmartMedia Write Enable */
-#define AT91_PC1_NCS7           (1 << 1)        /* B: Chip Select 7 */
-#define AT91_PC2_NWAIT          (1 << 2)        /* A: NWAIT */
-#define AT91_PC2_IRQ0           (1 << 2)        /* B: Interrupt input 0 */
-#define AT91_PC3_A25_CFRNW      (1 << 3)        /* A: Address Bus[25] / Compact Flash Read Not Write */
-#define AT91_PC4_NCS4_CFCS0     (1 << 4)        /* A: Chip Select 4 / CompactFlash Chip Select 0 */
-#define AT91_PC5_NCS5_CFCS1     (1 << 5)        /* A: Chip Select 5 / CompactFlash Chip Select 1 */
-#define AT91_PC6_CFCE1          (1 << 6)        /* A: CompactFlash Chip Enable 1 */
-#define AT91_PC7_CFCE2          (1 << 7)        /* A: CompactFlash Chip Enable 2 */
-#define AT91_PC8_TXD0           (1 << 8)        /* A: USART0 Transmit Data */
-#define AT91_PC8_PCK2           (1 << 8)        /* B: PMC Programmable clock Output 2 */
-#define AT91_PC9_RXD0           (1 << 9)        /* A: USART0 Receive Data */
-#define AT91_PC9_PCK3           (1 << 9)        /* B: PMC Programmable clock Output 3 */
-#define AT91_PC10_RTS0          (1 << 10)       /* A: USART0 Ready To Send */
-#define AT91_PC10_SCK0          (1 << 10)       /* B: USART0 Serial Clock */
-#define AT91_PC11_CTS0          (1 << 11)       /* A: USART0 Clear To Send */
-#define AT91_PC11_FIQ           (1 << 11)       /* B: AIC Fast Interrupt Input */
-#define AT91_PC12_TXD1          (1 << 12)       /* A: USART1 Transmit Data */
-#define AT91_PC12_NCS6          (1 << 12)       /* B: Chip Select 6 */
-#define AT91_PC13_RXD1          (1 << 13)       /* A: USART1 Receive Data */
-#define AT91_PC13_NCS7          (1 << 13)       /* B: Chip Select 7 */
-#define AT91_PC14_TXD2          (1 << 14)       /* A: USART2 Transmit Data */
-#define AT91_PC14_SPI1_NPCS2    (1 << 14)       /* B: SPI1 Peripheral Chip Select 2 */
-#define AT91_PC15_RXD2          (1 << 15)       /* A: USART2 Receive Data */
-#define AT91_PC15_SPI1_NPCS3    (1 << 15)       /* B: SPI1 Peripheral Chip Select 3 */
-#define AT91_PC16_D16           (1 << 16)       /* A: Data Bus [16] */
-#define AT91_PC16_TCLK0         (1 << 16)       /* B: Timer Counter 0 external clock input */
-#define AT91_PC17_D17           (1 << 17)       /* A: Data Bus [17] */
-#define AT91_PC17_TCLK1         (1 << 17)       /* B: Timer Counter 1 external clock input */
-#define AT91_PC18_D18           (1 << 18)       /* A: Data Bus [18] */
-#define AT91_PC18_TCLK2         (1 << 18)       /* B: Timer Counter 2 external clock input */
-#define AT91_PC19_D19           (1 << 19)       /* A: Data Bus [19] */
-#define AT91_PC19_TIOA0         (1 << 19)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
-#define AT91_PC20_D20           (1 << 20)       /* A: Data Bus [20] */
-#define AT91_PC20_TIOB0         (1 << 20)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
-#define AT91_PC21_D21           (1 << 21)       /* A: Data Bus [21] */
-#define AT91_PC21_TIOA1         (1 << 21)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
-#define AT91_PC22_D22           (1 << 22)       /* A: Data Bus [22] */
-#define AT91_PC22_TIOB1         (1 << 22)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
-#define AT91_PC23_D23           (1 << 23)       /* A: Data Bus [23] */
-#define AT91_PC23_TIOA2         (1 << 23)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
-#define AT91_PC24_D24           (1 << 24)       /* A: Data Bus [24] */
-#define AT91_PC24_TIOB2         (1 << 24)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
-#define AT91_PC25_D25           (1 << 25)       /* A: Data Bus [25] */
-#define AT91_PC25_TF2           (1 << 25)       /* B: SSC2 Transmit Frame Sync */
-#define AT91_PC26_D26           (1 << 26)       /* A: Data Bus [26] */
-#define AT91_PC26_TK2           (1 << 26)       /* B: SSC2 Transmit Clock */
-#define AT91_PC27_D27           (1 << 27)       /* A: Data Bus [27] */
-#define AT91_PC27_TD2           (1 << 27)       /* B: SSC2 Transmit Data */
-#define AT91_PC28_D28           (1 << 28)       /* A: Data Bus [28] */
-#define AT91_PC28_RD2           (1 << 28)       /* B: SSC2 Receive Data */
-#define AT91_PC29_D29           (1 << 29)       /* A: Data Bus [29] */
-#define AT91_PC29_RK2           (1 << 29)       /* B: SSC2 Receive Clock */
-#define AT91_PC30_D30           (1 << 30)       /* A: Data Bus [30] */
-#define AT91_PC30_RF2           (1 << 30)       /* B: SSC2 Receive Frame Sync */
-#define AT91_PC31_D31           (1 << 31)       /* A: Data Bus [31] */
-#define AT91_PC31_PCK1          (1 << 31)       /* B: PMC Programmable clock Output 1 */
-#endif
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
index f4af68ae0ea9..115c47ac7ebb 100644
--- a/include/asm-arm/arch-at91/at91sam9263.h
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -119,13 +119,5 @@
 #define AT91SAM9263_DMAC_BASE   0x00800000      /* DMA Controller */
 #define AT91SAM9263_UHP_BASE    0x00a00000      /* USB Host controller */
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-// TODO: Add
-#endif
 #endif
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index 7a34a5b1fed0..0ce6ee98ed0b 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -121,7 +121,7 @@ extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
 /* AC97 */
 struct atmel_ac97_data {
        u8              reset_pin;      /* reset */
-}
+};
 extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
 /* LEDs */
diff --git a/include/asm-arm/arch-omap/aic23.h b/include/asm-arm/arch-omap/aic23.h
index 6513065941d0..aec2d6563622 100644
--- a/include/asm-arm/arch-omap/aic23.h
+++ b/include/asm-arm/arch-omap/aic23.h
@@ -110,7 +110,7 @@
 #define TLV320AIC23ID1                  (0x1a)  // cs low
 #define TLV320AIC23ID2                  (0x1b)  // cs high
-void tlv320aic23_power_up(void);
+void aic23_power_up(void);
-void tlv320aic23_power_down(void);
+void aic23_power_down(void);
 #endif /* __ASM_ARCH_AIC23_H */
diff --git a/include/asm-arm/arch-omap/board-apollon.h b/include/asm-arm/arch-omap/board-apollon.h
index de0c5b792c58..dcb587b311f1 100644
--- a/include/asm-arm/arch-omap/board-apollon.h
+++ b/include/asm-arm/arch-omap/board-apollon.h
@@ -30,16 +30,7 @@
 #define __ASM_ARCH_OMAP_APOLLON_H
 /* Placeholder for APOLLON specific defines */
-/* GPMC CS0 */
-#define APOLLON_CS0_BASE                0x00000000
-/* GPMC CS1 */
-#define APOLLON_CS1_BASE                0x08000000
-#define APOLLON_ETHR_START              (APOLLON_CS1_BASE + 0x300)
 #define APOLLON_ETHR_GPIO_IRQ           74
-/* GPMC CS2 - reserved for OneNAND */
-#define APOLLON_CS2_BASE                0x10000000
-/* GPMC CS3 - reserved for NOR or NAND */
-#define APOLLON_CS3_BASE                0x18000000
 #endif /*  __ASM_ARCH_OMAP_APOLLON_H */
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h
index 7ef664bc9e33..7e0efef4bb65 100644
--- a/include/asm-arm/arch-omap/board-h4.h
+++ b/include/asm-arm/arch-omap/board-h4.h
@@ -30,9 +30,6 @@
 #define __ASM_ARCH_OMAP_H4_H
 /* Placeholder for H4 specific defines */
-/* GPMC CS1 */
-#define OMAP24XX_ETHR_START             0x08000300
 #define OMAP24XX_ETHR_GPIO_IRQ          92
-#define H4_CS0_BASE                     0x04000000
 #endif /*  __ASM_ARCH_OMAP_H4_H */
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
index edf1dc6ad919..2075f556bfe4 100644
--- a/include/asm-arm/arch-omap/board.h
+++ b/include/asm-arm/arch-omap/board.h
@@ -12,6 +12,8 @@
 #include <linux/types.h>
+#include <asm/arch/gpio-switch.h>
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK          0x4f01
 #define OMAP_TAG_MMC            0x4f02
@@ -99,26 +101,31 @@ struct omap_usb_config {
 struct omap_lcd_config {
        char panel_name[16];
        char ctrl_name[16];
+        s16  nreset_gpio;
+        u8   data_lines;
+};
+struct device;
+struct fb_info;
+struct omap_backlight_config {
+        int default_intensity;
+        int (*set_power)(struct device *dev, int state);
+        int (*check_fb)(struct fb_info *fb);
 };
 struct omap_fbmem_config {
-        u32 fb_sram_start;
+        u32 start;
-        u32 fb_sram_size;
+        u32 size;
-        u32 fb_sdram_start;
+};
-        u32 fb_sdram_size;
-};
+struct omap_pwm_led_platform_data {
+        const char *name;
-/* Cover:
+        int intensity_timer;
- *      high -> closed
+        int blink_timer;
- *      low  -> open
+        void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
- * Connection:
+};
- *      high -> connected
- *      low  -> disconnected
+/* See include/asm-arm/arch-omap/gpio-switch.h for definitions */
- */
-#define OMAP_GPIO_SWITCH_TYPE_COVER             0x0000
-#define OMAP_GPIO_SWITCH_TYPE_CONNECTION        0x0001
-#define OMAP_GPIO_SWITCH_FLAG_INVERTED          0x0001
-#define OMAP_GPIO_SWITCH_FLAG_OUTPUT            0x0002
 struct omap_gpio_switch_config {
        char name[12];
        u16 gpio;
diff --git a/include/asm-arm/arch-omap/dsp.h b/include/asm-arm/arch-omap/dsp.h
deleted file mode 100644
index 06dad83dd41f..000000000000
--- a/include/asm-arm/arch-omap/dsp.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/dsp.h
- *
- * Header for OMAP DSP driver
- *
- * Copyright (C) 2002-2005 Nokia Corporation
- *
- * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * 2005/06/01:  DSP Gateway version 3.3
- */
-#ifndef ASM_ARCH_DSP_H
-#define ASM_ARCH_DSP_H
-/*
- * for /dev/dspctl/ctl
- */
-#define OMAP_DSP_IOCTL_RESET                    1
-#define OMAP_DSP_IOCTL_RUN                      2
-#define OMAP_DSP_IOCTL_SETRSTVECT               3
-#define OMAP_DSP_IOCTL_CPU_IDLE                 4
-#define OMAP_DSP_IOCTL_MPUI_WORDSWAP_ON         5
-#define OMAP_DSP_IOCTL_MPUI_WORDSWAP_OFF        6
-#define OMAP_DSP_IOCTL_MPUI_BYTESWAP_ON         7
-#define OMAP_DSP_IOCTL_MPUI_BYTESWAP_OFF        8
-#define OMAP_DSP_IOCTL_GBL_IDLE                 9
-#define OMAP_DSP_IOCTL_DSPCFG                   10
-#define OMAP_DSP_IOCTL_DSPUNCFG                 11
-#define OMAP_DSP_IOCTL_TASKCNT                  12
-#define OMAP_DSP_IOCTL_POLL                     13
-#define OMAP_DSP_IOCTL_REGMEMR                  40
-#define OMAP_DSP_IOCTL_REGMEMW                  41
-#define OMAP_DSP_IOCTL_REGIOR                   42
-#define OMAP_DSP_IOCTL_REGIOW                   43
-#define OMAP_DSP_IOCTL_GETVAR                   44
-#define OMAP_DSP_IOCTL_SETVAR                   45
-#define OMAP_DSP_IOCTL_RUNLEVEL                 50
-#define OMAP_DSP_IOCTL_SUSPEND                  51
-#define OMAP_DSP_IOCTL_RESUME                   52
-#define OMAP_DSP_IOCTL_FBEN                     53
-#define OMAP_DSP_IOCTL_FBDIS                    54
-#define OMAP_DSP_IOCTL_MBSEND                   99
-/*
- * for taskdev
- * (ioctls below should be >= 0x10000)
- */
-#define OMAP_DSP_TASK_IOCTL_BFLSH       0x10000
-#define OMAP_DSP_TASK_IOCTL_SETBSZ      0x10001
-#define OMAP_DSP_TASK_IOCTL_LOCK        0x10002
-#define OMAP_DSP_TASK_IOCTL_UNLOCK      0x10003
-#define OMAP_DSP_TASK_IOCTL_GETNAME     0x10004
-/*
- * for /dev/dspctl/mem
- */
-#define OMAP_DSP_MEM_IOCTL_EXMAP        1
-#define OMAP_DSP_MEM_IOCTL_EXUNMAP      2
-#define OMAP_DSP_MEM_IOCTL_EXMAP_FLUSH  3
-#define OMAP_DSP_MEM_IOCTL_FBEXPORT     5
-#define OMAP_DSP_MEM_IOCTL_MMUITACK     7
-#define OMAP_DSP_MEM_IOCTL_MMUINIT      9
-#define OMAP_DSP_MEM_IOCTL_KMEM_RESERVE 11
-#define OMAP_DSP_MEM_IOCTL_KMEM_RELEASE 12
-struct omap_dsp_mapinfo {
-        unsigned long dspadr;
-        unsigned long size;
-};
-/*
- * for /dev/dspctl/twch
- */
-#define OMAP_DSP_TWCH_IOCTL_MKDEV       1
-#define OMAP_DSP_TWCH_IOCTL_RMDEV       2
-#define OMAP_DSP_TWCH_IOCTL_TADD        11
-#define OMAP_DSP_TWCH_IOCTL_TDEL        12
-#define OMAP_DSP_TWCH_IOCTL_TKILL       13
-#define OMAP_DSP_DEVSTATE_NOTASK        0x00000001
-#define OMAP_DSP_DEVSTATE_ATTACHED      0x00000002
-#define OMAP_DSP_DEVSTATE_GARBAGE       0x00000004
-#define OMAP_DSP_DEVSTATE_INVALID       0x00000008
-#define OMAP_DSP_DEVSTATE_ADDREQ        0x00000100
-#define OMAP_DSP_DEVSTATE_DELREQ        0x00000200
-#define OMAP_DSP_DEVSTATE_ADDFAIL       0x00001000
-#define OMAP_DSP_DEVSTATE_ADDING        0x00010000
-#define OMAP_DSP_DEVSTATE_DELING        0x00020000
-#define OMAP_DSP_DEVSTATE_KILLING       0x00040000
-#define OMAP_DSP_DEVSTATE_STATE_MASK    0x7fffffff
-#define OMAP_DSP_DEVSTATE_STALE         0x80000000
-struct omap_dsp_taddinfo {
-        unsigned char minor;
-        unsigned long taskadr;
-};
-#define OMAP_DSP_TADD_ABORTADR  0xffffffff
-/*
- * error cause definition (for error detection device)
- */
-#define OMAP_DSP_ERRDT_WDT      0x00000001
-#define OMAP_DSP_ERRDT_MMU      0x00000002
-/*
- * mailbox protocol definitions
- */
-struct omap_dsp_mailbox_cmd {
-        unsigned short cmd;
-        unsigned short data;
-};
-struct omap_dsp_reginfo {
-        unsigned short adr;
-        unsigned short val;
-};
-struct omap_dsp_varinfo {
-        unsigned char varid;
-        unsigned short val[0];
-};
-#define OMAP_DSP_MBPROT_REVISION        0x0019
-#define OMAP_DSP_MBCMD_WDSND    0x10
-#define OMAP_DSP_MBCMD_WDREQ    0x11
-#define OMAP_DSP_MBCMD_BKSND    0x20
-#define OMAP_DSP_MBCMD_BKREQ    0x21
-#define OMAP_DSP_MBCMD_BKYLD    0x23
-#define OMAP_DSP_MBCMD_BKSNDP   0x24
-#define OMAP_DSP_MBCMD_BKREQP   0x25
-#define OMAP_DSP_MBCMD_TCTL     0x30
-#define OMAP_DSP_MBCMD_TCTLDATA 0x31
-#define OMAP_DSP_MBCMD_POLL     0x32
-#define OMAP_DSP_MBCMD_WDT      0x50    /* v3.3: obsolete */
-#define OMAP_DSP_MBCMD_RUNLEVEL 0x51
-#define OMAP_DSP_MBCMD_PM       0x52
-#define OMAP_DSP_MBCMD_SUSPEND  0x53
-#define OMAP_DSP_MBCMD_KFUNC    0x54
-#define OMAP_DSP_MBCMD_TCFG     0x60
-#define OMAP_DSP_MBCMD_TADD     0x62
-#define OMAP_DSP_MBCMD_TDEL     0x63
-#define OMAP_DSP_MBCMD_TSTOP    0x65
-#define OMAP_DSP_MBCMD_DSPCFG   0x70
-#define OMAP_DSP_MBCMD_REGRW    0x72
-#define OMAP_DSP_MBCMD_GETVAR   0x74
-#define OMAP_DSP_MBCMD_SETVAR   0x75
-#define OMAP_DSP_MBCMD_ERR      0x78
-#define OMAP_DSP_MBCMD_DBG      0x79
-#define OMAP_DSP_MBCMD_TCTL_TINIT       0x0000
-#define OMAP_DSP_MBCMD_TCTL_TEN         0x0001
-#define OMAP_DSP_MBCMD_TCTL_TDIS        0x0002
-#define OMAP_DSP_MBCMD_TCTL_TCLR        0x0003
-#define OMAP_DSP_MBCMD_TCTL_TCLR_FORCE  0x0004
-#define OMAP_DSP_MBCMD_RUNLEVEL_USER            0x01
-#define OMAP_DSP_MBCMD_RUNLEVEL_SUPER           0x0e
-#define OMAP_DSP_MBCMD_RUNLEVEL_RECOVERY        0x10
-#define OMAP_DSP_MBCMD_PM_DISABLE       0x00
-#define OMAP_DSP_MBCMD_PM_ENABLE        0x01
-#define OMAP_DSP_MBCMD_KFUNC_FBCTL      0x00
-#define OMAP_DSP_MBCMD_KFUNC_AUDIO_PWR  0x01
-#define OMAP_DSP_MBCMD_FBCTL_UPD        0x0000
-#define OMAP_DSP_MBCMD_FBCTL_ENABLE     0x0002
-#define OMAP_DSP_MBCMD_FBCTL_DISABLE    0x0003
-#define OMAP_DSP_MBCMD_AUDIO_PWR_UP     0x0000
-#define OMAP_DSP_MBCMD_AUDIO_PWR_DOWN1  0x0001
-#define OMAP_DSP_MBCMD_AUDIO_PWR_DOWN2  0x0002
-#define OMAP_DSP_MBCMD_TDEL_SAFE        0x0000
-#define OMAP_DSP_MBCMD_TDEL_KILL        0x0001
-#define OMAP_DSP_MBCMD_DSPCFG_REQ       0x00
-#define OMAP_DSP_MBCMD_DSPCFG_SYSADRH   0x28
-#define OMAP_DSP_MBCMD_DSPCFG_SYSADRL   0x29
-#define OMAP_DSP_MBCMD_DSPCFG_PROTREV   0x70
-#define OMAP_DSP_MBCMD_DSPCFG_ABORT     0x78
-#define OMAP_DSP_MBCMD_DSPCFG_LAST      0x80
-#define OMAP_DSP_MBCMD_REGRW_MEMR       0x00
-#define OMAP_DSP_MBCMD_REGRW_MEMW       0x01
-#define OMAP_DSP_MBCMD_REGRW_IOR        0x02
-#define OMAP_DSP_MBCMD_REGRW_IOW        0x03
-#define OMAP_DSP_MBCMD_REGRW_DATA       0x04
-#define OMAP_DSP_MBCMD_VARID_ICRMASK    0x00
-#define OMAP_DSP_MBCMD_VARID_LOADINFO   0x01
-#define OMAP_DSP_TTYP_ARCV      0x0001
-#define OMAP_DSP_TTYP_ASND      0x0002
-#define OMAP_DSP_TTYP_BKMD      0x0004
-#define OMAP_DSP_TTYP_BKDM      0x0008
-#define OMAP_DSP_TTYP_PVMD      0x0010
-#define OMAP_DSP_TTYP_PVDM      0x0020
-#define OMAP_DSP_EID_BADTID     0x10
-#define OMAP_DSP_EID_BADTCN     0x11
-#define OMAP_DSP_EID_BADBID     0x20
-#define OMAP_DSP_EID_BADCNT     0x21
-#define OMAP_DSP_EID_NOTLOCKED  0x22
-#define OMAP_DSP_EID_STVBUF     0x23
-#define OMAP_DSP_EID_BADADR     0x24
-#define OMAP_DSP_EID_BADTCTL    0x30
-#define OMAP_DSP_EID_BADPARAM   0x50
-#define OMAP_DSP_EID_FATAL      0x58
-#define OMAP_DSP_EID_NOMEM      0xc0
-#define OMAP_DSP_EID_NORES      0xc1
-#define OMAP_DSP_EID_IPBFULL    0xc2
-#define OMAP_DSP_EID_WDT        0xd0
-#define OMAP_DSP_EID_TASKNOTRDY 0xe0
-#define OMAP_DSP_EID_TASKBSY    0xe1
-#define OMAP_DSP_EID_TASKERR    0xef
-#define OMAP_DSP_EID_BADCFGTYP  0xf0
-#define OMAP_DSP_EID_DEBUG      0xf8
-#define OMAP_DSP_EID_BADSEQ     0xfe
-#define OMAP_DSP_EID_BADCMD     0xff
-#define OMAP_DSP_TNM_LEN        16
-#define OMAP_DSP_TID_FREE       0xff
-#define OMAP_DSP_TID_ANON       0xfe
-#define OMAP_DSP_BID_NULL       0xffff
-#define OMAP_DSP_BID_PVT        0xfffe
-#endif /* ASM_ARCH_DSP_H */
diff --git a/include/asm-arm/arch-omap/dsp_common.h b/include/asm-arm/arch-omap/dsp_common.h
index 16a459dfa714..c61f868f24ee 100644
--- a/include/asm-arm/arch-omap/dsp_common.h
+++ b/include/asm-arm/arch-omap/dsp_common.h
@@ -1,38 +1,34 @@
 /*
- * linux/include/asm-arm/arch-omap/dsp_common.h
+ * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
 *
- * Header for OMAP DSP subsystem control
+ * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
 *
- * Copyright (C) 2004,2005 Nokia Corporation
+ * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
 *
- * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
 *
- * This program is free software; you can redistribute it and/or modify
+ * This program is distributed in the hope that it will be useful, but
- * it under the terms of the GNU General Public License as published by
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
- * the Free Software Foundation; either version 2 of the License, or
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * (at your option) any later version.
+ * General Public License for more details.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
 *
- * 2005/06/03:  DSP Gateway version 3.3
 */
 #ifndef ASM_ARCH_DSP_COMMON_H
 #define ASM_ARCH_DSP_COMMON_H
+#ifdef CONFIG_ARCH_OMAP1
 extern void omap_dsp_request_mpui(void);
 extern void omap_dsp_release_mpui(void);
 extern int omap_dsp_request_mem(void);
 extern int omap_dsp_release_mem(void);
+#endif
-extern void (*omap_dsp_audio_pwr_up_request)(int stage);
-extern void (*omap_dsp_audio_pwr_down_request)(int stage);
 #endif /* ASM_ARCH_DSP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/gpio-switch.h b/include/asm-arm/arch-omap/gpio-switch.h
new file mode 100644
index 000000000000..10da0e07c0cf
--- /dev/null
+++ b/include/asm-arm/arch-omap/gpio-switch.h
@@ -0,0 +1,54 @@
+/*
+ * GPIO switch definitions
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
+#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
+#include <linux/types.h>
+/* Cover:
+ *      high -> closed
+ *      low  -> open
+ * Connection:
+ *      high -> connected
+ *      low  -> disconnected
+ * Activity:
+ *      high -> active
+ *      low  -> inactive
+ *
+ */
+#define OMAP_GPIO_SWITCH_TYPE_COVER             0x0000
+#define OMAP_GPIO_SWITCH_TYPE_CONNECTION        0x0001
+#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY          0x0002
+#define OMAP_GPIO_SWITCH_FLAG_INVERTED          0x0001
+#define OMAP_GPIO_SWITCH_FLAG_OUTPUT            0x0002
+struct omap_gpio_switch {
+        const char *name;
+        s16 gpio;
+        unsigned flags:4;
+        unsigned type:4;
+        /* Time in ms to debounce when transitioning from
+         * inactive state to active state. */
+        u16 debounce_rising;
+        /* Same for transition from active to inactive state. */
+        u16 debounce_falling;
+        /* notify board-specific code about state changes */
+        void (* notify)(void *data, int state);
+        void *notify_data;
+};
+/* Call at init time only */
+extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
+                                        int count);
+#endif
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h
index 7c03ef6c14c4..995cc83482eb 100644
--- a/include/asm-arm/arch-omap/gpmc.h
+++ b/include/asm-arm/arch-omap/gpmc.h
@@ -87,5 +87,7 @@ extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
+extern int gpmc_cs_set_reserved(int cs, int reserved);
+extern int gpmc_cs_reserved(int cs);
 #endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 481048d65214..e225f4f39b34 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -267,6 +267,15 @@
 #define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
 /*
+ * ----------------------------------------------------------------------------
+ * Pulse-Width Light
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_PWL_BASE                   0xfffb5800
+#define OMAP_PWL_ENABLE                 (OMAP_PWL_BASE + 0x00)
+#define OMAP_PWL_CLK_ENABLE             (OMAP_PWL_BASE + 0x04)
+/*
 * ---------------------------------------------------------------------------
 * Processor specific defines
 * ---------------------------------------------------------------------------
diff --git a/include/asm-arm/arch-omap/hwa742.h b/include/asm-arm/arch-omap/hwa742.h
new file mode 100644
index 000000000000..577f492f2d3c
--- /dev/null
+++ b/include/asm-arm/arch-omap/hwa742.h
@@ -0,0 +1,12 @@
+#ifndef _HWA742_H
+#define _HWA742_H
+struct hwa742_platform_data {
+        void            (*power_up)(struct device *dev);
+        void            (*power_down)(struct device *dev);
+        unsigned long   (*get_clock_rate)(struct device *dev);
+        unsigned        te_connected:1;
+};
+#endif
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 78f68e6a4f0c..4aca7e3d7566 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -77,6 +77,17 @@
 #define io_p2v(pa)      ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
 #define io_v2p(va)      ((va) - IO_OFFSET)      /* Works for L3 and L4 */
+/* DSP */
+#define DSP_MEM_24XX_PHYS       OMAP24XX_DSP_MEM_BASE   /* 0x58000000 */
+#define DSP_MEM_24XX_VIRT       0xe0000000
+#define DSP_MEM_24XX_SIZE       0x28000
+#define DSP_IPI_24XX_PHYS       OMAP24XX_DSP_IPI_BASE   /* 0x59000000 */
+#define DSP_IPI_24XX_VIRT       0xe1000000
+#define DSP_IPI_24XX_SIZE       SZ_4K
+#define DSP_MMU_24XX_PHYS       OMAP24XX_DSP_MMU_BASE   /* 0x5a000000 */
+#define DSP_MMU_24XX_VIRT       0xe2000000
+#define DSP_MMU_24XX_SIZE       SZ_4K
 #endif
 #ifndef __ASSEMBLER__
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index c5bb05a69b81..3ede58b51db2 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -37,8 +37,6 @@
 #define INT_DSP_MMU_ABORT       7
 #define INT_HOST                8
 #define INT_ABORT               9
-#define INT_DSP_MAILBOX1        10
-#define INT_DSP_MAILBOX2        11
 #define INT_BRIDGE_PRIV         13
 #define INT_GPIO_BANK1          14
 #define INT_UART3               15
@@ -63,6 +61,8 @@
 #define INT_1510_RES2           2
 #define INT_1510_SPI_TX         4
 #define INT_1510_SPI_RX         5
+#define INT_1510_DSP_MAILBOX1   10
+#define INT_1510_DSP_MAILBOX2   11
 #define INT_1510_RES12          12
 #define INT_1510_LB_MMU         17
 #define INT_1510_RES18          18
@@ -75,6 +75,8 @@
 #define INT_1610_IH2_FIQ        2
 #define INT_1610_McBSP2_TX      4
 #define INT_1610_McBSP2_RX      5
+#define INT_1610_DSP_MAILBOX1   10
+#define INT_1610_DSP_MAILBOX2   11
 #define INT_1610_LCD_LINE       12
 #define INT_1610_GPTIMER1       17
 #define INT_1610_GPTIMER2       18
@@ -131,11 +133,11 @@
 #define INT_RTC_TIMER           (25 + IH2_BASE)
 #define INT_RTC_ALARM           (26 + IH2_BASE)
 #define INT_MEM_STICK           (27 + IH2_BASE)
-#define INT_DSP_MMU             (28 + IH2_BASE)
 /*
 * OMAP-1510 specific IRQ numbers for interrupt handler 2
 */
+#define INT_1510_DSP_MMU        (28 + IH2_BASE)
 #define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
 /*
@@ -146,6 +148,7 @@
 #define INT_1610_USB_OTG        (8 + IH2_BASE)
 #define INT_1610_SoSSI          (9 + IH2_BASE)
 #define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
+#define INT_1610_DSP_MMU        (28 + IH2_BASE)
 #define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
 #define INT_1610_STI            (32 + IH2_BASE)
 #define INT_1610_STI_WAKEUP     (33 + IH2_BASE)
@@ -239,10 +242,15 @@
 #define INT_24XX_SDMA_IRQ3      15
 #define INT_24XX_CAM_IRQ        24
 #define INT_24XX_DSS_IRQ        25
+#define INT_24XX_MAIL_U0_MPU    26
+#define INT_24XX_DSP_UMA        27
+#define INT_24XX_DSP_MMU        28
 #define INT_24XX_GPIO_BANK1     29
 #define INT_24XX_GPIO_BANK2     30
 #define INT_24XX_GPIO_BANK3     31
 #define INT_24XX_GPIO_BANK4     32
+#define INT_24XX_GPIO_BANK5     33
+#define INT_24XX_MAIL_U3_MPU    34
 #define INT_24XX_GPTIMER1       37
 #define INT_24XX_GPTIMER2       38
 #define INT_24XX_GPTIMER3       39
@@ -262,6 +270,12 @@
 #define INT_24XX_UART1_IRQ      72
 #define INT_24XX_UART2_IRQ      73
 #define INT_24XX_UART3_IRQ      74
+#define INT_24XX_USB_IRQ_GEN    75
+#define INT_24XX_USB_IRQ_NISO   76
+#define INT_24XX_USB_IRQ_ISO    77
+#define INT_24XX_USB_IRQ_HGEN   78
+#define INT_24XX_USB_IRQ_HSOF   79
+#define INT_24XX_USB_IRQ_OTG    80
 #define INT_24XX_MMC_IRQ        83
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
diff --git a/include/asm-arm/arch-omap/lcd_lph8923.h b/include/asm-arm/arch-omap/lcd_lph8923.h
deleted file mode 100644
index 004e67e22ca7..000000000000
--- a/include/asm-arm/arch-omap/lcd_lph8923.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __LCD_LPH8923_H
-#define __LCD_LPH8923_H
-enum lcd_lph8923_test_num {
-        LCD_LPH8923_TEST_RGB_LINES,
-};
-enum lcd_lph8923_test_result {
-        LCD_LPH8923_TEST_SUCCESS,
-        LCD_LPH8923_TEST_INVALID,
-        LCD_LPH8923_TEST_FAILED,
-};
-#endif
diff --git a/include/asm-arm/arch-omap/lcd_mipid.h b/include/asm-arm/arch-omap/lcd_mipid.h
new file mode 100644
index 000000000000..f8fbc4801e52
--- /dev/null
+++ b/include/asm-arm/arch-omap/lcd_mipid.h
@@ -0,0 +1,24 @@
+#ifndef __LCD_MIPID_H
+#define __LCD_MIPID_H
+enum mipid_test_num {
+        MIPID_TEST_RGB_LINES,
+};
+enum mipid_test_result {
+        MIPID_TEST_SUCCESS,
+        MIPID_TEST_INVALID,
+        MIPID_TEST_FAILED,
+};
+#ifdef __KERNEL__
+struct mipid_platform_data {
+        int     nreset_gpio;
+        int     data_lines;
+        void    (*shutdown)(struct mipid_platform_data *pdata);
+};
+#endif
+#endif
diff --git a/include/asm-arm/arch-omap/led.h b/include/asm-arm/arch-omap/led.h
new file mode 100644
index 000000000000..f3acae28e2da
--- /dev/null
+++ b/include/asm-arm/arch-omap/led.h
@@ -0,0 +1,24 @@
+/*
+ *  linux/include/asm-arm/arch-omap/led.h
+ *
+ *  Copyright (C) 2006 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASMARM_ARCH_LED_H
+#define ASMARM_ARCH_LED_H
+struct omap_led_config {
+        struct led_classdev     cdev;
+        s16                     gpio;
+};
+struct omap_led_platform_data {
+        s16                     nr_leds;
+        struct omap_led_config  *leds;
+};
+#endif
diff --git a/include/asm-arm/arch-omap/mailbox.h b/include/asm-arm/arch-omap/mailbox.h
new file mode 100644
index 000000000000..4bf0909461f2
--- /dev/null
+++ b/include/asm-arm/arch-omap/mailbox.h
@@ -0,0 +1,73 @@
+/* mailbox.h */
+#ifndef MAILBOX_H
+#define MAILBOX_H
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#include <linux/blkdev.h>
+typedef u32 mbox_msg_t;
+typedef void (mbox_receiver_t)(mbox_msg_t msg);
+struct omap_mbox;
+typedef int __bitwise omap_mbox_irq_t;
+#define IRQ_TX ((__force omap_mbox_irq_t) 1)
+#define IRQ_RX ((__force omap_mbox_irq_t) 2)
+typedef int __bitwise omap_mbox_type_t;
+#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
+#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
+struct omap_mbox_ops {
+        omap_mbox_type_t        type;
+        int             (*startup)(struct omap_mbox *mbox);
+        void            (*shutdown)(struct omap_mbox *mbox);
+        /* fifo */
+        mbox_msg_t      (*fifo_read)(struct omap_mbox *mbox);
+        void            (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
+        int             (*fifo_empty)(struct omap_mbox *mbox);
+        int             (*fifo_full)(struct omap_mbox *mbox);
+        /* irq */
+        void            (*enable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+        void            (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+        void            (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+        int             (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+};
+struct omap_mbox_queue {
+        spinlock_t              lock;
+        request_queue_t         *queue;
+        struct work_struct      work;
+        int     (*callback)(void *);
+        struct omap_mbox        *mbox;
+};
+struct omap_mbox {
+        char                    *name;
+        unsigned int            irq;
+        struct omap_mbox_queue  *txq, *rxq;
+        struct omap_mbox_ops    *ops;
+        mbox_msg_t              seq_snd, seq_rcv;
+        struct device           dev;
+        struct omap_mbox        *next;
+        void                    *priv;
+        void                    (*err_notify)(void);
+};
+int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *);
+void omap_mbox_init_seq(struct omap_mbox *);
+struct omap_mbox *omap_mbox_get(const char *);
+void omap_mbox_put(struct omap_mbox *);
+int omap_mbox_register(struct omap_mbox *);
+int omap_mbox_unregister(struct omap_mbox *);
+#endif /* MAILBOX_H */
diff --git a/include/asm-arm/arch-omap/mcspi.h b/include/asm-arm/arch-omap/mcspi.h
index 9e7f40a88e1b..1254e4945b6f 100644
--- a/include/asm-arm/arch-omap/mcspi.h
+++ b/include/asm-arm/arch-omap/mcspi.h
@@ -2,7 +2,6 @@
 #define _OMAP2_MCSPI_H
 struct omap2_mcspi_platform_config {
-        unsigned long   base;
        unsigned short  num_cs;
 };
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
index 48fabc493163..14cba97c18ad 100644
--- a/include/asm-arm/arch-omap/memory.h
+++ b/include/asm-arm/arch-omap/memory.h
@@ -86,5 +86,18 @@
 #endif  /* CONFIG_ARCH_OMAP15XX */
+/* Override the ARM default */
+#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
+#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
+#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
+#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
+#endif
+#define CONSISTENT_DMA_SIZE \
+        (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
+#endif
 #endif
diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h
index 88cd4c87f0de..82d276a6bd95 100644
--- a/include/asm-arm/arch-omap/menelaus.h
+++ b/include/asm-arm/arch-omap/menelaus.h
@@ -7,10 +7,19 @@
 #ifndef __ASM_ARCH_MENELAUS_H
 #define __ASM_ARCH_MENELAUS_H
-extern void menelaus_mmc_register(void (*callback)(unsigned long data, u8 card_mask),
+extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
-                                  unsigned long data);
+                                          void *data);
-extern void menelaus_mmc_remove(void);
+extern void menelaus_unregister_mmc_callback(void);
-extern void menelaus_mmc_opendrain(int enable);
+extern int menelaus_set_mmc_opendrain(int slot, int enable);
+extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
+extern int menelaus_set_vmem(unsigned int mV);
+extern int menelaus_set_vio(unsigned int mV);
+extern int menelaus_set_vmmc(unsigned int mV);
+extern int menelaus_set_vaux(unsigned int mV);
+extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
+extern int menelaus_set_slot_sel(int enable);
+extern int menelaus_get_slot_pin_states(void);
 #if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
 #define omap_has_menelaus()     1
diff --git a/include/asm-arm/arch-omap/omap16xx.h b/include/asm-arm/arch-omap/omap16xx.h
index f0c7f0fb4dc0..f7f5cdfdccce 100644
--- a/include/asm-arm/arch-omap/omap16xx.h
+++ b/include/asm-arm/arch-omap/omap16xx.h
@@ -159,15 +159,6 @@
 #define UART3_MVR               (OMAP_UART3_BASE + 0x50)
 /*
- * ----------------------------------------------------------------------------
- * Pulse-Width Light
- * ----------------------------------------------------------------------------
- */
-#define OMAP16XX_PWL_BASE       (0xfffb5800)
-#define OMAP16XX_PWL_ENABLE     (OMAP16XX_PWL_BASE + 0x00)
-#define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04)
-/*
 * ---------------------------------------------------------------------------
 * Watchdog timer
 * ---------------------------------------------------------------------------
@@ -199,5 +190,8 @@
 #define WSPR_DISABLE_0         (0x0000aaaa)
 #define WSPR_DISABLE_1         (0x00005555)
+/* Mailbox */
+#define OMAP16XX_MAILBOX_BASE   (0xfffcf000)
 #endif /*  __ASM_ARCH_OMAP16XX_H */
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index 6e59805fa654..708b2fac77f2 100644
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -20,5 +20,14 @@
 #define OMAP24XX_PRCM_BASE      (L4_24XX_BASE + 0x8000)
 #define OMAP24XX_SDRC_BASE      (L3_24XX_BASE + 0x9000)
+/* DSP SS */
+#define OMAP24XX_DSP_BASE       0x58000000
+#define OMAP24XX_DSP_MEM_BASE   (OMAP24XX_DSP_BASE + 0x0)
+#define OMAP24XX_DSP_IPI_BASE   (OMAP24XX_DSP_BASE + 0x1000000)
+#define OMAP24XX_DSP_MMU_BASE   (OMAP24XX_DSP_BASE + 0x2000000)
+/* Mailbox */
+#define OMAP24XX_MAILBOX_BASE   (L4_24XX_BASE + 0x94000)
 #endif /* __ASM_ARCH_OMAP24XX_H */
diff --git a/include/asm-arm/arch-omap/omapfb.h b/include/asm-arm/arch-omap/omapfb.h
index fccdb3db025f..46d7a4f60854 100644
--- a/include/asm-arm/arch-omap/omapfb.h
+++ b/include/asm-arm/arch-omap/omapfb.h
@@ -24,6 +24,9 @@
 #ifndef __OMAPFB_H
 #define __OMAPFB_H
+#include <asm/ioctl.h>
+#include <asm/types.h>
 /* IOCTL commands. */
 #define OMAP_IOW(num, dtype)    _IOW('O', num, dtype)
@@ -35,26 +38,46 @@
 #define OMAPFB_SYNC_GFX         OMAP_IO(37)
 #define OMAPFB_VSYNC            OMAP_IO(38)
 #define OMAPFB_SET_UPDATE_MODE  OMAP_IOW(40, int)
-#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(41, struct omapfb_update_window_old)
+#define OMAPFB_GET_CAPS         OMAP_IOR(42, struct omapfb_caps)
-#define OMAPFB_GET_CAPS         OMAP_IOR(42, unsigned long)
 #define OMAPFB_GET_UPDATE_MODE  OMAP_IOW(43, int)
 #define OMAPFB_LCD_TEST         OMAP_IOW(45, int)
 #define OMAPFB_CTRL_TEST        OMAP_IOW(46, int)
-#define OMAPFB_UPDATE_WINDOW    OMAP_IOW(47, struct omapfb_update_window)
+#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
-#define OMAPFB_SETUP_PLANE      OMAP_IOW(48, struct omapfb_setup_plane)
-#define OMAPFB_ENABLE_PLANE     OMAP_IOW(49, struct omapfb_enable_plane)
 #define OMAPFB_SET_COLOR_KEY    OMAP_IOW(50, struct omapfb_color_key)
+#define OMAPFB_GET_COLOR_KEY    OMAP_IOW(51, struct omapfb_color_key)
+#define OMAPFB_SETUP_PLANE      OMAP_IOW(52, struct omapfb_plane_info)
+#define OMAPFB_QUERY_PLANE      OMAP_IOW(53, struct omapfb_plane_info)
+#define OMAPFB_UPDATE_WINDOW    OMAP_IOW(54, struct omapfb_update_window)
+#define OMAPFB_SETUP_MEM        OMAP_IOW(55, struct omapfb_mem_info)
+#define OMAPFB_QUERY_MEM        OMAP_IOW(56, struct omapfb_mem_info)
 #define OMAPFB_CAPS_GENERIC_MASK        0x00000fff
 #define OMAPFB_CAPS_LCDC_MASK           0x00fff000
 #define OMAPFB_CAPS_PANEL_MASK          0xff000000
 #define OMAPFB_CAPS_MANUAL_UPDATE       0x00001000
+#define OMAPFB_CAPS_TEARSYNC            0x00002000
+#define OMAPFB_CAPS_PLANE_RELOCATE_MEM  0x00004000
+#define OMAPFB_CAPS_PLANE_SCALE         0x00008000
+#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
+#define OMAPFB_CAPS_WINDOW_SCALE        0x00020000
+#define OMAPFB_CAPS_WINDOW_OVERLAY      0x00040000
 #define OMAPFB_CAPS_SET_BACKLIGHT       0x01000000
 /* Values from DSP must map to lower 16-bits */
-#define OMAPFB_FORMAT_MASK         0x00ff
+#define OMAPFB_FORMAT_MASK              0x00ff
-#define OMAPFB_FORMAT_FLAG_DOUBLE  0x0100
+#define OMAPFB_FORMAT_FLAG_DOUBLE       0x0100
+#define OMAPFB_FORMAT_FLAG_TEARSYNC     0x0200
+#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC  0x0400
+#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY       0x0800
+#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY      0x1000
+#define OMAPFB_EVENT_READY      1
+#define OMAPFB_EVENT_DISABLED   2
+#define OMAPFB_MEMTYPE_SDRAM            0
+#define OMAPFB_MEMTYPE_SRAM             1
+#define OMAPFB_MEMTYPE_MAX              1
 enum omapfb_color_format {
        OMAPFB_COLOR_RGB565 = 0,
@@ -64,17 +87,23 @@ enum omapfb_color_format {
        OMAPFB_COLOR_CLUT_4BPP,
        OMAPFB_COLOR_CLUT_2BPP,
        OMAPFB_COLOR_CLUT_1BPP,
+        OMAPFB_COLOR_RGB444,
+        OMAPFB_COLOR_YUY422,
 };
 struct omapfb_update_window {
        __u32 x, y;
        __u32 width, height;
        __u32 format;
+        __u32 out_x, out_y;
+        __u32 out_width, out_height;
+        __u32 reserved[8];
 };
 struct omapfb_update_window_old {
        __u32 x, y;
        __u32 width, height;
+        __u32 format;
 };
 enum omapfb_plane {
@@ -88,18 +117,28 @@ enum omapfb_channel_out {
        OMAPFB_CHANNEL_OUT_DIGIT,
 };
-struct omapfb_setup_plane {
+struct omapfb_plane_info {
-        __u8  plane;
+        __u32 pos_x;
+        __u32 pos_y;
+        __u8  enabled;
        __u8  channel_out;
-        __u32 offset;
+        __u8  mirror;
-        __u32 pos_x, pos_y;
+        __u8  reserved1;
-        __u32 width, height;
+        __u32 out_width;
-        __u32 color_mode;
+        __u32 out_height;
+        __u32 reserved2[12];
 };
-struct omapfb_enable_plane {
+struct omapfb_mem_info {
-        __u8  plane;
+        __u32 size;
-        __u8  enable;
+        __u8  type;
+        __u8  reserved[3];
+};
+struct omapfb_caps {
+        __u32 ctrl;
+        __u32 plane_color;
+        __u32 wnd_color;
 };
 enum omapfb_color_key_type {
@@ -141,6 +180,9 @@ enum omapfb_update_mode {
 #define OMAP_LCDC_PANEL_TFT             0x0100
+#define OMAPFB_PLANE_XRES_MIN           8
+#define OMAPFB_PLANE_YRES_MIN           8
 #ifdef CONFIG_ARCH_OMAP1
 #define OMAPFB_PLANE_NUM                1
 #else
@@ -169,19 +211,19 @@ struct lcd_panel {
        int             pcd;            /* pixel clock divider.
                                           Obsolete use pixel_clock instead */
-        int             (*init)         (struct omapfb_device *fbdev);
+        int             (*init)         (struct lcd_panel *panel,
-        void            (*cleanup)      (void);
+                                         struct omapfb_device *fbdev);
-        int             (*enable)       (void);
+        void            (*cleanup)      (struct lcd_panel *panel);
-        void            (*disable)      (void);
+        int             (*enable)       (struct lcd_panel *panel);
-        unsigned long   (*get_caps)     (void);
+        void            (*disable)      (struct lcd_panel *panel);
-        int             (*set_bklight_level)(unsigned int level);
+        unsigned long   (*get_caps)     (struct lcd_panel *panel);
-        unsigned int    (*get_bklight_level)(void);
+        int             (*set_bklight_level)(struct lcd_panel *panel,
-        unsigned int    (*get_bklight_max)  (void);
+                                             unsigned int level);
-        int             (*run_test)     (int test_num);
+        unsigned int    (*get_bklight_level)(struct lcd_panel *panel);
+        unsigned int    (*get_bklight_max)  (struct lcd_panel *panel);
+        int             (*run_test)     (struct lcd_panel *panel, int test_num);
 };
-struct omapfb_device;
 struct extif_timings {
        int cs_on_time;
        int cs_off_time;
@@ -202,9 +244,10 @@ struct extif_timings {
 };
 struct lcd_ctrl_extif {
-        int  (*init)            (void);
+        int  (*init)            (struct omapfb_device *fbdev);
        void (*cleanup)         (void);
        void (*get_clk_info)    (u32 *clk_period, u32 *max_clk_div);
+        unsigned long (*get_max_tx_rate)(void);
        int  (*convert_timings) (struct extif_timings *timings);
        void (*set_timings)     (const struct extif_timings *timings);
        void (*set_bits_per_cycle)(int bpc);
@@ -213,31 +256,48 @@ struct lcd_ctrl_extif {
        void (*write_data)      (const void *buf, unsigned int len);
        void (*transfer_area)   (int width, int height,
                                 void (callback)(void * data), void *data);
+        int  (*setup_tearsync)  (unsigned pin_cnt,
+                                 unsigned hs_pulse_time, unsigned vs_pulse_time,
+                                 int hs_pol_inv, int vs_pol_inv, int div);
+        int  (*enable_tearsync) (int enable, unsigned line);
        unsigned long           max_transmit_size;
 };
 struct omapfb_notifier_block {
        struct notifier_block   nb;
        void                    *data;
+        int                     plane_idx;
 };
-typedef int (*omapfb_notifier_callback_t)(struct omapfb_notifier_block *,
+typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
-                                           unsigned long event,
+                                          unsigned long event,
-                                           struct omapfb_device *fbdev);
+                                          void *fbi);
+struct omapfb_mem_region {
+        dma_addr_t      paddr;
+        void            *vaddr;
+        unsigned long   size;
+        u8              type;           /* OMAPFB_PLANE_MEM_* */
+        unsigned        alloc:1;        /* allocated by the driver */
+        unsigned        map:1;          /* kernel mapped by the driver */
+};
+struct omapfb_mem_desc {
+        int                             region_cnt;
+        struct omapfb_mem_region        region[OMAPFB_PLANE_NUM];
+};
 struct lcd_ctrl {
        const char      *name;
        void            *data;
        int             (*init)           (struct omapfb_device *fbdev,
-                                           int ext_mode, int req_vram_size);
+                                           int ext_mode,
+                                           struct omapfb_mem_desc *req_md);
        void            (*cleanup)        (void);
        void            (*bind_client)    (struct omapfb_notifier_block *nb);
-        void            (*get_vram_layout)(unsigned long *size,
+        void            (*get_caps)       (int plane, struct omapfb_caps *caps);
-                                           void **virt_base,
-                                           dma_addr_t *phys_base);
-        int             (*mmap)           (struct vm_area_struct *vma);
-        unsigned long   (*get_caps)       (void);
        int             (*set_update_mode)(enum omapfb_update_mode mode);
        enum omapfb_update_mode (*get_update_mode)(void);
        int             (*setup_plane)    (int plane, int channel_out,
@@ -245,8 +305,16 @@ struct lcd_ctrl {
                                           int screen_width,
                                           int pos_x, int pos_y, int width,
                                           int height, int color_mode);
+        int             (*setup_mem)      (int plane, size_t size,
+                                           int mem_type, unsigned long *paddr);
+        int             (*mmap)           (struct fb_info *info,
+                                           struct vm_area_struct *vma);
+        int             (*set_scale)      (int plane,
+                                           int orig_width, int orig_height,
+                                           int out_width, int out_height);
        int             (*enable_plane)   (int plane, int enable);
-        int             (*update_window)  (struct omapfb_update_window *win,
+        int             (*update_window)  (struct fb_info *fbi,
+                                           struct omapfb_update_window *win,
                                           void (*callback)(void *),
                                           void *callback_data);
        void            (*sync)           (void);
@@ -257,7 +325,7 @@ struct lcd_ctrl {
                                           u16 blue, u16 transp,
                                           int update_hw_mem);
        int             (*set_color_key)  (struct omapfb_color_key *ck);
+        int             (*get_color_key)  (struct omapfb_color_key *ck);
 };
 enum omapfb_state {
@@ -266,19 +334,20 @@ enum omapfb_state {
        OMAPFB_ACTIVE   = 100
 };
+struct omapfb_plane_struct {
+        int                             idx;
+        struct omapfb_plane_info        info;
+        enum omapfb_color_format        color_mode;
+        struct omapfb_device            *fbdev;
+};
 struct omapfb_device {
        int                     state;
        int                     ext_lcdc;               /* Using external
                                                           LCD controller */
        struct mutex            rqueue_mutex;
-        void                    *vram_virt_base;
-        dma_addr_t              vram_phys_base;
-        unsigned long           vram_size;
-        int                     color_mode;
        int                     palette_size;
-        int                     mirror;
        u32                     pseudo_palette[17];
        struct lcd_panel        *panel;                 /* LCD panel */
@@ -286,19 +355,19 @@ struct omapfb_device {
        struct lcd_ctrl         *int_ctrl;              /* internal LCD ctrl */
        struct lcd_ctrl_extif   *ext_if;                /* LCD ctrl external
                                                           interface */
-        struct fb_info          *fb_info;
        struct device           *dev;
+        struct fb_var_screeninfo        new_var;        /* for mode changes */
+        struct omapfb_mem_desc          mem_desc;
+        struct fb_info                  *fb_info[OMAPFB_PLANE_NUM];
 };
 struct omapfb_platform_data {
-        struct omap_lcd_config   lcd;
+        struct omap_lcd_config          lcd;
-        struct omap_fbmem_config fbmem;
+        struct omapfb_mem_desc          mem_desc;
+        void                            *ctrl_platform_data;
 };
-#define OMAPFB_EVENT_READY      1
-#define OMAPFB_EVENT_DISABLED   2
 #ifdef CONFIG_ARCH_OMAP1
 extern struct lcd_ctrl omap1_lcd_ctrl;
 #else
@@ -310,15 +379,16 @@ extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
 extern void omapfb_notify_clients(struct omapfb_device *fbdev,
                                  unsigned long event);
 extern int  omapfb_register_client(struct omapfb_notifier_block *nb,
-                                    omapfb_notifier_callback_t callback,
+                                   omapfb_notifier_callback_t callback,
-                                    void *callback_data);
+                                   void *callback_data);
 extern int  omapfb_unregister_client(struct omapfb_notifier_block *nb);
-extern int  omapfb_update_window_async(struct omapfb_update_window *win,
+extern int  omapfb_update_window_async(struct fb_info *fbi,
-                                        void (*callback)(void *),
+                                       struct omapfb_update_window *win,
-                                        void *callback_data);
+                                       void (*callback)(void *),
+                                       void *callback_data);
-/* in arch/arm/plat-omap/devices.c */
+/* in arch/arm/plat-omap/fb.c */
-extern void omapfb_reserve_mem(void);
+extern void omapfb_set_ctrl_platform_data(void *pdata);
 #endif /* __KERNEL__ */
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
index 6fc0dd57b7c3..bb9bb3fd532f 100644
--- a/include/asm-arm/arch-omap/sram.h
+++ b/include/asm-arm/arch-omap/sram.h
@@ -20,9 +20,6 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
                                      u32 mem_type);
 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-extern unsigned long omap_fb_sram_start;
-extern unsigned long omap_fb_sram_size;
 /* Do not use these */
 extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl);
 extern unsigned long sram_reprogram_clock_sz;
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 054fb9a8e0c6..99ae9eabaf71 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -7,9 +7,27 @@
 /*-------------------------------------------------------------------------*/
-#define OTG_BASE                        0xfffb0400
+#define OMAP1_OTG_BASE                  0xfffb0400
-#define UDC_BASE                        0xfffb4000
+#define OMAP1_UDC_BASE                  0xfffb4000
-#define OMAP_OHCI_BASE                  0xfffba000
+#define OMAP1_OHCI_BASE                 0xfffba000
+#define OMAP2_OHCI_BASE                 0x4805e000
+#define OMAP2_UDC_BASE                  0x4805e200
+#define OMAP2_OTG_BASE                  0x4805e300
+#ifdef CONFIG_ARCH_OMAP1
+#define OTG_BASE                        OMAP1_OTG_BASE
+#define UDC_BASE                        OMAP1_UDC_BASE
+#define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
+#else
+#define OTG_BASE                        OMAP2_OTG_BASE
+#define UDC_BASE                        OMAP2_UDC_BASE
+#define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
+#endif
 /*-------------------------------------------------------------------------*/
@@ -28,6 +46,7 @@
 #       define   HST_IDLE_EN            (1 << 14)
 #       define   DEV_IDLE_EN            (1 << 13)
 #       define   OTG_RESET_DONE         (1 << 2)
+#       define   OTG_SOFT_RESET         (1 << 1)
 #define OTG_SYSCON_2_REG                OTG_REG32(0x08)
 #       define   OTG_EN                 (1 << 31)
 #       define   USBX_SYNCHRO           (1 << 30)
@@ -103,6 +122,7 @@
 /*-------------------------------------------------------------------------*/
+/* OMAP1 */
 #define USB_TRANSCEIVER_CTRL_REG        __REG32(0xfffe1000 + 0x0064)
 #       define  CONF_USB2_UNI_R         (1 << 8)
 #       define  CONF_USB1_UNI_R         (1 << 7)
@@ -111,7 +131,17 @@
 #       define  CONF_USB_PWRDN_DM_R     (1 << 2)
 #       define  CONF_USB_PWRDN_DP_R     (1 << 1)
+/* OMAP2 */
+#define CONTROL_DEVCONF_REG             __REG32(L4_24XX_BASE + 0x0274)
+#       define  USB_UNIDIR                      0x0
+#       define  USB_UNIDIR_TLL                  0x1
+#       define  USB_BIDIR                       0x2
+#       define  USB_BIDIR_TLL                   0x3
+#       define  USBT0WRMODEI(x)         ((x) << 22)
+#       define  USBT1WRMODEI(x)         ((x) << 20)
+#       define  USBT2WRMODEI(x)         ((x) << 18)
+#       define  USBT2TLL5PI             (1 << 17)
+#       define  USB0PUENACTLOI          (1 << 16)
+#       define  USBSTANDBYCTRL          (1 << 15)
 #endif  /* __ASM_ARCH_OMAP_USB_H */
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index afad32c76e6c..d1294a46c70c 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -102,6 +102,14 @@
 //# endif
 #endif
+#if defined(CONFIG_CPU_V7)
+//# ifdef _CACHE
+#  define MULTI_CACHE 1
+//# else
+//#  define _CACHE v7
+//# endif
+#endif
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 #error Unknown cache maintainence model
 #endif
@@ -418,11 +426,19 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 */
 #define flush_icache_page(vma,page)     do { } while (0)
-#define __cacheid_present(val)          (val != read_cpuid(CPUID_ID))
+#define __cacheid_present(val)                  (val != read_cpuid(CPUID_ID))
-#define __cacheid_vivt(val)             ((val & (15 << 25)) != (14 << 25))
+#define __cacheid_type_v7(val)                  ((val & (7 << 29)) == (4 << 29))
-#define __cacheid_vipt(val)             ((val & (15 << 25)) == (14 << 25))
-#define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
+#define __cacheid_vivt_prev7(val)               ((val & (15 << 25)) != (14 << 25))
-#define __cacheid_vipt_aliasing(val)    ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
+#define __cacheid_vipt_prev7(val)               ((val & (15 << 25)) == (14 << 25))
+#define __cacheid_vipt_nonaliasing_prev7(val)   ((val & (15 << 25 | 1 << 23)) == (14 << 25))
+#define __cacheid_vipt_aliasing_prev7(val)      ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
+#define __cacheid_vivt(val)                     (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
+#define __cacheid_vipt(val)                     (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
+#define __cacheid_vipt_nonaliasing(val)         (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
+#define __cacheid_vipt_aliasing(val)            (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
+#define __cacheid_vivt_asid_tagged_instr(val)   (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
@@ -430,6 +446,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 #define cache_is_vipt()                 0
 #define cache_is_vipt_nonaliasing()     0
 #define cache_is_vipt_aliasing()        0
+#define icache_is_vivt_asid_tagged()    0
 #elif defined(CONFIG_CPU_CACHE_VIPT)
@@ -447,6 +464,12 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
                __cacheid_vipt_aliasing(__val);                         \
        })
+#define icache_is_vivt_asid_tagged()                                    \
+        ({                                                              \
+                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
+                __cacheid_vivt_asid_tagged_instr(__val);                \
+        })
 #else
 #define cache_is_vivt()                                                 \
@@ -475,6 +498,13 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
                 __cacheid_vipt_aliasing(__val);                        \
        })
+#define icache_is_vivt_asid_tagged()                                    \
+        ({                                                              \
+                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
+                __cacheid_present(__val) &&                             \
+                 __cacheid_vivt_asid_tagged_instr(__val);               \
+        })
 #endif
 #endif
diff --git a/include/asm-arm/glue.h b/include/asm-arm/glue.h
index 0cc5d3b10ce2..22274ce81375 100644
--- a/include/asm-arm/glue.h
+++ b/include/asm-arm/glue.h
@@ -38,6 +38,7 @@
 *        v5tej_early   - ARMv5 with Thumb and Java early abort handler
 *        xscale        - ARMv5 with Thumb with Xscale extensions
 *        v6_early      - ARMv6 generic early abort handler
+ *        v7_early      - ARMv7 generic early abort handler
 */
 #undef CPU_ABORT_HANDLER
 #undef MULTI_ABORT
@@ -106,6 +107,14 @@
 # endif
 #endif
+#ifdef CONFIG_CPU_ABRT_EV7
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v7_early_abort
+# endif
+#endif
 #ifndef CPU_ABORT_HANDLER
 #error Unknown data abort handler type
 #endif
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index ea7e54c319be..5599d4e5e708 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -193,6 +193,14 @@
 #   define CPU_NAME cpu_v6
 #  endif
 # endif
+# ifdef CONFIG_CPU_V7
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_v7
+#  endif
+# endif
 #endif
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 63b3080bdac4..41dd49151dae 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -14,6 +14,7 @@
 #define CPU_ARCH_ARMv5TE        6
 #define CPU_ARCH_ARMv5TEJ       7
 #define CPU_ARCH_ARMv6          8
+#define CPU_ARCH_ARMv7          9
 /*
 * CR1 bits (CP#15 CR1)
@@ -157,7 +158,11 @@ extern unsigned int user_debug;
 #define vectors_high()  (0)
 #endif
-#if defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ >= 6
+#if __LINUX_ARM_ARCH__ >= 7
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
                                    : : "r" (0) : "memory")
 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \