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-rw-r--r--arch/blackfin/mach-bf561/head.S10
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h6
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h4
3 files changed, 15 insertions, 5 deletions
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 2f08bcb2dded..38650a628980 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -440,15 +440,15 @@ ENTRY(_bfin_reset)
440 SSYNC; 440 SSYNC;
441 441
442 /* make sure SYSCR is set to use BMODE */ 442 /* make sure SYSCR is set to use BMODE */
443 P0.h = hi(SICA_SYSCR); 443 P0.h = hi(SYSCR);
444 P0.l = lo(SICA_SYSCR); 444 P0.l = lo(SYSCR);
445 R0.l = 0x20; 445 R0.l = 0x20; /* on BF561, disable core b */
446 W[P0] = R0.l; 446 W[P0] = R0.l;
447 SSYNC; 447 SSYNC;
448 448
449 /* issue a system soft reset */ 449 /* issue a system soft reset */
450 P1.h = hi(SICA_SWRST); 450 P1.h = hi(SWRST);
451 P1.l = lo(SICA_SWRST); 451 P1.l = lo(SWRST);
452 R1.l = 0x0007; 452 R1.l = 0x0007;
453 W[P1] = R1; 453 W[P1] = R1;
454 SSYNC; 454 SSYNC;
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 1a8ec9e46922..6e87ab269ffe 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -81,6 +81,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
81#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) 81#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
82#define bfin_read_CHIPID() bfin_read32(CHIPID) 82#define bfin_read_CHIPID() bfin_read32(CHIPID)
83 83
84/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
85#define bfin_read_SWRST() bfin_read_SICA_SWRST()
86#define bfin_write_SWRST() bfin_write_SICA_SWRST()
87#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
88#define bfin_write_SYSCR() bfin_write_SICA_SYSCR()
89
84/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 90/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
85#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) 91#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
86#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) 92#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val)
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 89150ecb909d..0f2dc6e6335b 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -52,6 +52,10 @@
52#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ 52#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
53#define CHIPID 0xFFC00014 /* Chip ID Register */ 53#define CHIPID 0xFFC00014 /* Chip ID Register */
54 54
55/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
56#define SWRST SICA_SWRST
57#define SYSCR SICA_SYSCR
58
55/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 59/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
56#define SICA_SWRST 0xFFC00100 /* Software Reset register */ 60#define SICA_SWRST 0xFFC00100 /* Software Reset register */
57#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ 61#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */