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-rw-r--r--Documentation/DocBook/libata.tmpl156
-rw-r--r--arch/ppc64/kernel/entry.S9
-rw-r--r--arch/ppc64/kernel/head.S10
-rw-r--r--arch/ppc64/kernel/iSeries_setup.c22
-rw-r--r--arch/ppc64/kernel/idle.c8
-rw-r--r--arch/ppc64/kernel/process.c3
-rw-r--r--arch/ppc64/kernel/setup.c56
-rw-r--r--arch/ppc64/kernel/smp.c3
-rw-r--r--arch/ppc64/kernel/sysfs.c8
-rw-r--r--drivers/net/hamradio/baycom_epp.c126
-rw-r--r--drivers/scsi/ata_piix.c16
-rw-r--r--drivers/scsi/libata-core.c470
-rw-r--r--drivers/scsi/libata-scsi.c2
-rw-r--r--fs/jbd/checkpoint.c5
-rw-r--r--include/asm-ppc64/processor.h186
-rw-r--r--include/asm-ppc64/thread_info.h4
-rw-r--r--include/linux/libata.h58
17 files changed, 707 insertions, 435 deletions
diff --git a/Documentation/DocBook/libata.tmpl b/Documentation/DocBook/libata.tmpl
index cf2fce7707da..6df1dfd18b65 100644
--- a/Documentation/DocBook/libata.tmpl
+++ b/Documentation/DocBook/libata.tmpl
@@ -14,7 +14,7 @@
14 </authorgroup> 14 </authorgroup>
15 15
16 <copyright> 16 <copyright>
17 <year>2003</year> 17 <year>2003-2005</year>
18 <holder>Jeff Garzik</holder> 18 <holder>Jeff Garzik</holder>
19 </copyright> 19 </copyright>
20 20
@@ -44,30 +44,38 @@
44 44
45<toc></toc> 45<toc></toc>
46 46
47 <chapter id="libataThanks"> 47 <chapter id="libataIntroduction">
48 <title>Thanks</title> 48 <title>Introduction</title>
49 <para> 49 <para>
50 The bulk of the ATA knowledge comes thanks to long conversations with 50 libATA is a library used inside the Linux kernel to support ATA host
51 Andre Hedrick (www.linux-ide.org). 51 controllers and devices. libATA provides an ATA driver API, class
52 transports for ATA and ATAPI devices, and SCSI&lt;-&gt;ATA translation
53 for ATA devices according to the T10 SAT specification.
52 </para> 54 </para>
53 <para> 55 <para>
54 Thanks to Alan Cox for pointing out similarities 56 This Guide documents the libATA driver API, library functions, library
55 between SATA and SCSI, and in general for motivation to hack on 57 internals, and a couple sample ATA low-level drivers.
56 libata.
57 </para>
58 <para>
59 libata's device detection
60 method, ata_pio_devchk, and in general all the early probing was
61 based on extensive study of Hale Landis's probe/reset code in his
62 ATADRVR driver (www.ata-atapi.com).
63 </para> 58 </para>
64 </chapter> 59 </chapter>
65 60
66 <chapter id="libataDriverApi"> 61 <chapter id="libataDriverApi">
67 <title>libata Driver API</title> 62 <title>libata Driver API</title>
63 <para>
64 struct ata_port_operations is defined for every low-level libata
65 hardware driver, and it controls how the low-level driver
66 interfaces with the ATA and SCSI layers.
67 </para>
68 <para>
69 FIS-based drivers will hook into the system with ->qc_prep() and
70 ->qc_issue() high-level hooks. Hardware which behaves in a manner
71 similar to PCI IDE hardware may utilize several generic helpers,
72 defining at a bare minimum the bus I/O addresses of the ATA shadow
73 register blocks.
74 </para>
68 <sect1> 75 <sect1>
69 <title>struct ata_port_operations</title> 76 <title>struct ata_port_operations</title>
70 77
78 <sect2><title>Disable ATA port</title>
71 <programlisting> 79 <programlisting>
72void (*port_disable) (struct ata_port *); 80void (*port_disable) (struct ata_port *);
73 </programlisting> 81 </programlisting>
@@ -78,6 +86,9 @@ void (*port_disable) (struct ata_port *);
78 unplug). 86 unplug).
79 </para> 87 </para>
80 88
89 </sect2>
90
91 <sect2><title>Post-IDENTIFY device configuration</title>
81 <programlisting> 92 <programlisting>
82void (*dev_config) (struct ata_port *, struct ata_device *); 93void (*dev_config) (struct ata_port *, struct ata_device *);
83 </programlisting> 94 </programlisting>
@@ -88,6 +99,9 @@ void (*dev_config) (struct ata_port *, struct ata_device *);
88 issue of SET FEATURES - XFER MODE, and prior to operation. 99 issue of SET FEATURES - XFER MODE, and prior to operation.
89 </para> 100 </para>
90 101
102 </sect2>
103
104 <sect2><title>Set PIO/DMA mode</title>
91 <programlisting> 105 <programlisting>
92void (*set_piomode) (struct ata_port *, struct ata_device *); 106void (*set_piomode) (struct ata_port *, struct ata_device *);
93void (*set_dmamode) (struct ata_port *, struct ata_device *); 107void (*set_dmamode) (struct ata_port *, struct ata_device *);
@@ -108,6 +122,9 @@ void (*post_set_mode) (struct ata_port *ap);
108 ->set_dma_mode() is only called if DMA is possible. 122 ->set_dma_mode() is only called if DMA is possible.
109 </para> 123 </para>
110 124
125 </sect2>
126
127 <sect2><title>Taskfile read/write</title>
111 <programlisting> 128 <programlisting>
112void (*tf_load) (struct ata_port *ap, struct ata_taskfile *tf); 129void (*tf_load) (struct ata_port *ap, struct ata_taskfile *tf);
113void (*tf_read) (struct ata_port *ap, struct ata_taskfile *tf); 130void (*tf_read) (struct ata_port *ap, struct ata_taskfile *tf);
@@ -120,6 +137,9 @@ void (*tf_read) (struct ata_port *ap, struct ata_taskfile *tf);
120 taskfile register values. 137 taskfile register values.
121 </para> 138 </para>
122 139
140 </sect2>
141
142 <sect2><title>ATA command execute</title>
123 <programlisting> 143 <programlisting>
124void (*exec_command)(struct ata_port *ap, struct ata_taskfile *tf); 144void (*exec_command)(struct ata_port *ap, struct ata_taskfile *tf);
125 </programlisting> 145 </programlisting>
@@ -129,17 +149,37 @@ void (*exec_command)(struct ata_port *ap, struct ata_taskfile *tf);
129 ->tf_load(), to be initiated in hardware. 149 ->tf_load(), to be initiated in hardware.
130 </para> 150 </para>
131 151
152 </sect2>
153
154 <sect2><title>Per-cmd ATAPI DMA capabilities filter</title>
155 <programlisting>
156int (*check_atapi_dma) (struct ata_queued_cmd *qc);
157 </programlisting>
158
159 <para>
160Allow low-level driver to filter ATA PACKET commands, returning a status
161indicating whether or not it is OK to use DMA for the supplied PACKET
162command.
163 </para>
164
165 </sect2>
166
167 <sect2><title>Read specific ATA shadow registers</title>
132 <programlisting> 168 <programlisting>
133u8 (*check_status)(struct ata_port *ap); 169u8 (*check_status)(struct ata_port *ap);
134void (*dev_select)(struct ata_port *ap, unsigned int device); 170u8 (*check_altstatus)(struct ata_port *ap);
171u8 (*check_err)(struct ata_port *ap);
135 </programlisting> 172 </programlisting>
136 173
137 <para> 174 <para>
138 Reads the Status ATA shadow register from hardware. On some 175 Reads the Status/AltStatus/Error ATA shadow register from
139 hardware, this has the side effect of clearing the interrupt 176 hardware. On some hardware, reading the Status register has
140 condition. 177 the side effect of clearing the interrupt condition.
141 </para> 178 </para>
142 179
180 </sect2>
181
182 <sect2><title>Select ATA device on bus</title>
143 <programlisting> 183 <programlisting>
144void (*dev_select)(struct ata_port *ap, unsigned int device); 184void (*dev_select)(struct ata_port *ap, unsigned int device);
145 </programlisting> 185 </programlisting>
@@ -147,9 +187,13 @@ void (*dev_select)(struct ata_port *ap, unsigned int device);
147 <para> 187 <para>
148 Issues the low-level hardware command(s) that causes one of N 188 Issues the low-level hardware command(s) that causes one of N
149 hardware devices to be considered 'selected' (active and 189 hardware devices to be considered 'selected' (active and
150 available for use) on the ATA bus. 190 available for use) on the ATA bus. This generally has no
191meaning on FIS-based devices.
151 </para> 192 </para>
152 193
194 </sect2>
195
196 <sect2><title>Reset ATA bus</title>
153 <programlisting> 197 <programlisting>
154void (*phy_reset) (struct ata_port *ap); 198void (*phy_reset) (struct ata_port *ap);
155 </programlisting> 199 </programlisting>
@@ -162,17 +206,31 @@ void (*phy_reset) (struct ata_port *ap);
162 functions ata_bus_reset() or sata_phy_reset() for this hook. 206 functions ata_bus_reset() or sata_phy_reset() for this hook.
163 </para> 207 </para>
164 208
209 </sect2>
210
211 <sect2><title>Control PCI IDE BMDMA engine</title>
165 <programlisting> 212 <programlisting>
166void (*bmdma_setup) (struct ata_queued_cmd *qc); 213void (*bmdma_setup) (struct ata_queued_cmd *qc);
167void (*bmdma_start) (struct ata_queued_cmd *qc); 214void (*bmdma_start) (struct ata_queued_cmd *qc);
215void (*bmdma_stop) (struct ata_port *ap);
216u8 (*bmdma_status) (struct ata_port *ap);
168 </programlisting> 217 </programlisting>
169 218
170 <para> 219 <para>
171 When setting up an IDE BMDMA transaction, these hooks arm 220When setting up an IDE BMDMA transaction, these hooks arm
172 (->bmdma_setup) and fire (->bmdma_start) the hardware's DMA 221(->bmdma_setup), fire (->bmdma_start), and halt (->bmdma_stop)
173 engine. 222the hardware's DMA engine. ->bmdma_status is used to read the standard
223PCI IDE DMA Status register.
174 </para> 224 </para>
175 225
226 <para>
227These hooks are typically either no-ops, or simply not implemented, in
228FIS-based drivers.
229 </para>
230
231 </sect2>
232
233 <sect2><title>High-level taskfile hooks</title>
176 <programlisting> 234 <programlisting>
177void (*qc_prep) (struct ata_queued_cmd *qc); 235void (*qc_prep) (struct ata_queued_cmd *qc);
178int (*qc_issue) (struct ata_queued_cmd *qc); 236int (*qc_issue) (struct ata_queued_cmd *qc);
@@ -190,20 +248,26 @@ int (*qc_issue) (struct ata_queued_cmd *qc);
190 ->qc_issue is used to make a command active, once the hardware 248 ->qc_issue is used to make a command active, once the hardware
191 and S/G tables have been prepared. IDE BMDMA drivers use the 249 and S/G tables have been prepared. IDE BMDMA drivers use the
192 helper function ata_qc_issue_prot() for taskfile protocol-based 250 helper function ata_qc_issue_prot() for taskfile protocol-based
193 dispatch. More advanced drivers roll their own ->qc_issue 251 dispatch. More advanced drivers implement their own ->qc_issue.
194 implementation, using this as the "issue new ATA command to
195 hardware" hook.
196 </para> 252 </para>
197 253
254 </sect2>
255
256 <sect2><title>Timeout (error) handling</title>
198 <programlisting> 257 <programlisting>
199void (*eng_timeout) (struct ata_port *ap); 258void (*eng_timeout) (struct ata_port *ap);
200 </programlisting> 259 </programlisting>
201 260
202 <para> 261 <para>
203 This is a high level error handling function, called from the 262This is a high level error handling function, called from the
204 error handling thread, when a command times out. 263error handling thread, when a command times out. Most newer
264hardware will implement its own error handling code here. IDE BMDMA
265drivers may use the helper function ata_eng_timeout().
205 </para> 266 </para>
206 267
268 </sect2>
269
270 <sect2><title>Hardware interrupt handling</title>
207 <programlisting> 271 <programlisting>
208irqreturn_t (*irq_handler)(int, void *, struct pt_regs *); 272irqreturn_t (*irq_handler)(int, void *, struct pt_regs *);
209void (*irq_clear) (struct ata_port *); 273void (*irq_clear) (struct ata_port *);
@@ -216,6 +280,9 @@ void (*irq_clear) (struct ata_port *);
216 is quiet. 280 is quiet.
217 </para> 281 </para>
218 282
283 </sect2>
284
285 <sect2><title>SATA phy read/write</title>
219 <programlisting> 286 <programlisting>
220u32 (*scr_read) (struct ata_port *ap, unsigned int sc_reg); 287u32 (*scr_read) (struct ata_port *ap, unsigned int sc_reg);
221void (*scr_write) (struct ata_port *ap, unsigned int sc_reg, 288void (*scr_write) (struct ata_port *ap, unsigned int sc_reg,
@@ -227,6 +294,9 @@ void (*scr_write) (struct ata_port *ap, unsigned int sc_reg,
227 if ->phy_reset hook called the sata_phy_reset() helper function. 294 if ->phy_reset hook called the sata_phy_reset() helper function.
228 </para> 295 </para>
229 296
297 </sect2>
298
299 <sect2><title>Init and shutdown</title>
230 <programlisting> 300 <programlisting>
231int (*port_start) (struct ata_port *ap); 301int (*port_start) (struct ata_port *ap);
232void (*port_stop) (struct ata_port *ap); 302void (*port_stop) (struct ata_port *ap);
@@ -240,15 +310,17 @@ void (*host_stop) (struct ata_host_set *host_set);
240 tasks. 310 tasks.
241 </para> 311 </para>
242 <para> 312 <para>
243 ->host_stop() is called when the rmmod or hot unplug process
244 begins. The hook must stop all hardware interrupts, DMA
245 engines, etc.
246 </para>
247 <para>
248 ->port_stop() is called after ->host_stop(). It's sole function 313 ->port_stop() is called after ->host_stop(). It's sole function
249 is to release DMA/memory resources, now that they are no longer 314 is to release DMA/memory resources, now that they are no longer
250 actively being used. 315 actively being used.
251 </para> 316 </para>
317 <para>
318 ->host_stop() is called after all ->port_stop() calls
319have completed. The hook must finalize hardware shutdown, release DMA
320and other resources, etc.
321 </para>
322
323 </sect2>
252 324
253 </sect1> 325 </sect1>
254 </chapter> 326 </chapter>
@@ -279,4 +351,24 @@ void (*host_stop) (struct ata_host_set *host_set);
279!Idrivers/scsi/sata_sil.c 351!Idrivers/scsi/sata_sil.c
280 </chapter> 352 </chapter>
281 353
354 <chapter id="libataThanks">
355 <title>Thanks</title>
356 <para>
357 The bulk of the ATA knowledge comes thanks to long conversations with
358 Andre Hedrick (www.linux-ide.org), and long hours pondering the ATA
359 and SCSI specifications.
360 </para>
361 <para>
362 Thanks to Alan Cox for pointing out similarities
363 between SATA and SCSI, and in general for motivation to hack on
364 libata.
365 </para>
366 <para>
367 libata's device detection
368 method, ata_pio_devchk, and in general all the early probing was
369 based on extensive study of Hale Landis's probe/reset code in his
370 ATADRVR driver (www.ata-atapi.com).
371 </para>
372 </chapter>
373
282</book> 374</book>
diff --git a/arch/ppc64/kernel/entry.S b/arch/ppc64/kernel/entry.S
index d3604056e1a9..b61572eb2a71 100644
--- a/arch/ppc64/kernel/entry.S
+++ b/arch/ppc64/kernel/entry.S
@@ -436,15 +436,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
436 REST_8GPRS(14, r1) 436 REST_8GPRS(14, r1)
437 REST_10GPRS(22, r1) 437 REST_10GPRS(22, r1)
438 438
439#ifdef CONFIG_PPC_ISERIES
440 clrrdi r7,r1,THREAD_SHIFT /* get current_thread_info() */
441 ld r7,TI_FLAGS(r7) /* Get run light flag */
442 mfspr r9,CTRLF
443 srdi r7,r7,TIF_RUN_LIGHT
444 insrdi r9,r7,1,63 /* Insert run light into CTRL */
445 mtspr CTRLT,r9
446#endif
447
448 /* convert old thread to its task_struct for return value */ 439 /* convert old thread to its task_struct for return value */
449 addi r3,r3,-THREAD 440 addi r3,r3,-THREAD
450 ld r7,_NIP(r1) /* Return to _switch caller in new task */ 441 ld r7,_NIP(r1) /* Return to _switch caller in new task */
diff --git a/arch/ppc64/kernel/head.S b/arch/ppc64/kernel/head.S
index 92a744c31ab1..346dbf606b5d 100644
--- a/arch/ppc64/kernel/head.S
+++ b/arch/ppc64/kernel/head.S
@@ -626,10 +626,10 @@ system_reset_iSeries:
626 lhz r24,PACAPACAINDEX(r13) /* Get processor # */ 626 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
627 cmpwi 0,r24,0 /* Are we processor 0? */ 627 cmpwi 0,r24,0 /* Are we processor 0? */
628 beq .__start_initialization_iSeries /* Start up the first processor */ 628 beq .__start_initialization_iSeries /* Start up the first processor */
629 mfspr r4,CTRLF 629 mfspr r4,SPRN_CTRLF
630 li r5,RUNLATCH /* Turn off the run light */ 630 li r5,CTRL_RUNLATCH /* Turn off the run light */
631 andc r4,r4,r5 631 andc r4,r4,r5
632 mtspr CTRLT,r4 632 mtspr SPRN_CTRLT,r4
633 633
6341: 6341:
635 HMT_LOW 635 HMT_LOW
@@ -2082,9 +2082,9 @@ _GLOBAL(hmt_start_secondary)
2082 mfspr r4, HID0 2082 mfspr r4, HID0
2083 ori r4, r4, 0x1 2083 ori r4, r4, 0x1
2084 mtspr HID0, r4 2084 mtspr HID0, r4
2085 mfspr r4, CTRLF 2085 mfspr r4, SPRN_CTRLF
2086 oris r4, r4, 0x40 2086 oris r4, r4, 0x40
2087 mtspr CTRLT, r4 2087 mtspr SPRN_CTRLT, r4
2088 blr 2088 blr
2089#endif 2089#endif
2090 2090
diff --git a/arch/ppc64/kernel/iSeries_setup.c b/arch/ppc64/kernel/iSeries_setup.c
index da20120f2261..6d06eb550a3f 100644
--- a/arch/ppc64/kernel/iSeries_setup.c
+++ b/arch/ppc64/kernel/iSeries_setup.c
@@ -852,6 +852,28 @@ static int __init iSeries_src_init(void)
852 852
853late_initcall(iSeries_src_init); 853late_initcall(iSeries_src_init);
854 854
855static int set_spread_lpevents(char *str)
856{
857 unsigned long i;
858 unsigned long val = simple_strtoul(str, NULL, 0);
859
860 /*
861 * The parameter is the number of processors to share in processing
862 * lp events.
863 */
864 if (( val > 0) && (val <= NR_CPUS)) {
865 for (i = 1; i < val; ++i)
866 paca[i].lpqueue_ptr = paca[0].lpqueue_ptr;
867
868 printk("lpevent processing spread over %ld processors\n", val);
869 } else {
870 printk("invalid spread_lpevents %ld\n", val);
871 }
872
873 return 1;
874}
875__setup("spread_lpevents=", set_spread_lpevents);
876
855void __init iSeries_early_setup(void) 877void __init iSeries_early_setup(void)
856{ 878{
857 iSeries_fixup_klimit(); 879 iSeries_fixup_klimit();
diff --git a/arch/ppc64/kernel/idle.c b/arch/ppc64/kernel/idle.c
index 6abc621d3ba0..f24ce2b87200 100644
--- a/arch/ppc64/kernel/idle.c
+++ b/arch/ppc64/kernel/idle.c
@@ -75,13 +75,9 @@ static int iSeries_idle(void)
75{ 75{
76 struct paca_struct *lpaca; 76 struct paca_struct *lpaca;
77 long oldval; 77 long oldval;
78 unsigned long CTRL;
79 78
80 /* ensure iSeries run light will be out when idle */ 79 /* ensure iSeries run light will be out when idle */
81 clear_thread_flag(TIF_RUN_LIGHT); 80 ppc64_runlatch_off();
82 CTRL = mfspr(CTRLF);
83 CTRL &= ~RUNLATCH;
84 mtspr(CTRLT, CTRL);
85 81
86 lpaca = get_paca(); 82 lpaca = get_paca();
87 83
@@ -111,7 +107,9 @@ static int iSeries_idle(void)
111 } 107 }
112 } 108 }
113 109
110 ppc64_runlatch_on();
114 schedule(); 111 schedule();
112 ppc64_runlatch_off();
115 } 113 }
116 114
117 return 0; 115 return 0;
diff --git a/arch/ppc64/kernel/process.c b/arch/ppc64/kernel/process.c
index 8b0686122738..cdfecbeb331f 100644
--- a/arch/ppc64/kernel/process.c
+++ b/arch/ppc64/kernel/process.c
@@ -378,9 +378,6 @@ copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
378 childregs->gpr[1] = sp + sizeof(struct pt_regs); 378 childregs->gpr[1] = sp + sizeof(struct pt_regs);
379 p->thread.regs = NULL; /* no user register state */ 379 p->thread.regs = NULL; /* no user register state */
380 clear_ti_thread_flag(p->thread_info, TIF_32BIT); 380 clear_ti_thread_flag(p->thread_info, TIF_32BIT);
381#ifdef CONFIG_PPC_ISERIES
382 set_ti_thread_flag(p->thread_info, TIF_RUN_LIGHT);
383#endif
384 } else { 381 } else {
385 childregs->gpr[1] = usp; 382 childregs->gpr[1] = usp;
386 p->thread.regs = childregs; 383 p->thread.regs = childregs;
diff --git a/arch/ppc64/kernel/setup.c b/arch/ppc64/kernel/setup.c
index 21c57f539c29..dce198d39328 100644
--- a/arch/ppc64/kernel/setup.c
+++ b/arch/ppc64/kernel/setup.c
@@ -103,11 +103,6 @@ extern void unflatten_device_tree(void);
103 103
104extern void smp_release_cpus(void); 104extern void smp_release_cpus(void);
105 105
106unsigned long decr_overclock = 1;
107unsigned long decr_overclock_proc0 = 1;
108unsigned long decr_overclock_set = 0;
109unsigned long decr_overclock_proc0_set = 0;
110
111int have_of = 1; 106int have_of = 1;
112int boot_cpuid = 0; 107int boot_cpuid = 0;
113int boot_cpuid_phys = 0; 108int boot_cpuid_phys = 0;
@@ -1120,64 +1115,15 @@ void ppc64_dump_msg(unsigned int src, const char *msg)
1120 printk("[dump]%04x %s\n", src, msg); 1115 printk("[dump]%04x %s\n", src, msg);
1121} 1116}
1122 1117
1123int set_spread_lpevents( char * str )
1124{
1125 /* The parameter is the number of processors to share in processing lp events */
1126 unsigned long i;
1127 unsigned long val = simple_strtoul( str, NULL, 0 );
1128 if ( ( val > 0 ) && ( val <= NR_CPUS ) ) {
1129 for ( i=1; i<val; ++i )
1130 paca[i].lpqueue_ptr = paca[0].lpqueue_ptr;
1131 printk("lpevent processing spread over %ld processors\n", val);
1132 }
1133 else
1134 printk("invalid spreaqd_lpevents %ld\n", val);
1135 return 1;
1136}
1137
1138/* This should only be called on processor 0 during calibrate decr */ 1118/* This should only be called on processor 0 during calibrate decr */
1139void setup_default_decr(void) 1119void setup_default_decr(void)
1140{ 1120{
1141 struct paca_struct *lpaca = get_paca(); 1121 struct paca_struct *lpaca = get_paca();
1142 1122
1143 if ( decr_overclock_set && !decr_overclock_proc0_set ) 1123 lpaca->default_decr = tb_ticks_per_jiffy;
1144 decr_overclock_proc0 = decr_overclock;
1145
1146 lpaca->default_decr = tb_ticks_per_jiffy / decr_overclock_proc0;
1147 lpaca->next_jiffy_update_tb = get_tb() + tb_ticks_per_jiffy; 1124 lpaca->next_jiffy_update_tb = get_tb() + tb_ticks_per_jiffy;
1148} 1125}
1149 1126
1150int set_decr_overclock_proc0( char * str )
1151{
1152 unsigned long val = simple_strtoul( str, NULL, 0 );
1153 if ( ( val >= 1 ) && ( val <= 48 ) ) {
1154 decr_overclock_proc0_set = 1;
1155 decr_overclock_proc0 = val;
1156 printk("proc 0 decrementer overclock factor of %ld\n", val);
1157 }
1158 else
1159 printk("invalid proc 0 decrementer overclock factor of %ld\n", val);
1160 return 1;
1161}
1162
1163int set_decr_overclock( char * str )
1164{
1165 unsigned long val = simple_strtoul( str, NULL, 0 );
1166 if ( ( val >= 1 ) && ( val <= 48 ) ) {
1167 decr_overclock_set = 1;
1168 decr_overclock = val;
1169 printk("decrementer overclock factor of %ld\n", val);
1170 }
1171 else
1172 printk("invalid decrementer overclock factor of %ld\n", val);
1173 return 1;
1174
1175}
1176
1177__setup("spread_lpevents=", set_spread_lpevents );
1178__setup("decr_overclock_proc0=", set_decr_overclock_proc0 );
1179__setup("decr_overclock=", set_decr_overclock );
1180
1181#ifndef CONFIG_PPC_ISERIES 1127#ifndef CONFIG_PPC_ISERIES
1182/* 1128/*
1183 * This function can be used by platforms to "find" legacy serial ports. 1129 * This function can be used by platforms to "find" legacy serial ports.
diff --git a/arch/ppc64/kernel/smp.c b/arch/ppc64/kernel/smp.c
index 3b906cd94037..9ef5d36d6b25 100644
--- a/arch/ppc64/kernel/smp.c
+++ b/arch/ppc64/kernel/smp.c
@@ -334,7 +334,6 @@ void smp_call_function_interrupt(void)
334 } 334 }
335} 335}
336 336
337extern unsigned long decr_overclock;
338extern struct gettimeofday_struct do_gtod; 337extern struct gettimeofday_struct do_gtod;
339 338
340struct thread_info *current_set[NR_CPUS]; 339struct thread_info *current_set[NR_CPUS];
@@ -491,7 +490,7 @@ int __devinit __cpu_up(unsigned int cpu)
491 if (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu)) 490 if (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))
492 return -EINVAL; 491 return -EINVAL;
493 492
494 paca[cpu].default_decr = tb_ticks_per_jiffy / decr_overclock; 493 paca[cpu].default_decr = tb_ticks_per_jiffy;
495 494
496 if (!cpu_has_feature(CPU_FTR_SLB)) { 495 if (!cpu_has_feature(CPU_FTR_SLB)) {
497 void *tmp; 496 void *tmp;
diff --git a/arch/ppc64/kernel/sysfs.c b/arch/ppc64/kernel/sysfs.c
index 0925694c3ce5..c8fa6569b2fd 100644
--- a/arch/ppc64/kernel/sysfs.c
+++ b/arch/ppc64/kernel/sysfs.c
@@ -113,7 +113,6 @@ void ppc64_enable_pmcs(void)
113#ifdef CONFIG_PPC_PSERIES 113#ifdef CONFIG_PPC_PSERIES
114 unsigned long set, reset; 114 unsigned long set, reset;
115 int ret; 115 int ret;
116 unsigned int ctrl;
117#endif /* CONFIG_PPC_PSERIES */ 116#endif /* CONFIG_PPC_PSERIES */
118 117
119 /* Only need to enable them once */ 118 /* Only need to enable them once */
@@ -167,11 +166,8 @@ void ppc64_enable_pmcs(void)
167 * On SMT machines we have to set the run latch in the ctrl register 166 * On SMT machines we have to set the run latch in the ctrl register
168 * in order to make PMC6 spin. 167 * in order to make PMC6 spin.
169 */ 168 */
170 if (cpu_has_feature(CPU_FTR_SMT)) { 169 if (cpu_has_feature(CPU_FTR_SMT))
171 ctrl = mfspr(CTRLF); 170 ppc64_runlatch_on();
172 ctrl |= RUNLATCH;
173 mtspr(CTRLT, ctrl);
174 }
175#endif /* CONFIG_PPC_PSERIES */ 171#endif /* CONFIG_PPC_PSERIES */
176} 172}
177 173
diff --git a/drivers/net/hamradio/baycom_epp.c b/drivers/net/hamradio/baycom_epp.c
index 1c563f905a59..a7f15d9f13e5 100644
--- a/drivers/net/hamradio/baycom_epp.c
+++ b/drivers/net/hamradio/baycom_epp.c
@@ -374,29 +374,6 @@ static inline void do_kiss_params(struct baycom_state *bc,
374} 374}
375 375
376/* --------------------------------------------------------------------- */ 376/* --------------------------------------------------------------------- */
377/*
378 * high performance HDLC encoder
379 * yes, it's ugly, but generates pretty good code
380 */
381
382#define ENCODEITERA(j) \
383({ \
384 if (!(notbitstream & (0x1f0 << j))) \
385 goto stuff##j; \
386 encodeend##j: ; \
387})
388
389#define ENCODEITERB(j) \
390({ \
391 stuff##j: \
392 bitstream &= ~(0x100 << j); \
393 bitbuf = (bitbuf & (((2 << j) << numbit) - 1)) | \
394 ((bitbuf & ~(((2 << j) << numbit) - 1)) << 1); \
395 numbit++; \
396 notbitstream = ~bitstream; \
397 goto encodeend##j; \
398})
399
400 377
401static void encode_hdlc(struct baycom_state *bc) 378static void encode_hdlc(struct baycom_state *bc)
402{ 379{
@@ -405,6 +382,7 @@ static void encode_hdlc(struct baycom_state *bc)
405 int pkt_len; 382 int pkt_len;
406 unsigned bitstream, notbitstream, bitbuf, numbit, crc; 383 unsigned bitstream, notbitstream, bitbuf, numbit, crc;
407 unsigned char crcarr[2]; 384 unsigned char crcarr[2];
385 int j;
408 386
409 if (bc->hdlctx.bufcnt > 0) 387 if (bc->hdlctx.bufcnt > 0)
410 return; 388 return;
@@ -429,24 +407,14 @@ static void encode_hdlc(struct baycom_state *bc)
429 pkt_len--; 407 pkt_len--;
430 if (!pkt_len) 408 if (!pkt_len)
431 bp = crcarr; 409 bp = crcarr;
432 ENCODEITERA(0); 410 for (j = 0; j < 8; j++)
433 ENCODEITERA(1); 411 if (unlikely(!(notbitstream & (0x1f0 << j)))) {
434 ENCODEITERA(2); 412 bitstream &= ~(0x100 << j);
435 ENCODEITERA(3); 413 bitbuf = (bitbuf & (((2 << j) << numbit) - 1)) |
436 ENCODEITERA(4); 414 ((bitbuf & ~(((2 << j) << numbit) - 1)) << 1);
437 ENCODEITERA(5); 415 numbit++;
438 ENCODEITERA(6); 416 notbitstream = ~bitstream;
439 ENCODEITERA(7); 417 }
440 goto enditer;
441 ENCODEITERB(0);
442 ENCODEITERB(1);
443 ENCODEITERB(2);
444 ENCODEITERB(3);
445 ENCODEITERB(4);
446 ENCODEITERB(5);
447 ENCODEITERB(6);
448 ENCODEITERB(7);
449 enditer:
450 numbit += 8; 418 numbit += 8;
451 while (numbit >= 8) { 419 while (numbit >= 8) {
452 *wp++ = bitbuf; 420 *wp++ = bitbuf;
@@ -610,37 +578,6 @@ static void do_rxpacket(struct net_device *dev)
610 bc->stats.rx_packets++; 578 bc->stats.rx_packets++;
611} 579}
612 580
613#define DECODEITERA(j) \
614({ \
615 if (!(notbitstream & (0x0fc << j))) /* flag or abort */ \
616 goto flgabrt##j; \
617 if ((bitstream & (0x1f8 << j)) == (0xf8 << j)) /* stuffed bit */ \
618 goto stuff##j; \
619 enditer##j: ; \
620})
621
622#define DECODEITERB(j) \
623({ \
624 flgabrt##j: \
625 if (!(notbitstream & (0x1fc << j))) { /* abort received */ \
626 state = 0; \
627 goto enditer##j; \
628 } \
629 if ((bitstream & (0x1fe << j)) != (0x0fc << j)) /* flag received */ \
630 goto enditer##j; \
631 if (state) \
632 do_rxpacket(dev); \
633 bc->hdlcrx.bufcnt = 0; \
634 bc->hdlcrx.bufptr = bc->hdlcrx.buf; \
635 state = 1; \
636 numbits = 7-j; \
637 goto enditer##j; \
638 stuff##j: \
639 numbits--; \
640 bitbuf = (bitbuf & ((~0xff) << j)) | ((bitbuf & ~((~0xff) << j)) << 1); \
641 goto enditer##j; \
642})
643
644static int receive(struct net_device *dev, int cnt) 581static int receive(struct net_device *dev, int cnt)
645{ 582{
646 struct baycom_state *bc = netdev_priv(dev); 583 struct baycom_state *bc = netdev_priv(dev);
@@ -649,6 +586,7 @@ static int receive(struct net_device *dev, int cnt)
649 unsigned char tmp[128]; 586 unsigned char tmp[128];
650 unsigned char *cp; 587 unsigned char *cp;
651 int cnt2, ret = 0; 588 int cnt2, ret = 0;
589 int j;
652 590
653 numbits = bc->hdlcrx.numbits; 591 numbits = bc->hdlcrx.numbits;
654 state = bc->hdlcrx.state; 592 state = bc->hdlcrx.state;
@@ -669,24 +607,32 @@ static int receive(struct net_device *dev, int cnt)
669 bitbuf |= (*cp) << 8; 607 bitbuf |= (*cp) << 8;
670 numbits += 8; 608 numbits += 8;
671 notbitstream = ~bitstream; 609 notbitstream = ~bitstream;
672 DECODEITERA(0); 610 for (j = 0; j < 8; j++) {
673 DECODEITERA(1); 611
674 DECODEITERA(2); 612 /* flag or abort */
675 DECODEITERA(3); 613 if (unlikely(!(notbitstream & (0x0fc << j)))) {
676 DECODEITERA(4); 614
677 DECODEITERA(5); 615 /* abort received */
678 DECODEITERA(6); 616 if (!(notbitstream & (0x1fc << j)))
679 DECODEITERA(7); 617 state = 0;
680 goto enddec; 618
681 DECODEITERB(0); 619 /* not flag received */
682 DECODEITERB(1); 620 else if (!(bitstream & (0x1fe << j)) != (0x0fc << j)) {
683 DECODEITERB(2); 621 if (state)
684 DECODEITERB(3); 622 do_rxpacket(dev);
685 DECODEITERB(4); 623 bc->hdlcrx.bufcnt = 0;
686 DECODEITERB(5); 624 bc->hdlcrx.bufptr = bc->hdlcrx.buf;
687 DECODEITERB(6); 625 state = 1;
688 DECODEITERB(7); 626 numbits = 7-j;
689 enddec: 627 }
628 }
629
630 /* stuffed bit */
631 else if (unlikely((bitstream & (0x1f8 << j)) == (0xf8 << j))) {
632 numbits--;
633 bitbuf = (bitbuf & ((~0xff) << j)) | ((bitbuf & ~((~0xff) << j)) << 1);
634 }
635 }
690 while (state && numbits >= 8) { 636 while (state && numbits >= 8) {
691 if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) { 637 if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) {
692 state = 0; 638 state = 0;
diff --git a/drivers/scsi/ata_piix.c b/drivers/scsi/ata_piix.c
index 54c52349adc5..3be546439252 100644
--- a/drivers/scsi/ata_piix.c
+++ b/drivers/scsi/ata_piix.c
@@ -665,15 +665,6 @@ static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
665 return ata_pci_init_one(pdev, port_info, n_ports); 665 return ata_pci_init_one(pdev, port_info, n_ports);
666} 666}
667 667
668/**
669 * piix_init -
670 *
671 * LOCKING:
672 *
673 * RETURNS:
674 *
675 */
676
677static int __init piix_init(void) 668static int __init piix_init(void)
678{ 669{
679 int rc; 670 int rc;
@@ -689,13 +680,6 @@ static int __init piix_init(void)
689 return 0; 680 return 0;
690} 681}
691 682
692/**
693 * piix_exit -
694 *
695 * LOCKING:
696 *
697 */
698
699static void __exit piix_exit(void) 683static void __exit piix_exit(void)
700{ 684{
701 pci_unregister_driver(&piix_pci_driver); 685 pci_unregister_driver(&piix_pci_driver);
diff --git a/drivers/scsi/libata-core.c b/drivers/scsi/libata-core.c
index 30a88f0e7bd6..21d194c6ace3 100644
--- a/drivers/scsi/libata-core.c
+++ b/drivers/scsi/libata-core.c
@@ -186,6 +186,28 @@ static void ata_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
186 ata_wait_idle(ap); 186 ata_wait_idle(ap);
187} 187}
188 188
189
190/**
191 * ata_tf_load - send taskfile registers to host controller
192 * @ap: Port to which output is sent
193 * @tf: ATA taskfile register set
194 *
195 * Outputs ATA taskfile to standard ATA host controller using MMIO
196 * or PIO as indicated by the ATA_FLAG_MMIO flag.
197 * Writes the control, feature, nsect, lbal, lbam, and lbah registers.
198 * Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect,
199 * hob_lbal, hob_lbam, and hob_lbah.
200 *
201 * This function waits for idle (!BUSY and !DRQ) after writing
202 * registers. If the control register has a new value, this
203 * function also waits for idle after writing control and before
204 * writing the remaining registers.
205 *
206 * May be used as the tf_load() entry in ata_port_operations.
207 *
208 * LOCKING:
209 * Inherited from caller.
210 */
189void ata_tf_load(struct ata_port *ap, struct ata_taskfile *tf) 211void ata_tf_load(struct ata_port *ap, struct ata_taskfile *tf)
190{ 212{
191 if (ap->flags & ATA_FLAG_MMIO) 213 if (ap->flags & ATA_FLAG_MMIO)
@@ -195,11 +217,11 @@ void ata_tf_load(struct ata_port *ap, struct ata_taskfile *tf)
195} 217}
196 218
197/** 219/**
198 * ata_exec_command - issue ATA command to host controller 220 * ata_exec_command_pio - issue ATA command to host controller
199 * @ap: port to which command is being issued 221 * @ap: port to which command is being issued
200 * @tf: ATA taskfile register set 222 * @tf: ATA taskfile register set
201 * 223 *
202 * Issues PIO/MMIO write to ATA command register, with proper 224 * Issues PIO write to ATA command register, with proper
203 * synchronization with interrupt handler / other threads. 225 * synchronization with interrupt handler / other threads.
204 * 226 *
205 * LOCKING: 227 * LOCKING:
@@ -235,6 +257,18 @@ static void ata_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
235 ata_pause(ap); 257 ata_pause(ap);
236} 258}
237 259
260
261/**
262 * ata_exec_command - issue ATA command to host controller
263 * @ap: port to which command is being issued
264 * @tf: ATA taskfile register set
265 *
266 * Issues PIO/MMIO write to ATA command register, with proper
267 * synchronization with interrupt handler / other threads.
268 *
269 * LOCKING:
270 * spin_lock_irqsave(host_set lock)
271 */
238void ata_exec_command(struct ata_port *ap, struct ata_taskfile *tf) 272void ata_exec_command(struct ata_port *ap, struct ata_taskfile *tf)
239{ 273{
240 if (ap->flags & ATA_FLAG_MMIO) 274 if (ap->flags & ATA_FLAG_MMIO)
@@ -305,7 +339,7 @@ void ata_tf_to_host_nolock(struct ata_port *ap, struct ata_taskfile *tf)
305} 339}
306 340
307/** 341/**
308 * ata_tf_read - input device's ATA taskfile shadow registers 342 * ata_tf_read_pio - input device's ATA taskfile shadow registers
309 * @ap: Port from which input is read 343 * @ap: Port from which input is read
310 * @tf: ATA taskfile register set for storing input 344 * @tf: ATA taskfile register set for storing input
311 * 345 *
@@ -368,6 +402,23 @@ static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf)
368 } 402 }
369} 403}
370 404
405
406/**
407 * ata_tf_read - input device's ATA taskfile shadow registers
408 * @ap: Port from which input is read
409 * @tf: ATA taskfile register set for storing input
410 *
411 * Reads ATA taskfile registers for currently-selected device
412 * into @tf.
413 *
414 * Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48
415 * is set, also reads the hob registers.
416 *
417 * May be used as the tf_read() entry in ata_port_operations.
418 *
419 * LOCKING:
420 * Inherited from caller.
421 */
371void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 422void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
372{ 423{
373 if (ap->flags & ATA_FLAG_MMIO) 424 if (ap->flags & ATA_FLAG_MMIO)
@@ -381,7 +432,7 @@ void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
381 * @ap: port where the device is 432 * @ap: port where the device is
382 * 433 *
383 * Reads ATA taskfile status register for currently-selected device 434 * Reads ATA taskfile status register for currently-selected device
384 * and return it's value. This also clears pending interrupts 435 * and return its value. This also clears pending interrupts
385 * from this device 436 * from this device
386 * 437 *
387 * LOCKING: 438 * LOCKING:
@@ -397,7 +448,7 @@ static u8 ata_check_status_pio(struct ata_port *ap)
397 * @ap: port where the device is 448 * @ap: port where the device is
398 * 449 *
399 * Reads ATA taskfile status register for currently-selected device 450 * Reads ATA taskfile status register for currently-selected device
400 * via MMIO and return it's value. This also clears pending interrupts 451 * via MMIO and return its value. This also clears pending interrupts
401 * from this device 452 * from this device
402 * 453 *
403 * LOCKING: 454 * LOCKING:
@@ -408,6 +459,20 @@ static u8 ata_check_status_mmio(struct ata_port *ap)
408 return readb((void __iomem *) ap->ioaddr.status_addr); 459 return readb((void __iomem *) ap->ioaddr.status_addr);
409} 460}
410 461
462
463/**
464 * ata_check_status - Read device status reg & clear interrupt
465 * @ap: port where the device is
466 *
467 * Reads ATA taskfile status register for currently-selected device
468 * and return its value. This also clears pending interrupts
469 * from this device
470 *
471 * May be used as the check_status() entry in ata_port_operations.
472 *
473 * LOCKING:
474 * Inherited from caller.
475 */
411u8 ata_check_status(struct ata_port *ap) 476u8 ata_check_status(struct ata_port *ap)
412{ 477{
413 if (ap->flags & ATA_FLAG_MMIO) 478 if (ap->flags & ATA_FLAG_MMIO)
@@ -415,6 +480,20 @@ u8 ata_check_status(struct ata_port *ap)
415 return ata_check_status_pio(ap); 480 return ata_check_status_pio(ap);
416} 481}
417 482
483
484/**
485 * ata_altstatus - Read device alternate status reg
486 * @ap: port where the device is
487 *
488 * Reads ATA taskfile alternate status register for
489 * currently-selected device and return its value.
490 *
491 * Note: may NOT be used as the check_altstatus() entry in
492 * ata_port_operations.
493 *
494 * LOCKING:
495 * Inherited from caller.
496 */
418u8 ata_altstatus(struct ata_port *ap) 497u8 ata_altstatus(struct ata_port *ap)
419{ 498{
420 if (ap->ops->check_altstatus) 499 if (ap->ops->check_altstatus)
@@ -425,6 +504,20 @@ u8 ata_altstatus(struct ata_port *ap)
425 return inb(ap->ioaddr.altstatus_addr); 504 return inb(ap->ioaddr.altstatus_addr);
426} 505}
427 506
507
508/**
509 * ata_chk_err - Read device error reg
510 * @ap: port where the device is
511 *
512 * Reads ATA taskfile error register for
513 * currently-selected device and return its value.
514 *
515 * Note: may NOT be used as the check_err() entry in
516 * ata_port_operations.
517 *
518 * LOCKING:
519 * Inherited from caller.
520 */
428u8 ata_chk_err(struct ata_port *ap) 521u8 ata_chk_err(struct ata_port *ap)
429{ 522{
430 if (ap->ops->check_err) 523 if (ap->ops->check_err)
@@ -873,10 +966,24 @@ void ata_dev_id_string(u16 *id, unsigned char *s,
873 } 966 }
874} 967}
875 968
969
970/**
971 * ata_noop_dev_select - Select device 0/1 on ATA bus
972 * @ap: ATA channel to manipulate
973 * @device: ATA device (numbered from zero) to select
974 *
975 * This function performs no actual function.
976 *
977 * May be used as the dev_select() entry in ata_port_operations.
978 *
979 * LOCKING:
980 * caller.
981 */
876void ata_noop_dev_select (struct ata_port *ap, unsigned int device) 982void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
877{ 983{
878} 984}
879 985
986
880/** 987/**
881 * ata_std_dev_select - Select device 0/1 on ATA bus 988 * ata_std_dev_select - Select device 0/1 on ATA bus
882 * @ap: ATA channel to manipulate 989 * @ap: ATA channel to manipulate
@@ -884,7 +991,9 @@ void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
884 * 991 *
885 * Use the method defined in the ATA specification to 992 * Use the method defined in the ATA specification to
886 * make either device 0, or device 1, active on the 993 * make either device 0, or device 1, active on the
887 * ATA channel. 994 * ATA channel. Works with both PIO and MMIO.
995 *
996 * May be used as the dev_select() entry in ata_port_operations.
888 * 997 *
889 * LOCKING: 998 * LOCKING:
890 * caller. 999 * caller.
@@ -1190,7 +1299,12 @@ err_out:
1190 * ata_bus_probe - Reset and probe ATA bus 1299 * ata_bus_probe - Reset and probe ATA bus
1191 * @ap: Bus to probe 1300 * @ap: Bus to probe
1192 * 1301 *
1302 * Master ATA bus probing function. Initiates a hardware-dependent
1303 * bus reset, then attempts to identify any devices found on
1304 * the bus.
1305 *
1193 * LOCKING: 1306 * LOCKING:
1307 * PCI/etc. bus probe sem.
1194 * 1308 *
1195 * RETURNS: 1309 * RETURNS:
1196 * Zero on success, non-zero on error. 1310 * Zero on success, non-zero on error.
@@ -1229,10 +1343,14 @@ err_out:
1229} 1343}
1230 1344
1231/** 1345/**
1232 * ata_port_probe - 1346 * ata_port_probe - Mark port as enabled
1233 * @ap: 1347 * @ap: Port for which we indicate enablement
1234 * 1348 *
1235 * LOCKING: 1349 * Modify @ap data structure such that the system
1350 * thinks that the entire port is enabled.
1351 *
1352 * LOCKING: host_set lock, or some other form of
1353 * serialization.
1236 */ 1354 */
1237 1355
1238void ata_port_probe(struct ata_port *ap) 1356void ata_port_probe(struct ata_port *ap)
@@ -1241,10 +1359,15 @@ void ata_port_probe(struct ata_port *ap)
1241} 1359}
1242 1360
1243/** 1361/**
1244 * __sata_phy_reset - 1362 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1245 * @ap: 1363 * @ap: SATA port associated with target SATA PHY.
1364 *
1365 * This function issues commands to standard SATA Sxxx
1366 * PHY registers, to wake up the phy (and device), and
1367 * clear any reset condition.
1246 * 1368 *
1247 * LOCKING: 1369 * LOCKING:
1370 * PCI/etc. bus probe sem.
1248 * 1371 *
1249 */ 1372 */
1250void __sata_phy_reset(struct ata_port *ap) 1373void __sata_phy_reset(struct ata_port *ap)
@@ -1289,10 +1412,14 @@ void __sata_phy_reset(struct ata_port *ap)
1289} 1412}
1290 1413
1291/** 1414/**
1292 * __sata_phy_reset - 1415 * sata_phy_reset - Reset SATA bus.
1293 * @ap: 1416 * @ap: SATA port associated with target SATA PHY.
1417 *
1418 * This function resets the SATA bus, and then probes
1419 * the bus for devices.
1294 * 1420 *
1295 * LOCKING: 1421 * LOCKING:
1422 * PCI/etc. bus probe sem.
1296 * 1423 *
1297 */ 1424 */
1298void sata_phy_reset(struct ata_port *ap) 1425void sata_phy_reset(struct ata_port *ap)
@@ -1304,10 +1431,16 @@ void sata_phy_reset(struct ata_port *ap)
1304} 1431}
1305 1432
1306/** 1433/**
1307 * ata_port_disable - 1434 * ata_port_disable - Disable port.
1308 * @ap: 1435 * @ap: Port to be disabled.
1309 * 1436 *
1310 * LOCKING: 1437 * Modify @ap data structure such that the system
1438 * thinks that the entire port is disabled, and should
1439 * never attempt to probe or communicate with devices
1440 * on this port.
1441 *
1442 * LOCKING: host_set lock, or some other form of
1443 * serialization.
1311 */ 1444 */
1312 1445
1313void ata_port_disable(struct ata_port *ap) 1446void ata_port_disable(struct ata_port *ap)
@@ -1416,7 +1549,10 @@ static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1416 * ata_set_mode - Program timings and issue SET FEATURES - XFER 1549 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1417 * @ap: port on which timings will be programmed 1550 * @ap: port on which timings will be programmed
1418 * 1551 *
1552 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1553 *
1419 * LOCKING: 1554 * LOCKING:
1555 * PCI/etc. bus probe sem.
1420 * 1556 *
1421 */ 1557 */
1422static void ata_set_mode(struct ata_port *ap) 1558static void ata_set_mode(struct ata_port *ap)
@@ -1467,7 +1603,10 @@ err_out:
1467 * @tmout_pat: impatience timeout 1603 * @tmout_pat: impatience timeout
1468 * @tmout: overall timeout 1604 * @tmout: overall timeout
1469 * 1605 *
1470 * LOCKING: 1606 * Sleep until ATA Status register bit BSY clears,
1607 * or a timeout occurs.
1608 *
1609 * LOCKING: None.
1471 * 1610 *
1472 */ 1611 */
1473 1612
@@ -1553,10 +1692,14 @@ static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1553} 1692}
1554 1693
1555/** 1694/**
1556 * ata_bus_edd - 1695 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
1557 * @ap: 1696 * @ap: Port to reset and probe
1697 *
1698 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
1699 * probe the bus. Not often used these days.
1558 * 1700 *
1559 * LOCKING: 1701 * LOCKING:
1702 * PCI/etc. bus probe sem.
1560 * 1703 *
1561 */ 1704 */
1562 1705
@@ -1633,8 +1776,8 @@ static unsigned int ata_bus_softreset(struct ata_port *ap,
1633 * the device is ATA or ATAPI. 1776 * the device is ATA or ATAPI.
1634 * 1777 *
1635 * LOCKING: 1778 * LOCKING:
1636 * Inherited from caller. Some functions called by this function 1779 * PCI/etc. bus probe sem.
1637 * obtain the host_set lock. 1780 * Obtains host_set lock.
1638 * 1781 *
1639 * SIDE EFFECTS: 1782 * SIDE EFFECTS:
1640 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails. 1783 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
@@ -1876,7 +2019,11 @@ static int fgb(u32 bitmap)
1876 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code 2019 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code
1877 * @xfer_shift_out: (output) bit shift that selects this mode 2020 * @xfer_shift_out: (output) bit shift that selects this mode
1878 * 2021 *
2022 * Based on host and device capabilities, determine the
2023 * maximum transfer mode that is amenable to all.
2024 *
1879 * LOCKING: 2025 * LOCKING:
2026 * PCI/etc. bus probe sem.
1880 * 2027 *
1881 * RETURNS: 2028 * RETURNS:
1882 * Zero on success, negative on error. 2029 * Zero on success, negative on error.
@@ -1909,7 +2056,11 @@ static int ata_choose_xfer_mode(struct ata_port *ap,
1909 * @ap: Port associated with device @dev 2056 * @ap: Port associated with device @dev
1910 * @dev: Device to which command will be sent 2057 * @dev: Device to which command will be sent
1911 * 2058 *
2059 * Issue SET FEATURES - XFER MODE command to device @dev
2060 * on port @ap.
2061 *
1912 * LOCKING: 2062 * LOCKING:
2063 * PCI/etc. bus probe sem.
1913 */ 2064 */
1914 2065
1915static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev) 2066static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
@@ -1947,10 +2098,13 @@ static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
1947} 2098}
1948 2099
1949/** 2100/**
1950 * ata_sg_clean - 2101 * ata_sg_clean - Unmap DMA memory associated with command
1951 * @qc: 2102 * @qc: Command containing DMA memory to be released
2103 *
2104 * Unmap all mapped DMA memory associated with this command.
1952 * 2105 *
1953 * LOCKING: 2106 * LOCKING:
2107 * spin_lock_irqsave(host_set lock)
1954 */ 2108 */
1955 2109
1956static void ata_sg_clean(struct ata_queued_cmd *qc) 2110static void ata_sg_clean(struct ata_queued_cmd *qc)
@@ -1981,7 +2135,11 @@ static void ata_sg_clean(struct ata_queued_cmd *qc)
1981 * ata_fill_sg - Fill PCI IDE PRD table 2135 * ata_fill_sg - Fill PCI IDE PRD table
1982 * @qc: Metadata associated with taskfile to be transferred 2136 * @qc: Metadata associated with taskfile to be transferred
1983 * 2137 *
2138 * Fill PCI IDE PRD (scatter-gather) table with segments
2139 * associated with the current disk command.
2140 *
1984 * LOCKING: 2141 * LOCKING:
2142 * spin_lock_irqsave(host_set lock)
1985 * 2143 *
1986 */ 2144 */
1987static void ata_fill_sg(struct ata_queued_cmd *qc) 2145static void ata_fill_sg(struct ata_queued_cmd *qc)
@@ -2028,7 +2186,13 @@ static void ata_fill_sg(struct ata_queued_cmd *qc)
2028 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported 2186 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2029 * @qc: Metadata associated with taskfile to check 2187 * @qc: Metadata associated with taskfile to check
2030 * 2188 *
2189 * Allow low-level driver to filter ATA PACKET commands, returning
2190 * a status indicating whether or not it is OK to use DMA for the
2191 * supplied PACKET command.
2192 *
2031 * LOCKING: 2193 * LOCKING:
2194 * spin_lock_irqsave(host_set lock)
2195 *
2032 * RETURNS: 0 when ATAPI DMA can be used 2196 * RETURNS: 0 when ATAPI DMA can be used
2033 * nonzero otherwise 2197 * nonzero otherwise
2034 */ 2198 */
@@ -2046,6 +2210,8 @@ int ata_check_atapi_dma(struct ata_queued_cmd *qc)
2046 * ata_qc_prep - Prepare taskfile for submission 2210 * ata_qc_prep - Prepare taskfile for submission
2047 * @qc: Metadata associated with taskfile to be prepared 2211 * @qc: Metadata associated with taskfile to be prepared
2048 * 2212 *
2213 * Prepare ATA taskfile for submission.
2214 *
2049 * LOCKING: 2215 * LOCKING:
2050 * spin_lock_irqsave(host_set lock) 2216 * spin_lock_irqsave(host_set lock)
2051 */ 2217 */
@@ -2057,6 +2223,32 @@ void ata_qc_prep(struct ata_queued_cmd *qc)
2057 ata_fill_sg(qc); 2223 ata_fill_sg(qc);
2058} 2224}
2059 2225
2226/**
2227 * ata_sg_init_one - Associate command with memory buffer
2228 * @qc: Command to be associated
2229 * @buf: Memory buffer
2230 * @buflen: Length of memory buffer, in bytes.
2231 *
2232 * Initialize the data-related elements of queued_cmd @qc
2233 * to point to a single memory buffer, @buf of byte length @buflen.
2234 *
2235 * LOCKING:
2236 * spin_lock_irqsave(host_set lock)
2237 */
2238
2239
2240
2241/**
2242 * ata_sg_init_one - Prepare a one-entry scatter-gather list.
2243 * @qc: Queued command
2244 * @buf: transfer buffer
2245 * @buflen: length of buf
2246 *
2247 * Builds a single-entry scatter-gather list to initiate a
2248 * transfer utilizing the specified buffer.
2249 *
2250 * LOCKING:
2251 */
2060void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen) 2252void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2061{ 2253{
2062 struct scatterlist *sg; 2254 struct scatterlist *sg;
@@ -2074,6 +2266,32 @@ void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2074 sg->length = buflen; 2266 sg->length = buflen;
2075} 2267}
2076 2268
2269/**
2270 * ata_sg_init - Associate command with scatter-gather table.
2271 * @qc: Command to be associated
2272 * @sg: Scatter-gather table.
2273 * @n_elem: Number of elements in s/g table.
2274 *
2275 * Initialize the data-related elements of queued_cmd @qc
2276 * to point to a scatter-gather table @sg, containing @n_elem
2277 * elements.
2278 *
2279 * LOCKING:
2280 * spin_lock_irqsave(host_set lock)
2281 */
2282
2283
2284/**
2285 * ata_sg_init - Assign a scatter gather list to a queued command
2286 * @qc: Queued command
2287 * @sg: Scatter-gather list
2288 * @n_elem: length of sg list
2289 *
2290 * Attaches a scatter-gather list to a queued command.
2291 *
2292 * LOCKING:
2293 */
2294
2077void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg, 2295void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2078 unsigned int n_elem) 2296 unsigned int n_elem)
2079{ 2297{
@@ -2083,14 +2301,16 @@ void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2083} 2301}
2084 2302
2085/** 2303/**
2086 * ata_sg_setup_one - 2304 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
2087 * @qc: 2305 * @qc: Command with memory buffer to be mapped.
2306 *
2307 * DMA-map the memory buffer associated with queued_cmd @qc.
2088 * 2308 *
2089 * LOCKING: 2309 * LOCKING:
2090 * spin_lock_irqsave(host_set lock) 2310 * spin_lock_irqsave(host_set lock)
2091 * 2311 *
2092 * RETURNS: 2312 * RETURNS:
2093 * 2313 * Zero on success, negative on error.
2094 */ 2314 */
2095 2315
2096static int ata_sg_setup_one(struct ata_queued_cmd *qc) 2316static int ata_sg_setup_one(struct ata_queued_cmd *qc)
@@ -2115,13 +2335,16 @@ static int ata_sg_setup_one(struct ata_queued_cmd *qc)
2115} 2335}
2116 2336
2117/** 2337/**
2118 * ata_sg_setup - 2338 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
2119 * @qc: 2339 * @qc: Command with scatter-gather table to be mapped.
2340 *
2341 * DMA-map the scatter-gather table associated with queued_cmd @qc.
2120 * 2342 *
2121 * LOCKING: 2343 * LOCKING:
2122 * spin_lock_irqsave(host_set lock) 2344 * spin_lock_irqsave(host_set lock)
2123 * 2345 *
2124 * RETURNS: 2346 * RETURNS:
2347 * Zero on success, negative on error.
2125 * 2348 *
2126 */ 2349 */
2127 2350
@@ -2151,6 +2374,7 @@ static int ata_sg_setup(struct ata_queued_cmd *qc)
2151 * @ap: 2374 * @ap:
2152 * 2375 *
2153 * LOCKING: 2376 * LOCKING:
2377 * None. (executing in kernel thread context)
2154 * 2378 *
2155 * RETURNS: 2379 * RETURNS:
2156 * 2380 *
@@ -2198,6 +2422,7 @@ static unsigned long ata_pio_poll(struct ata_port *ap)
2198 * @ap: 2422 * @ap:
2199 * 2423 *
2200 * LOCKING: 2424 * LOCKING:
2425 * None. (executing in kernel thread context)
2201 */ 2426 */
2202 2427
2203static void ata_pio_complete (struct ata_port *ap) 2428static void ata_pio_complete (struct ata_port *ap)
@@ -2240,6 +2465,18 @@ static void ata_pio_complete (struct ata_port *ap)
2240 ata_qc_complete(qc, drv_stat); 2465 ata_qc_complete(qc, drv_stat);
2241} 2466}
2242 2467
2468
2469/**
2470 * swap_buf_le16 -
2471 * @buf: Buffer to swap
2472 * @buf_words: Number of 16-bit words in buffer.
2473 *
2474 * Swap halves of 16-bit words if needed to convert from
2475 * little-endian byte order to native cpu byte order, or
2476 * vice-versa.
2477 *
2478 * LOCKING:
2479 */
2243void swap_buf_le16(u16 *buf, unsigned int buf_words) 2480void swap_buf_le16(u16 *buf, unsigned int buf_words)
2244{ 2481{
2245#ifdef __BIG_ENDIAN 2482#ifdef __BIG_ENDIAN
@@ -2415,6 +2652,7 @@ err_out:
2415 * @ap: 2652 * @ap:
2416 * 2653 *
2417 * LOCKING: 2654 * LOCKING:
2655 * None. (executing in kernel thread context)
2418 */ 2656 */
2419 2657
2420static void ata_pio_block(struct ata_port *ap) 2658static void ata_pio_block(struct ata_port *ap)
@@ -2583,6 +2821,7 @@ static void atapi_request_sense(struct ata_port *ap, struct ata_device *dev,
2583 * transaction completed successfully. 2821 * transaction completed successfully.
2584 * 2822 *
2585 * LOCKING: 2823 * LOCKING:
2824 * Inherited from SCSI layer (none, can sleep)
2586 */ 2825 */
2587 2826
2588static void ata_qc_timeout(struct ata_queued_cmd *qc) 2827static void ata_qc_timeout(struct ata_queued_cmd *qc)
@@ -2692,6 +2931,7 @@ out:
2692 * @dev: Device from whom we request an available command structure 2931 * @dev: Device from whom we request an available command structure
2693 * 2932 *
2694 * LOCKING: 2933 * LOCKING:
2934 * None.
2695 */ 2935 */
2696 2936
2697static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap) 2937static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
@@ -2717,6 +2957,7 @@ static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
2717 * @dev: Device from whom we request an available command structure 2957 * @dev: Device from whom we request an available command structure
2718 * 2958 *
2719 * LOCKING: 2959 * LOCKING:
2960 * None.
2720 */ 2961 */
2721 2962
2722struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap, 2963struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
@@ -2781,6 +3022,7 @@ static void __ata_qc_complete(struct ata_queued_cmd *qc)
2781 * in case something prevents using it. 3022 * in case something prevents using it.
2782 * 3023 *
2783 * LOCKING: 3024 * LOCKING:
3025 * spin_lock_irqsave(host_set lock)
2784 * 3026 *
2785 */ 3027 */
2786void ata_qc_free(struct ata_queued_cmd *qc) 3028void ata_qc_free(struct ata_queued_cmd *qc)
@@ -2794,9 +3036,13 @@ void ata_qc_free(struct ata_queued_cmd *qc)
2794/** 3036/**
2795 * ata_qc_complete - Complete an active ATA command 3037 * ata_qc_complete - Complete an active ATA command
2796 * @qc: Command to complete 3038 * @qc: Command to complete
2797 * @drv_stat: ATA status register contents 3039 * @drv_stat: ATA Status register contents
3040 *
3041 * Indicate to the mid and upper layers that an ATA
3042 * command has completed, with either an ok or not-ok status.
2798 * 3043 *
2799 * LOCKING: 3044 * LOCKING:
3045 * spin_lock_irqsave(host_set lock)
2800 * 3046 *
2801 */ 3047 */
2802 3048
@@ -2892,6 +3138,7 @@ err_out:
2892 return -1; 3138 return -1;
2893} 3139}
2894 3140
3141
2895/** 3142/**
2896 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner 3143 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
2897 * @qc: command to issue to device 3144 * @qc: command to issue to device
@@ -2901,6 +3148,8 @@ err_out:
2901 * classes called "protocols", and issuing each type of protocol 3148 * classes called "protocols", and issuing each type of protocol
2902 * is slightly different. 3149 * is slightly different.
2903 * 3150 *
3151 * May be used as the qc_issue() entry in ata_port_operations.
3152 *
2904 * LOCKING: 3153 * LOCKING:
2905 * spin_lock_irqsave(host_set lock) 3154 * spin_lock_irqsave(host_set lock)
2906 * 3155 *
@@ -2958,7 +3207,7 @@ int ata_qc_issue_prot(struct ata_queued_cmd *qc)
2958} 3207}
2959 3208
2960/** 3209/**
2961 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction 3210 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
2962 * @qc: Info associated with this ATA transaction. 3211 * @qc: Info associated with this ATA transaction.
2963 * 3212 *
2964 * LOCKING: 3213 * LOCKING:
@@ -3065,6 +3314,18 @@ static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
3065 ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 3314 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3066} 3315}
3067 3316
3317
3318/**
3319 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3320 * @qc: Info associated with this ATA transaction.
3321 *
3322 * Writes the ATA_DMA_START flag to the DMA command register.
3323 *
3324 * May be used as the bmdma_start() entry in ata_port_operations.
3325 *
3326 * LOCKING:
3327 * spin_lock_irqsave(host_set lock)
3328 */
3068void ata_bmdma_start(struct ata_queued_cmd *qc) 3329void ata_bmdma_start(struct ata_queued_cmd *qc)
3069{ 3330{
3070 if (qc->ap->flags & ATA_FLAG_MMIO) 3331 if (qc->ap->flags & ATA_FLAG_MMIO)
@@ -3073,6 +3334,20 @@ void ata_bmdma_start(struct ata_queued_cmd *qc)
3073 ata_bmdma_start_pio(qc); 3334 ata_bmdma_start_pio(qc);
3074} 3335}
3075 3336
3337
3338/**
3339 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3340 * @qc: Info associated with this ATA transaction.
3341 *
3342 * Writes address of PRD table to device's PRD Table Address
3343 * register, sets the DMA control register, and calls
3344 * ops->exec_command() to start the transfer.
3345 *
3346 * May be used as the bmdma_setup() entry in ata_port_operations.
3347 *
3348 * LOCKING:
3349 * spin_lock_irqsave(host_set lock)
3350 */
3076void ata_bmdma_setup(struct ata_queued_cmd *qc) 3351void ata_bmdma_setup(struct ata_queued_cmd *qc)
3077{ 3352{
3078 if (qc->ap->flags & ATA_FLAG_MMIO) 3353 if (qc->ap->flags & ATA_FLAG_MMIO)
@@ -3081,6 +3356,19 @@ void ata_bmdma_setup(struct ata_queued_cmd *qc)
3081 ata_bmdma_setup_pio(qc); 3356 ata_bmdma_setup_pio(qc);
3082} 3357}
3083 3358
3359
3360/**
3361 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
3362 * @ap: Port associated with this ATA transaction.
3363 *
3364 * Clear interrupt and error flags in DMA status register.
3365 *
3366 * May be used as the irq_clear() entry in ata_port_operations.
3367 *
3368 * LOCKING:
3369 * spin_lock_irqsave(host_set lock)
3370 */
3371
3084void ata_bmdma_irq_clear(struct ata_port *ap) 3372void ata_bmdma_irq_clear(struct ata_port *ap)
3085{ 3373{
3086 if (ap->flags & ATA_FLAG_MMIO) { 3374 if (ap->flags & ATA_FLAG_MMIO) {
@@ -3093,6 +3381,19 @@ void ata_bmdma_irq_clear(struct ata_port *ap)
3093 3381
3094} 3382}
3095 3383
3384
3385/**
3386 * ata_bmdma_status - Read PCI IDE BMDMA status
3387 * @ap: Port associated with this ATA transaction.
3388 *
3389 * Read and return BMDMA status register.
3390 *
3391 * May be used as the bmdma_status() entry in ata_port_operations.
3392 *
3393 * LOCKING:
3394 * spin_lock_irqsave(host_set lock)
3395 */
3396
3096u8 ata_bmdma_status(struct ata_port *ap) 3397u8 ata_bmdma_status(struct ata_port *ap)
3097{ 3398{
3098 u8 host_stat; 3399 u8 host_stat;
@@ -3104,6 +3405,19 @@ u8 ata_bmdma_status(struct ata_port *ap)
3104 return host_stat; 3405 return host_stat;
3105} 3406}
3106 3407
3408
3409/**
3410 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
3411 * @ap: Port associated with this ATA transaction.
3412 *
3413 * Clears the ATA_DMA_START flag in the dma control register
3414 *
3415 * May be used as the bmdma_stop() entry in ata_port_operations.
3416 *
3417 * LOCKING:
3418 * spin_lock_irqsave(host_set lock)
3419 */
3420
3107void ata_bmdma_stop(struct ata_port *ap) 3421void ata_bmdma_stop(struct ata_port *ap)
3108{ 3422{
3109 if (ap->flags & ATA_FLAG_MMIO) { 3423 if (ap->flags & ATA_FLAG_MMIO) {
@@ -3203,13 +3517,18 @@ idle_irq:
3203 3517
3204/** 3518/**
3205 * ata_interrupt - Default ATA host interrupt handler 3519 * ata_interrupt - Default ATA host interrupt handler
3206 * @irq: irq line 3520 * @irq: irq line (unused)
3207 * @dev_instance: pointer to our host information structure 3521 * @dev_instance: pointer to our ata_host_set information structure
3208 * @regs: unused 3522 * @regs: unused
3209 * 3523 *
3524 * Default interrupt handler for PCI IDE devices. Calls
3525 * ata_host_intr() for each port that is not disabled.
3526 *
3210 * LOCKING: 3527 * LOCKING:
3528 * Obtains host_set lock during operation.
3211 * 3529 *
3212 * RETURNS: 3530 * RETURNS:
3531 * IRQ_NONE or IRQ_HANDLED.
3213 * 3532 *
3214 */ 3533 */
3215 3534
@@ -3302,6 +3621,19 @@ err_out:
3302 ata_qc_complete(qc, ATA_ERR); 3621 ata_qc_complete(qc, ATA_ERR);
3303} 3622}
3304 3623
3624
3625/**
3626 * ata_port_start - Set port up for dma.
3627 * @ap: Port to initialize
3628 *
3629 * Called just after data structures for each port are
3630 * initialized. Allocates space for PRD table.
3631 *
3632 * May be used as the port_start() entry in ata_port_operations.
3633 *
3634 * LOCKING:
3635 */
3636
3305int ata_port_start (struct ata_port *ap) 3637int ata_port_start (struct ata_port *ap)
3306{ 3638{
3307 struct device *dev = ap->host_set->dev; 3639 struct device *dev = ap->host_set->dev;
@@ -3315,6 +3647,18 @@ int ata_port_start (struct ata_port *ap)
3315 return 0; 3647 return 0;
3316} 3648}
3317 3649
3650
3651/**
3652 * ata_port_stop - Undo ata_port_start()
3653 * @ap: Port to shut down
3654 *
3655 * Frees the PRD table.
3656 *
3657 * May be used as the port_stop() entry in ata_port_operations.
3658 *
3659 * LOCKING:
3660 */
3661
3318void ata_port_stop (struct ata_port *ap) 3662void ata_port_stop (struct ata_port *ap)
3319{ 3663{
3320 struct device *dev = ap->host_set->dev; 3664 struct device *dev = ap->host_set->dev;
@@ -3357,7 +3701,11 @@ static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
3357 * @ent: Probe information provided by low-level driver 3701 * @ent: Probe information provided by low-level driver
3358 * @port_no: Port number associated with this ata_port 3702 * @port_no: Port number associated with this ata_port
3359 * 3703 *
3704 * Initialize a new ata_port structure, and its associated
3705 * scsi_host.
3706 *
3360 * LOCKING: 3707 * LOCKING:
3708 * Inherited from caller.
3361 * 3709 *
3362 */ 3710 */
3363 3711
@@ -3412,9 +3760,13 @@ static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
3412 * @host_set: Collections of ports to which we add 3760 * @host_set: Collections of ports to which we add
3413 * @port_no: Port number associated with this host 3761 * @port_no: Port number associated with this host
3414 * 3762 *
3763 * Attach low-level ATA driver to system.
3764 *
3415 * LOCKING: 3765 * LOCKING:
3766 * PCI/etc. bus probe sem.
3416 * 3767 *
3417 * RETURNS: 3768 * RETURNS:
3769 * New ata_port on success, for NULL on error.
3418 * 3770 *
3419 */ 3771 */
3420 3772
@@ -3447,12 +3799,22 @@ err_out:
3447} 3799}
3448 3800
3449/** 3801/**
3450 * ata_device_add - 3802 * ata_device_add - Register hardware device with ATA and SCSI layers
3451 * @ent: 3803 * @ent: Probe information describing hardware device to be registered
3804 *
3805 * This function processes the information provided in the probe
3806 * information struct @ent, allocates the necessary ATA and SCSI
3807 * host information structures, initializes them, and registers
3808 * everything with requisite kernel subsystems.
3809 *
3810 * This function requests irqs, probes the ATA bus, and probes
3811 * the SCSI bus.
3452 * 3812 *
3453 * LOCKING: 3813 * LOCKING:
3814 * PCI/etc. bus probe sem.
3454 * 3815 *
3455 * RETURNS: 3816 * RETURNS:
3817 * Number of ports registered. Zero on error (no ports registered).
3456 * 3818 *
3457 */ 3819 */
3458 3820
@@ -3604,7 +3966,15 @@ int ata_scsi_release(struct Scsi_Host *host)
3604/** 3966/**
3605 * ata_std_ports - initialize ioaddr with standard port offsets. 3967 * ata_std_ports - initialize ioaddr with standard port offsets.
3606 * @ioaddr: IO address structure to be initialized 3968 * @ioaddr: IO address structure to be initialized
3969 *
3970 * Utility function which initializes data_addr, error_addr,
3971 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
3972 * device_addr, status_addr, and command_addr to standard offsets
3973 * relative to cmd_addr.
3974 *
3975 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
3607 */ 3976 */
3977
3608void ata_std_ports(struct ata_ioports *ioaddr) 3978void ata_std_ports(struct ata_ioports *ioaddr)
3609{ 3979{
3610 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; 3980 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
@@ -3646,6 +4016,20 @@ ata_probe_ent_alloc(struct device *dev, struct ata_port_info *port)
3646 return probe_ent; 4016 return probe_ent;
3647} 4017}
3648 4018
4019
4020
4021/**
4022 * ata_pci_init_native_mode - Initialize native-mode driver
4023 * @pdev: pci device to be initialized
4024 * @port: array[2] of pointers to port info structures.
4025 *
4026 * Utility function which allocates and initializes an
4027 * ata_probe_ent structure for a standard dual-port
4028 * PIO-based IDE controller. The returned ata_probe_ent
4029 * structure can be passed to ata_device_add(). The returned
4030 * ata_probe_ent structure should then be freed with kfree().
4031 */
4032
3649#ifdef CONFIG_PCI 4033#ifdef CONFIG_PCI
3650struct ata_probe_ent * 4034struct ata_probe_ent *
3651ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port) 4035ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port)
@@ -3727,10 +4111,19 @@ ata_pci_init_legacy_mode(struct pci_dev *pdev, struct ata_port_info **port,
3727 * @port_info: Information from low-level host driver 4111 * @port_info: Information from low-level host driver
3728 * @n_ports: Number of ports attached to host controller 4112 * @n_ports: Number of ports attached to host controller
3729 * 4113 *
4114 * This is a helper function which can be called from a driver's
4115 * xxx_init_one() probe function if the hardware uses traditional
4116 * IDE taskfile registers.
4117 *
4118 * This function calls pci_enable_device(), reserves its register
4119 * regions, sets the dma mask, enables bus master mode, and calls
4120 * ata_device_add()
4121 *
3730 * LOCKING: 4122 * LOCKING:
3731 * Inherited from PCI layer (may sleep). 4123 * Inherited from PCI layer (may sleep).
3732 * 4124 *
3733 * RETURNS: 4125 * RETURNS:
4126 * Zero on success, negative on errno-based value on error.
3734 * 4127 *
3735 */ 4128 */
3736 4129
@@ -3949,15 +4342,6 @@ int pci_test_config_bits(struct pci_dev *pdev, struct pci_bits *bits)
3949#endif /* CONFIG_PCI */ 4342#endif /* CONFIG_PCI */
3950 4343
3951 4344
3952/**
3953 * ata_init -
3954 *
3955 * LOCKING:
3956 *
3957 * RETURNS:
3958 *
3959 */
3960
3961static int __init ata_init(void) 4345static int __init ata_init(void)
3962{ 4346{
3963 ata_wq = create_workqueue("ata"); 4347 ata_wq = create_workqueue("ata");
diff --git a/drivers/scsi/libata-scsi.c b/drivers/scsi/libata-scsi.c
index 416ba67ba9ee..7a4adc4c8f09 100644
--- a/drivers/scsi/libata-scsi.c
+++ b/drivers/scsi/libata-scsi.c
@@ -947,7 +947,7 @@ unsigned int ata_scsiop_inq_83(struct ata_scsi_args *args, u8 *rbuf,
947} 947}
948 948
949/** 949/**
950 * ata_scsiop_noop - 950 * ata_scsiop_noop - Command handler that simply returns success.
951 * @args: device IDENTIFY data / SCSI command of interest. 951 * @args: device IDENTIFY data / SCSI command of interest.
952 * @rbuf: Response buffer, to which simulated SCSI cmd output is sent. 952 * @rbuf: Response buffer, to which simulated SCSI cmd output is sent.
953 * @buflen: Response buffer length. 953 * @buflen: Response buffer length.
diff --git a/fs/jbd/checkpoint.c b/fs/jbd/checkpoint.c
index 98d830401c56..5a97e346bd95 100644
--- a/fs/jbd/checkpoint.c
+++ b/fs/jbd/checkpoint.c
@@ -188,7 +188,6 @@ static int __cleanup_transaction(journal_t *journal, transaction_t *transaction)
188 } else { 188 } else {
189 jbd_unlock_bh_state(bh); 189 jbd_unlock_bh_state(bh);
190 } 190 }
191 jh = next_jh;
192 } while (jh != last_jh); 191 } while (jh != last_jh);
193 192
194 return ret; 193 return ret;
@@ -339,8 +338,10 @@ int log_do_checkpoint(journal_t *journal)
339 } 338 }
340 } while (jh != last_jh && !retry); 339 } while (jh != last_jh && !retry);
341 340
342 if (batch_count) 341 if (batch_count) {
343 __flush_batch(journal, bhs, &batch_count); 342 __flush_batch(journal, bhs, &batch_count);
343 retry = 1;
344 }
344 345
345 /* 346 /*
346 * If someone cleaned up this transaction while we slept, we're 347 * If someone cleaned up this transaction while we slept, we're
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
index 0035efe2db2b..809c634ba1df 100644
--- a/include/asm-ppc64/processor.h
+++ b/include/asm-ppc64/processor.h
@@ -120,103 +120,18 @@
120 120
121/* Special Purpose Registers (SPRNs)*/ 121/* Special Purpose Registers (SPRNs)*/
122 122
123#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
124#define SPRN_CTR 0x009 /* Count Register */ 123#define SPRN_CTR 0x009 /* Count Register */
125#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 124#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
126#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ 125#define DABR_TRANSLATION (1UL << 2)
127#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
128#define SPRN_DAR 0x013 /* Data Address Register */ 126#define SPRN_DAR 0x013 /* Data Address Register */
129#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
130#define DBCR_EDM 0x80000000
131#define DBCR_IDM 0x40000000
132#define DBCR_RST(x) (((x) & 0x3) << 28)
133#define DBCR_RST_NONE 0
134#define DBCR_RST_CORE 1
135#define DBCR_RST_CHIP 2
136#define DBCR_RST_SYSTEM 3
137#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
138#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
139#define DBCR_EDE 0x02000000 /* Exception Debug Event */
140#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
141#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
142#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
143#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
144#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
145#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
146#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
147#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
148#define DAC_BYTE 0
149#define DAC_HALF 1
150#define DAC_WORD 2
151#define DAC_QUAD 3
152#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
153#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
154#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
155#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
156#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
157#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
158#define DBCR_SIA 0x00000008 /* Second IAC Enable */
159#define DBCR_SDA 0x00000004 /* Second DAC Enable */
160#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
161#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
162#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
163#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
164#define SPRN_DBSR 0x3F0 /* Debug Status Register */
165#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
166#define DCCR_NOCACHE 0 /* Noncacheable */
167#define DCCR_CACHE 1 /* Cacheable */
168#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
169#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
170#define DCWR_COPY 0 /* Copy-back */
171#define DCWR_WRITE 1 /* Write-through */
172#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
173#define SPRN_DEC 0x016 /* Decrement Register */ 127#define SPRN_DEC 0x016 /* Decrement Register */
174#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
175#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 128#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
176#define DSISR_NOHPTE 0x40000000 /* no translation found */ 129#define DSISR_NOHPTE 0x40000000 /* no translation found */
177#define DSISR_PROTFAULT 0x08000000 /* protection fault */ 130#define DSISR_PROTFAULT 0x08000000 /* protection fault */
178#define DSISR_ISSTORE 0x02000000 /* access was a store */ 131#define DSISR_ISSTORE 0x02000000 /* access was a store */
179#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ 132#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
180#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */ 133#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
181#define SPRN_EAR 0x11A /* External Address Register */
182#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
183#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
184#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
185#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
186#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
187#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
188#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
189#define ESR_PTR 0x02000000 /* Program Exception - Trap */
190#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
191#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
192#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
193#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
194#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
195#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ 134#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
196#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
197#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
198#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
199#define HID0_SBCLK (1<<27)
200#define HID0_EICE (1<<26)
201#define HID0_ECLK (1<<25)
202#define HID0_PAR (1<<24)
203#define HID0_DOZE (1<<23)
204#define HID0_NAP (1<<22)
205#define HID0_SLEEP (1<<21)
206#define HID0_DPM (1<<20)
207#define HID0_ICE (1<<15) /* Instruction Cache Enable */
208#define HID0_DCE (1<<14) /* Data Cache Enable */
209#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
210#define HID0_DLOCK (1<<12) /* Data Cache Lock */
211#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
212#define HID0_DCI (1<<10) /* Data Cache Invalidate */
213#define HID0_SPD (1<<9) /* Speculative disable */
214#define HID0_SGE (1<<7) /* Store Gathering Enable */
215#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
216#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
217#define HID0_ABE (1<<3) /* Address Broadcast Enable */
218#define HID0_BHTE (1<<2) /* Branch History Table Enable */
219#define HID0_BTCD (1<<1) /* Branch target cache disable */
220#define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */ 135#define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */
221#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ 136#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
222#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 137#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
@@ -225,23 +140,8 @@
225#define SPRN_HID5 0x3F6 /* 970 HID5 */ 140#define SPRN_HID5 0x3F6 /* 970 HID5 */
226#define SPRN_TSC 0x3FD /* Thread switch control */ 141#define SPRN_TSC 0x3FD /* Thread switch control */
227#define SPRN_TST 0x3FC /* Thread switch timeout */ 142#define SPRN_TST 0x3FC /* Thread switch timeout */
228#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
229#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
230#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
231#define ICCR_NOCACHE 0 /* Noncacheable */
232#define ICCR_CACHE 1 /* Cacheable */
233#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
234#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
235#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
236#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
237#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
238#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ 143#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
239#define SPRN_LR 0x008 /* Link Register */ 144#define SPRN_LR 0x008 /* Link Register */
240#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
241#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
242#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
243#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
244#define SPRN_PID 0x3B1 /* Process ID */
245#define SPRN_PIR 0x3FF /* Processor Identification Register */ 145#define SPRN_PIR 0x3FF /* Processor Identification Register */
246#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 146#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
247#define SPRN_PURR 0x135 /* Processor Utilization of Resources Register */ 147#define SPRN_PURR 0x135 /* Processor Utilization of Resources Register */
@@ -249,9 +149,6 @@
249#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 149#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
250#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ 150#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
251#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 151#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
252#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
253#define SGR_NORMAL 0
254#define SGR_GUARDED 1
255#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 152#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
256#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 153#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
257#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 154#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
@@ -264,50 +161,12 @@
264#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, W/O) */ 161#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, W/O) */
265#define SPRN_TBWU 0x11D /* Time Base Write Upper Register (super, W/O) */ 162#define SPRN_TBWU 0x11D /* Time Base Write Upper Register (super, W/O) */
266#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 163#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
267#define SPRN_TCR 0x3DA /* Timer Control Register */
268#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
269#define WP_2_17 0 /* 2^17 clocks */
270#define WP_2_21 1 /* 2^21 clocks */
271#define WP_2_25 2 /* 2^25 clocks */
272#define WP_2_29 3 /* 2^29 clocks */
273#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
274#define WRC_NONE 0 /* No reset will occur */
275#define WRC_CORE 1 /* Core reset will occur */
276#define WRC_CHIP 2 /* Chip reset will occur */
277#define WRC_SYSTEM 3 /* System reset will occur */
278#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
279#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
280#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
281#define FP_2_9 0 /* 2^9 clocks */
282#define FP_2_13 1 /* 2^13 clocks */
283#define FP_2_17 2 /* 2^17 clocks */
284#define FP_2_21 3 /* 2^21 clocks */
285#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
286#define TCR_ARE 0x00400000 /* Auto Reload Enable */
287#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
288#define THRM1_TIN (1<<0)
289#define THRM1_TIV (1<<1)
290#define THRM1_THRES (0x7f<<2)
291#define THRM1_TID (1<<29)
292#define THRM1_TIE (1<<30)
293#define THRM1_V (1<<31)
294#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
295#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
296#define THRM3_E (1<<31)
297#define SPRN_TSR 0x3D8 /* Timer Status Register */
298#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
299#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
300#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
301#define WRS_NONE 0 /* No WDT reset occurred */
302#define WRS_CORE 1 /* WDT forced core reset */
303#define WRS_CHIP 2 /* WDT forced chip reset */
304#define WRS_SYSTEM 3 /* WDT forced system reset */
305#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
306#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
307#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ 164#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
308#define SPRN_XER 0x001 /* Fixed Point Exception Register */ 165#define SPRN_XER 0x001 /* Fixed Point Exception Register */
309#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
310#define SPRN_VRSAVE 0x100 /* Vector save */ 166#define SPRN_VRSAVE 0x100 /* Vector save */
167#define SPRN_CTRLF 0x088
168#define SPRN_CTRLT 0x098
169#define CTRL_RUNLATCH 0x1
311 170
312/* Performance monitor SPRs */ 171/* Performance monitor SPRs */
313#define SPRN_SIAR 780 172#define SPRN_SIAR 780
@@ -352,28 +211,19 @@
352#define CTR SPRN_CTR /* Counter Register */ 211#define CTR SPRN_CTR /* Counter Register */
353#define DAR SPRN_DAR /* Data Address Register */ 212#define DAR SPRN_DAR /* Data Address Register */
354#define DABR SPRN_DABR /* Data Address Breakpoint Register */ 213#define DABR SPRN_DABR /* Data Address Breakpoint Register */
355#define DCMP SPRN_DCMP /* Data TLB Compare Register */
356#define DEC SPRN_DEC /* Decrement Register */ 214#define DEC SPRN_DEC /* Decrement Register */
357#define DMISS SPRN_DMISS /* Data TLB Miss Register */
358#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ 215#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
359#define EAR SPRN_EAR /* External Address Register */
360#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
361#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
362#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ 216#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
363#define MSRDORM SPRN_MSRDORM /* MSR Dormant Register */ 217#define MSRDORM SPRN_MSRDORM /* MSR Dormant Register */
364#define NIADORM SPRN_NIADORM /* NIA Dormant Register */ 218#define NIADORM SPRN_NIADORM /* NIA Dormant Register */
365#define TSC SPRN_TSC /* Thread switch control */ 219#define TSC SPRN_TSC /* Thread switch control */
366#define TST SPRN_TST /* Thread switch timeout */ 220#define TST SPRN_TST /* Thread switch timeout */
367#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ 221#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
368#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
369#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
370#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
371#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ 222#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
372#define __LR SPRN_LR 223#define __LR SPRN_LR
373#define PVR SPRN_PVR /* Processor Version */ 224#define PVR SPRN_PVR /* Processor Version */
374#define PIR SPRN_PIR /* Processor ID */ 225#define PIR SPRN_PIR /* Processor ID */
375#define PURR SPRN_PURR /* Processor Utilization of Resource Register */ 226#define PURR SPRN_PURR /* Processor Utilization of Resource Register */
376//#define RPA SPRN_RPA /* Required Physical Address Register */
377#define SDR1 SPRN_SDR1 /* MMU hash base register */ 227#define SDR1 SPRN_SDR1 /* MMU hash base register */
378#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ 228#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
379#define SPR1 SPRN_SPRG1 229#define SPR1 SPRN_SPRG1
@@ -389,10 +239,6 @@
389#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ 239#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
390#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ 240#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
391#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ 241#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
392#define ICTC 1019
393#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
394#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
395#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
396#define XER SPRN_XER 242#define XER SPRN_XER
397 243
398/* Processor Version Register (PVR) field extraction */ 244/* Processor Version Register (PVR) field extraction */
@@ -436,12 +282,6 @@
436#define XGLUE(a,b) a##b 282#define XGLUE(a,b) a##b
437#define GLUE(a,b) XGLUE(a,b) 283#define GLUE(a,b) XGLUE(a,b)
438 284
439/* iSeries CTRL register (for runlatch) */
440
441#define CTRLT 0x098
442#define CTRLF 0x088
443#define RUNLATCH 0x0001
444
445#ifdef __ASSEMBLY__ 285#ifdef __ASSEMBLY__
446 286
447#define _GLOBAL(name) \ 287#define _GLOBAL(name) \
@@ -656,6 +496,24 @@ static inline void prefetchw(const void *x)
656 496
657#define HAVE_ARCH_PICK_MMAP_LAYOUT 497#define HAVE_ARCH_PICK_MMAP_LAYOUT
658 498
499static inline void ppc64_runlatch_on(void)
500{
501 unsigned long ctrl;
502
503 ctrl = mfspr(SPRN_CTRLF);
504 ctrl |= CTRL_RUNLATCH;
505 mtspr(SPRN_CTRLT, ctrl);
506}
507
508static inline void ppc64_runlatch_off(void)
509{
510 unsigned long ctrl;
511
512 ctrl = mfspr(SPRN_CTRLF);
513 ctrl &= ~CTRL_RUNLATCH;
514 mtspr(SPRN_CTRLT, ctrl);
515}
516
659#endif /* __KERNEL__ */ 517#endif /* __KERNEL__ */
660 518
661#endif /* __ASSEMBLY__ */ 519#endif /* __ASSEMBLY__ */
diff --git a/include/asm-ppc64/thread_info.h b/include/asm-ppc64/thread_info.h
index 037b5e06083c..48b7900e90ec 100644
--- a/include/asm-ppc64/thread_info.h
+++ b/include/asm-ppc64/thread_info.h
@@ -96,7 +96,7 @@ static inline struct thread_info *current_thread_info(void)
96#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling 96#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling
97 TIF_NEED_RESCHED */ 97 TIF_NEED_RESCHED */
98#define TIF_32BIT 5 /* 32 bit binary */ 98#define TIF_32BIT 5 /* 32 bit binary */
99#define TIF_RUN_LIGHT 6 /* iSeries run light */ 99/* #define SPARE 6 */
100#define TIF_ABI_PENDING 7 /* 32/64 bit switch needed */ 100#define TIF_ABI_PENDING 7 /* 32/64 bit switch needed */
101#define TIF_SYSCALL_AUDIT 8 /* syscall auditing active */ 101#define TIF_SYSCALL_AUDIT 8 /* syscall auditing active */
102#define TIF_SINGLESTEP 9 /* singlestepping active */ 102#define TIF_SINGLESTEP 9 /* singlestepping active */
@@ -110,7 +110,7 @@ static inline struct thread_info *current_thread_info(void)
110#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 110#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
111#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 111#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
112#define _TIF_32BIT (1<<TIF_32BIT) 112#define _TIF_32BIT (1<<TIF_32BIT)
113#define _TIF_RUN_LIGHT (1<<TIF_RUN_LIGHT) 113/* #define _SPARE (1<<SPARE) */
114#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING) 114#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
115#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) 115#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
116#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) 116#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
diff --git a/include/linux/libata.h b/include/linux/libata.h
index e74f301e9bae..b009f801e7c5 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -467,12 +467,34 @@ static inline u8 ata_chk_status(struct ata_port *ap)
467 return ap->ops->check_status(ap); 467 return ap->ops->check_status(ap);
468} 468}
469 469
470
471/**
472 * ata_pause - Flush writes and pause 400 nanoseconds.
473 * @ap: Port to wait for.
474 *
475 * LOCKING:
476 * Inherited from caller.
477 */
478
470static inline void ata_pause(struct ata_port *ap) 479static inline void ata_pause(struct ata_port *ap)
471{ 480{
472 ata_altstatus(ap); 481 ata_altstatus(ap);
473 ndelay(400); 482 ndelay(400);
474} 483}
475 484
485
486/**
487 * ata_busy_wait - Wait for a port status register
488 * @ap: Port to wait for.
489 *
490 * Waits up to max*10 microseconds for the selected bits in the port's
491 * status register to be cleared.
492 * Returns final value of status register.
493 *
494 * LOCKING:
495 * Inherited from caller.
496 */
497
476static inline u8 ata_busy_wait(struct ata_port *ap, unsigned int bits, 498static inline u8 ata_busy_wait(struct ata_port *ap, unsigned int bits,
477 unsigned int max) 499 unsigned int max)
478{ 500{
@@ -487,6 +509,18 @@ static inline u8 ata_busy_wait(struct ata_port *ap, unsigned int bits,
487 return status; 509 return status;
488} 510}
489 511
512
513/**
514 * ata_wait_idle - Wait for a port to be idle.
515 * @ap: Port to wait for.
516 *
517 * Waits up to 10ms for port's BUSY and DRQ signals to clear.
518 * Returns final value of status register.
519 *
520 * LOCKING:
521 * Inherited from caller.
522 */
523
490static inline u8 ata_wait_idle(struct ata_port *ap) 524static inline u8 ata_wait_idle(struct ata_port *ap)
491{ 525{
492 u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); 526 u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
@@ -525,6 +559,18 @@ static inline void ata_tf_init(struct ata_port *ap, struct ata_taskfile *tf, uns
525 tf->device = ATA_DEVICE_OBS | ATA_DEV1; 559 tf->device = ATA_DEVICE_OBS | ATA_DEV1;
526} 560}
527 561
562
563/**
564 * ata_irq_on - Enable interrupts on a port.
565 * @ap: Port on which interrupts are enabled.
566 *
567 * Enable interrupts on a legacy IDE device using MMIO or PIO,
568 * wait for idle, clear any pending interrupts.
569 *
570 * LOCKING:
571 * Inherited from caller.
572 */
573
528static inline u8 ata_irq_on(struct ata_port *ap) 574static inline u8 ata_irq_on(struct ata_port *ap)
529{ 575{
530 struct ata_ioports *ioaddr = &ap->ioaddr; 576 struct ata_ioports *ioaddr = &ap->ioaddr;
@@ -544,6 +590,18 @@ static inline u8 ata_irq_on(struct ata_port *ap)
544 return tmp; 590 return tmp;
545} 591}
546 592
593
594/**
595 * ata_irq_ack - Acknowledge a device interrupt.
596 * @ap: Port on which interrupts are enabled.
597 *
598 * Wait up to 10 ms for legacy IDE device to become idle (BUSY
599 * or BUSY+DRQ clear). Obtain dma status and port status from
600 * device. Clear the interrupt. Return port status.
601 *
602 * LOCKING:
603 */
604
547static inline u8 ata_irq_ack(struct ata_port *ap, unsigned int chk_drq) 605static inline u8 ata_irq_ack(struct ata_port *ap, unsigned int chk_drq)
548{ 606{
549 unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY; 607 unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-10 11:14:28 -0400