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-rw-r--r--arch/arm/Kconfig11
-rw-r--r--arch/arm/common/time-acorn.c2
-rw-r--r--arch/arm/configs/ixp4xx_defconfig982
-rw-r--r--arch/arm/kernel/setup.c1
-rw-r--r--arch/arm/kernel/smp.c39
-rw-r--r--arch/arm/mach-at91/Kconfig30
-rw-r--r--arch/arm/mach-at91/at91sam926x_time.c3
-rw-r--r--arch/arm/mach-at91/generic.h3
-rw-r--r--arch/arm/mach-at91/gpio.c89
-rw-r--r--arch/arm/mach-ixp4xx/Kconfig14
-rw-r--r--arch/arm/mach-ixp4xx/Makefile8
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-power.c125
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-setup.c134
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-setup.c29
-rw-r--r--arch/arm/mach-ixp4xx/ixp4xx_npe.c741
-rw-r--r--arch/arm/mach-ixp4xx/ixp4xx_qmgr.c274
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-power.c69
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-setup.c174
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-power.c91
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-setup.c137
-rw-r--r--arch/arm/mach-pxa/Makefile2
-rw-r--r--arch/arm/mach-pxa/cm-x270.c1
-rw-r--r--arch/arm/mach-pxa/devices.c1
-rw-r--r--arch/arm/mach-pxa/generic.c57
-rw-r--r--arch/arm/mach-pxa/generic.h3
-rw-r--r--arch/arm/mach-pxa/irq.c62
-rw-r--r--arch/arm/mach-pxa/mfp.c11
-rw-r--r--arch/arm/mach-pxa/pcm027.c1
-rw-r--r--arch/arm/mach-pxa/poodle.c8
-rw-r--r--arch/arm/mach-pxa/pxa25x.c43
-rw-r--r--arch/arm/mach-pxa/pxa27x.c49
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c99
-rw-r--r--arch/arm/mach-pxa/sleep.S102
-rw-r--r--arch/arm/mach-pxa/smemc.c88
-rw-r--r--arch/arm/mach-pxa/spitz.c1
-rw-r--r--arch/arm/mach-pxa/tosa.c1
-rw-r--r--arch/arm/mach-realview/Kconfig21
-rw-r--r--arch/arm/mach-realview/Makefile3
-rw-r--r--arch/arm/mach-realview/core.c179
-rw-r--r--arch/arm/mach-realview/core.h71
-rw-r--r--arch/arm/mach-realview/localtimer.c144
-rw-r--r--arch/arm/mach-realview/platsmp.c20
-rw-r--r--arch/arm/mach-realview/realview_eb.c234
-rw-r--r--arch/arm/mach-sa1100/generic.c2
-rw-r--r--arch/arm/plat-iop/time.c4
-rw-r--r--arch/arm/plat-s3c24xx/time.c2
-rw-r--r--drivers/pcmcia/sa1100_jornada720.c2
-rw-r--r--drivers/serial/21285.c8
-rw-r--r--drivers/serial/atmel_serial.c3
-rw-r--r--include/asm-arm/arch-at91/at91_mci.h2
-rw-r--r--include/asm-arm/arch-at91/at91rm9200.h5
-rw-r--r--include/asm-arm/arch-at91/at91sam9260.h7
-rw-r--r--include/asm-arm/arch-at91/at91sam9261.h4
-rw-r--r--include/asm-arm/arch-at91/at91sam9263.h4
-rw-r--r--include/asm-arm/arch-at91/at91sam9rl.h5
-rw-r--r--include/asm-arm/arch-at91/uncompress.h32
-rw-r--r--include/asm-arm/arch-ixp4xx/cpu.h15
-rw-r--r--include/asm-arm/arch-ixp4xx/dsmg600.h7
-rw-r--r--include/asm-arm/arch-ixp4xx/hardware.h6
-rw-r--r--include/asm-arm/arch-ixp4xx/io.h2
-rw-r--r--include/asm-arm/arch-ixp4xx/ixp4xx-regs.h36
-rw-r--r--include/asm-arm/arch-ixp4xx/nas100d.h18
-rw-r--r--include/asm-arm/arch-ixp4xx/npe.h39
-rw-r--r--include/asm-arm/arch-ixp4xx/nslu2.h21
-rw-r--r--include/asm-arm/arch-ixp4xx/platform.h21
-rw-r--r--include/asm-arm/arch-ixp4xx/qmgr.h126
-rw-r--r--include/asm-arm/arch-ixp4xx/uncompress.h2
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx-regs.h13
-rw-r--r--include/asm-arm/arch-realview/board-eb.h171
-rw-r--r--include/asm-arm/arch-realview/entry-macro.S3
-rw-r--r--include/asm-arm/arch-realview/hardware.h1
-rw-r--r--include/asm-arm/arch-realview/irqs.h105
-rw-r--r--include/asm-arm/arch-realview/platform.h170
-rw-r--r--include/asm-arm/arch-realview/scu.h4
-rw-r--r--include/asm-arm/arch-realview/uncompress.h2
-rw-r--r--include/asm-arm/hardware/arm_twd.h7
-rw-r--r--include/asm-arm/smp.h21
-rw-r--r--include/linux/atmel_serial.h (renamed from drivers/serial/atmel_serial.h)2
78 files changed, 3660 insertions, 1369 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4bd8952eef9a..9d8b7f9bca1d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -33,6 +33,11 @@ config GENERIC_CLOCKEVENTS
33 bool 33 bool
34 default n 34 default n
35 35
36config GENERIC_CLOCKEVENTS_BROADCAST
37 bool
38 depends on GENERIC_CLOCKEVENTS
39 default y if SMP && !LOCAL_TIMERS
40
36config MMU 41config MMU
37 bool 42 bool
38 default y 43 default y
@@ -168,6 +173,8 @@ config ARCH_REALVIEW
168 bool "ARM Ltd. RealView family" 173 bool "ARM Ltd. RealView family"
169 select ARM_AMBA 174 select ARM_AMBA
170 select ICST307 175 select ICST307
176 select GENERIC_TIME
177 select GENERIC_CLOCKEVENTS
171 help 178 help
172 This enables support for ARM Ltd RealView boards. 179 This enables support for ARM Ltd RealView boards.
173 180
@@ -604,7 +611,7 @@ source "kernel/time/Kconfig"
604 611
605config SMP 612config SMP
606 bool "Symmetric Multi-Processing (EXPERIMENTAL)" 613 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
607 depends on EXPERIMENTAL && REALVIEW_MPCORE 614 depends on EXPERIMENTAL && REALVIEW_EB_ARM11MP
608 help 615 help
609 This enables support for systems with more than one CPU. If you have 616 This enables support for systems with more than one CPU. If you have
610 a system with only one CPU, like most personal computers, say N. If 617 a system with only one CPU, like most personal computers, say N. If
@@ -638,7 +645,7 @@ config HOTPLUG_CPU
638 645
639config LOCAL_TIMERS 646config LOCAL_TIMERS
640 bool "Use local timer interrupts" 647 bool "Use local timer interrupts"
641 depends on SMP && REALVIEW_MPCORE 648 depends on SMP && REALVIEW_EB_ARM11MP
642 default y 649 default y
643 help 650 help
644 Enable support for local timers on SMP platforms, rather then the 651 Enable support for local timers on SMP platforms, rather then the
diff --git a/arch/arm/common/time-acorn.c b/arch/arm/common/time-acorn.c
index 34038eccbba9..d544da414731 100644
--- a/arch/arm/common/time-acorn.c
+++ b/arch/arm/common/time-acorn.c
@@ -69,9 +69,7 @@ void __init ioctime_init(void)
69static irqreturn_t 69static irqreturn_t
70ioc_timer_interrupt(int irq, void *dev_id) 70ioc_timer_interrupt(int irq, void *dev_id)
71{ 71{
72 write_seqlock(&xtime_lock);
73 timer_tick(); 72 timer_tick();
74 write_sequnlock(&xtime_lock);
75 return IRQ_HANDLED; 73 return IRQ_HANDLED;
76} 74}
77 75
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index db850a5689eb..efa0485d2f7e 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -1,69 +1,96 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.15 3# Linux kernel version: 2.6.24
4# Tue Jan 3 03:20:40 2006 4# Sun Jan 27 07:33:38 2008
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
7CONFIG_MMU=y 11CONFIG_MMU=y
8CONFIG_UID16=y 12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 27
12# 28#
13# Code maturity level options 29# General setup
14# 30#
15CONFIG_EXPERIMENTAL=y 31CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 32CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 33CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="" 34CONFIG_LOCALVERSION=""
24CONFIG_LOCALVERSION_AUTO=y 35CONFIG_LOCALVERSION_AUTO=y
25CONFIG_SWAP=y 36CONFIG_SWAP=y
26CONFIG_SYSVIPC=y 37CONFIG_SYSVIPC=y
38CONFIG_SYSVIPC_SYSCTL=y
27# CONFIG_POSIX_MQUEUE is not set 39# CONFIG_POSIX_MQUEUE is not set
28CONFIG_BSD_PROCESS_ACCT=y 40CONFIG_BSD_PROCESS_ACCT=y
29# CONFIG_BSD_PROCESS_ACCT_V3 is not set 41# CONFIG_BSD_PROCESS_ACCT_V3 is not set
30CONFIG_SYSCTL=y 42# CONFIG_TASKSTATS is not set
43# CONFIG_USER_NS is not set
44# CONFIG_PID_NS is not set
31# CONFIG_AUDIT is not set 45# CONFIG_AUDIT is not set
32# CONFIG_HOTPLUG is not set
33CONFIG_KOBJECT_UEVENT=y
34# CONFIG_IKCONFIG is not set 46# CONFIG_IKCONFIG is not set
47CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set
49CONFIG_FAIR_GROUP_SCHED=y
50CONFIG_FAIR_USER_SCHED=y
51# CONFIG_FAIR_CGROUP_SCHED is not set
52CONFIG_SYSFS_DEPRECATED=y
53# CONFIG_RELAY is not set
54CONFIG_BLK_DEV_INITRD=y
35CONFIG_INITRAMFS_SOURCE="" 55CONFIG_INITRAMFS_SOURCE=""
36CONFIG_CC_OPTIMIZE_FOR_SIZE=y 56CONFIG_CC_OPTIMIZE_FOR_SIZE=y
57CONFIG_SYSCTL=y
37CONFIG_EMBEDDED=y 58CONFIG_EMBEDDED=y
59CONFIG_UID16=y
60CONFIG_SYSCTL_SYSCALL=y
38CONFIG_KALLSYMS=y 61CONFIG_KALLSYMS=y
39# CONFIG_KALLSYMS_ALL is not set 62# CONFIG_KALLSYMS_ALL is not set
40# CONFIG_KALLSYMS_EXTRA_PASS is not set 63# CONFIG_KALLSYMS_EXTRA_PASS is not set
64CONFIG_HOTPLUG=y
41CONFIG_PRINTK=y 65CONFIG_PRINTK=y
42CONFIG_BUG=y 66CONFIG_BUG=y
67CONFIG_ELF_CORE=y
43CONFIG_BASE_FULL=y 68CONFIG_BASE_FULL=y
44CONFIG_FUTEX=y 69CONFIG_FUTEX=y
70CONFIG_ANON_INODES=y
45CONFIG_EPOLL=y 71CONFIG_EPOLL=y
72CONFIG_SIGNALFD=y
73CONFIG_EVENTFD=y
46CONFIG_SHMEM=y 74CONFIG_SHMEM=y
47CONFIG_CC_ALIGN_FUNCTIONS=0 75CONFIG_VM_EVENT_COUNTERS=y
48CONFIG_CC_ALIGN_LABELS=0 76CONFIG_SLUB_DEBUG=y
49CONFIG_CC_ALIGN_LOOPS=0 77# CONFIG_SLAB is not set
50CONFIG_CC_ALIGN_JUMPS=0 78CONFIG_SLUB=y
79# CONFIG_SLOB is not set
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
51# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
52CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
53
54#
55# Loadable module support
56#
57CONFIG_MODULES=y 84CONFIG_MODULES=y
58# CONFIG_MODULE_UNLOAD is not set 85# CONFIG_MODULE_UNLOAD is not set
59CONFIG_OBSOLETE_MODPARM=y
60CONFIG_MODVERSIONS=y 86CONFIG_MODVERSIONS=y
61# CONFIG_MODULE_SRCVERSION_ALL is not set 87# CONFIG_MODULE_SRCVERSION_ALL is not set
62CONFIG_KMOD=y 88CONFIG_KMOD=y
63 89CONFIG_BLOCK=y
64# 90# CONFIG_LBD is not set
65# Block layer 91# CONFIG_BLK_DEV_IO_TRACE is not set
66# 92# CONFIG_LSF is not set
93# CONFIG_BLK_DEV_BSG is not set
67 94
68# 95#
69# IO Schedulers 96# IO Schedulers
@@ -81,28 +108,39 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
81# 108#
82# System Type 109# System Type
83# 110#
111# CONFIG_ARCH_AAEC2000 is not set
112# CONFIG_ARCH_INTEGRATOR is not set
113# CONFIG_ARCH_REALVIEW is not set
114# CONFIG_ARCH_VERSATILE is not set
115# CONFIG_ARCH_AT91 is not set
84# CONFIG_ARCH_CLPS7500 is not set 116# CONFIG_ARCH_CLPS7500 is not set
85# CONFIG_ARCH_CLPS711X is not set 117# CONFIG_ARCH_CLPS711X is not set
86# CONFIG_ARCH_CO285 is not set 118# CONFIG_ARCH_CO285 is not set
87# CONFIG_ARCH_EBSA110 is not set 119# CONFIG_ARCH_EBSA110 is not set
120# CONFIG_ARCH_EP93XX is not set
88# CONFIG_ARCH_FOOTBRIDGE is not set 121# CONFIG_ARCH_FOOTBRIDGE is not set
89# CONFIG_ARCH_INTEGRATOR is not set 122# CONFIG_ARCH_NETX is not set
90# CONFIG_ARCH_IOP3XX is not set 123# CONFIG_ARCH_H720X is not set
91CONFIG_ARCH_IXP4XX=y 124# CONFIG_ARCH_IMX is not set
125# CONFIG_ARCH_IOP13XX is not set
126# CONFIG_ARCH_IOP32X is not set
127# CONFIG_ARCH_IOP33X is not set
128# CONFIG_ARCH_IXP23XX is not set
92# CONFIG_ARCH_IXP2000 is not set 129# CONFIG_ARCH_IXP2000 is not set
130CONFIG_ARCH_IXP4XX=y
93# CONFIG_ARCH_L7200 is not set 131# CONFIG_ARCH_L7200 is not set
132# CONFIG_ARCH_KS8695 is not set
133# CONFIG_ARCH_NS9XXX is not set
134# CONFIG_ARCH_MXC is not set
135# CONFIG_ARCH_PNX4008 is not set
94# CONFIG_ARCH_PXA is not set 136# CONFIG_ARCH_PXA is not set
95# CONFIG_ARCH_RPC is not set 137# CONFIG_ARCH_RPC is not set
96# CONFIG_ARCH_SA1100 is not set 138# CONFIG_ARCH_SA1100 is not set
97# CONFIG_ARCH_S3C2410 is not set 139# CONFIG_ARCH_S3C2410 is not set
98# CONFIG_ARCH_SHARK is not set 140# CONFIG_ARCH_SHARK is not set
99# CONFIG_ARCH_LH7A40X is not set 141# CONFIG_ARCH_LH7A40X is not set
142# CONFIG_ARCH_DAVINCI is not set
100# CONFIG_ARCH_OMAP is not set 143# CONFIG_ARCH_OMAP is not set
101# CONFIG_ARCH_VERSATILE is not set
102# CONFIG_ARCH_REALVIEW is not set
103# CONFIG_ARCH_IMX is not set
104# CONFIG_ARCH_H720X is not set
105# CONFIG_ARCH_AAEC2000 is not set
106CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y 144CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
107 145
108# 146#
@@ -112,8 +150,12 @@ CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
112# 150#
113# IXP4xx Platforms 151# IXP4xx Platforms
114# 152#
115CONFIG_ARCH_AVILA=y 153CONFIG_MACH_NSLU2=y
154CONFIG_MACH_AVILA=y
155CONFIG_MACH_LOFT=y
116CONFIG_ARCH_ADI_COYOTE=y 156CONFIG_ARCH_ADI_COYOTE=y
157CONFIG_MACH_GATEWAY7001=y
158CONFIG_MACH_WG302V2=y
117CONFIG_ARCH_IXDP425=y 159CONFIG_ARCH_IXDP425=y
118CONFIG_MACH_IXDPG425=y 160CONFIG_MACH_IXDPG425=y
119CONFIG_MACH_IXDP465=y 161CONFIG_MACH_IXDP465=y
@@ -121,15 +163,27 @@ CONFIG_MACH_KIXRP435=y
121CONFIG_ARCH_IXCDP1100=y 163CONFIG_ARCH_IXCDP1100=y
122CONFIG_ARCH_PRPMC1100=y 164CONFIG_ARCH_PRPMC1100=y
123CONFIG_MACH_NAS100D=y 165CONFIG_MACH_NAS100D=y
166CONFIG_MACH_DSMG600=y
124CONFIG_ARCH_IXDP4XX=y 167CONFIG_ARCH_IXDP4XX=y
125CONFIG_CPU_IXP46X=y 168CONFIG_CPU_IXP46X=y
126CONFIG_CPU_IXP43X=y 169CONFIG_CPU_IXP43X=y
127# CONFIG_MACH_GTWX5715 is not set 170CONFIG_MACH_GTWX5715=y
128 171
129# 172#
130# IXP4xx Options 173# IXP4xx Options
131# 174#
175CONFIG_DMABOUNCE=y
132# CONFIG_IXP4XX_INDIRECT_PCI is not set 176# CONFIG_IXP4XX_INDIRECT_PCI is not set
177CONFIG_IXP4XX_QMGR=y
178CONFIG_IXP4XX_NPE=y
179
180#
181# Boot options
182#
183
184#
185# Power management
186#
133 187
134# 188#
135# Processor Type 189# Processor Type
@@ -140,33 +194,40 @@ CONFIG_CPU_32v5=y
140CONFIG_CPU_ABRT_EV5T=y 194CONFIG_CPU_ABRT_EV5T=y
141CONFIG_CPU_CACHE_VIVT=y 195CONFIG_CPU_CACHE_VIVT=y
142CONFIG_CPU_TLB_V4WBI=y 196CONFIG_CPU_TLB_V4WBI=y
197CONFIG_CPU_CP15=y
198CONFIG_CPU_CP15_MMU=y
143 199
144# 200#
145# Processor Features 201# Processor Features
146# 202#
147# CONFIG_ARM_THUMB is not set 203# CONFIG_ARM_THUMB is not set
148CONFIG_CPU_BIG_ENDIAN=y 204CONFIG_CPU_BIG_ENDIAN=y
205# CONFIG_CPU_DCACHE_DISABLE is not set
206# CONFIG_OUTER_CACHE is not set
207# CONFIG_IWMMXT is not set
149CONFIG_XSCALE_PMU=y 208CONFIG_XSCALE_PMU=y
150CONFIG_DMABOUNCE=y
151 209
152# 210#
153# Bus support 211# Bus support
154# 212#
155CONFIG_ISA_DMA_API=y
156CONFIG_PCI=y 213CONFIG_PCI=y
157CONFIG_PCI_LEGACY_PROC=y 214CONFIG_PCI_SYSCALL=y
215# CONFIG_ARCH_SUPPORTS_MSI is not set
216CONFIG_PCI_LEGACY=y
158# CONFIG_PCI_DEBUG is not set 217# CONFIG_PCI_DEBUG is not set
159
160#
161# PCCARD (PCMCIA/CardBus) support
162#
163# CONFIG_PCCARD is not set 218# CONFIG_PCCARD is not set
164 219
165# 220#
166# Kernel Features 221# Kernel Features
167# 222#
223# CONFIG_TICK_ONESHOT is not set
224# CONFIG_NO_HZ is not set
225# CONFIG_HIGH_RES_TIMERS is not set
226CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
168# CONFIG_PREEMPT is not set 227# CONFIG_PREEMPT is not set
169# CONFIG_NO_IDLE_HZ is not set 228CONFIG_HZ=100
229CONFIG_AEABI=y
230CONFIG_OABI_COMPAT=y
170# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 231# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
171CONFIG_SELECT_MEMORY_MODEL=y 232CONFIG_SELECT_MEMORY_MODEL=y
172CONFIG_FLATMEM_MANUAL=y 233CONFIG_FLATMEM_MANUAL=y
@@ -175,7 +236,12 @@ CONFIG_FLATMEM_MANUAL=y
175CONFIG_FLATMEM=y 236CONFIG_FLATMEM=y
176CONFIG_FLAT_NODE_MEM_MAP=y 237CONFIG_FLAT_NODE_MEM_MAP=y
177# CONFIG_SPARSEMEM_STATIC is not set 238# CONFIG_SPARSEMEM_STATIC is not set
239# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
178CONFIG_SPLIT_PTLOCK_CPUS=4096 240CONFIG_SPLIT_PTLOCK_CPUS=4096
241# CONFIG_RESOURCES_64BIT is not set
242CONFIG_ZONE_DMA_FLAG=1
243CONFIG_BOUNCE=y
244CONFIG_VIRT_TO_BUS=y
179CONFIG_ALIGNMENT_TRAP=y 245CONFIG_ALIGNMENT_TRAP=y
180 246
181# 247#
@@ -185,6 +251,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
185CONFIG_ZBOOT_ROM_BSS=0x0 251CONFIG_ZBOOT_ROM_BSS=0x0
186CONFIG_CMDLINE="console=ttyS0,115200 ip=bootp root=/dev/nfs" 252CONFIG_CMDLINE="console=ttyS0,115200 ip=bootp root=/dev/nfs"
187# CONFIG_XIP_KERNEL is not set 253# CONFIG_XIP_KERNEL is not set
254# CONFIG_KEXEC is not set
188 255
189# 256#
190# Floating point emulation 257# Floating point emulation
@@ -203,13 +270,12 @@ CONFIG_FPE_NWFPE=y
203CONFIG_BINFMT_ELF=y 270CONFIG_BINFMT_ELF=y
204# CONFIG_BINFMT_AOUT is not set 271# CONFIG_BINFMT_AOUT is not set
205# CONFIG_BINFMT_MISC is not set 272# CONFIG_BINFMT_MISC is not set
206# CONFIG_ARTHUR is not set
207 273
208# 274#
209# Power management options 275# Power management options
210# 276#
211# CONFIG_PM is not set 277# CONFIG_PM is not set
212# CONFIG_APM is not set 278CONFIG_SUSPEND_UP_POSSIBLE=y
213 279
214# 280#
215# Networking 281# Networking
@@ -219,11 +285,13 @@ CONFIG_NET=y
219# 285#
220# Networking options 286# Networking options
221# 287#
222CONFIG_PACKET=m 288CONFIG_PACKET=y
223CONFIG_PACKET_MMAP=y 289CONFIG_PACKET_MMAP=y
224CONFIG_UNIX=y 290CONFIG_UNIX=y
225CONFIG_XFRM=y 291CONFIG_XFRM=y
226# CONFIG_XFRM_USER is not set 292# CONFIG_XFRM_USER is not set
293# CONFIG_XFRM_SUB_POLICY is not set
294# CONFIG_XFRM_MIGRATE is not set
227# CONFIG_NET_KEY is not set 295# CONFIG_NET_KEY is not set
228CONFIG_INET=y 296CONFIG_INET=y
229CONFIG_IP_MULTICAST=y 297CONFIG_IP_MULTICAST=y
@@ -232,9 +300,7 @@ CONFIG_ASK_IP_FIB_HASH=y
232# CONFIG_IP_FIB_TRIE is not set 300# CONFIG_IP_FIB_TRIE is not set
233CONFIG_IP_FIB_HASH=y 301CONFIG_IP_FIB_HASH=y
234CONFIG_IP_MULTIPLE_TABLES=y 302CONFIG_IP_MULTIPLE_TABLES=y
235CONFIG_IP_ROUTE_FWMARK=y
236CONFIG_IP_ROUTE_MULTIPATH=y 303CONFIG_IP_ROUTE_MULTIPATH=y
237# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
238CONFIG_IP_ROUTE_VERBOSE=y 304CONFIG_IP_ROUTE_VERBOSE=y
239CONFIG_IP_PNP=y 305CONFIG_IP_PNP=y
240CONFIG_IP_PNP_DHCP=y 306CONFIG_IP_PNP_DHCP=y
@@ -251,15 +317,18 @@ CONFIG_SYN_COOKIES=y
251# CONFIG_INET_AH is not set 317# CONFIG_INET_AH is not set
252# CONFIG_INET_ESP is not set 318# CONFIG_INET_ESP is not set
253# CONFIG_INET_IPCOMP is not set 319# CONFIG_INET_IPCOMP is not set
254CONFIG_INET_TUNNEL=m 320# CONFIG_INET_XFRM_TUNNEL is not set
321# CONFIG_INET_TUNNEL is not set
322CONFIG_INET_XFRM_MODE_TRANSPORT=y
323CONFIG_INET_XFRM_MODE_TUNNEL=y
324CONFIG_INET_XFRM_MODE_BEET=y
325# CONFIG_INET_LRO is not set
255CONFIG_INET_DIAG=y 326CONFIG_INET_DIAG=y
256CONFIG_INET_TCP_DIAG=y 327CONFIG_INET_TCP_DIAG=y
257# CONFIG_TCP_CONG_ADVANCED is not set 328# CONFIG_TCP_CONG_ADVANCED is not set
258CONFIG_TCP_CONG_BIC=y 329CONFIG_TCP_CONG_CUBIC=y
259 330CONFIG_DEFAULT_TCP_CONG="cubic"
260# 331# CONFIG_TCP_MD5SIG is not set
261# IP: Virtual Server Configuration
262#
263CONFIG_IP_VS=m 332CONFIG_IP_VS=m
264CONFIG_IP_VS_DEBUG=y 333CONFIG_IP_VS_DEBUG=y
265CONFIG_IP_VS_TAB_BITS=12 334CONFIG_IP_VS_TAB_BITS=12
@@ -290,6 +359,9 @@ CONFIG_IP_VS_SH=m
290# IPVS application helper 359# IPVS application helper
291# 360#
292# CONFIG_IPV6 is not set 361# CONFIG_IPV6 is not set
362# CONFIG_INET6_XFRM_TUNNEL is not set
363# CONFIG_INET6_TUNNEL is not set
364# CONFIG_NETWORK_SECMARK is not set
293CONFIG_NETFILTER=y 365CONFIG_NETFILTER=y
294# CONFIG_NETFILTER_DEBUG is not set 366# CONFIG_NETFILTER_DEBUG is not set
295CONFIG_BRIDGE_NETFILTER=y 367CONFIG_BRIDGE_NETFILTER=y
@@ -298,70 +370,57 @@ CONFIG_BRIDGE_NETFILTER=y
298# Core Netfilter Configuration 370# Core Netfilter Configuration
299# 371#
300# CONFIG_NETFILTER_NETLINK is not set 372# CONFIG_NETFILTER_NETLINK is not set
373# CONFIG_NF_CONNTRACK_ENABLED is not set
374# CONFIG_NF_CONNTRACK is not set
375CONFIG_NETFILTER_XTABLES=m
376# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
377# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
378# CONFIG_NETFILTER_XT_TARGET_MARK is not set
379# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
380# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
381# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
382# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
383# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
384# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
385# CONFIG_NETFILTER_XT_MATCH_ESP is not set
386# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
387# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
388# CONFIG_NETFILTER_XT_MATCH_MAC is not set
389# CONFIG_NETFILTER_XT_MATCH_MARK is not set
390# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
391# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
392# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
393# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
394# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
395# CONFIG_NETFILTER_XT_MATCH_REALM is not set
396# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
397# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
398# CONFIG_NETFILTER_XT_MATCH_STRING is not set
399# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
400# CONFIG_NETFILTER_XT_MATCH_TIME is not set
401# CONFIG_NETFILTER_XT_MATCH_U32 is not set
402# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
301 403
302# 404#
303# IP: Netfilter Configuration 405# IP: Netfilter Configuration
304# 406#
305CONFIG_IP_NF_CONNTRACK=m
306# CONFIG_IP_NF_CT_ACCT is not set
307# CONFIG_IP_NF_CONNTRACK_MARK is not set
308# CONFIG_IP_NF_CONNTRACK_EVENTS is not set
309# CONFIG_IP_NF_CT_PROTO_SCTP is not set
310CONFIG_IP_NF_FTP=m
311CONFIG_IP_NF_IRC=m
312# CONFIG_IP_NF_NETBIOS_NS is not set
313# CONFIG_IP_NF_TFTP is not set
314# CONFIG_IP_NF_AMANDA is not set
315# CONFIG_IP_NF_PPTP is not set
316CONFIG_IP_NF_QUEUE=m 407CONFIG_IP_NF_QUEUE=m
317CONFIG_IP_NF_IPTABLES=m 408CONFIG_IP_NF_IPTABLES=m
318CONFIG_IP_NF_MATCH_LIMIT=m
319# CONFIG_IP_NF_MATCH_IPRANGE is not set 409# CONFIG_IP_NF_MATCH_IPRANGE is not set
320CONFIG_IP_NF_MATCH_MAC=m
321# CONFIG_IP_NF_MATCH_PKTTYPE is not set
322CONFIG_IP_NF_MATCH_MARK=m
323CONFIG_IP_NF_MATCH_MULTIPORT=m
324CONFIG_IP_NF_MATCH_TOS=m 410CONFIG_IP_NF_MATCH_TOS=m
325# CONFIG_IP_NF_MATCH_RECENT is not set 411# CONFIG_IP_NF_MATCH_RECENT is not set
326# CONFIG_IP_NF_MATCH_ECN is not set 412# CONFIG_IP_NF_MATCH_ECN is not set
327# CONFIG_IP_NF_MATCH_DSCP is not set 413# CONFIG_IP_NF_MATCH_AH is not set
328CONFIG_IP_NF_MATCH_AH_ESP=m
329CONFIG_IP_NF_MATCH_LENGTH=m
330CONFIG_IP_NF_MATCH_TTL=m 414CONFIG_IP_NF_MATCH_TTL=m
331CONFIG_IP_NF_MATCH_TCPMSS=m
332# CONFIG_IP_NF_MATCH_HELPER is not set
333CONFIG_IP_NF_MATCH_STATE=m
334# CONFIG_IP_NF_MATCH_CONNTRACK is not set
335CONFIG_IP_NF_MATCH_OWNER=m 415CONFIG_IP_NF_MATCH_OWNER=m
336# CONFIG_IP_NF_MATCH_PHYSDEV is not set
337# CONFIG_IP_NF_MATCH_ADDRTYPE is not set 416# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
338# CONFIG_IP_NF_MATCH_REALM is not set
339# CONFIG_IP_NF_MATCH_SCTP is not set
340# CONFIG_IP_NF_MATCH_DCCP is not set
341# CONFIG_IP_NF_MATCH_COMMENT is not set
342# CONFIG_IP_NF_MATCH_HASHLIMIT is not set
343# CONFIG_IP_NF_MATCH_STRING is not set
344CONFIG_IP_NF_FILTER=m 417CONFIG_IP_NF_FILTER=m
345CONFIG_IP_NF_TARGET_REJECT=m 418CONFIG_IP_NF_TARGET_REJECT=m
346CONFIG_IP_NF_TARGET_LOG=m 419CONFIG_IP_NF_TARGET_LOG=m
347CONFIG_IP_NF_TARGET_ULOG=m 420CONFIG_IP_NF_TARGET_ULOG=m
348CONFIG_IP_NF_TARGET_TCPMSS=m
349# CONFIG_IP_NF_TARGET_NFQUEUE is not set
350CONFIG_IP_NF_NAT=m
351CONFIG_IP_NF_NAT_NEEDED=y
352CONFIG_IP_NF_TARGET_MASQUERADE=m
353CONFIG_IP_NF_TARGET_REDIRECT=m
354# CONFIG_IP_NF_TARGET_NETMAP is not set
355# CONFIG_IP_NF_TARGET_SAME is not set
356CONFIG_IP_NF_NAT_SNMP_BASIC=m
357CONFIG_IP_NF_NAT_IRC=m
358CONFIG_IP_NF_NAT_FTP=m
359CONFIG_IP_NF_MANGLE=m 421CONFIG_IP_NF_MANGLE=m
360CONFIG_IP_NF_TARGET_TOS=m 422CONFIG_IP_NF_TARGET_TOS=m
361# CONFIG_IP_NF_TARGET_ECN is not set 423# CONFIG_IP_NF_TARGET_ECN is not set
362# CONFIG_IP_NF_TARGET_DSCP is not set
363CONFIG_IP_NF_TARGET_MARK=m
364# CONFIG_IP_NF_TARGET_CLASSIFY is not set
365# CONFIG_IP_NF_TARGET_TTL is not set 424# CONFIG_IP_NF_TARGET_TTL is not set
366# CONFIG_IP_NF_RAW is not set 425# CONFIG_IP_NF_RAW is not set
367CONFIG_IP_NF_ARPTABLES=m 426CONFIG_IP_NF_ARPTABLES=m
@@ -372,16 +431,9 @@ CONFIG_IP_NF_ARPFILTER=m
372# Bridge: Netfilter Configuration 431# Bridge: Netfilter Configuration
373# 432#
374# CONFIG_BRIDGE_NF_EBTABLES is not set 433# CONFIG_BRIDGE_NF_EBTABLES is not set
375
376#
377# DCCP Configuration (EXPERIMENTAL)
378#
379# CONFIG_IP_DCCP is not set 434# CONFIG_IP_DCCP is not set
380
381#
382# SCTP Configuration (EXPERIMENTAL)
383#
384# CONFIG_IP_SCTP is not set 435# CONFIG_IP_SCTP is not set
436# CONFIG_TIPC is not set
385CONFIG_ATM=y 437CONFIG_ATM=y
386CONFIG_ATM_CLIP=y 438CONFIG_ATM_CLIP=y
387# CONFIG_ATM_CLIP_NO_ICMP is not set 439# CONFIG_ATM_CLIP_NO_ICMP is not set
@@ -397,25 +449,17 @@ CONFIG_LLC=m
397CONFIG_IPX=m 449CONFIG_IPX=m
398# CONFIG_IPX_INTERN is not set 450# CONFIG_IPX_INTERN is not set
399CONFIG_ATALK=m 451CONFIG_ATALK=m
400CONFIG_DEV_APPLETALK=y 452CONFIG_DEV_APPLETALK=m
401CONFIG_IPDDP=m 453CONFIG_IPDDP=m
402CONFIG_IPDDP_ENCAP=y 454CONFIG_IPDDP_ENCAP=y
403CONFIG_IPDDP_DECAP=y 455CONFIG_IPDDP_DECAP=y
404CONFIG_X25=m 456CONFIG_X25=m
405CONFIG_LAPB=m 457CONFIG_LAPB=m
406# CONFIG_NET_DIVERT is not set
407CONFIG_ECONET=m 458CONFIG_ECONET=m
408CONFIG_ECONET_AUNUDP=y 459CONFIG_ECONET_AUNUDP=y
409CONFIG_ECONET_NATIVE=y 460CONFIG_ECONET_NATIVE=y
410CONFIG_WAN_ROUTER=m 461CONFIG_WAN_ROUTER=m
411
412#
413# QoS and/or fair queueing
414#
415CONFIG_NET_SCHED=y 462CONFIG_NET_SCHED=y
416CONFIG_NET_SCH_CLK_JIFFIES=y
417# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
418# CONFIG_NET_SCH_CLK_CPU is not set
419 463
420# 464#
421# Queueing/Scheduling 465# Queueing/Scheduling
@@ -425,6 +469,7 @@ CONFIG_NET_SCH_HTB=m
425# CONFIG_NET_SCH_HFSC is not set 469# CONFIG_NET_SCH_HFSC is not set
426# CONFIG_NET_SCH_ATM is not set 470# CONFIG_NET_SCH_ATM is not set
427CONFIG_NET_SCH_PRIO=m 471CONFIG_NET_SCH_PRIO=m
472# CONFIG_NET_SCH_RR is not set
428CONFIG_NET_SCH_RED=m 473CONFIG_NET_SCH_RED=m
429CONFIG_NET_SCH_SFQ=m 474CONFIG_NET_SCH_SFQ=m
430CONFIG_NET_SCH_TEQL=m 475CONFIG_NET_SCH_TEQL=m
@@ -449,10 +494,17 @@ CONFIG_NET_CLS_U32=m
449CONFIG_NET_CLS_RSVP=m 494CONFIG_NET_CLS_RSVP=m
450CONFIG_NET_CLS_RSVP6=m 495CONFIG_NET_CLS_RSVP6=m
451# CONFIG_NET_EMATCH is not set 496# CONFIG_NET_EMATCH is not set
452# CONFIG_NET_CLS_ACT is not set 497CONFIG_NET_CLS_ACT=y
498CONFIG_NET_ACT_POLICE=y
499# CONFIG_NET_ACT_GACT is not set
500# CONFIG_NET_ACT_MIRRED is not set
501# CONFIG_NET_ACT_IPT is not set
502# CONFIG_NET_ACT_NAT is not set
503# CONFIG_NET_ACT_PEDIT is not set
504# CONFIG_NET_ACT_SIMP is not set
453CONFIG_NET_CLS_POLICE=y 505CONFIG_NET_CLS_POLICE=y
454# CONFIG_NET_CLS_IND is not set 506# CONFIG_NET_CLS_IND is not set
455CONFIG_NET_ESTIMATOR=y 507CONFIG_NET_SCH_FIFO=y
456 508
457# 509#
458# Network testing 510# Network testing
@@ -461,7 +513,18 @@ CONFIG_NET_PKTGEN=m
461# CONFIG_HAMRADIO is not set 513# CONFIG_HAMRADIO is not set
462# CONFIG_IRDA is not set 514# CONFIG_IRDA is not set
463# CONFIG_BT is not set 515# CONFIG_BT is not set
516# CONFIG_AF_RXRPC is not set
517CONFIG_FIB_RULES=y
518
519#
520# Wireless
521#
522# CONFIG_CFG80211 is not set
523# CONFIG_WIRELESS_EXT is not set
524# CONFIG_MAC80211 is not set
464# CONFIG_IEEE80211 is not set 525# CONFIG_IEEE80211 is not set
526# CONFIG_RFKILL is not set
527# CONFIG_NET_9P is not set
465 528
466# 529#
467# Device Drivers 530# Device Drivers
@@ -470,19 +533,14 @@ CONFIG_NET_PKTGEN=m
470# 533#
471# Generic Driver Options 534# Generic Driver Options
472# 535#
536CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
473CONFIG_STANDALONE=y 537CONFIG_STANDALONE=y
474CONFIG_PREVENT_FIRMWARE_BUILD=y 538CONFIG_PREVENT_FIRMWARE_BUILD=y
475# CONFIG_FW_LOADER is not set 539CONFIG_FW_LOADER=y
476# CONFIG_DEBUG_DRIVER is not set 540# CONFIG_DEBUG_DRIVER is not set
477 541# CONFIG_DEBUG_DEVRES is not set
478# 542# CONFIG_SYS_HYPERVISOR is not set
479# Connector - unified userspace <-> kernelspace linker
480#
481# CONFIG_CONNECTOR is not set 543# CONFIG_CONNECTOR is not set
482
483#
484# Memory Technology Devices (MTD)
485#
486CONFIG_MTD=y 544CONFIG_MTD=y
487# CONFIG_MTD_DEBUG is not set 545# CONFIG_MTD_DEBUG is not set
488# CONFIG_MTD_CONCAT is not set 546# CONFIG_MTD_CONCAT is not set
@@ -498,11 +556,14 @@ CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
498# User Modules And Translation Layers 556# User Modules And Translation Layers
499# 557#
500CONFIG_MTD_CHAR=y 558CONFIG_MTD_CHAR=y
559CONFIG_MTD_BLKDEVS=y
501CONFIG_MTD_BLOCK=y 560CONFIG_MTD_BLOCK=y
502# CONFIG_FTL is not set 561# CONFIG_FTL is not set
503# CONFIG_NFTL is not set 562# CONFIG_NFTL is not set
504# CONFIG_INFTL is not set 563# CONFIG_INFTL is not set
505# CONFIG_RFD_FTL is not set 564# CONFIG_RFD_FTL is not set
565# CONFIG_SSFDC is not set
566# CONFIG_MTD_OOPS is not set
506 567
507# 568#
508# RAM/ROM/Flash chip drivers 569# RAM/ROM/Flash chip drivers
@@ -528,7 +589,6 @@ CONFIG_MTD_CFI_UTIL=y
528# CONFIG_MTD_RAM is not set 589# CONFIG_MTD_RAM is not set
529# CONFIG_MTD_ROM is not set 590# CONFIG_MTD_ROM is not set
530# CONFIG_MTD_ABSENT is not set 591# CONFIG_MTD_ABSENT is not set
531# CONFIG_MTD_XIP is not set
532 592
533# 593#
534# Mapping drivers for chip access 594# Mapping drivers for chip access
@@ -538,6 +598,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
538# CONFIG_MTD_ARM_INTEGRATOR is not set 598# CONFIG_MTD_ARM_INTEGRATOR is not set
539CONFIG_MTD_IXP4XX=y 599CONFIG_MTD_IXP4XX=y
540# CONFIG_MTD_PCI is not set 600# CONFIG_MTD_PCI is not set
601# CONFIG_MTD_INTEL_VR_NOR is not set
541# CONFIG_MTD_PLATRAM is not set 602# CONFIG_MTD_PLATRAM is not set
542 603
543# 604#
@@ -547,7 +608,6 @@ CONFIG_MTD_IXP4XX=y
547# CONFIG_MTD_SLRAM is not set 608# CONFIG_MTD_SLRAM is not set
548# CONFIG_MTD_PHRAM is not set 609# CONFIG_MTD_PHRAM is not set
549# CONFIG_MTD_MTDRAM is not set 610# CONFIG_MTD_MTDRAM is not set
550# CONFIG_MTD_BLKMTD is not set
551# CONFIG_MTD_BLOCK2MTD is not set 611# CONFIG_MTD_BLOCK2MTD is not set
552 612
553# 613#
@@ -556,33 +616,24 @@ CONFIG_MTD_IXP4XX=y
556# CONFIG_MTD_DOC2000 is not set 616# CONFIG_MTD_DOC2000 is not set
557# CONFIG_MTD_DOC2001 is not set 617# CONFIG_MTD_DOC2001 is not set
558# CONFIG_MTD_DOC2001PLUS is not set 618# CONFIG_MTD_DOC2001PLUS is not set
559
560#
561# NAND Flash Device Drivers
562#
563CONFIG_MTD_NAND=m 619CONFIG_MTD_NAND=m
564# CONFIG_MTD_NAND_VERIFY_WRITE is not set 620# CONFIG_MTD_NAND_VERIFY_WRITE is not set
621# CONFIG_MTD_NAND_ECC_SMC is not set
622# CONFIG_MTD_NAND_MUSEUM_IDS is not set
565CONFIG_MTD_NAND_IDS=m 623CONFIG_MTD_NAND_IDS=m
566# CONFIG_MTD_NAND_DISKONCHIP is not set 624# CONFIG_MTD_NAND_DISKONCHIP is not set
625# CONFIG_MTD_NAND_CAFE is not set
567# CONFIG_MTD_NAND_NANDSIM is not set 626# CONFIG_MTD_NAND_NANDSIM is not set
568 627# CONFIG_MTD_NAND_PLATFORM is not set
569# 628# CONFIG_MTD_ALAUDA is not set
570# OneNAND Flash Device Drivers
571#
572# CONFIG_MTD_ONENAND is not set 629# CONFIG_MTD_ONENAND is not set
573 630
574# 631#
575# Parallel port support 632# UBI - Unsorted block images
576# 633#
634# CONFIG_MTD_UBI is not set
577# CONFIG_PARPORT is not set 635# CONFIG_PARPORT is not set
578 636CONFIG_BLK_DEV=y
579#
580# Plug and Play support
581#
582
583#
584# Block devices
585#
586# CONFIG_BLK_CPQ_DA is not set 637# CONFIG_BLK_CPQ_DA is not set
587# CONFIG_BLK_CPQ_CISS_DA is not set 638# CONFIG_BLK_CPQ_CISS_DA is not set
588# CONFIG_BLK_DEV_DAC960 is not set 639# CONFIG_BLK_DEV_DAC960 is not set
@@ -592,17 +643,20 @@ CONFIG_BLK_DEV_LOOP=y
592# CONFIG_BLK_DEV_CRYPTOLOOP is not set 643# CONFIG_BLK_DEV_CRYPTOLOOP is not set
593# CONFIG_BLK_DEV_NBD is not set 644# CONFIG_BLK_DEV_NBD is not set
594# CONFIG_BLK_DEV_SX8 is not set 645# CONFIG_BLK_DEV_SX8 is not set
646# CONFIG_BLK_DEV_UB is not set
595CONFIG_BLK_DEV_RAM=y 647CONFIG_BLK_DEV_RAM=y
596CONFIG_BLK_DEV_RAM_COUNT=16 648CONFIG_BLK_DEV_RAM_COUNT=16
597CONFIG_BLK_DEV_RAM_SIZE=8192 649CONFIG_BLK_DEV_RAM_SIZE=8192
598CONFIG_BLK_DEV_INITRD=y 650CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
599# CONFIG_CDROM_PKTCDVD is not set 651# CONFIG_CDROM_PKTCDVD is not set
600# CONFIG_ATA_OVER_ETH is not set 652# CONFIG_ATA_OVER_ETH is not set
601 653CONFIG_MISC_DEVICES=y
602# 654# CONFIG_PHANTOM is not set
603# ATA/ATAPI/MFM/RLL support 655# CONFIG_EEPROM_93CX6 is not set
604# 656# CONFIG_SGI_IOC4 is not set
657# CONFIG_TIFM_CORE is not set
605CONFIG_IDE=y 658CONFIG_IDE=y
659CONFIG_IDE_MAX_HWIFS=4
606CONFIG_BLK_DEV_IDE=y 660CONFIG_BLK_DEV_IDE=y
607 661
608# 662#
@@ -614,24 +668,28 @@ CONFIG_BLK_DEV_IDEDISK=y
614# CONFIG_BLK_DEV_IDECD is not set 668# CONFIG_BLK_DEV_IDECD is not set
615# CONFIG_BLK_DEV_IDETAPE is not set 669# CONFIG_BLK_DEV_IDETAPE is not set
616# CONFIG_BLK_DEV_IDEFLOPPY is not set 670# CONFIG_BLK_DEV_IDEFLOPPY is not set
671# CONFIG_BLK_DEV_IDESCSI is not set
617# CONFIG_IDE_TASK_IOCTL is not set 672# CONFIG_IDE_TASK_IOCTL is not set
673CONFIG_IDE_PROC_FS=y
618 674
619# 675#
620# IDE chipset support/bugfixes 676# IDE chipset support/bugfixes
621# 677#
622CONFIG_IDE_GENERIC=y 678CONFIG_IDE_GENERIC=y
679# CONFIG_BLK_DEV_PLATFORM is not set
680
681#
682# PCI IDE chipsets support
683#
623CONFIG_BLK_DEV_IDEPCI=y 684CONFIG_BLK_DEV_IDEPCI=y
624# CONFIG_IDEPCI_SHARE_IRQ is not set 685# CONFIG_IDEPCI_SHARE_IRQ is not set
686CONFIG_IDEPCI_PCIBUS_ORDER=y
625# CONFIG_BLK_DEV_OFFBOARD is not set 687# CONFIG_BLK_DEV_OFFBOARD is not set
626# CONFIG_BLK_DEV_GENERIC is not set 688# CONFIG_BLK_DEV_GENERIC is not set
627# CONFIG_BLK_DEV_OPTI621 is not set 689# CONFIG_BLK_DEV_OPTI621 is not set
628# CONFIG_BLK_DEV_SL82C105 is not set
629CONFIG_BLK_DEV_IDEDMA_PCI=y 690CONFIG_BLK_DEV_IDEDMA_PCI=y
630# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
631# CONFIG_IDEDMA_PCI_AUTO is not set
632# CONFIG_BLK_DEV_AEC62XX is not set 691# CONFIG_BLK_DEV_AEC62XX is not set
633# CONFIG_BLK_DEV_ALI15X3 is not set 692# CONFIG_BLK_DEV_ALI15X3 is not set
634# CONFIG_BLK_DEV_AMD74XX is not set
635CONFIG_BLK_DEV_CMD64X=y 693CONFIG_BLK_DEV_CMD64X=y
636# CONFIG_BLK_DEV_TRIFLEX is not set 694# CONFIG_BLK_DEV_TRIFLEX is not set
637# CONFIG_BLK_DEV_CY82C693 is not set 695# CONFIG_BLK_DEV_CY82C693 is not set
@@ -639,93 +697,163 @@ CONFIG_BLK_DEV_CMD64X=y
639# CONFIG_BLK_DEV_CS5530 is not set 697# CONFIG_BLK_DEV_CS5530 is not set
640# CONFIG_BLK_DEV_HPT34X is not set 698# CONFIG_BLK_DEV_HPT34X is not set
641CONFIG_BLK_DEV_HPT366=y 699CONFIG_BLK_DEV_HPT366=y
700# CONFIG_BLK_DEV_JMICRON is not set
642# CONFIG_BLK_DEV_SC1200 is not set 701# CONFIG_BLK_DEV_SC1200 is not set
643# CONFIG_BLK_DEV_PIIX is not set 702# CONFIG_BLK_DEV_PIIX is not set
703# CONFIG_BLK_DEV_IT8213 is not set
644# CONFIG_BLK_DEV_IT821X is not set 704# CONFIG_BLK_DEV_IT821X is not set
645# CONFIG_BLK_DEV_NS87415 is not set 705# CONFIG_BLK_DEV_NS87415 is not set
646# CONFIG_BLK_DEV_PDC202XX_OLD is not set 706# CONFIG_BLK_DEV_PDC202XX_OLD is not set
647CONFIG_BLK_DEV_PDC202XX_NEW=y 707CONFIG_BLK_DEV_PDC202XX_NEW=y
648# CONFIG_PDC202XX_FORCE is not set
649# CONFIG_BLK_DEV_SVWKS is not set 708# CONFIG_BLK_DEV_SVWKS is not set
650# CONFIG_BLK_DEV_SIIMAGE is not set 709# CONFIG_BLK_DEV_SIIMAGE is not set
710# CONFIG_BLK_DEV_SL82C105 is not set
651# CONFIG_BLK_DEV_SLC90E66 is not set 711# CONFIG_BLK_DEV_SLC90E66 is not set
652# CONFIG_BLK_DEV_TRM290 is not set 712# CONFIG_BLK_DEV_TRM290 is not set
653# CONFIG_BLK_DEV_VIA82CXXX is not set 713# CONFIG_BLK_DEV_VIA82CXXX is not set
714# CONFIG_BLK_DEV_TC86C001 is not set
654# CONFIG_IDE_ARM is not set 715# CONFIG_IDE_ARM is not set
655CONFIG_BLK_DEV_IDEDMA=y 716CONFIG_BLK_DEV_IDEDMA=y
656# CONFIG_IDEDMA_IVB is not set 717CONFIG_IDE_ARCH_OBSOLETE_INIT=y
657# CONFIG_IDEDMA_AUTO is not set
658# CONFIG_BLK_DEV_HD is not set 718# CONFIG_BLK_DEV_HD is not set
659 719
660# 720#
661# SCSI device support 721# SCSI device support
662# 722#
663# CONFIG_RAID_ATTRS is not set 723# CONFIG_RAID_ATTRS is not set
664# CONFIG_SCSI is not set 724CONFIG_SCSI=y
665 725CONFIG_SCSI_DMA=y
666# 726# CONFIG_SCSI_TGT is not set
667# Multi-device support (RAID and LVM) 727# CONFIG_SCSI_NETLINK is not set
668# 728# CONFIG_SCSI_PROC_FS is not set
729
730#
731# SCSI support type (disk, tape, CD-ROM)
732#
733CONFIG_BLK_DEV_SD=y
734# CONFIG_CHR_DEV_ST is not set
735# CONFIG_CHR_DEV_OSST is not set
736# CONFIG_BLK_DEV_SR is not set
737# CONFIG_CHR_DEV_SG is not set
738# CONFIG_CHR_DEV_SCH is not set
739
740#
741# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
742#
743# CONFIG_SCSI_MULTI_LUN is not set
744# CONFIG_SCSI_CONSTANTS is not set
745# CONFIG_SCSI_LOGGING is not set
746# CONFIG_SCSI_SCAN_ASYNC is not set
747CONFIG_SCSI_WAIT_SCAN=m
748
749#
750# SCSI Transports
751#
752# CONFIG_SCSI_SPI_ATTRS is not set
753# CONFIG_SCSI_FC_ATTRS is not set
754# CONFIG_SCSI_ISCSI_ATTRS is not set
755# CONFIG_SCSI_SAS_LIBSAS is not set
756# CONFIG_SCSI_SRP_ATTRS is not set
757# CONFIG_SCSI_LOWLEVEL is not set
758CONFIG_ATA=y
759# CONFIG_ATA_NONSTANDARD is not set
760# CONFIG_SATA_AHCI is not set
761# CONFIG_SATA_SVW is not set
762# CONFIG_ATA_PIIX is not set
763# CONFIG_SATA_MV is not set
764# CONFIG_SATA_NV is not set
765# CONFIG_PDC_ADMA is not set
766# CONFIG_SATA_QSTOR is not set
767# CONFIG_SATA_PROMISE is not set
768# CONFIG_SATA_SX4 is not set
769# CONFIG_SATA_SIL is not set
770# CONFIG_SATA_SIL24 is not set
771# CONFIG_SATA_SIS is not set
772# CONFIG_SATA_ULI is not set
773# CONFIG_SATA_VIA is not set
774# CONFIG_SATA_VITESSE is not set
775# CONFIG_SATA_INIC162X is not set
776# CONFIG_PATA_ALI is not set
777# CONFIG_PATA_AMD is not set
778CONFIG_PATA_ARTOP=y
779# CONFIG_PATA_ATIIXP is not set
780# CONFIG_PATA_CMD640_PCI is not set
781# CONFIG_PATA_CMD64X is not set
782# CONFIG_PATA_CS5520 is not set
783# CONFIG_PATA_CS5530 is not set
784# CONFIG_PATA_CYPRESS is not set
785# CONFIG_PATA_EFAR is not set
786# CONFIG_ATA_GENERIC is not set
787# CONFIG_PATA_HPT366 is not set
788# CONFIG_PATA_HPT37X is not set
789# CONFIG_PATA_HPT3X2N is not set
790# CONFIG_PATA_HPT3X3 is not set
791# CONFIG_PATA_IT821X is not set
792# CONFIG_PATA_IT8213 is not set
793# CONFIG_PATA_JMICRON is not set
794# CONFIG_PATA_TRIFLEX is not set
795# CONFIG_PATA_MARVELL is not set
796# CONFIG_PATA_MPIIX is not set
797# CONFIG_PATA_OLDPIIX is not set
798# CONFIG_PATA_NETCELL is not set
799# CONFIG_PATA_NS87410 is not set
800# CONFIG_PATA_NS87415 is not set
801# CONFIG_PATA_OPTI is not set
802# CONFIG_PATA_OPTIDMA is not set
803# CONFIG_PATA_PDC_OLD is not set
804# CONFIG_PATA_RADISYS is not set
805# CONFIG_PATA_RZ1000 is not set
806# CONFIG_PATA_SC1200 is not set
807# CONFIG_PATA_SERVERWORKS is not set
808# CONFIG_PATA_PDC2027X is not set
809# CONFIG_PATA_SIL680 is not set
810# CONFIG_PATA_SIS is not set
811# CONFIG_PATA_VIA is not set
812# CONFIG_PATA_WINBOND is not set
813# CONFIG_PATA_PLATFORM is not set
814CONFIG_PATA_IXP4XX_CF=y
669# CONFIG_MD is not set 815# CONFIG_MD is not set
670
671#
672# Fusion MPT device support
673#
674# CONFIG_FUSION is not set 816# CONFIG_FUSION is not set
675 817
676# 818#
677# IEEE 1394 (FireWire) support 819# IEEE 1394 (FireWire) support
678# 820#
821# CONFIG_FIREWIRE is not set
679# CONFIG_IEEE1394 is not set 822# CONFIG_IEEE1394 is not set
680
681#
682# I2O device support
683#
684# CONFIG_I2O is not set 823# CONFIG_I2O is not set
685
686#
687# Network device support
688#
689CONFIG_NETDEVICES=y 824CONFIG_NETDEVICES=y
825# CONFIG_NETDEVICES_MULTIQUEUE is not set
826# CONFIG_IFB is not set
690CONFIG_DUMMY=y 827CONFIG_DUMMY=y
691# CONFIG_BONDING is not set 828# CONFIG_BONDING is not set
829# CONFIG_MACVLAN is not set
692# CONFIG_EQUALIZER is not set 830# CONFIG_EQUALIZER is not set
693# CONFIG_TUN is not set 831# CONFIG_TUN is not set
694 832# CONFIG_VETH is not set
695#
696# ARCnet devices
697#
698# CONFIG_ARCNET is not set 833# CONFIG_ARCNET is not set
699
700#
701# PHY device support
702#
703# CONFIG_PHYLIB is not set 834# CONFIG_PHYLIB is not set
704
705#
706# Ethernet (10 or 100Mbit)
707#
708CONFIG_NET_ETHERNET=y 835CONFIG_NET_ETHERNET=y
709CONFIG_MII=y 836CONFIG_MII=y
837CONFIG_IXP4XX_ETH=y
838# CONFIG_AX88796 is not set
710# CONFIG_HAPPYMEAL is not set 839# CONFIG_HAPPYMEAL is not set
711# CONFIG_SUNGEM is not set 840# CONFIG_SUNGEM is not set
712# CONFIG_CASSINI is not set 841# CONFIG_CASSINI is not set
713# CONFIG_NET_VENDOR_3COM is not set 842# CONFIG_NET_VENDOR_3COM is not set
714# CONFIG_SMC91X is not set 843# CONFIG_SMC91X is not set
715# CONFIG_DM9000 is not set 844# CONFIG_DM9000 is not set
716
717#
718# Tulip family network device support
719#
720# CONFIG_NET_TULIP is not set 845# CONFIG_NET_TULIP is not set
721# CONFIG_HP100 is not set 846# CONFIG_HP100 is not set
847# CONFIG_IBM_NEW_EMAC_ZMII is not set
848# CONFIG_IBM_NEW_EMAC_RGMII is not set
849# CONFIG_IBM_NEW_EMAC_TAH is not set
850# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
722CONFIG_NET_PCI=y 851CONFIG_NET_PCI=y
723# CONFIG_PCNET32 is not set 852# CONFIG_PCNET32 is not set
724# CONFIG_AMD8111_ETH is not set 853# CONFIG_AMD8111_ETH is not set
725# CONFIG_ADAPTEC_STARFIRE is not set 854# CONFIG_ADAPTEC_STARFIRE is not set
726# CONFIG_B44 is not set 855# CONFIG_B44 is not set
727# CONFIG_FORCEDETH is not set 856# CONFIG_FORCEDETH is not set
728# CONFIG_DGRS is not set
729CONFIG_EEPRO100=y 857CONFIG_EEPRO100=y
730# CONFIG_E100 is not set 858# CONFIG_E100 is not set
731# CONFIG_FEALNX is not set 859# CONFIG_FEALNX is not set
@@ -738,93 +866,76 @@ CONFIG_EEPRO100=y
738# CONFIG_SUNDANCE is not set 866# CONFIG_SUNDANCE is not set
739# CONFIG_TLAN is not set 867# CONFIG_TLAN is not set
740# CONFIG_VIA_RHINE is not set 868# CONFIG_VIA_RHINE is not set
741 869# CONFIG_SC92031 is not set
742# 870CONFIG_NETDEV_1000=y
743# Ethernet (1000 Mbit)
744#
745# CONFIG_ACENIC is not set 871# CONFIG_ACENIC is not set
746# CONFIG_DL2K is not set 872# CONFIG_DL2K is not set
747# CONFIG_E1000 is not set 873# CONFIG_E1000 is not set
874# CONFIG_E1000E is not set
875# CONFIG_IP1000 is not set
748# CONFIG_NS83820 is not set 876# CONFIG_NS83820 is not set
749# CONFIG_HAMACHI is not set 877# CONFIG_HAMACHI is not set
750# CONFIG_YELLOWFIN is not set 878# CONFIG_YELLOWFIN is not set
751# CONFIG_R8169 is not set 879# CONFIG_R8169 is not set
752# CONFIG_SIS190 is not set 880# CONFIG_SIS190 is not set
753# CONFIG_SKGE is not set 881# CONFIG_SKGE is not set
882# CONFIG_SKY2 is not set
754# CONFIG_SK98LIN is not set 883# CONFIG_SK98LIN is not set
755# CONFIG_VIA_VELOCITY is not set 884# CONFIG_VIA_VELOCITY is not set
756# CONFIG_TIGON3 is not set 885# CONFIG_TIGON3 is not set
757# CONFIG_BNX2 is not set 886# CONFIG_BNX2 is not set
758 887# CONFIG_QLA3XXX is not set
759# 888# CONFIG_ATL1 is not set
760# Ethernet (10000 Mbit) 889CONFIG_NETDEV_10000=y
761#
762# CONFIG_CHELSIO_T1 is not set 890# CONFIG_CHELSIO_T1 is not set
891# CONFIG_CHELSIO_T3 is not set
892# CONFIG_IXGBE is not set
763# CONFIG_IXGB is not set 893# CONFIG_IXGB is not set
764# CONFIG_S2IO is not set 894# CONFIG_S2IO is not set
765 895# CONFIG_MYRI10GE is not set
766# 896# CONFIG_NETXEN_NIC is not set
767# Token Ring devices 897# CONFIG_NIU is not set
768# 898# CONFIG_MLX4_CORE is not set
899# CONFIG_TEHUTI is not set
769# CONFIG_TR is not set 900# CONFIG_TR is not set
770 901
771# 902#
772# Wireless LAN (non-hamradio) 903# Wireless LAN
773#
774CONFIG_NET_RADIO=y
775
776#
777# Obsolete Wireless cards support (pre-802.11)
778#
779# CONFIG_STRIP is not set
780
781#
782# Wireless 802.11b ISA/PCI cards support
783#
784# CONFIG_AIRO is not set
785CONFIG_HERMES=y
786# CONFIG_PLX_HERMES is not set
787# CONFIG_TMD_HERMES is not set
788# CONFIG_NORTEL_HERMES is not set
789CONFIG_PCI_HERMES=y
790# CONFIG_ATMEL is not set
791
792#
793# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support
794# 904#
795# CONFIG_PRISM54 is not set 905# CONFIG_WLAN_PRE80211 is not set
796# CONFIG_HOSTAP is not set 906# CONFIG_WLAN_80211 is not set
797CONFIG_NET_WIRELESS=y
798 907
799# 908#
800# Wan interfaces 909# USB Network Adapters
801# 910#
911# CONFIG_USB_CATC is not set
912# CONFIG_USB_KAWETH is not set
913# CONFIG_USB_PEGASUS is not set
914# CONFIG_USB_RTL8150 is not set
915# CONFIG_USB_USBNET is not set
802CONFIG_WAN=y 916CONFIG_WAN=y
803# CONFIG_DSCC4 is not set
804# CONFIG_LANMEDIA is not set 917# CONFIG_LANMEDIA is not set
805# CONFIG_SYNCLINK_SYNCPPP is not set
806CONFIG_HDLC=m 918CONFIG_HDLC=m
807CONFIG_HDLC_RAW=y 919CONFIG_HDLC_RAW=m
808# CONFIG_HDLC_RAW_ETH is not set 920# CONFIG_HDLC_RAW_ETH is not set
809CONFIG_HDLC_CISCO=y 921CONFIG_HDLC_CISCO=m
810CONFIG_HDLC_FR=y 922CONFIG_HDLC_FR=m
811CONFIG_HDLC_PPP=y 923CONFIG_HDLC_PPP=m
812CONFIG_HDLC_X25=y 924CONFIG_HDLC_X25=m
813# CONFIG_PCI200SYN is not set 925# CONFIG_PCI200SYN is not set
814# CONFIG_WANXL is not set 926# CONFIG_WANXL is not set
815# CONFIG_PC300 is not set 927# CONFIG_PC300 is not set
928# CONFIG_PC300TOO is not set
816# CONFIG_FARSYNC is not set 929# CONFIG_FARSYNC is not set
930# CONFIG_DSCC4 is not set
931# CONFIG_IXP4XX_HSS is not set
817CONFIG_DLCI=m 932CONFIG_DLCI=m
818CONFIG_DLCI_COUNT=24
819CONFIG_DLCI_MAX=8 933CONFIG_DLCI_MAX=8
820CONFIG_WAN_ROUTER_DRIVERS=y 934CONFIG_WAN_ROUTER_DRIVERS=m
821# CONFIG_CYCLADES_SYNC is not set 935# CONFIG_CYCLADES_SYNC is not set
822# CONFIG_LAPBETHER is not set 936# CONFIG_LAPBETHER is not set
823# CONFIG_X25_ASY is not set 937# CONFIG_X25_ASY is not set
824 938CONFIG_ATM_DRIVERS=y
825#
826# ATM drivers
827#
828# CONFIG_ATM_DUMMY is not set 939# CONFIG_ATM_DUMMY is not set
829CONFIG_ATM_TCP=m 940CONFIG_ATM_TCP=m
830# CONFIG_ATM_LANAI is not set 941# CONFIG_ATM_LANAI is not set
@@ -842,20 +953,19 @@ CONFIG_ATM_TCP=m
842# CONFIG_HIPPI is not set 953# CONFIG_HIPPI is not set
843# CONFIG_PPP is not set 954# CONFIG_PPP is not set
844# CONFIG_SLIP is not set 955# CONFIG_SLIP is not set
956# CONFIG_NET_FC is not set
845# CONFIG_SHAPER is not set 957# CONFIG_SHAPER is not set
846# CONFIG_NETCONSOLE is not set 958# CONFIG_NETCONSOLE is not set
847# CONFIG_NETPOLL is not set 959# CONFIG_NETPOLL is not set
848# CONFIG_NET_POLL_CONTROLLER is not set 960# CONFIG_NET_POLL_CONTROLLER is not set
849
850#
851# ISDN subsystem
852#
853# CONFIG_ISDN is not set 961# CONFIG_ISDN is not set
854 962
855# 963#
856# Input device support 964# Input device support
857# 965#
858CONFIG_INPUT=y 966CONFIG_INPUT=y
967# CONFIG_INPUT_FF_MEMLESS is not set
968# CONFIG_INPUT_POLLDEV is not set
859 969
860# 970#
861# Userland interfaces 971# Userland interfaces
@@ -865,7 +975,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
865CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 975CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
866CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 976CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
867# CONFIG_INPUT_JOYDEV is not set 977# CONFIG_INPUT_JOYDEV is not set
868# CONFIG_INPUT_TSDEV is not set
869# CONFIG_INPUT_EVDEV is not set 978# CONFIG_INPUT_EVDEV is not set
870# CONFIG_INPUT_EVBUG is not set 979# CONFIG_INPUT_EVBUG is not set
871 980
@@ -875,8 +984,16 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
875# CONFIG_INPUT_KEYBOARD is not set 984# CONFIG_INPUT_KEYBOARD is not set
876# CONFIG_INPUT_MOUSE is not set 985# CONFIG_INPUT_MOUSE is not set
877# CONFIG_INPUT_JOYSTICK is not set 986# CONFIG_INPUT_JOYSTICK is not set
987# CONFIG_INPUT_TABLET is not set
878# CONFIG_INPUT_TOUCHSCREEN is not set 988# CONFIG_INPUT_TOUCHSCREEN is not set
879# CONFIG_INPUT_MISC is not set 989CONFIG_INPUT_MISC=y
990CONFIG_INPUT_IXP4XX_BEEPER=y
991# CONFIG_INPUT_ATI_REMOTE is not set
992# CONFIG_INPUT_ATI_REMOTE2 is not set
993# CONFIG_INPUT_KEYSPAN_REMOTE is not set
994# CONFIG_INPUT_POWERMATE is not set
995# CONFIG_INPUT_YEALINK is not set
996# CONFIG_INPUT_UINPUT is not set
880 997
881# 998#
882# Hardware I/O ports 999# Hardware I/O ports
@@ -895,7 +1012,9 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
895# 1012#
896CONFIG_SERIAL_8250=y 1013CONFIG_SERIAL_8250=y
897CONFIG_SERIAL_8250_CONSOLE=y 1014CONFIG_SERIAL_8250_CONSOLE=y
1015CONFIG_SERIAL_8250_PCI=y
898CONFIG_SERIAL_8250_NR_UARTS=2 1016CONFIG_SERIAL_8250_NR_UARTS=2
1017CONFIG_SERIAL_8250_RUNTIME_UARTS=2
899# CONFIG_SERIAL_8250_EXTENDED is not set 1018# CONFIG_SERIAL_8250_EXTENDED is not set
900 1019
901# 1020#
@@ -907,51 +1026,17 @@ CONFIG_SERIAL_CORE_CONSOLE=y
907CONFIG_UNIX98_PTYS=y 1026CONFIG_UNIX98_PTYS=y
908CONFIG_LEGACY_PTYS=y 1027CONFIG_LEGACY_PTYS=y
909CONFIG_LEGACY_PTY_COUNT=256 1028CONFIG_LEGACY_PTY_COUNT=256
910
911#
912# IPMI
913#
914# CONFIG_IPMI_HANDLER is not set 1029# CONFIG_IPMI_HANDLER is not set
915 1030CONFIG_HW_RANDOM=m
916# 1031CONFIG_HW_RANDOM_IXP4XX=m
917# Watchdog Cards
918#
919CONFIG_WATCHDOG=y
920# CONFIG_WATCHDOG_NOWAYOUT is not set
921
922#
923# Watchdog Device Drivers
924#
925# CONFIG_SOFT_WATCHDOG is not set
926CONFIG_IXP4XX_WATCHDOG=y
927
928#
929# PCI-based Watchdog Cards
930#
931# CONFIG_PCIPCWATCHDOG is not set
932# CONFIG_WDTPCI is not set
933# CONFIG_NVRAM is not set 1032# CONFIG_NVRAM is not set
934# CONFIG_RTC is not set
935# CONFIG_DTLK is not set
936# CONFIG_R3964 is not set 1033# CONFIG_R3964 is not set
937# CONFIG_APPLICOM is not set 1034# CONFIG_APPLICOM is not set
938
939#
940# Ftape, the floppy tape device driver
941#
942# CONFIG_DRM is not set
943# CONFIG_RAW_DRIVER is not set 1035# CONFIG_RAW_DRIVER is not set
944
945#
946# TPM devices
947#
948# CONFIG_TCG_TPM is not set 1036# CONFIG_TCG_TPM is not set
949# CONFIG_TELCLOCK is not set 1037CONFIG_DEVPORT=y
950
951#
952# I2C support
953#
954CONFIG_I2C=y 1038CONFIG_I2C=y
1039CONFIG_I2C_BOARDINFO=y
955CONFIG_I2C_CHARDEV=y 1040CONFIG_I2C_CHARDEV=y
956 1041
957# 1042#
@@ -969,57 +1054,68 @@ CONFIG_I2C_ALGOBIT=y
969# CONFIG_I2C_ALI15X3 is not set 1054# CONFIG_I2C_ALI15X3 is not set
970# CONFIG_I2C_AMD756 is not set 1055# CONFIG_I2C_AMD756 is not set
971# CONFIG_I2C_AMD8111 is not set 1056# CONFIG_I2C_AMD8111 is not set
1057# CONFIG_I2C_GPIO is not set
972# CONFIG_I2C_I801 is not set 1058# CONFIG_I2C_I801 is not set
973# CONFIG_I2C_I810 is not set 1059# CONFIG_I2C_I810 is not set
974# CONFIG_I2C_PIIX4 is not set 1060# CONFIG_I2C_PIIX4 is not set
975# CONFIG_I2C_IOP3XX is not set 1061# CONFIG_I2C_IOP3XX is not set
976CONFIG_I2C_IXP4XX=y 1062CONFIG_I2C_IXP4XX=y
977# CONFIG_I2C_NFORCE2 is not set 1063# CONFIG_I2C_NFORCE2 is not set
1064# CONFIG_I2C_OCORES is not set
978# CONFIG_I2C_PARPORT_LIGHT is not set 1065# CONFIG_I2C_PARPORT_LIGHT is not set
979# CONFIG_I2C_PROSAVAGE is not set 1066# CONFIG_I2C_PROSAVAGE is not set
980# CONFIG_I2C_SAVAGE4 is not set 1067# CONFIG_I2C_SAVAGE4 is not set
981# CONFIG_SCx200_ACB is not set 1068# CONFIG_I2C_SIMTEC is not set
982# CONFIG_I2C_SIS5595 is not set 1069# CONFIG_I2C_SIS5595 is not set
983# CONFIG_I2C_SIS630 is not set 1070# CONFIG_I2C_SIS630 is not set
984# CONFIG_I2C_SIS96X is not set 1071# CONFIG_I2C_SIS96X is not set
1072# CONFIG_I2C_TAOS_EVM is not set
985# CONFIG_I2C_STUB is not set 1073# CONFIG_I2C_STUB is not set
1074# CONFIG_I2C_TINY_USB is not set
986# CONFIG_I2C_VIA is not set 1075# CONFIG_I2C_VIA is not set
987# CONFIG_I2C_VIAPRO is not set 1076# CONFIG_I2C_VIAPRO is not set
988# CONFIG_I2C_VOODOO3 is not set 1077# CONFIG_I2C_VOODOO3 is not set
989# CONFIG_I2C_PCA_ISA is not set
990 1078
991# 1079#
992# Miscellaneous I2C Chip support 1080# Miscellaneous I2C Chip support
993# 1081#
994# CONFIG_SENSORS_DS1337 is not set 1082# CONFIG_SENSORS_DS1337 is not set
995# CONFIG_SENSORS_DS1374 is not set 1083# CONFIG_SENSORS_DS1374 is not set
1084# CONFIG_DS1682 is not set
996CONFIG_SENSORS_EEPROM=y 1085CONFIG_SENSORS_EEPROM=y
997# CONFIG_SENSORS_PCF8574 is not set 1086# CONFIG_SENSORS_PCF8574 is not set
998# CONFIG_SENSORS_PCA9539 is not set 1087# CONFIG_SENSORS_PCA9539 is not set
999# CONFIG_SENSORS_PCF8591 is not set 1088# CONFIG_SENSORS_PCF8591 is not set
1000# CONFIG_SENSORS_RTC8564 is not set
1001# CONFIG_SENSORS_MAX6875 is not set 1089# CONFIG_SENSORS_MAX6875 is not set
1002# CONFIG_RTC_X1205_I2C is not set 1090# CONFIG_SENSORS_TSL2550 is not set
1003# CONFIG_I2C_DEBUG_CORE is not set 1091# CONFIG_I2C_DEBUG_CORE is not set
1004# CONFIG_I2C_DEBUG_ALGO is not set 1092# CONFIG_I2C_DEBUG_ALGO is not set
1005# CONFIG_I2C_DEBUG_BUS is not set 1093# CONFIG_I2C_DEBUG_BUS is not set
1006# CONFIG_I2C_DEBUG_CHIP is not set 1094# CONFIG_I2C_DEBUG_CHIP is not set
1007 1095
1008# 1096#
1009# Hardware Monitoring support 1097# SPI support
1010# 1098#
1099# CONFIG_SPI is not set
1100# CONFIG_SPI_MASTER is not set
1101# CONFIG_W1 is not set
1102# CONFIG_POWER_SUPPLY is not set
1011CONFIG_HWMON=y 1103CONFIG_HWMON=y
1012# CONFIG_HWMON_VID is not set 1104# CONFIG_HWMON_VID is not set
1105# CONFIG_SENSORS_AD7418 is not set
1013# CONFIG_SENSORS_ADM1021 is not set 1106# CONFIG_SENSORS_ADM1021 is not set
1014# CONFIG_SENSORS_ADM1025 is not set 1107# CONFIG_SENSORS_ADM1025 is not set
1015# CONFIG_SENSORS_ADM1026 is not set 1108# CONFIG_SENSORS_ADM1026 is not set
1109# CONFIG_SENSORS_ADM1029 is not set
1016# CONFIG_SENSORS_ADM1031 is not set 1110# CONFIG_SENSORS_ADM1031 is not set
1017# CONFIG_SENSORS_ADM9240 is not set 1111# CONFIG_SENSORS_ADM9240 is not set
1018# CONFIG_SENSORS_ASB100 is not set 1112# CONFIG_SENSORS_ADT7470 is not set
1019# CONFIG_SENSORS_ATXP1 is not set 1113# CONFIG_SENSORS_ATXP1 is not set
1020# CONFIG_SENSORS_DS1621 is not set 1114# CONFIG_SENSORS_DS1621 is not set
1021# CONFIG_SENSORS_FSCHER is not set 1115# CONFIG_SENSORS_I5K_AMB is not set
1022# CONFIG_SENSORS_FSCPOS is not set 1116# CONFIG_SENSORS_F71805F is not set
1117# CONFIG_SENSORS_F71882FG is not set
1118# CONFIG_SENSORS_F75375S is not set
1023# CONFIG_SENSORS_GL518SM is not set 1119# CONFIG_SENSORS_GL518SM is not set
1024# CONFIG_SENSORS_GL520SM is not set 1120# CONFIG_SENSORS_GL520SM is not set
1025# CONFIG_SENSORS_IT87 is not set 1121# CONFIG_SENSORS_IT87 is not set
@@ -1033,67 +1129,268 @@ CONFIG_HWMON=y
1033# CONFIG_SENSORS_LM87 is not set 1129# CONFIG_SENSORS_LM87 is not set
1034# CONFIG_SENSORS_LM90 is not set 1130# CONFIG_SENSORS_LM90 is not set
1035# CONFIG_SENSORS_LM92 is not set 1131# CONFIG_SENSORS_LM92 is not set
1132# CONFIG_SENSORS_LM93 is not set
1036# CONFIG_SENSORS_MAX1619 is not set 1133# CONFIG_SENSORS_MAX1619 is not set
1134# CONFIG_SENSORS_MAX6650 is not set
1037# CONFIG_SENSORS_PC87360 is not set 1135# CONFIG_SENSORS_PC87360 is not set
1136# CONFIG_SENSORS_PC87427 is not set
1038# CONFIG_SENSORS_SIS5595 is not set 1137# CONFIG_SENSORS_SIS5595 is not set
1138# CONFIG_SENSORS_DME1737 is not set
1039# CONFIG_SENSORS_SMSC47M1 is not set 1139# CONFIG_SENSORS_SMSC47M1 is not set
1140# CONFIG_SENSORS_SMSC47M192 is not set
1040# CONFIG_SENSORS_SMSC47B397 is not set 1141# CONFIG_SENSORS_SMSC47B397 is not set
1142# CONFIG_SENSORS_THMC50 is not set
1041# CONFIG_SENSORS_VIA686A is not set 1143# CONFIG_SENSORS_VIA686A is not set
1144# CONFIG_SENSORS_VT1211 is not set
1145# CONFIG_SENSORS_VT8231 is not set
1042# CONFIG_SENSORS_W83781D is not set 1146# CONFIG_SENSORS_W83781D is not set
1147# CONFIG_SENSORS_W83791D is not set
1043# CONFIG_SENSORS_W83792D is not set 1148# CONFIG_SENSORS_W83792D is not set
1149# CONFIG_SENSORS_W83793 is not set
1044# CONFIG_SENSORS_W83L785TS is not set 1150# CONFIG_SENSORS_W83L785TS is not set
1045# CONFIG_SENSORS_W83627HF is not set 1151# CONFIG_SENSORS_W83627HF is not set
1046# CONFIG_SENSORS_W83627EHF is not set 1152# CONFIG_SENSORS_W83627EHF is not set
1047# CONFIG_HWMON_DEBUG_CHIP is not set 1153# CONFIG_HWMON_DEBUG_CHIP is not set
1154CONFIG_WATCHDOG=y
1155# CONFIG_WATCHDOG_NOWAYOUT is not set
1048 1156
1049# 1157#
1050# Misc devices 1158# Watchdog Device Drivers
1051# 1159#
1160# CONFIG_SOFT_WATCHDOG is not set
1161CONFIG_IXP4XX_WATCHDOG=y
1052 1162
1053# 1163#
1054# Multimedia Capabilities Port drivers 1164# PCI-based Watchdog Cards
1055# 1165#
1166# CONFIG_PCIPCWATCHDOG is not set
1167# CONFIG_WDTPCI is not set
1056 1168
1057# 1169#
1058# Multimedia devices 1170# USB-based Watchdog Cards
1059# 1171#
1060# CONFIG_VIDEO_DEV is not set 1172# CONFIG_USBPCWATCHDOG is not set
1061 1173
1062# 1174#
1063# Digital Video Broadcasting Devices 1175# Sonics Silicon Backplane
1064# 1176#
1065# CONFIG_DVB is not set 1177CONFIG_SSB_POSSIBLE=y
1178# CONFIG_SSB is not set
1179
1180#
1181# Multifunction device drivers
1182#
1183# CONFIG_MFD_SM501 is not set
1184
1185#
1186# Multimedia devices
1187#
1188# CONFIG_VIDEO_DEV is not set
1189# CONFIG_DVB_CORE is not set
1190CONFIG_DAB=y
1191# CONFIG_USB_DABUSB is not set
1066 1192
1067# 1193#
1068# Graphics support 1194# Graphics support
1069# 1195#
1196# CONFIG_DRM is not set
1197# CONFIG_VGASTATE is not set
1198# CONFIG_VIDEO_OUTPUT_CONTROL is not set
1070# CONFIG_FB is not set 1199# CONFIG_FB is not set
1200# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1201
1202#
1203# Display device support
1204#
1205# CONFIG_DISPLAY_SUPPORT is not set
1071 1206
1072# 1207#
1073# Sound 1208# Sound
1074# 1209#
1075# CONFIG_SOUND is not set 1210# CONFIG_SOUND is not set
1211CONFIG_HID_SUPPORT=y
1212CONFIG_HID=y
1213# CONFIG_HID_DEBUG is not set
1214# CONFIG_HIDRAW is not set
1076 1215
1077# 1216#
1078# USB support 1217# USB Input Devices
1079# 1218#
1219CONFIG_USB_HID=y
1220# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1221# CONFIG_HID_FF is not set
1222# CONFIG_USB_HIDDEV is not set
1223CONFIG_USB_SUPPORT=y
1080CONFIG_USB_ARCH_HAS_HCD=y 1224CONFIG_USB_ARCH_HAS_HCD=y
1081CONFIG_USB_ARCH_HAS_OHCI=y 1225CONFIG_USB_ARCH_HAS_OHCI=y
1082# CONFIG_USB is not set 1226CONFIG_USB_ARCH_HAS_EHCI=y
1227CONFIG_USB=y
1228# CONFIG_USB_DEBUG is not set
1229
1230#
1231# Miscellaneous USB options
1232#
1233CONFIG_USB_DEVICEFS=y
1234# CONFIG_USB_DEVICE_CLASS is not set
1235# CONFIG_USB_DYNAMIC_MINORS is not set
1236# CONFIG_USB_OTG is not set
1237
1238#
1239# USB Host Controller Drivers
1240#
1241CONFIG_USB_EHCI_HCD=y
1242# CONFIG_USB_EHCI_SPLIT_ISO is not set
1243# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
1244# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1245# CONFIG_USB_ISP116X_HCD is not set
1246CONFIG_USB_OHCI_HCD=y
1247# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1248# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1249CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1250CONFIG_USB_UHCI_HCD=y
1251# CONFIG_USB_SL811_HCD is not set
1252# CONFIG_USB_R8A66597_HCD is not set
1253
1254#
1255# USB Device Class drivers
1256#
1257# CONFIG_USB_ACM is not set
1258# CONFIG_USB_PRINTER is not set
1083 1259
1084# 1260#
1085# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1261# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1086# 1262#
1087 1263
1088# 1264#
1265# may also be needed; see USB_STORAGE Help for more information
1266#
1267CONFIG_USB_STORAGE=y
1268# CONFIG_USB_STORAGE_DEBUG is not set
1269# CONFIG_USB_STORAGE_DATAFAB is not set
1270# CONFIG_USB_STORAGE_FREECOM is not set
1271# CONFIG_USB_STORAGE_ISD200 is not set
1272# CONFIG_USB_STORAGE_DPCM is not set
1273# CONFIG_USB_STORAGE_USBAT is not set
1274# CONFIG_USB_STORAGE_SDDR09 is not set
1275# CONFIG_USB_STORAGE_SDDR55 is not set
1276# CONFIG_USB_STORAGE_JUMPSHOT is not set
1277# CONFIG_USB_STORAGE_ALAUDA is not set
1278# CONFIG_USB_STORAGE_KARMA is not set
1279# CONFIG_USB_LIBUSUAL is not set
1280
1281#
1282# USB Imaging devices
1283#
1284# CONFIG_USB_MDC800 is not set
1285# CONFIG_USB_MICROTEK is not set
1286# CONFIG_USB_MON is not set
1287
1288#
1289# USB port drivers
1290#
1291
1292#
1293# USB Serial Converter support
1294#
1295# CONFIG_USB_SERIAL is not set
1296
1297#
1298# USB Miscellaneous drivers
1299#
1300# CONFIG_USB_EMI62 is not set
1301# CONFIG_USB_EMI26 is not set
1302# CONFIG_USB_ADUTUX is not set
1303# CONFIG_USB_AUERSWALD is not set
1304# CONFIG_USB_RIO500 is not set
1305# CONFIG_USB_LEGOTOWER is not set
1306# CONFIG_USB_LCD is not set
1307# CONFIG_USB_BERRY_CHARGE is not set
1308# CONFIG_USB_LED is not set
1309# CONFIG_USB_CYPRESS_CY7C63 is not set
1310# CONFIG_USB_CYTHERM is not set
1311# CONFIG_USB_PHIDGET is not set
1312# CONFIG_USB_IDMOUSE is not set
1313# CONFIG_USB_FTDI_ELAN is not set
1314# CONFIG_USB_APPLEDISPLAY is not set
1315# CONFIG_USB_SISUSBVGA is not set
1316# CONFIG_USB_LD is not set
1317# CONFIG_USB_TRANCEVIBRATOR is not set
1318# CONFIG_USB_IOWARRIOR is not set
1319# CONFIG_USB_TEST is not set
1320
1321#
1322# USB DSL modem support
1323#
1324# CONFIG_USB_ATM is not set
1325
1326#
1089# USB Gadget Support 1327# USB Gadget Support
1090# 1328#
1091# CONFIG_USB_GADGET is not set 1329# CONFIG_USB_GADGET is not set
1330# CONFIG_MMC is not set
1331CONFIG_NEW_LEDS=y
1332CONFIG_LEDS_CLASS=y
1092 1333
1093# 1334#
1094# MMC/SD Card support 1335# LED drivers
1336#
1337# CONFIG_LEDS_IXP4XX is not set
1338CONFIG_LEDS_GPIO=y
1339
1340#
1341# LED Triggers
1342#
1343CONFIG_LEDS_TRIGGERS=y
1344CONFIG_LEDS_TRIGGER_TIMER=y
1345CONFIG_LEDS_TRIGGER_IDE_DISK=y
1346CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1347CONFIG_RTC_LIB=y
1348CONFIG_RTC_CLASS=y
1349CONFIG_RTC_HCTOSYS=y
1350CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1351# CONFIG_RTC_DEBUG is not set
1352
1353#
1354# RTC interfaces
1355#
1356CONFIG_RTC_INTF_SYSFS=y
1357CONFIG_RTC_INTF_PROC=y
1358CONFIG_RTC_INTF_DEV=y
1359# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1360# CONFIG_RTC_DRV_TEST is not set
1361
1362#
1363# I2C RTC drivers
1364#
1365# CONFIG_RTC_DRV_DS1307 is not set
1366# CONFIG_RTC_DRV_DS1374 is not set
1367# CONFIG_RTC_DRV_DS1672 is not set
1368# CONFIG_RTC_DRV_MAX6900 is not set
1369# CONFIG_RTC_DRV_RS5C372 is not set
1370# CONFIG_RTC_DRV_ISL1208 is not set
1371CONFIG_RTC_DRV_X1205=y
1372CONFIG_RTC_DRV_PCF8563=y
1373# CONFIG_RTC_DRV_PCF8583 is not set
1374# CONFIG_RTC_DRV_M41T80 is not set
1375
1376#
1377# SPI RTC drivers
1378#
1379
1380#
1381# Platform RTC drivers
1382#
1383# CONFIG_RTC_DRV_CMOS is not set
1384# CONFIG_RTC_DRV_DS1553 is not set
1385# CONFIG_RTC_DRV_STK17TA8 is not set
1386# CONFIG_RTC_DRV_DS1742 is not set
1387# CONFIG_RTC_DRV_M48T86 is not set
1388# CONFIG_RTC_DRV_M48T59 is not set
1389# CONFIG_RTC_DRV_V3020 is not set
1390
1391#
1392# on-CPU RTC drivers
1095# 1393#
1096# CONFIG_MMC is not set
1097 1394
1098# 1395#
1099# File systems 1396# File systems
@@ -1107,16 +1404,19 @@ CONFIG_EXT3_FS=y
1107CONFIG_EXT3_FS_XATTR=y 1404CONFIG_EXT3_FS_XATTR=y
1108CONFIG_EXT3_FS_POSIX_ACL=y 1405CONFIG_EXT3_FS_POSIX_ACL=y
1109# CONFIG_EXT3_FS_SECURITY is not set 1406# CONFIG_EXT3_FS_SECURITY is not set
1407# CONFIG_EXT4DEV_FS is not set
1110CONFIG_JBD=y 1408CONFIG_JBD=y
1111# CONFIG_JBD_DEBUG is not set
1112CONFIG_FS_MBCACHE=y 1409CONFIG_FS_MBCACHE=y
1113# CONFIG_REISERFS_FS is not set 1410# CONFIG_REISERFS_FS is not set
1114# CONFIG_JFS_FS is not set 1411# CONFIG_JFS_FS is not set
1115CONFIG_FS_POSIX_ACL=y 1412CONFIG_FS_POSIX_ACL=y
1116# CONFIG_XFS_FS is not set 1413# CONFIG_XFS_FS is not set
1414# CONFIG_GFS2_FS is not set
1415# CONFIG_OCFS2_FS is not set
1117# CONFIG_MINIX_FS is not set 1416# CONFIG_MINIX_FS is not set
1118# CONFIG_ROMFS_FS is not set 1417# CONFIG_ROMFS_FS is not set
1119CONFIG_INOTIFY=y 1418CONFIG_INOTIFY=y
1419CONFIG_INOTIFY_USER=y
1120# CONFIG_QUOTA is not set 1420# CONFIG_QUOTA is not set
1121CONFIG_DNOTIFY=y 1421CONFIG_DNOTIFY=y
1122# CONFIG_AUTOFS_FS is not set 1422# CONFIG_AUTOFS_FS is not set
@@ -1140,11 +1440,12 @@ CONFIG_DNOTIFY=y
1140# Pseudo filesystems 1440# Pseudo filesystems
1141# 1441#
1142CONFIG_PROC_FS=y 1442CONFIG_PROC_FS=y
1443CONFIG_PROC_SYSCTL=y
1143CONFIG_SYSFS=y 1444CONFIG_SYSFS=y
1144CONFIG_TMPFS=y 1445CONFIG_TMPFS=y
1446# CONFIG_TMPFS_POSIX_ACL is not set
1145# CONFIG_HUGETLB_PAGE is not set 1447# CONFIG_HUGETLB_PAGE is not set
1146CONFIG_RAMFS=y 1448# CONFIG_CONFIGFS_FS is not set
1147# CONFIG_RELAYFS_FS is not set
1148 1449
1149# 1450#
1150# Miscellaneous filesystems 1451# Miscellaneous filesystems
@@ -1156,13 +1457,15 @@ CONFIG_RAMFS=y
1156# CONFIG_BEFS_FS is not set 1457# CONFIG_BEFS_FS is not set
1157# CONFIG_BFS_FS is not set 1458# CONFIG_BFS_FS is not set
1158# CONFIG_EFS_FS is not set 1459# CONFIG_EFS_FS is not set
1159# CONFIG_JFFS_FS is not set
1160CONFIG_JFFS2_FS=y 1460CONFIG_JFFS2_FS=y
1161CONFIG_JFFS2_FS_DEBUG=0 1461CONFIG_JFFS2_FS_DEBUG=0
1162CONFIG_JFFS2_FS_WRITEBUFFER=y 1462CONFIG_JFFS2_FS_WRITEBUFFER=y
1463# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1163# CONFIG_JFFS2_SUMMARY is not set 1464# CONFIG_JFFS2_SUMMARY is not set
1465# CONFIG_JFFS2_FS_XATTR is not set
1164# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set 1466# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1165CONFIG_JFFS2_ZLIB=y 1467CONFIG_JFFS2_ZLIB=y
1468# CONFIG_JFFS2_LZO is not set
1166CONFIG_JFFS2_RTIME=y 1469CONFIG_JFFS2_RTIME=y
1167# CONFIG_JFFS2_RUBIN is not set 1470# CONFIG_JFFS2_RUBIN is not set
1168# CONFIG_CRAMFS is not set 1471# CONFIG_CRAMFS is not set
@@ -1171,10 +1474,7 @@ CONFIG_JFFS2_RTIME=y
1171# CONFIG_QNX4FS_FS is not set 1474# CONFIG_QNX4FS_FS is not set
1172# CONFIG_SYSV_FS is not set 1475# CONFIG_SYSV_FS is not set
1173# CONFIG_UFS_FS is not set 1476# CONFIG_UFS_FS is not set
1174 1477CONFIG_NETWORK_FILESYSTEMS=y
1175#
1176# Network File Systems
1177#
1178CONFIG_NFS_FS=y 1478CONFIG_NFS_FS=y
1179CONFIG_NFS_V3=y 1479CONFIG_NFS_V3=y
1180# CONFIG_NFS_V3_ACL is not set 1480# CONFIG_NFS_V3_ACL is not set
@@ -1186,6 +1486,7 @@ CONFIG_LOCKD=y
1186CONFIG_LOCKD_V4=y 1486CONFIG_LOCKD_V4=y
1187CONFIG_NFS_COMMON=y 1487CONFIG_NFS_COMMON=y
1188CONFIG_SUNRPC=y 1488CONFIG_SUNRPC=y
1489# CONFIG_SUNRPC_BIND34 is not set
1189# CONFIG_RPCSEC_GSS_KRB5 is not set 1490# CONFIG_RPCSEC_GSS_KRB5 is not set
1190# CONFIG_RPCSEC_GSS_SPKM3 is not set 1491# CONFIG_RPCSEC_GSS_SPKM3 is not set
1191# CONFIG_SMB_FS is not set 1492# CONFIG_SMB_FS is not set
@@ -1193,7 +1494,6 @@ CONFIG_SUNRPC=y
1193# CONFIG_NCP_FS is not set 1494# CONFIG_NCP_FS is not set
1194# CONFIG_CODA_FS is not set 1495# CONFIG_CODA_FS is not set
1195# CONFIG_AFS_FS is not set 1496# CONFIG_AFS_FS is not set
1196# CONFIG_9P_FS is not set
1197 1497
1198# 1498#
1199# Partition Types 1499# Partition Types
@@ -1213,37 +1513,53 @@ CONFIG_MSDOS_PARTITION=y
1213# CONFIG_SGI_PARTITION is not set 1513# CONFIG_SGI_PARTITION is not set
1214# CONFIG_ULTRIX_PARTITION is not set 1514# CONFIG_ULTRIX_PARTITION is not set
1215# CONFIG_SUN_PARTITION is not set 1515# CONFIG_SUN_PARTITION is not set
1516# CONFIG_KARMA_PARTITION is not set
1216# CONFIG_EFI_PARTITION is not set 1517# CONFIG_EFI_PARTITION is not set
1217 1518# CONFIG_SYSV68_PARTITION is not set
1218#
1219# Native Language Support
1220#
1221# CONFIG_NLS is not set 1519# CONFIG_NLS is not set
1222 1520# CONFIG_DLM is not set
1223# 1521CONFIG_INSTRUMENTATION=y
1224# Profiling support
1225#
1226# CONFIG_PROFILING is not set 1522# CONFIG_PROFILING is not set
1523# CONFIG_MARKERS is not set
1227 1524
1228# 1525#
1229# Kernel hacking 1526# Kernel hacking
1230# 1527#
1231# CONFIG_PRINTK_TIME is not set 1528# CONFIG_PRINTK_TIME is not set
1232CONFIG_DEBUG_KERNEL=y 1529CONFIG_ENABLE_WARN_DEPRECATED=y
1530CONFIG_ENABLE_MUST_CHECK=y
1233CONFIG_MAGIC_SYSRQ=y 1531CONFIG_MAGIC_SYSRQ=y
1234CONFIG_LOG_BUF_SHIFT=14 1532# CONFIG_UNUSED_SYMBOLS is not set
1533# CONFIG_DEBUG_FS is not set
1534# CONFIG_HEADERS_CHECK is not set
1535CONFIG_DEBUG_KERNEL=y
1536# CONFIG_DEBUG_SHIRQ is not set
1235CONFIG_DETECT_SOFTLOCKUP=y 1537CONFIG_DETECT_SOFTLOCKUP=y
1538CONFIG_SCHED_DEBUG=y
1236# CONFIG_SCHEDSTATS is not set 1539# CONFIG_SCHEDSTATS is not set
1237# CONFIG_DEBUG_SLAB is not set 1540# CONFIG_TIMER_STATS is not set
1541# CONFIG_SLUB_DEBUG_ON is not set
1542# CONFIG_DEBUG_RT_MUTEXES is not set
1543# CONFIG_RT_MUTEX_TESTER is not set
1238# CONFIG_DEBUG_SPINLOCK is not set 1544# CONFIG_DEBUG_SPINLOCK is not set
1545# CONFIG_DEBUG_MUTEXES is not set
1546# CONFIG_DEBUG_LOCK_ALLOC is not set
1547# CONFIG_PROVE_LOCKING is not set
1548# CONFIG_LOCK_STAT is not set
1239# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1549# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1550# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1240# CONFIG_DEBUG_KOBJECT is not set 1551# CONFIG_DEBUG_KOBJECT is not set
1241CONFIG_DEBUG_BUGVERBOSE=y 1552CONFIG_DEBUG_BUGVERBOSE=y
1242# CONFIG_DEBUG_INFO is not set 1553# CONFIG_DEBUG_INFO is not set
1243# CONFIG_DEBUG_FS is not set
1244# CONFIG_DEBUG_VM is not set 1554# CONFIG_DEBUG_VM is not set
1555# CONFIG_DEBUG_LIST is not set
1556# CONFIG_DEBUG_SG is not set
1245CONFIG_FRAME_POINTER=y 1557CONFIG_FRAME_POINTER=y
1558CONFIG_FORCED_INLINING=y
1559# CONFIG_BOOT_PRINTK_DELAY is not set
1246# CONFIG_RCU_TORTURE_TEST is not set 1560# CONFIG_RCU_TORTURE_TEST is not set
1561# CONFIG_FAULT_INJECTION is not set
1562# CONFIG_SAMPLES is not set
1247# CONFIG_DEBUG_USER is not set 1563# CONFIG_DEBUG_USER is not set
1248CONFIG_DEBUG_ERRORS=y 1564CONFIG_DEBUG_ERRORS=y
1249CONFIG_DEBUG_LL=y 1565CONFIG_DEBUG_LL=y
@@ -1254,22 +1570,22 @@ CONFIG_DEBUG_LL=y
1254# 1570#
1255# CONFIG_KEYS is not set 1571# CONFIG_KEYS is not set
1256# CONFIG_SECURITY is not set 1572# CONFIG_SECURITY is not set
1257 1573# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1258#
1259# Cryptographic options
1260#
1261# CONFIG_CRYPTO is not set 1574# CONFIG_CRYPTO is not set
1262 1575
1263# 1576#
1264# Hardware crypto devices
1265#
1266
1267#
1268# Library routines 1577# Library routines
1269# 1578#
1579CONFIG_BITREVERSE=y
1270# CONFIG_CRC_CCITT is not set 1580# CONFIG_CRC_CCITT is not set
1271# CONFIG_CRC16 is not set 1581# CONFIG_CRC16 is not set
1582# CONFIG_CRC_ITU_T is not set
1272CONFIG_CRC32=y 1583CONFIG_CRC32=y
1584# CONFIG_CRC7 is not set
1273# CONFIG_LIBCRC32C is not set 1585# CONFIG_LIBCRC32C is not set
1274CONFIG_ZLIB_INFLATE=y 1586CONFIG_ZLIB_INFLATE=y
1275CONFIG_ZLIB_DEFLATE=y 1587CONFIG_ZLIB_DEFLATE=y
1588CONFIG_PLIST=y
1589CONFIG_HAS_IOMEM=y
1590CONFIG_HAS_IOPORT=y
1591CONFIG_HAS_DMA=y
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index ae3712d39ab7..d3941a7b0455 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -62,6 +62,7 @@ extern int root_mountflags;
62extern void _stext, _text, _etext, __data_start, _edata, _end; 62extern void _stext, _text, _etext, __data_start, _edata, _end;
63 63
64unsigned int processor_id; 64unsigned int processor_id;
65EXPORT_SYMBOL(processor_id);
65unsigned int __machine_arch_type; 66unsigned int __machine_arch_type;
66EXPORT_SYMBOL(__machine_arch_type); 67EXPORT_SYMBOL(__machine_arch_type);
67 68
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index eafbb2b05eb8..e9dfbab46cb6 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -290,6 +290,11 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
290 local_irq_enable(); 290 local_irq_enable();
291 local_fiq_enable(); 291 local_fiq_enable();
292 292
293 /*
294 * Setup local timer for this CPU.
295 */
296 local_timer_setup(cpu);
297
293 calibrate_delay(); 298 calibrate_delay();
294 299
295 smp_store_cpu_info(cpu); 300 smp_store_cpu_info(cpu);
@@ -300,11 +305,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
300 cpu_set(cpu, cpu_online_map); 305 cpu_set(cpu, cpu_online_map);
301 306
302 /* 307 /*
303 * Setup local timer for this CPU.
304 */
305 local_timer_setup(cpu);
306
307 /*
308 * OK, it's off to the idle thread for us 308 * OK, it's off to the idle thread for us
309 */ 309 */
310 cpu_idle(); 310 cpu_idle();
@@ -454,6 +454,27 @@ int smp_call_function(void (*func)(void *info), void *info, int retry,
454} 454}
455EXPORT_SYMBOL_GPL(smp_call_function); 455EXPORT_SYMBOL_GPL(smp_call_function);
456 456
457int smp_call_function_single(int cpu, void (*func)(void *info), void *info,
458 int retry, int wait)
459{
460 /* prevent preemption and reschedule on another processor */
461 int current_cpu = get_cpu();
462 int ret = 0;
463
464 if (cpu == current_cpu) {
465 local_irq_disable();
466 func(info);
467 local_irq_enable();
468 } else
469 ret = smp_call_function_on_cpu(func, info, retry, wait,
470 cpumask_of_cpu(cpu));
471
472 put_cpu();
473
474 return ret;
475}
476EXPORT_SYMBOL_GPL(smp_call_function_single);
477
457void show_ipi_list(struct seq_file *p) 478void show_ipi_list(struct seq_file *p)
458{ 479{
459 unsigned int cpu; 480 unsigned int cpu;
@@ -481,8 +502,7 @@ void show_local_irqs(struct seq_file *p)
481static void ipi_timer(void) 502static void ipi_timer(void)
482{ 503{
483 irq_enter(); 504 irq_enter();
484 profile_tick(CPU_PROFILING); 505 local_timer_interrupt();
485 update_process_times(user_mode(get_irq_regs()));
486 irq_exit(); 506 irq_exit();
487} 507}
488 508
@@ -621,6 +641,11 @@ void smp_send_timer(void)
621 send_ipi_message(mask, IPI_TIMER); 641 send_ipi_message(mask, IPI_TIMER);
622} 642}
623 643
644void smp_timer_broadcast(cpumask_t mask)
645{
646 send_ipi_message(mask, IPI_TIMER);
647}
648
624void smp_send_stop(void) 649void smp_send_stop(void)
625{ 650{
626 cpumask_t mask = cpu_online_map; 651 cpumask_t mask = cpu_online_map;
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 5b0422cdde76..074dcd5d9a7e 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -253,6 +253,36 @@ config AT91_TIMER_HZ
253 system clock (of at least several MHz), rounding is less of a 253 system clock (of at least several MHz), rounding is less of a
254 problem so it can be safer to use a decimal values like 100. 254 problem so it can be safer to use a decimal values like 100.
255 255
256choice
257 prompt "Select a UART for early kernel messages"
258
259config AT91_EARLY_DBGU
260 bool "DBGU"
261
262config AT91_EARLY_USART0
263 bool "USART0"
264
265config AT91_EARLY_USART1
266 bool "USART1"
267
268config AT91_EARLY_USART2
269 bool "USART2"
270 depends on ! ARCH_AT91X40
271
272config AT91_EARLY_USART3
273 bool "USART3"
274 depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260)
275
276config AT91_EARLY_USART4
277 bool "USART4"
278 depends on ARCH_AT91SAM9260
279
280config AT91_EARLY_USART5
281 bool "USART5"
282 depends on ARCH_AT91SAM9260
283
284endchoice
285
256endmenu 286endmenu
257 287
258endif 288endif
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 5c090c9442f5..e38d23770992 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -49,8 +49,6 @@ static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
49 volatile long nr_ticks; 49 volatile long nr_ticks;
50 50
51 if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */ 51 if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */
52 write_seqlock(&xtime_lock);
53
54 /* Get number to ticks performed before interrupt and clear PIT interrupt */ 52 /* Get number to ticks performed before interrupt and clear PIT interrupt */
55 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); 53 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
56 do { 54 do {
@@ -58,7 +56,6 @@ static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
58 nr_ticks--; 56 nr_ticks--;
59 } while (nr_ticks); 57 } while (nr_ticks);
60 58
61 write_sequnlock(&xtime_lock);
62 return IRQ_HANDLED; 59 return IRQ_HANDLED;
63 } else 60 } else
64 return IRQ_NONE; /* not handled */ 61 return IRQ_NONE; /* not handled */
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index b5daf7f5e011..7b9ce7a336b0 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -47,6 +47,9 @@ extern void at91_irq_resume(void);
47#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ 47#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
48 48
49struct at91_gpio_bank { 49struct at91_gpio_bank {
50 unsigned chipbase; /* bank's first GPIO number */
51 void __iomem *regbase; /* base of register bank */
52 struct at91_gpio_bank *next; /* bank sharing same IRQ/clock/... */
50 unsigned short id; /* peripheral ID */ 53 unsigned short id; /* peripheral ID */
51 unsigned long offset; /* offset from system peripheral base */ 54 unsigned long offset; /* offset from system peripheral base */
52 struct clk *clock; /* associated clock */ 55 struct clk *clock; /* associated clock */
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 6aeddd68d8af..f629c2b5f0c5 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -33,12 +33,10 @@ static int gpio_banks;
33 33
34static inline void __iomem *pin_to_controller(unsigned pin) 34static inline void __iomem *pin_to_controller(unsigned pin)
35{ 35{
36 void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
37
38 pin -= PIN_BASE; 36 pin -= PIN_BASE;
39 pin /= 32; 37 pin /= 32;
40 if (likely(pin < gpio_banks)) 38 if (likely(pin < gpio_banks))
41 return sys_base + gpio[pin].offset; 39 return gpio[pin].regbase;
42 40
43 return NULL; 41 return NULL;
44} 42}
@@ -294,11 +292,11 @@ void at91_gpio_suspend(void)
294 int i; 292 int i;
295 293
296 for (i = 0; i < gpio_banks; i++) { 294 for (i = 0; i < gpio_banks; i++) {
297 u32 pio = gpio[i].offset; 295 void __iomem *pio = gpio[i].regbase;
298 296
299 backups[i] = at91_sys_read(pio + PIO_IMR); 297 backups[i] = __raw_readl(pio + PIO_IMR);
300 at91_sys_write(pio + PIO_IDR, backups[i]); 298 __raw_writel(backups[i], pio + PIO_IDR);
301 at91_sys_write(pio + PIO_IER, wakeups[i]); 299 __raw_writel(wakeups[i], pio + PIO_IER);
302 300
303 if (!wakeups[i]) 301 if (!wakeups[i])
304 clk_disable(gpio[i].clock); 302 clk_disable(gpio[i].clock);
@@ -315,13 +313,13 @@ void at91_gpio_resume(void)
315 int i; 313 int i;
316 314
317 for (i = 0; i < gpio_banks; i++) { 315 for (i = 0; i < gpio_banks; i++) {
318 u32 pio = gpio[i].offset; 316 void __iomem *pio = gpio[i].regbase;
319 317
320 if (!wakeups[i]) 318 if (!wakeups[i])
321 clk_enable(gpio[i].clock); 319 clk_enable(gpio[i].clock);
322 320
323 at91_sys_write(pio + PIO_IDR, wakeups[i]); 321 __raw_writel(wakeups[i], pio + PIO_IDR);
324 at91_sys_write(pio + PIO_IER, backups[i]); 322 __raw_writel(backups[i], pio + PIO_IER);
325 } 323 }
326} 324}
327 325
@@ -361,7 +359,13 @@ static void gpio_irq_unmask(unsigned pin)
361 359
362static int gpio_irq_type(unsigned pin, unsigned type) 360static int gpio_irq_type(unsigned pin, unsigned type)
363{ 361{
364 return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL; 362 switch (type) {
363 case IRQ_TYPE_NONE:
364 case IRQ_TYPE_EDGE_BOTH:
365 return 0;
366 default:
367 return -EINVAL;
368 }
365} 369}
366 370
367static struct irq_chip gpio_irqchip = { 371static struct irq_chip gpio_irqchip = {
@@ -376,20 +380,30 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
376{ 380{
377 unsigned pin; 381 unsigned pin;
378 struct irq_desc *gpio; 382 struct irq_desc *gpio;
383 struct at91_gpio_bank *bank;
379 void __iomem *pio; 384 void __iomem *pio;
380 u32 isr; 385 u32 isr;
381 386
382 pio = get_irq_chip_data(irq); 387 bank = get_irq_chip_data(irq);
388 pio = bank->regbase;
383 389
384 /* temporarily mask (level sensitive) parent IRQ */ 390 /* temporarily mask (level sensitive) parent IRQ */
385 desc->chip->ack(irq); 391 desc->chip->ack(irq);
386 for (;;) { 392 for (;;) {
387 /* reading ISR acks the pending (edge triggered) GPIO interrupt */ 393 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
394 * When there none are pending, we're finished unless we need
395 * to process multiple banks (like ID_PIOCDE on sam9263).
396 */
388 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); 397 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
389 if (!isr) 398 if (!isr) {
390 break; 399 if (!bank->next)
400 break;
401 bank = bank->next;
402 pio = bank->regbase;
403 continue;
404 }
391 405
392 pin = (unsigned) get_irq_data(irq); 406 pin = bank->chipbase;
393 gpio = &irq_desc[pin]; 407 gpio = &irq_desc[pin];
394 408
395 while (isr) { 409 while (isr) {
@@ -481,24 +495,21 @@ postcore_initcall(at91_gpio_debugfs_init);
481 */ 495 */
482void __init at91_gpio_irq_setup(void) 496void __init at91_gpio_irq_setup(void)
483{ 497{
484 unsigned pioc, pin; 498 unsigned pioc, pin;
499 struct at91_gpio_bank *this, *prev;
485 500
486 for (pioc = 0, pin = PIN_BASE; 501 for (pioc = 0, pin = PIN_BASE, this = gpio, prev = NULL;
487 pioc < gpio_banks; 502 pioc++ < gpio_banks;
488 pioc++) { 503 prev = this, this++) {
489 void __iomem *controller; 504 unsigned id = this->id;
490 unsigned id = gpio[pioc].id;
491 unsigned i; 505 unsigned i;
492 506
493 clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */ 507 /* enable PIO controller's clock */
494 508 clk_enable(this->clock);
495 controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset;
496 __raw_writel(~0, controller + PIO_IDR);
497 509
498 set_irq_data(id, (void *) pin); 510 __raw_writel(~0, this->regbase + PIO_IDR);
499 set_irq_chip_data(id, controller);
500 511
501 for (i = 0; i < 32; i++, pin++) { 512 for (i = 0, pin = this->chipbase; i < 32; i++, pin++) {
502 /* 513 /*
503 * Can use the "simple" and not "edge" handler since it's 514 * Can use the "simple" and not "edge" handler since it's
504 * shorter, and the AIC handles interrupts sanely. 515 * shorter, and the AIC handles interrupts sanely.
@@ -508,6 +519,14 @@ void __init at91_gpio_irq_setup(void)
508 set_irq_flags(pin, IRQF_VALID); 519 set_irq_flags(pin, IRQF_VALID);
509 } 520 }
510 521
522 /* The toplevel handler handles one bank of GPIOs, except
523 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
524 * the list, so we only set up that handler.
525 */
526 if (prev && prev->next == this)
527 continue;
528
529 set_irq_chip_data(id, this);
511 set_irq_chained_handler(id, gpio_irq_handler); 530 set_irq_chained_handler(id, gpio_irq_handler);
512 } 531 }
513 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); 532 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
@@ -518,8 +537,20 @@ void __init at91_gpio_irq_setup(void)
518 */ 537 */
519void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) 538void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
520{ 539{
540 unsigned i;
541 struct at91_gpio_bank *last;
542
521 BUG_ON(nr_banks > MAX_GPIO_BANKS); 543 BUG_ON(nr_banks > MAX_GPIO_BANKS);
522 544
523 gpio = data; 545 gpio = data;
524 gpio_banks = nr_banks; 546 gpio_banks = nr_banks;
547
548 for (i = 0, last = NULL; i < nr_banks; i++, last = data, data++) {
549 data->chipbase = PIN_BASE + i * 32;
550 data->regbase = data->offset + (void __iomem *)AT91_VA_BASE_SYS;
551
552 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
553 if (last && last->id == data->id)
554 last->next = data;
555 }
525} 556}
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 61b2dfcb89d6..e774447c0592 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -189,6 +189,20 @@ config IXP4XX_INDIRECT_PCI
189 need to use the indirect method instead. If you don't know 189 need to use the indirect method instead. If you don't know
190 what you need, leave this option unselected. 190 what you need, leave this option unselected.
191 191
192config IXP4XX_QMGR
193 tristate "IXP4xx Queue Manager support"
194 help
195 This driver supports IXP4xx built-in hardware queue manager
196 and is automatically selected by Ethernet and HSS drivers.
197
198config IXP4XX_NPE
199 tristate "IXP4xx Network Processor Engine support"
200 select HOTPLUG
201 select FW_LOADER
202 help
203 This driver supports IXP4xx built-in network coprocessors
204 and is automatically selected by Ethernet and HSS drivers.
205
192endmenu 206endmenu
193 207
194endif 208endif
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index 77e00ade5585..c1956882c48b 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -23,10 +23,12 @@ obj-$(CONFIG_MACH_AVILA) += avila-setup.o
23obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o 23obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
24obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o 24obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
25obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o 25obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
26obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o nslu2-power.o 26obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o
27obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o nas100d-power.o 27obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o
28obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o dsmg600-power.o 28obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o
29obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o 29obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
30obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o 30obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
31 31
32obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o 32obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
33obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
34obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o
diff --git a/arch/arm/mach-ixp4xx/dsmg600-power.c b/arch/arm/mach-ixp4xx/dsmg600-power.c
deleted file mode 100644
index 34717872d076..000000000000
--- a/arch/arm/mach-ixp4xx/dsmg600-power.c
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/dsmg600-power.c
3 *
4 * DSM-G600 Power/Reset driver
5 * Author: Michael Westerhof <mwester@dls.net>
6 *
7 * Based on nslu2-power.c
8 * Copyright (C) 2005 Tower Technologies
9 * Author: Alessandro Zummo <a.zummo@towertech.it>
10 *
11 * which was based on nslu2-io.c
12 * Copyright (C) 2004 Karen Spearel
13 *
14 * Maintainers: http://www.nslu2-linux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/reboot.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/jiffies.h>
27#include <linux/timer.h>
28
29#include <asm/mach-types.h>
30
31extern void ctrl_alt_del(void);
32
33/* This is used to make sure the power-button pusher is serious. The button
34 * must be held until the value of this counter reaches zero.
35 */
36static volatile int power_button_countdown;
37
38/* Must hold the button down for at least this many counts to be processed */
39#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */
40
41static void dsmg600_power_handler(unsigned long data);
42static DEFINE_TIMER(dsmg600_power_timer, dsmg600_power_handler, 0, 0);
43
44static void dsmg600_power_handler(unsigned long data)
45{
46 /* This routine is called twice per second to check the
47 * state of the power button.
48 */
49
50 if (*IXP4XX_GPIO_GPINR & DSMG600_PB_BM) {
51
52 /* IO Pin is 1 (button pushed) */
53 if (power_button_countdown == 0) {
54 /* Signal init to do the ctrlaltdel action, this will bypass
55 * init if it hasn't started and do a kernel_restart.
56 */
57 ctrl_alt_del();
58
59 /* Change the state of the power LED to "blink" */
60 gpio_line_set(DSMG600_LED_PWR_GPIO, IXP4XX_GPIO_LOW);
61 }
62 power_button_countdown--;
63
64 } else {
65 power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
66 }
67
68 mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500));
69}
70
71static irqreturn_t dsmg600_reset_handler(int irq, void *dev_id)
72{
73 /* This is the paper-clip reset, it shuts the machine down directly. */
74 machine_power_off();
75
76 return IRQ_HANDLED;
77}
78
79static int __init dsmg600_power_init(void)
80{
81 if (!(machine_is_dsmg600()))
82 return 0;
83
84 if (request_irq(DSMG600_RB_IRQ, &dsmg600_reset_handler,
85 IRQF_DISABLED | IRQF_TRIGGER_LOW, "DSM-G600 reset button",
86 NULL) < 0) {
87
88 printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
89 DSMG600_RB_IRQ);
90
91 return -EIO;
92 }
93
94 /* The power button on the D-Link DSM-G600 is on GPIO 15, but
95 * it cannot handle interrupts on that GPIO line. So we'll
96 * have to poll it with a kernel timer.
97 */
98
99 /* Make sure that the power button GPIO is set up as an input */
100 gpio_line_config(DSMG600_PB_GPIO, IXP4XX_GPIO_IN);
101
102 /* Set the initial value for the power button IRQ handler */
103 power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
104
105 mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500));
106
107 return 0;
108}
109
110static void __exit dsmg600_power_exit(void)
111{
112 if (!(machine_is_dsmg600()))
113 return;
114
115 del_timer_sync(&dsmg600_power_timer);
116
117 free_irq(DSMG600_RB_IRQ, NULL);
118}
119
120module_init(dsmg600_power_init);
121module_exit(dsmg600_power_exit);
122
123MODULE_AUTHOR("Michael Westerhof <mwester@dls.net>");
124MODULE_DESCRIPTION("DSM-G600 Power/Reset driver");
125MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index c473d408aa7c..688659668bdf 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -1,25 +1,37 @@
1/* 1/*
2 * DSM-G600 board-setup 2 * DSM-G600 board-setup
3 * 3 *
4 * Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
4 * Copyright (C) 2006 Tower Technologies 5 * Copyright (C) 2006 Tower Technologies
5 * Author: Alessandro Zummo <a.zummo@towertech.it>
6 * 6 *
7 * based ixdp425-setup.c: 7 * based on ixdp425-setup.c:
8 * Copyright (C) 2003-2004 MontaVista Software, Inc. 8 * Copyright (C) 2003-2004 MontaVista Software, Inc.
9 * based on nslu2-power.c:
10 * Copyright (C) 2005 Tower Technologies
11 * based on nslu2-io.c:
12 * Copyright (C) 2004 Karen Spearel
9 * 13 *
10 * Author: Alessandro Zummo <a.zummo@towertech.it> 14 * Author: Alessandro Zummo <a.zummo@towertech.it>
15 * Author: Michael Westerhof <mwester@dls.net>
16 * Author: Rod Whitby <rod@whitby.id.au>
11 * Maintainers: http://www.nslu2-linux.org/ 17 * Maintainers: http://www.nslu2-linux.org/
12 */ 18 */
13 19
14#include <linux/kernel.h> 20#include <linux/irq.h>
21#include <linux/jiffies.h>
22#include <linux/timer.h>
15#include <linux/serial.h> 23#include <linux/serial.h>
16#include <linux/serial_8250.h> 24#include <linux/serial_8250.h>
25#include <linux/leds.h>
26#include <linux/reboot.h>
27#include <linux/i2c.h>
17#include <linux/i2c-gpio.h> 28#include <linux/i2c-gpio.h>
18 29
19#include <asm/mach-types.h> 30#include <asm/mach-types.h>
20#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
21#include <asm/mach/flash.h> 32#include <asm/mach/flash.h>
22#include <asm/mach/time.h> 33#include <asm/mach/time.h>
34#include <asm/gpio.h>
23 35
24static struct flash_platform_data dsmg600_flash_data = { 36static struct flash_platform_data dsmg600_flash_data = {
25 .map_name = "cfi_probe", 37 .map_name = "cfi_probe",
@@ -51,29 +63,34 @@ static struct platform_device dsmg600_i2c_gpio = {
51 }, 63 },
52}; 64};
53 65
54#ifdef CONFIG_LEDS_CLASS 66static struct i2c_board_info __initdata dsmg600_i2c_board_info [] = {
55static struct resource dsmg600_led_resources[] = { 67 {
68 I2C_BOARD_INFO("rtc-pcf8563", 0x51),
69 },
70};
71
72static struct gpio_led dsmg600_led_pins[] = {
56 { 73 {
57 .name = "power", 74 .name = "power",
58 .start = DSMG600_LED_PWR_GPIO, 75 .gpio = DSMG600_LED_PWR_GPIO,
59 .end = DSMG600_LED_PWR_GPIO,
60 .flags = IXP4XX_GPIO_HIGH,
61 }, 76 },
62 { 77 {
63 .name = "wlan", 78 .name = "wlan",
64 .start = DSMG600_LED_WLAN_GPIO, 79 .gpio = DSMG600_LED_WLAN_GPIO,
65 .end = DSMG600_LED_WLAN_GPIO, 80 .active_low = true,
66 .flags = IXP4XX_GPIO_LOW,
67 }, 81 },
68}; 82};
69 83
84static struct gpio_led_platform_data dsmg600_led_data = {
85 .num_leds = ARRAY_SIZE(dsmg600_led_pins),
86 .leds = dsmg600_led_pins,
87};
88
70static struct platform_device dsmg600_leds = { 89static struct platform_device dsmg600_leds = {
71 .name = "IXP4XX-GPIO-LED", 90 .name = "leds-gpio",
72 .id = -1, 91 .id = -1,
73 .num_resources = ARRAY_SIZE(dsmg600_led_resources), 92 .dev.platform_data = &dsmg600_led_data,
74 .resource = dsmg600_led_resources,
75}; 93};
76#endif
77 94
78static struct resource dsmg600_uart_resources[] = { 95static struct resource dsmg600_uart_resources[] = {
79 { 96 {
@@ -121,6 +138,7 @@ static struct platform_device dsmg600_uart = {
121static struct platform_device *dsmg600_devices[] __initdata = { 138static struct platform_device *dsmg600_devices[] __initdata = {
122 &dsmg600_i2c_gpio, 139 &dsmg600_i2c_gpio,
123 &dsmg600_flash, 140 &dsmg600_flash,
141 &dsmg600_leds,
124}; 142};
125 143
126static void dsmg600_power_off(void) 144static void dsmg600_power_off(void)
@@ -132,6 +150,57 @@ static void dsmg600_power_off(void)
132 gpio_line_set(DSMG600_PO_GPIO, IXP4XX_GPIO_HIGH); 150 gpio_line_set(DSMG600_PO_GPIO, IXP4XX_GPIO_HIGH);
133} 151}
134 152
153/* This is used to make sure the power-button pusher is serious. The button
154 * must be held until the value of this counter reaches zero.
155 */
156static int power_button_countdown;
157
158/* Must hold the button down for at least this many counts to be processed */
159#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */
160
161static void dsmg600_power_handler(unsigned long data);
162static DEFINE_TIMER(dsmg600_power_timer, dsmg600_power_handler, 0, 0);
163
164static void dsmg600_power_handler(unsigned long data)
165{
166 /* This routine is called twice per second to check the
167 * state of the power button.
168 */
169
170 if (gpio_get_value(DSMG600_PB_GPIO)) {
171
172 /* IO Pin is 1 (button pushed) */
173 if (power_button_countdown > 0)
174 power_button_countdown--;
175
176 } else {
177
178 /* Done on button release, to allow for auto-power-on mods. */
179 if (power_button_countdown == 0) {
180 /* Signal init to do the ctrlaltdel action,
181 * this will bypass init if it hasn't started
182 * and do a kernel_restart.
183 */
184 ctrl_alt_del();
185
186 /* Change the state of the power LED to "blink" */
187 gpio_line_set(DSMG600_LED_PWR_GPIO, IXP4XX_GPIO_LOW);
188 } else {
189 power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
190 }
191 }
192
193 mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500));
194}
195
196static irqreturn_t dsmg600_reset_handler(int irq, void *dev_id)
197{
198 /* This is the paper-clip reset, it shuts the machine down directly. */
199 machine_power_off();
200
201 return IRQ_HANDLED;
202}
203
135static void __init dsmg600_timer_init(void) 204static void __init dsmg600_timer_init(void)
136{ 205{
137 /* The xtal on this machine is non-standard. */ 206 /* The xtal on this machine is non-standard. */
@@ -156,7 +225,8 @@ static void __init dsmg600_init(void)
156 dsmg600_flash_resource.end = 225 dsmg600_flash_resource.end =
157 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; 226 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
158 227
159 pm_power_off = dsmg600_power_off; 228 i2c_register_board_info(0, dsmg600_i2c_board_info,
229 ARRAY_SIZE(dsmg600_i2c_board_info));
160 230
161 /* The UART is required on the DSM-G600 (Redboot cannot use the 231 /* The UART is required on the DSM-G600 (Redboot cannot use the
162 * NIC) -- do it here so that it does *not* get removed if 232 * NIC) -- do it here so that it does *not* get removed if
@@ -166,10 +236,28 @@ static void __init dsmg600_init(void)
166 236
167 platform_add_devices(dsmg600_devices, ARRAY_SIZE(dsmg600_devices)); 237 platform_add_devices(dsmg600_devices, ARRAY_SIZE(dsmg600_devices));
168 238
169#ifdef CONFIG_LEDS_CLASS 239 pm_power_off = dsmg600_power_off;
170 /* We don't care whether or not this works. */ 240
171 (void)platform_device_register(&dsmg600_leds); 241 if (request_irq(gpio_to_irq(DSMG600_RB_GPIO), &dsmg600_reset_handler,
172#endif 242 IRQF_DISABLED | IRQF_TRIGGER_LOW,
243 "DSM-G600 reset button", NULL) < 0) {
244
245 printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
246 gpio_to_irq(DSMG600_RB_GPIO));
247 }
248
249 /* The power button on the D-Link DSM-G600 is on GPIO 15, but
250 * it cannot handle interrupts on that GPIO line. So we'll
251 * have to poll it with a kernel timer.
252 */
253
254 /* Make sure that the power button GPIO is set up as an input */
255 gpio_line_config(DSMG600_PB_GPIO, IXP4XX_GPIO_IN);
256
257 /* Set the initial value for the power button IRQ handler */
258 power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
259
260 mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500));
173} 261}
174 262
175MACHINE_START(DSMG600, "D-Link DSM-G600 RevA") 263MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index e89070da28bf..44584afb34a3 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -177,6 +177,31 @@ static struct platform_device ixdp425_uart = {
177 .resource = ixdp425_uart_resources 177 .resource = ixdp425_uart_resources
178}; 178};
179 179
180/* Built-in 10/100 Ethernet MAC interfaces */
181static struct eth_plat_info ixdp425_plat_eth[] = {
182 {
183 .phy = 0,
184 .rxq = 3,
185 .txreadyq = 20,
186 }, {
187 .phy = 1,
188 .rxq = 4,
189 .txreadyq = 21,
190 }
191};
192
193static struct platform_device ixdp425_eth[] = {
194 {
195 .name = "ixp4xx_eth",
196 .id = IXP4XX_ETH_NPEB,
197 .dev.platform_data = ixdp425_plat_eth,
198 }, {
199 .name = "ixp4xx_eth",
200 .id = IXP4XX_ETH_NPEC,
201 .dev.platform_data = ixdp425_plat_eth + 1,
202 }
203};
204
180static struct platform_device *ixdp425_devices[] __initdata = { 205static struct platform_device *ixdp425_devices[] __initdata = {
181 &ixdp425_i2c_gpio, 206 &ixdp425_i2c_gpio,
182 &ixdp425_flash, 207 &ixdp425_flash,
@@ -184,7 +209,9 @@ static struct platform_device *ixdp425_devices[] __initdata = {
184 defined(CONFIG_MTD_NAND_PLATFORM_MODULE) 209 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
185 &ixdp425_flash_nand, 210 &ixdp425_flash_nand,
186#endif 211#endif
187 &ixdp425_uart 212 &ixdp425_uart,
213 &ixdp425_eth[0],
214 &ixdp425_eth[1],
188}; 215};
189 216
190static void __init ixdp425_init(void) 217static void __init ixdp425_init(void)
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
new file mode 100644
index 000000000000..83c137ec582c
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -0,0 +1,741 @@
1/*
2 * Intel IXP4xx Network Processor Engine driver for Linux
3 *
4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * The code is based on publicly available information:
11 * - Intel IXP4xx Developer's Manual and other e-papers
12 * - Intel IXP400 Access Library Software (BSD license)
13 * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com>
14 * Thanks, Christian.
15 */
16
17#include <linux/delay.h>
18#include <linux/dma-mapping.h>
19#include <linux/firmware.h>
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <asm/arch/npe.h>
25
26#define DEBUG_MSG 0
27#define DEBUG_FW 0
28
29#define NPE_COUNT 3
30#define MAX_RETRIES 1000 /* microseconds */
31#define NPE_42X_DATA_SIZE 0x800 /* in dwords */
32#define NPE_46X_DATA_SIZE 0x1000
33#define NPE_A_42X_INSTR_SIZE 0x1000
34#define NPE_B_AND_C_42X_INSTR_SIZE 0x800
35#define NPE_46X_INSTR_SIZE 0x1000
36#define REGS_SIZE 0x1000
37
38#define NPE_PHYS_REG 32
39
40#define FW_MAGIC 0xFEEDF00D
41#define FW_BLOCK_TYPE_INSTR 0x0
42#define FW_BLOCK_TYPE_DATA 0x1
43#define FW_BLOCK_TYPE_EOF 0xF
44
45/* NPE exec status (read) and command (write) */
46#define CMD_NPE_STEP 0x01
47#define CMD_NPE_START 0x02
48#define CMD_NPE_STOP 0x03
49#define CMD_NPE_CLR_PIPE 0x04
50#define CMD_CLR_PROFILE_CNT 0x0C
51#define CMD_RD_INS_MEM 0x10 /* instruction memory */
52#define CMD_WR_INS_MEM 0x11
53#define CMD_RD_DATA_MEM 0x12 /* data memory */
54#define CMD_WR_DATA_MEM 0x13
55#define CMD_RD_ECS_REG 0x14 /* exec access register */
56#define CMD_WR_ECS_REG 0x15
57
58#define STAT_RUN 0x80000000
59#define STAT_STOP 0x40000000
60#define STAT_CLEAR 0x20000000
61#define STAT_ECS_K 0x00800000 /* pipeline clean */
62
63#define NPE_STEVT 0x1B
64#define NPE_STARTPC 0x1C
65#define NPE_REGMAP 0x1E
66#define NPE_CINDEX 0x1F
67
68#define INSTR_WR_REG_SHORT 0x0000C000
69#define INSTR_WR_REG_BYTE 0x00004000
70#define INSTR_RD_FIFO 0x0F888220
71#define INSTR_RESET_MBOX 0x0FAC8210
72
73#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */
74#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */
75#define ECS_BG_CTXT_REG_2 0x02
76#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */
77#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */
78#define ECS_PRI_1_CTXT_REG_2 0x06
79#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */
80#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */
81#define ECS_PRI_2_CTXT_REG_2 0x0A
82#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */
83#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */
84#define ECS_DBG_CTXT_REG_2 0x0E
85#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */
86
87#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */
88#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */
89#define ECS_REG_0_LDUR_BITS 8
90#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */
91#define ECS_REG_1_CCTXT_BITS 16
92#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */
93#define ECS_REG_1_SELCTXT_BITS 0
94#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */
95#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */
96#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */
97
98/* NPE watchpoint_fifo register bit */
99#define WFIFO_VALID 0x80000000
100
101/* NPE messaging_status register bit definitions */
102#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */
103#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */
104#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */
105#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */
106#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */
107#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */
108#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */
109#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */
110
111/* NPE messaging_control register bit definitions */
112#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */
113#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */
114#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */
115#define MSGCTL_IN_FIFO_WRITE 0x02000000
116
117/* NPE mailbox_status value for reset */
118#define RESET_MBOX_STAT 0x0000F0F0
119
120const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
121
122#define print_npe(pri, npe, fmt, ...) \
123 printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
124
125#if DEBUG_MSG
126#define debug_msg(npe, fmt, ...) \
127 print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
128#else
129#define debug_msg(npe, fmt, ...)
130#endif
131
132static struct {
133 u32 reg, val;
134} ecs_reset[] = {
135 { ECS_BG_CTXT_REG_0, 0xA0000000 },
136 { ECS_BG_CTXT_REG_1, 0x01000000 },
137 { ECS_BG_CTXT_REG_2, 0x00008000 },
138 { ECS_PRI_1_CTXT_REG_0, 0x20000080 },
139 { ECS_PRI_1_CTXT_REG_1, 0x01000000 },
140 { ECS_PRI_1_CTXT_REG_2, 0x00008000 },
141 { ECS_PRI_2_CTXT_REG_0, 0x20000080 },
142 { ECS_PRI_2_CTXT_REG_1, 0x01000000 },
143 { ECS_PRI_2_CTXT_REG_2, 0x00008000 },
144 { ECS_DBG_CTXT_REG_0, 0x20000000 },
145 { ECS_DBG_CTXT_REG_1, 0x00000000 },
146 { ECS_DBG_CTXT_REG_2, 0x001E0000 },
147 { ECS_INSTRUCT_REG, 0x1003C00F },
148};
149
150static struct npe npe_tab[NPE_COUNT] = {
151 {
152 .id = 0,
153 .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT,
154 .regs_phys = IXP4XX_NPEA_BASE_PHYS,
155 }, {
156 .id = 1,
157 .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT,
158 .regs_phys = IXP4XX_NPEB_BASE_PHYS,
159 }, {
160 .id = 2,
161 .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT,
162 .regs_phys = IXP4XX_NPEC_BASE_PHYS,
163 }
164};
165
166int npe_running(struct npe *npe)
167{
168 return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
169}
170
171static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
172{
173 __raw_writel(data, &npe->regs->exec_data);
174 __raw_writel(addr, &npe->regs->exec_addr);
175 __raw_writel(cmd, &npe->regs->exec_status_cmd);
176}
177
178static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
179{
180 __raw_writel(addr, &npe->regs->exec_addr);
181 __raw_writel(cmd, &npe->regs->exec_status_cmd);
182 /* Iintroduce extra read cycles after issuing read command to NPE
183 so that we read the register after the NPE has updated it.
184 This is to overcome race condition between XScale and NPE */
185 __raw_readl(&npe->regs->exec_data);
186 __raw_readl(&npe->regs->exec_data);
187 return __raw_readl(&npe->regs->exec_data);
188}
189
190static void npe_clear_active(struct npe *npe, u32 reg)
191{
192 u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
193 npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
194}
195
196static void npe_start(struct npe *npe)
197{
198 /* ensure only Background Context Stack Level is active */
199 npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
200 npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
201 npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
202
203 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
204 __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
205}
206
207static void npe_stop(struct npe *npe)
208{
209 __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
210 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
211}
212
213static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
214 u32 ldur)
215{
216 u32 wc;
217 int i;
218
219 /* set the Active bit, and the LDUR, in the debug level */
220 npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
221 ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
222
223 /* set CCTXT at ECS DEBUG L3 to specify in which context to execute
224 the instruction, and set SELCTXT at ECS DEBUG Level to specify
225 which context store to access.
226 Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
227 */
228 npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
229 (ctx << ECS_REG_1_CCTXT_BITS) |
230 (ctx << ECS_REG_1_SELCTXT_BITS));
231
232 /* clear the pipeline */
233 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
234
235 /* load NPE instruction into the instruction register */
236 npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
237
238 /* we need this value later to wait for completion of NPE execution
239 step */
240 wc = __raw_readl(&npe->regs->watch_count);
241
242 /* issue a Step One command via the Execution Control register */
243 __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
244
245 /* Watch Count register increments when NPE completes an instruction */
246 for (i = 0; i < MAX_RETRIES; i++) {
247 if (wc != __raw_readl(&npe->regs->watch_count))
248 return 0;
249 udelay(1);
250 }
251
252 print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
253 return -ETIMEDOUT;
254}
255
256static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
257 u8 val, u32 ctx)
258{
259 /* here we build the NPE assembler instruction: mov8 d0, #0 */
260 u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
261 addr << 9 | /* base Operand */
262 (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
263 (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
264 return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
265}
266
267static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
268 u16 val, u32 ctx)
269{
270 /* here we build the NPE assembler instruction: mov16 d0, #0 */
271 u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
272 addr << 9 | /* base Operand */
273 (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
274 (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
275 return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
276}
277
278static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
279 u32 val, u32 ctx)
280{
281 /* write in 16 bit steps first the high and then the low value */
282 if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
283 return -ETIMEDOUT;
284 return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
285}
286
287static int npe_reset(struct npe *npe)
288{
289 u32 val, ctl, exec_count, ctx_reg2;
290 int i;
291
292 ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
293 0x3F3FFFFF;
294
295 /* disable parity interrupt */
296 __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
297
298 /* pre exec - debug instruction */
299 /* turn off the halt bit by clearing Execution Count register. */
300 exec_count = __raw_readl(&npe->regs->exec_count);
301 __raw_writel(0, &npe->regs->exec_count);
302 /* ensure that IF and IE are on (temporarily), so that we don't end up
303 stepping forever */
304 ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
305 npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
306 ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
307
308 /* clear the FIFOs */
309 while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
310 ;
311 while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
312 /* read from the outFIFO until empty */
313 print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
314 __raw_readl(&npe->regs->in_out_fifo));
315
316 while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
317 /* step execution of the NPE intruction to read inFIFO using
318 the Debug Executing Context stack */
319 if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
320 return -ETIMEDOUT;
321
322 /* reset the mailbox reg from the XScale side */
323 __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
324 /* from NPE side */
325 if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
326 return -ETIMEDOUT;
327
328 /* Reset the physical registers in the NPE register file */
329 for (val = 0; val < NPE_PHYS_REG; val++) {
330 if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
331 return -ETIMEDOUT;
332 /* address is either 0 or 4 */
333 if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
334 return -ETIMEDOUT;
335 }
336
337 /* Reset the context store = each context's Context Store registers */
338
339 /* Context 0 has no STARTPC. Instead, this value is used to set NextPC
340 for Background ECS, to set where NPE starts executing code */
341 val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
342 val &= ~ECS_REG_0_NEXTPC_MASK;
343 val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
344 npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
345
346 for (i = 0; i < 16; i++) {
347 if (i) { /* Context 0 has no STEVT nor STARTPC */
348 /* STEVT = off, 0x80 */
349 if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
350 return -ETIMEDOUT;
351 if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
352 return -ETIMEDOUT;
353 }
354 /* REGMAP = d0->p0, d8->p2, d16->p4 */
355 if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
356 return -ETIMEDOUT;
357 if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
358 return -ETIMEDOUT;
359 }
360
361 /* post exec */
362 /* clear active bit in debug level */
363 npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
364 /* clear the pipeline */
365 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
366 /* restore previous values */
367 __raw_writel(exec_count, &npe->regs->exec_count);
368 npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
369
370 /* write reset values to Execution Context Stack registers */
371 for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
372 npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
373 ecs_reset[val].val);
374
375 /* clear the profile counter */
376 __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
377
378 __raw_writel(0, &npe->regs->exec_count);
379 __raw_writel(0, &npe->regs->action_points[0]);
380 __raw_writel(0, &npe->regs->action_points[1]);
381 __raw_writel(0, &npe->regs->action_points[2]);
382 __raw_writel(0, &npe->regs->action_points[3]);
383 __raw_writel(0, &npe->regs->watch_count);
384
385 val = ixp4xx_read_feature_bits();
386 /* reset the NPE */
387 ixp4xx_write_feature_bits(val &
388 ~(IXP4XX_FEATURE_RESET_NPEA << npe->id));
389 for (i = 0; i < MAX_RETRIES; i++) {
390 if (!(ixp4xx_read_feature_bits() &
391 (IXP4XX_FEATURE_RESET_NPEA << npe->id)))
392 break; /* reset completed */
393 udelay(1);
394 }
395 if (i == MAX_RETRIES)
396 return -ETIMEDOUT;
397
398 /* deassert reset */
399 ixp4xx_write_feature_bits(val |
400 (IXP4XX_FEATURE_RESET_NPEA << npe->id));
401 for (i = 0; i < MAX_RETRIES; i++) {
402 if (ixp4xx_read_feature_bits() &
403 (IXP4XX_FEATURE_RESET_NPEA << npe->id))
404 break; /* NPE is back alive */
405 udelay(1);
406 }
407 if (i == MAX_RETRIES)
408 return -ETIMEDOUT;
409
410 npe_stop(npe);
411
412 /* restore NPE configuration bus Control Register - parity settings */
413 __raw_writel(ctl, &npe->regs->messaging_control);
414 return 0;
415}
416
417
418int npe_send_message(struct npe *npe, const void *msg, const char *what)
419{
420 const u32 *send = msg;
421 int cycles = 0;
422
423 debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
424 what, send[0], send[1]);
425
426 if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
427 debug_msg(npe, "NPE input FIFO not empty\n");
428 return -EIO;
429 }
430
431 __raw_writel(send[0], &npe->regs->in_out_fifo);
432
433 if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
434 debug_msg(npe, "NPE input FIFO full\n");
435 return -EIO;
436 }
437
438 __raw_writel(send[1], &npe->regs->in_out_fifo);
439
440 while ((cycles < MAX_RETRIES) &&
441 (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
442 udelay(1);
443 cycles++;
444 }
445
446 if (cycles == MAX_RETRIES) {
447 debug_msg(npe, "Timeout sending message\n");
448 return -ETIMEDOUT;
449 }
450
451 debug_msg(npe, "Sending a message took %i cycles\n", cycles);
452 return 0;
453}
454
455int npe_recv_message(struct npe *npe, void *msg, const char *what)
456{
457 u32 *recv = msg;
458 int cycles = 0, cnt = 0;
459
460 debug_msg(npe, "Trying to receive message %s\n", what);
461
462 while (cycles < MAX_RETRIES) {
463 if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
464 recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
465 if (cnt == 2)
466 break;
467 } else {
468 udelay(1);
469 cycles++;
470 }
471 }
472
473 switch(cnt) {
474 case 1:
475 debug_msg(npe, "Received [%08X]\n", recv[0]);
476 break;
477 case 2:
478 debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
479 break;
480 }
481
482 if (cycles == MAX_RETRIES) {
483 debug_msg(npe, "Timeout waiting for message\n");
484 return -ETIMEDOUT;
485 }
486
487 debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
488 return 0;
489}
490
491int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
492{
493 int result;
494 u32 *send = msg, recv[2];
495
496 if ((result = npe_send_message(npe, msg, what)) != 0)
497 return result;
498 if ((result = npe_recv_message(npe, recv, what)) != 0)
499 return result;
500
501 if ((recv[0] != send[0]) || (recv[1] != send[1])) {
502 debug_msg(npe, "Message %s: unexpected message received\n",
503 what);
504 return -EIO;
505 }
506 return 0;
507}
508
509
510int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
511{
512 const struct firmware *fw_entry;
513
514 struct dl_block {
515 u32 type;
516 u32 offset;
517 } *blk;
518
519 struct dl_image {
520 u32 magic;
521 u32 id;
522 u32 size;
523 union {
524 u32 data[0];
525 struct dl_block blocks[0];
526 };
527 } *image;
528
529 struct dl_codeblock {
530 u32 npe_addr;
531 u32 size;
532 u32 data[0];
533 } *cb;
534
535 int i, j, err, data_size, instr_size, blocks, table_end;
536 u32 cmd;
537
538 if ((err = request_firmware(&fw_entry, name, dev)) != 0)
539 return err;
540
541 err = -EINVAL;
542 if (fw_entry->size < sizeof(struct dl_image)) {
543 print_npe(KERN_ERR, npe, "incomplete firmware file\n");
544 goto err;
545 }
546 image = (struct dl_image*)fw_entry->data;
547
548#if DEBUG_FW
549 print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
550 image->magic, image->id, image->size, image->size * 4);
551#endif
552
553 if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
554 image->id = swab32(image->id);
555 image->size = swab32(image->size);
556 } else if (image->magic != FW_MAGIC) {
557 print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
558 image->magic);
559 goto err;
560 }
561 if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
562 print_npe(KERN_ERR, npe,
563 "inconsistent size of firmware file\n");
564 goto err;
565 }
566 if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
567 print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
568 goto err;
569 }
570 if (image->magic == swab32(FW_MAGIC))
571 for (i = 0; i < image->size; i++)
572 image->data[i] = swab32(image->data[i]);
573
574 if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
575 print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
576 "IXP42x\n");
577 goto err;
578 }
579
580 if (npe_running(npe)) {
581 print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
582 "already running\n");
583 err = -EBUSY;
584 goto err;
585 }
586#if 0
587 npe_stop(npe);
588 npe_reset(npe);
589#endif
590
591 print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
592 "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
593 (image->id >> 8) & 0xFF, image->id & 0xFF);
594
595 if (!cpu_is_ixp46x()) {
596 if (!npe->id)
597 instr_size = NPE_A_42X_INSTR_SIZE;
598 else
599 instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
600 data_size = NPE_42X_DATA_SIZE;
601 } else {
602 instr_size = NPE_46X_INSTR_SIZE;
603 data_size = NPE_46X_DATA_SIZE;
604 }
605
606 for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
607 blocks++)
608 if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
609 break;
610 if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
611 print_npe(KERN_INFO, npe, "firmware EOF block marker not "
612 "found\n");
613 goto err;
614 }
615
616#if DEBUG_FW
617 print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
618#endif
619
620 table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
621 for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
622 if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
623 || blk->offset < table_end) {
624 print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
625 "firmware block #%i\n", blk->offset, i);
626 goto err;
627 }
628
629 cb = (struct dl_codeblock*)&image->data[blk->offset];
630 if (blk->type == FW_BLOCK_TYPE_INSTR) {
631 if (cb->npe_addr + cb->size > instr_size)
632 goto too_big;
633 cmd = CMD_WR_INS_MEM;
634 } else if (blk->type == FW_BLOCK_TYPE_DATA) {
635 if (cb->npe_addr + cb->size > data_size)
636 goto too_big;
637 cmd = CMD_WR_DATA_MEM;
638 } else {
639 print_npe(KERN_INFO, npe, "invalid firmware block #%i "
640 "type 0x%X\n", i, blk->type);
641 goto err;
642 }
643 if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
644 print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
645 "fit in firmware image: type %c, start 0x%X,"
646 " length 0x%X\n", i,
647 blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
648 cb->npe_addr, cb->size);
649 goto err;
650 }
651
652 for (j = 0; j < cb->size; j++)
653 npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
654 }
655
656 npe_start(npe);
657 if (!npe_running(npe))
658 print_npe(KERN_ERR, npe, "unable to start\n");
659 release_firmware(fw_entry);
660 return 0;
661
662too_big:
663 print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
664 "memory: type %c, start 0x%X, length 0x%X\n", i,
665 blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
666 cb->npe_addr, cb->size);
667err:
668 release_firmware(fw_entry);
669 return err;
670}
671
672
673struct npe *npe_request(int id)
674{
675 if (id < NPE_COUNT)
676 if (npe_tab[id].valid)
677 if (try_module_get(THIS_MODULE))
678 return &npe_tab[id];
679 return NULL;
680}
681
682void npe_release(struct npe *npe)
683{
684 module_put(THIS_MODULE);
685}
686
687
688static int __init npe_init_module(void)
689{
690
691 int i, found = 0;
692
693 for (i = 0; i < NPE_COUNT; i++) {
694 struct npe *npe = &npe_tab[i];
695 if (!(ixp4xx_read_feature_bits() &
696 (IXP4XX_FEATURE_RESET_NPEA << i)))
697 continue; /* NPE already disabled or not present */
698 if (!(npe->mem_res = request_mem_region(npe->regs_phys,
699 REGS_SIZE,
700 npe_name(npe)))) {
701 print_npe(KERN_ERR, npe,
702 "failed to request memory region\n");
703 continue;
704 }
705
706 if (npe_reset(npe))
707 continue;
708 npe->valid = 1;
709 found++;
710 }
711
712 if (!found)
713 return -ENOSYS;
714 return 0;
715}
716
717static void __exit npe_cleanup_module(void)
718{
719 int i;
720
721 for (i = 0; i < NPE_COUNT; i++)
722 if (npe_tab[i].mem_res) {
723 npe_reset(&npe_tab[i]);
724 release_resource(npe_tab[i].mem_res);
725 }
726}
727
728module_init(npe_init_module);
729module_exit(npe_cleanup_module);
730
731MODULE_AUTHOR("Krzysztof Halasa");
732MODULE_LICENSE("GPL v2");
733
734EXPORT_SYMBOL(npe_names);
735EXPORT_SYMBOL(npe_running);
736EXPORT_SYMBOL(npe_request);
737EXPORT_SYMBOL(npe_release);
738EXPORT_SYMBOL(npe_load_firmware);
739EXPORT_SYMBOL(npe_send_message);
740EXPORT_SYMBOL(npe_recv_message);
741EXPORT_SYMBOL(npe_send_recv_message);
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
new file mode 100644
index 000000000000..e83301325301
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
@@ -0,0 +1,274 @@
1/*
2 * Intel IXP4xx Queue Manager driver for Linux
3 *
4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 */
10
11#include <linux/ioport.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <asm/arch/qmgr.h>
16
17#define DEBUG 0
18
19struct qmgr_regs __iomem *qmgr_regs;
20static struct resource *mem_res;
21static spinlock_t qmgr_lock;
22static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
23static void (*irq_handlers[HALF_QUEUES])(void *pdev);
24static void *irq_pdevs[HALF_QUEUES];
25
26void qmgr_set_irq(unsigned int queue, int src,
27 void (*handler)(void *pdev), void *pdev)
28{
29 u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */
30 int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
31 unsigned long flags;
32
33 src &= 7;
34 spin_lock_irqsave(&qmgr_lock, flags);
35 __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg);
36 irq_handlers[queue] = handler;
37 irq_pdevs[queue] = pdev;
38 spin_unlock_irqrestore(&qmgr_lock, flags);
39}
40
41
42static irqreturn_t qmgr_irq1(int irq, void *pdev)
43{
44 int i;
45 u32 val = __raw_readl(&qmgr_regs->irqstat[0]);
46 __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */
47
48 for (i = 0; i < HALF_QUEUES; i++)
49 if (val & (1 << i))
50 irq_handlers[i](irq_pdevs[i]);
51
52 return val ? IRQ_HANDLED : 0;
53}
54
55
56void qmgr_enable_irq(unsigned int queue)
57{
58 unsigned long flags;
59
60 spin_lock_irqsave(&qmgr_lock, flags);
61 __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue),
62 &qmgr_regs->irqen[0]);
63 spin_unlock_irqrestore(&qmgr_lock, flags);
64}
65
66void qmgr_disable_irq(unsigned int queue)
67{
68 unsigned long flags;
69
70 spin_lock_irqsave(&qmgr_lock, flags);
71 __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
72 &qmgr_regs->irqen[0]);
73 spin_unlock_irqrestore(&qmgr_lock, flags);
74}
75
76static inline void shift_mask(u32 *mask)
77{
78 mask[3] = mask[3] << 1 | mask[2] >> 31;
79 mask[2] = mask[2] << 1 | mask[1] >> 31;
80 mask[1] = mask[1] << 1 | mask[0] >> 31;
81 mask[0] <<= 1;
82}
83
84int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
85 unsigned int nearly_empty_watermark,
86 unsigned int nearly_full_watermark)
87{
88 u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
89 int err;
90
91 if (queue >= HALF_QUEUES)
92 return -ERANGE;
93
94 if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
95 return -EINVAL;
96
97 switch (len) {
98 case 16:
99 cfg = 0 << 24;
100 mask[0] = 0x1;
101 break;
102 case 32:
103 cfg = 1 << 24;
104 mask[0] = 0x3;
105 break;
106 case 64:
107 cfg = 2 << 24;
108 mask[0] = 0xF;
109 break;
110 case 128:
111 cfg = 3 << 24;
112 mask[0] = 0xFF;
113 break;
114 default:
115 return -EINVAL;
116 }
117
118 cfg |= nearly_empty_watermark << 26;
119 cfg |= nearly_full_watermark << 29;
120 len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
121 mask[1] = mask[2] = mask[3] = 0;
122
123 if (!try_module_get(THIS_MODULE))
124 return -ENODEV;
125
126 spin_lock_irq(&qmgr_lock);
127 if (__raw_readl(&qmgr_regs->sram[queue])) {
128 err = -EBUSY;
129 goto err;
130 }
131
132 while (1) {
133 if (!(used_sram_bitmap[0] & mask[0]) &&
134 !(used_sram_bitmap[1] & mask[1]) &&
135 !(used_sram_bitmap[2] & mask[2]) &&
136 !(used_sram_bitmap[3] & mask[3]))
137 break; /* found free space */
138
139 addr++;
140 shift_mask(mask);
141 if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
142 printk(KERN_ERR "qmgr: no free SRAM space for"
143 " queue %i\n", queue);
144 err = -ENOMEM;
145 goto err;
146 }
147 }
148
149 used_sram_bitmap[0] |= mask[0];
150 used_sram_bitmap[1] |= mask[1];
151 used_sram_bitmap[2] |= mask[2];
152 used_sram_bitmap[3] |= mask[3];
153 __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
154 spin_unlock_irq(&qmgr_lock);
155
156#if DEBUG
157 printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n",
158 queue, addr);
159#endif
160 return 0;
161
162err:
163 spin_unlock_irq(&qmgr_lock);
164 module_put(THIS_MODULE);
165 return err;
166}
167
168void qmgr_release_queue(unsigned int queue)
169{
170 u32 cfg, addr, mask[4];
171
172 BUG_ON(queue >= HALF_QUEUES); /* not in valid range */
173
174 spin_lock_irq(&qmgr_lock);
175 cfg = __raw_readl(&qmgr_regs->sram[queue]);
176 addr = (cfg >> 14) & 0xFF;
177
178 BUG_ON(!addr); /* not requested */
179
180 switch ((cfg >> 24) & 3) {
181 case 0: mask[0] = 0x1; break;
182 case 1: mask[0] = 0x3; break;
183 case 2: mask[0] = 0xF; break;
184 case 3: mask[0] = 0xFF; break;
185 }
186
187 while (addr--)
188 shift_mask(mask);
189
190 __raw_writel(0, &qmgr_regs->sram[queue]);
191
192 used_sram_bitmap[0] &= ~mask[0];
193 used_sram_bitmap[1] &= ~mask[1];
194 used_sram_bitmap[2] &= ~mask[2];
195 used_sram_bitmap[3] &= ~mask[3];
196 irq_handlers[queue] = NULL; /* catch IRQ bugs */
197 spin_unlock_irq(&qmgr_lock);
198
199 module_put(THIS_MODULE);
200#if DEBUG
201 printk(KERN_DEBUG "qmgr: released queue %i\n", queue);
202#endif
203}
204
205static int qmgr_init(void)
206{
207 int i, err;
208 mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
209 IXP4XX_QMGR_REGION_SIZE,
210 "IXP4xx Queue Manager");
211 if (mem_res == NULL)
212 return -EBUSY;
213
214 qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
215 if (qmgr_regs == NULL) {
216 err = -ENOMEM;
217 goto error_map;
218 }
219
220 /* reset qmgr registers */
221 for (i = 0; i < 4; i++) {
222 __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
223 __raw_writel(0, &qmgr_regs->irqsrc[i]);
224 }
225 for (i = 0; i < 2; i++) {
226 __raw_writel(0, &qmgr_regs->stat2[i]);
227 __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
228 __raw_writel(0, &qmgr_regs->irqen[i]);
229 }
230
231 for (i = 0; i < QUEUES; i++)
232 __raw_writel(0, &qmgr_regs->sram[i]);
233
234 err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0,
235 "IXP4xx Queue Manager", NULL);
236 if (err) {
237 printk(KERN_ERR "qmgr: failed to request IRQ%i\n",
238 IRQ_IXP4XX_QM1);
239 goto error_irq;
240 }
241
242 used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
243 spin_lock_init(&qmgr_lock);
244
245 printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
246 return 0;
247
248error_irq:
249 iounmap(qmgr_regs);
250error_map:
251 release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
252 return err;
253}
254
255static void qmgr_remove(void)
256{
257 free_irq(IRQ_IXP4XX_QM1, NULL);
258 synchronize_irq(IRQ_IXP4XX_QM1);
259 iounmap(qmgr_regs);
260 release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
261}
262
263module_init(qmgr_init);
264module_exit(qmgr_remove);
265
266MODULE_LICENSE("GPL v2");
267MODULE_AUTHOR("Krzysztof Halasa");
268
269EXPORT_SYMBOL(qmgr_regs);
270EXPORT_SYMBOL(qmgr_set_irq);
271EXPORT_SYMBOL(qmgr_enable_irq);
272EXPORT_SYMBOL(qmgr_disable_irq);
273EXPORT_SYMBOL(qmgr_request_queue);
274EXPORT_SYMBOL(qmgr_release_queue);
diff --git a/arch/arm/mach-ixp4xx/nas100d-power.c b/arch/arm/mach-ixp4xx/nas100d-power.c
deleted file mode 100644
index 29aa98d3a7fa..000000000000
--- a/arch/arm/mach-ixp4xx/nas100d-power.c
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/nas100d-power.c
3 *
4 * NAS 100d Power/Reset driver
5 *
6 * Copyright (C) 2005 Tower Technologies
7 *
8 * based on nas100d-io.c
9 * Copyright (C) 2004 Karen Spearel
10 *
11 * Author: Alessandro Zummo <a.zummo@towertech.it>
12 * Maintainers: http://www.nslu2-linux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/module.h>
23#include <linux/reboot.h>
24
25#include <asm/mach-types.h>
26
27static irqreturn_t nas100d_reset_handler(int irq, void *dev_id)
28{
29 /* Signal init to do the ctrlaltdel action, this will bypass init if
30 * it hasn't started and do a kernel_restart.
31 */
32 ctrl_alt_del();
33
34 return IRQ_HANDLED;
35}
36
37static int __init nas100d_power_init(void)
38{
39 if (!(machine_is_nas100d()))
40 return 0;
41
42 set_irq_type(NAS100D_RB_IRQ, IRQT_LOW);
43
44 if (request_irq(NAS100D_RB_IRQ, &nas100d_reset_handler,
45 IRQF_DISABLED, "NAS100D reset button", NULL) < 0) {
46
47 printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
48 NAS100D_RB_IRQ);
49
50 return -EIO;
51 }
52
53 return 0;
54}
55
56static void __exit nas100d_power_exit(void)
57{
58 if (!(machine_is_nas100d()))
59 return;
60
61 free_irq(NAS100D_RB_IRQ, NULL);
62}
63
64module_init(nas100d_power_init);
65module_exit(nas100d_power_exit);
66
67MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
68MODULE_DESCRIPTION("NAS100D Power/Reset driver");
69MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index 54d884fb2517..4cecae84837b 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -3,8 +3,14 @@
3 * 3 *
4 * NAS 100d board-setup 4 * NAS 100d board-setup
5 * 5 *
6 * based ixdp425-setup.c: 6 * Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
7 *
8 * based on ixdp425-setup.c:
7 * Copyright (C) 2003-2004 MontaVista Software, Inc. 9 * Copyright (C) 2003-2004 MontaVista Software, Inc.
10 * based on nas100d-power.c:
11 * Copyright (C) 2005 Tower Technologies
12 * based on nas100d-io.c
13 * Copyright (C) 2004 Karen Spearel
8 * 14 *
9 * Author: Alessandro Zummo <a.zummo@towertech.it> 15 * Author: Alessandro Zummo <a.zummo@towertech.it>
10 * Author: Rod Whitby <rod@whitby.id.au> 16 * Author: Rod Whitby <rod@whitby.id.au>
@@ -12,15 +18,22 @@
12 * 18 *
13 */ 19 */
14 20
15#include <linux/kernel.h> 21#include <linux/if_ether.h>
22#include <linux/irq.h>
23#include <linux/jiffies.h>
24#include <linux/timer.h>
16#include <linux/serial.h> 25#include <linux/serial.h>
17#include <linux/serial_8250.h> 26#include <linux/serial_8250.h>
18#include <linux/leds.h> 27#include <linux/leds.h>
28#include <linux/reboot.h>
29#include <linux/i2c.h>
19#include <linux/i2c-gpio.h> 30#include <linux/i2c-gpio.h>
20 31
21#include <asm/mach-types.h> 32#include <asm/mach-types.h>
22#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
23#include <asm/mach/flash.h> 34#include <asm/mach/flash.h>
35#include <asm/io.h>
36#include <asm/gpio.h>
24 37
25static struct flash_platform_data nas100d_flash_data = { 38static struct flash_platform_data nas100d_flash_data = {
26 .map_name = "cfi_probe", 39 .map_name = "cfi_probe",
@@ -39,35 +52,40 @@ static struct platform_device nas100d_flash = {
39 .resource = &nas100d_flash_resource, 52 .resource = &nas100d_flash_resource,
40}; 53};
41 54
42#ifdef CONFIG_LEDS_IXP4XX 55static struct i2c_board_info __initdata nas100d_i2c_board_info [] = {
43static struct resource nas100d_led_resources[] = { 56 {
57 I2C_BOARD_INFO("rtc-pcf8563", 0x51),
58 },
59};
60
61static struct gpio_led nas100d_led_pins[] = {
44 { 62 {
45 .name = "wlan", /* green led */ 63 .name = "wlan", /* green led */
46 .start = 0, 64 .gpio = NAS100D_LED_WLAN_GPIO,
47 .end = 0, 65 .active_low = true,
48 .flags = IXP4XX_GPIO_LOW,
49 }, 66 },
50 { 67 {
51 .name = "ready", /* blue power led (off is flashing!) */ 68 .name = "power", /* blue power led (off=flashing) */
52 .start = 15, 69 .gpio = NAS100D_LED_PWR_GPIO,
53 .end = 15, 70 .active_low = true,
54 .flags = IXP4XX_GPIO_LOW,
55 }, 71 },
56 { 72 {
57 .name = "disk", /* yellow led */ 73 .name = "disk", /* yellow led */
58 .start = 3, 74 .gpio = NAS100D_LED_DISK_GPIO,
59 .end = 3, 75 .active_low = true,
60 .flags = IXP4XX_GPIO_LOW,
61 }, 76 },
62}; 77};
63 78
79static struct gpio_led_platform_data nas100d_led_data = {
80 .num_leds = ARRAY_SIZE(nas100d_led_pins),
81 .leds = nas100d_led_pins,
82};
83
64static struct platform_device nas100d_leds = { 84static struct platform_device nas100d_leds = {
65 .name = "IXP4XX-GPIO-LED", 85 .name = "leds-gpio",
66 .id = -1, 86 .id = -1,
67 .num_resources = ARRAY_SIZE(nas100d_led_resources), 87 .dev.platform_data = &nas100d_led_data,
68 .resource = nas100d_led_resources,
69}; 88};
70#endif
71 89
72static struct i2c_gpio_platform_data nas100d_i2c_gpio_data = { 90static struct i2c_gpio_platform_data nas100d_i2c_gpio_data = {
73 .sda_pin = NAS100D_SDA_PIN, 91 .sda_pin = NAS100D_SDA_PIN,
@@ -125,12 +143,28 @@ static struct platform_device nas100d_uart = {
125 .resource = nas100d_uart_resources, 143 .resource = nas100d_uart_resources,
126}; 144};
127 145
146/* Built-in 10/100 Ethernet MAC interfaces */
147static struct eth_plat_info nas100d_plat_eth[] = {
148 {
149 .phy = 0,
150 .rxq = 3,
151 .txreadyq = 20,
152 }
153};
154
155static struct platform_device nas100d_eth[] = {
156 {
157 .name = "ixp4xx_eth",
158 .id = IXP4XX_ETH_NPEB,
159 .dev.platform_data = nas100d_plat_eth,
160 }
161};
162
128static struct platform_device *nas100d_devices[] __initdata = { 163static struct platform_device *nas100d_devices[] __initdata = {
129 &nas100d_i2c_gpio, 164 &nas100d_i2c_gpio,
130 &nas100d_flash, 165 &nas100d_flash,
131#ifdef CONFIG_LEDS_IXP4XX
132 &nas100d_leds, 166 &nas100d_leds,
133#endif 167 &nas100d_eth[0],
134}; 168};
135 169
136static void nas100d_power_off(void) 170static void nas100d_power_off(void)
@@ -144,8 +178,63 @@ static void nas100d_power_off(void)
144 gpio_line_set(NAS100D_PO_GPIO, IXP4XX_GPIO_HIGH); 178 gpio_line_set(NAS100D_PO_GPIO, IXP4XX_GPIO_HIGH);
145} 179}
146 180
181/* This is used to make sure the power-button pusher is serious. The button
182 * must be held until the value of this counter reaches zero.
183 */
184static int power_button_countdown;
185
186/* Must hold the button down for at least this many counts to be processed */
187#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */
188
189static void nas100d_power_handler(unsigned long data);
190static DEFINE_TIMER(nas100d_power_timer, nas100d_power_handler, 0, 0);
191
192static void nas100d_power_handler(unsigned long data)
193{
194 /* This routine is called twice per second to check the
195 * state of the power button.
196 */
197
198 if (gpio_get_value(NAS100D_PB_GPIO)) {
199
200 /* IO Pin is 1 (button pushed) */
201 if (power_button_countdown > 0)
202 power_button_countdown--;
203
204 } else {
205
206 /* Done on button release, to allow for auto-power-on mods. */
207 if (power_button_countdown == 0) {
208 /* Signal init to do the ctrlaltdel action,
209 * this will bypass init if it hasn't started
210 * and do a kernel_restart.
211 */
212 ctrl_alt_del();
213
214 /* Change the state of the power LED to "blink" */
215 gpio_line_set(NAS100D_LED_PWR_GPIO, IXP4XX_GPIO_LOW);
216 } else {
217 power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
218 }
219 }
220
221 mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500));
222}
223
224static irqreturn_t nas100d_reset_handler(int irq, void *dev_id)
225{
226 /* This is the paper-clip reset, it shuts the machine down directly. */
227 machine_power_off();
228
229 return IRQ_HANDLED;
230}
231
147static void __init nas100d_init(void) 232static void __init nas100d_init(void)
148{ 233{
234 DECLARE_MAC_BUF(mac_buf);
235 uint8_t __iomem *f;
236 int i;
237
149 ixp4xx_sys_init(); 238 ixp4xx_sys_init();
150 239
151 /* gpio 14 and 15 are _not_ clocks */ 240 /* gpio 14 and 15 are _not_ clocks */
@@ -155,7 +244,8 @@ static void __init nas100d_init(void)
155 nas100d_flash_resource.end = 244 nas100d_flash_resource.end =
156 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; 245 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
157 246
158 pm_power_off = nas100d_power_off; 247 i2c_register_board_info(0, nas100d_i2c_board_info,
248 ARRAY_SIZE(nas100d_i2c_board_info));
159 249
160 /* 250 /*
161 * This is only useful on a modified machine, but it is valuable 251 * This is only useful on a modified machine, but it is valuable
@@ -165,6 +255,48 @@ static void __init nas100d_init(void)
165 (void)platform_device_register(&nas100d_uart); 255 (void)platform_device_register(&nas100d_uart);
166 256
167 platform_add_devices(nas100d_devices, ARRAY_SIZE(nas100d_devices)); 257 platform_add_devices(nas100d_devices, ARRAY_SIZE(nas100d_devices));
258
259 pm_power_off = nas100d_power_off;
260
261 if (request_irq(gpio_to_irq(NAS100D_RB_GPIO), &nas100d_reset_handler,
262 IRQF_DISABLED | IRQF_TRIGGER_LOW,
263 "NAS100D reset button", NULL) < 0) {
264
265 printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
266 gpio_to_irq(NAS100D_RB_GPIO));
267 }
268
269 /* The power button on the Iomega NAS100d is on GPIO 14, but
270 * it cannot handle interrupts on that GPIO line. So we'll
271 * have to poll it with a kernel timer.
272 */
273
274 /* Make sure that the power button GPIO is set up as an input */
275 gpio_line_config(NAS100D_PB_GPIO, IXP4XX_GPIO_IN);
276
277 /* Set the initial value for the power button IRQ handler */
278 power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
279
280 mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500));
281
282 /*
283 * Map in a portion of the flash and read the MAC address.
284 * Since it is stored in BE in the flash itself, we need to
285 * byteswap it if we're in LE mode.
286 */
287 f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x1000000);
288 if (f) {
289 for (i = 0; i < 6; i++)
290#ifdef __ARMEB__
291 nas100d_plat_eth[0].hwaddr[i] = readb(f + 0xFC0FD8 + i);
292#else
293 nas100d_plat_eth[0].hwaddr[i] = readb(f + 0xFC0FD8 + (i^3));
294#endif
295 iounmap(f);
296 }
297 printk(KERN_INFO "NAS100D: Using MAC address %s for port 0\n",
298 print_mac(mac_buf, nas100d_plat_eth[0].hwaddr));
299
168} 300}
169 301
170MACHINE_START(NAS100D, "Iomega NAS 100d") 302MACHINE_START(NAS100D, "Iomega NAS 100d")
diff --git a/arch/arm/mach-ixp4xx/nslu2-power.c b/arch/arm/mach-ixp4xx/nslu2-power.c
deleted file mode 100644
index 6f10dc208320..000000000000
--- a/arch/arm/mach-ixp4xx/nslu2-power.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/nslu2-power.c
3 *
4 * NSLU2 Power/Reset driver
5 *
6 * Copyright (C) 2005 Tower Technologies
7 *
8 * based on nslu2-io.c
9 * Copyright (C) 2004 Karen Spearel
10 *
11 * Author: Alessandro Zummo <a.zummo@towertech.it>
12 * Maintainers: http://www.nslu2-linux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/reboot.h>
22#include <linux/irq.h>
23#include <linux/interrupt.h>
24
25#include <asm/mach-types.h>
26
27static irqreturn_t nslu2_power_handler(int irq, void *dev_id)
28{
29 /* Signal init to do the ctrlaltdel action, this will bypass init if
30 * it hasn't started and do a kernel_restart.
31 */
32 ctrl_alt_del();
33
34 return IRQ_HANDLED;
35}
36
37static irqreturn_t nslu2_reset_handler(int irq, void *dev_id)
38{
39 /* This is the paper-clip reset, it shuts the machine down directly.
40 */
41 machine_power_off();
42
43 return IRQ_HANDLED;
44}
45
46static int __init nslu2_power_init(void)
47{
48 if (!(machine_is_nslu2()))
49 return 0;
50
51 *IXP4XX_GPIO_GPISR = 0x20400000; /* read the 2 irqs to clr */
52
53 set_irq_type(NSLU2_RB_IRQ, IRQT_LOW);
54 set_irq_type(NSLU2_PB_IRQ, IRQT_HIGH);
55
56 if (request_irq(NSLU2_RB_IRQ, &nslu2_reset_handler,
57 IRQF_DISABLED, "NSLU2 reset button", NULL) < 0) {
58
59 printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
60 NSLU2_RB_IRQ);
61
62 return -EIO;
63 }
64
65 if (request_irq(NSLU2_PB_IRQ, &nslu2_power_handler,
66 IRQF_DISABLED, "NSLU2 power button", NULL) < 0) {
67
68 printk(KERN_DEBUG "Power Button IRQ %d not available\n",
69 NSLU2_PB_IRQ);
70
71 return -EIO;
72 }
73
74 return 0;
75}
76
77static void __exit nslu2_power_exit(void)
78{
79 if (!(machine_is_nslu2()))
80 return;
81
82 free_irq(NSLU2_RB_IRQ, NULL);
83 free_irq(NSLU2_PB_IRQ, NULL);
84}
85
86module_init(nslu2_power_init);
87module_exit(nslu2_power_exit);
88
89MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
90MODULE_DESCRIPTION("NSLU2 Power/Reset driver");
91MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index 77277d27fcc5..acaebcbce53a 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -3,27 +3,35 @@
3 * 3 *
4 * NSLU2 board-setup 4 * NSLU2 board-setup
5 * 5 *
6 * based ixdp425-setup.c: 6 * Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
7 *
8 * based on ixdp425-setup.c:
7 * Copyright (C) 2003-2004 MontaVista Software, Inc. 9 * Copyright (C) 2003-2004 MontaVista Software, Inc.
10 * based on nslu2-power.c:
11 * Copyright (C) 2005 Tower Technologies
8 * 12 *
9 * Author: Mark Rakes <mrakes at mac.com> 13 * Author: Mark Rakes <mrakes at mac.com>
10 * Author: Rod Whitby <rod@whitby.id.au> 14 * Author: Rod Whitby <rod@whitby.id.au>
15 * Author: Alessandro Zummo <a.zummo@towertech.it>
11 * Maintainers: http://www.nslu2-linux.org/ 16 * Maintainers: http://www.nslu2-linux.org/
12 * 17 *
13 * Fixed missing init_time in MACHINE_START kas11 10/22/04
14 * Changed to conform to new style __init ixdp425 kas11 10/22/04
15 */ 18 */
16 19
17#include <linux/kernel.h> 20#include <linux/if_ether.h>
21#include <linux/irq.h>
18#include <linux/serial.h> 22#include <linux/serial.h>
19#include <linux/serial_8250.h> 23#include <linux/serial_8250.h>
20#include <linux/leds.h> 24#include <linux/leds.h>
25#include <linux/reboot.h>
26#include <linux/i2c.h>
21#include <linux/i2c-gpio.h> 27#include <linux/i2c-gpio.h>
22 28
23#include <asm/mach-types.h> 29#include <asm/mach-types.h>
24#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
25#include <asm/mach/flash.h> 31#include <asm/mach/flash.h>
26#include <asm/mach/time.h> 32#include <asm/mach/time.h>
33#include <asm/io.h>
34#include <asm/gpio.h>
27 35
28static struct flash_platform_data nslu2_flash_data = { 36static struct flash_platform_data nslu2_flash_data = {
29 .map_name = "cfi_probe", 37 .map_name = "cfi_probe",
@@ -47,41 +55,43 @@ static struct i2c_gpio_platform_data nslu2_i2c_gpio_data = {
47 .scl_pin = NSLU2_SCL_PIN, 55 .scl_pin = NSLU2_SCL_PIN,
48}; 56};
49 57
50#ifdef CONFIG_LEDS_IXP4XX 58static struct i2c_board_info __initdata nslu2_i2c_board_info [] = {
51static struct resource nslu2_led_resources[] = { 59 {
60 I2C_BOARD_INFO("rtc-x1205", 0x6f),
61 },
62};
63
64static struct gpio_led nslu2_led_pins[] = {
52 { 65 {
53 .name = "ready", /* green led */ 66 .name = "ready", /* green led */
54 .start = NSLU2_LED_GRN_GPIO, 67 .gpio = NSLU2_LED_GRN_GPIO,
55 .end = NSLU2_LED_GRN_GPIO,
56 .flags = IXP4XX_GPIO_HIGH,
57 }, 68 },
58 { 69 {
59 .name = "status", /* red led */ 70 .name = "status", /* red led */
60 .start = NSLU2_LED_RED_GPIO, 71 .gpio = NSLU2_LED_RED_GPIO,
61 .end = NSLU2_LED_RED_GPIO,
62 .flags = IXP4XX_GPIO_HIGH,
63 }, 72 },
64 { 73 {
65 .name = "disk-1", 74 .name = "disk-1",
66 .start = NSLU2_LED_DISK1_GPIO, 75 .gpio = NSLU2_LED_DISK1_GPIO,
67 .end = NSLU2_LED_DISK1_GPIO, 76 .active_low = true,
68 .flags = IXP4XX_GPIO_LOW,
69 }, 77 },
70 { 78 {
71 .name = "disk-2", 79 .name = "disk-2",
72 .start = NSLU2_LED_DISK2_GPIO, 80 .gpio = NSLU2_LED_DISK2_GPIO,
73 .end = NSLU2_LED_DISK2_GPIO, 81 .active_low = true,
74 .flags = IXP4XX_GPIO_LOW,
75 }, 82 },
76}; 83};
77 84
85static struct gpio_led_platform_data nslu2_led_data = {
86 .num_leds = ARRAY_SIZE(nslu2_led_pins),
87 .leds = nslu2_led_pins,
88};
89
78static struct platform_device nslu2_leds = { 90static struct platform_device nslu2_leds = {
79 .name = "IXP4XX-GPIO-LED", 91 .name = "leds-gpio",
80 .id = -1, 92 .id = -1,
81 .num_resources = ARRAY_SIZE(nslu2_led_resources), 93 .dev.platform_data = &nslu2_led_data,
82 .resource = nslu2_led_resources,
83}; 94};
84#endif
85 95
86static struct platform_device nslu2_i2c_gpio = { 96static struct platform_device nslu2_i2c_gpio = {
87 .name = "i2c-gpio", 97 .name = "i2c-gpio",
@@ -140,13 +150,29 @@ static struct platform_device nslu2_uart = {
140 .resource = nslu2_uart_resources, 150 .resource = nslu2_uart_resources,
141}; 151};
142 152
153/* Built-in 10/100 Ethernet MAC interfaces */
154static struct eth_plat_info nslu2_plat_eth[] = {
155 {
156 .phy = 1,
157 .rxq = 3,
158 .txreadyq = 20,
159 }
160};
161
162static struct platform_device nslu2_eth[] = {
163 {
164 .name = "ixp4xx_eth",
165 .id = IXP4XX_ETH_NPEB,
166 .dev.platform_data = nslu2_plat_eth,
167 }
168};
169
143static struct platform_device *nslu2_devices[] __initdata = { 170static struct platform_device *nslu2_devices[] __initdata = {
144 &nslu2_i2c_gpio, 171 &nslu2_i2c_gpio,
145 &nslu2_flash, 172 &nslu2_flash,
146 &nslu2_beeper, 173 &nslu2_beeper,
147#ifdef CONFIG_LEDS_IXP4XX
148 &nslu2_leds, 174 &nslu2_leds,
149#endif 175 &nslu2_eth[0],
150}; 176};
151 177
152static void nslu2_power_off(void) 178static void nslu2_power_off(void)
@@ -160,6 +186,25 @@ static void nslu2_power_off(void)
160 gpio_line_set(NSLU2_PO_GPIO, IXP4XX_GPIO_HIGH); 186 gpio_line_set(NSLU2_PO_GPIO, IXP4XX_GPIO_HIGH);
161} 187}
162 188
189static irqreturn_t nslu2_power_handler(int irq, void *dev_id)
190{
191 /* Signal init to do the ctrlaltdel action, this will bypass init if
192 * it hasn't started and do a kernel_restart.
193 */
194 ctrl_alt_del();
195
196 return IRQ_HANDLED;
197}
198
199static irqreturn_t nslu2_reset_handler(int irq, void *dev_id)
200{
201 /* This is the paper-clip reset, it shuts the machine down directly.
202 */
203 machine_power_off();
204
205 return IRQ_HANDLED;
206}
207
163static void __init nslu2_timer_init(void) 208static void __init nslu2_timer_init(void)
164{ 209{
165 /* The xtal on this machine is non-standard. */ 210 /* The xtal on this machine is non-standard. */
@@ -175,13 +220,18 @@ static struct sys_timer nslu2_timer = {
175 220
176static void __init nslu2_init(void) 221static void __init nslu2_init(void)
177{ 222{
223 DECLARE_MAC_BUF(mac_buf);
224 uint8_t __iomem *f;
225 int i;
226
178 ixp4xx_sys_init(); 227 ixp4xx_sys_init();
179 228
180 nslu2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); 229 nslu2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
181 nslu2_flash_resource.end = 230 nslu2_flash_resource.end =
182 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; 231 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
183 232
184 pm_power_off = nslu2_power_off; 233 i2c_register_board_info(0, nslu2_i2c_board_info,
234 ARRAY_SIZE(nslu2_i2c_board_info));
185 235
186 /* 236 /*
187 * This is only useful on a modified machine, but it is valuable 237 * This is only useful on a modified machine, but it is valuable
@@ -191,6 +241,43 @@ static void __init nslu2_init(void)
191 (void)platform_device_register(&nslu2_uart); 241 (void)platform_device_register(&nslu2_uart);
192 242
193 platform_add_devices(nslu2_devices, ARRAY_SIZE(nslu2_devices)); 243 platform_add_devices(nslu2_devices, ARRAY_SIZE(nslu2_devices));
244
245 pm_power_off = nslu2_power_off;
246
247 if (request_irq(gpio_to_irq(NSLU2_RB_GPIO), &nslu2_reset_handler,
248 IRQF_DISABLED | IRQF_TRIGGER_LOW,
249 "NSLU2 reset button", NULL) < 0) {
250
251 printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
252 gpio_to_irq(NSLU2_RB_GPIO));
253 }
254
255 if (request_irq(gpio_to_irq(NSLU2_PB_GPIO), &nslu2_power_handler,
256 IRQF_DISABLED | IRQF_TRIGGER_HIGH,
257 "NSLU2 power button", NULL) < 0) {
258
259 printk(KERN_DEBUG "Power Button IRQ %d not available\n",
260 gpio_to_irq(NSLU2_PB_GPIO));
261 }
262
263 /*
264 * Map in a portion of the flash and read the MAC address.
265 * Since it is stored in BE in the flash itself, we need to
266 * byteswap it if we're in LE mode.
267 */
268 f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x40000);
269 if (f) {
270 for (i = 0; i < 6; i++)
271#ifdef __ARMEB__
272 nslu2_plat_eth[0].hwaddr[i] = readb(f + 0x3FFB0 + i);
273#else
274 nslu2_plat_eth[0].hwaddr[i] = readb(f + 0x3FFB0 + (i^3));
275#endif
276 iounmap(f);
277 }
278 printk(KERN_INFO "NSLU2: Using MAC address %s for port 0\n",
279 print_mac(mac_buf, nslu2_plat_eth[0].hwaddr));
280
194} 281}
195 282
196MACHINE_START(NSLU2, "Linksys NSLU2") 283MACHINE_START(NSLU2, "Linksys NSLU2")
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index b5c916c0747d..8604938bd948 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -6,7 +6,7 @@
6obj-y += clock.o devices.o generic.o irq.o dma.o time.o 6obj-y += clock.o devices.o generic.o irq.o dma.o time.o
7obj-$(CONFIG_PXA25x) += pxa25x.o 7obj-$(CONFIG_PXA25x) += pxa25x.o
8obj-$(CONFIG_PXA27x) += pxa27x.o 8obj-$(CONFIG_PXA27x) += pxa27x.o
9obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o 9obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o smemc.o
10obj-$(CONFIG_CPU_PXA300) += pxa300.o 10obj-$(CONFIG_CPU_PXA300) += pxa300.o
11obj-$(CONFIG_CPU_PXA320) += pxa320.o 11obj-$(CONFIG_CPU_PXA320) += pxa320.o
12 12
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index 28cfd71c032d..6012177a29a3 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -29,6 +29,7 @@
29#include <asm/mach/map.h> 29#include <asm/mach/map.h>
30 30
31#include <asm/arch/pxa-regs.h> 31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/pxa2xx-regs.h>
32#include <asm/arch/pxafb.h> 33#include <asm/arch/pxafb.h>
33#include <asm/arch/ohci.h> 34#include <asm/arch/ohci.h>
34#include <asm/arch/mmc.h> 35#include <asm/arch/mmc.h>
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 50ff453ad370..bfccb80ac8ef 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -10,6 +10,7 @@
10#include <asm/arch/mmc.h> 10#include <asm/arch/mmc.h>
11#include <asm/arch/irda.h> 11#include <asm/arch/irda.h>
12#include <asm/arch/i2c.h> 12#include <asm/arch/i2c.h>
13#include <asm/arch/ohci.h>
13 14
14#include "devices.h" 15#include "devices.h"
15 16
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 698aeec52961..76970598f550 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -23,6 +23,7 @@
23#include <linux/ioport.h> 23#include <linux/ioport.h>
24#include <linux/pm.h> 24#include <linux/pm.h>
25#include <linux/string.h> 25#include <linux/string.h>
26#include <linux/sysdev.h>
26 27
27#include <asm/hardware.h> 28#include <asm/hardware.h>
28#include <asm/irq.h> 29#include <asm/irq.h>
@@ -226,3 +227,59 @@ void __init pxa_map_io(void)
226 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 227 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
227 get_clk_frequency_khz(1); 228 get_clk_frequency_khz(1);
228} 229}
230
231#ifdef CONFIG_PM
232
233static unsigned long saved_gplr[4];
234static unsigned long saved_gpdr[4];
235static unsigned long saved_grer[4];
236static unsigned long saved_gfer[4];
237
238static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
239{
240 int i, gpio;
241
242 for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
243 saved_gplr[i] = GPLR(gpio);
244 saved_gpdr[i] = GPDR(gpio);
245 saved_grer[i] = GRER(gpio);
246 saved_gfer[i] = GFER(gpio);
247
248 /* Clear GPIO transition detect bits */
249 GEDR(gpio) = GEDR(gpio);
250 }
251 return 0;
252}
253
254static int pxa_gpio_resume(struct sys_device *dev)
255{
256 int i, gpio;
257
258 for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
259 /* restore level with set/clear */
260 GPSR(gpio) = saved_gplr[i];
261 GPCR(gpio) = ~saved_gplr[i];
262
263 GRER(gpio) = saved_grer[i];
264 GFER(gpio) = saved_gfer[i];
265 GPDR(gpio) = saved_gpdr[i];
266 }
267 return 0;
268}
269#else
270#define pxa_gpio_suspend NULL
271#define pxa_gpio_resume NULL
272#endif
273
274struct sysdev_class pxa_gpio_sysclass = {
275 .name = "gpio",
276 .suspend = pxa_gpio_suspend,
277 .resume = pxa_gpio_resume,
278};
279
280static int __init pxa_gpio_init(void)
281{
282 return sysdev_class_register(&pxa_gpio_sysclass);
283}
284
285core_initcall(pxa_gpio_init);
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index b30f240a16c7..1a16ad3ecee6 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -52,3 +52,6 @@ extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
52#define pxa3xx_get_clk_frequency_khz(x) (0) 52#define pxa3xx_get_clk_frequency_khz(x) (0)
53#define pxa3xx_get_memclk_frequency_10khz() (0) 53#define pxa3xx_get_memclk_frequency_10khz() (0)
54#endif 54#endif
55
56extern struct sysdev_class pxa_irq_sysclass;
57extern struct sysdev_class pxa_gpio_sysclass;
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 07acb45b16ea..5a1d5eef10a4 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/sysdev.h>
18 19
19#include <asm/hardware.h> 20#include <asm/hardware.h>
20#include <asm/irq.h> 21#include <asm/irq.h>
@@ -321,3 +322,64 @@ void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
321 pxa_low_gpio_chip.set_wake = set_wake; 322 pxa_low_gpio_chip.set_wake = set_wake;
322 pxa_muxed_gpio_chip.set_wake = set_wake; 323 pxa_muxed_gpio_chip.set_wake = set_wake;
323} 324}
325
326#ifdef CONFIG_PM
327static unsigned long saved_icmr[2];
328
329static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
330{
331 switch (dev->id) {
332 case 0:
333 saved_icmr[0] = ICMR;
334 ICMR = 0;
335 break;
336#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
337 case 1:
338 saved_icmr[1] = ICMR2;
339 ICMR2 = 0;
340 break;
341#endif
342 default:
343 return -EINVAL;
344 }
345
346 return 0;
347}
348
349static int pxa_irq_resume(struct sys_device *dev)
350{
351 switch (dev->id) {
352 case 0:
353 ICMR = saved_icmr[0];
354 ICLR = 0;
355 ICCR = 1;
356 break;
357#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
358 case 1:
359 ICMR2 = saved_icmr[1];
360 ICLR2 = 0;
361 break;
362#endif
363 default:
364 return -EINVAL;
365 }
366
367 return 0;
368}
369#else
370#define pxa_irq_suspend NULL
371#define pxa_irq_resume NULL
372#endif
373
374struct sysdev_class pxa_irq_sysclass = {
375 .name = "irq",
376 .suspend = pxa_irq_suspend,
377 .resume = pxa_irq_resume,
378};
379
380static int __init pxa_irq_init(void)
381{
382 return sysdev_class_register(&pxa_irq_sysclass);
383}
384
385core_initcall(pxa_irq_init);
diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp.c
index ec1b2d8f61c4..f5809adce298 100644
--- a/arch/arm/mach-pxa/mfp.c
+++ b/arch/arm/mach-pxa/mfp.c
@@ -22,6 +22,7 @@
22#include <asm/hardware.h> 22#include <asm/hardware.h>
23#include <asm/arch/mfp.h> 23#include <asm/arch/mfp.h>
24#include <asm/arch/mfp-pxa3xx.h> 24#include <asm/arch/mfp-pxa3xx.h>
25#include <asm/arch/pxa3xx-regs.h>
25 26
26/* mfp_spin_lock is used to ensure that MFP register configuration 27/* mfp_spin_lock is used to ensure that MFP register configuration
27 * (most likely a read-modify-write operation) is atomic, and that 28 * (most likely a read-modify-write operation) is atomic, and that
@@ -223,11 +224,19 @@ static int pxa3xx_mfp_resume(struct sys_device *d)
223 struct pxa3xx_mfp_pin *p = &mfp_table[pin]; 224 struct pxa3xx_mfp_pin *p = &mfp_table[pin];
224 __mfp_config_run(p); 225 __mfp_config_run(p);
225 } 226 }
227
228 /* clear RDH bit when MFP settings are restored
229 *
230 * NOTE: the last 3 bits DxS are write-1-to-clear so carefully
231 * preserve them here in case they will be referenced later
232 */
233 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
234
226 return 0; 235 return 0;
227} 236}
228 237
229static struct sysdev_class mfp_sysclass = { 238static struct sysdev_class mfp_sysclass = {
230 set_kset_name("mfp"), 239 .name = "mfp",
231 .suspend = pxa3xx_mfp_suspend, 240 .suspend = pxa3xx_mfp_suspend,
232 .resume = pxa3xx_mfp_resume, 241 .resume = pxa3xx_mfp_resume,
233}; 242};
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 540c3bba5f9a..c14696b9979d 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -29,6 +29,7 @@
29#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
30#include <asm/arch/hardware.h> 30#include <asm/arch/hardware.h>
31#include <asm/arch/pxa-regs.h> 31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/pxa2xx-regs.h>
32#include <asm/arch/pxa2xx_spi.h> 33#include <asm/arch/pxa2xx_spi.h>
33#include <asm/arch/pcm027.h> 34#include <asm/arch/pcm027.h>
34#include "generic.h" 35#include "generic.h"
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index dd54496083cb..209eabf0ed3e 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -164,7 +164,7 @@ static struct resource poodlets_resources[] = {
164 }, 164 },
165}; 165};
166 166
167static unsigned long poodle_get_hsync_len(void) 167static unsigned long poodle_get_hsync_invperiod(void)
168{ 168{
169 return 0; 169 return 0;
170} 170}
@@ -174,9 +174,9 @@ static void poodle_null_hsync(void)
174} 174}
175 175
176static struct corgits_machinfo poodle_ts_machinfo = { 176static struct corgits_machinfo poodle_ts_machinfo = {
177 .get_hsync_len = poodle_get_hsync_len, 177 .get_hsync_invperiod = poodle_get_hsync_invperiod,
178 .put_hsync = poodle_null_hsync, 178 .put_hsync = poodle_null_hsync,
179 .wait_hsync = poodle_null_hsync, 179 .wait_hsync = poodle_null_hsync,
180}; 180};
181 181
182static struct platform_device poodle_ts_device = { 182static struct platform_device poodle_ts_device = {
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index ddd05bf78e02..599e53fcc2c5 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/suspend.h> 23#include <linux/suspend.h>
24#include <linux/sysdev.h>
24 25
25#include <asm/hardware.h> 26#include <asm/hardware.h>
26#include <asm/arch/irqs.h> 27#include <asm/arch/irqs.h>
@@ -141,11 +142,6 @@ static struct clk pxa25x_clks[] = {
141#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 142#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
142#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 143#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
143 144
144#define RESTORE_GPLEVEL(n) do { \
145 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
146 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
147} while (0)
148
149/* 145/*
150 * List of global PXA peripheral registers to preserve. 146 * List of global PXA peripheral registers to preserve.
151 * More ones like CP and general purpose register values are preserved 147 * More ones like CP and general purpose register values are preserved
@@ -153,10 +149,6 @@ static struct clk pxa25x_clks[] = {
153 */ 149 */
154enum { SLEEP_SAVE_START = 0, 150enum { SLEEP_SAVE_START = 0,
155 151
156 SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2,
157 SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
158 SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
159 SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
160 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, 152 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
161 153
162 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 154 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
@@ -165,7 +157,6 @@ enum { SLEEP_SAVE_START = 0,
165 157
166 SLEEP_SAVE_PSTR, 158 SLEEP_SAVE_PSTR,
167 159
168 SLEEP_SAVE_ICMR,
169 SLEEP_SAVE_CKEN, 160 SLEEP_SAVE_CKEN,
170 161
171 SLEEP_SAVE_SIZE 162 SLEEP_SAVE_SIZE
@@ -174,17 +165,12 @@ enum { SLEEP_SAVE_START = 0,
174 165
175static void pxa25x_cpu_pm_save(unsigned long *sleep_save) 166static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
176{ 167{
177 SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
178 SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
179 SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
180 SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
181 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); 168 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
182 169
183 SAVE(GAFR0_L); SAVE(GAFR0_U); 170 SAVE(GAFR0_L); SAVE(GAFR0_U);
184 SAVE(GAFR1_L); SAVE(GAFR1_U); 171 SAVE(GAFR1_L); SAVE(GAFR1_U);
185 SAVE(GAFR2_L); SAVE(GAFR2_U); 172 SAVE(GAFR2_L); SAVE(GAFR2_U);
186 173
187 SAVE(ICMR); ICMR = 0;
188 SAVE(CKEN); 174 SAVE(CKEN);
189 SAVE(PSTR); 175 SAVE(PSTR);
190 176
@@ -198,22 +184,14 @@ static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
198 PSPR = 0; 184 PSPR = 0;
199 185
200 /* restore registers */ 186 /* restore registers */
201 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
202 RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
203 RESTORE(GAFR0_L); RESTORE(GAFR0_U); 187 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
204 RESTORE(GAFR1_L); RESTORE(GAFR1_U); 188 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
205 RESTORE(GAFR2_L); RESTORE(GAFR2_U); 189 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
206 RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
207 RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
208 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); 190 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
209 191
210 PSSR = PSSR_RDH | PSSR_PH; 192 PSSR = PSSR_RDH | PSSR_PH;
211 193
212 RESTORE(CKEN); 194 RESTORE(CKEN);
213
214 ICLR = 0;
215 ICCR = 1;
216 RESTORE(ICMR);
217 RESTORE(PSTR); 195 RESTORE(PSTR);
218} 196}
219 197
@@ -304,9 +282,17 @@ static struct platform_device *pxa25x_devices[] __initdata = {
304 &pxa25x_device_assp, 282 &pxa25x_device_assp,
305}; 283};
306 284
285static struct sys_device pxa25x_sysdev[] = {
286 {
287 .cls = &pxa_irq_sysclass,
288 }, {
289 .cls = &pxa_gpio_sysclass,
290 },
291};
292
307static int __init pxa25x_init(void) 293static int __init pxa25x_init(void)
308{ 294{
309 int ret = 0; 295 int i, ret = 0;
310 296
311 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 297 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
312 if (cpu_is_pxa25x()) 298 if (cpu_is_pxa25x())
@@ -320,9 +306,18 @@ static int __init pxa25x_init(void)
320 306
321 pxa25x_init_pm(); 307 pxa25x_init_pm();
322 308
309 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
310 ret = sysdev_register(&pxa25x_sysdev[i]);
311 if (ret)
312 pr_err("failed to register sysdev[%d]\n", i);
313 }
314
323 ret = platform_add_devices(pxa25x_devices, 315 ret = platform_add_devices(pxa25x_devices,
324 ARRAY_SIZE(pxa25x_devices)); 316 ARRAY_SIZE(pxa25x_devices));
317 if (ret)
318 return ret;
325 } 319 }
320
326 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 321 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
327 if (cpu_is_pxa25x()) 322 if (cpu_is_pxa25x())
328 ret = platform_device_register(&pxa_device_hwuart); 323 ret = platform_device_register(&pxa_device_hwuart);
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 96cf274ec7cb..46a951c3e5a0 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -16,6 +16,7 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/suspend.h> 17#include <linux/suspend.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/sysdev.h>
19 20
20#include <asm/hardware.h> 21#include <asm/hardware.h>
21#include <asm/irq.h> 22#include <asm/irq.h>
@@ -171,11 +172,6 @@ static struct clk pxa27x_clks[] = {
171#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 172#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
172#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 173#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
173 174
174#define RESTORE_GPLEVEL(n) do { \
175 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
176 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
177} while (0)
178
179/* 175/*
180 * List of global PXA peripheral registers to preserve. 176 * List of global PXA peripheral registers to preserve.
181 * More ones like CP and general purpose register values are preserved 177 * More ones like CP and general purpose register values are preserved
@@ -183,10 +179,6 @@ static struct clk pxa27x_clks[] = {
183 */ 179 */
184enum { SLEEP_SAVE_START = 0, 180enum { SLEEP_SAVE_START = 0,
185 181
186 SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
187 SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
188 SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
189 SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
190 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, 182 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
191 183
192 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 184 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
@@ -196,7 +188,6 @@ enum { SLEEP_SAVE_START = 0,
196 188
197 SLEEP_SAVE_PSTR, 189 SLEEP_SAVE_PSTR,
198 190
199 SLEEP_SAVE_ICMR,
200 SLEEP_SAVE_CKEN, 191 SLEEP_SAVE_CKEN,
201 192
202 SLEEP_SAVE_MDREFR, 193 SLEEP_SAVE_MDREFR,
@@ -208,10 +199,6 @@ enum { SLEEP_SAVE_START = 0,
208 199
209void pxa27x_cpu_pm_save(unsigned long *sleep_save) 200void pxa27x_cpu_pm_save(unsigned long *sleep_save)
210{ 201{
211 SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3);
212 SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3);
213 SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3);
214 SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3);
215 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3); 202 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
216 203
217 SAVE(GAFR0_L); SAVE(GAFR0_U); 204 SAVE(GAFR0_L); SAVE(GAFR0_U);
@@ -223,12 +210,8 @@ void pxa27x_cpu_pm_save(unsigned long *sleep_save)
223 SAVE(PWER); SAVE(PCFR); SAVE(PRER); 210 SAVE(PWER); SAVE(PCFR); SAVE(PRER);
224 SAVE(PFER); SAVE(PKWR); 211 SAVE(PFER); SAVE(PKWR);
225 212
226 SAVE(ICMR); ICMR = 0;
227 SAVE(CKEN); 213 SAVE(CKEN);
228 SAVE(PSTR); 214 SAVE(PSTR);
229
230 /* Clear GPIO transition detect bits */
231 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3;
232} 215}
233 216
234void pxa27x_cpu_pm_restore(unsigned long *sleep_save) 217void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
@@ -237,15 +220,10 @@ void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
237 PSPR = 0; 220 PSPR = 0;
238 221
239 /* restore registers */ 222 /* restore registers */
240 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1);
241 RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3);
242 RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3);
243 RESTORE(GAFR0_L); RESTORE(GAFR0_U); 223 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
244 RESTORE(GAFR1_L); RESTORE(GAFR1_U); 224 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
245 RESTORE(GAFR2_L); RESTORE(GAFR2_U); 225 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
246 RESTORE(GAFR3_L); RESTORE(GAFR3_U); 226 RESTORE(GAFR3_L); RESTORE(GAFR3_U);
247 RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3);
248 RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3);
249 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3); 227 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
250 228
251 RESTORE(MDREFR); 229 RESTORE(MDREFR);
@@ -256,9 +234,6 @@ void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
256 234
257 RESTORE(CKEN); 235 RESTORE(CKEN);
258 236
259 ICLR = 0;
260 ICCR = 1;
261 RESTORE(ICMR);
262 RESTORE(PSTR); 237 RESTORE(PSTR);
263} 238}
264 239
@@ -409,9 +384,22 @@ static struct platform_device *devices[] __initdata = {
409 &pxa27x_device_ssp3, 384 &pxa27x_device_ssp3,
410}; 385};
411 386
387static struct sys_device pxa27x_sysdev[] = {
388 {
389 .id = 0,
390 .cls = &pxa_irq_sysclass,
391 }, {
392 .id = 1,
393 .cls = &pxa_irq_sysclass,
394 }, {
395 .cls = &pxa_gpio_sysclass,
396 },
397};
398
412static int __init pxa27x_init(void) 399static int __init pxa27x_init(void)
413{ 400{
414 int ret = 0; 401 int i, ret = 0;
402
415 if (cpu_is_pxa27x()) { 403 if (cpu_is_pxa27x()) {
416 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); 404 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
417 405
@@ -420,8 +408,15 @@ static int __init pxa27x_init(void)
420 408
421 pxa27x_init_pm(); 409 pxa27x_init_pm();
422 410
411 for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
412 ret = sysdev_register(&pxa27x_sysdev[i]);
413 if (ret)
414 pr_err("failed to register sysdev[%d]\n", i);
415 }
416
423 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 417 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
424 } 418 }
419
425 return ret; 420 return ret;
426} 421}
427 422
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 5cbf057a1b32..e47e67c11afe 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -20,6 +20,7 @@
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/sysdev.h>
23 24
24#include <asm/hardware.h> 25#include <asm/hardware.h>
25#include <asm/arch/pxa3xx-regs.h> 26#include <asm/arch/pxa3xx-regs.h>
@@ -39,6 +40,7 @@
39#define RO_CLK 60000000 40#define RO_CLK 60000000
40 41
41#define ACCR_D0CS (1 << 26) 42#define ACCR_D0CS (1 << 26)
43#define ACCR_PCCE (1 << 11)
42 44
43/* crystal frequency to static memory controller multiplier (SMCFS) */ 45/* crystal frequency to static memory controller multiplier (SMCFS) */
44static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 46static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
@@ -203,7 +205,6 @@ static struct clk pxa3xx_clks[] = {
203}; 205};
204 206
205#ifdef CONFIG_PM 207#ifdef CONFIG_PM
206#define SLEEP_SAVE_SIZE 4
207 208
208#define ISRAM_START 0x5c000000 209#define ISRAM_START 0x5c000000
209#define ISRAM_SIZE SZ_256K 210#define ISRAM_SIZE SZ_256K
@@ -211,25 +212,29 @@ static struct clk pxa3xx_clks[] = {
211static void __iomem *sram; 212static void __iomem *sram;
212static unsigned long wakeup_src; 213static unsigned long wakeup_src;
213 214
214static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 215#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
215{ 216#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
216 pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB);
217 217
218 if (CKENA & (1 << CKEN_USBH)) { 218enum { SLEEP_SAVE_START = 0,
219 printk(KERN_ERR "PM: USB host clock not stopped?\n"); 219 SLEEP_SAVE_CKENA,
220 CKENA &= ~(1 << CKEN_USBH); 220 SLEEP_SAVE_CKENB,
221 } 221 SLEEP_SAVE_ACCR,
222// CKENA |= 1 << (CKEN_ISC & 31);
223 222
224 /* 223 SLEEP_SAVE_SIZE,
225 * Low power modes require the HSIO2 clock to be enabled. 224};
226 */ 225
227 CKENB |= 1 << (CKEN_HSIO2 & 31); 226static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
227{
228 SAVE(CKENA);
229 SAVE(CKENB);
230 SAVE(ACCR);
228} 231}
229 232
230static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 233static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
231{ 234{
232 CKENB &= ~(1 << (CKEN_HSIO2 & 31)); 235 RESTORE(ACCR);
236 RESTORE(CKENA);
237 RESTORE(CKENB);
233} 238}
234 239
235/* 240/*
@@ -265,6 +270,46 @@ static void pxa3xx_cpu_standby(unsigned int pwrmode)
265 printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR); 270 printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
266} 271}
267 272
273/*
274 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
275 * PXA3xx development kits assumes that the resuming process continues
276 * with the address stored within the first 4 bytes of SDRAM. The PSPR
277 * register is used privately by BootROM and OBM, and _must_ be set to
278 * 0x5c014000 for the moment.
279 */
280static void pxa3xx_cpu_pm_suspend(void)
281{
282 volatile unsigned long *p = (volatile void *)0xc0000000;
283 unsigned long saved_data = *p;
284
285 extern void pxa3xx_cpu_suspend(void);
286 extern void pxa3xx_cpu_resume(void);
287
288 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
289 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
290 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
291
292 /* clear and setup wakeup source */
293 AD3SR = ~0;
294 AD3ER = wakeup_src;
295 ASCR = ASCR;
296 ARSR = ARSR;
297
298 PCFR |= (1u << 13); /* L1_DIS */
299 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
300
301 PSPR = 0x5c014000;
302
303 /* overwrite with the resume address */
304 *p = virt_to_phys(pxa3xx_cpu_resume);
305
306 pxa3xx_cpu_suspend();
307
308 *p = saved_data;
309
310 AD3ER = 0;
311}
312
268static void pxa3xx_cpu_pm_enter(suspend_state_t state) 313static void pxa3xx_cpu_pm_enter(suspend_state_t state)
269{ 314{
270 /* 315 /*
@@ -279,6 +324,7 @@ static void pxa3xx_cpu_pm_enter(suspend_state_t state)
279 break; 324 break;
280 325
281 case PM_SUSPEND_MEM: 326 case PM_SUSPEND_MEM:
327 pxa3xx_cpu_pm_suspend();
282 break; 328 break;
283 } 329 }
284} 330}
@@ -452,9 +498,21 @@ static struct platform_device *devices[] __initdata = {
452 &pxa3xx_device_ssp4, 498 &pxa3xx_device_ssp4,
453}; 499};
454 500
501static struct sys_device pxa3xx_sysdev[] = {
502 {
503 .id = 0,
504 .cls = &pxa_irq_sysclass,
505 }, {
506 .id = 1,
507 .cls = &pxa_irq_sysclass,
508 }, {
509 .cls = &pxa_gpio_sysclass,
510 },
511};
512
455static int __init pxa3xx_init(void) 513static int __init pxa3xx_init(void)
456{ 514{
457 int ret = 0; 515 int i, ret = 0;
458 516
459 if (cpu_is_pxa3xx()) { 517 if (cpu_is_pxa3xx()) {
460 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 518 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
@@ -464,9 +522,16 @@ static int __init pxa3xx_init(void)
464 522
465 pxa3xx_init_pm(); 523 pxa3xx_init_pm();
466 524
467 return platform_add_devices(devices, ARRAY_SIZE(devices)); 525 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
526 ret = sysdev_register(&pxa3xx_sysdev[i]);
527 if (ret)
528 pr_err("failed to register sysdev[%d]\n", i);
529 }
530
531 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
468 } 532 }
469 return 0; 533
534 return ret;
470} 535}
471 536
472subsys_initcall(pxa3xx_init); 537subsys_initcall(pxa3xx_init);
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 14bb4a93ea52..784716eb7fc5 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -50,6 +50,108 @@ pxa_cpu_save_sp:
50 str r0, [r1] 50 str r0, [r1]
51 ldr pc, [sp], #4 51 ldr pc, [sp], #4
52 52
53#ifdef CONFIG_PXA3xx
54/*
55 * pxa3xx_cpu_suspend() - forces CPU into sleep state (S2D3C4)
56 *
57 * NOTE: unfortunately, pxa_cpu_save_cp can not be reused here since
58 * the auxiliary control register address is different between pxa3xx
59 * and pxa{25x,27x}
60 */
61
62ENTRY(pxa3xx_cpu_suspend)
63
64#ifndef CONFIG_IWMMXT
65 mra r2, r3, acc0
66#endif
67 stmfd sp!, {r2 - r12, lr} @ save registers on stack
68
69 mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode
70 mrc p15, 0, r4, c15, c1, 0 @ CP access reg
71 mrc p15, 0, r5, c13, c0, 0 @ PID
72 mrc p15, 0, r6, c3, c0, 0 @ domain ID
73 mrc p15, 0, r7, c2, c0, 0 @ translation table base addr
74 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
75 mrc p15, 0, r9, c1, c0, 0 @ control reg
76
77 bic r3, r3, #2 @ clear frequency change bit
78
79 @ store them plus current virtual stack ptr on stack
80 mov r10, sp
81 stmfd sp!, {r3 - r10}
82
83 @ store physical address of stack pointer
84 mov r0, sp
85 bl sleep_phys_sp
86 ldr r1, =sleep_save_sp
87 str r0, [r1]
88
89 @ clean data cache
90 bl xsc3_flush_kern_cache_all
91
92 mov r0, #0x06 @ S2D3C4 mode
93 mcr p14, 0, r0, c7, c0, 0 @ enter sleep
94
9520: b 20b @ waiting for sleep
96
97 .data
98 .align 5
99/*
100 * pxa3xx_cpu_resume
101 */
102
103ENTRY(pxa3xx_cpu_resume)
104
105 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
106 msr cpsr_c, r0
107
108 ldr r0, sleep_save_sp @ stack phys addr
109 ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr
110
111 mov r1, #0
112 mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
113 mcr p15, 0, r1, c7, c10, 4 @ drain write (&fill) buffer
114 mcr p15, 0, r1, c7, c5, 4 @ flush prefetch buffer
115 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
116
117 mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode.
118 mcr p15, 0, r4, c15, c1, 0 @ CP access reg
119 mcr p15, 0, r5, c13, c0, 0 @ PID
120 mcr p15, 0, r6, c3, c0, 0 @ domain ID
121 mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
122 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
123
124 @ temporarily map resume_turn_on_mmu into the page table,
125 @ otherwise prefetch abort occurs after MMU is turned on
126 mov r1, r7
127 bic r1, r1, #0x00ff
128 bic r1, r1, #0x3f00
129 ldr r2, =0x542e
130
131 adr r3, resume_turn_on_mmu
132 mov r3, r3, lsr #20
133 orr r4, r2, r3, lsl #20
134 ldr r5, [r1, r3, lsl #2]
135 str r4, [r1, r3, lsl #2]
136
137 @ Mapping page table address in the page table
138 mov r6, r1, lsr #20
139 orr r7, r2, r6, lsl #20
140 ldr r8, [r1, r6, lsl #2]
141 str r7, [r1, r6, lsl #2]
142
143 ldr r2, =pxa3xx_resume_after_mmu @ absolute virtual address
144 b resume_turn_on_mmu @ cache align execution
145
146 .text
147pxa3xx_resume_after_mmu:
148 /* restore the temporary mapping */
149 str r5, [r1, r3, lsl #2]
150 str r8, [r1, r6, lsl #2]
151 b resume_after_mmu
152
153#endif /* CONFIG_PXA3xx */
154
53#ifdef CONFIG_PXA27x 155#ifdef CONFIG_PXA27x
54/* 156/*
55 * pxa27x_cpu_suspend() 157 * pxa27x_cpu_suspend()
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c
new file mode 100644
index 000000000000..ad346addc028
--- /dev/null
+++ b/arch/arm/mach-pxa/smemc.c
@@ -0,0 +1,88 @@
1/*
2 * Static Memory Controller
3 */
4
5#include <linux/module.h>
6#include <linux/kernel.h>
7#include <linux/init.h>
8#include <linux/io.h>
9#include <linux/sysdev.h>
10
11#define SMEMC_PHYS_BASE (0x4A000000)
12#define SMEMC_PHYS_SIZE (0x90)
13
14#define MSC0 (0x08) /* Static Memory Controller Register 0 */
15#define MSC1 (0x0C) /* Static Memory Controller Register 1 */
16#define SXCNFG (0x1C) /* Synchronous Static Memory Control Register */
17#define MEMCLKCFG (0x68) /* Clock Configuration */
18#define CSADRCFG0 (0x80) /* Address Configuration Register for CS0 */
19#define CSADRCFG1 (0x84) /* Address Configuration Register for CS1 */
20#define CSADRCFG2 (0x88) /* Address Configuration Register for CS2 */
21#define CSADRCFG3 (0x8C) /* Address Configuration Register for CS3 */
22
23#ifdef CONFIG_PM
24static void __iomem *smemc_mmio_base;
25
26static unsigned long msc[2];
27static unsigned long sxcnfg, memclkcfg;
28static unsigned long csadrcfg[4];
29
30static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state)
31{
32 msc[0] = __raw_readl(smemc_mmio_base + MSC0);
33 msc[1] = __raw_readl(smemc_mmio_base + MSC1);
34 sxcnfg = __raw_readl(smemc_mmio_base + SXCNFG);
35 memclkcfg = __raw_readl(smemc_mmio_base + MEMCLKCFG);
36 csadrcfg[0] = __raw_readl(smemc_mmio_base + CSADRCFG0);
37 csadrcfg[1] = __raw_readl(smemc_mmio_base + CSADRCFG1);
38 csadrcfg[2] = __raw_readl(smemc_mmio_base + CSADRCFG2);
39 csadrcfg[3] = __raw_readl(smemc_mmio_base + CSADRCFG3);
40
41 return 0;
42}
43
44static int pxa3xx_smemc_resume(struct sys_device *dev)
45{
46 __raw_writel(msc[0], smemc_mmio_base + MSC0);
47 __raw_writel(msc[1], smemc_mmio_base + MSC1);
48 __raw_writel(sxcnfg, smemc_mmio_base + SXCNFG);
49 __raw_writel(memclkcfg, smemc_mmio_base + MEMCLKCFG);
50 __raw_writel(csadrcfg[0], smemc_mmio_base + CSADRCFG0);
51 __raw_writel(csadrcfg[1], smemc_mmio_base + CSADRCFG1);
52 __raw_writel(csadrcfg[2], smemc_mmio_base + CSADRCFG2);
53 __raw_writel(csadrcfg[3], smemc_mmio_base + CSADRCFG3);
54
55 return 0;
56}
57
58static struct sysdev_class smemc_sysclass = {
59 .name = "smemc",
60 .suspend = pxa3xx_smemc_suspend,
61 .resume = pxa3xx_smemc_resume,
62};
63
64static struct sys_device smemc_sysdev = {
65 .id = 0,
66 .cls = &smemc_sysclass,
67};
68
69static int __init smemc_init(void)
70{
71 int ret = 0;
72
73 if (cpu_is_pxa3xx()) {
74 smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE);
75 if (smemc_mmio_base == NULL)
76 return -ENODEV;
77
78 ret = sysdev_class_register(&smemc_sysclass);
79 if (ret)
80 return ret;
81
82 ret = sysdev_register(&smemc_sysdev);
83 }
84
85 return ret;
86}
87subsys_initcall(smemc_init);
88#endif
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 5078edeadf96..9e7773fca01c 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -36,6 +36,7 @@
36#include <asm/mach/irq.h> 36#include <asm/mach/irq.h>
37 37
38#include <asm/arch/pxa-regs.h> 38#include <asm/arch/pxa-regs.h>
39#include <asm/arch/pxa2xx-regs.h>
39#include <asm/arch/irda.h> 40#include <asm/arch/irda.h>
40#include <asm/arch/mmc.h> 41#include <asm/arch/mmc.h>
41#include <asm/arch/ohci.h> 42#include <asm/arch/ohci.h>
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 1a9c844ac7eb..9b26fa5edad6 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -29,6 +29,7 @@
29#include <asm/irq.h> 29#include <asm/irq.h>
30#include <asm/system.h> 30#include <asm/system.h>
31#include <asm/arch/pxa-regs.h> 31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/pxa2xx-regs.h>
32#include <asm/arch/irda.h> 33#include <asm/arch/irda.h>
33#include <asm/arch/mmc.h> 34#include <asm/arch/mmc.h>
34#include <asm/arch/udc.h> 35#include <asm/arch/udc.h>
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 35156ca39df7..39b3bb7f1020 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -7,24 +7,21 @@ config MACH_REALVIEW_EB
7 help 7 help
8 Include support for the ARM(R) RealView Emulation Baseboard platform. 8 Include support for the ARM(R) RealView Emulation Baseboard platform.
9 9
10config REALVIEW_MPCORE 10config REALVIEW_EB_ARM11MP
11 bool "Support MPcore tile" 11 bool "Support ARM11MPCore tile"
12 depends on MACH_REALVIEW_EB 12 depends on MACH_REALVIEW_EB
13 select CACHE_L2X0 13 select CACHE_L2X0
14 help 14 help
15 Enable support for the MPCore tile on the Realview platform. 15 Enable support for the ARM11MPCore tile on the Realview platform.
16 Since there are device address and interrupt differences, a
17 kernel built with this option enabled is not compatible with
18 other tiles.
19 16
20config REALVIEW_MPCORE_REVB 17config REALVIEW_EB_ARM11MP_REVB
21 bool "Support MPcore RevB tile" 18 bool "Support ARM11MPCore RevB tile"
22 depends on REALVIEW_MPCORE 19 depends on REALVIEW_EB_ARM11MP
23 default n 20 default n
24 help 21 help
25 Enable support for the MPCore RevB tile on the Realview platform. 22 Enable support for the ARM11MPCore RevB tile on the Realview
26 Since there are device address differences, a 23 platform. Since there are device address differences, a
27 kernel built with this option enabled is not compatible with 24 kernel built with this option enabled is not compatible with
28 other tiles. 25 other revisions of the ARM11MPCore tile.
29 26
30endmenu 27endmenu
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index 36e76ba937fc..ca1e390c3c28 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -4,6 +4,5 @@
4 4
5obj-y := core.o clock.o 5obj-y := core.o clock.o
6obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o 6obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o
7obj-$(CONFIG_SMP) += platsmp.o headsmp.o 7obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o
8obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 8obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
9obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 61d70218f1e8..98aefc9f4df3 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -25,6 +25,8 @@
25#include <linux/interrupt.h> 25#include <linux/interrupt.h>
26#include <linux/amba/bus.h> 26#include <linux/amba/bus.h>
27#include <linux/amba/clcd.h> 27#include <linux/amba/clcd.h>
28#include <linux/clocksource.h>
29#include <linux/clockchips.h>
28 30
29#include <asm/system.h> 31#include <asm/system.h>
30#include <asm/hardware.h> 32#include <asm/hardware.h>
@@ -37,7 +39,6 @@
37#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
38#include <asm/mach/flash.h> 40#include <asm/mach/flash.h>
39#include <asm/mach/irq.h> 41#include <asm/mach/irq.h>
40#include <asm/mach/time.h>
41#include <asm/mach/map.h> 42#include <asm/mach/map.h>
42#include <asm/mach/mmc.h> 43#include <asm/mach/mmc.h>
43 44
@@ -48,6 +49,9 @@
48 49
49#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) 50#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
50 51
52/* used by entry-macro.S */
53void __iomem *gic_cpu_base_addr;
54
51/* 55/*
52 * This is the RealView sched_clock implementation. This has 56 * This is the RealView sched_clock implementation. This has
53 * a resolution of 41.7ns, and a maximum value of about 179s. 57 * a resolution of 41.7ns, and a maximum value of about 179s.
@@ -121,26 +125,6 @@ struct platform_device realview_flash_device = {
121 .resource = &realview_flash_resource, 125 .resource = &realview_flash_resource,
122}; 126};
123 127
124static struct resource realview_smc91x_resources[] = {
125 [0] = {
126 .start = REALVIEW_ETH_BASE,
127 .end = REALVIEW_ETH_BASE + SZ_64K - 1,
128 .flags = IORESOURCE_MEM,
129 },
130 [1] = {
131 .start = IRQ_ETH,
132 .end = IRQ_ETH,
133 .flags = IORESOURCE_IRQ,
134 },
135};
136
137struct platform_device realview_smc91x_device = {
138 .name = "smc91x",
139 .id = 0,
140 .num_resources = ARRAY_SIZE(realview_smc91x_resources),
141 .resource = realview_smc91x_resources,
142};
143
144static struct resource realview_i2c_resource = { 128static struct resource realview_i2c_resource = {
145 .start = REALVIEW_I2C_BASE, 129 .start = REALVIEW_I2C_BASE,
146 .end = REALVIEW_I2C_BASE + SZ_4K - 1, 130 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
@@ -484,45 +468,64 @@ void realview_leds_event(led_event_t ledevt)
484#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) 468#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
485#endif 469#endif
486 470
487/* 471static void timer_set_mode(enum clock_event_mode mode,
488 * Returns number of ms since last clock interrupt. Note that interrupts 472 struct clock_event_device *clk)
489 * will have been disabled by do_gettimeoffset()
490 */
491static unsigned long realview_gettimeoffset(void)
492{ 473{
493 unsigned long ticks1, ticks2, status; 474 unsigned long ctrl;
494 475
495 /* 476 switch(mode) {
496 * Get the current number of ticks. Note that there is a race 477 case CLOCK_EVT_MODE_PERIODIC:
497 * condition between us reading the timer and checking for 478 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
498 * an interrupt. We get around this by ensuring that the
499 * counter has not reloaded between our two reads.
500 */
501 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
502 do {
503 ticks1 = ticks2;
504 status = __raw_readl(__io_address(REALVIEW_GIC_DIST_BASE + GIC_DIST_PENDING_SET)
505 + ((IRQ_TIMERINT0_1 >> 5) << 2));
506 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
507 } while (ticks2 > ticks1);
508 479
509 /* 480 ctrl = TIMER_CTRL_PERIODIC;
510 * Number of ticks since last interrupt. 481 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
511 */ 482 break;
512 ticks1 = TIMER_RELOAD - ticks2; 483 case CLOCK_EVT_MODE_ONESHOT:
484 /* period set, and timer enabled in 'next_event' hook */
485 ctrl = TIMER_CTRL_ONESHOT;
486 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
487 break;
488 case CLOCK_EVT_MODE_UNUSED:
489 case CLOCK_EVT_MODE_SHUTDOWN:
490 default:
491 ctrl = 0;
492 }
513 493
514 /* 494 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
515 * Interrupt pending? If so, we've reloaded once already. 495}
516 *
517 * FIXME: Need to check this is effectively timer 0 that expires
518 */
519 if (status & IRQMASK_TIMERINT0_1)
520 ticks1 += TIMER_RELOAD;
521 496
522 /* 497static int timer_set_next_event(unsigned long evt,
523 * Convert the ticks to usecs 498 struct clock_event_device *unused)
524 */ 499{
525 return TICKS2USECS(ticks1); 500 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
501
502 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
503 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
504
505 return 0;
506}
507
508static struct clock_event_device timer0_clockevent = {
509 .name = "timer0",
510 .shift = 32,
511 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
512 .set_mode = timer_set_mode,
513 .set_next_event = timer_set_next_event,
514 .rating = 300,
515 .cpumask = CPU_MASK_ALL,
516};
517
518static void __init realview_clockevents_init(unsigned int timer_irq)
519{
520 timer0_clockevent.irq = timer_irq;
521 timer0_clockevent.mult =
522 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
523 timer0_clockevent.max_delta_ns =
524 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
525 timer0_clockevent.min_delta_ns =
526 clockevent_delta2ns(0xf, &timer0_clockevent);
527
528 clockevents_register_device(&timer0_clockevent);
526} 529}
527 530
528/* 531/*
@@ -530,15 +533,12 @@ static unsigned long realview_gettimeoffset(void)
530 */ 533 */
531static irqreturn_t realview_timer_interrupt(int irq, void *dev_id) 534static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
532{ 535{
533 // ...clear the interrupt 536 struct clock_event_device *evt = &timer0_clockevent;
537
538 /* clear the interrupt */
534 writel(1, TIMER0_VA_BASE + TIMER_INTCLR); 539 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
535 540
536 timer_tick(); 541 evt->event_handler(evt);
537
538#if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
539 smp_send_timer();
540 update_process_times(user_mode(get_irq_regs()));
541#endif
542 542
543 return IRQ_HANDLED; 543 return IRQ_HANDLED;
544} 544}
@@ -549,13 +549,49 @@ static struct irqaction realview_timer_irq = {
549 .handler = realview_timer_interrupt, 549 .handler = realview_timer_interrupt,
550}; 550};
551 551
552static cycle_t realview_get_cycles(void)
553{
554 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
555}
556
557static struct clocksource clocksource_realview = {
558 .name = "timer3",
559 .rating = 200,
560 .read = realview_get_cycles,
561 .mask = CLOCKSOURCE_MASK(32),
562 .shift = 20,
563 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
564};
565
566static void __init realview_clocksource_init(void)
567{
568 /* setup timer 0 as free-running clocksource */
569 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
570 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
571 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
572 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
573 TIMER3_VA_BASE + TIMER_CTRL);
574
575 clocksource_realview.mult =
576 clocksource_khz2mult(1000, clocksource_realview.shift);
577 clocksource_register(&clocksource_realview);
578}
579
552/* 580/*
553 * Set up timer interrupt, and return the current time in seconds. 581 * Set up the clock source and clock events devices
554 */ 582 */
555static void __init realview_timer_init(void) 583void __init realview_timer_init(unsigned int timer_irq)
556{ 584{
557 u32 val; 585 u32 val;
558 586
587#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
588 /*
589 * The dummy clock device has to be registered before the main device
590 * so that the latter will broadcast the clock events
591 */
592 local_timer_setup(smp_processor_id());
593#endif
594
559 /* 595 /*
560 * set clock frequency: 596 * set clock frequency:
561 * REALVIEW_REFCLK is 32KHz 597 * REALVIEW_REFCLK is 32KHz
@@ -576,18 +612,11 @@ static void __init realview_timer_init(void)
576 writel(0, TIMER2_VA_BASE + TIMER_CTRL); 612 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
577 writel(0, TIMER3_VA_BASE + TIMER_CTRL); 613 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
578 614
579 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
580 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
581 writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
582 TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
583
584 /* 615 /*
585 * Make irqs happen for the system timer 616 * Make irqs happen for the system timer
586 */ 617 */
587 setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq); 618 setup_irq(timer_irq, &realview_timer_irq);
588}
589 619
590struct sys_timer realview_timer = { 620 realview_clocksource_init();
591 .init = realview_timer_init, 621 realview_clockevents_init(timer_irq);
592 .offset = realview_gettimeoffset, 622}
593};
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 2b53420f9c1b..492a14c0d604 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -27,8 +27,6 @@
27#include <asm/leds.h> 27#include <asm/leds.h>
28#include <asm/io.h> 28#include <asm/io.h>
29 29
30extern struct sys_timer realview_timer;
31
32#define AMBA_DEVICE(name,busid,base,plat) \ 30#define AMBA_DEVICE(name,busid,base,plat) \
33static struct amba_device name##_device = { \ 31static struct amba_device name##_device = { \
34 .dev = { \ 32 .dev = { \
@@ -38,7 +36,7 @@ static struct amba_device name##_device = { \
38 }, \ 36 }, \
39 .res = { \ 37 .res = { \
40 .start = REALVIEW_##base##_BASE, \ 38 .start = REALVIEW_##base##_BASE, \
41 .end = (REALVIEW_##base##_BASE) + SZ_4K - 1,\ 39 .end = (REALVIEW_##base##_BASE) + SZ_4K - 1, \
42 .flags = IORESOURCE_MEM, \ 40 .flags = IORESOURCE_MEM, \
43 }, \ 41 }, \
44 .dma_mask = ~0, \ 42 .dma_mask = ~0, \
@@ -46,74 +44,19 @@ static struct amba_device name##_device = { \
46 /* .dma = base##_DMA,*/ \ 44 /* .dma = base##_DMA,*/ \
47} 45}
48 46
49/*
50 * These devices are connected via the core APB bridge
51 */
52#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ }
53#define GPIO2_DMA { 0, 0 }
54#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ }
55#define GPIO3_DMA { 0, 0 }
56
57#define AACI_IRQ { IRQ_AACI, NO_IRQ }
58#define AACI_DMA { 0x80, 0x81 }
59#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_MMCI0B }
60#define MMCI0_DMA { 0x84, 0 }
61#define KMI0_IRQ { IRQ_KMI0, NO_IRQ }
62#define KMI0_DMA { 0, 0 }
63#define KMI1_IRQ { IRQ_KMI1, NO_IRQ }
64#define KMI1_DMA { 0, 0 }
65
66/*
67 * These devices are connected directly to the multi-layer AHB switch
68 */
69#define SMC_IRQ { NO_IRQ, NO_IRQ }
70#define SMC_DMA { 0, 0 }
71#define MPMC_IRQ { NO_IRQ, NO_IRQ }
72#define MPMC_DMA { 0, 0 }
73#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
74#define CLCD_DMA { 0, 0 }
75#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
76#define DMAC_DMA { 0, 0 }
77
78/*
79 * These devices are connected via the core APB bridge
80 */
81#define SCTL_IRQ { NO_IRQ, NO_IRQ }
82#define SCTL_DMA { 0, 0 }
83#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
84#define WATCHDOG_DMA { 0, 0 }
85#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
86#define GPIO0_DMA { 0, 0 }
87#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
88#define GPIO1_DMA { 0, 0 }
89#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
90#define RTC_DMA { 0, 0 }
91
92/*
93 * These devices are connected via the DMA APB bridge
94 */
95#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
96#define SCI_DMA { 7, 6 }
97#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
98#define UART0_DMA { 15, 14 }
99#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
100#define UART1_DMA { 13, 12 }
101#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
102#define UART2_DMA { 11, 10 }
103#define UART3_IRQ { IRQ_UART3, NO_IRQ }
104#define UART3_DMA { 0x86, 0x87 }
105#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
106#define SSP_DMA { 9, 8 }
107
108
109extern struct platform_device realview_flash_device; 47extern struct platform_device realview_flash_device;
110extern struct platform_device realview_smc91x_device;
111extern struct platform_device realview_i2c_device; 48extern struct platform_device realview_i2c_device;
112extern struct mmc_platform_data realview_mmc0_plat_data; 49extern struct mmc_platform_data realview_mmc0_plat_data;
113extern struct mmc_platform_data realview_mmc1_plat_data; 50extern struct mmc_platform_data realview_mmc1_plat_data;
114extern struct clk realview_clcd_clk; 51extern struct clk realview_clcd_clk;
115extern struct clcd_board clcd_plat_data; 52extern struct clcd_board clcd_plat_data;
53extern void __iomem *gic_cpu_base_addr;
54#ifdef CONFIG_LOCAL_TIMERS
55extern void __iomem *twd_base_addr;
56extern unsigned int twd_size;
57#endif
116 58
117extern void realview_leds_event(led_event_t ledevt); 59extern void realview_leds_event(led_event_t ledevt);
60extern void realview_timer_init(unsigned int timer_irq);
118 61
119#endif 62#endif
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
index c7bdf04ab094..50604360479f 100644
--- a/arch/arm/mach-realview/localtimer.c
+++ b/arch/arm/mach-realview/localtimer.c
@@ -14,19 +14,75 @@
14#include <linux/device.h> 14#include <linux/device.h>
15#include <linux/smp.h> 15#include <linux/smp.h>
16#include <linux/jiffies.h> 16#include <linux/jiffies.h>
17#include <linux/percpu.h>
18#include <linux/clockchips.h>
19#include <linux/irq.h>
17 20
18#include <asm/mach/time.h>
19#include <asm/hardware/arm_twd.h> 21#include <asm/hardware/arm_twd.h>
20#include <asm/hardware/gic.h> 22#include <asm/hardware/gic.h>
21#include <asm/hardware.h> 23#include <asm/hardware.h>
22#include <asm/io.h> 24#include <asm/io.h>
23#include <asm/irq.h> 25#include <asm/irq.h>
24 26
25#define TWD_BASE(cpu) (__io_address(REALVIEW_TWD_BASE) + \ 27static DEFINE_PER_CPU(struct clock_event_device, local_clockevent);
26 ((cpu) * REALVIEW_TWD_SIZE)) 28
29/*
30 * Used on SMP for either the local timer or IPI_TIMER
31 */
32void local_timer_interrupt(void)
33{
34 struct clock_event_device *clk = &__get_cpu_var(local_clockevent);
35
36 clk->event_handler(clk);
37}
38
39#ifdef CONFIG_LOCAL_TIMERS
40
41#define TWD_BASE(cpu) (twd_base_addr + (cpu) * twd_size)
42
43/* set up by the platform code */
44void __iomem *twd_base_addr;
45unsigned int twd_size;
27 46
28static unsigned long mpcore_timer_rate; 47static unsigned long mpcore_timer_rate;
29 48
49static void local_timer_set_mode(enum clock_event_mode mode,
50 struct clock_event_device *clk)
51{
52 void __iomem *base = TWD_BASE(smp_processor_id());
53 unsigned long ctrl;
54
55 switch(mode) {
56 case CLOCK_EVT_MODE_PERIODIC:
57 /* timer load already set up */
58 ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
59 | TWD_TIMER_CONTROL_PERIODIC;
60 break;
61 case CLOCK_EVT_MODE_ONESHOT:
62 /* period set, and timer enabled in 'next_event' hook */
63 ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
64 break;
65 case CLOCK_EVT_MODE_UNUSED:
66 case CLOCK_EVT_MODE_SHUTDOWN:
67 default:
68 ctrl = 0;
69 }
70
71 __raw_writel(ctrl, base + TWD_TIMER_CONTROL);
72}
73
74static int local_timer_set_next_event(unsigned long evt,
75 struct clock_event_device *unused)
76{
77 void __iomem *base = TWD_BASE(smp_processor_id());
78 unsigned long ctrl = __raw_readl(base + TWD_TIMER_CONTROL);
79
80 __raw_writel(evt, base + TWD_TIMER_COUNTER);
81 __raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, base + TWD_TIMER_CONTROL);
82
83 return 0;
84}
85
30/* 86/*
31 * local_timer_ack: checks for a local timer interrupt. 87 * local_timer_ack: checks for a local timer interrupt.
32 * 88 *
@@ -45,12 +101,11 @@ int local_timer_ack(void)
45 return 0; 101 return 0;
46} 102}
47 103
48void __cpuinit local_timer_setup(unsigned int cpu) 104static void __cpuinit twd_calibrate_rate(unsigned int cpu)
49{ 105{
50 void __iomem *base = TWD_BASE(cpu); 106 void __iomem *base = TWD_BASE(cpu);
51 unsigned int load, offset; 107 unsigned long load, count;
52 u64 waitjiffies; 108 u64 waitjiffies;
53 unsigned int count;
54 109
55 /* 110 /*
56 * If this is the first time round, we need to work out how fast 111 * If this is the first time round, we need to work out how fast
@@ -88,36 +143,36 @@ void __cpuinit local_timer_setup(unsigned int cpu)
88 load = mpcore_timer_rate / HZ; 143 load = mpcore_timer_rate / HZ;
89 144
90 __raw_writel(load, base + TWD_TIMER_LOAD); 145 __raw_writel(load, base + TWD_TIMER_LOAD);
91 __raw_writel(0x7, base + TWD_TIMER_CONTROL); 146}
92
93 /*
94 * Now maneuver our local tick into the right part of the jiffy.
95 * Start by working out where within the tick our local timer
96 * interrupt should go.
97 */
98 offset = ((mpcore_timer_rate / HZ) / (NR_CPUS + 1)) * (cpu + 1);
99
100 /*
101 * gettimeoffset() will return a number of us since the last tick.
102 * Convert this number of us to a local timer tick count.
103 * Be careful of integer overflow whilst keeping maximum precision.
104 *
105 * with HZ=100 and 1MHz (fpga) ~ 1GHz processor:
106 * load = 1 ~ 10,000
107 * mpcore_timer_rate/10000 = 100 ~ 100,000
108 *
109 * so the multiply value will be less than 10^9 always.
110 */
111 load = (system_timer->offset() * (mpcore_timer_rate / 10000)) / 100;
112
113 /* Add on our offset to get the load value */
114 load = (load + offset) % (mpcore_timer_rate / HZ);
115 147
116 __raw_writel(load, base + TWD_TIMER_COUNTER); 148/*
149 * Setup the local clock events for a CPU.
150 */
151void __cpuinit local_timer_setup(unsigned int cpu)
152{
153 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
154 unsigned long flags;
155
156 twd_calibrate_rate(cpu);
157
158 clk->name = "local_timer";
159 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
160 clk->rating = 350;
161 clk->set_mode = local_timer_set_mode;
162 clk->set_next_event = local_timer_set_next_event;
163 clk->irq = IRQ_LOCALTIMER;
164 clk->cpumask = cpumask_of_cpu(cpu);
165 clk->shift = 20;
166 clk->mult = div_sc(mpcore_timer_rate, NSEC_PER_SEC, clk->shift);
167 clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
168 clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
117 169
118 /* Make sure our local interrupt controller has this enabled */ 170 /* Make sure our local interrupt controller has this enabled */
119 __raw_writel(1 << IRQ_LOCALTIMER, 171 local_irq_save(flags);
120 __io_address(REALVIEW_GIC_DIST_BASE) + GIC_DIST_ENABLE_SET); 172 get_irq_chip(IRQ_LOCALTIMER)->unmask(IRQ_LOCALTIMER);
173 local_irq_restore(flags);
174
175 clockevents_register_device(clk);
121} 176}
122 177
123/* 178/*
@@ -127,3 +182,26 @@ void __cpuexit local_timer_stop(unsigned int cpu)
127{ 182{
128 __raw_writel(0, TWD_BASE(cpu) + TWD_TIMER_CONTROL); 183 __raw_writel(0, TWD_BASE(cpu) + TWD_TIMER_CONTROL);
129} 184}
185
186#else /* CONFIG_LOCAL_TIMERS */
187
188static void dummy_timer_set_mode(enum clock_event_mode mode,
189 struct clock_event_device *clk)
190{
191}
192
193void __cpuinit local_timer_setup(unsigned int cpu)
194{
195 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
196
197 clk->name = "dummy_timer";
198 clk->features = CLOCK_EVT_FEAT_DUMMY;
199 clk->rating = 200;
200 clk->set_mode = dummy_timer_set_mode;
201 clk->broadcast = smp_timer_broadcast;
202 clk->cpumask = cpumask_of_cpu(cpu);
203
204 clockevents_register_device(clk);
205}
206
207#endif /* !CONFIG_LOCAL_TIMERS */
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index fce3596f9950..de2b7159557d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -18,6 +18,7 @@
18#include <asm/hardware/arm_scu.h> 18#include <asm/hardware/arm_scu.h>
19#include <asm/hardware.h> 19#include <asm/hardware.h>
20#include <asm/io.h> 20#include <asm/io.h>
21#include <asm/mach-types.h>
21 22
22extern void realview_secondary_startup(void); 23extern void realview_secondary_startup(void);
23 24
@@ -31,9 +32,13 @@ static unsigned int __init get_core_count(void)
31{ 32{
32 unsigned int ncores; 33 unsigned int ncores;
33 34
34 ncores = __raw_readl(__io_address(REALVIEW_MPCORE_SCU_BASE) + SCU_CONFIG); 35 if (machine_is_realview_eb() && core_tile_eb11mp()) {
36 ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG);
37 ncores = (ncores & 0x03) + 1;
38 } else
39 ncores = 1;
35 40
36 return (ncores & 0x03) + 1; 41 return ncores;
37} 42}
38 43
39static DEFINE_SPINLOCK(boot_lock); 44static DEFINE_SPINLOCK(boot_lock);
@@ -52,7 +57,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
52 * core (e.g. timer irq), then they will not have been enabled 57 * core (e.g. timer irq), then they will not have been enabled
53 * for us: do so 58 * for us: do so
54 */ 59 */
55 gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); 60 gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
56 61
57 /* 62 /*
58 * let the primary processor know we're out of the 63 * let the primary processor know we're out of the
@@ -187,10 +192,15 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
187 if (max_cpus > ncores) 192 if (max_cpus > ncores)
188 max_cpus = ncores; 193 max_cpus = ncores;
189 194
195#ifdef CONFIG_LOCAL_TIMERS
190 /* 196 /*
191 * Enable the local timer for primary CPU 197 * Enable the local timer for primary CPU. If the device is
198 * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
199 * realview_timer_init
192 */ 200 */
193 local_timer_setup(cpu); 201 if (machine_is_realview_eb() && core_tile_eb11mp())
202 local_timer_setup(cpu);
203#endif
194 204
195 /* 205 /*
196 * Initialise the present map, which describes the set of CPUs 206 * Initialise the present map, which describes the set of CPUs
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index ecec2f85c4cd..60d9eb810246 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -36,7 +36,9 @@
36#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
37#include <asm/mach/map.h> 37#include <asm/mach/map.h>
38#include <asm/mach/mmc.h> 38#include <asm/mach/mmc.h>
39#include <asm/mach/time.h>
39 40
41#include <asm/arch/board-eb.h>
40#include <asm/arch/irqs.h> 42#include <asm/arch/irqs.h>
41 43
42#include "core.h" 44#include "core.h"
@@ -58,26 +60,7 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
58 .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE), 60 .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE),
59 .length = SZ_4K, 61 .length = SZ_4K,
60 .type = MT_DEVICE, 62 .type = MT_DEVICE,
61 },
62#ifdef CONFIG_REALVIEW_MPCORE
63 {
64 .virtual = IO_ADDRESS(REALVIEW_GIC1_CPU_BASE),
65 .pfn = __phys_to_pfn(REALVIEW_GIC1_CPU_BASE),
66 .length = SZ_4K,
67 .type = MT_DEVICE,
68 }, { 63 }, {
69 .virtual = IO_ADDRESS(REALVIEW_GIC1_DIST_BASE),
70 .pfn = __phys_to_pfn(REALVIEW_GIC1_DIST_BASE),
71 .length = SZ_4K,
72 .type = MT_DEVICE,
73 }, {
74 .virtual = IO_ADDRESS(REALVIEW_MPCORE_L220_BASE),
75 .pfn = __phys_to_pfn(REALVIEW_MPCORE_L220_BASE),
76 .length = SZ_8K,
77 .type = MT_DEVICE,
78 },
79#endif
80 {
81 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), 64 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
82 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), 65 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
83 .length = SZ_4K, 66 .length = SZ_4K,
@@ -103,11 +86,95 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
103#endif 86#endif
104}; 87};
105 88
89static struct map_desc realview_eb11mp_io_desc[] __initdata = {
90 {
91 .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE),
92 .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE),
93 .length = SZ_4K,
94 .type = MT_DEVICE,
95 }, {
96 .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE),
97 .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE),
98 .length = SZ_4K,
99 .type = MT_DEVICE,
100 }, {
101 .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
102 .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE),
103 .length = SZ_8K,
104 .type = MT_DEVICE,
105 }
106};
107
106static void __init realview_eb_map_io(void) 108static void __init realview_eb_map_io(void)
107{ 109{
108 iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc)); 110 iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
111 if (core_tile_eb11mp())
112 iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
109} 113}
110 114
115/*
116 * RealView EB AMBA devices
117 */
118
119/*
120 * These devices are connected via the core APB bridge
121 */
122#define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ }
123#define GPIO2_DMA { 0, 0 }
124#define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ }
125#define GPIO3_DMA { 0, 0 }
126
127#define AACI_IRQ { IRQ_EB_AACI, NO_IRQ }
128#define AACI_DMA { 0x80, 0x81 }
129#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
130#define MMCI0_DMA { 0x84, 0 }
131#define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ }
132#define KMI0_DMA { 0, 0 }
133#define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ }
134#define KMI1_DMA { 0, 0 }
135
136/*
137 * These devices are connected directly to the multi-layer AHB switch
138 */
139#define SMC_IRQ { NO_IRQ, NO_IRQ }
140#define SMC_DMA { 0, 0 }
141#define MPMC_IRQ { NO_IRQ, NO_IRQ }
142#define MPMC_DMA { 0, 0 }
143#define CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ }
144#define CLCD_DMA { 0, 0 }
145#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ }
146#define DMAC_DMA { 0, 0 }
147
148/*
149 * These devices are connected via the core APB bridge
150 */
151#define SCTL_IRQ { NO_IRQ, NO_IRQ }
152#define SCTL_DMA { 0, 0 }
153#define WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
154#define WATCHDOG_DMA { 0, 0 }
155#define GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ }
156#define GPIO0_DMA { 0, 0 }
157#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ }
158#define GPIO1_DMA { 0, 0 }
159#define RTC_IRQ { IRQ_EB_RTC, NO_IRQ }
160#define RTC_DMA { 0, 0 }
161
162/*
163 * These devices are connected via the DMA APB bridge
164 */
165#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ }
166#define SCI_DMA { 7, 6 }
167#define UART0_IRQ { IRQ_EB_UART0, NO_IRQ }
168#define UART0_DMA { 15, 14 }
169#define UART1_IRQ { IRQ_EB_UART1, NO_IRQ }
170#define UART1_DMA { 13, 12 }
171#define UART2_IRQ { IRQ_EB_UART2, NO_IRQ }
172#define UART2_DMA { 11, 10 }
173#define UART3_IRQ { IRQ_EB_UART3, NO_IRQ }
174#define UART3_DMA { 0x86, 0x87 }
175#define SSP_IRQ { IRQ_EB_SSP, NO_IRQ }
176#define SSP_DMA { 9, 8 }
177
111/* FPGA Primecells */ 178/* FPGA Primecells */
112AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); 179AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
113AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); 180AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
@@ -153,38 +220,127 @@ static struct amba_device *amba_devs[] __initdata = {
153 &kmi1_device, 220 &kmi1_device,
154}; 221};
155 222
223/*
224 * RealView EB platform devices
225 */
226
227static struct resource realview_eb_smc91x_resources[] = {
228 [0] = {
229 .start = REALVIEW_ETH_BASE,
230 .end = REALVIEW_ETH_BASE + SZ_64K - 1,
231 .flags = IORESOURCE_MEM,
232 },
233 [1] = {
234 .start = IRQ_EB_ETH,
235 .end = IRQ_EB_ETH,
236 .flags = IORESOURCE_IRQ,
237 },
238};
239
240static struct platform_device realview_eb_smc91x_device = {
241 .name = "smc91x",
242 .id = 0,
243 .num_resources = ARRAY_SIZE(realview_eb_smc91x_resources),
244 .resource = realview_eb_smc91x_resources,
245};
246
156static void __init gic_init_irq(void) 247static void __init gic_init_irq(void)
157{ 248{
158#ifdef CONFIG_REALVIEW_MPCORE 249 if (core_tile_eb11mp()) {
159 unsigned int pldctrl; 250 unsigned int pldctrl;
160 writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); 251
161 pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1); 252 /* new irq mode */
162 pldctrl |= 0x00800000; /* New irq mode */ 253 writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
163 writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1); 254 pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
164 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); 255 pldctrl |= 0x00800000;
256 writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
257 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
258
259 /* core tile GIC, primary */
260 gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
261 gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
262 gic_cpu_init(0, gic_cpu_base_addr);
263
264#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
265 /* board GIC, secondary */
266 gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64);
267 gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE));
268 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
165#endif 269#endif
166 gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); 270 } else {
167 gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); 271 /* board GIC, primary */
168#if defined(CONFIG_REALVIEW_MPCORE) && !defined(CONFIG_REALVIEW_MPCORE_REVB) 272 gic_cpu_base_addr = __io_address(REALVIEW_GIC_CPU_BASE);
169 gic_dist_init(1, __io_address(REALVIEW_GIC1_DIST_BASE), 64); 273 gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
170 gic_cpu_init(1, __io_address(REALVIEW_GIC1_CPU_BASE)); 274 gic_cpu_init(0, gic_cpu_base_addr);
171 gic_cascade_irq(1, IRQ_EB_IRQ1); 275 }
276}
277
278/*
279 * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile
280 */
281static void realview_eb11mp_fixup(void)
282{
283 /* AMBA devices */
284 dmac_device.irq[0] = IRQ_EB11MP_DMA;
285 uart0_device.irq[0] = IRQ_EB11MP_UART0;
286 uart1_device.irq[0] = IRQ_EB11MP_UART1;
287 uart2_device.irq[0] = IRQ_EB11MP_UART2;
288 uart3_device.irq[0] = IRQ_EB11MP_UART3;
289 clcd_device.irq[0] = IRQ_EB11MP_CLCD;
290 wdog_device.irq[0] = IRQ_EB11MP_WDOG;
291 gpio0_device.irq[0] = IRQ_EB11MP_GPIO0;
292 gpio1_device.irq[0] = IRQ_EB11MP_GPIO1;
293 gpio2_device.irq[0] = IRQ_EB11MP_GPIO2;
294 rtc_device.irq[0] = IRQ_EB11MP_RTC;
295 sci0_device.irq[0] = IRQ_EB11MP_SCI;
296 ssp0_device.irq[0] = IRQ_EB11MP_SSP;
297 aaci_device.irq[0] = IRQ_EB11MP_AACI;
298 mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A;
299 mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B;
300 kmi0_device.irq[0] = IRQ_EB11MP_KMI0;
301 kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
302
303 /* platform devices */
304 realview_eb_smc91x_resources[1].start = IRQ_EB11MP_ETH;
305 realview_eb_smc91x_resources[1].end = IRQ_EB11MP_ETH;
306}
307
308static void __init realview_eb_timer_init(void)
309{
310 unsigned int timer_irq;
311
312 if (core_tile_eb11mp()) {
313#ifdef CONFIG_LOCAL_TIMERS
314 twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE);
315 twd_size = REALVIEW_EB11MP_TWD_SIZE;
172#endif 316#endif
317 timer_irq = IRQ_EB11MP_TIMER0_1;
318 } else
319 timer_irq = IRQ_EB_TIMER0_1;
320
321 realview_timer_init(timer_irq);
173} 322}
174 323
324static struct sys_timer realview_eb_timer = {
325 .init = realview_eb_timer_init,
326};
327
175static void __init realview_eb_init(void) 328static void __init realview_eb_init(void)
176{ 329{
177 int i; 330 int i;
178 331
179#ifdef CONFIG_REALVIEW_MPCORE 332 if (core_tile_eb11mp()) {
180 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled 333 realview_eb11mp_fixup();
181 * Bits: .... ...0 0111 1001 0000 .... .... .... */ 334
182 l2x0_init(__io_address(REALVIEW_MPCORE_L220_BASE), 0x00790000, 0xfe000fff); 335 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
183#endif 336 * Bits: .... ...0 0111 1001 0000 .... .... .... */
337 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
338 }
339
184 clk_register(&realview_clcd_clk); 340 clk_register(&realview_clcd_clk);
185 341
186 platform_device_register(&realview_flash_device); 342 platform_device_register(&realview_flash_device);
187 platform_device_register(&realview_smc91x_device); 343 platform_device_register(&realview_eb_smc91x_device);
188 platform_device_register(&realview_i2c_device); 344 platform_device_register(&realview_i2c_device);
189 345
190 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 346 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
@@ -204,6 +360,6 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
204 .boot_params = 0x00000100, 360 .boot_params = 0x00000100,
205 .map_io = realview_eb_map_io, 361 .map_io = realview_eb_map_io,
206 .init_irq = gic_init_irq, 362 .init_irq = gic_init_irq,
207 .timer = &realview_timer, 363 .timer = &realview_eb_timer,
208 .init_machine = realview_eb_init, 364 .init_machine = realview_eb_init,
209MACHINE_END 365MACHINE_END
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9e13c8358ea7..5c84c604ed86 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -470,7 +470,7 @@ void __init sa1110_mb_disable(void)
470 * If the system is going to use the SA-1111 DMA engines, set up 470 * If the system is going to use the SA-1111 DMA engines, set up
471 * the memory bus request/grant pins. 471 * the memory bus request/grant pins.
472 */ 472 */
473void __init sa1110_mb_enable(void) 473void __devinit sa1110_mb_enable(void)
474{ 474{
475 unsigned long flags; 475 unsigned long flags;
476 476
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index ba3d21d8fba3..6fe481ff4fdf 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -57,8 +57,6 @@ unsigned long iop_gettimeoffset(void)
57static irqreturn_t 57static irqreturn_t
58iop_timer_interrupt(int irq, void *dev_id) 58iop_timer_interrupt(int irq, void *dev_id)
59{ 59{
60 write_seqlock(&xtime_lock);
61
62 write_tisr(1); 60 write_tisr(1);
63 61
64 while ((signed long)(next_jiffy_time - read_tcr1()) 62 while ((signed long)(next_jiffy_time - read_tcr1())
@@ -67,8 +65,6 @@ iop_timer_interrupt(int irq, void *dev_id)
67 next_jiffy_time -= ticks_per_jiffy; 65 next_jiffy_time -= ticks_per_jiffy;
68 } 66 }
69 67
70 write_sequnlock(&xtime_lock);
71
72 return IRQ_HANDLED; 68 return IRQ_HANDLED;
73} 69}
74 70
diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c
index 2ec1daaa0e53..766473b3f98b 100644
--- a/arch/arm/plat-s3c24xx/time.c
+++ b/arch/arm/plat-s3c24xx/time.c
@@ -130,9 +130,7 @@ static unsigned long s3c2410_gettimeoffset (void)
130static irqreturn_t 130static irqreturn_t
131s3c2410_timer_interrupt(int irq, void *dev_id) 131s3c2410_timer_interrupt(int irq, void *dev_id)
132{ 132{
133 write_seqlock(&xtime_lock);
134 timer_tick(); 133 timer_tick();
135 write_sequnlock(&xtime_lock);
136 return IRQ_HANDLED; 134 return IRQ_HANDLED;
137} 135}
138 136
diff --git a/drivers/pcmcia/sa1100_jornada720.c b/drivers/pcmcia/sa1100_jornada720.c
index af485ae38602..6284c35dabc6 100644
--- a/drivers/pcmcia/sa1100_jornada720.c
+++ b/drivers/pcmcia/sa1100_jornada720.c
@@ -101,7 +101,7 @@ static struct pcmcia_low_level jornada720_pcmcia_ops = {
101 .socket_suspend = sa1111_pcmcia_socket_suspend, 101 .socket_suspend = sa1111_pcmcia_socket_suspend,
102}; 102};
103 103
104int __init pcmcia_jornada720_init(struct device *dev) 104int __devinit pcmcia_jornada720_init(struct device *dev)
105{ 105{
106 int ret = -ENODEV; 106 int ret = -ENODEV;
107 107
diff --git a/drivers/serial/21285.c b/drivers/serial/21285.c
index 6a48dfa1efe8..0276471cb25e 100644
--- a/drivers/serial/21285.c
+++ b/drivers/serial/21285.c
@@ -237,6 +237,12 @@ serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
237 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 237 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
238 quot = uart_get_divisor(port, baud); 238 quot = uart_get_divisor(port, baud);
239 239
240 if (port->info && port->info->tty) {
241 struct tty_struct *tty = port->info->tty;
242 unsigned int b = port->uartclk / (16 * quot);
243 tty_encode_baud_rate(tty, b, b);
244 }
245
240 switch (termios->c_cflag & CSIZE) { 246 switch (termios->c_cflag & CSIZE) {
241 case CS5: 247 case CS5:
242 h_lcr = 0x00; 248 h_lcr = 0x00;
@@ -277,8 +283,6 @@ serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
277 if (termios->c_iflag & INPCK) 283 if (termios->c_iflag & INPCK)
278 port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY; 284 port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
279 285
280 tty_encode_baud_rate(tty, baud, baud);
281
282 /* 286 /*
283 * Which character status flags should we ignore? 287 * Which character status flags should we ignore?
284 */ 288 */
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
index 111da57f5334..60f52904aad0 100644
--- a/drivers/serial/atmel_serial.c
+++ b/drivers/serial/atmel_serial.c
@@ -34,6 +34,7 @@
34#include <linux/tty_flip.h> 34#include <linux/tty_flip.h>
35#include <linux/platform_device.h> 35#include <linux/platform_device.h>
36#include <linux/atmel_pdc.h> 36#include <linux/atmel_pdc.h>
37#include <linux/atmel_serial.h>
37 38
38#include <asm/io.h> 39#include <asm/io.h>
39 40
@@ -45,8 +46,6 @@
45#include <asm/arch/gpio.h> 46#include <asm/arch/gpio.h>
46#endif 47#endif
47 48
48#include "atmel_serial.h"
49
50#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 49#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
51#define SUPPORT_SYSRQ 50#define SUPPORT_SYSRQ
52#endif 51#endif
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h
index c2e11cc374ba..1551fc24eb43 100644
--- a/include/asm-arm/arch-at91/at91_mci.h
+++ b/include/asm-arm/arch-at91/at91_mci.h
@@ -89,7 +89,7 @@
89#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ 89#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
90#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ 90#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
91#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ 91#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
92#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */ 92#define AT91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B */
93#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ 93#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
94#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ 94#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
95#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ 95#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h
index 802891a9cd81..e8fc0b1c33f4 100644
--- a/include/asm-arm/arch-at91/at91rm9200.h
+++ b/include/asm-arm/arch-at91/at91rm9200.h
@@ -93,6 +93,11 @@
93#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ 93#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
94#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ 94#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
95 95
96#define AT91_USART0 AT91RM9200_BASE_US0
97#define AT91_USART1 AT91RM9200_BASE_US1
98#define AT91_USART2 AT91RM9200_BASE_US2
99#define AT91_USART3 AT91RM9200_BASE_US3
100
96#define AT91_MATRIX 0 /* not supported */ 101#define AT91_MATRIX 0 /* not supported */
97 102
98/* 103/*
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index 0427f8698c07..c8934fe34dc5 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -99,6 +99,13 @@
99#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 99#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
100#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 100#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
101 101
102#define AT91_USART0 AT91SAM9260_BASE_US0
103#define AT91_USART1 AT91SAM9260_BASE_US1
104#define AT91_USART2 AT91SAM9260_BASE_US2
105#define AT91_USART3 AT91SAM9260_BASE_US3
106#define AT91_USART4 AT91SAM9260_BASE_US4
107#define AT91_USART5 AT91SAM9260_BASE_US5
108
102 109
103/* 110/*
104 * Internal Memory. 111 * Internal Memory.
diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h
index 9eb459570330..c7c4778dac49 100644
--- a/include/asm-arm/arch-at91/at91sam9261.h
+++ b/include/asm-arm/arch-at91/at91sam9261.h
@@ -84,6 +84,10 @@
84#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 84#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
85#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 85#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
86 86
87#define AT91_USART0 AT91SAM9261_BASE_US0
88#define AT91_USART1 AT91SAM9261_BASE_US1
89#define AT91_USART2 AT91SAM9261_BASE_US2
90
87 91
88/* 92/*
89 * Internal Memory. 93 * Internal Memory.
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
index 115c47ac7ebb..018a647311da 100644
--- a/include/asm-arm/arch-at91/at91sam9263.h
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -101,6 +101,10 @@
101#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) 101#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
102#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 102#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
103 103
104#define AT91_USART0 AT91SAM9263_BASE_US0
105#define AT91_USART1 AT91SAM9263_BASE_US1
106#define AT91_USART2 AT91SAM9263_BASE_US2
107
104#define AT91_SMC AT91_SMC0 108#define AT91_SMC AT91_SMC0
105 109
106/* 110/*
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
index 8a9708a370c6..16d2832f6c0a 100644
--- a/include/asm-arm/arch-at91/at91sam9rl.h
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -94,6 +94,11 @@
94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
95#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) 95#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
96 96
97#define AT91_USART0 AT91SAM9RL_BASE_US0
98#define AT91_USART1 AT91SAM9RL_BASE_US1
99#define AT91_USART2 AT91SAM9RL_BASE_US2
100#define AT91_USART3 AT91SAM9RL_BASE_US3
101
97 102
98/* 103/*
99 * Internal Memory. 104 * Internal Memory.
diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h
index 272a7e0dc6cf..f5636a8f6132 100644
--- a/include/asm-arm/arch-at91/uncompress.h
+++ b/include/asm-arm/arch-at91/uncompress.h
@@ -22,7 +22,23 @@
22#define __ASM_ARCH_UNCOMPRESS_H 22#define __ASM_ARCH_UNCOMPRESS_H
23 23
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/arch/at91_dbgu.h> 25#include <linux/atmel_serial.h>
26
27#if defined(CONFIG_AT91_EARLY_DBGU)
28#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS)
29#elif defined(CONFIG_AT91_EARLY_USART0)
30#define UART_OFFSET AT91_USART0
31#elif defined(CONFIG_AT91_EARLY_USART1)
32#define UART_OFFSET AT91_USART1
33#elif defined(CONFIG_AT91_EARLY_USART2)
34#define UART_OFFSET AT91_USART2
35#elif defined(CONFIG_AT91_EARLY_USART3)
36#define UART_OFFSET AT91_USART3
37#elif defined(CONFIG_AT91_EARLY_USART4)
38#define UART_OFFSET AT91_USART4
39#elif defined(CONFIG_AT91_EARLY_USART5)
40#define UART_OFFSET AT91_USART5
41#endif
26 42
27/* 43/*
28 * The following code assumes the serial port has already been 44 * The following code assumes the serial port has already been
@@ -33,22 +49,22 @@
33 */ 49 */
34static void putc(int c) 50static void putc(int c)
35{ 51{
36#ifdef AT91_DBGU 52#ifdef UART_OFFSET
37 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ 53 void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */
38 54
39 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) 55 while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY))
40 barrier(); 56 barrier();
41 __raw_writel(c, sys + AT91_DBGU_THR); 57 __raw_writel(c, sys + ATMEL_US_THR);
42#endif 58#endif
43} 59}
44 60
45static inline void flush(void) 61static inline void flush(void)
46{ 62{
47#ifdef AT91_DBGU 63#ifdef UART_OFFSET
48 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ 64 void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */
49 65
50 /* wait for transmission to complete */ 66 /* wait for transmission to complete */
51 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) 67 while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
52 barrier(); 68 barrier();
53#endif 69#endif
54} 70}
diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h
index d2523b326c6c..2fa3d6b8dbb8 100644
--- a/include/asm-arm/arch-ixp4xx/cpu.h
+++ b/include/asm-arm/arch-ixp4xx/cpu.h
@@ -28,4 +28,19 @@ extern unsigned int processor_id;
28#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ 28#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
29 IXP465_PROCESSOR_ID_VALUE) 29 IXP465_PROCESSOR_ID_VALUE)
30 30
31static inline u32 ixp4xx_read_feature_bits(void)
32{
33 unsigned int val = ~*IXP4XX_EXP_CFG2;
34 val &= ~IXP4XX_FEATURE_RESERVED;
35 if (!cpu_is_ixp46x())
36 val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
37
38 return val;
39}
40
41static inline void ixp4xx_write_feature_bits(u32 value)
42{
43 *IXP4XX_EXP_CFG2 = ~value;
44}
45
31#endif /* _ASM_ARCH_CPU_H */ 46#endif /* _ASM_ARCH_CPU_H */
diff --git a/include/asm-arm/arch-ixp4xx/dsmg600.h b/include/asm-arm/arch-ixp4xx/dsmg600.h
index a19605ad240d..b7673e171abe 100644
--- a/include/asm-arm/arch-ixp4xx/dsmg600.h
+++ b/include/asm-arm/arch-ixp4xx/dsmg600.h
@@ -40,18 +40,13 @@
40/* Buttons */ 40/* Buttons */
41 41
42#define DSMG600_PB_GPIO 15 /* power button */ 42#define DSMG600_PB_GPIO 15 /* power button */
43#define DSMG600_PB_BM (1L << DSMG600_PB_GPIO)
44
45#define DSMG600_RB_GPIO 3 /* reset button */ 43#define DSMG600_RB_GPIO 3 /* reset button */
46 44
47#define DSMG600_RB_IRQ IRQ_IXP4XX_GPIO3 45/* Power control */
48 46
49#define DSMG600_PO_GPIO 2 /* power off */ 47#define DSMG600_PO_GPIO 2 /* power off */
50 48
51/* LEDs */ 49/* LEDs */
52 50
53#define DSMG600_LED_PWR_GPIO 0 51#define DSMG600_LED_PWR_GPIO 0
54#define DSMG600_LED_PWR_BM (1L << DSMG600_LED_PWR_GPIO)
55
56#define DSMG600_LED_WLAN_GPIO 14 52#define DSMG600_LED_WLAN_GPIO 14
57#define DSMG600_LED_WLAN_BM (1L << DSMG600_LED_WLAN_GPIO)
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
index 297ceda08b61..73e8dc36f6a4 100644
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -27,13 +27,13 @@
27 27
28#define pcibios_assign_all_busses() 1 28#define pcibios_assign_all_busses() 1
29 29
30/* Register locations and bits */
31#include "ixp4xx-regs.h"
32
30#ifndef __ASSEMBLER__ 33#ifndef __ASSEMBLER__
31#include <asm/arch/cpu.h> 34#include <asm/arch/cpu.h>
32#endif 35#endif
33 36
34/* Register locations and bits */
35#include "ixp4xx-regs.h"
36
37/* Platform helper functions and definitions */ 37/* Platform helper functions and definitions */
38#include "platform.h" 38#include "platform.h"
39 39
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index 9c5d2357aff3..de181ce958db 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARM_ARCH_IO_H 13#ifndef __ASM_ARM_ARCH_IO_H
14#define __ASM_ARM_ARCH_IO_H 14#define __ASM_ARM_ARCH_IO_H
15 15
16#include <linux/bitops.h>
17
16#include <asm/hardware.h> 18#include <asm/hardware.h>
17 19
18#define IO_SPACE_LIMIT 0xffff0000 20#define IO_SPACE_LIMIT 0xffff0000
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
index 5d949d763a91..c704fe8cf42f 100644
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -15,10 +15,6 @@
15 * 15 *
16 */ 16 */
17 17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <asm/hardware.h>"
20#endif
21
22#ifndef _ASM_ARM_IXP4XX_H_ 18#ifndef _ASM_ARM_IXP4XX_H_
23#define _ASM_ARM_IXP4XX_H_ 19#define _ASM_ARM_IXP4XX_H_
24 20
@@ -607,4 +603,36 @@
607 603
608#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ 604#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
609 605
606/* "fuse" bits of IXP_EXP_CFG2 */
607#define IXP4XX_FEATURE_RCOMP (1 << 0)
608#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
609#define IXP4XX_FEATURE_HASH (1 << 2)
610#define IXP4XX_FEATURE_AES (1 << 3)
611#define IXP4XX_FEATURE_DES (1 << 4)
612#define IXP4XX_FEATURE_HDLC (1 << 5)
613#define IXP4XX_FEATURE_AAL (1 << 6)
614#define IXP4XX_FEATURE_HSS (1 << 7)
615#define IXP4XX_FEATURE_UTOPIA (1 << 8)
616#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
617#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
618#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
619#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
620#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
621#define IXP4XX_FEATURE_PCI (1 << 14)
622#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
623#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
624#define IXP4XX_FEATURE_USB_HOST (1 << 18)
625#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
626#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
627#define IXP4XX_FEATURE_RSA (1 << 21)
628#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
629#define IXP4XX_FEATURE_RESERVED (0xFF << 24)
630
631#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
632 IXP4XX_FEATURE_USB_HOST | \
633 IXP4XX_FEATURE_NPEA_ETH | \
634 IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
635 IXP4XX_FEATURE_RSA | \
636 IXP4XX_FEATURE_XSCALE_MAX_FREQ)
637
610#endif 638#endif
diff --git a/include/asm-arm/arch-ixp4xx/nas100d.h b/include/asm-arm/arch-ixp4xx/nas100d.h
index 131e0a1d0df3..98d937897bce 100644
--- a/include/asm-arm/arch-ixp4xx/nas100d.h
+++ b/include/asm-arm/arch-ixp4xx/nas100d.h
@@ -38,15 +38,15 @@
38 38
39/* Buttons */ 39/* Buttons */
40 40
41#define NAS100D_PB_GPIO 14 41#define NAS100D_PB_GPIO 14 /* power button */
42#define NAS100D_RB_GPIO 4 42#define NAS100D_RB_GPIO 4 /* reset button */
43
44/* Power control */
45
43#define NAS100D_PO_GPIO 12 /* power off */ 46#define NAS100D_PO_GPIO 12 /* power off */
44 47
45#define NAS100D_PB_IRQ IRQ_IXP4XX_GPIO14 48/* LEDs */
46#define NAS100D_RB_IRQ IRQ_IXP4XX_GPIO4
47 49
48/* 50#define NAS100D_LED_WLAN_GPIO 0
49#define NAS100D_PB_BM (1L << NAS100D_PB_GPIO) 51#define NAS100D_LED_DISK_GPIO 3
50#define NAS100D_PO_BM (1L << NAS100D_PO_GPIO) 52#define NAS100D_LED_PWR_GPIO 15
51#define NAS100D_RB_BM (1L << NAS100D_RB_GPIO)
52*/
diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/include/asm-arm/arch-ixp4xx/npe.h
new file mode 100644
index 000000000000..37d0511689dc
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/npe.h
@@ -0,0 +1,39 @@
1#ifndef __IXP4XX_NPE_H
2#define __IXP4XX_NPE_H
3
4#include <linux/kernel.h>
5
6extern const char *npe_names[];
7
8struct npe_regs {
9 u32 exec_addr, exec_data, exec_status_cmd, exec_count;
10 u32 action_points[4];
11 u32 watchpoint_fifo, watch_count;
12 u32 profile_count;
13 u32 messaging_status, messaging_control;
14 u32 mailbox_status, /*messaging_*/ in_out_fifo;
15};
16
17struct npe {
18 struct resource *mem_res;
19 struct npe_regs __iomem *regs;
20 u32 regs_phys;
21 int id;
22 int valid;
23};
24
25
26static inline const char *npe_name(struct npe *npe)
27{
28 return npe_names[npe->id];
29}
30
31int npe_running(struct npe *npe);
32int npe_send_message(struct npe *npe, const void *msg, const char *what);
33int npe_recv_message(struct npe *npe, void *msg, const char *what);
34int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
35int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
36struct npe *npe_request(int id);
37void npe_release(struct npe *npe);
38
39#endif /* __IXP4XX_NPE_H */
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h
index 850fdc5b45da..714bbc65126a 100644
--- a/include/asm-arm/arch-ixp4xx/nslu2.h
+++ b/include/asm-arm/arch-ixp4xx/nslu2.h
@@ -39,34 +39,17 @@
39 39
40/* Buttons */ 40/* Buttons */
41 41
42#define NSLU2_PB_GPIO 5 42#define NSLU2_PB_GPIO 5 /* power button */
43#define NSLU2_PO_GPIO 8 /* power off */ 43#define NSLU2_PO_GPIO 8 /* power off */
44#define NSLU2_RB_GPIO 12 44#define NSLU2_RB_GPIO 12 /* reset button */
45
46#define NSLU2_PB_IRQ IRQ_IXP4XX_GPIO5
47#define NSLU2_RB_IRQ IRQ_IXP4XX_GPIO12
48
49#define NSLU2_PB_BM (1L << NSLU2_PB_GPIO)
50#define NSLU2_PO_BM (1L << NSLU2_PO_GPIO)
51#define NSLU2_RB_BM (1L << NSLU2_RB_GPIO)
52 45
53/* Buzzer */ 46/* Buzzer */
54 47
55#define NSLU2_GPIO_BUZZ 4 48#define NSLU2_GPIO_BUZZ 4
56#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ)
57 49
58/* LEDs */ 50/* LEDs */
59 51
60#define NSLU2_LED_RED_GPIO 0 52#define NSLU2_LED_RED_GPIO 0
61#define NSLU2_LED_GRN_GPIO 1 53#define NSLU2_LED_GRN_GPIO 1
62
63#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED_GPIO)
64#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN_GPIO)
65
66#define NSLU2_LED_DISK1_GPIO 3 54#define NSLU2_LED_DISK1_GPIO 3
67#define NSLU2_LED_DISK2_GPIO 2 55#define NSLU2_LED_DISK2_GPIO 2
68
69#define NSLU2_LED_DISK1_BM (1L << NSLU2_LED_DISK1_GPIO)
70#define NSLU2_LED_DISK2_BM (1L << NSLU2_LED_DISK2_GPIO)
71
72
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index 2ce28e3fd325..a1f2b5404db1 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -91,6 +91,27 @@ struct ixp4xx_pata_data {
91 91
92struct sys_timer; 92struct sys_timer;
93 93
94#define IXP4XX_ETH_NPEA 0x00
95#define IXP4XX_ETH_NPEB 0x10
96#define IXP4XX_ETH_NPEC 0x20
97
98/* Information about built-in Ethernet MAC interfaces */
99struct eth_plat_info {
100 u8 phy; /* MII PHY ID, 0 - 31 */
101 u8 rxq; /* configurable, currently 0 - 31 only */
102 u8 txreadyq;
103 u8 hwaddr[6];
104};
105
106/* Information about built-in HSS (synchronous serial) interfaces */
107struct hss_plat_info {
108 int (*set_clock)(int port, unsigned int clock_type);
109 int (*open)(int port, void *pdev,
110 void (*set_carrier_cb)(void *pdev, int carrier));
111 void (*close)(int port, void *pdev);
112 u8 txreadyq;
113};
114
94/* 115/*
95 * Frequency of clock used for primary clocksource 116 * Frequency of clock used for primary clocksource
96 */ 117 */
diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/include/asm-arm/arch-ixp4xx/qmgr.h
new file mode 100644
index 000000000000..1e52b95cede5
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/qmgr.h
@@ -0,0 +1,126 @@
1/*
2 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9#ifndef IXP4XX_QMGR_H
10#define IXP4XX_QMGR_H
11
12#include <linux/io.h>
13#include <linux/kernel.h>
14
15#define HALF_QUEUES 32
16#define QUEUES 64 /* only 32 lower queues currently supported */
17#define MAX_QUEUE_LENGTH 4 /* in dwords */
18
19#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
20#define QUEUE_STAT1_NEARLY_EMPTY 2
21#define QUEUE_STAT1_NEARLY_FULL 4
22#define QUEUE_STAT1_FULL 8
23#define QUEUE_STAT2_UNDERFLOW 1
24#define QUEUE_STAT2_OVERFLOW 2
25
26#define QUEUE_WATERMARK_0_ENTRIES 0
27#define QUEUE_WATERMARK_1_ENTRY 1
28#define QUEUE_WATERMARK_2_ENTRIES 2
29#define QUEUE_WATERMARK_4_ENTRIES 3
30#define QUEUE_WATERMARK_8_ENTRIES 4
31#define QUEUE_WATERMARK_16_ENTRIES 5
32#define QUEUE_WATERMARK_32_ENTRIES 6
33#define QUEUE_WATERMARK_64_ENTRIES 7
34
35/* queue interrupt request conditions */
36#define QUEUE_IRQ_SRC_EMPTY 0
37#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
38#define QUEUE_IRQ_SRC_NEARLY_FULL 2
39#define QUEUE_IRQ_SRC_FULL 3
40#define QUEUE_IRQ_SRC_NOT_EMPTY 4
41#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
42#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
43#define QUEUE_IRQ_SRC_NOT_FULL 7
44
45struct qmgr_regs {
46 u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
47 u32 stat1[4]; /* 0x400 - 0x40F */
48 u32 stat2[2]; /* 0x410 - 0x417 */
49 u32 statne_h; /* 0x418 - queue nearly empty */
50 u32 statf_h; /* 0x41C - queue full */
51 u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
52 u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
53 u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
54 u32 reserved[1776];
55 u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
56};
57
58void qmgr_set_irq(unsigned int queue, int src,
59 void (*handler)(void *pdev), void *pdev);
60void qmgr_enable_irq(unsigned int queue);
61void qmgr_disable_irq(unsigned int queue);
62
63/* request_ and release_queue() must be called from non-IRQ context */
64int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
65 unsigned int nearly_empty_watermark,
66 unsigned int nearly_full_watermark);
67void qmgr_release_queue(unsigned int queue);
68
69
70static inline void qmgr_put_entry(unsigned int queue, u32 val)
71{
72 extern struct qmgr_regs __iomem *qmgr_regs;
73 __raw_writel(val, &qmgr_regs->acc[queue][0]);
74}
75
76static inline u32 qmgr_get_entry(unsigned int queue)
77{
78 extern struct qmgr_regs __iomem *qmgr_regs;
79 return __raw_readl(&qmgr_regs->acc[queue][0]);
80}
81
82static inline int qmgr_get_stat1(unsigned int queue)
83{
84 extern struct qmgr_regs __iomem *qmgr_regs;
85 return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
86 >> ((queue & 7) << 2)) & 0xF;
87}
88
89static inline int qmgr_get_stat2(unsigned int queue)
90{
91 extern struct qmgr_regs __iomem *qmgr_regs;
92 return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
93 >> ((queue & 0xF) << 1)) & 0x3;
94}
95
96static inline int qmgr_stat_empty(unsigned int queue)
97{
98 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
99}
100
101static inline int qmgr_stat_nearly_empty(unsigned int queue)
102{
103 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
104}
105
106static inline int qmgr_stat_nearly_full(unsigned int queue)
107{
108 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
109}
110
111static inline int qmgr_stat_full(unsigned int queue)
112{
113 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
114}
115
116static inline int qmgr_stat_underflow(unsigned int queue)
117{
118 return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
119}
120
121static inline int qmgr_stat_overflow(unsigned int queue)
122{
123 return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
124}
125
126#endif
diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
index f7a35b78823f..34ef48fe327e 100644
--- a/include/asm-arm/arch-ixp4xx/uncompress.h
+++ b/include/asm-arm/arch-ixp4xx/uncompress.h
@@ -13,7 +13,7 @@
13#ifndef _ARCH_UNCOMPRESS_H_ 13#ifndef _ARCH_UNCOMPRESS_H_
14#define _ARCH_UNCOMPRESS_H_ 14#define _ARCH_UNCOMPRESS_H_
15 15
16#include <asm/hardware.h> 16#include "ixp4xx-regs.h"
17#include <asm/mach-types.h> 17#include <asm/mach-types.h>
18#include <linux/serial_reg.h> 18#include <linux/serial_reg.h>
19 19
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
index 66d54119757c..8e1b3ead827f 100644
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -12,6 +12,19 @@
12 12
13#ifndef __ASM_ARCH_PXA3XX_REGS_H 13#ifndef __ASM_ARCH_PXA3XX_REGS_H
14#define __ASM_ARCH_PXA3XX_REGS_H 14#define __ASM_ARCH_PXA3XX_REGS_H
15/*
16 * Service Power Management Unit (MPMU)
17 */
18#define PMCR __REG(0x40F50000) /* Power Manager Control Register */
19#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
20#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
21#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
22#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
23#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
24#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
25#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
26#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
27#define PCMD(x) __REG(0x40F50110 + ((x) << 2))
15 28
16/* 29/*
17 * Slave Power Managment Unit 30 * Slave Power Managment Unit
diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h
new file mode 100644
index 000000000000..3e437b7f425a
--- /dev/null
+++ b/include/asm-arm/arch-realview/board-eb.h
@@ -0,0 +1,171 @@
1/*
2 * include/asm-arm/arch-realview/board-eb.h
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#ifndef __ASM_ARCH_BOARD_EB_H
22#define __ASM_ARCH_BOARD_EB_H
23
24#include <asm/arch/platform.h>
25
26/*
27 * RealView EB + ARM11MPCore peripheral addresses
28 */
29#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
30#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
31#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
32#define REALVIEW_EB11MP_TWD_BASE 0x10100700
33#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
34#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
35#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
36#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
37#else
38#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */
39#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
40#define REALVIEW_EB11MP_TWD_BASE 0x1F000700
41#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
42#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
43#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
44#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
45#endif
46
47#define IRQ_EB_GIC_START 32
48
49/*
50 * RealView EB interrupt sources
51 */
52#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */
53#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */
54#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */
55#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */
56#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */
57#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */
58#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */
59#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */
60#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */
61 /* 9 reserved */
62#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */
63#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */
64#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */
65#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */
66#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */
67#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */
68#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */
69#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */
70#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */
71#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */
72#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */
73#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */
74#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */
75#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */
76#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */
77#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */
78#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */
79#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */
80#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */
81#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */
82#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */
83#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */
84
85/*
86 * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
87 */
88#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0)
89#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1)
90#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2)
91#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3)
92#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4)
93#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5)
94#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6)
95#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7)
96#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8)
97#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9)
98#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */
99#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */
100#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */
101#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */
102#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14)
103#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15)
104
105#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17)
106#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18)
107#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19)
108#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20)
109#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21)
110#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22)
111#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23)
112#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24)
113#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25)
114#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26)
115#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27)
116#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28)
117
118#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29)
119#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
120#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
121
122#define IRQ_EB11MP_UART2 -1
123#define IRQ_EB11MP_UART3 -1
124#define IRQ_EB11MP_CLCD -1
125#define IRQ_EB11MP_DMA -1
126#define IRQ_EB11MP_WDOG -1
127#define IRQ_EB11MP_GPIO0 -1
128#define IRQ_EB11MP_GPIO1 -1
129#define IRQ_EB11MP_GPIO2 -1
130#define IRQ_EB11MP_SCI -1
131#define IRQ_EB11MP_SSP -1
132
133#define NR_GIC_EB11MP 2
134
135/*
136 * Only define NR_IRQS if less than NR_IRQS_EB
137 */
138#define NR_IRQS_EB (IRQ_EB_GIC_START + 96)
139
140#if defined(CONFIG_MACH_REALVIEW_EB) \
141 && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
142#undef NR_IRQS
143#define NR_IRQS NR_IRQS_EB
144#endif
145
146#if defined(CONFIG_REALVIEW_EB_ARM11MP) \
147 && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
148#undef MAX_GIC_NR
149#define MAX_GIC_NR NR_GIC_EB11MP
150#endif
151
152/*
153 * Core tile identification (REALVIEW_SYS_PROCID)
154 */
155#define REALVIEW_EB_PROC_MASK 0xFF000000
156#define REALVIEW_EB_PROC_ARM7TDMI 0x00000000
157#define REALVIEW_EB_PROC_ARM9 0x02000000
158#define REALVIEW_EB_PROC_ARM11 0x04000000
159#define REALVIEW_EB_PROC_ARM11MP 0x06000000
160
161#define check_eb_proc(proc_type) \
162 ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \
163 == proc_type)
164
165#ifdef CONFIG_REALVIEW_EB_ARM11MP
166#define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP)
167#else
168#define core_tile_eb11mp() 0
169#endif
170
171#endif /* __ASM_ARCH_BOARD_EB_H */
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 3b4e2076603a..cd26306d8e57 100644
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -14,7 +14,8 @@
14 .endm 14 .endm
15 15
16 .macro get_irqnr_preamble, base, tmp 16 .macro get_irqnr_preamble, base, tmp
17 ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) 17 ldr \base, =gic_cpu_base_addr
18 ldr \base, [\base]
18 .endm 19 .endm
19 20
20 .macro arch_ret_to_user, tmp1, tmp2 21 .macro arch_ret_to_user, tmp1, tmp2
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h
index aa78fe087ab2..bad8d7ce9bfe 100644
--- a/include/asm-arm/arch-realview/hardware.h
+++ b/include/asm-arm/arch-realview/hardware.h
@@ -23,7 +23,6 @@
23#define __ASM_ARCH_HARDWARE_H 23#define __ASM_ARCH_HARDWARE_H
24 24
25#include <asm/sizes.h> 25#include <asm/sizes.h>
26#include <asm/arch/platform.h>
27 26
28/* macro to get at IO space when running virtually */ 27/* macro to get at IO space when running virtually */
29#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000) 28#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
index 5a5db56f86b8..ad0c911002fc 100644
--- a/include/asm-arm/arch-realview/irqs.h
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -19,103 +19,18 @@
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21 21
22#include <asm/arch/platform.h> 22#ifndef __ASM_ARCH_IRQS_H
23#define __ASM_ARCH_IRQS_H
23 24
24#define IRQ_LOCALTIMER 29 25#include <asm/arch/board-eb.h>
25#define IRQ_LOCALWDOG 30
26 26
27/* 27#define IRQ_LOCALTIMER 29
28 * IRQ interrupts definitions are the same the INT definitions 28#define IRQ_LOCALWDOG 30
29 * held within platform.h
30 */
31#define IRQ_GIC_START 32
32#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT)
33#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT)
34#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx)
35#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx)
36#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1)
37#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3)
38#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0)
39#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1)
40#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2)
41#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3)
42#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT)
43#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT)
44#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0)
45#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1)
46#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2)
47#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3)
48#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT)
49#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT)
50#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT)
51#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT)
52#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT)
53#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT)
54#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B)
55#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B)
56#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0)
57#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1)
58#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3)
59#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD)
60#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH)
61#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD)
62#define IRQ_DoC (IRQ_GIC_START + INT_DoC)
63#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A)
64#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A)
65#define IRQ_AACI (IRQ_GIC_START + INT_AACI)
66#define IRQ_ETH (IRQ_GIC_START + INT_ETH)
67#define IRQ_USB (IRQ_GIC_START + INT_USB)
68#define IRQ_PMU_CPU0 (IRQ_GIC_START + INT_PMU_CPU0)
69#define IRQ_PMU_CPU1 (IRQ_GIC_START + INT_PMU_CPU1)
70#define IRQ_PMU_CPU2 (IRQ_GIC_START + INT_PMU_CPU2)
71#define IRQ_PMU_CPU3 (IRQ_GIC_START + INT_PMU_CPU3)
72#define IRQ_PMU_SCU0 (IRQ_GIC_START + INT_PMU_SCU0)
73#define IRQ_PMU_SCU1 (IRQ_GIC_START + INT_PMU_SCU1)
74#define IRQ_PMU_SCU2 (IRQ_GIC_START + INT_PMU_SCU2)
75#define IRQ_PMU_SCU3 (IRQ_GIC_START + INT_PMU_SCU3)
76#define IRQ_PMU_SCU4 (IRQ_GIC_START + INT_PMU_SCU4)
77#define IRQ_PMU_SCU5 (IRQ_GIC_START + INT_PMU_SCU5)
78#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6)
79#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7)
80 29
81#define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1) 30#define IRQ_GIC_START 32
82#define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2)
83 31
84#define IRQMASK_WDOGINT INTMASK_WDOGINT 32#ifndef NR_IRQS
85#define IRQMASK_SOFTINT INTMASK_SOFTINT 33#error "NR_IRQS not defined by the board-specific files"
86#define IRQMASK_COMMRx INTMASK_COMMRx 34#endif
87#define IRQMASK_COMMTx INTMASK_COMMTx
88#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
89#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
90#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
91#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
92#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
93#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
94#define IRQMASK_RTCINT INTMASK_RTCINT
95#define IRQMASK_SSPINT INTMASK_SSPINT
96#define IRQMASK_UARTINT0 INTMASK_UARTINT0
97#define IRQMASK_UARTINT1 INTMASK_UARTINT1
98#define IRQMASK_UARTINT2 INTMASK_UARTINT2
99#define IRQMASK_SCIINT INTMASK_SCIINT
100#define IRQMASK_CLCDINT INTMASK_CLCDINT
101#define IRQMASK_DMAINT INTMASK_DMAINT
102#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
103#define IRQMASK_MBXINT INTMASK_MBXINT
104#define IRQMASK_GNDINT INTMASK_GNDINT
105#define IRQMASK_MMCI0B INTMASK_MMCI0B
106#define IRQMASK_MMCI1B INTMASK_MMCI1B
107#define IRQMASK_KMI0 INTMASK_KMI0
108#define IRQMASK_KMI1 INTMASK_KMI1
109#define IRQMASK_SCI3 INTMASK_SCI3
110#define IRQMASK_UART3 INTMASK_UART3
111#define IRQMASK_CLCD INTMASK_CLCD
112#define IRQMASK_TOUCH INTMASK_TOUCH
113#define IRQMASK_KEYPAD INTMASK_KEYPAD
114#define IRQMASK_DoC INTMASK_DoC
115#define IRQMASK_MMCI0A INTMASK_MMCI0A
116#define IRQMASK_MMCI1A INTMASK_MMCI1A
117#define IRQMASK_AACI INTMASK_AACI
118#define IRQMASK_ETH INTMASK_ETH
119#define IRQMASK_USB INTMASK_USB
120 35
121#define NR_IRQS (IRQ_GIC_START + 96) 36#endif
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index 6e0eab95a3a2..4fd351b5e4a2 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -18,8 +18,8 @@
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20 20
21#ifndef __address_h 21#ifndef __ASM_ARCH_PLATFORM_H
22#define __address_h 1 22#define __ASM_ARCH_PLATFORM_H
23 23
24/* 24/*
25 * Memory definitions 25 * Memory definitions
@@ -81,11 +81,12 @@
81#define REALVIEW_SYS_24MHz_OFFSET 0x5C 81#define REALVIEW_SYS_24MHz_OFFSET 0x5C
82#define REALVIEW_SYS_MISC_OFFSET 0x60 82#define REALVIEW_SYS_MISC_OFFSET 0x60
83#define REALVIEW_SYS_IOSEL_OFFSET 0x70 83#define REALVIEW_SYS_IOSEL_OFFSET 0x70
84#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80 84#define REALVIEW_SYS_PROCID_OFFSET 0x84
85#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84 85#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
86#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88 86#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
87#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C 87#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
88#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90 88#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
89#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
89 90
90#define REALVIEW_SYS_BASE 0x10000000 91#define REALVIEW_SYS_BASE 0x10000000
91#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) 92#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
@@ -114,6 +115,7 @@
114#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) 115#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
115#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) 116#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
116#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) 117#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
118#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
117#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) 119#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
118#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) 120#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
119#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) 121#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
@@ -203,30 +205,8 @@
203 /* Reserved 0x1001A000 - 0x1001FFFF */ 205 /* Reserved 0x1001A000 - 0x1001FFFF */
204#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ 206#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
205#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ 207#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
206#ifndef CONFIG_REALVIEW_MPCORE
207#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ 208#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
208#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ 209#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
209#else
210#ifdef CONFIG_REALVIEW_MPCORE_REVB
211#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
212#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
213#define REALVIEW_TWD_BASE 0x10100700
214#define REALVIEW_TWD_SIZE 0x00000100
215#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
216#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */
217#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
218#else
219#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
220#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
221#define REALVIEW_TWD_BASE 0x1F000700
222#define REALVIEW_TWD_SIZE 0x00000100
223#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
224#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */
225#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
226#endif
227#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
228#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
229#endif
230#define REALVIEW_SMC_BASE 0x10080000 /* SMC */ 210#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
231 /* Reserved 0x10090000 - 0x100EFFFF */ 211 /* Reserved 0x10090000 - 0x100EFFFF */
232 212
@@ -283,134 +263,6 @@
283#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ 263#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
284#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ 264#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
285 265
286/* ------------------------------------------------------------------------
287 * Interrupts - bit assignment (primary)
288 * ------------------------------------------------------------------------
289 */
290#ifndef CONFIG_REALVIEW_MPCORE
291#define INT_WDOGINT 0 /* Watchdog timer */
292#define INT_SOFTINT 1 /* Software interrupt */
293#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
294#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
295#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
296#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
297#define INT_GPIOINT0 6 /* GPIO 0 */
298#define INT_GPIOINT1 7 /* GPIO 1 */
299#define INT_GPIOINT2 8 /* GPIO 2 */
300/* 9 reserved */
301#define INT_RTCINT 10 /* Real Time Clock */
302#define INT_SSPINT 11 /* Synchronous Serial Port */
303#define INT_UARTINT0 12 /* UART 0 on development chip */
304#define INT_UARTINT1 13 /* UART 1 on development chip */
305#define INT_UARTINT2 14 /* UART 2 on development chip */
306#define INT_UARTINT3 15 /* UART 3 on development chip */
307#define INT_SCIINT 16 /* Smart Card Interface */
308#define INT_MMCI0A 17 /* Multimedia Card 0A */
309#define INT_MMCI0B 18 /* Multimedia Card 0B */
310#define INT_AACI 19 /* Audio Codec */
311#define INT_KMI0 20 /* Keyboard/Mouse port 0 */
312#define INT_KMI1 21 /* Keyboard/Mouse port 1 */
313#define INT_CHARLCD 22 /* Character LCD */
314#define INT_CLCDINT 23 /* CLCD controller */
315#define INT_DMAINT 24 /* DMA controller */
316#define INT_PWRFAILINT 25 /* Power failure */
317#define INT_PISMO 26
318#define INT_DoC 27 /* Disk on Chip memory controller */
319#define INT_ETH 28 /* Ethernet controller */
320#define INT_USB 29 /* USB controller */
321#define INT_TSPENINT 30 /* Touchscreen pen */
322#define INT_TSKPADINT 31 /* Touchscreen keypad */
323
324#else
325
326#define MAX_GIC_NR 2
327
328#define INT_AACI 0
329#define INT_TIMERINT0_1 1
330#define INT_TIMERINT2_3 2
331#define INT_USB 3
332#define INT_UARTINT0 4
333#define INT_UARTINT1 5
334#define INT_RTCINT 6
335#define INT_KMI0 7
336#define INT_KMI1 8
337#define INT_ETH 9
338#define INT_EB_IRQ1 10 /* main GIC */
339#define INT_EB_IRQ2 11 /* tile GIC */
340#define INT_EB_FIQ1 12 /* main GIC */
341#define INT_EB_FIQ2 13 /* tile GIC */
342#define INT_MMCI0A 14
343#define INT_MMCI0B 15
344
345#define INT_PMU_CPU0 17
346#define INT_PMU_CPU1 18
347#define INT_PMU_CPU2 19
348#define INT_PMU_CPU3 20
349#define INT_PMU_SCU0 21
350#define INT_PMU_SCU1 22
351#define INT_PMU_SCU2 23
352#define INT_PMU_SCU3 24
353#define INT_PMU_SCU4 25
354#define INT_PMU_SCU5 26
355#define INT_PMU_SCU6 27
356#define INT_PMU_SCU7 28
357
358#define INT_L220_EVENT 29
359#define INT_L220_SLAVE 30
360#define INT_L220_DECODE 31
361
362#define INT_UARTINT2 -1
363#define INT_UARTINT3 -1
364#define INT_CLCDINT -1
365#define INT_DMAINT -1
366#define INT_WDOGINT -1
367#define INT_GPIOINT0 -1
368#define INT_GPIOINT1 -1
369#define INT_GPIOINT2 -1
370#define INT_SCIINT -1
371#define INT_SSPINT -1
372#endif
373
374/*
375 * Interrupt bit positions
376 *
377 */
378#define INTMASK_WDOGINT (1 << INT_WDOGINT)
379#define INTMASK_SOFTINT (1 << INT_SOFTINT)
380#define INTMASK_COMMRx (1 << INT_COMMRx)
381#define INTMASK_COMMTx (1 << INT_COMMTx)
382#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
383#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
384#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
385#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
386#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
387#define INTMASK_RTCINT (1 << INT_RTCINT)
388#define INTMASK_SSPINT (1 << INT_SSPINT)
389#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
390#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
391#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
392#define INTMASK_UARTINT3 (1 << INT_UARTINT3)
393#define INTMASK_SCIINT (1 << INT_SCIINT)
394#define INTMASK_MMCI0A (1 << INT_MMCI0A)
395#define INTMASK_MMCI0B (1 << INT_MMCI0B)
396#define INTMASK_AACI (1 << INT_AACI)
397#define INTMASK_KMI0 (1 << INT_KMI0)
398#define INTMASK_KMI1 (1 << INT_KMI1)
399#define INTMASK_CHARLCD (1 << INT_CHARLCD)
400#define INTMASK_CLCDINT (1 << INT_CLCDINT)
401#define INTMASK_DMAINT (1 << INT_DMAINT)
402#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
403#define INTMASK_PISMO (1 << INT_PISMO)
404#define INTMASK_DoC (1 << INT_DoC)
405#define INTMASK_ETH (1 << INT_ETH)
406#define INTMASK_USB (1 << INT_USB)
407#define INTMASK_TSPENINT (1 << INT_TSPENINT)
408#define INTMASK_TSKPADINT (1 << INT_TSKPADINT)
409
410#define MAXIRQNUM 31
411#define MAXFIQNUM 31
412#define MAXSWINUM 31
413
414/* 266/*
415 * Application Flash 267 * Application Flash
416 * 268 *
@@ -463,6 +315,4 @@
463#define REALVIEW_CSR_BASE 0x10000000 315#define REALVIEW_CSR_BASE 0x10000000
464#define REALVIEW_CSR_SIZE 0x10000000 316#define REALVIEW_CSR_SIZE 0x10000000
465 317
466#endif 318#endif /* __ASM_ARCH_PLATFORM_H */
467
468/* END */
diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h
index cc293640178e..08b3db883c36 100644
--- a/include/asm-arm/arch-realview/scu.h
+++ b/include/asm-arm/arch-realview/scu.h
@@ -1,8 +1,8 @@
1#ifndef __ASMARM_ARCH_SCU_H 1#ifndef __ASMARM_ARCH_SCU_H
2#define __ASMARM_ARCH_SCU_H 2#define __ASMARM_ARCH_SCU_H
3 3
4#include <asm/arch/platform.h> 4#include <asm/arch/board-eb.h>
5 5
6#define SCU_BASE REALVIEW_MPCORE_SCU_BASE 6#define SCU_BASE REALVIEW_EB11MP_SCU_BASE
7 7
8#endif 8#endif
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
index f05631d76743..3d5c2db07a26 100644
--- a/include/asm-arm/arch-realview/uncompress.h
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -19,6 +19,8 @@
19 */ 19 */
20#include <asm/hardware.h> 20#include <asm/hardware.h>
21 21
22#include <asm/arch/platform.h>
23
22#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00)) 24#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
23#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c)) 25#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
24#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30)) 26#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
diff --git a/include/asm-arm/hardware/arm_twd.h b/include/asm-arm/hardware/arm_twd.h
index 131d5b40e072..e521b70713c8 100644
--- a/include/asm-arm/hardware/arm_twd.h
+++ b/include/asm-arm/hardware/arm_twd.h
@@ -1,7 +1,7 @@
1#ifndef __ASM_HARDWARE_TWD_H 1#ifndef __ASM_HARDWARE_TWD_H
2#define __ASM_HARDWARE_TWD_H 2#define __ASM_HARDWARE_TWD_H
3 3
4#define TWD_TIMER_LOAD 0x00 4#define TWD_TIMER_LOAD 0x00
5#define TWD_TIMER_COUNTER 0x04 5#define TWD_TIMER_COUNTER 0x04
6#define TWD_TIMER_CONTROL 0x08 6#define TWD_TIMER_CONTROL 0x08
7#define TWD_TIMER_INTSTAT 0x0C 7#define TWD_TIMER_INTSTAT 0x0C
@@ -13,4 +13,9 @@
13#define TWD_WDOG_RESETSTAT 0x30 13#define TWD_WDOG_RESETSTAT 0x30
14#define TWD_WDOG_DISABLE 0x34 14#define TWD_WDOG_DISABLE 0x34
15 15
16#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
17#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
18#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
19#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
20
16#endif 21#endif
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index f67acce387e7..af99636db400 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -61,6 +61,11 @@ extern void smp_cross_call(cpumask_t callmap);
61extern void smp_send_timer(void); 61extern void smp_send_timer(void);
62 62
63/* 63/*
64 * Broadcast a clock event to other CPUs.
65 */
66extern void smp_timer_broadcast(cpumask_t mask);
67
68/*
64 * Boot a secondary CPU, and assign it the specified idle task. 69 * Boot a secondary CPU, and assign it the specified idle task.
65 * This also gives us the initial stack to use for this CPU. 70 * This also gives us the initial stack to use for this CPU.
66 */ 71 */
@@ -96,11 +101,12 @@ extern void platform_cpu_die(unsigned int cpu);
96extern int platform_cpu_kill(unsigned int cpu); 101extern int platform_cpu_kill(unsigned int cpu);
97extern void platform_cpu_enable(unsigned int cpu); 102extern void platform_cpu_enable(unsigned int cpu);
98 103
99#ifdef CONFIG_LOCAL_TIMERS
100/* 104/*
101 * Setup a local timer interrupt for a CPU. 105 * Local timer interrupt handling function (can be IPI'ed).
102 */ 106 */
103extern void local_timer_setup(unsigned int cpu); 107extern void local_timer_interrupt(void);
108
109#ifdef CONFIG_LOCAL_TIMERS
104 110
105/* 111/*
106 * Stop a local timer interrupt. 112 * Stop a local timer interrupt.
@@ -114,10 +120,6 @@ extern int local_timer_ack(void);
114 120
115#else 121#else
116 122
117static inline void local_timer_setup(unsigned int cpu)
118{
119}
120
121static inline void local_timer_stop(unsigned int cpu) 123static inline void local_timer_stop(unsigned int cpu)
122{ 124{
123} 125}
@@ -125,6 +127,11 @@ static inline void local_timer_stop(unsigned int cpu)
125#endif 127#endif
126 128
127/* 129/*
130 * Setup a local timer interrupt for a CPU.
131 */
132extern void local_timer_setup(unsigned int cpu);
133
134/*
128 * show local interrupt info 135 * show local interrupt info
129 */ 136 */
130extern void show_local_irqs(struct seq_file *); 137extern void show_local_irqs(struct seq_file *);
diff --git a/drivers/serial/atmel_serial.h b/include/linux/atmel_serial.h
index e0141776517c..fd6833764d72 100644
--- a/drivers/serial/atmel_serial.h
+++ b/include/linux/atmel_serial.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * drivers/serial/atmel_serial.h 2 * include/linux/atmel_serial.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 18:07:32 -0500