3 files changed, 93 insertions, 9 deletions

diff --git a/arch/ia64/kernel/sal.c b/arch/ia64/kernel/sal.c
index acc0f132f86c..056f7a6eedc7 100644
--- a/arch/ia64/kernel/sal.c
+++ b/arch/ia64/kernel/sal.c
@@ -14,6 +14,7 @@
 #include <linux/spinlock.h>
 #include <linux/string.h>
 
+#include <asm/delay.h>
 #include <asm/page.h>
 #include <asm/sal.h>
 #include <asm/pal.h>
@@ -214,6 +215,78 @@ chk_nointroute_opt(void)
 static void __init sal_desc_ap_wakeup(void *p) { }
 #endif
 
+/*
+ * HP rx5670 firmware polls for interrupts during SAL_CACHE_FLUSH by reading
+ * cr.ivr, but it never writes cr.eoi.  This leaves any interrupt marked as
+ * "in-service" and masks other interrupts of equal or lower priority.
+ *
+ * HP internal defect reports: F1859, F2775, F3031.
+ */
+static int sal_cache_flush_drops_interrupts;
+
+static void __init
+check_sal_cache_flush (void)
+{
+        unsigned long flags, itv;
+        int cpu;
+        u64 vector;
+
+        cpu = get_cpu();
+        local_irq_save(flags);
+
+        /*
+         * Schedule a timer interrupt, wait until it's reported, and see if
+         * SAL_CACHE_FLUSH drops it.
+         */
+        itv = ia64_get_itv();
+        BUG_ON((itv & (1 << 16)) == 0);
+
+        ia64_set_itv(IA64_TIMER_VECTOR);
+        ia64_set_itm(ia64_get_itc() + 1000);
+
+        while (!ia64_get_irr(IA64_TIMER_VECTOR))
+                cpu_relax();
+
+        ia64_sal_cache_flush(3);
+
+        if (ia64_get_irr(IA64_TIMER_VECTOR)) {
+                vector = ia64_get_ivr();
+                ia64_eoi();
+                WARN_ON(vector != IA64_TIMER_VECTOR);
+        } else {
+                sal_cache_flush_drops_interrupts = 1;
+                printk(KERN_ERR "SAL: SAL_CACHE_FLUSH drops interrupts; "
+                        "PAL_CACHE_FLUSH will be used instead\n");
+                ia64_eoi();
+        }
+
+        ia64_set_itv(itv);
+        local_irq_restore(flags);
+        put_cpu();
+}
+
+s64
+ia64_sal_cache_flush (u64 cache_type)
+{
+        struct ia64_sal_retval isrv;
+
+        if (sal_cache_flush_drops_interrupts) {
+                unsigned long flags;
+                u64 progress;
+                s64 rc;
+
+                progress = 0;
+                local_irq_save(flags);
+                rc = ia64_pal_cache_flush(cache_type,
+                        PAL_CACHE_FLUSH_INVALIDATE, &progress, NULL);
+                local_irq_restore(flags);
+                return rc;
+        }
+
+        SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type, 0, 0, 0, 0, 0, 0);
+        return isrv.status;
+}
+
 void __init
 ia64_sal_init (struct ia64_sal_systab *systab)
 {
@@ -262,6 +335,8 @@ ia64_sal_init (struct ia64_sal_systab *systab)
                 }
                 p += SAL_DESC_SIZE(*p);
         }
+
+        check_sal_cache_flush();
 }
 
 int
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index 09b99029ac1a..23c8e1be1911 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -559,6 +559,23 @@ ia64_eoi (void)
 
 #define cpu_relax()     ia64_hint(ia64_hint_pause)
 
+static inline int
+ia64_get_irr(unsigned int vector)
+{
+        unsigned int reg = vector / 64;
+        unsigned int bit = vector % 64;
+        u64 irr;
+
+        switch (reg) {
+        case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
+        case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
+        case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
+        case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
+        }
+
+        return test_bit(bit, &irr);
+}
+
 static inline void
 ia64_set_lrr0 (unsigned long val)
 {
diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h
index 313cad0628d0..0b210abbe003 100644
--- a/include/asm-ia64/sal.h
+++ b/include/asm-ia64/sal.h
@@ -658,15 +658,7 @@ ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
         return isrv.status;
 }
 
-/* Flush all the processor and platform level instruction and/or data caches */
-static inline s64
-ia64_sal_cache_flush (u64 cache_type)
-{
-        struct ia64_sal_retval isrv;
-        SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type, 0, 0, 0, 0, 0, 0);
-        return isrv.status;
-}
-
+extern s64 ia64_sal_cache_flush (u64 cache_type);
 
 /* Initialize all the processor and platform level instruction and data caches */
 static inline s64