diff options
-rw-r--r-- | arch/arm/mach-ixp4xx/common.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/coyote-pci.c | 3 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/ixdp425-pci.c | 5 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/ixdpg425-pci.c | 3 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/nslu2-pci.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/nslu2-power.c | 3 | ||||
-rw-r--r-- | include/asm-arm/arch-ixp4xx/platform.h | 5 |
7 files changed, 3 insertions, 28 deletions
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index f3c687cf0071..9f33cb21e7f3 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c | |||
@@ -142,6 +142,8 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) | |||
142 | *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << | 142 | *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << |
143 | (line * IXP4XX_GPIO_STYLE_SIZE)); | 143 | (line * IXP4XX_GPIO_STYLE_SIZE)); |
144 | 144 | ||
145 | *IXP4XX_GPIO_GPISR = (1 << line); | ||
146 | |||
145 | /* Set the new style */ | 147 | /* Set the new style */ |
146 | *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); | 148 | *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); |
147 | 149 | ||
@@ -169,7 +171,7 @@ static void ixp4xx_irq_ack(unsigned int irq) | |||
169 | int line = (irq < 32) ? irq2gpio[irq] : -1; | 171 | int line = (irq < 32) ? irq2gpio[irq] : -1; |
170 | 172 | ||
171 | if (line >= 0) | 173 | if (line >= 0) |
172 | gpio_line_isr_clear(line); | 174 | *IXP4XX_GPIO_GPISR = (1 << line); |
173 | } | 175 | } |
174 | 176 | ||
175 | /* | 177 | /* |
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index 60de8a94cff5..e6b7fcd923fa 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c | |||
@@ -33,9 +33,6 @@ void __init coyote_pci_preinit(void) | |||
33 | set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQT_LOW); | 33 | set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQT_LOW); |
34 | set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQT_LOW); | 34 | set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQT_LOW); |
35 | 35 | ||
36 | gpio_line_isr_clear(COYOTE_PCI_SLOT0_PIN); | ||
37 | gpio_line_isr_clear(COYOTE_PCI_SLOT1_PIN); | ||
38 | |||
39 | ixp4xx_pci_preinit(); | 36 | ixp4xx_pci_preinit(); |
40 | } | 37 | } |
41 | 38 | ||
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index f9a1d3e7d692..da415d5d7f37 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c | |||
@@ -32,11 +32,6 @@ void __init ixdp425_pci_preinit(void) | |||
32 | set_irq_type(IRQ_IXDP425_PCI_INTC, IRQT_LOW); | 32 | set_irq_type(IRQ_IXDP425_PCI_INTC, IRQT_LOW); |
33 | set_irq_type(IRQ_IXDP425_PCI_INTD, IRQT_LOW); | 33 | set_irq_type(IRQ_IXDP425_PCI_INTD, IRQT_LOW); |
34 | 34 | ||
35 | gpio_line_isr_clear(IXDP425_PCI_INTA_PIN); | ||
36 | gpio_line_isr_clear(IXDP425_PCI_INTB_PIN); | ||
37 | gpio_line_isr_clear(IXDP425_PCI_INTC_PIN); | ||
38 | gpio_line_isr_clear(IXDP425_PCI_INTD_PIN); | ||
39 | |||
40 | ixp4xx_pci_preinit(); | 35 | ixp4xx_pci_preinit(); |
41 | } | 36 | } |
42 | 37 | ||
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index fe5e7660de1d..526fb6175bc3 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c | |||
@@ -32,9 +32,6 @@ void __init ixdpg425_pci_preinit(void) | |||
32 | set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW); | 32 | set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW); |
33 | set_irq_type(IRQ_IXP4XX_GPIO7, IRQT_LOW); | 33 | set_irq_type(IRQ_IXP4XX_GPIO7, IRQT_LOW); |
34 | 34 | ||
35 | gpio_line_isr_clear(6); | ||
36 | gpio_line_isr_clear(7); | ||
37 | |||
38 | ixp4xx_pci_preinit(); | 35 | ixp4xx_pci_preinit(); |
39 | } | 36 | } |
40 | 37 | ||
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index a575f2e0b2c8..ece860444d5b 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c | |||
@@ -28,14 +28,6 @@ void __init nslu2_pci_preinit(void) | |||
28 | set_irq_type(IRQ_NSLU2_PCI_INTB, IRQT_LOW); | 28 | set_irq_type(IRQ_NSLU2_PCI_INTB, IRQT_LOW); |
29 | set_irq_type(IRQ_NSLU2_PCI_INTC, IRQT_LOW); | 29 | set_irq_type(IRQ_NSLU2_PCI_INTC, IRQT_LOW); |
30 | 30 | ||
31 | gpio_line_isr_clear(NSLU2_PCI_INTA_PIN); | ||
32 | gpio_line_isr_clear(NSLU2_PCI_INTB_PIN); | ||
33 | gpio_line_isr_clear(NSLU2_PCI_INTC_PIN); | ||
34 | |||
35 | /* INTD is not configured as GPIO is used | ||
36 | * for the power input button. | ||
37 | */ | ||
38 | |||
39 | ixp4xx_pci_preinit(); | 31 | ixp4xx_pci_preinit(); |
40 | } | 32 | } |
41 | 33 | ||
diff --git a/arch/arm/mach-ixp4xx/nslu2-power.c b/arch/arm/mach-ixp4xx/nslu2-power.c index 18fbc8c0fb30..b0ad9e901f6e 100644 --- a/arch/arm/mach-ixp4xx/nslu2-power.c +++ b/arch/arm/mach-ixp4xx/nslu2-power.c | |||
@@ -54,9 +54,6 @@ static int __init nslu2_power_init(void) | |||
54 | set_irq_type(NSLU2_RB_IRQ, IRQT_LOW); | 54 | set_irq_type(NSLU2_RB_IRQ, IRQT_LOW); |
55 | set_irq_type(NSLU2_PB_IRQ, IRQT_HIGH); | 55 | set_irq_type(NSLU2_PB_IRQ, IRQT_HIGH); |
56 | 56 | ||
57 | gpio_line_isr_clear(NSLU2_RB_GPIO); | ||
58 | gpio_line_isr_clear(NSLU2_PB_GPIO); | ||
59 | |||
60 | if (request_irq(NSLU2_RB_IRQ, &nslu2_reset_handler, | 57 | if (request_irq(NSLU2_RB_IRQ, &nslu2_reset_handler, |
61 | SA_INTERRUPT, "NSLU2 reset button", NULL) < 0) { | 58 | SA_INTERRUPT, "NSLU2 reset button", NULL) < 0) { |
62 | 59 | ||
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h index f14ed63590c3..6b77ed26be79 100644 --- a/include/asm-arm/arch-ixp4xx/platform.h +++ b/include/asm-arm/arch-ixp4xx/platform.h | |||
@@ -112,10 +112,5 @@ static inline void gpio_line_set(u8 line, int value) | |||
112 | *IXP4XX_GPIO_GPOUTR &= ~(1 << line); | 112 | *IXP4XX_GPIO_GPOUTR &= ~(1 << line); |
113 | } | 113 | } |
114 | 114 | ||
115 | static inline void gpio_line_isr_clear(u8 line) | ||
116 | { | ||
117 | *IXP4XX_GPIO_GPISR = (1 << line); | ||
118 | } | ||
119 | |||
120 | #endif // __ASSEMBLY__ | 115 | #endif // __ASSEMBLY__ |
121 | 116 | ||