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-rw-r--r--arch/ia64/configs/sn2_defconfig4
-rw-r--r--arch/ia64/hp/common/sba_iommu.c4
-rw-r--r--arch/ia64/hp/sim/simserial.c16
-rw-r--r--arch/ia64/kernel/entry.S110
-rw-r--r--arch/ia64/kernel/fsys.S147
-rw-r--r--arch/ia64/kernel/gate.S62
-rw-r--r--arch/ia64/kernel/ia64_ksyms.c3
-rw-r--r--arch/ia64/kernel/ivt.S198
-rw-r--r--arch/ia64/kernel/ptrace.c22
-rw-r--r--arch/ia64/kernel/setup.c12
-rw-r--r--arch/ia64/kernel/smp.c3
-rw-r--r--arch/ia64/sn/kernel/io_init.c2
-rw-r--r--arch/ia64/sn/kernel/iomv.c6
-rw-r--r--arch/ia64/sn/kernel/setup.c43
-rw-r--r--arch/ia64/sn/kernel/sn2/ptc_deadlock.S1
-rw-r--r--arch/ia64/sn/kernel/tiocx.c14
-rw-r--r--arch/ia64/sn/pci/tioca_provider.c8
-rw-r--r--drivers/firmware/pcdp.c24
-rw-r--r--drivers/firmware/pcdp.h33
-rw-r--r--include/asm-ia64/mmu_context.h3
-rw-r--r--include/asm-ia64/sn/addrs.h17
-rw-r--r--include/asm-ia64/sn/l1.h1
-rw-r--r--include/asm-ia64/sn/shub_mmr.h346
-rw-r--r--include/asm-ia64/sn/simulator.h13
-rw-r--r--include/asm-ia64/sn/sn2/sn_hwperf.h2
-rw-r--r--include/asm-ia64/sn/sn_sal.h10
-rw-r--r--include/asm-ia64/sn/tioca_provider.h1
-rw-r--r--include/asm-ia64/vga.h5
28 files changed, 660 insertions, 450 deletions
diff --git a/arch/ia64/configs/sn2_defconfig b/arch/ia64/configs/sn2_defconfig
index 487d2e36b0a6..c05613980300 100644
--- a/arch/ia64/configs/sn2_defconfig
+++ b/arch/ia64/configs/sn2_defconfig
@@ -99,7 +99,7 @@ CONFIG_ACPI_DEALLOCATE_IRQ=y
99# Firmware Drivers 99# Firmware Drivers
100# 100#
101CONFIG_EFI_VARS=y 101CONFIG_EFI_VARS=y
102# CONFIG_EFI_PCDP is not set 102CONFIG_EFI_PCDP=y
103CONFIG_BINFMT_ELF=y 103CONFIG_BINFMT_ELF=y
104# CONFIG_BINFMT_MISC is not set 104# CONFIG_BINFMT_MISC is not set
105 105
@@ -650,7 +650,7 @@ CONFIG_MMTIMER=y
650# 650#
651# Console display driver support 651# Console display driver support
652# 652#
653# CONFIG_VGA_CONSOLE is not set 653CONFIG_VGA_CONSOLE=y
654CONFIG_DUMMY_CONSOLE=y 654CONFIG_DUMMY_CONSOLE=y
655 655
656# 656#
diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c
index b8db6e3e5e81..11957598a8b9 100644
--- a/arch/ia64/hp/common/sba_iommu.c
+++ b/arch/ia64/hp/common/sba_iommu.c
@@ -156,10 +156,13 @@
156*/ 156*/
157#define DELAYED_RESOURCE_CNT 64 157#define DELAYED_RESOURCE_CNT 64
158 158
159#define PCI_DEVICE_ID_HP_SX2000_IOC 0x12ec
160
159#define ZX1_IOC_ID ((PCI_DEVICE_ID_HP_ZX1_IOC << 16) | PCI_VENDOR_ID_HP) 161#define ZX1_IOC_ID ((PCI_DEVICE_ID_HP_ZX1_IOC << 16) | PCI_VENDOR_ID_HP)
160#define ZX2_IOC_ID ((PCI_DEVICE_ID_HP_ZX2_IOC << 16) | PCI_VENDOR_ID_HP) 162#define ZX2_IOC_ID ((PCI_DEVICE_ID_HP_ZX2_IOC << 16) | PCI_VENDOR_ID_HP)
161#define REO_IOC_ID ((PCI_DEVICE_ID_HP_REO_IOC << 16) | PCI_VENDOR_ID_HP) 163#define REO_IOC_ID ((PCI_DEVICE_ID_HP_REO_IOC << 16) | PCI_VENDOR_ID_HP)
162#define SX1000_IOC_ID ((PCI_DEVICE_ID_HP_SX1000_IOC << 16) | PCI_VENDOR_ID_HP) 164#define SX1000_IOC_ID ((PCI_DEVICE_ID_HP_SX1000_IOC << 16) | PCI_VENDOR_ID_HP)
165#define SX2000_IOC_ID ((PCI_DEVICE_ID_HP_SX2000_IOC << 16) | PCI_VENDOR_ID_HP)
163 166
164#define ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */ 167#define ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */
165 168
@@ -1726,6 +1729,7 @@ static struct ioc_iommu ioc_iommu_info[] __initdata = {
1726 { ZX1_IOC_ID, "zx1", ioc_zx1_init }, 1729 { ZX1_IOC_ID, "zx1", ioc_zx1_init },
1727 { ZX2_IOC_ID, "zx2", NULL }, 1730 { ZX2_IOC_ID, "zx2", NULL },
1728 { SX1000_IOC_ID, "sx1000", NULL }, 1731 { SX1000_IOC_ID, "sx1000", NULL },
1732 { SX2000_IOC_ID, "sx2000", NULL },
1729}; 1733};
1730 1734
1731static struct ioc * __init 1735static struct ioc * __init
diff --git a/arch/ia64/hp/sim/simserial.c b/arch/ia64/hp/sim/simserial.c
index 786e70718ce4..7a8ae0f4b387 100644
--- a/arch/ia64/hp/sim/simserial.c
+++ b/arch/ia64/hp/sim/simserial.c
@@ -30,6 +30,7 @@
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/serial.h> 31#include <linux/serial.h>
32#include <linux/serialP.h> 32#include <linux/serialP.h>
33#include <linux/sysrq.h>
33 34
34#include <asm/irq.h> 35#include <asm/irq.h>
35#include <asm/hw_irq.h> 36#include <asm/hw_irq.h>
@@ -149,12 +150,17 @@ static void receive_chars(struct tty_struct *tty, struct pt_regs *regs)
149 seen_esc = 2; 150 seen_esc = 2;
150 continue; 151 continue;
151 } else if ( seen_esc == 2 ) { 152 } else if ( seen_esc == 2 ) {
152 if ( ch == 'P' ) show_state(); /* F1 key */ 153 if ( ch == 'P' ) /* F1 */
153#ifdef CONFIG_KDB 154 show_state();
154 if ( ch == 'S' ) 155#ifdef CONFIG_MAGIC_SYSRQ
155 kdb(KDB_REASON_KEYBOARD, 0, (kdb_eframe_t) regs); 156 if ( ch == 'S' ) { /* F4 */
157 do
158 ch = ia64_ssc(0, 0, 0, 0,
159 SSC_GETCHAR);
160 while (!ch);
161 handle_sysrq(ch, regs, NULL);
162 }
156#endif 163#endif
157
158 seen_esc = 0; 164 seen_esc = 0;
159 continue; 165 continue;
160 } 166 }
diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
index 785a51b0ad8e..69f88d561d62 100644
--- a/arch/ia64/kernel/entry.S
+++ b/arch/ia64/kernel/entry.S
@@ -470,18 +470,6 @@ ENTRY(load_switch_stack)
470 br.cond.sptk.many b7 470 br.cond.sptk.many b7
471END(load_switch_stack) 471END(load_switch_stack)
472 472
473GLOBAL_ENTRY(__ia64_syscall)
474 .regstk 6,0,0,0
475 mov r15=in5 // put syscall number in place
476 break __BREAK_SYSCALL
477 movl r2=errno
478 cmp.eq p6,p7=-1,r10
479 ;;
480(p6) st4 [r2]=r8
481(p6) mov r8=-1
482 br.ret.sptk.many rp
483END(__ia64_syscall)
484
485GLOBAL_ENTRY(execve) 473GLOBAL_ENTRY(execve)
486 mov r15=__NR_execve // put syscall number in place 474 mov r15=__NR_execve // put syscall number in place
487 break __BREAK_SYSCALL 475 break __BREAK_SYSCALL
@@ -637,7 +625,7 @@ END(ia64_ret_from_syscall)
637 * r8-r11: restored (syscall return value(s)) 625 * r8-r11: restored (syscall return value(s))
638 * r12: restored (user-level stack pointer) 626 * r12: restored (user-level stack pointer)
639 * r13: restored (user-level thread pointer) 627 * r13: restored (user-level thread pointer)
640 * r14: cleared 628 * r14: set to __kernel_syscall_via_epc
641 * r15: restored (syscall #) 629 * r15: restored (syscall #)
642 * r16-r17: cleared 630 * r16-r17: cleared
643 * r18: user-level b6 631 * r18: user-level b6
@@ -658,7 +646,7 @@ END(ia64_ret_from_syscall)
658 * pr: restored (user-level pr) 646 * pr: restored (user-level pr)
659 * b0: restored (user-level rp) 647 * b0: restored (user-level rp)
660 * b6: restored 648 * b6: restored
661 * b7: cleared 649 * b7: set to __kernel_syscall_via_epc
662 * ar.unat: restored (user-level ar.unat) 650 * ar.unat: restored (user-level ar.unat)
663 * ar.pfs: restored (user-level ar.pfs) 651 * ar.pfs: restored (user-level ar.pfs)
664 * ar.rsc: restored (user-level ar.rsc) 652 * ar.rsc: restored (user-level ar.rsc)
@@ -704,72 +692,79 @@ ENTRY(ia64_leave_syscall)
704 ;; 692 ;;
705(p6) ld4 r31=[r18] // load current_thread_info()->flags 693(p6) ld4 r31=[r18] // load current_thread_info()->flags
706 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs" 694 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
707 mov b7=r0 // clear b7 695 nop.i 0
708 ;; 696 ;;
709 ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage) 697 mov r16=ar.bsp // M2 get existing backing store pointer
710 ld8 r18=[r2],PT(R9)-PT(B6) // load b6 698 ld8 r18=[r2],PT(R9)-PT(B6) // load b6
711(p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE? 699(p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
712 ;; 700 ;;
713 mov r16=ar.bsp // M2 get existing backing store pointer 701 ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
714(p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending? 702(p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending?
715(p6) br.cond.spnt .work_pending_syscall 703(p6) br.cond.spnt .work_pending_syscall
716 ;; 704 ;;
717 // start restoring the state saved on the kernel stack (struct pt_regs): 705 // start restoring the state saved on the kernel stack (struct pt_regs):
718 ld8 r9=[r2],PT(CR_IPSR)-PT(R9) 706 ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
719 ld8 r11=[r3],PT(CR_IIP)-PT(R11) 707 ld8 r11=[r3],PT(CR_IIP)-PT(R11)
720 mov f6=f0 // clear f6 708(pNonSys) break 0 // bug check: we shouldn't be here if pNonSys is TRUE!
721 ;; 709 ;;
722 invala // M0|1 invalidate ALAT 710 invala // M0|1 invalidate ALAT
723 rsm psr.i | psr.ic // M2 initiate turning off of interrupt and interruption collection 711 rsm psr.i | psr.ic // M2 turn off interrupts and interruption collection
724 mov f9=f0 // clear f9 712 cmp.eq p9,p0=r0,r0 // A set p9 to indicate that we should restore cr.ifs
725 713
726 ld8 r29=[r2],16 // load cr.ipsr 714 ld8 r29=[r2],16 // M0|1 load cr.ipsr
727 ld8 r28=[r3],16 // load cr.iip 715 ld8 r28=[r3],16 // M0|1 load cr.iip
728 mov f8=f0 // clear f8 716 mov r22=r0 // A clear r22
729 ;; 717 ;;
730 ld8 r30=[r2],16 // M0|1 load cr.ifs 718 ld8 r30=[r2],16 // M0|1 load cr.ifs
731 ld8 r25=[r3],16 // M0|1 load ar.unat 719 ld8 r25=[r3],16 // M0|1 load ar.unat
732 cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs 720(pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
733 ;; 721 ;;
734 ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs 722 ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs
735(pKStk) mov r22=psr // M2 read PSR now that interrupts are disabled 723(pKStk) mov r22=psr // M2 read PSR now that interrupts are disabled
736 mov f10=f0 // clear f10 724 nop 0
737 ;; 725 ;;
738 ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // load b0 726 ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // M0|1 load b0
739 ld8 r27=[r3],PT(PR)-PT(AR_RSC) // load ar.rsc 727 ld8 r27=[r3],PT(PR)-PT(AR_RSC) // M0|1 load ar.rsc
740 mov f11=f0 // clear f11 728 mov f6=f0 // F clear f6
741 ;; 729 ;;
742 ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // load ar.rnat (may be garbage) 730 ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // M0|1 load ar.rnat (may be garbage)
743 ld8 r31=[r3],PT(R1)-PT(PR) // load predicates 731 ld8 r31=[r3],PT(R1)-PT(PR) // M0|1 load predicates
744(pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13 732 mov f7=f0 // F clear f7
745 ;; 733 ;;
746 ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // load ar.fpsr 734 ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // M0|1 load ar.fpsr
747 ld8.fill r1=[r3],16 // load r1 735 ld8.fill r1=[r3],16 // M0|1 load r1
748(pUStk) mov r17=1 736(pUStk) mov r17=1 // A
749 ;; 737 ;;
750 srlz.d // M0 ensure interruption collection is off 738(pUStk) st1 [r14]=r17 // M2|3
751 ld8.fill r13=[r3],16 739 ld8.fill r13=[r3],16 // M0|1
752 mov f7=f0 // clear f7 740 mov f8=f0 // F clear f8
753 ;; 741 ;;
754 ld8.fill r12=[r2] // restore r12 (sp) 742 ld8.fill r12=[r2] // M0|1 restore r12 (sp)
755 mov.m ar.ssd=r0 // M2 clear ar.ssd 743 ld8.fill r15=[r3] // M0|1 restore r15
756 mov r22=r0 // clear r22 744 mov b6=r18 // I0 restore b6
757 745
758 ld8.fill r15=[r3] // restore r15 746 addl r17=THIS_CPU(ia64_phys_stacked_size_p8),r0 // A
759(pUStk) st1 [r14]=r17 747 mov f9=f0 // F clear f9
760 addl r3=THIS_CPU(ia64_phys_stacked_size_p8),r0 748(pKStk) br.cond.dpnt.many skip_rbs_switch // B
749
750 srlz.d // M0 ensure interruption collection is off (for cover)
751 shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition
752 cover // B add current frame into dirty partition & set cr.ifs
761 ;; 753 ;;
762(pUStk) ld4 r17=[r3] // r17 = cpu_data->phys_stacked_size_p8 754(pUStk) ld4 r17=[r17] // M0|1 r17 = cpu_data->phys_stacked_size_p8
763 mov.m ar.csd=r0 // M2 clear ar.csd 755 mov r19=ar.bsp // M2 get new backing store pointer
764 mov b6=r18 // I0 restore b6 756 mov f10=f0 // F clear f10
757
758 nop.m 0
759 movl r14=__kernel_syscall_via_epc // X
765 ;; 760 ;;
766 mov r14=r0 // clear r14 761 mov.m ar.csd=r0 // M2 clear ar.csd
767 shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition 762 mov.m ar.ccv=r0 // M2 clear ar.ccv
768(pKStk) br.cond.dpnt.many skip_rbs_switch 763 mov b7=r14 // I0 clear b7 (hint with __kernel_syscall_via_epc)
769 764
770 mov.m ar.ccv=r0 // clear ar.ccv 765 mov.m ar.ssd=r0 // M2 clear ar.ssd
771(pNonSys) br.cond.dpnt.many dont_preserve_current_frame 766 mov f11=f0 // F clear f11
772 br.cond.sptk.many rbs_switch 767 br.cond.sptk.many rbs_switch // B
773END(ia64_leave_syscall) 768END(ia64_leave_syscall)
774 769
775#ifdef CONFIG_IA32_SUPPORT 770#ifdef CONFIG_IA32_SUPPORT
@@ -885,7 +880,7 @@ GLOBAL_ENTRY(ia64_leave_kernel)
885 ldf.fill f7=[r2],PT(F11)-PT(F7) 880 ldf.fill f7=[r2],PT(F11)-PT(F7)
886 ldf.fill f8=[r3],32 881 ldf.fill f8=[r3],32
887 ;; 882 ;;
888 srlz.i // ensure interruption collection is off 883 srlz.d // ensure that inter. collection is off (VHPT is don't care, since text is pinned)
889 mov ar.ccv=r15 884 mov ar.ccv=r15
890 ;; 885 ;;
891 ldf.fill f11=[r2] 886 ldf.fill f11=[r2]
@@ -945,11 +940,10 @@ GLOBAL_ENTRY(ia64_leave_kernel)
945 * NOTE: alloc, loadrs, and cover can't be predicated. 940 * NOTE: alloc, loadrs, and cover can't be predicated.
946 */ 941 */
947(pNonSys) br.cond.dpnt dont_preserve_current_frame 942(pNonSys) br.cond.dpnt dont_preserve_current_frame
948
949rbs_switch:
950 cover // add current frame into dirty partition and set cr.ifs 943 cover // add current frame into dirty partition and set cr.ifs
951 ;; 944 ;;
952 mov r19=ar.bsp // get new backing store pointer 945 mov r19=ar.bsp // get new backing store pointer
946rbs_switch:
953 sub r16=r16,r18 // krbs = old bsp - size of dirty partition 947 sub r16=r16,r18 // krbs = old bsp - size of dirty partition
954 cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs 948 cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs
955 ;; 949 ;;
@@ -1024,14 +1018,14 @@ rse_clear_invalid:
1024 mov loc5=0 1018 mov loc5=0
1025 mov loc6=0 1019 mov loc6=0
1026 mov loc7=0 1020 mov loc7=0
1027(pRecurse) br.call.sptk.few b0=rse_clear_invalid 1021(pRecurse) br.call.dptk.few b0=rse_clear_invalid
1028 ;; 1022 ;;
1029 mov loc8=0 1023 mov loc8=0
1030 mov loc9=0 1024 mov loc9=0
1031 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret 1025 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
1032 mov loc10=0 1026 mov loc10=0
1033 mov loc11=0 1027 mov loc11=0
1034(pReturn) br.ret.sptk.many b0 1028(pReturn) br.ret.dptk.many b0
1035#endif /* !CONFIG_ITANIUM */ 1029#endif /* !CONFIG_ITANIUM */
1036# undef pRecurse 1030# undef pRecurse
1037# undef pReturn 1031# undef pReturn
diff --git a/arch/ia64/kernel/fsys.S b/arch/ia64/kernel/fsys.S
index 962b6c4e32b5..7d7684a369d3 100644
--- a/arch/ia64/kernel/fsys.S
+++ b/arch/ia64/kernel/fsys.S
@@ -531,93 +531,114 @@ GLOBAL_ENTRY(fsys_bubble_down)
531 .altrp b6 531 .altrp b6
532 .body 532 .body
533 /* 533 /*
534 * We get here for syscalls that don't have a lightweight handler. For those, we 534 * We get here for syscalls that don't have a lightweight
535 * need to bubble down into the kernel and that requires setting up a minimal 535 * handler. For those, we need to bubble down into the kernel
536 * pt_regs structure, and initializing the CPU state more or less as if an 536 * and that requires setting up a minimal pt_regs structure,
537 * interruption had occurred. To make syscall-restarts work, we setup pt_regs 537 * and initializing the CPU state more or less as if an
538 * such that cr_iip points to the second instruction in syscall_via_break. 538 * interruption had occurred. To make syscall-restarts work,
539 * Decrementing the IP hence will restart the syscall via break and not 539 * we setup pt_regs such that cr_iip points to the second
540 * decrementing IP will return us to the caller, as usual. Note that we preserve 540 * instruction in syscall_via_break. Decrementing the IP
541 * the value of psr.pp rather than initializing it from dcr.pp. This makes it 541 * hence will restart the syscall via break and not
542 * possible to distinguish fsyscall execution from other privileged execution. 542 * decrementing IP will return us to the caller, as usual.
543 * Note that we preserve the value of psr.pp rather than
544 * initializing it from dcr.pp. This makes it possible to
545 * distinguish fsyscall execution from other privileged
546 * execution.
543 * 547 *
544 * On entry: 548 * On entry:
545 * - normal fsyscall handler register usage, except that we also have: 549 * - normal fsyscall handler register usage, except
550 * that we also have:
546 * - r18: address of syscall entry point 551 * - r18: address of syscall entry point
547 * - r21: ar.fpsr 552 * - r21: ar.fpsr
548 * - r26: ar.pfs 553 * - r26: ar.pfs
549 * - r27: ar.rsc 554 * - r27: ar.rsc
550 * - r29: psr 555 * - r29: psr
556 *
557 * We used to clear some PSR bits here but that requires slow
558 * serialization. Fortuntely, that isn't really necessary.
559 * The rationale is as follows: we used to clear bits
560 * ~PSR_PRESERVED_BITS in PSR.L. Since
561 * PSR_PRESERVED_BITS==PSR.{UP,MFL,MFH,PK,DT,PP,SP,RT,IC}, we
562 * ended up clearing PSR.{BE,AC,I,DFL,DFH,DI,DB,SI,TB}.
563 * However,
564 *
565 * PSR.BE : already is turned off in __kernel_syscall_via_epc()
566 * PSR.AC : don't care (kernel normally turns PSR.AC on)
567 * PSR.I : already turned off by the time fsys_bubble_down gets
568 * invoked
569 * PSR.DFL: always 0 (kernel never turns it on)
570 * PSR.DFH: don't care --- kernel never touches f32-f127 on its own
571 * initiative
572 * PSR.DI : always 0 (kernel never turns it on)
573 * PSR.SI : always 0 (kernel never turns it on)
574 * PSR.DB : don't care --- kernel never enables kernel-level
575 * breakpoints
576 * PSR.TB : must be 0 already; if it wasn't zero on entry to
577 * __kernel_syscall_via_epc, the branch to fsys_bubble_down
578 * will trigger a taken branch; the taken-trap-handler then
579 * converts the syscall into a break-based system-call.
551 */ 580 */
552# define PSR_PRESERVED_BITS (IA64_PSR_UP | IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_PK \
553 | IA64_PSR_DT | IA64_PSR_PP | IA64_PSR_SP | IA64_PSR_RT \
554 | IA64_PSR_IC)
555 /* 581 /*
556 * Reading psr.l gives us only bits 0-31, psr.it, and psr.mc. The rest we have 582 * Reading psr.l gives us only bits 0-31, psr.it, and psr.mc.
557 * to synthesize. 583 * The rest we have to synthesize.
558 */ 584 */
559# define PSR_ONE_BITS ((3 << IA64_PSR_CPL0_BIT) | (0x1 << IA64_PSR_RI_BIT) \ 585# define PSR_ONE_BITS ((3 << IA64_PSR_CPL0_BIT) \
586 | (0x1 << IA64_PSR_RI_BIT) \
560 | IA64_PSR_BN | IA64_PSR_I) 587 | IA64_PSR_BN | IA64_PSR_I)
561 588
562 invala 589 invala // M0|1
563 movl r8=PSR_ONE_BITS 590 movl r14=ia64_ret_from_syscall // X
564 591
565 mov r25=ar.unat // save ar.unat (5 cyc) 592 nop.m 0
566 movl r9=PSR_PRESERVED_BITS 593 movl r28=__kernel_syscall_via_break // X create cr.iip
594 ;;
567 595
568 mov ar.rsc=0 // set enforced lazy mode, pl 0, little-endian, loadrs=0 596 mov r2=r16 // A get task addr to addl-addressable register
569 movl r28=__kernel_syscall_via_break 597 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // A
598 mov r31=pr // I0 save pr (2 cyc)
570 ;; 599 ;;
571 mov r23=ar.bspstore // save ar.bspstore (12 cyc) 600 st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
572 mov r31=pr // save pr (2 cyc) 601 addl r22=IA64_RBS_OFFSET,r2 // A compute base of RBS
573 mov r20=r1 // save caller's gp in r20 602 add r3=TI_FLAGS+IA64_TASK_SIZE,r2 // A
574 ;; 603 ;;
575 mov r2=r16 // copy current task addr to addl-addressable register 604 ld4 r3=[r3] // M0|1 r3 = current_thread_info()->flags
576 and r9=r9,r29 605 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch register backing-store
577 mov r19=b6 // save b6 (2 cyc) 606 nop.i 0
578 ;; 607 ;;
579 mov psr.l=r9 // slam the door (17 cyc to srlz.i) 608 mov ar.rsc=0 // M2 set enforced lazy mode, pl 0, LE, loadrs=0
580 or r29=r8,r29 // construct cr.ipsr value to save 609 nop.m 0
581 addl r22=IA64_RBS_OFFSET,r2 // compute base of RBS 610 nop.i 0
582 ;; 611 ;;
583 // GAS reports a spurious RAW hazard on the read of ar.rnat because it thinks 612 mov r23=ar.bspstore // M2 (12 cyc) save ar.bspstore
584 // we may be reading ar.itc after writing to psr.l. Avoid that message with 613 mov.m r24=ar.rnat // M2 (5 cyc) read ar.rnat (dual-issues!)
585 // this directive: 614 nop.i 0
586 dv_serialize_data
587 mov.m r24=ar.rnat // read ar.rnat (5 cyc lat)
588 lfetch.fault.excl.nt1 [r22]
589 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r2
590
591 // ensure previous insn group is issued before we stall for srlz.i:
592 ;; 615 ;;
593 srlz.i // ensure new psr.l has been established 616 mov ar.bspstore=r22 // M2 (6 cyc) switch to kernel RBS
594 ///////////////////////////////////////////////////////////////////////////// 617 movl r8=PSR_ONE_BITS // X
595 ////////// from this point on, execution is not interruptible anymore
596 /////////////////////////////////////////////////////////////////////////////
597 addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r2 // compute base of memory stack
598 cmp.ne pKStk,pUStk=r0,r0 // set pKStk <- 0, pUStk <- 1
599 ;; 618 ;;
600 st1 [r16]=r0 // clear current->thread.on_ustack flag 619 mov r25=ar.unat // M2 (5 cyc) save ar.unat
601 mov ar.bspstore=r22 // switch to kernel RBS 620 mov r19=b6 // I0 save b6 (2 cyc)
602 mov b6=r18 // copy syscall entry-point to b6 (7 cyc) 621 mov r20=r1 // A save caller's gp in r20
603 add r3=TI_FLAGS+IA64_TASK_SIZE,r2
604 ;; 622 ;;
605 ld4 r3=[r3] // r2 = current_thread_info()->flags 623 or r29=r8,r29 // A construct cr.ipsr value to save
606 mov r18=ar.bsp // save (kernel) ar.bsp (12 cyc) 624 mov b6=r18 // I0 copy syscall entry-point to b6 (7 cyc)
607 mov ar.rsc=0x3 // set eager mode, pl 0, little-endian, loadrs=0 625 addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r2 // A compute base of memory stack
608 br.call.sptk.many b7=ia64_syscall_setup 626
609 ;; 627 mov r18=ar.bsp // M2 save (kernel) ar.bsp (12 cyc)
610 ssm psr.i 628 cmp.ne pKStk,pUStk=r0,r0 // A set pKStk <- 0, pUStk <- 1
611 movl r2=ia64_ret_from_syscall 629 br.call.sptk.many b7=ia64_syscall_setup // B
612 ;; 630 ;;
613 mov rp=r2 // set the real return addr 631 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
614 and r3=_TIF_SYSCALL_TRACEAUDIT,r3 632 mov rp=r14 // I0 set the real return addr
633 and r3=_TIF_SYSCALL_TRACEAUDIT,r3 // A
615 ;; 634 ;;
616 cmp.eq p8,p0=r3,r0 635 ssm psr.i // M2 we're on kernel stacks now, reenable irqs
636 cmp.eq p8,p0=r3,r0 // A
637(p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT
617 638
618(p10) br.cond.spnt.many ia64_ret_from_syscall // p10==true means out registers are more than 8 639 nop.m 0
619(p8) br.call.sptk.many b6=b6 // ignore this return addr 640(p8) br.call.sptk.many b6=b6 // B (ignore return address)
620 br.cond.sptk ia64_trace_syscall 641 br.cond.spnt ia64_trace_syscall // B
621END(fsys_bubble_down) 642END(fsys_bubble_down)
622 643
623 .rodata 644 .rodata
diff --git a/arch/ia64/kernel/gate.S b/arch/ia64/kernel/gate.S
index facf75acdc85..86948ce63e43 100644
--- a/arch/ia64/kernel/gate.S
+++ b/arch/ia64/kernel/gate.S
@@ -72,38 +72,40 @@ GLOBAL_ENTRY(__kernel_syscall_via_epc)
72 * bundle get executed. The remaining code must be safe even if 72 * bundle get executed. The remaining code must be safe even if
73 * they do not get executed. 73 * they do not get executed.
74 */ 74 */
75 adds r17=-1024,r15 75 adds r17=-1024,r15 // A
76 mov r10=0 // default to successful syscall execution 76 mov r10=0 // A default to successful syscall execution
77 epc 77 epc // B causes split-issue
78} 78}
79 ;; 79 ;;
80 rsm psr.be // note: on McKinley "rsm psr.be/srlz.d" is slightly faster than "rum psr.be" 80 rsm psr.be | psr.i // M2 (5 cyc to srlz.d)
81 LOAD_FSYSCALL_TABLE(r14) 81 LOAD_FSYSCALL_TABLE(r14) // X
82
83 mov r16=IA64_KR(CURRENT) // 12 cycle read latency
84 tnat.nz p10,p9=r15
85 mov r19=NR_syscalls-1
86 ;; 82 ;;
87 shladd r18=r17,3,r14 83 mov r16=IA64_KR(CURRENT) // M2 (12 cyc)
88 84 shladd r18=r17,3,r14 // A
89 srlz.d 85 mov r19=NR_syscalls-1 // A
90 cmp.ne p8,p0=r0,r0 // p8 <- FALSE 86 ;;
91 /* Note: if r17 is a NaT, p6 will be set to zero. */ 87 lfetch [r18] // M0|1
92 cmp.geu p6,p7=r19,r17 // (syscall > 0 && syscall < 1024+NR_syscalls)? 88 mov r29=psr // M2 (12 cyc)
93 ;; 89 // If r17 is a NaT, p6 will be zero
94(p6) ld8 r18=[r18] 90 cmp.geu p6,p7=r19,r17 // A (sysnr > 0 && sysnr < 1024+NR_syscalls)?
95 mov r21=ar.fpsr 91 ;;
96 add r14=-8,r14 // r14 <- addr of fsys_bubble_down entry 92 mov r21=ar.fpsr // M2 (12 cyc)
97 ;; 93 tnat.nz p10,p9=r15 // I0
98(p6) mov b7=r18 94 mov.i r26=ar.pfs // I0 (would stall anyhow due to srlz.d...)
99(p6) tbit.z p8,p0=r18,0 95 ;;
100(p8) br.dptk.many b7 96 srlz.d // M0 (forces split-issue) ensure PSR.BE==0
101 97(p6) ld8 r18=[r18] // M0|1
102(p6) rsm psr.i 98 nop.i 0
103 mov r27=ar.rsc 99 ;;
104 mov r26=ar.pfs 100 nop.m 0
101(p6) tbit.z.unc p8,p0=r18,0 // I0 (dual-issues with "mov b7=r18"!)
102 nop.i 0
105 ;; 103 ;;
106 mov r29=psr // read psr (12 cyc load latency) 104(p8) ssm psr.i
105(p6) mov b7=r18 // I0
106(p8) br.dptk.many b7 // B
107
108 mov r27=ar.rsc // M2 (12 cyc)
107/* 109/*
108 * brl.cond doesn't work as intended because the linker would convert this branch 110 * brl.cond doesn't work as intended because the linker would convert this branch
109 * into a branch to a PLT. Perhaps there will be a way to avoid this with some 111 * into a branch to a PLT. Perhaps there will be a way to avoid this with some
@@ -111,6 +113,8 @@ GLOBAL_ENTRY(__kernel_syscall_via_epc)
111 * instead. 113 * instead.
112 */ 114 */
113#ifdef CONFIG_ITANIUM 115#ifdef CONFIG_ITANIUM
116(p6) add r14=-8,r14 // r14 <- addr of fsys_bubble_down entry
117 ;;
114(p6) ld8 r14=[r14] // r14 <- fsys_bubble_down 118(p6) ld8 r14=[r14] // r14 <- fsys_bubble_down
115 ;; 119 ;;
116(p6) mov b7=r14 120(p6) mov b7=r14
@@ -118,7 +122,7 @@ GLOBAL_ENTRY(__kernel_syscall_via_epc)
118#else 122#else
119 BRL_COND_FSYS_BUBBLE_DOWN(p6) 123 BRL_COND_FSYS_BUBBLE_DOWN(p6)
120#endif 124#endif
121 125 ssm psr.i
122 mov r10=-1 126 mov r10=-1
123(p10) mov r8=EINVAL 127(p10) mov r8=EINVAL
124(p9) mov r8=ENOSYS 128(p9) mov r8=ENOSYS
diff --git a/arch/ia64/kernel/ia64_ksyms.c b/arch/ia64/kernel/ia64_ksyms.c
index 7bbf019c9867..01572814abe4 100644
--- a/arch/ia64/kernel/ia64_ksyms.c
+++ b/arch/ia64/kernel/ia64_ksyms.c
@@ -58,9 +58,6 @@ EXPORT_SYMBOL(__strlen_user);
58EXPORT_SYMBOL(__strncpy_from_user); 58EXPORT_SYMBOL(__strncpy_from_user);
59EXPORT_SYMBOL(__strnlen_user); 59EXPORT_SYMBOL(__strnlen_user);
60 60
61#include <asm/unistd.h>
62EXPORT_SYMBOL(__ia64_syscall);
63
64/* from arch/ia64/lib */ 61/* from arch/ia64/lib */
65extern void __divsi3(void); 62extern void __divsi3(void);
66extern void __udivsi3(void); 63extern void __udivsi3(void);
diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S
index 2bc085a73e30..3bb3a13c4047 100644
--- a/arch/ia64/kernel/ivt.S
+++ b/arch/ia64/kernel/ivt.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/ia64/kernel/ivt.S 2 * arch/ia64/kernel/ivt.S
3 * 3 *
4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co 4 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com> 5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger <davidm@hpl.hp.com> 6 * David Mosberger <davidm@hpl.hp.com>
7 * Copyright (C) 2000, 2002-2003 Intel Co 7 * Copyright (C) 2000, 2002-2003 Intel Co
@@ -692,82 +692,118 @@ ENTRY(break_fault)
692 * to prevent leaking bits from kernel to user level. 692 * to prevent leaking bits from kernel to user level.
693 */ 693 */
694 DBG_FAULT(11) 694 DBG_FAULT(11)
695 mov r16=IA64_KR(CURRENT) // r16 = current task; 12 cycle read lat. 695 mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc)
696 mov r17=cr.iim 696 mov r29=cr.ipsr // M2 (12 cyc)
697 mov r18=__IA64_BREAK_SYSCALL 697 mov r31=pr // I0 (2 cyc)
698 mov r21=ar.fpsr 698
699 mov r29=cr.ipsr 699 mov r17=cr.iim // M2 (2 cyc)
700 mov r19=b6 700 mov.m r27=ar.rsc // M2 (12 cyc)
701 mov r25=ar.unat 701 mov r18=__IA64_BREAK_SYSCALL // A
702 mov r27=ar.rsc 702
703 mov r26=ar.pfs 703 mov.m ar.rsc=0 // M2
704 mov r28=cr.iip 704 mov.m r21=ar.fpsr // M2 (12 cyc)
705 mov r31=pr // prepare to save predicates 705 mov r19=b6 // I0 (2 cyc)
706 mov r20=r1 706 ;;
707 ;; 707 mov.m r23=ar.bspstore // M2 (12 cyc)
708 mov.m r24=ar.rnat // M2 (5 cyc)
709 mov.i r26=ar.pfs // I0 (2 cyc)
710
711 invala // M0|1
712 nop.m 0 // M
713 mov r20=r1 // A save r1
714
715 nop.m 0
716 movl r30=sys_call_table // X
717
718 mov r28=cr.iip // M2 (2 cyc)
719 cmp.eq p0,p7=r18,r17 // I0 is this a system call?
720(p7) br.cond.spnt non_syscall // B no ->
721 //
722 // From this point on, we are definitely on the syscall-path
723 // and we can use (non-banked) scratch registers.
724 //
725///////////////////////////////////////////////////////////////////////
726 mov r1=r16 // A move task-pointer to "addl"-addressable reg
727 mov r2=r16 // A setup r2 for ia64_syscall_setup
728 add r9=TI_FLAGS+IA64_TASK_SIZE,r16 // A r9 = &current_thread_info()->flags
729
708 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 730 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
709 cmp.eq p0,p7=r18,r17 // is this a system call? (p7 <- false, if so) 731 adds r15=-1024,r15 // A subtract 1024 from syscall number
710(p7) br.cond.spnt non_syscall 732 mov r3=NR_syscalls - 1
711 ;; 733 ;;
712 ld1 r17=[r16] // load current->thread.on_ustack flag 734 ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag
713 st1 [r16]=r0 // clear current->thread.on_ustack flag 735 ld4 r9=[r9] // M0|1 r9 = current_thread_info()->flags
714 add r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // set r1 for MINSTATE_START_SAVE_MIN_VIRT 736 extr.u r8=r29,41,2 // I0 extract ei field from cr.ipsr
737
738 shladd r30=r15,3,r30 // A r30 = sys_call_table + 8*(syscall-1024)
739 addl r22=IA64_RBS_OFFSET,r1 // A compute base of RBS
740 cmp.leu p6,p7=r15,r3 // A syscall number in range?
715 ;; 741 ;;
716 invala
717 742
718 /* adjust return address so we skip over the break instruction: */ 743 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch RBS
744(p6) ld8 r30=[r30] // M0|1 load address of syscall entry point
745 tnat.nz.or p7,p0=r15 // I0 is syscall nr a NaT?
719 746
720 extr.u r8=r29,41,2 // extract ei field from cr.ipsr 747 mov.m ar.bspstore=r22 // M2 switch to kernel RBS
721 ;; 748 cmp.eq p8,p9=2,r8 // A isr.ei==2?
722 cmp.eq p6,p7=2,r8 // isr.ei==2?
723 mov r2=r1 // setup r2 for ia64_syscall_setup
724 ;;
725(p6) mov r8=0 // clear ei to 0
726(p6) adds r28=16,r28 // switch cr.iip to next bundle cr.ipsr.ei wrapped
727(p7) adds r8=1,r8 // increment ei to next slot
728 ;;
729 cmp.eq pKStk,pUStk=r0,r17 // are we in kernel mode already?
730 dep r29=r8,r29,41,2 // insert new ei into cr.ipsr
731 ;; 749 ;;
732 750
733 // switch from user to kernel RBS: 751(p8) mov r8=0 // A clear ei to 0
734 MINSTATE_START_SAVE_MIN_VIRT 752(p7) movl r30=sys_ni_syscall // X
735 br.call.sptk.many b7=ia64_syscall_setup
736 ;;
737 MINSTATE_END_SAVE_MIN_VIRT // switch to bank 1
738 ssm psr.ic | PSR_DEFAULT_BITS
739 ;;
740 srlz.i // guarantee that interruption collection is on
741 mov r3=NR_syscalls - 1
742 ;;
743(p15) ssm psr.i // restore psr.i
744 // p10==true means out registers are more than 8 or r15's Nat is true
745(p10) br.cond.spnt.many ia64_ret_from_syscall
746 ;;
747 movl r16=sys_call_table
748 753
749 adds r15=-1024,r15 // r15 contains the syscall number---subtract 1024 754(p8) adds r28=16,r28 // A switch cr.iip to next bundle
750 movl r2=ia64_ret_from_syscall 755(p9) adds r8=1,r8 // A increment ei to next slot
751 ;; 756 nop.i 0
752 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
753 cmp.leu p6,p7=r15,r3 // (syscall > 0 && syscall < 1024 + NR_syscalls) ?
754 mov rp=r2 // set the real return addr
755 ;; 757 ;;
756(p6) ld8 r20=[r20] // load address of syscall entry point
757(p7) movl r20=sys_ni_syscall
758 758
759 add r2=TI_FLAGS+IA64_TASK_SIZE,r13 759 mov.m r25=ar.unat // M2 (5 cyc)
760 ;; 760 dep r29=r8,r29,41,2 // I0 insert new ei into cr.ipsr
761 ld4 r2=[r2] // r2 = current_thread_info()->flags 761 adds r15=1024,r15 // A restore original syscall number
762 ;; 762 //
763 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit 763 // If any of the above loads miss in L1D, we'll stall here until
764 // the data arrives.
765 //
766///////////////////////////////////////////////////////////////////////
767 st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
768 mov b6=r30 // I0 setup syscall handler branch reg early
769 cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already?
770
771 and r9=_TIF_SYSCALL_TRACEAUDIT,r9 // A mask trace or audit
772 mov r18=ar.bsp // M2 (12 cyc)
773(pKStk) br.cond.spnt .break_fixup // B we're already in kernel-mode -- fix up RBS
774 ;;
775.back_from_break_fixup:
776(pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1 // A compute base of memory stack
777 cmp.eq p14,p0=r9,r0 // A are syscalls being traced/audited?
778 br.call.sptk.many b7=ia64_syscall_setup // B
7791:
780 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
781 nop 0
782 bsw.1 // B (6 cyc) regs are saved, switch to bank 1
764 ;; 783 ;;
765 cmp.eq p8,p0=r2,r0 784
766 mov b6=r20 785 ssm psr.ic | PSR_DEFAULT_BITS // M2 now it's safe to re-enable intr.-collection
786 movl r3=ia64_ret_from_syscall // X
767 ;; 787 ;;
768(p8) br.call.sptk.many b6=b6 // ignore this return addr 788
769 br.cond.sptk ia64_trace_syscall 789 srlz.i // M0 ensure interruption collection is on
790 mov rp=r3 // I0 set the real return addr
791(p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT
792
793(p15) ssm psr.i // M2 restore psr.i
794(p14) br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr)
795 br.cond.spnt.many ia64_trace_syscall // B do syscall-tracing thingamagic
770 // NOT REACHED 796 // NOT REACHED
797///////////////////////////////////////////////////////////////////////
798 // On entry, we optimistically assumed that we're coming from user-space.
799 // For the rare cases where a system-call is done from within the kernel,
800 // we fix things up at this point:
801.break_fixup:
802 add r1=-IA64_PT_REGS_SIZE,sp // A allocate space for pt_regs structure
803 mov ar.rnat=r24 // M2 restore kernel's AR.RNAT
804 ;;
805 mov ar.bspstore=r23 // M2 restore kernel's AR.BSPSTORE
806 br.cond.sptk .back_from_break_fixup
771END(break_fault) 807END(break_fault)
772 808
773 .org ia64_ivt+0x3000 809 .org ia64_ivt+0x3000
@@ -842,8 +878,6 @@ END(interrupt)
842 * - r31: saved pr 878 * - r31: saved pr
843 * - b0: original contents (to be saved) 879 * - b0: original contents (to be saved)
844 * On exit: 880 * On exit:
845 * - executing on bank 1 registers
846 * - psr.ic enabled, interrupts restored
847 * - p10: TRUE if syscall is invoked with more than 8 out 881 * - p10: TRUE if syscall is invoked with more than 8 out
848 * registers or r15's Nat is true 882 * registers or r15's Nat is true
849 * - r1: kernel's gp 883 * - r1: kernel's gp
@@ -851,8 +885,11 @@ END(interrupt)
851 * - r8: -EINVAL if p10 is true 885 * - r8: -EINVAL if p10 is true
852 * - r12: points to kernel stack 886 * - r12: points to kernel stack
853 * - r13: points to current task 887 * - r13: points to current task
888 * - r14: preserved (same as on entry)
889 * - p13: preserved
854 * - p15: TRUE if interrupts need to be re-enabled 890 * - p15: TRUE if interrupts need to be re-enabled
855 * - ar.fpsr: set to kernel settings 891 * - ar.fpsr: set to kernel settings
892 * - b6: preserved (same as on entry)
856 */ 893 */
857GLOBAL_ENTRY(ia64_syscall_setup) 894GLOBAL_ENTRY(ia64_syscall_setup)
858#if PT(B6) != 0 895#if PT(B6) != 0
@@ -920,10 +957,10 @@ GLOBAL_ENTRY(ia64_syscall_setup)
920(p13) mov in5=-1 957(p13) mov in5=-1
921 ;; 958 ;;
922 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr 959 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
923 tnat.nz p14,p0=in6 960 tnat.nz p13,p0=in6
924 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8 961 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8
925 ;; 962 ;;
926 stf8 [r16]=f1 // ensure pt_regs.r8 != 0 (see handle_syscall_error) 963 mov r8=1
927(p9) tnat.nz p10,p0=r15 964(p9) tnat.nz p10,p0=r15
928 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch) 965 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
929 966
@@ -934,9 +971,9 @@ GLOBAL_ENTRY(ia64_syscall_setup)
934 mov r13=r2 // establish `current' 971 mov r13=r2 // establish `current'
935 movl r1=__gp // establish kernel global pointer 972 movl r1=__gp // establish kernel global pointer
936 ;; 973 ;;
937(p14) mov in6=-1 974 st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
975(p13) mov in6=-1
938(p8) mov in7=-1 976(p8) mov in7=-1
939 nop.i 0
940 977
941 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0 978 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
942 movl r17=FPSR_DEFAULT 979 movl r17=FPSR_DEFAULT
@@ -1007,6 +1044,8 @@ END(dispatch_illegal_op_fault)
1007 FAULT(17) 1044 FAULT(17)
1008 1045
1009ENTRY(non_syscall) 1046ENTRY(non_syscall)
1047 mov ar.rsc=r27 // restore ar.rsc before SAVE_MIN_WITH_COVER
1048 ;;
1010 SAVE_MIN_WITH_COVER 1049 SAVE_MIN_WITH_COVER
1011 1050
1012 // There is no particular reason for this code to be here, other than that 1051 // There is no particular reason for this code to be here, other than that
@@ -1204,6 +1243,25 @@ END(disabled_fp_reg)
1204// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50) 1243// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1205ENTRY(nat_consumption) 1244ENTRY(nat_consumption)
1206 DBG_FAULT(26) 1245 DBG_FAULT(26)
1246
1247 mov r16=cr.ipsr
1248 mov r17=cr.isr
1249 mov r31=pr // save PR
1250 ;;
1251 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1252 tbit.z p6,p0=r17,IA64_ISR_NA_BIT
1253 ;;
1254 cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18
1255 dep r16=-1,r16,IA64_PSR_ED_BIT,1
1256(p6) br.cond.spnt 1f // branch if (cr.ispr.na == 0 || cr.ipsr.code{3:0} != LFETCH)
1257 ;;
1258 mov cr.ipsr=r16 // set cr.ipsr.na
1259 mov pr=r31,-1
1260 ;;
1261 rfi
1262
12631: mov pr=r31,-1
1264 ;;
1207 FAULT(26) 1265 FAULT(26)
1208END(nat_consumption) 1266END(nat_consumption)
1209 1267
diff --git a/arch/ia64/kernel/ptrace.c b/arch/ia64/kernel/ptrace.c
index 6d57aebad485..bbb8bc7c0552 100644
--- a/arch/ia64/kernel/ptrace.c
+++ b/arch/ia64/kernel/ptrace.c
@@ -725,12 +725,32 @@ convert_to_non_syscall (struct task_struct *child, struct pt_regs *pt,
725 break; 725 break;
726 } 726 }
727 727
728 /*
729 * Note: at the time of this call, the target task is blocked
730 * in notify_resume_user() and by clearling PRED_LEAVE_SYSCALL
731 * (aka, "pLvSys") we redirect execution from
732 * .work_pending_syscall_end to .work_processed_kernel.
733 */
728 unw_get_pr(&prev_info, &pr); 734 unw_get_pr(&prev_info, &pr);
729 pr &= ~(1UL << PRED_SYSCALL); 735 pr &= ~((1UL << PRED_SYSCALL) | (1UL << PRED_LEAVE_SYSCALL));
730 pr |= (1UL << PRED_NON_SYSCALL); 736 pr |= (1UL << PRED_NON_SYSCALL);
731 unw_set_pr(&prev_info, pr); 737 unw_set_pr(&prev_info, pr);
732 738
733 pt->cr_ifs = (1UL << 63) | cfm; 739 pt->cr_ifs = (1UL << 63) | cfm;
740 /*
741 * Clear the memory that is NOT written on syscall-entry to
742 * ensure we do not leak kernel-state to user when execution
743 * resumes.
744 */
745 pt->r2 = 0;
746 pt->r3 = 0;
747 pt->r14 = 0;
748 memset(&pt->r16, 0, 16*8); /* clear r16-r31 */
749 memset(&pt->f6, 0, 6*16); /* clear f6-f11 */
750 pt->b7 = 0;
751 pt->ar_ccv = 0;
752 pt->ar_csd = 0;
753 pt->ar_ssd = 0;
734} 754}
735 755
736static int 756static int
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index d14692e0920a..2693e1522d7c 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -72,6 +72,8 @@ DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
72unsigned long ia64_cycles_per_usec; 72unsigned long ia64_cycles_per_usec;
73struct ia64_boot_param *ia64_boot_param; 73struct ia64_boot_param *ia64_boot_param;
74struct screen_info screen_info; 74struct screen_info screen_info;
75unsigned long vga_console_iobase;
76unsigned long vga_console_membase;
75 77
76unsigned long ia64_max_cacheline_size; 78unsigned long ia64_max_cacheline_size;
77unsigned long ia64_iobase; /* virtual address for I/O accesses */ 79unsigned long ia64_iobase; /* virtual address for I/O accesses */
@@ -273,23 +275,25 @@ io_port_init (void)
273static inline int __init 275static inline int __init
274early_console_setup (char *cmdline) 276early_console_setup (char *cmdline)
275{ 277{
278 int earlycons = 0;
279
276#ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 280#ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
277 { 281 {
278 extern int sn_serial_console_early_setup(void); 282 extern int sn_serial_console_early_setup(void);
279 if (!sn_serial_console_early_setup()) 283 if (!sn_serial_console_early_setup())
280 return 0; 284 earlycons++;
281 } 285 }
282#endif 286#endif
283#ifdef CONFIG_EFI_PCDP 287#ifdef CONFIG_EFI_PCDP
284 if (!efi_setup_pcdp_console(cmdline)) 288 if (!efi_setup_pcdp_console(cmdline))
285 return 0; 289 earlycons++;
286#endif 290#endif
287#ifdef CONFIG_SERIAL_8250_CONSOLE 291#ifdef CONFIG_SERIAL_8250_CONSOLE
288 if (!early_serial_console_init(cmdline)) 292 if (!early_serial_console_init(cmdline))
289 return 0; 293 earlycons++;
290#endif 294#endif
291 295
292 return -1; 296 return (earlycons) ? 0 : -1;
293} 297}
294 298
295static inline void 299static inline void
diff --git a/arch/ia64/kernel/smp.c b/arch/ia64/kernel/smp.c
index b49d4ddaab93..0166a9847095 100644
--- a/arch/ia64/kernel/smp.c
+++ b/arch/ia64/kernel/smp.c
@@ -231,13 +231,16 @@ smp_flush_tlb_all (void)
231void 231void
232smp_flush_tlb_mm (struct mm_struct *mm) 232smp_flush_tlb_mm (struct mm_struct *mm)
233{ 233{
234 preempt_disable();
234 /* this happens for the common case of a single-threaded fork(): */ 235 /* this happens for the common case of a single-threaded fork(): */
235 if (likely(mm == current->active_mm && atomic_read(&mm->mm_users) == 1)) 236 if (likely(mm == current->active_mm && atomic_read(&mm->mm_users) == 1))
236 { 237 {
237 local_finish_flush_tlb_mm(mm); 238 local_finish_flush_tlb_mm(mm);
239 preempt_enable();
238 return; 240 return;
239 } 241 }
240 242
243 preempt_enable();
241 /* 244 /*
242 * We could optimize this further by using mm->cpu_vm_mask to track which CPUs 245 * We could optimize this further by using mm->cpu_vm_mask to track which CPUs
243 * have been running in the address space. It's not clear that this is worth the 246 * have been running in the address space. It's not clear that this is worth the
diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index 9e07f5463f21..783eb4323847 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -384,7 +384,7 @@ static int __init sn_pci_init(void)
384 extern void register_sn_procfs(void); 384 extern void register_sn_procfs(void);
385#endif 385#endif
386 386
387 if (!ia64_platform_is("sn2") || IS_RUNNING_ON_SIMULATOR()) 387 if (!ia64_platform_is("sn2") || IS_RUNNING_ON_FAKE_PROM())
388 return 0; 388 return 0;
389 389
390 /* 390 /*
diff --git a/arch/ia64/sn/kernel/iomv.c b/arch/ia64/sn/kernel/iomv.c
index fec6d8b8237b..7ce3cdad627b 100644
--- a/arch/ia64/sn/kernel/iomv.c
+++ b/arch/ia64/sn/kernel/iomv.c
@@ -9,12 +9,16 @@
9#include <linux/module.h> 9#include <linux/module.h>
10#include <asm/io.h> 10#include <asm/io.h>
11#include <asm/delay.h> 11#include <asm/delay.h>
12#include <asm/vga.h>
12#include <asm/sn/nodepda.h> 13#include <asm/sn/nodepda.h>
13#include <asm/sn/simulator.h> 14#include <asm/sn/simulator.h>
14#include <asm/sn/pda.h> 15#include <asm/sn/pda.h>
15#include <asm/sn/sn_cpuid.h> 16#include <asm/sn/sn_cpuid.h>
16#include <asm/sn/shub_mmr.h> 17#include <asm/sn/shub_mmr.h>
17 18
19#define IS_LEGACY_VGA_IOPORT(p) \
20 (((p) >= 0x3b0 && (p) <= 0x3bb) || ((p) >= 0x3c0 && (p) <= 0x3df))
21
18/** 22/**
19 * sn_io_addr - convert an in/out port to an i/o address 23 * sn_io_addr - convert an in/out port to an i/o address
20 * @port: port to convert 24 * @port: port to convert
@@ -26,6 +30,8 @@
26void *sn_io_addr(unsigned long port) 30void *sn_io_addr(unsigned long port)
27{ 31{
28 if (!IS_RUNNING_ON_SIMULATOR()) { 32 if (!IS_RUNNING_ON_SIMULATOR()) {
33 if (IS_LEGACY_VGA_IOPORT(port))
34 port += vga_console_iobase;
29 /* On sn2, legacy I/O ports don't point at anything */ 35 /* On sn2, legacy I/O ports don't point at anything */
30 if (port < (64 * 1024)) 36 if (port < (64 * 1024))
31 return NULL; 37 return NULL;
diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c
index 44bfc7f318cb..22e10d282c7f 100644
--- a/arch/ia64/sn/kernel/setup.c
+++ b/arch/ia64/sn/kernel/setup.c
@@ -36,6 +36,7 @@
36#include <asm/machvec.h> 36#include <asm/machvec.h>
37#include <asm/system.h> 37#include <asm/system.h>
38#include <asm/processor.h> 38#include <asm/processor.h>
39#include <asm/vga.h>
39#include <asm/sn/arch.h> 40#include <asm/sn/arch.h>
40#include <asm/sn/addrs.h> 41#include <asm/sn/addrs.h>
41#include <asm/sn/pda.h> 42#include <asm/sn/pda.h>
@@ -95,6 +96,7 @@ u8 sn_coherency_id;
95EXPORT_SYMBOL(sn_coherency_id); 96EXPORT_SYMBOL(sn_coherency_id);
96u8 sn_region_size; 97u8 sn_region_size;
97EXPORT_SYMBOL(sn_region_size); 98EXPORT_SYMBOL(sn_region_size);
99int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
98 100
99short physical_node_map[MAX_PHYSNODE_ID]; 101short physical_node_map[MAX_PHYSNODE_ID];
100 102
@@ -273,14 +275,17 @@ void __init sn_setup(char **cmdline_p)
273 275
274 ia64_sn_plat_set_error_handling_features(); 276 ia64_sn_plat_set_error_handling_features();
275 277
278#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
276 /* 279 /*
277 * If the generic code has enabled vga console support - lets 280 * If there was a primary vga adapter identified through the
278 * get rid of it again. This is a kludge for the fact that ACPI 281 * EFI PCDP table, make it the preferred console. Otherwise
279 * currtently has no way of informing us if legacy VGA is available 282 * zero out conswitchp.
280 * or not.
281 */ 283 */
282#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 284
283 if (conswitchp == &vga_con) { 285 if (vga_console_membase) {
286 /* usable vga ... make tty0 the preferred default console */
287 add_preferred_console("tty", 0, NULL);
288 } else {
284 printk(KERN_DEBUG "SGI: Disabling VGA console\n"); 289 printk(KERN_DEBUG "SGI: Disabling VGA console\n");
285#ifdef CONFIG_DUMMY_CONSOLE 290#ifdef CONFIG_DUMMY_CONSOLE
286 conswitchp = &dummy_con; 291 conswitchp = &dummy_con;
@@ -350,7 +355,7 @@ void __init sn_setup(char **cmdline_p)
350 355
351 ia64_mark_idle = &snidle; 356 ia64_mark_idle = &snidle;
352 357
353 /* 358 /*
354 * For the bootcpu, we do this here. All other cpus will make the 359 * For the bootcpu, we do this here. All other cpus will make the
355 * call as part of cpu_init in slave cpu initialization. 360 * call as part of cpu_init in slave cpu initialization.
356 */ 361 */
@@ -397,7 +402,7 @@ static void __init sn_init_pdas(char **cmdline_p)
397 nodepdaindr[cnode] = 402 nodepdaindr[cnode] =
398 alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t)); 403 alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t));
399 memset(nodepdaindr[cnode], 0, sizeof(nodepda_t)); 404 memset(nodepdaindr[cnode], 0, sizeof(nodepda_t));
400 memset(nodepdaindr[cnode]->phys_cpuid, -1, 405 memset(nodepdaindr[cnode]->phys_cpuid, -1,
401 sizeof(nodepdaindr[cnode]->phys_cpuid)); 406 sizeof(nodepdaindr[cnode]->phys_cpuid));
402 } 407 }
403 408
@@ -427,7 +432,7 @@ static void __init sn_init_pdas(char **cmdline_p)
427 } 432 }
428 433
429 /* 434 /*
430 * Initialize the per node hubdev. This includes IO Nodes and 435 * Initialize the per node hubdev. This includes IO Nodes and
431 * headless/memless nodes. 436 * headless/memless nodes.
432 */ 437 */
433 for (cnode = 0; cnode < numionodes; cnode++) { 438 for (cnode = 0; cnode < numionodes; cnode++) {
@@ -455,6 +460,14 @@ void __init sn_cpu_init(void)
455 int i; 460 int i;
456 static int wars_have_been_checked; 461 static int wars_have_been_checked;
457 462
463 if (smp_processor_id() == 0 && IS_MEDUSA()) {
464 if (ia64_sn_is_fake_prom())
465 sn_prom_type = 2;
466 else
467 sn_prom_type = 1;
468 printk("Running on medusa with %s PROM\n", (sn_prom_type == 1) ? "real" : "fake");
469 }
470
458 memset(pda, 0, sizeof(pda)); 471 memset(pda, 0, sizeof(pda));
459 if (ia64_sn_get_sn_info(0, &sn_hub_info->shub2, &sn_hub_info->nasid_bitmask, &sn_hub_info->nasid_shift, 472 if (ia64_sn_get_sn_info(0, &sn_hub_info->shub2, &sn_hub_info->nasid_bitmask, &sn_hub_info->nasid_shift,
460 &sn_system_size, &sn_sharing_domain_size, &sn_partition_id, 473 &sn_system_size, &sn_sharing_domain_size, &sn_partition_id,
@@ -520,7 +533,7 @@ void __init sn_cpu_init(void)
520 */ 533 */
521 { 534 {
522 u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0}; 535 u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0};
523 u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_1, 536 u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_1,
524 SH2_PIO_WRITE_STATUS_2, SH2_PIO_WRITE_STATUS_3}; 537 SH2_PIO_WRITE_STATUS_2, SH2_PIO_WRITE_STATUS_3};
525 u64 *pio; 538 u64 *pio;
526 pio = is_shub1() ? pio1 : pio2; 539 pio = is_shub1() ? pio1 : pio2;
@@ -552,6 +565,10 @@ static void __init scan_for_ionodes(void)
552 int nasid = 0; 565 int nasid = 0;
553 lboard_t *brd; 566 lboard_t *brd;
554 567
568 /* fakeprom does not support klgraph */
569 if (IS_RUNNING_ON_FAKE_PROM())
570 return;
571
555 /* Setup ionodes with memory */ 572 /* Setup ionodes with memory */
556 for (nasid = 0; nasid < MAX_PHYSNODE_ID; nasid += 2) { 573 for (nasid = 0; nasid < MAX_PHYSNODE_ID; nasid += 2) {
557 char *klgraph_header; 574 char *klgraph_header;
@@ -563,8 +580,6 @@ static void __init scan_for_ionodes(void)
563 cnodeid = -1; 580 cnodeid = -1;
564 klgraph_header = __va(ia64_sn_get_klconfig_addr(nasid)); 581 klgraph_header = __va(ia64_sn_get_klconfig_addr(nasid));
565 if (!klgraph_header) { 582 if (!klgraph_header) {
566 if (IS_RUNNING_ON_SIMULATOR())
567 continue;
568 BUG(); /* All nodes must have klconfig tables! */ 583 BUG(); /* All nodes must have klconfig tables! */
569 } 584 }
570 cnodeid = nasid_to_cnodeid(nasid); 585 cnodeid = nasid_to_cnodeid(nasid);
@@ -630,8 +645,8 @@ int
630nasid_slice_to_cpuid(int nasid, int slice) 645nasid_slice_to_cpuid(int nasid, int slice)
631{ 646{
632 long cpu; 647 long cpu;
633 648
634 for (cpu=0; cpu < NR_CPUS; cpu++) 649 for (cpu=0; cpu < NR_CPUS; cpu++)
635 if (cpuid_to_nasid(cpu) == nasid && 650 if (cpuid_to_nasid(cpu) == nasid &&
636 cpuid_to_slice(cpu) == slice) 651 cpuid_to_slice(cpu) == slice)
637 return cpu; 652 return cpu;
diff --git a/arch/ia64/sn/kernel/sn2/ptc_deadlock.S b/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
index 7947312801ec..96cb71d15682 100644
--- a/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
+++ b/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
@@ -6,6 +6,7 @@
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8 8
9#include <asm/types.h>
9#include <asm/sn/shub_mmr.h> 10#include <asm/sn/shub_mmr.h>
10 11
11#define DEADLOCKBIT SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 12#define DEADLOCKBIT SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
diff --git a/arch/ia64/sn/kernel/tiocx.c b/arch/ia64/sn/kernel/tiocx.c
index a087b274847e..8716f4d5314b 100644
--- a/arch/ia64/sn/kernel/tiocx.c
+++ b/arch/ia64/sn/kernel/tiocx.c
@@ -204,8 +204,8 @@ cx_device_register(nasid_t nasid, int part_num, int mfg_num,
204 cx_dev->dev.parent = NULL; 204 cx_dev->dev.parent = NULL;
205 cx_dev->dev.bus = &tiocx_bus_type; 205 cx_dev->dev.bus = &tiocx_bus_type;
206 cx_dev->dev.release = tiocx_bus_release; 206 cx_dev->dev.release = tiocx_bus_release;
207 snprintf(cx_dev->dev.bus_id, BUS_ID_SIZE, "%d.0x%x", 207 snprintf(cx_dev->dev.bus_id, BUS_ID_SIZE, "%d",
208 cx_dev->cx_id.nasid, cx_dev->cx_id.part_num); 208 cx_dev->cx_id.nasid);
209 device_register(&cx_dev->dev); 209 device_register(&cx_dev->dev);
210 get_device(&cx_dev->dev); 210 get_device(&cx_dev->dev);
211 211
@@ -236,7 +236,6 @@ int cx_device_unregister(struct cx_dev *cx_dev)
236 */ 236 */
237static int cx_device_reload(struct cx_dev *cx_dev) 237static int cx_device_reload(struct cx_dev *cx_dev)
238{ 238{
239 device_remove_file(&cx_dev->dev, &dev_attr_cxdev_control);
240 cx_device_unregister(cx_dev); 239 cx_device_unregister(cx_dev);
241 return cx_device_register(cx_dev->cx_id.nasid, cx_dev->cx_id.part_num, 240 return cx_device_register(cx_dev->cx_id.nasid, cx_dev->cx_id.part_num,
242 cx_dev->cx_id.mfg_num, cx_dev->hubdev); 241 cx_dev->cx_id.mfg_num, cx_dev->hubdev);
@@ -383,6 +382,7 @@ static int is_fpga_brick(int nasid)
383 switch (tiocx_btchar_get(nasid)) { 382 switch (tiocx_btchar_get(nasid)) {
384 case L1_BRICKTYPE_SA: 383 case L1_BRICKTYPE_SA:
385 case L1_BRICKTYPE_ATHENA: 384 case L1_BRICKTYPE_ATHENA:
385 case L1_BRICKTYPE_DAYTONA:
386 return 1; 386 return 1;
387 } 387 }
388 return 0; 388 return 0;
@@ -409,7 +409,7 @@ static int tiocx_reload(struct cx_dev *cx_dev)
409 uint64_t cx_id; 409 uint64_t cx_id;
410 410
411 cx_id = 411 cx_id =
412 *(volatile int32_t *)(TIO_SWIN_BASE(nasid, TIOCX_CORELET) + 412 *(volatile uint64_t *)(TIO_SWIN_BASE(nasid, TIOCX_CORELET) +
413 WIDGET_ID); 413 WIDGET_ID);
414 part_num = XWIDGET_PART_NUM(cx_id); 414 part_num = XWIDGET_PART_NUM(cx_id);
415 mfg_num = XWIDGET_MFG_NUM(cx_id); 415 mfg_num = XWIDGET_MFG_NUM(cx_id);
@@ -458,6 +458,10 @@ static ssize_t store_cxdev_control(struct device *dev, struct device_attribute *
458 458
459 switch (n) { 459 switch (n) {
460 case 1: 460 case 1:
461 tio_corelet_reset(cx_dev->cx_id.nasid, TIOCX_CORELET);
462 tiocx_reload(cx_dev);
463 break;
464 case 2:
461 tiocx_reload(cx_dev); 465 tiocx_reload(cx_dev);
462 break; 466 break;
463 case 3: 467 case 3:
@@ -537,7 +541,7 @@ static void __exit tiocx_exit(void)
537 bus_unregister(&tiocx_bus_type); 541 bus_unregister(&tiocx_bus_type);
538} 542}
539 543
540module_init(tiocx_init); 544subsys_initcall(tiocx_init);
541module_exit(tiocx_exit); 545module_exit(tiocx_exit);
542 546
543/************************************************************************ 547/************************************************************************
diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c
index 8dae9eb45456..05aa8c2fe9bb 100644
--- a/arch/ia64/sn/pci/tioca_provider.c
+++ b/arch/ia64/sn/pci/tioca_provider.c
@@ -336,7 +336,7 @@ tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr)
336 if (!ct_addr) 336 if (!ct_addr)
337 return 0; 337 return 0;
338 338
339 bus_addr = (dma_addr_t) (ct_addr & 0xffffffffffff); 339 bus_addr = (dma_addr_t) (ct_addr & 0xffffffffffffUL);
340 node_upper = ct_addr >> 48; 340 node_upper = ct_addr >> 48;
341 341
342 if (node_upper > 64) { 342 if (node_upper > 64) {
@@ -464,7 +464,7 @@ map_return:
464 * For mappings created using the direct modes (64 or 48) there are no 464 * For mappings created using the direct modes (64 or 48) there are no
465 * resources to release. 465 * resources to release.
466 */ 466 */
467void 467static void
468tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir) 468tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
469{ 469{
470 int i, entry; 470 int i, entry;
@@ -514,7 +514,7 @@ tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
514 * The mapping mode used is based on the devices dma_mask. As a last resort 514 * The mapping mode used is based on the devices dma_mask. As a last resort
515 * use the GART mapped mode. 515 * use the GART mapped mode.
516 */ 516 */
517uint64_t 517static uint64_t
518tioca_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count) 518tioca_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
519{ 519{
520 uint64_t mapaddr; 520 uint64_t mapaddr;
@@ -580,7 +580,7 @@ tioca_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
580 * On successful setup, returns the kernel version of tioca_common back to 580 * On successful setup, returns the kernel version of tioca_common back to
581 * the caller. 581 * the caller.
582 */ 582 */
583void * 583static void *
584tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft) 584tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft)
585{ 585{
586 struct tioca_common *tioca_common; 586 struct tioca_common *tioca_common;
diff --git a/drivers/firmware/pcdp.c b/drivers/firmware/pcdp.c
index 839b44a7e08b..53c95c0bbf46 100644
--- a/drivers/firmware/pcdp.c
+++ b/drivers/firmware/pcdp.c
@@ -16,6 +16,7 @@
16#include <linux/console.h> 16#include <linux/console.h>
17#include <linux/efi.h> 17#include <linux/efi.h>
18#include <linux/serial.h> 18#include <linux/serial.h>
19#include <asm/vga.h>
19#include "pcdp.h" 20#include "pcdp.h"
20 21
21static int __init 22static int __init
@@ -40,10 +41,27 @@ setup_serial_console(struct pcdp_uart *uart)
40} 41}
41 42
42static int __init 43static int __init
43setup_vga_console(struct pcdp_vga *vga) 44setup_vga_console(struct pcdp_device *dev)
44{ 45{
45#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 46#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
46 if (efi_mem_type(0xA0000) == EFI_CONVENTIONAL_MEMORY) { 47 u8 *if_ptr;
48
49 if_ptr = ((u8 *)dev + sizeof(struct pcdp_device));
50 if (if_ptr[0] == PCDP_IF_PCI) {
51 struct pcdp_if_pci if_pci;
52
53 /* struct copy since ifptr might not be correctly aligned */
54
55 memcpy(&if_pci, if_ptr, sizeof(if_pci));
56
57 if (if_pci.trans & PCDP_PCI_TRANS_IOPORT)
58 vga_console_iobase = if_pci.ioport_tra;
59
60 if (if_pci.trans & PCDP_PCI_TRANS_MMIO)
61 vga_console_membase = if_pci.mmio_tra;
62 }
63
64 if (efi_mem_type(vga_console_membase + 0xA0000) == EFI_CONVENTIONAL_MEMORY) {
47 printk(KERN_ERR "PCDP: VGA selected, but frame buffer is not MMIO!\n"); 65 printk(KERN_ERR "PCDP: VGA selected, but frame buffer is not MMIO!\n");
48 return -ENODEV; 66 return -ENODEV;
49 } 67 }
@@ -95,7 +113,7 @@ efi_setup_pcdp_console(char *cmdline)
95 dev = (struct pcdp_device *) ((u8 *) dev + dev->length)) { 113 dev = (struct pcdp_device *) ((u8 *) dev + dev->length)) {
96 if (dev->flags & PCDP_PRIMARY_CONSOLE) { 114 if (dev->flags & PCDP_PRIMARY_CONSOLE) {
97 if (dev->type == PCDP_CONSOLE_VGA) { 115 if (dev->type == PCDP_CONSOLE_VGA) {
98 return setup_vga_console((struct pcdp_vga *) dev); 116 return setup_vga_console(dev);
99 } 117 }
100 } 118 }
101 } 119 }
diff --git a/drivers/firmware/pcdp.h b/drivers/firmware/pcdp.h
index 1dc7c88b7b4d..e72cc47de33b 100644
--- a/drivers/firmware/pcdp.h
+++ b/drivers/firmware/pcdp.h
@@ -52,11 +52,34 @@ struct pcdp_uart {
52 u32 clock_rate; 52 u32 clock_rate;
53 u8 pci_prog_intfc; 53 u8 pci_prog_intfc;
54 u8 flags; 54 u8 flags;
55}; 55} __attribute__((packed));
56
57#define PCDP_IF_PCI 1
58
59/* pcdp_if_pci.trans */
60#define PCDP_PCI_TRANS_IOPORT 0x02
61#define PCDP_PCI_TRANS_MMIO 0x01
62
63struct pcdp_if_pci {
64 u8 interconnect;
65 u8 reserved;
66 u16 length;
67 u8 segment;
68 u8 bus;
69 u8 dev;
70 u8 fun;
71 u16 dev_id;
72 u16 vendor_id;
73 u32 acpi_interrupt;
74 u64 mmio_tra;
75 u64 ioport_tra;
76 u8 flags;
77 u8 trans;
78} __attribute__((packed));
56 79
57struct pcdp_vga { 80struct pcdp_vga {
58 u8 count; /* address space descriptors */ 81 u8 count; /* address space descriptors */
59}; 82} __attribute__((packed));
60 83
61/* pcdp_device.flags */ 84/* pcdp_device.flags */
62#define PCDP_PRIMARY_CONSOLE 1 85#define PCDP_PRIMARY_CONSOLE 1
@@ -66,7 +89,9 @@ struct pcdp_device {
66 u8 flags; 89 u8 flags;
67 u16 length; 90 u16 length;
68 u16 efi_index; 91 u16 efi_index;
69}; 92 /* next data is pcdp_if_pci or pcdp_if_acpi (not yet supported) */
93 /* next data is device specific type (currently only pcdp_vga) */
94} __attribute__((packed));
70 95
71struct pcdp { 96struct pcdp {
72 u8 signature[4]; 97 u8 signature[4];
@@ -81,4 +106,4 @@ struct pcdp {
81 u32 num_uarts; 106 u32 num_uarts;
82 struct pcdp_uart uart[0]; /* actual size is num_uarts */ 107 struct pcdp_uart uart[0]; /* actual size is num_uarts */
83 /* remainder of table is pcdp_device structures */ 108 /* remainder of table is pcdp_device structures */
84}; 109} __attribute__((packed));
diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h
index 0096e7e05012..e3e5fededb04 100644
--- a/include/asm-ia64/mmu_context.h
+++ b/include/asm-ia64/mmu_context.h
@@ -132,6 +132,9 @@ reload_context (mm_context_t context)
132 ia64_srlz_i(); /* srlz.i implies srlz.d */ 132 ia64_srlz_i(); /* srlz.i implies srlz.d */
133} 133}
134 134
135/*
136 * Must be called with preemption off
137 */
135static inline void 138static inline void
136activate_context (struct mm_struct *mm) 139activate_context (struct mm_struct *mm)
137{ 140{
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index 1bfdfb4d7b01..103d745dc5f2 100644
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -216,6 +216,10 @@
216#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK) 216#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
217 217
218 218
219#define TIO_IOSPACE_ADDR(n,x) \
220 /* Move in the Chiplet ID for TIO Local Block MMR */ \
221 (REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2))
222
219/* 223/*
220 * The following macros produce the correct base virtual address for 224 * The following macros produce the correct base virtual address for
221 * the hub registers. The REMOTE_HUB_* macro produce 225 * the hub registers. The REMOTE_HUB_* macro produce
@@ -233,13 +237,16 @@
233#define REMOTE_HUB_ADDR(n,x) \ 237#define REMOTE_HUB_ADDR(n,x) \
234 ((n & 1) ? \ 238 ((n & 1) ? \
235 /* TIO: */ \ 239 /* TIO: */ \
236 ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \ 240 (is_shub2() ? \
237 : /* SHUB: */ \ 241 /* TIO on Shub2 */ \
238 (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))\ 242 (volatile u64 *)(TIO_IOSPACE_ADDR(n,x)) \
243 : /* TIO on shub1 */ \
244 (volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
245 \
246 : /* SHUB1 and SHUB2 MMRs: */ \
247 (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
239 : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x))))) 248 : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
240 249
241
242
243#define HUB_L(x) (*((volatile typeof(*x) *)x)) 250#define HUB_L(x) (*((volatile typeof(*x) *)x))
244#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d)) 251#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
245 252
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
index 08050d37b662..2e5f0aa38889 100644
--- a/include/asm-ia64/sn/l1.h
+++ b/include/asm-ia64/sn/l1.h
@@ -33,5 +33,6 @@
33#define L1_BRICKTYPE_PA 0x6a /* j */ 33#define L1_BRICKTYPE_PA 0x6a /* j */
34#define L1_BRICKTYPE_IA 0x6b /* k */ 34#define L1_BRICKTYPE_IA 0x6b /* k */
35#define L1_BRICKTYPE_ATHENA 0x2b /* + */ 35#define L1_BRICKTYPE_ATHENA 0x2b /* + */
36#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
36 37
37#endif /* _ASM_IA64_SN_L1_H */ 38#endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
index 323fa0cd8d83..7de1d1d4b71a 100644
--- a/include/asm-ia64/sn/shub_mmr.h
+++ b/include/asm-ia64/sn/shub_mmr.h
@@ -14,96 +14,98 @@
14/* Register "SH_IPI_INT" */ 14/* Register "SH_IPI_INT" */
15/* SHub Inter-Processor Interrupt Registers */ 15/* SHub Inter-Processor Interrupt Registers */
16/* ==================================================================== */ 16/* ==================================================================== */
17#define SH1_IPI_INT 0x0000000110000380 17#define SH1_IPI_INT __IA64_UL_CONST(0x0000000110000380)
18#define SH2_IPI_INT 0x0000000010000380 18#define SH2_IPI_INT __IA64_UL_CONST(0x0000000010000380)
19 19
20/* SH_IPI_INT_TYPE */ 20/* SH_IPI_INT_TYPE */
21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
22#define SH_IPI_INT_TYPE_SHFT 0 22#define SH_IPI_INT_TYPE_SHFT 0
23#define SH_IPI_INT_TYPE_MASK 0x0000000000000007 23#define SH_IPI_INT_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
24 24
25/* SH_IPI_INT_AGT */ 25/* SH_IPI_INT_AGT */
26/* Description: Agent, must be 0 for SHub */ 26/* Description: Agent, must be 0 for SHub */
27#define SH_IPI_INT_AGT_SHFT 3 27#define SH_IPI_INT_AGT_SHFT 3
28#define SH_IPI_INT_AGT_MASK 0x0000000000000008 28#define SH_IPI_INT_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
29 29
30/* SH_IPI_INT_PID */ 30/* SH_IPI_INT_PID */
31/* Description: Processor ID, same setting as on targeted McKinley */ 31/* Description: Processor ID, same setting as on targeted McKinley */
32#define SH_IPI_INT_PID_SHFT 4 32#define SH_IPI_INT_PID_SHFT 4
33#define SH_IPI_INT_PID_MASK 0x00000000000ffff0 33#define SH_IPI_INT_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
34 34
35/* SH_IPI_INT_BASE */ 35/* SH_IPI_INT_BASE */
36/* Description: Optional interrupt vector area, 2MB aligned */ 36/* Description: Optional interrupt vector area, 2MB aligned */
37#define SH_IPI_INT_BASE_SHFT 21 37#define SH_IPI_INT_BASE_SHFT 21
38#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000 38#define SH_IPI_INT_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
39 39
40/* SH_IPI_INT_IDX */ 40/* SH_IPI_INT_IDX */
41/* Description: Targeted McKinley interrupt vector */ 41/* Description: Targeted McKinley interrupt vector */
42#define SH_IPI_INT_IDX_SHFT 52 42#define SH_IPI_INT_IDX_SHFT 52
43#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000 43#define SH_IPI_INT_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
44 44
45/* SH_IPI_INT_SEND */ 45/* SH_IPI_INT_SEND */
46/* Description: Send Interrupt Message to PI, This generates a puls */ 46/* Description: Send Interrupt Message to PI, This generates a puls */
47#define SH_IPI_INT_SEND_SHFT 63 47#define SH_IPI_INT_SEND_SHFT 63
48#define SH_IPI_INT_SEND_MASK 0x8000000000000000 48#define SH_IPI_INT_SEND_MASK __IA64_UL_CONST(0x8000000000000000)
49 49
50/* ==================================================================== */ 50/* ==================================================================== */
51/* Register "SH_EVENT_OCCURRED" */ 51/* Register "SH_EVENT_OCCURRED" */
52/* SHub Interrupt Event Occurred */ 52/* SHub Interrupt Event Occurred */
53/* ==================================================================== */ 53/* ==================================================================== */
54#define SH1_EVENT_OCCURRED 0x0000000110010000 54#define SH1_EVENT_OCCURRED __IA64_UL_CONST(0x0000000110010000)
55#define SH1_EVENT_OCCURRED_ALIAS 0x0000000110010008 55#define SH1_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000110010008)
56#define SH2_EVENT_OCCURRED 0x0000000010010000 56#define SH2_EVENT_OCCURRED __IA64_UL_CONST(0x0000000010010000)
57#define SH2_EVENT_OCCURRED_ALIAS 0x0000000010010008 57#define SH2_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000010010008)
58 58
59/* ==================================================================== */ 59/* ==================================================================== */
60/* Register "SH_PI_CAM_CONTROL" */ 60/* Register "SH_PI_CAM_CONTROL" */
61/* CRB CAM MMR Access Control */ 61/* CRB CAM MMR Access Control */
62/* ==================================================================== */ 62/* ==================================================================== */
63#define SH1_PI_CAM_CONTROL 0x0000000120050300 63#define SH1_PI_CAM_CONTROL __IA64_UL_CONST(0x0000000120050300)
64 64
65/* ==================================================================== */ 65/* ==================================================================== */
66/* Register "SH_SHUB_ID" */ 66/* Register "SH_SHUB_ID" */
67/* SHub ID Number */ 67/* SHub ID Number */
68/* ==================================================================== */ 68/* ==================================================================== */
69#define SH1_SHUB_ID 0x0000000110060580 69#define SH1_SHUB_ID __IA64_UL_CONST(0x0000000110060580)
70#define SH1_SHUB_ID_REVISION_SHFT 28 70#define SH1_SHUB_ID_REVISION_SHFT 28
71#define SH1_SHUB_ID_REVISION_MASK 0x00000000f0000000 71#define SH1_SHUB_ID_REVISION_MASK __IA64_UL_CONST(0x00000000f0000000)
72 72
73/* ==================================================================== */ 73/* ==================================================================== */
74/* Register "SH_RTC" */ 74/* Register "SH_RTC" */
75/* Real-time Clock */ 75/* Real-time Clock */
76/* ==================================================================== */ 76/* ==================================================================== */
77#define SH1_RTC 0x00000001101c0000 77#define SH1_RTC __IA64_UL_CONST(0x00000001101c0000)
78#define SH2_RTC 0x00000002101c0000 78#define SH2_RTC __IA64_UL_CONST(0x00000002101c0000)
79#define SH_RTC_MASK 0x007fffffffffffff 79#define SH_RTC_MASK __IA64_UL_CONST(0x007fffffffffffff)
80 80
81/* ==================================================================== */ 81/* ==================================================================== */
82/* Register "SH_PIO_WRITE_STATUS_0|1" */ 82/* Register "SH_PIO_WRITE_STATUS_0|1" */
83/* PIO Write Status for CPU 0 & 1 */ 83/* PIO Write Status for CPU 0 & 1 */
84/* ==================================================================== */ 84/* ==================================================================== */
85#define SH1_PIO_WRITE_STATUS_0 0x0000000120070200 85#define SH1_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000120070200)
86#define SH1_PIO_WRITE_STATUS_1 0x0000000120070280 86#define SH1_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000120070280)
87#define SH2_PIO_WRITE_STATUS_0 0x0000000020070200 87#define SH2_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000020070200)
88#define SH2_PIO_WRITE_STATUS_1 0x0000000020070280 88#define SH2_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000020070280)
89#define SH2_PIO_WRITE_STATUS_2 0x0000000020070300 89#define SH2_PIO_WRITE_STATUS_2 __IA64_UL_CONST(0x0000000020070300)
90#define SH2_PIO_WRITE_STATUS_3 0x0000000020070380 90#define SH2_PIO_WRITE_STATUS_3 __IA64_UL_CONST(0x0000000020070380)
91 91
92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ 92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */
93/* Description: Deadlock response detected */ 93/* Description: Deadlock response detected */
94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1 94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK 0x0000000000000002 95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
96 __IA64_UL_CONST(0x0000000000000002)
96 97
97/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ 98/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */
98/* Description: Count of currently pending PIO writes */ 99/* Description: Count of currently pending PIO writes */
99#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56 100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 101#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
102 __IA64_UL_CONST(0x3f00000000000000)
101 103
102/* ==================================================================== */ 104/* ==================================================================== */
103/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ 105/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */
104/* ==================================================================== */ 106/* ==================================================================== */
105#define SH1_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 107#define SH1_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000120070208)
106#define SH2_PIO_WRITE_STATUS_0_ALIAS 0x0000000020070208 108#define SH2_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000020070208)
107 109
108/* ==================================================================== */ 110/* ==================================================================== */
109/* Register "SH_EVENT_OCCURRED" */ 111/* Register "SH_EVENT_OCCURRED" */
@@ -111,33 +113,33 @@
111/* ==================================================================== */ 113/* ==================================================================== */
112/* SH_EVENT_OCCURRED_UART_INT */ 114/* SH_EVENT_OCCURRED_UART_INT */
113/* Description: Pending Junk Bus UART Interrupt */ 115/* Description: Pending Junk Bus UART Interrupt */
114#define SH_EVENT_OCCURRED_UART_INT_SHFT 20 116#define SH_EVENT_OCCURRED_UART_INT_SHFT 20
115#define SH_EVENT_OCCURRED_UART_INT_MASK 0x0000000000100000 117#define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000)
116 118
117/* SH_EVENT_OCCURRED_IPI_INT */ 119/* SH_EVENT_OCCURRED_IPI_INT */
118/* Description: Pending IPI Interrupt */ 120/* Description: Pending IPI Interrupt */
119#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28 121#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28
120#define SH_EVENT_OCCURRED_IPI_INT_MASK 0x0000000010000000 122#define SH_EVENT_OCCURRED_IPI_INT_MASK __IA64_UL_CONST(0x0000000010000000)
121 123
122/* SH_EVENT_OCCURRED_II_INT0 */ 124/* SH_EVENT_OCCURRED_II_INT0 */
123/* Description: Pending II 0 Interrupt */ 125/* Description: Pending II 0 Interrupt */
124#define SH_EVENT_OCCURRED_II_INT0_SHFT 29 126#define SH_EVENT_OCCURRED_II_INT0_SHFT 29
125#define SH_EVENT_OCCURRED_II_INT0_MASK 0x0000000020000000 127#define SH_EVENT_OCCURRED_II_INT0_MASK __IA64_UL_CONST(0x0000000020000000)
126 128
127/* SH_EVENT_OCCURRED_II_INT1 */ 129/* SH_EVENT_OCCURRED_II_INT1 */
128/* Description: Pending II 1 Interrupt */ 130/* Description: Pending II 1 Interrupt */
129#define SH_EVENT_OCCURRED_II_INT1_SHFT 30 131#define SH_EVENT_OCCURRED_II_INT1_SHFT 30
130#define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 132#define SH_EVENT_OCCURRED_II_INT1_MASK __IA64_UL_CONST(0x0000000040000000)
131 133
132/* SH2_EVENT_OCCURRED_EXTIO_INT2 */ 134/* SH2_EVENT_OCCURRED_EXTIO_INT2 */
133/* Description: Pending SHUB 2 EXT IO INT2 */ 135/* Description: Pending SHUB 2 EXT IO INT2 */
134#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33 136#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33
135#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK 0x0000000200000000 137#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
136 138
137/* SH2_EVENT_OCCURRED_EXTIO_INT3 */ 139/* SH2_EVENT_OCCURRED_EXTIO_INT3 */
138/* Description: Pending SHUB 2 EXT IO INT3 */ 140/* Description: Pending SHUB 2 EXT IO INT3 */
139#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34 141#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34
140#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK 0x0000000400000000 142#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
141 143
142#define SH_ALL_INT_MASK \ 144#define SH_ALL_INT_MASK \
143 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \ 145 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
@@ -149,310 +151,310 @@
149/* ==================================================================== */ 151/* ==================================================================== */
150/* LEDS */ 152/* LEDS */
151/* ==================================================================== */ 153/* ==================================================================== */
152#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL 154#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL
153#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL 155#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL
154#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL 156#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL
155#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL 157#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL
156 158
157#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL 159#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL
158#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL 160#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL
159#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL 161#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL
160#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL 162#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL
161 163
162/* ==================================================================== */ 164/* ==================================================================== */
163/* Register "SH1_PTC_0" */ 165/* Register "SH1_PTC_0" */
164/* Puge Translation Cache Message Configuration Information */ 166/* Puge Translation Cache Message Configuration Information */
165/* ==================================================================== */ 167/* ==================================================================== */
166#define SH1_PTC_0 0x00000001101a0000 168#define SH1_PTC_0 __IA64_UL_CONST(0x00000001101a0000)
167 169
168/* SH1_PTC_0_A */ 170/* SH1_PTC_0_A */
169/* Description: Type */ 171/* Description: Type */
170#define SH1_PTC_0_A_SHFT 0 172#define SH1_PTC_0_A_SHFT 0
171 173
172/* SH1_PTC_0_PS */ 174/* SH1_PTC_0_PS */
173/* Description: Page Size */ 175/* Description: Page Size */
174#define SH1_PTC_0_PS_SHFT 2 176#define SH1_PTC_0_PS_SHFT 2
175 177
176/* SH1_PTC_0_RID */ 178/* SH1_PTC_0_RID */
177/* Description: Region ID */ 179/* Description: Region ID */
178#define SH1_PTC_0_RID_SHFT 8 180#define SH1_PTC_0_RID_SHFT 8
179 181
180/* SH1_PTC_0_START */ 182/* SH1_PTC_0_START */
181/* Description: Start */ 183/* Description: Start */
182#define SH1_PTC_0_START_SHFT 63 184#define SH1_PTC_0_START_SHFT 63
183 185
184/* ==================================================================== */ 186/* ==================================================================== */
185/* Register "SH1_PTC_1" */ 187/* Register "SH1_PTC_1" */
186/* Puge Translation Cache Message Configuration Information */ 188/* Puge Translation Cache Message Configuration Information */
187/* ==================================================================== */ 189/* ==================================================================== */
188#define SH1_PTC_1 0x00000001101a0080 190#define SH1_PTC_1 __IA64_UL_CONST(0x00000001101a0080)
189 191
190/* SH1_PTC_1_START */ 192/* SH1_PTC_1_START */
191/* Description: PTC_1 Start */ 193/* Description: PTC_1 Start */
192#define SH1_PTC_1_START_SHFT 63 194#define SH1_PTC_1_START_SHFT 63
193
194 195
195/* ==================================================================== */ 196/* ==================================================================== */
196/* Register "SH2_PTC" */ 197/* Register "SH2_PTC" */
197/* Puge Translation Cache Message Configuration Information */ 198/* Puge Translation Cache Message Configuration Information */
198/* ==================================================================== */ 199/* ==================================================================== */
199#define SH2_PTC 0x0000000170000000 200#define SH2_PTC __IA64_UL_CONST(0x0000000170000000)
200 201
201/* SH2_PTC_A */ 202/* SH2_PTC_A */
202/* Description: Type */ 203/* Description: Type */
203#define SH2_PTC_A_SHFT 0 204#define SH2_PTC_A_SHFT 0
204 205
205/* SH2_PTC_PS */ 206/* SH2_PTC_PS */
206/* Description: Page Size */ 207/* Description: Page Size */
207#define SH2_PTC_PS_SHFT 2 208#define SH2_PTC_PS_SHFT 2
208 209
209/* SH2_PTC_RID */ 210/* SH2_PTC_RID */
210/* Description: Region ID */ 211/* Description: Region ID */
211#define SH2_PTC_RID_SHFT 4 212#define SH2_PTC_RID_SHFT 4
212 213
213/* SH2_PTC_START */ 214/* SH2_PTC_START */
214/* Description: Start */ 215/* Description: Start */
215#define SH2_PTC_START_SHFT 63 216#define SH2_PTC_START_SHFT 63
216 217
217/* SH2_PTC_ADDR_RID */ 218/* SH2_PTC_ADDR_RID */
218/* Description: Region ID */ 219/* Description: Region ID */
219#define SH2_PTC_ADDR_SHFT 4 220#define SH2_PTC_ADDR_SHFT 4
220#define SH2_PTC_ADDR_MASK 0x1ffffffffffff000 221#define SH2_PTC_ADDR_MASK __IA64_UL_CONST(0x1ffffffffffff000)
221 222
222/* ==================================================================== */ 223/* ==================================================================== */
223/* Register "SH_RTC1_INT_CONFIG" */ 224/* Register "SH_RTC1_INT_CONFIG" */
224/* SHub RTC 1 Interrupt Config Registers */ 225/* SHub RTC 1 Interrupt Config Registers */
225/* ==================================================================== */ 226/* ==================================================================== */
226 227
227#define SH1_RTC1_INT_CONFIG 0x0000000110001480 228#define SH1_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000110001480)
228#define SH2_RTC1_INT_CONFIG 0x0000000010001480 229#define SH2_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000010001480)
229#define SH_RTC1_INT_CONFIG_MASK 0x0ff3ffffffefffff 230#define SH_RTC1_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
230#define SH_RTC1_INT_CONFIG_INIT 0x0000000000000000 231#define SH_RTC1_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
231 232
232/* SH_RTC1_INT_CONFIG_TYPE */ 233/* SH_RTC1_INT_CONFIG_TYPE */
233/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 234/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
234#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0 235#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0
235#define SH_RTC1_INT_CONFIG_TYPE_MASK 0x0000000000000007 236#define SH_RTC1_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
236 237
237/* SH_RTC1_INT_CONFIG_AGT */ 238/* SH_RTC1_INT_CONFIG_AGT */
238/* Description: Agent, must be 0 for SHub */ 239/* Description: Agent, must be 0 for SHub */
239#define SH_RTC1_INT_CONFIG_AGT_SHFT 3 240#define SH_RTC1_INT_CONFIG_AGT_SHFT 3
240#define SH_RTC1_INT_CONFIG_AGT_MASK 0x0000000000000008 241#define SH_RTC1_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
241 242
242/* SH_RTC1_INT_CONFIG_PID */ 243/* SH_RTC1_INT_CONFIG_PID */
243/* Description: Processor ID, same setting as on targeted McKinley */ 244/* Description: Processor ID, same setting as on targeted McKinley */
244#define SH_RTC1_INT_CONFIG_PID_SHFT 4 245#define SH_RTC1_INT_CONFIG_PID_SHFT 4
245#define SH_RTC1_INT_CONFIG_PID_MASK 0x00000000000ffff0 246#define SH_RTC1_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
246 247
247/* SH_RTC1_INT_CONFIG_BASE */ 248/* SH_RTC1_INT_CONFIG_BASE */
248/* Description: Optional interrupt vector area, 2MB aligned */ 249/* Description: Optional interrupt vector area, 2MB aligned */
249#define SH_RTC1_INT_CONFIG_BASE_SHFT 21 250#define SH_RTC1_INT_CONFIG_BASE_SHFT 21
250#define SH_RTC1_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 251#define SH_RTC1_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
251 252
252/* SH_RTC1_INT_CONFIG_IDX */ 253/* SH_RTC1_INT_CONFIG_IDX */
253/* Description: Targeted McKinley interrupt vector */ 254/* Description: Targeted McKinley interrupt vector */
254#define SH_RTC1_INT_CONFIG_IDX_SHFT 52 255#define SH_RTC1_INT_CONFIG_IDX_SHFT 52
255#define SH_RTC1_INT_CONFIG_IDX_MASK 0x0ff0000000000000 256#define SH_RTC1_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
256 257
257/* ==================================================================== */ 258/* ==================================================================== */
258/* Register "SH_RTC1_INT_ENABLE" */ 259/* Register "SH_RTC1_INT_ENABLE" */
259/* SHub RTC 1 Interrupt Enable Registers */ 260/* SHub RTC 1 Interrupt Enable Registers */
260/* ==================================================================== */ 261/* ==================================================================== */
261 262
262#define SH1_RTC1_INT_ENABLE 0x0000000110001500 263#define SH1_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000110001500)
263#define SH2_RTC1_INT_ENABLE 0x0000000010001500 264#define SH2_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000010001500)
264#define SH_RTC1_INT_ENABLE_MASK 0x0000000000000001 265#define SH_RTC1_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
265#define SH_RTC1_INT_ENABLE_INIT 0x0000000000000000 266#define SH_RTC1_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
266 267
267/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */ 268/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */
268/* Description: Enable RTC 1 Interrupt */ 269/* Description: Enable RTC 1 Interrupt */
269#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0 270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0
270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK 0x0000000000000001 271#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
272 __IA64_UL_CONST(0x0000000000000001)
271 273
272/* ==================================================================== */ 274/* ==================================================================== */
273/* Register "SH_RTC2_INT_CONFIG" */ 275/* Register "SH_RTC2_INT_CONFIG" */
274/* SHub RTC 2 Interrupt Config Registers */ 276/* SHub RTC 2 Interrupt Config Registers */
275/* ==================================================================== */ 277/* ==================================================================== */
276 278
277#define SH1_RTC2_INT_CONFIG 0x0000000110001580 279#define SH1_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000110001580)
278#define SH2_RTC2_INT_CONFIG 0x0000000010001580 280#define SH2_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000010001580)
279#define SH_RTC2_INT_CONFIG_MASK 0x0ff3ffffffefffff 281#define SH_RTC2_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
280#define SH_RTC2_INT_CONFIG_INIT 0x0000000000000000 282#define SH_RTC2_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
281 283
282/* SH_RTC2_INT_CONFIG_TYPE */ 284/* SH_RTC2_INT_CONFIG_TYPE */
283/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 285/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
284#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0 286#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0
285#define SH_RTC2_INT_CONFIG_TYPE_MASK 0x0000000000000007 287#define SH_RTC2_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
286 288
287/* SH_RTC2_INT_CONFIG_AGT */ 289/* SH_RTC2_INT_CONFIG_AGT */
288/* Description: Agent, must be 0 for SHub */ 290/* Description: Agent, must be 0 for SHub */
289#define SH_RTC2_INT_CONFIG_AGT_SHFT 3 291#define SH_RTC2_INT_CONFIG_AGT_SHFT 3
290#define SH_RTC2_INT_CONFIG_AGT_MASK 0x0000000000000008 292#define SH_RTC2_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
291 293
292/* SH_RTC2_INT_CONFIG_PID */ 294/* SH_RTC2_INT_CONFIG_PID */
293/* Description: Processor ID, same setting as on targeted McKinley */ 295/* Description: Processor ID, same setting as on targeted McKinley */
294#define SH_RTC2_INT_CONFIG_PID_SHFT 4 296#define SH_RTC2_INT_CONFIG_PID_SHFT 4
295#define SH_RTC2_INT_CONFIG_PID_MASK 0x00000000000ffff0 297#define SH_RTC2_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
296 298
297/* SH_RTC2_INT_CONFIG_BASE */ 299/* SH_RTC2_INT_CONFIG_BASE */
298/* Description: Optional interrupt vector area, 2MB aligned */ 300/* Description: Optional interrupt vector area, 2MB aligned */
299#define SH_RTC2_INT_CONFIG_BASE_SHFT 21 301#define SH_RTC2_INT_CONFIG_BASE_SHFT 21
300#define SH_RTC2_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 302#define SH_RTC2_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
301 303
302/* SH_RTC2_INT_CONFIG_IDX */ 304/* SH_RTC2_INT_CONFIG_IDX */
303/* Description: Targeted McKinley interrupt vector */ 305/* Description: Targeted McKinley interrupt vector */
304#define SH_RTC2_INT_CONFIG_IDX_SHFT 52 306#define SH_RTC2_INT_CONFIG_IDX_SHFT 52
305#define SH_RTC2_INT_CONFIG_IDX_MASK 0x0ff0000000000000 307#define SH_RTC2_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
306 308
307/* ==================================================================== */ 309/* ==================================================================== */
308/* Register "SH_RTC2_INT_ENABLE" */ 310/* Register "SH_RTC2_INT_ENABLE" */
309/* SHub RTC 2 Interrupt Enable Registers */ 311/* SHub RTC 2 Interrupt Enable Registers */
310/* ==================================================================== */ 312/* ==================================================================== */
311 313
312#define SH1_RTC2_INT_ENABLE 0x0000000110001600 314#define SH1_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000110001600)
313#define SH2_RTC2_INT_ENABLE 0x0000000010001600 315#define SH2_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000010001600)
314#define SH_RTC2_INT_ENABLE_MASK 0x0000000000000001 316#define SH_RTC2_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
315#define SH_RTC2_INT_ENABLE_INIT 0x0000000000000000 317#define SH_RTC2_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
316 318
317/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */ 319/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */
318/* Description: Enable RTC 2 Interrupt */ 320/* Description: Enable RTC 2 Interrupt */
319#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0 321#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0
320#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK 0x0000000000000001 322#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
323 __IA64_UL_CONST(0x0000000000000001)
321 324
322/* ==================================================================== */ 325/* ==================================================================== */
323/* Register "SH_RTC3_INT_CONFIG" */ 326/* Register "SH_RTC3_INT_CONFIG" */
324/* SHub RTC 3 Interrupt Config Registers */ 327/* SHub RTC 3 Interrupt Config Registers */
325/* ==================================================================== */ 328/* ==================================================================== */
326 329
327#define SH1_RTC3_INT_CONFIG 0x0000000110001680 330#define SH1_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000110001680)
328#define SH2_RTC3_INT_CONFIG 0x0000000010001680 331#define SH2_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000010001680)
329#define SH_RTC3_INT_CONFIG_MASK 0x0ff3ffffffefffff 332#define SH_RTC3_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
330#define SH_RTC3_INT_CONFIG_INIT 0x0000000000000000 333#define SH_RTC3_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
331 334
332/* SH_RTC3_INT_CONFIG_TYPE */ 335/* SH_RTC3_INT_CONFIG_TYPE */
333/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 336/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
334#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0 337#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0
335#define SH_RTC3_INT_CONFIG_TYPE_MASK 0x0000000000000007 338#define SH_RTC3_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
336 339
337/* SH_RTC3_INT_CONFIG_AGT */ 340/* SH_RTC3_INT_CONFIG_AGT */
338/* Description: Agent, must be 0 for SHub */ 341/* Description: Agent, must be 0 for SHub */
339#define SH_RTC3_INT_CONFIG_AGT_SHFT 3 342#define SH_RTC3_INT_CONFIG_AGT_SHFT 3
340#define SH_RTC3_INT_CONFIG_AGT_MASK 0x0000000000000008 343#define SH_RTC3_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
341 344
342/* SH_RTC3_INT_CONFIG_PID */ 345/* SH_RTC3_INT_CONFIG_PID */
343/* Description: Processor ID, same setting as on targeted McKinley */ 346/* Description: Processor ID, same setting as on targeted McKinley */
344#define SH_RTC3_INT_CONFIG_PID_SHFT 4 347#define SH_RTC3_INT_CONFIG_PID_SHFT 4
345#define SH_RTC3_INT_CONFIG_PID_MASK 0x00000000000ffff0 348#define SH_RTC3_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
346 349
347/* SH_RTC3_INT_CONFIG_BASE */ 350/* SH_RTC3_INT_CONFIG_BASE */
348/* Description: Optional interrupt vector area, 2MB aligned */ 351/* Description: Optional interrupt vector area, 2MB aligned */
349#define SH_RTC3_INT_CONFIG_BASE_SHFT 21 352#define SH_RTC3_INT_CONFIG_BASE_SHFT 21
350#define SH_RTC3_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 353#define SH_RTC3_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
351 354
352/* SH_RTC3_INT_CONFIG_IDX */ 355/* SH_RTC3_INT_CONFIG_IDX */
353/* Description: Targeted McKinley interrupt vector */ 356/* Description: Targeted McKinley interrupt vector */
354#define SH_RTC3_INT_CONFIG_IDX_SHFT 52 357#define SH_RTC3_INT_CONFIG_IDX_SHFT 52
355#define SH_RTC3_INT_CONFIG_IDX_MASK 0x0ff0000000000000 358#define SH_RTC3_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
356 359
357/* ==================================================================== */ 360/* ==================================================================== */
358/* Register "SH_RTC3_INT_ENABLE" */ 361/* Register "SH_RTC3_INT_ENABLE" */
359/* SHub RTC 3 Interrupt Enable Registers */ 362/* SHub RTC 3 Interrupt Enable Registers */
360/* ==================================================================== */ 363/* ==================================================================== */
361 364
362#define SH1_RTC3_INT_ENABLE 0x0000000110001700 365#define SH1_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000110001700)
363#define SH2_RTC3_INT_ENABLE 0x0000000010001700 366#define SH2_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000010001700)
364#define SH_RTC3_INT_ENABLE_MASK 0x0000000000000001 367#define SH_RTC3_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
365#define SH_RTC3_INT_ENABLE_INIT 0x0000000000000000 368#define SH_RTC3_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
366 369
367/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */ 370/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */
368/* Description: Enable RTC 3 Interrupt */ 371/* Description: Enable RTC 3 Interrupt */
369#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0 372#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0
370#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK 0x0000000000000001 373#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
374 __IA64_UL_CONST(0x0000000000000001)
371 375
372/* SH_EVENT_OCCURRED_RTC1_INT */ 376/* SH_EVENT_OCCURRED_RTC1_INT */
373/* Description: Pending RTC 1 Interrupt */ 377/* Description: Pending RTC 1 Interrupt */
374#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24 378#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24
375#define SH_EVENT_OCCURRED_RTC1_INT_MASK 0x0000000001000000 379#define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000)
376 380
377/* SH_EVENT_OCCURRED_RTC2_INT */ 381/* SH_EVENT_OCCURRED_RTC2_INT */
378/* Description: Pending RTC 2 Interrupt */ 382/* Description: Pending RTC 2 Interrupt */
379#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25 383#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25
380#define SH_EVENT_OCCURRED_RTC2_INT_MASK 0x0000000002000000 384#define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000)
381 385
382/* SH_EVENT_OCCURRED_RTC3_INT */ 386/* SH_EVENT_OCCURRED_RTC3_INT */
383/* Description: Pending RTC 3 Interrupt */ 387/* Description: Pending RTC 3 Interrupt */
384#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26 388#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
385#define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 389#define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000)
386 390
387/* ==================================================================== */ 391/* ==================================================================== */
388/* Register "SH_IPI_ACCESS" */ 392/* Register "SH_IPI_ACCESS" */
389/* CPU interrupt Access Permission Bits */ 393/* CPU interrupt Access Permission Bits */
390/* ==================================================================== */ 394/* ==================================================================== */
391 395
392#define SH1_IPI_ACCESS 0x0000000110060480 396#define SH1_IPI_ACCESS __IA64_UL_CONST(0x0000000110060480)
393#define SH2_IPI_ACCESS0 0x0000000010060c00 397#define SH2_IPI_ACCESS0 __IA64_UL_CONST(0x0000000010060c00)
394#define SH2_IPI_ACCESS1 0x0000000010060c80 398#define SH2_IPI_ACCESS1 __IA64_UL_CONST(0x0000000010060c80)
395#define SH2_IPI_ACCESS2 0x0000000010060d00 399#define SH2_IPI_ACCESS2 __IA64_UL_CONST(0x0000000010060d00)
396#define SH2_IPI_ACCESS3 0x0000000010060d80 400#define SH2_IPI_ACCESS3 __IA64_UL_CONST(0x0000000010060d80)
397 401
398/* ==================================================================== */ 402/* ==================================================================== */
399/* Register "SH_INT_CMPB" */ 403/* Register "SH_INT_CMPB" */
400/* RTC Compare Value for Processor B */ 404/* RTC Compare Value for Processor B */
401/* ==================================================================== */ 405/* ==================================================================== */
402 406
403#define SH1_INT_CMPB 0x00000001101b0080 407#define SH1_INT_CMPB __IA64_UL_CONST(0x00000001101b0080)
404#define SH2_INT_CMPB 0x00000000101b0080 408#define SH2_INT_CMPB __IA64_UL_CONST(0x00000000101b0080)
405#define SH_INT_CMPB_MASK 0x007fffffffffffff 409#define SH_INT_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
406#define SH_INT_CMPB_INIT 0x0000000000000000 410#define SH_INT_CMPB_INIT __IA64_UL_CONST(0x0000000000000000)
407 411
408/* SH_INT_CMPB_REAL_TIME_CMPB */ 412/* SH_INT_CMPB_REAL_TIME_CMPB */
409/* Description: Real Time Clock Compare */ 413/* Description: Real Time Clock Compare */
410#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 414#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
411#define SH_INT_CMPB_REAL_TIME_CMPB_MASK 0x007fffffffffffff 415#define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
412 416
413/* ==================================================================== */ 417/* ==================================================================== */
414/* Register "SH_INT_CMPC" */ 418/* Register "SH_INT_CMPC" */
415/* RTC Compare Value for Processor C */ 419/* RTC Compare Value for Processor C */
416/* ==================================================================== */ 420/* ==================================================================== */
417 421
418#define SH1_INT_CMPC 0x00000001101b0100 422#define SH1_INT_CMPC __IA64_UL_CONST(0x00000001101b0100)
419#define SH2_INT_CMPC 0x00000000101b0100 423#define SH2_INT_CMPC __IA64_UL_CONST(0x00000000101b0100)
420#define SH_INT_CMPC_MASK 0x007fffffffffffff 424#define SH_INT_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
421#define SH_INT_CMPC_INIT 0x0000000000000000 425#define SH_INT_CMPC_INIT __IA64_UL_CONST(0x0000000000000000)
422 426
423/* SH_INT_CMPC_REAL_TIME_CMPC */ 427/* SH_INT_CMPC_REAL_TIME_CMPC */
424/* Description: Real Time Clock Compare */ 428/* Description: Real Time Clock Compare */
425#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 429#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
426#define SH_INT_CMPC_REAL_TIME_CMPC_MASK 0x007fffffffffffff 430#define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
427 431
428/* ==================================================================== */ 432/* ==================================================================== */
429/* Register "SH_INT_CMPD" */ 433/* Register "SH_INT_CMPD" */
430/* RTC Compare Value for Processor D */ 434/* RTC Compare Value for Processor D */
431/* ==================================================================== */ 435/* ==================================================================== */
432 436
433#define SH1_INT_CMPD 0x00000001101b0180 437#define SH1_INT_CMPD __IA64_UL_CONST(0x00000001101b0180)
434#define SH2_INT_CMPD 0x00000000101b0180 438#define SH2_INT_CMPD __IA64_UL_CONST(0x00000000101b0180)
435#define SH_INT_CMPD_MASK 0x007fffffffffffff 439#define SH_INT_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
436#define SH_INT_CMPD_INIT 0x0000000000000000 440#define SH_INT_CMPD_INIT __IA64_UL_CONST(0x0000000000000000)
437 441
438/* SH_INT_CMPD_REAL_TIME_CMPD */ 442/* SH_INT_CMPD_REAL_TIME_CMPD */
439/* Description: Real Time Clock Compare */ 443/* Description: Real Time Clock Compare */
440#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 444#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
441#define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff 445#define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
442 446
443/* ==================================================================== */ 447/* ==================================================================== */
444/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ 448/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
445/* privilege vector for acc=0 */ 449/* privilege vector for acc=0 */
446/* ==================================================================== */ 450/* ==================================================================== */
447 451#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100030300)
448#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300
449 452
450/* ==================================================================== */ 453/* ==================================================================== */
451/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ 454/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
452/* privilege vector for acc=0 */ 455/* privilege vector for acc=0 */
453/* ==================================================================== */ 456/* ==================================================================== */
454 457#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100050300)
455#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300
456 458
457/* ==================================================================== */ 459/* ==================================================================== */
458/* Some MMRs are functionally identical (or close enough) on both SHUB1 */ 460/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
@@ -484,17 +486,17 @@
484/* Engine 0 Control and Status Register */ 486/* Engine 0 Control and Status Register */
485/* ========================================================================== */ 487/* ========================================================================== */
486 488
487#define SH2_BT_ENG_CSR_0 0x0000000030040000 489#define SH2_BT_ENG_CSR_0 __IA64_UL_CONST(0x0000000030040000)
488#define SH2_BT_ENG_SRC_ADDR_0 0x0000000030040080 490#define SH2_BT_ENG_SRC_ADDR_0 __IA64_UL_CONST(0x0000000030040080)
489#define SH2_BT_ENG_DEST_ADDR_0 0x0000000030040100 491#define SH2_BT_ENG_DEST_ADDR_0 __IA64_UL_CONST(0x0000000030040100)
490#define SH2_BT_ENG_NOTIF_ADDR_0 0x0000000030040180 492#define SH2_BT_ENG_NOTIF_ADDR_0 __IA64_UL_CONST(0x0000000030040180)
491 493
492/* ========================================================================== */ 494/* ========================================================================== */
493/* BTE interfaces 1-3 */ 495/* BTE interfaces 1-3 */
494/* ========================================================================== */ 496/* ========================================================================== */
495 497
496#define SH2_BT_ENG_CSR_1 0x0000000030050000 498#define SH2_BT_ENG_CSR_1 __IA64_UL_CONST(0x0000000030050000)
497#define SH2_BT_ENG_CSR_2 0x0000000030060000 499#define SH2_BT_ENG_CSR_2 __IA64_UL_CONST(0x0000000030060000)
498#define SH2_BT_ENG_CSR_3 0x0000000030070000 500#define SH2_BT_ENG_CSR_3 __IA64_UL_CONST(0x0000000030070000)
499 501
500#endif /* _ASM_IA64_SN_SHUB_MMR_H */ 502#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h
index 78eb4f869c8b..cf770e246af5 100644
--- a/include/asm-ia64/sn/simulator.h
+++ b/include/asm-ia64/sn/simulator.h
@@ -10,16 +10,17 @@
10 10
11#include <linux/config.h> 11#include <linux/config.h>
12 12
13#ifdef CONFIG_IA64_SGI_SN_SIM
14
15#define SNMAGIC 0xaeeeeeee8badbeefL 13#define SNMAGIC 0xaeeeeeee8badbeefL
16#define IS_RUNNING_ON_SIMULATOR() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;}) 14#define IS_MEDUSA() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
17
18#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
19 15
16#ifdef CONFIG_IA64_SGI_SN_SIM
17#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
18#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type)
19#define IS_RUNNING_ON_FAKE_PROM() (sn_prom_type == 2)
20extern int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
20#else 21#else
21
22#define IS_RUNNING_ON_SIMULATOR() (0) 22#define IS_RUNNING_ON_SIMULATOR() (0)
23#define IS_RUNNING_ON_FAKE_PROM() (0)
23#define SIMULATOR_SLEEP() 24#define SIMULATOR_SLEEP()
24 25
25#endif 26#endif
diff --git a/include/asm-ia64/sn/sn2/sn_hwperf.h b/include/asm-ia64/sn/sn2/sn_hwperf.h
index b0c4d6dd77ba..df75f4c4aec3 100644
--- a/include/asm-ia64/sn/sn2/sn_hwperf.h
+++ b/include/asm-ia64/sn/sn2/sn_hwperf.h
@@ -223,4 +223,6 @@ struct sn_hwperf_ioctl_args {
223#define SN_HWPERF_OP_RECONFIGURE 253 223#define SN_HWPERF_OP_RECONFIGURE 253
224#define SN_HWPERF_OP_INVAL 254 224#define SN_HWPERF_OP_INVAL 254
225 225
226int sn_topology_open(struct inode *inode, struct file *file);
227int sn_topology_release(struct inode *inode, struct file *file);
226#endif /* SN_HWPERF_H */ 228#endif /* SN_HWPERF_H */
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index eb0395ad0d6a..1455375d2ce4 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -132,6 +132,8 @@
132#define SALRET_INVALID_ARG (-2) 132#define SALRET_INVALID_ARG (-2)
133#define SALRET_ERROR (-3) 133#define SALRET_ERROR (-3)
134 134
135#define SN_SAL_FAKE_PROM 0x02009999
136
135 137
136/** 138/**
137 * sn_sal_rev_major - get the major SGI SAL revision number 139 * sn_sal_rev_major - get the major SGI SAL revision number
@@ -1105,4 +1107,12 @@ ia64_sn_bte_recovery(nasid_t nasid)
1105 return (int) rv.status; 1107 return (int) rv.status;
1106} 1108}
1107 1109
1110static inline int
1111ia64_sn_is_fake_prom(void)
1112{
1113 struct ia64_sal_retval rv;
1114 SAL_CALL_NOLOCK(rv, SN_SAL_FAKE_PROM, 0, 0, 0, 0, 0, 0, 0);
1115 return (rv.status == 0);
1116}
1117
1108#endif /* _ASM_IA64_SN_SN_SAL_H */ 1118#endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
index b6acc22ab239..5ccec608d325 100644
--- a/include/asm-ia64/sn/tioca_provider.h
+++ b/include/asm-ia64/sn/tioca_provider.h
@@ -201,6 +201,7 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
201} 201}
202 202
203extern uint32_t tioca_gart_found; 203extern uint32_t tioca_gart_found;
204extern struct list_head tioca_list;
204extern int tioca_init_provider(void); 205extern int tioca_init_provider(void);
205extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern); 206extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
206#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */ 207#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/include/asm-ia64/vga.h b/include/asm-ia64/vga.h
index 1f446d6841f6..bc3349ffc505 100644
--- a/include/asm-ia64/vga.h
+++ b/include/asm-ia64/vga.h
@@ -14,7 +14,10 @@
14 * videoram directly without any black magic. 14 * videoram directly without any black magic.
15 */ 15 */
16 16
17#define VGA_MAP_MEM(x) ((unsigned long) ioremap((x), 0)) 17extern unsigned long vga_console_iobase;
18extern unsigned long vga_console_membase;
19
20#define VGA_MAP_MEM(x) ((unsigned long) ioremap(vga_console_membase + (x), 0))
18 21
19#define vga_readb(x) (*(x)) 22#define vga_readb(x) (*(x))
20#define vga_writeb(x,y) (*(y) = (x)) 23#define vga_writeb(x,y) (*(y) = (x))
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 09:31:43 -0500