3 files changed, 30 insertions, 6 deletions

diff --git a/arch/mips/lib/iomap.c b/arch/mips/lib/iomap.c
index 7e2ced715cfb..f4ac5bbcd81f 100644
--- a/arch/mips/lib/iomap.c
+++ b/arch/mips/lib/iomap.c
@@ -63,7 +63,7 @@ void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
                 return ioport_map(start, len);
         if (flags & IORESOURCE_MEM) {
                 if (flags & IORESOURCE_CACHEABLE)
-                        return ioremap_cacheable_cow(start, len);
+                        return ioremap_cachable(start, len);
                 return ioremap_nocache(start, len);
         }
 
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 1b71d91e8268..0668e9bfce41 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -235,7 +235,9 @@ static inline void r4k_blast_scache_page_setup(void)
 {
         unsigned long sc_lsize = cpu_scache_line_size();
 
-        if (sc_lsize == 16)
+        if (scache_size == 0)
+                r4k_blast_scache_page = (void *)no_sc_noop;
+        else if (sc_lsize == 16)
                 r4k_blast_scache_page = blast_scache16_page;
         else if (sc_lsize == 32)
                 r4k_blast_scache_page = blast_scache32_page;
@@ -251,7 +253,9 @@ static inline void r4k_blast_scache_page_indexed_setup(void)
 {
         unsigned long sc_lsize = cpu_scache_line_size();
 
-        if (sc_lsize == 16)
+        if (scache_size == 0)
+                r4k_blast_scache_page_indexed = (void *)no_sc_noop;
+        else if (sc_lsize == 16)
                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
         else if (sc_lsize == 32)
                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
@@ -267,7 +271,9 @@ static inline void r4k_blast_scache_setup(void)
 {
         unsigned long sc_lsize = cpu_scache_line_size();
 
-        if (sc_lsize == 16)
+        if (scache_size == 0)
+                r4k_blast_scache = (void *)no_sc_noop;
+        else if (sc_lsize == 16)
                 r4k_blast_scache = blast_scache16;
         else if (sc_lsize == 32)
                 r4k_blast_scache = blast_scache32;
@@ -482,7 +488,7 @@ static inline void local_r4k_flush_icache_range(void *args)
                         protected_blast_dcache_range(start, end);
                 }
 
-                if (!cpu_icache_snoops_remote_store) {
+                if (!cpu_icache_snoops_remote_store && scache_size) {
                         if (end - start > scache_size)
                                 r4k_blast_scache();
                         else
@@ -651,7 +657,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
 
         R4600_HIT_CACHEOP_WAR_IMPL;
         protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
-        if (!cpu_icache_snoops_remote_store)
+        if (!cpu_icache_snoops_remote_store && scache_size)
                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
         protected_flush_icache_line(addr & ~(ic_lsize - 1));
         if (MIPS4K_ICACHE_REFILL_WAR) {
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 5a4c8a54b8f4..8c011aa61afa 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -283,6 +283,24 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 
 /*
+ * ioremap_cachable -   map bus memory into CPU space
+ * @offset:         bus address of the memory
+ * @size:           size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked cachable by
+ * the CPU.  Also enables full write-combining.  Useful for some
+ * memory-like regions on I/O busses.
+ */
+#define ioremap_cachable(offset, size)                                  \
+        __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
+
+/*
  * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
  * requests a cachable mapping, ioremap_uncached_accelerated requests a
  * mapping using the uncached accelerated mode which isn't supported on