2 files changed, 21 insertions, 0 deletions

diff --git a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c
index eb5279d23b7f..3fff3c62d57a 100644
--- a/arch/i386/kernel/apic.c
+++ b/arch/i386/kernel/apic.c
@@ -415,6 +415,7 @@ void __init init_bsp_APIC(void)
 void __devinit setup_local_APIC(void)
 {
         unsigned long oldvalue, value, ver, maxlvt;
+        int i, j;
 
         /* Pound the ESR really hard over the head with a big hammer - mbligh */
         if (esr_disable) {
@@ -452,6 +453,25 @@ void __devinit setup_local_APIC(void)
         apic_write_around(APIC_TASKPRI, value);
 
         /*
+         * After a crash, we no longer service the interrupts and a pending
+         * interrupt from previous kernel might still have ISR bit set.
+         *
+         * Most probably by now CPU has serviced that pending interrupt and
+         * it might not have done the ack_APIC_irq() because it thought,
+         * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
+         * does not clear the ISR bit and cpu thinks it has already serivced
+         * the interrupt. Hence a vector might get locked. It was noticed
+         * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
+         */
+        for (i = APIC_ISR_NR - 1; i >= 0; i--) {
+                value = apic_read(APIC_ISR + i*0x10);
+                for (j = 31; j >= 0; j--) {
+                        if (value & (1<<j))
+                                ack_APIC_irq();
+                }
+        }
+
+        /*
          * Now that we are all set up, enable the APIC
          */
         value = apic_read(APIC_SPIV);
diff --git a/include/asm-i386/apicdef.h b/include/asm-i386/apicdef.h
index 03185cef8e0a..5e4a35af2921 100644
--- a/include/asm-i386/apicdef.h
+++ b/include/asm-i386/apicdef.h
@@ -37,6 +37,7 @@
 #define                 APIC_SPIV_FOCUS_DISABLED        (1<<9)
 #define                 APIC_SPIV_APIC_ENABLED          (1<<8)
 #define         APIC_ISR        0x100
+#define         APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
 #define         APIC_TMR        0x180
 #define         APIC_IRR        0x200
 #define         APIC_ESR        0x280