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-rw-r--r--arch/arm/configs/omap_h2_1610_defconfig201
-rw-r--r--arch/arm/configs/omap_osk_5912_defconfig110
-rw-r--r--arch/arm/configs/orion_defconfig93
-rw-r--r--arch/arm/kernel/setup.c2
-rw-r--r--arch/arm/mach-at91/clock.c2
-rw-r--r--arch/arm/mach-davinci/clock.c4
-rw-r--r--arch/arm/mach-omap1/Makefile6
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c7
-rw-r--r--arch/arm/mach-omap1/board-fsample.c6
-rw-r--r--arch/arm/mach-omap1/board-generic.c24
-rw-r--r--arch/arm/mach-omap1/board-h2-mmc.c110
-rw-r--r--arch/arm/mach-omap1/board-h2.c103
-rw-r--r--arch/arm/mach-omap1/board-h3-mmc.c114
-rw-r--r--arch/arm/mach-omap1/board-h3.c75
-rw-r--r--arch/arm/mach-omap1/board-innovator.c19
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c3
-rw-r--r--arch/arm/mach-omap1/board-osk.c25
-rw-r--r--arch/arm/mach-omap1/board-palmte.c84
-rw-r--r--arch/arm/mach-omap1/board-palmtt.c15
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c3
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c8
-rw-r--r--arch/arm/mach-omap1/board-sx1-mmc.c124
-rw-r--r--arch/arm/mach-omap1/board-sx1.c64
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c4
-rw-r--r--arch/arm/mach-omap1/clock.c7
-rw-r--r--arch/arm/mach-omap1/leds-osk.c4
-rw-r--r--arch/arm/mach-omap1/mailbox.c14
-rw-r--r--arch/arm/mach-omap1/pm.c27
-rw-r--r--arch/arm/mach-omap1/sleep.S161
-rw-r--r--arch/arm/mach-orion/addr-map.c14
-rw-r--r--arch/arm/mach-orion/common.c84
-rw-r--r--arch/arm/mach-orion/common.h8
-rw-r--r--arch/arm/mach-orion/db88f5281-setup.c4
-rw-r--r--arch/arm/mach-orion/dns323-setup.c8
-rw-r--r--arch/arm/mach-orion/kurobox_pro-setup.c17
-rw-r--r--arch/arm/mach-orion/pci.c10
-rw-r--r--arch/arm/mach-orion/rd88f5182-setup.c17
-rw-r--r--arch/arm/mach-orion/ts209-setup.c20
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c10
-rw-r--r--arch/arm/plat-omap/Makefile1
-rw-r--r--arch/arm/plat-omap/dma.c844
-rw-r--r--arch/arm/plat-omap/dmtimer.c118
-rw-r--r--arch/arm/plat-omap/gpio.c256
-rw-r--r--arch/arm/plat-omap/i2c.c148
-rw-r--r--arch/arm/plat-omap/mcbsp.c11
-rw-r--r--include/asm-arm/arch-omap/board-apollon.h2
-rw-r--r--include/asm-arm/arch-omap/board-h2.h3
-rw-r--r--include/asm-arm/arch-omap/board-h3.h2
-rw-r--r--include/asm-arm/arch-omap/board-sx1.h8
-rw-r--r--include/asm-arm/arch-omap/common.h11
-rw-r--r--include/asm-arm/arch-omap/cpu.h127
-rw-r--r--include/asm-arm/arch-omap/dma.h135
-rw-r--r--include/asm-arm/arch-omap/gpio.h4
-rw-r--r--include/asm-arm/arch-omap/irqs.h2
-rw-r--r--include/asm-arm/arch-omap/nand.h24
-rw-r--r--include/asm-arm/arch-orion/debug-macro.S9
-rw-r--r--include/asm-arm/arch-orion/entry-macro.S4
-rw-r--r--include/asm-arm/arch-orion/hardware.h13
-rw-r--r--include/asm-arm/arch-orion/orion.h102
-rw-r--r--include/asm-arm/arch-orion/uncompress.h14
-rw-r--r--include/asm-arm/arch-orion/vmalloc.h2
61 files changed, 2494 insertions, 957 deletions
diff --git a/arch/arm/configs/omap_h2_1610_defconfig b/arch/arm/configs/omap_h2_1610_defconfig
index b8a78ab49cdd..c2345af3707a 100644
--- a/arch/arm/configs/omap_h2_1610_defconfig
+++ b/arch/arm/configs/omap_h2_1610_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6 3# Linux kernel version: 2.6.24-rc5
4# Mon Sep 17 14:21:45 2007 4# Mon Dec 17 20:04:38 2007
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -41,9 +41,14 @@ CONFIG_SYSVIPC_SYSCTL=y
41# CONFIG_BSD_PROCESS_ACCT is not set 41# CONFIG_BSD_PROCESS_ACCT is not set
42# CONFIG_TASKSTATS is not set 42# CONFIG_TASKSTATS is not set
43# CONFIG_USER_NS is not set 43# CONFIG_USER_NS is not set
44# CONFIG_PID_NS is not set
44# CONFIG_AUDIT is not set 45# CONFIG_AUDIT is not set
45# CONFIG_IKCONFIG is not set 46# CONFIG_IKCONFIG is not set
46CONFIG_LOG_BUF_SHIFT=14 47CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set
49CONFIG_FAIR_GROUP_SCHED=y
50CONFIG_FAIR_USER_SCHED=y
51# CONFIG_FAIR_CGROUP_SCHED is not set
47# CONFIG_SYSFS_DEPRECATED is not set 52# CONFIG_SYSFS_DEPRECATED is not set
48# CONFIG_RELAY is not set 53# CONFIG_RELAY is not set
49CONFIG_BLK_DEV_INITRD=y 54CONFIG_BLK_DEV_INITRD=y
@@ -64,7 +69,6 @@ CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y 69CONFIG_ANON_INODES=y
65CONFIG_EPOLL=y 70CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y 71CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y 72CONFIG_EVENTFD=y
69CONFIG_SHMEM=y 73CONFIG_SHMEM=y
70CONFIG_VM_EVENT_COUNTERS=y 74CONFIG_VM_EVENT_COUNTERS=y
@@ -224,10 +228,6 @@ CONFIG_ARM_THUMB=y
224# 228#
225# CONFIG_PCI_SYSCALL is not set 229# CONFIG_PCI_SYSCALL is not set
226# CONFIG_ARCH_SUPPORTS_MSI is not set 230# CONFIG_ARCH_SUPPORTS_MSI is not set
227
228#
229# PCCARD (PCMCIA/CardBus) support
230#
231# CONFIG_PCCARD is not set 231# CONFIG_PCCARD is not set
232 232
233# 233#
@@ -236,6 +236,7 @@ CONFIG_ARM_THUMB=y
236CONFIG_TICK_ONESHOT=y 236CONFIG_TICK_ONESHOT=y
237CONFIG_NO_HZ=y 237CONFIG_NO_HZ=y
238CONFIG_HIGH_RES_TIMERS=y 238CONFIG_HIGH_RES_TIMERS=y
239CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
239CONFIG_PREEMPT=y 240CONFIG_PREEMPT=y
240CONFIG_HZ=128 241CONFIG_HZ=128
241CONFIG_AEABI=y 242CONFIG_AEABI=y
@@ -248,6 +249,7 @@ CONFIG_FLATMEM_MANUAL=y
248CONFIG_FLATMEM=y 249CONFIG_FLATMEM=y
249CONFIG_FLAT_NODE_MEM_MAP=y 250CONFIG_FLAT_NODE_MEM_MAP=y
250# CONFIG_SPARSEMEM_STATIC is not set 251# CONFIG_SPARSEMEM_STATIC is not set
252# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
251CONFIG_SPLIT_PTLOCK_CPUS=4096 253CONFIG_SPLIT_PTLOCK_CPUS=4096
252# CONFIG_RESOURCES_64BIT is not set 254# CONFIG_RESOURCES_64BIT is not set
253CONFIG_ZONE_DMA_FLAG=1 255CONFIG_ZONE_DMA_FLAG=1
@@ -275,6 +277,8 @@ CONFIG_CPU_FREQ_STAT=y
275# CONFIG_CPU_FREQ_STAT_DETAILS is not set 277# CONFIG_CPU_FREQ_STAT_DETAILS is not set
276# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set 278# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
277CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y 279CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
280# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
281# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
278# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set 282# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
279# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set 283# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
280CONFIG_CPU_FREQ_GOV_USERSPACE=y 284CONFIG_CPU_FREQ_GOV_USERSPACE=y
@@ -347,6 +351,7 @@ CONFIG_IP_PNP_BOOTP=y
347CONFIG_INET_XFRM_MODE_TRANSPORT=y 351CONFIG_INET_XFRM_MODE_TRANSPORT=y
348CONFIG_INET_XFRM_MODE_TUNNEL=y 352CONFIG_INET_XFRM_MODE_TUNNEL=y
349CONFIG_INET_XFRM_MODE_BEET=y 353CONFIG_INET_XFRM_MODE_BEET=y
354# CONFIG_INET_LRO is not set
350CONFIG_INET_DIAG=y 355CONFIG_INET_DIAG=y
351CONFIG_INET_TCP_DIAG=y 356CONFIG_INET_TCP_DIAG=y
352# CONFIG_TCP_CONG_ADVANCED is not set 357# CONFIG_TCP_CONG_ADVANCED is not set
@@ -372,10 +377,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
372# CONFIG_LAPB is not set 377# CONFIG_LAPB is not set
373# CONFIG_ECONET is not set 378# CONFIG_ECONET is not set
374# CONFIG_WAN_ROUTER is not set 379# CONFIG_WAN_ROUTER is not set
375
376#
377# QoS and/or fair queueing
378#
379# CONFIG_NET_SCHED is not set 380# CONFIG_NET_SCHED is not set
380 381
381# 382#
@@ -404,6 +405,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
404# 405#
405# Generic Driver Options 406# Generic Driver Options
406# 407#
408CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
407CONFIG_STANDALONE=y 409CONFIG_STANDALONE=y
408CONFIG_PREVENT_FIRMWARE_BUILD=y 410CONFIG_PREVENT_FIRMWARE_BUILD=y
409# CONFIG_FW_LOADER is not set 411# CONFIG_FW_LOADER is not set
@@ -422,6 +424,8 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
422CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 424CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
423# CONFIG_CDROM_PKTCDVD is not set 425# CONFIG_CDROM_PKTCDVD is not set
424CONFIG_ATA_OVER_ETH=m 426CONFIG_ATA_OVER_ETH=m
427CONFIG_MISC_DEVICES=y
428# CONFIG_EEPROM_93CX6 is not set
425 429
426# 430#
427# SCSI device support 431# SCSI device support
@@ -459,6 +463,7 @@ CONFIG_SCSI_WAIT_SCAN=m
459# CONFIG_SCSI_FC_ATTRS is not set 463# CONFIG_SCSI_FC_ATTRS is not set
460# CONFIG_SCSI_ISCSI_ATTRS is not set 464# CONFIG_SCSI_ISCSI_ATTRS is not set
461# CONFIG_SCSI_SAS_LIBSAS is not set 465# CONFIG_SCSI_SAS_LIBSAS is not set
466# CONFIG_SCSI_SRP_ATTRS is not set
462CONFIG_SCSI_LOWLEVEL=y 467CONFIG_SCSI_LOWLEVEL=y
463# CONFIG_ISCSI_TCP is not set 468# CONFIG_ISCSI_TCP is not set
464# CONFIG_SCSI_DEBUG is not set 469# CONFIG_SCSI_DEBUG is not set
@@ -471,12 +476,18 @@ CONFIG_NETDEVICES=y
471# CONFIG_MACVLAN is not set 476# CONFIG_MACVLAN is not set
472# CONFIG_EQUALIZER is not set 477# CONFIG_EQUALIZER is not set
473# CONFIG_TUN is not set 478# CONFIG_TUN is not set
479# CONFIG_VETH is not set
474# CONFIG_PHYLIB is not set 480# CONFIG_PHYLIB is not set
475CONFIG_NET_ETHERNET=y 481CONFIG_NET_ETHERNET=y
476CONFIG_MII=y 482CONFIG_MII=y
477# CONFIG_AX88796 is not set 483# CONFIG_AX88796 is not set
478CONFIG_SMC91X=y 484CONFIG_SMC91X=y
479# CONFIG_DM9000 is not set 485# CONFIG_DM9000 is not set
486# CONFIG_IBM_NEW_EMAC_ZMII is not set
487# CONFIG_IBM_NEW_EMAC_RGMII is not set
488# CONFIG_IBM_NEW_EMAC_TAH is not set
489# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
490# CONFIG_B44 is not set
480CONFIG_NETDEV_1000=y 491CONFIG_NETDEV_1000=y
481CONFIG_NETDEV_10000=y 492CONFIG_NETDEV_10000=y
482 493
@@ -522,7 +533,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
522CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 533CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
523CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 534CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
524# CONFIG_INPUT_JOYDEV is not set 535# CONFIG_INPUT_JOYDEV is not set
525# CONFIG_INPUT_TSDEV is not set
526CONFIG_INPUT_EVDEV=y 536CONFIG_INPUT_EVDEV=y
527CONFIG_INPUT_EVBUG=y 537CONFIG_INPUT_EVBUG=y
528 538
@@ -576,20 +586,51 @@ CONFIG_SERIAL_CORE_CONSOLE=y
576CONFIG_UNIX98_PTYS=y 586CONFIG_UNIX98_PTYS=y
577# CONFIG_LEGACY_PTYS is not set 587# CONFIG_LEGACY_PTYS is not set
578# CONFIG_IPMI_HANDLER is not set 588# CONFIG_IPMI_HANDLER is not set
579CONFIG_WATCHDOG=y
580CONFIG_WATCHDOG_NOWAYOUT=y
581
582#
583# Watchdog Device Drivers
584#
585# CONFIG_SOFT_WATCHDOG is not set
586# CONFIG_OMAP_WATCHDOG is not set
587# CONFIG_HW_RANDOM is not set 589# CONFIG_HW_RANDOM is not set
588# CONFIG_NVRAM is not set 590# CONFIG_NVRAM is not set
589# CONFIG_R3964 is not set 591# CONFIG_R3964 is not set
590# CONFIG_RAW_DRIVER is not set 592# CONFIG_RAW_DRIVER is not set
591# CONFIG_TCG_TPM is not set 593# CONFIG_TCG_TPM is not set
592# CONFIG_I2C is not set 594CONFIG_I2C=y
595CONFIG_I2C_BOARDINFO=y
596# CONFIG_I2C_CHARDEV is not set
597
598#
599# I2C Algorithms
600#
601# CONFIG_I2C_ALGOBIT is not set
602# CONFIG_I2C_ALGOPCF is not set
603# CONFIG_I2C_ALGOPCA is not set
604
605#
606# I2C Hardware Bus support
607#
608# CONFIG_I2C_GPIO is not set
609# CONFIG_I2C_OCORES is not set
610CONFIG_I2C_OMAP=y
611# CONFIG_I2C_PARPORT_LIGHT is not set
612# CONFIG_I2C_SIMTEC is not set
613# CONFIG_I2C_TAOS_EVM is not set
614# CONFIG_I2C_STUB is not set
615
616#
617# Miscellaneous I2C Chip support
618#
619# CONFIG_SENSORS_DS1337 is not set
620# CONFIG_SENSORS_DS1374 is not set
621# CONFIG_DS1682 is not set
622# CONFIG_SENSORS_EEPROM is not set
623# CONFIG_SENSORS_PCF8574 is not set
624# CONFIG_SENSORS_PCA9539 is not set
625# CONFIG_SENSORS_PCF8591 is not set
626# CONFIG_ISP1301_OMAP is not set
627CONFIG_TPS65010=y
628# CONFIG_SENSORS_MAX6875 is not set
629# CONFIG_SENSORS_TSL2550 is not set
630# CONFIG_I2C_DEBUG_CORE is not set
631# CONFIG_I2C_DEBUG_ALGO is not set
632# CONFIG_I2C_DEBUG_BUS is not set
633# CONFIG_I2C_DEBUG_CHIP is not set
593 634
594# 635#
595# SPI support 636# SPI support
@@ -597,28 +638,73 @@ CONFIG_WATCHDOG_NOWAYOUT=y
597# CONFIG_SPI is not set 638# CONFIG_SPI is not set
598# CONFIG_SPI_MASTER is not set 639# CONFIG_SPI_MASTER is not set
599# CONFIG_W1 is not set 640# CONFIG_W1 is not set
641# CONFIG_POWER_SUPPLY is not set
600CONFIG_HWMON=y 642CONFIG_HWMON=y
601# CONFIG_HWMON_VID is not set 643# CONFIG_HWMON_VID is not set
602# CONFIG_SENSORS_ABITUGURU is not set 644# CONFIG_SENSORS_AD7418 is not set
603# CONFIG_SENSORS_ABITUGURU3 is not set 645# CONFIG_SENSORS_ADM1021 is not set
646# CONFIG_SENSORS_ADM1025 is not set
647# CONFIG_SENSORS_ADM1026 is not set
648# CONFIG_SENSORS_ADM1029 is not set
649# CONFIG_SENSORS_ADM1031 is not set
650# CONFIG_SENSORS_ADM9240 is not set
651# CONFIG_SENSORS_ADT7470 is not set
652# CONFIG_SENSORS_ATXP1 is not set
653# CONFIG_SENSORS_DS1621 is not set
604# CONFIG_SENSORS_F71805F is not set 654# CONFIG_SENSORS_F71805F is not set
655# CONFIG_SENSORS_F71882FG is not set
656# CONFIG_SENSORS_F75375S is not set
657# CONFIG_SENSORS_GL518SM is not set
658# CONFIG_SENSORS_GL520SM is not set
605# CONFIG_SENSORS_IT87 is not set 659# CONFIG_SENSORS_IT87 is not set
660# CONFIG_SENSORS_LM63 is not set
661# CONFIG_SENSORS_LM75 is not set
662# CONFIG_SENSORS_LM77 is not set
663# CONFIG_SENSORS_LM78 is not set
664# CONFIG_SENSORS_LM80 is not set
665# CONFIG_SENSORS_LM83 is not set
666# CONFIG_SENSORS_LM85 is not set
667# CONFIG_SENSORS_LM87 is not set
668# CONFIG_SENSORS_LM90 is not set
669# CONFIG_SENSORS_LM92 is not set
670# CONFIG_SENSORS_LM93 is not set
671# CONFIG_SENSORS_MAX1619 is not set
672# CONFIG_SENSORS_MAX6650 is not set
606# CONFIG_SENSORS_PC87360 is not set 673# CONFIG_SENSORS_PC87360 is not set
607# CONFIG_SENSORS_PC87427 is not set 674# CONFIG_SENSORS_PC87427 is not set
675# CONFIG_SENSORS_DME1737 is not set
608# CONFIG_SENSORS_SMSC47M1 is not set 676# CONFIG_SENSORS_SMSC47M1 is not set
677# CONFIG_SENSORS_SMSC47M192 is not set
609# CONFIG_SENSORS_SMSC47B397 is not set 678# CONFIG_SENSORS_SMSC47B397 is not set
679# CONFIG_SENSORS_THMC50 is not set
610# CONFIG_SENSORS_VT1211 is not set 680# CONFIG_SENSORS_VT1211 is not set
681# CONFIG_SENSORS_W83781D is not set
682# CONFIG_SENSORS_W83791D is not set
683# CONFIG_SENSORS_W83792D is not set
684# CONFIG_SENSORS_W83793 is not set
685# CONFIG_SENSORS_W83L785TS is not set
611# CONFIG_SENSORS_W83627HF is not set 686# CONFIG_SENSORS_W83627HF is not set
612# CONFIG_SENSORS_W83627EHF is not set 687# CONFIG_SENSORS_W83627EHF is not set
613# CONFIG_HWMON_DEBUG_CHIP is not set 688# CONFIG_HWMON_DEBUG_CHIP is not set
614CONFIG_MISC_DEVICES=y 689CONFIG_WATCHDOG=y
615# CONFIG_EEPROM_93CX6 is not set 690CONFIG_WATCHDOG_NOWAYOUT=y
691
692#
693# Watchdog Device Drivers
694#
695# CONFIG_SOFT_WATCHDOG is not set
696# CONFIG_OMAP_WATCHDOG is not set
697
698#
699# Sonics Silicon Backplane
700#
701CONFIG_SSB_POSSIBLE=y
702# CONFIG_SSB is not set
616 703
617# 704#
618# Multifunction device drivers 705# Multifunction device drivers
619# 706#
620# CONFIG_MFD_SM501 is not set 707# CONFIG_MFD_SM501 is not set
621# CONFIG_NEW_LEDS is not set
622 708
623# 709#
624# Multimedia devices 710# Multimedia devices
@@ -630,12 +716,6 @@ CONFIG_DAB=y
630# 716#
631# Graphics support 717# Graphics support
632# 718#
633# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
634
635#
636# Display device support
637#
638# CONFIG_DISPLAY_SUPPORT is not set
639# CONFIG_VGASTATE is not set 719# CONFIG_VGASTATE is not set
640CONFIG_VIDEO_OUTPUT_CONTROL=m 720CONFIG_VIDEO_OUTPUT_CONTROL=m
641CONFIG_FB=y 721CONFIG_FB=y
@@ -644,6 +724,7 @@ CONFIG_FIRMWARE_EDID=y
644# CONFIG_FB_CFB_FILLRECT is not set 724# CONFIG_FB_CFB_FILLRECT is not set
645# CONFIG_FB_CFB_COPYAREA is not set 725# CONFIG_FB_CFB_COPYAREA is not set
646# CONFIG_FB_CFB_IMAGEBLIT is not set 726# CONFIG_FB_CFB_IMAGEBLIT is not set
727# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
647# CONFIG_FB_SYS_FILLRECT is not set 728# CONFIG_FB_SYS_FILLRECT is not set
648# CONFIG_FB_SYS_COPYAREA is not set 729# CONFIG_FB_SYS_COPYAREA is not set
649# CONFIG_FB_SYS_IMAGEBLIT is not set 730# CONFIG_FB_SYS_IMAGEBLIT is not set
@@ -659,8 +740,14 @@ CONFIG_FB_MODE_HELPERS=y
659# Frame buffer hardware drivers 740# Frame buffer hardware drivers
660# 741#
661# CONFIG_FB_S1D13XXX is not set 742# CONFIG_FB_S1D13XXX is not set
662# CONFIG_FB_OMAP is not set
663# CONFIG_FB_VIRTUAL is not set 743# CONFIG_FB_VIRTUAL is not set
744# CONFIG_FB_OMAP is not set
745# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
746
747#
748# Display device support
749#
750# CONFIG_DISPLAY_SUPPORT is not set
664 751
665# 752#
666# Console display driver support 753# Console display driver support
@@ -705,6 +792,7 @@ CONFIG_SOUND_PRIME=y
705CONFIG_HID_SUPPORT=y 792CONFIG_HID_SUPPORT=y
706CONFIG_HID=y 793CONFIG_HID=y
707CONFIG_HID_DEBUG=y 794CONFIG_HID_DEBUG=y
795# CONFIG_HIDRAW is not set
708CONFIG_USB_SUPPORT=y 796CONFIG_USB_SUPPORT=y
709CONFIG_USB_ARCH_HAS_HCD=y 797CONFIG_USB_ARCH_HAS_HCD=y
710CONFIG_USB_ARCH_HAS_OHCI=y 798CONFIG_USB_ARCH_HAS_OHCI=y
@@ -720,23 +808,11 @@ CONFIG_USB_ARCH_HAS_OHCI=y
720# 808#
721# CONFIG_USB_GADGET is not set 809# CONFIG_USB_GADGET is not set
722# CONFIG_MMC is not set 810# CONFIG_MMC is not set
811# CONFIG_NEW_LEDS is not set
723CONFIG_RTC_LIB=y 812CONFIG_RTC_LIB=y
724# CONFIG_RTC_CLASS is not set 813# CONFIG_RTC_CLASS is not set
725 814
726# 815#
727# DMA Engine support
728#
729# CONFIG_DMA_ENGINE is not set
730
731#
732# DMA Clients
733#
734
735#
736# DMA Devices
737#
738
739#
740# File systems 816# File systems
741# 817#
742CONFIG_EXT2_FS=y 818CONFIG_EXT2_FS=y
@@ -771,8 +847,9 @@ CONFIG_DNOTIFY=y
771# 847#
772CONFIG_FAT_FS=y 848CONFIG_FAT_FS=y
773CONFIG_MSDOS_FS=y 849CONFIG_MSDOS_FS=y
774# CONFIG_VFAT_FS is not set 850CONFIG_VFAT_FS=y
775CONFIG_FAT_DEFAULT_CODEPAGE=437 851CONFIG_FAT_DEFAULT_CODEPAGE=437
852CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
776# CONFIG_NTFS_FS is not set 853# CONFIG_NTFS_FS is not set
777 854
778# 855#
@@ -783,7 +860,6 @@ CONFIG_PROC_SYSCTL=y
783CONFIG_SYSFS=y 860CONFIG_SYSFS=y
784# CONFIG_TMPFS is not set 861# CONFIG_TMPFS is not set
785# CONFIG_HUGETLB_PAGE is not set 862# CONFIG_HUGETLB_PAGE is not set
786CONFIG_RAMFS=y
787# CONFIG_CONFIGFS_FS is not set 863# CONFIG_CONFIGFS_FS is not set
788 864
789# 865#
@@ -802,10 +878,7 @@ CONFIG_CRAMFS=y
802# CONFIG_QNX4FS_FS is not set 878# CONFIG_QNX4FS_FS is not set
803# CONFIG_SYSV_FS is not set 879# CONFIG_SYSV_FS is not set
804# CONFIG_UFS_FS is not set 880# CONFIG_UFS_FS is not set
805 881CONFIG_NETWORK_FILESYSTEMS=y
806#
807# Network File Systems
808#
809CONFIG_NFS_FS=y 882CONFIG_NFS_FS=y
810CONFIG_NFS_V3=y 883CONFIG_NFS_V3=y
811# CONFIG_NFS_V3_ACL is not set 884# CONFIG_NFS_V3_ACL is not set
@@ -832,13 +905,9 @@ CONFIG_RPCSEC_GSS_KRB5=y
832# 905#
833# CONFIG_PARTITION_ADVANCED is not set 906# CONFIG_PARTITION_ADVANCED is not set
834CONFIG_MSDOS_PARTITION=y 907CONFIG_MSDOS_PARTITION=y
835
836#
837# Native Language Support
838#
839CONFIG_NLS=y 908CONFIG_NLS=y
840CONFIG_NLS_DEFAULT="iso8859-1" 909CONFIG_NLS_DEFAULT="iso8859-1"
841# CONFIG_NLS_CODEPAGE_437 is not set 910CONFIG_NLS_CODEPAGE_437=y
842# CONFIG_NLS_CODEPAGE_737 is not set 911# CONFIG_NLS_CODEPAGE_737 is not set
843# CONFIG_NLS_CODEPAGE_775 is not set 912# CONFIG_NLS_CODEPAGE_775 is not set
844# CONFIG_NLS_CODEPAGE_850 is not set 913# CONFIG_NLS_CODEPAGE_850 is not set
@@ -862,7 +931,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
862# CONFIG_NLS_CODEPAGE_1250 is not set 931# CONFIG_NLS_CODEPAGE_1250 is not set
863# CONFIG_NLS_CODEPAGE_1251 is not set 932# CONFIG_NLS_CODEPAGE_1251 is not set
864# CONFIG_NLS_ASCII is not set 933# CONFIG_NLS_ASCII is not set
865# CONFIG_NLS_ISO8859_1 is not set 934CONFIG_NLS_ISO8859_1=y
866# CONFIG_NLS_ISO8859_2 is not set 935# CONFIG_NLS_ISO8859_2 is not set
867# CONFIG_NLS_ISO8859_3 is not set 936# CONFIG_NLS_ISO8859_3 is not set
868# CONFIG_NLS_ISO8859_4 is not set 937# CONFIG_NLS_ISO8859_4 is not set
@@ -876,21 +945,16 @@ CONFIG_NLS_DEFAULT="iso8859-1"
876# CONFIG_NLS_KOI8_R is not set 945# CONFIG_NLS_KOI8_R is not set
877# CONFIG_NLS_KOI8_U is not set 946# CONFIG_NLS_KOI8_U is not set
878# CONFIG_NLS_UTF8 is not set 947# CONFIG_NLS_UTF8 is not set
879
880#
881# Distributed Lock Manager
882#
883# CONFIG_DLM is not set 948# CONFIG_DLM is not set
884 949CONFIG_INSTRUMENTATION=y
885#
886# Profiling support
887#
888# CONFIG_PROFILING is not set 950# CONFIG_PROFILING is not set
951# CONFIG_MARKERS is not set
889 952
890# 953#
891# Kernel hacking 954# Kernel hacking
892# 955#
893# CONFIG_PRINTK_TIME is not set 956# CONFIG_PRINTK_TIME is not set
957CONFIG_ENABLE_WARN_DEPRECATED=y
894CONFIG_ENABLE_MUST_CHECK=y 958CONFIG_ENABLE_MUST_CHECK=y
895# CONFIG_MAGIC_SYSRQ is not set 959# CONFIG_MAGIC_SYSRQ is not set
896# CONFIG_UNUSED_SYMBOLS is not set 960# CONFIG_UNUSED_SYMBOLS is not set
@@ -899,6 +963,7 @@ CONFIG_ENABLE_MUST_CHECK=y
899# CONFIG_DEBUG_KERNEL is not set 963# CONFIG_DEBUG_KERNEL is not set
900CONFIG_DEBUG_BUGVERBOSE=y 964CONFIG_DEBUG_BUGVERBOSE=y
901CONFIG_FRAME_POINTER=y 965CONFIG_FRAME_POINTER=y
966# CONFIG_SAMPLES is not set
902# CONFIG_DEBUG_USER is not set 967# CONFIG_DEBUG_USER is not set
903 968
904# 969#
@@ -906,6 +971,7 @@ CONFIG_FRAME_POINTER=y
906# 971#
907# CONFIG_KEYS is not set 972# CONFIG_KEYS is not set
908# CONFIG_SECURITY is not set 973# CONFIG_SECURITY is not set
974# CONFIG_SECURITY_FILE_CAPABILITIES is not set
909CONFIG_CRYPTO=y 975CONFIG_CRYPTO=y
910CONFIG_CRYPTO_ALGAPI=y 976CONFIG_CRYPTO_ALGAPI=y
911CONFIG_CRYPTO_BLKCIPHER=y 977CONFIG_CRYPTO_BLKCIPHER=y
@@ -925,6 +991,7 @@ CONFIG_CRYPTO_ECB=m
925CONFIG_CRYPTO_CBC=y 991CONFIG_CRYPTO_CBC=y
926CONFIG_CRYPTO_PCBC=m 992CONFIG_CRYPTO_PCBC=m
927# CONFIG_CRYPTO_LRW is not set 993# CONFIG_CRYPTO_LRW is not set
994# CONFIG_CRYPTO_XTS is not set
928# CONFIG_CRYPTO_CRYPTD is not set 995# CONFIG_CRYPTO_CRYPTD is not set
929CONFIG_CRYPTO_DES=y 996CONFIG_CRYPTO_DES=y
930# CONFIG_CRYPTO_FCRYPT is not set 997# CONFIG_CRYPTO_FCRYPT is not set
@@ -938,11 +1005,13 @@ CONFIG_CRYPTO_DES=y
938# CONFIG_CRYPTO_ARC4 is not set 1005# CONFIG_CRYPTO_ARC4 is not set
939# CONFIG_CRYPTO_KHAZAD is not set 1006# CONFIG_CRYPTO_KHAZAD is not set
940# CONFIG_CRYPTO_ANUBIS is not set 1007# CONFIG_CRYPTO_ANUBIS is not set
1008# CONFIG_CRYPTO_SEED is not set
941# CONFIG_CRYPTO_DEFLATE is not set 1009# CONFIG_CRYPTO_DEFLATE is not set
942# CONFIG_CRYPTO_MICHAEL_MIC is not set 1010# CONFIG_CRYPTO_MICHAEL_MIC is not set
943# CONFIG_CRYPTO_CRC32C is not set 1011# CONFIG_CRYPTO_CRC32C is not set
944# CONFIG_CRYPTO_CAMELLIA is not set 1012# CONFIG_CRYPTO_CAMELLIA is not set
945# CONFIG_CRYPTO_TEST is not set 1013# CONFIG_CRYPTO_TEST is not set
1014# CONFIG_CRYPTO_AUTHENC is not set
946CONFIG_CRYPTO_HW=y 1015CONFIG_CRYPTO_HW=y
947 1016
948# 1017#
diff --git a/arch/arm/configs/omap_osk_5912_defconfig b/arch/arm/configs/omap_osk_5912_defconfig
index 8c1f15c7c45c..d592a6487114 100644
--- a/arch/arm/configs/omap_osk_5912_defconfig
+++ b/arch/arm/configs/omap_osk_5912_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc6 3# Linux kernel version: 2.6.24-rc5
4# Mon Sep 17 14:15:05 2007 4# Mon Dec 17 21:12:45 2007
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -40,9 +40,14 @@ CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_BSD_PROCESS_ACCT is not set 40# CONFIG_BSD_PROCESS_ACCT is not set
41# CONFIG_TASKSTATS is not set 41# CONFIG_TASKSTATS is not set
42# CONFIG_USER_NS is not set 42# CONFIG_USER_NS is not set
43# CONFIG_PID_NS is not set
43# CONFIG_AUDIT is not set 44# CONFIG_AUDIT is not set
44# CONFIG_IKCONFIG is not set 45# CONFIG_IKCONFIG is not set
45CONFIG_LOG_BUF_SHIFT=14 46CONFIG_LOG_BUF_SHIFT=14
47# CONFIG_CGROUPS is not set
48CONFIG_FAIR_GROUP_SCHED=y
49CONFIG_FAIR_USER_SCHED=y
50# CONFIG_FAIR_CGROUP_SCHED is not set
46# CONFIG_SYSFS_DEPRECATED is not set 51# CONFIG_SYSFS_DEPRECATED is not set
47# CONFIG_RELAY is not set 52# CONFIG_RELAY is not set
48CONFIG_BLK_DEV_INITRD=y 53CONFIG_BLK_DEV_INITRD=y
@@ -63,7 +68,6 @@ CONFIG_FUTEX=y
63CONFIG_ANON_INODES=y 68CONFIG_ANON_INODES=y
64CONFIG_EPOLL=y 69CONFIG_EPOLL=y
65CONFIG_SIGNALFD=y 70CONFIG_SIGNALFD=y
66CONFIG_TIMERFD=y
67CONFIG_EVENTFD=y 71CONFIG_EVENTFD=y
68CONFIG_SHMEM=y 72CONFIG_SHMEM=y
69CONFIG_VM_EVENT_COUNTERS=y 73CONFIG_VM_EVENT_COUNTERS=y
@@ -224,10 +228,6 @@ CONFIG_CPU_CP15_MMU=y
224# 228#
225# CONFIG_PCI_SYSCALL is not set 229# CONFIG_PCI_SYSCALL is not set
226# CONFIG_ARCH_SUPPORTS_MSI is not set 230# CONFIG_ARCH_SUPPORTS_MSI is not set
227
228#
229# PCCARD (PCMCIA/CardBus) support
230#
231CONFIG_PCCARD=y 231CONFIG_PCCARD=y
232# CONFIG_PCMCIA_DEBUG is not set 232# CONFIG_PCMCIA_DEBUG is not set
233CONFIG_PCMCIA=y 233CONFIG_PCMCIA=y
@@ -245,6 +245,7 @@ CONFIG_OMAP_CF=y
245CONFIG_TICK_ONESHOT=y 245CONFIG_TICK_ONESHOT=y
246CONFIG_NO_HZ=y 246CONFIG_NO_HZ=y
247CONFIG_HIGH_RES_TIMERS=y 247CONFIG_HIGH_RES_TIMERS=y
248CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
248# CONFIG_PREEMPT is not set 249# CONFIG_PREEMPT is not set
249CONFIG_HZ=128 250CONFIG_HZ=128
250CONFIG_AEABI=y 251CONFIG_AEABI=y
@@ -257,6 +258,7 @@ CONFIG_FLATMEM_MANUAL=y
257CONFIG_FLATMEM=y 258CONFIG_FLATMEM=y
258CONFIG_FLAT_NODE_MEM_MAP=y 259CONFIG_FLAT_NODE_MEM_MAP=y
259# CONFIG_SPARSEMEM_STATIC is not set 260# CONFIG_SPARSEMEM_STATIC is not set
261# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
260CONFIG_SPLIT_PTLOCK_CPUS=4096 262CONFIG_SPLIT_PTLOCK_CPUS=4096
261# CONFIG_RESOURCES_64BIT is not set 263# CONFIG_RESOURCES_64BIT is not set
262CONFIG_ZONE_DMA_FLAG=1 264CONFIG_ZONE_DMA_FLAG=1
@@ -346,6 +348,7 @@ CONFIG_IP_PNP_BOOTP=y
346CONFIG_INET_XFRM_MODE_TRANSPORT=y 348CONFIG_INET_XFRM_MODE_TRANSPORT=y
347CONFIG_INET_XFRM_MODE_TUNNEL=y 349CONFIG_INET_XFRM_MODE_TUNNEL=y
348CONFIG_INET_XFRM_MODE_BEET=y 350CONFIG_INET_XFRM_MODE_BEET=y
351# CONFIG_INET_LRO is not set
349CONFIG_INET_DIAG=y 352CONFIG_INET_DIAG=y
350CONFIG_INET_TCP_DIAG=y 353CONFIG_INET_TCP_DIAG=y
351# CONFIG_TCP_CONG_ADVANCED is not set 354# CONFIG_TCP_CONG_ADVANCED is not set
@@ -371,10 +374,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
371# CONFIG_LAPB is not set 374# CONFIG_LAPB is not set
372# CONFIG_ECONET is not set 375# CONFIG_ECONET is not set
373# CONFIG_WAN_ROUTER is not set 376# CONFIG_WAN_ROUTER is not set
374
375#
376# QoS and/or fair queueing
377#
378# CONFIG_NET_SCHED is not set 377# CONFIG_NET_SCHED is not set
379 378
380# 379#
@@ -403,6 +402,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
403# 402#
404# Generic Driver Options 403# Generic Driver Options
405# 404#
405CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
406CONFIG_STANDALONE=y 406CONFIG_STANDALONE=y
407CONFIG_PREVENT_FIRMWARE_BUILD=y 407CONFIG_PREVENT_FIRMWARE_BUILD=y
408CONFIG_FW_LOADER=y 408CONFIG_FW_LOADER=y
@@ -427,6 +427,7 @@ CONFIG_MTD_BLOCK=y
427# CONFIG_INFTL is not set 427# CONFIG_INFTL is not set
428# CONFIG_RFD_FTL is not set 428# CONFIG_RFD_FTL is not set
429# CONFIG_SSFDC is not set 429# CONFIG_SSFDC is not set
430# CONFIG_MTD_OOPS is not set
430 431
431# 432#
432# RAM/ROM/Flash chip drivers 433# RAM/ROM/Flash chip drivers
@@ -495,6 +496,8 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
495CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 496CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
496# CONFIG_CDROM_PKTCDVD is not set 497# CONFIG_CDROM_PKTCDVD is not set
497# CONFIG_ATA_OVER_ETH is not set 498# CONFIG_ATA_OVER_ETH is not set
499CONFIG_MISC_DEVICES=y
500# CONFIG_EEPROM_93CX6 is not set
498CONFIG_IDE=m 501CONFIG_IDE=m
499CONFIG_BLK_DEV_IDE=m 502CONFIG_BLK_DEV_IDE=m
500 503
@@ -515,9 +518,10 @@ CONFIG_IDE_PROC_FS=y
515# IDE chipset support/bugfixes 518# IDE chipset support/bugfixes
516# 519#
517# CONFIG_IDE_GENERIC is not set 520# CONFIG_IDE_GENERIC is not set
518# CONFIG_IDEPCI_PCIBUS_ORDER is not set 521# CONFIG_BLK_DEV_PLATFORM is not set
519# CONFIG_IDE_ARM is not set 522# CONFIG_IDE_ARM is not set
520# CONFIG_BLK_DEV_IDEDMA is not set 523# CONFIG_BLK_DEV_IDEDMA is not set
524CONFIG_IDE_ARCH_OBSOLETE_INIT=y
521# CONFIG_BLK_DEV_HD is not set 525# CONFIG_BLK_DEV_HD is not set
522 526
523# 527#
@@ -536,12 +540,18 @@ CONFIG_NETDEVICES=y
536# CONFIG_MACVLAN is not set 540# CONFIG_MACVLAN is not set
537# CONFIG_EQUALIZER is not set 541# CONFIG_EQUALIZER is not set
538# CONFIG_TUN is not set 542# CONFIG_TUN is not set
543# CONFIG_VETH is not set
539# CONFIG_PHYLIB is not set 544# CONFIG_PHYLIB is not set
540CONFIG_NET_ETHERNET=y 545CONFIG_NET_ETHERNET=y
541CONFIG_MII=y 546CONFIG_MII=y
542# CONFIG_AX88796 is not set 547# CONFIG_AX88796 is not set
543CONFIG_SMC91X=y 548CONFIG_SMC91X=y
544# CONFIG_DM9000 is not set 549# CONFIG_DM9000 is not set
550# CONFIG_IBM_NEW_EMAC_ZMII is not set
551# CONFIG_IBM_NEW_EMAC_RGMII is not set
552# CONFIG_IBM_NEW_EMAC_TAH is not set
553# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
554# CONFIG_B44 is not set
545CONFIG_NETDEV_1000=y 555CONFIG_NETDEV_1000=y
546CONFIG_NETDEV_10000=y 556CONFIG_NETDEV_10000=y
547 557
@@ -585,7 +595,6 @@ CONFIG_INPUT_MOUSEDEV=y
585CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 595CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
586CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 596CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
587# CONFIG_INPUT_JOYDEV is not set 597# CONFIG_INPUT_JOYDEV is not set
588# CONFIG_INPUT_TSDEV is not set
589CONFIG_INPUT_EVDEV=y 598CONFIG_INPUT_EVDEV=y
590# CONFIG_INPUT_EVBUG is not set 599# CONFIG_INPUT_EVBUG is not set
591 600
@@ -651,7 +660,6 @@ CONFIG_UNIX98_PTYS=y
651CONFIG_LEGACY_PTYS=y 660CONFIG_LEGACY_PTYS=y
652CONFIG_LEGACY_PTY_COUNT=256 661CONFIG_LEGACY_PTY_COUNT=256
653# CONFIG_IPMI_HANDLER is not set 662# CONFIG_IPMI_HANDLER is not set
654# CONFIG_WATCHDOG is not set
655CONFIG_HW_RANDOM=m 663CONFIG_HW_RANDOM=m
656CONFIG_HW_RANDOM_OMAP=m 664CONFIG_HW_RANDOM_OMAP=m
657# CONFIG_NVRAM is not set 665# CONFIG_NVRAM is not set
@@ -712,10 +720,9 @@ CONFIG_TPS65010=y
712# CONFIG_SPI is not set 720# CONFIG_SPI is not set
713# CONFIG_SPI_MASTER is not set 721# CONFIG_SPI_MASTER is not set
714# CONFIG_W1 is not set 722# CONFIG_W1 is not set
723# CONFIG_POWER_SUPPLY is not set
715CONFIG_HWMON=y 724CONFIG_HWMON=y
716# CONFIG_HWMON_VID is not set 725# CONFIG_HWMON_VID is not set
717# CONFIG_SENSORS_ABITUGURU is not set
718# CONFIG_SENSORS_ABITUGURU3 is not set
719# CONFIG_SENSORS_AD7418 is not set 726# CONFIG_SENSORS_AD7418 is not set
720# CONFIG_SENSORS_ADM1021 is not set 727# CONFIG_SENSORS_ADM1021 is not set
721# CONFIG_SENSORS_ADM1025 is not set 728# CONFIG_SENSORS_ADM1025 is not set
@@ -723,12 +730,12 @@ CONFIG_HWMON=y
723# CONFIG_SENSORS_ADM1029 is not set 730# CONFIG_SENSORS_ADM1029 is not set
724# CONFIG_SENSORS_ADM1031 is not set 731# CONFIG_SENSORS_ADM1031 is not set
725# CONFIG_SENSORS_ADM9240 is not set 732# CONFIG_SENSORS_ADM9240 is not set
726# CONFIG_SENSORS_ASB100 is not set 733# CONFIG_SENSORS_ADT7470 is not set
727# CONFIG_SENSORS_ATXP1 is not set 734# CONFIG_SENSORS_ATXP1 is not set
728# CONFIG_SENSORS_DS1621 is not set 735# CONFIG_SENSORS_DS1621 is not set
729# CONFIG_SENSORS_F71805F is not set 736# CONFIG_SENSORS_F71805F is not set
730# CONFIG_SENSORS_FSCHER is not set 737# CONFIG_SENSORS_F71882FG is not set
731# CONFIG_SENSORS_FSCPOS is not set 738# CONFIG_SENSORS_F75375S is not set
732# CONFIG_SENSORS_GL518SM is not set 739# CONFIG_SENSORS_GL518SM is not set
733# CONFIG_SENSORS_GL520SM is not set 740# CONFIG_SENSORS_GL520SM is not set
734# CONFIG_SENSORS_IT87 is not set 741# CONFIG_SENSORS_IT87 is not set
@@ -761,14 +768,18 @@ CONFIG_HWMON=y
761# CONFIG_SENSORS_W83627HF is not set 768# CONFIG_SENSORS_W83627HF is not set
762# CONFIG_SENSORS_W83627EHF is not set 769# CONFIG_SENSORS_W83627EHF is not set
763# CONFIG_HWMON_DEBUG_CHIP is not set 770# CONFIG_HWMON_DEBUG_CHIP is not set
764CONFIG_MISC_DEVICES=y 771# CONFIG_WATCHDOG is not set
765# CONFIG_EEPROM_93CX6 is not set 772
773#
774# Sonics Silicon Backplane
775#
776CONFIG_SSB_POSSIBLE=y
777# CONFIG_SSB is not set
766 778
767# 779#
768# Multifunction device drivers 780# Multifunction device drivers
769# 781#
770# CONFIG_MFD_SM501 is not set 782# CONFIG_MFD_SM501 is not set
771# CONFIG_NEW_LEDS is not set
772 783
773# 784#
774# Multimedia devices 785# Multimedia devices
@@ -780,12 +791,6 @@ CONFIG_DAB=y
780# 791#
781# Graphics support 792# Graphics support
782# 793#
783# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
784
785#
786# Display device support
787#
788# CONFIG_DISPLAY_SUPPORT is not set
789# CONFIG_VGASTATE is not set 794# CONFIG_VGASTATE is not set
790CONFIG_VIDEO_OUTPUT_CONTROL=m 795CONFIG_VIDEO_OUTPUT_CONTROL=m
791CONFIG_FB=y 796CONFIG_FB=y
@@ -794,6 +799,7 @@ CONFIG_FIRMWARE_EDID=y
794# CONFIG_FB_CFB_FILLRECT is not set 799# CONFIG_FB_CFB_FILLRECT is not set
795# CONFIG_FB_CFB_COPYAREA is not set 800# CONFIG_FB_CFB_COPYAREA is not set
796# CONFIG_FB_CFB_IMAGEBLIT is not set 801# CONFIG_FB_CFB_IMAGEBLIT is not set
802# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
797# CONFIG_FB_SYS_FILLRECT is not set 803# CONFIG_FB_SYS_FILLRECT is not set
798# CONFIG_FB_SYS_COPYAREA is not set 804# CONFIG_FB_SYS_COPYAREA is not set
799# CONFIG_FB_SYS_IMAGEBLIT is not set 805# CONFIG_FB_SYS_IMAGEBLIT is not set
@@ -809,8 +815,14 @@ CONFIG_FB_MODE_HELPERS=y
809# Frame buffer hardware drivers 815# Frame buffer hardware drivers
810# 816#
811# CONFIG_FB_S1D13XXX is not set 817# CONFIG_FB_S1D13XXX is not set
812# CONFIG_FB_OMAP is not set
813# CONFIG_FB_VIRTUAL is not set 818# CONFIG_FB_VIRTUAL is not set
819# CONFIG_FB_OMAP is not set
820# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
821
822#
823# Display device support
824#
825# CONFIG_DISPLAY_SUPPORT is not set
814 826
815# 827#
816# Console display driver support 828# Console display driver support
@@ -843,6 +855,7 @@ CONFIG_LOGO_LINUX_CLUT224=y
843CONFIG_HID_SUPPORT=y 855CONFIG_HID_SUPPORT=y
844CONFIG_HID=y 856CONFIG_HID=y
845CONFIG_HID_DEBUG=y 857CONFIG_HID_DEBUG=y
858# CONFIG_HIDRAW is not set
846CONFIG_USB_SUPPORT=y 859CONFIG_USB_SUPPORT=y
847CONFIG_USB_ARCH_HAS_HCD=y 860CONFIG_USB_ARCH_HAS_HCD=y
848CONFIG_USB_ARCH_HAS_OHCI=y 861CONFIG_USB_ARCH_HAS_OHCI=y
@@ -858,23 +871,11 @@ CONFIG_USB_ARCH_HAS_OHCI=y
858# 871#
859# CONFIG_USB_GADGET is not set 872# CONFIG_USB_GADGET is not set
860# CONFIG_MMC is not set 873# CONFIG_MMC is not set
874# CONFIG_NEW_LEDS is not set
861CONFIG_RTC_LIB=y 875CONFIG_RTC_LIB=y
862# CONFIG_RTC_CLASS is not set 876# CONFIG_RTC_CLASS is not set
863 877
864# 878#
865# DMA Engine support
866#
867# CONFIG_DMA_ENGINE is not set
868
869#
870# DMA Clients
871#
872
873#
874# DMA Devices
875#
876
877#
878# File systems 879# File systems
879# 880#
880CONFIG_EXT2_FS=y 881CONFIG_EXT2_FS=y
@@ -922,7 +923,6 @@ CONFIG_PROC_SYSCTL=y
922CONFIG_SYSFS=y 923CONFIG_SYSFS=y
923# CONFIG_TMPFS is not set 924# CONFIG_TMPFS is not set
924# CONFIG_HUGETLB_PAGE is not set 925# CONFIG_HUGETLB_PAGE is not set
925CONFIG_RAMFS=y
926# CONFIG_CONFIGFS_FS is not set 926# CONFIG_CONFIGFS_FS is not set
927 927
928# 928#
@@ -938,10 +938,12 @@ CONFIG_RAMFS=y
938CONFIG_JFFS2_FS=y 938CONFIG_JFFS2_FS=y
939CONFIG_JFFS2_FS_DEBUG=0 939CONFIG_JFFS2_FS_DEBUG=0
940CONFIG_JFFS2_FS_WRITEBUFFER=y 940CONFIG_JFFS2_FS_WRITEBUFFER=y
941# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
941# CONFIG_JFFS2_SUMMARY is not set 942# CONFIG_JFFS2_SUMMARY is not set
942# CONFIG_JFFS2_FS_XATTR is not set 943# CONFIG_JFFS2_FS_XATTR is not set
943# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set 944# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
944CONFIG_JFFS2_ZLIB=y 945CONFIG_JFFS2_ZLIB=y
946# CONFIG_JFFS2_LZO is not set
945CONFIG_JFFS2_RTIME=y 947CONFIG_JFFS2_RTIME=y
946# CONFIG_JFFS2_RUBIN is not set 948# CONFIG_JFFS2_RUBIN is not set
947# CONFIG_CRAMFS is not set 949# CONFIG_CRAMFS is not set
@@ -950,10 +952,7 @@ CONFIG_JFFS2_RTIME=y
950# CONFIG_QNX4FS_FS is not set 952# CONFIG_QNX4FS_FS is not set
951# CONFIG_SYSV_FS is not set 953# CONFIG_SYSV_FS is not set
952# CONFIG_UFS_FS is not set 954# CONFIG_UFS_FS is not set
953 955CONFIG_NETWORK_FILESYSTEMS=y
954#
955# Network File Systems
956#
957CONFIG_NFS_FS=y 956CONFIG_NFS_FS=y
958CONFIG_NFS_V3=y 957CONFIG_NFS_V3=y
959# CONFIG_NFS_V3_ACL is not set 958# CONFIG_NFS_V3_ACL is not set
@@ -979,10 +978,6 @@ CONFIG_SUNRPC=y
979# 978#
980# CONFIG_PARTITION_ADVANCED is not set 979# CONFIG_PARTITION_ADVANCED is not set
981CONFIG_MSDOS_PARTITION=y 980CONFIG_MSDOS_PARTITION=y
982
983#
984# Native Language Support
985#
986CONFIG_NLS=m 981CONFIG_NLS=m
987CONFIG_NLS_DEFAULT="iso8859-1" 982CONFIG_NLS_DEFAULT="iso8859-1"
988CONFIG_NLS_CODEPAGE_437=m 983CONFIG_NLS_CODEPAGE_437=m
@@ -1023,21 +1018,16 @@ CONFIG_NLS_ISO8859_1=m
1023# CONFIG_NLS_KOI8_R is not set 1018# CONFIG_NLS_KOI8_R is not set
1024# CONFIG_NLS_KOI8_U is not set 1019# CONFIG_NLS_KOI8_U is not set
1025# CONFIG_NLS_UTF8 is not set 1020# CONFIG_NLS_UTF8 is not set
1026
1027#
1028# Distributed Lock Manager
1029#
1030# CONFIG_DLM is not set 1021# CONFIG_DLM is not set
1031 1022CONFIG_INSTRUMENTATION=y
1032#
1033# Profiling support
1034#
1035# CONFIG_PROFILING is not set 1023# CONFIG_PROFILING is not set
1024# CONFIG_MARKERS is not set
1036 1025
1037# 1026#
1038# Kernel hacking 1027# Kernel hacking
1039# 1028#
1040# CONFIG_PRINTK_TIME is not set 1029# CONFIG_PRINTK_TIME is not set
1030CONFIG_ENABLE_WARN_DEPRECATED=y
1041CONFIG_ENABLE_MUST_CHECK=y 1031CONFIG_ENABLE_MUST_CHECK=y
1042# CONFIG_MAGIC_SYSRQ is not set 1032# CONFIG_MAGIC_SYSRQ is not set
1043# CONFIG_UNUSED_SYMBOLS is not set 1033# CONFIG_UNUSED_SYMBOLS is not set
@@ -1046,6 +1036,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1046# CONFIG_DEBUG_KERNEL is not set 1036# CONFIG_DEBUG_KERNEL is not set
1047CONFIG_DEBUG_BUGVERBOSE=y 1037CONFIG_DEBUG_BUGVERBOSE=y
1048CONFIG_FRAME_POINTER=y 1038CONFIG_FRAME_POINTER=y
1039# CONFIG_SAMPLES is not set
1049# CONFIG_DEBUG_USER is not set 1040# CONFIG_DEBUG_USER is not set
1050 1041
1051# 1042#
@@ -1053,6 +1044,7 @@ CONFIG_FRAME_POINTER=y
1053# 1044#
1054# CONFIG_KEYS is not set 1045# CONFIG_KEYS is not set
1055# CONFIG_SECURITY is not set 1046# CONFIG_SECURITY is not set
1047# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1056# CONFIG_CRYPTO is not set 1048# CONFIG_CRYPTO is not set
1057 1049
1058# 1050#
diff --git a/arch/arm/configs/orion_defconfig b/arch/arm/configs/orion_defconfig
index 17a55def1103..1e5aaa645fcd 100644
--- a/arch/arm/configs/orion_defconfig
+++ b/arch/arm/configs/orion_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24-rc3 3# Linux kernel version: 2.6.24
4# Wed Nov 28 15:13:57 2007 4# Thu Feb 7 14:10:30 2008
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -63,17 +63,26 @@ CONFIG_HOTPLUG=y
63CONFIG_PRINTK=y 63CONFIG_PRINTK=y
64CONFIG_BUG=y 64CONFIG_BUG=y
65CONFIG_ELF_CORE=y 65CONFIG_ELF_CORE=y
66CONFIG_COMPAT_BRK=y
66CONFIG_BASE_FULL=y 67CONFIG_BASE_FULL=y
67CONFIG_FUTEX=y 68CONFIG_FUTEX=y
68CONFIG_ANON_INODES=y 69CONFIG_ANON_INODES=y
69CONFIG_EPOLL=y 70CONFIG_EPOLL=y
70CONFIG_SIGNALFD=y 71CONFIG_SIGNALFD=y
72CONFIG_TIMERFD=y
71CONFIG_EVENTFD=y 73CONFIG_EVENTFD=y
72CONFIG_SHMEM=y 74CONFIG_SHMEM=y
73CONFIG_VM_EVENT_COUNTERS=y 75CONFIG_VM_EVENT_COUNTERS=y
74CONFIG_SLAB=y 76CONFIG_SLAB=y
75# CONFIG_SLUB is not set 77# CONFIG_SLUB is not set
76# CONFIG_SLOB is not set 78# CONFIG_SLOB is not set
79# CONFIG_PROFILING is not set
80# CONFIG_MARKERS is not set
81CONFIG_HAVE_OPROFILE=y
82# CONFIG_KPROBES is not set
83CONFIG_HAVE_KPROBES=y
84CONFIG_PROC_PAGE_MONITOR=y
85CONFIG_SLABINFO=y
77CONFIG_RT_MUTEXES=y 86CONFIG_RT_MUTEXES=y
78# CONFIG_TINY_SHMEM is not set 87# CONFIG_TINY_SHMEM is not set
79CONFIG_BASE_SMALL=0 88CONFIG_BASE_SMALL=0
@@ -101,6 +110,8 @@ CONFIG_IOSCHED_CFQ=y
101CONFIG_DEFAULT_CFQ=y 110CONFIG_DEFAULT_CFQ=y
102# CONFIG_DEFAULT_NOOP is not set 111# CONFIG_DEFAULT_NOOP is not set
103CONFIG_DEFAULT_IOSCHED="cfq" 112CONFIG_DEFAULT_IOSCHED="cfq"
113CONFIG_CLASSIC_RCU=y
114# CONFIG_PREEMPT_RCU is not set
104 115
105# 116#
106# System Type 117# System Type
@@ -139,6 +150,7 @@ CONFIG_ARCH_ORION=y
139# CONFIG_ARCH_LH7A40X is not set 150# CONFIG_ARCH_LH7A40X is not set
140# CONFIG_ARCH_DAVINCI is not set 151# CONFIG_ARCH_DAVINCI is not set
141# CONFIG_ARCH_OMAP is not set 152# CONFIG_ARCH_OMAP is not set
153# CONFIG_ARCH_MSM7X00A is not set
142 154
143# 155#
144# Orion Implementations 156# Orion Implementations
@@ -226,6 +238,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
226CONFIG_CMDLINE="" 238CONFIG_CMDLINE=""
227# CONFIG_XIP_KERNEL is not set 239# CONFIG_XIP_KERNEL is not set
228# CONFIG_KEXEC is not set 240# CONFIG_KEXEC is not set
241# CONFIG_ATAGS_PROC is not set
229 242
230# 243#
231# Floating point emulation 244# Floating point emulation
@@ -250,7 +263,7 @@ CONFIG_BINFMT_ELF=y
250# Power management options 263# Power management options
251# 264#
252# CONFIG_PM is not set 265# CONFIG_PM is not set
253CONFIG_SUSPEND_UP_POSSIBLE=y 266CONFIG_ARCH_SUSPEND_POSSIBLE=y
254 267
255# 268#
256# Networking 269# Networking
@@ -267,6 +280,7 @@ CONFIG_XFRM=y
267# CONFIG_XFRM_USER is not set 280# CONFIG_XFRM_USER is not set
268# CONFIG_XFRM_SUB_POLICY is not set 281# CONFIG_XFRM_SUB_POLICY is not set
269# CONFIG_XFRM_MIGRATE is not set 282# CONFIG_XFRM_MIGRATE is not set
283# CONFIG_XFRM_STATISTICS is not set
270# CONFIG_NET_KEY is not set 284# CONFIG_NET_KEY is not set
271CONFIG_INET=y 285CONFIG_INET=y
272CONFIG_IP_MULTICAST=y 286CONFIG_IP_MULTICAST=y
@@ -322,6 +336,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
322# 336#
323CONFIG_NET_PKTGEN=m 337CONFIG_NET_PKTGEN=m
324# CONFIG_HAMRADIO is not set 338# CONFIG_HAMRADIO is not set
339# CONFIG_CAN is not set
325# CONFIG_IRDA is not set 340# CONFIG_IRDA is not set
326# CONFIG_BT is not set 341# CONFIG_BT is not set
327# CONFIG_AF_RXRPC is not set 342# CONFIG_AF_RXRPC is not set
@@ -475,7 +490,7 @@ CONFIG_SCSI=y
475CONFIG_SCSI_DMA=y 490CONFIG_SCSI_DMA=y
476# CONFIG_SCSI_TGT is not set 491# CONFIG_SCSI_TGT is not set
477# CONFIG_SCSI_NETLINK is not set 492# CONFIG_SCSI_NETLINK is not set
478CONFIG_SCSI_PROC_FS=y 493# CONFIG_SCSI_PROC_FS is not set
479 494
480# 495#
481# SCSI support type (disk, tape, CD-ROM) 496# SCSI support type (disk, tape, CD-ROM)
@@ -483,15 +498,15 @@ CONFIG_SCSI_PROC_FS=y
483CONFIG_BLK_DEV_SD=y 498CONFIG_BLK_DEV_SD=y
484# CONFIG_CHR_DEV_ST is not set 499# CONFIG_CHR_DEV_ST is not set
485# CONFIG_CHR_DEV_OSST is not set 500# CONFIG_CHR_DEV_OSST is not set
486CONFIG_BLK_DEV_SR=y 501CONFIG_BLK_DEV_SR=m
487# CONFIG_BLK_DEV_SR_VENDOR is not set 502# CONFIG_BLK_DEV_SR_VENDOR is not set
488CONFIG_CHR_DEV_SG=y 503CONFIG_CHR_DEV_SG=m
489# CONFIG_CHR_DEV_SCH is not set 504# CONFIG_CHR_DEV_SCH is not set
490 505
491# 506#
492# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 507# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
493# 508#
494CONFIG_SCSI_MULTI_LUN=y 509# CONFIG_SCSI_MULTI_LUN is not set
495# CONFIG_SCSI_CONSTANTS is not set 510# CONFIG_SCSI_CONSTANTS is not set
496# CONFIG_SCSI_LOGGING is not set 511# CONFIG_SCSI_LOGGING is not set
497# CONFIG_SCSI_SCAN_ASYNC is not set 512# CONFIG_SCSI_SCAN_ASYNC is not set
@@ -528,16 +543,6 @@ CONFIG_SCSI_LOWLEVEL=y
528# CONFIG_SCSI_INITIO is not set 543# CONFIG_SCSI_INITIO is not set
529# CONFIG_SCSI_INIA100 is not set 544# CONFIG_SCSI_INIA100 is not set
530# CONFIG_SCSI_STEX is not set 545# CONFIG_SCSI_STEX is not set
531CONFIG_SCSI_MVSATA=y
532
533#
534# Sata options
535#
536# CONFIG_MV_SATA_SUPPORT_ATAPI is not set
537# CONFIG_MV_SATA_ENABLE_1MB_IOS is not set
538CONFIG_SATA_NO_DEBUG=y
539# CONFIG_SATA_DEBUG_ON_ERROR is not set
540# CONFIG_SATA_FULL_DEBUG is not set
541# CONFIG_SCSI_SYM53C8XX_2 is not set 546# CONFIG_SCSI_SYM53C8XX_2 is not set
542# CONFIG_SCSI_IPR is not set 547# CONFIG_SCSI_IPR is not set
543# CONFIG_SCSI_QLOGIC_1280 is not set 548# CONFIG_SCSI_QLOGIC_1280 is not set
@@ -549,12 +554,12 @@ CONFIG_SATA_NO_DEBUG=y
549# CONFIG_SCSI_NSP32 is not set 554# CONFIG_SCSI_NSP32 is not set
550# CONFIG_SCSI_DEBUG is not set 555# CONFIG_SCSI_DEBUG is not set
551# CONFIG_SCSI_SRP is not set 556# CONFIG_SCSI_SRP is not set
552CONFIG_ATA=m 557CONFIG_ATA=y
553# CONFIG_ATA_NONSTANDARD is not set 558# CONFIG_ATA_NONSTANDARD is not set
554# CONFIG_SATA_AHCI is not set 559# CONFIG_SATA_AHCI is not set
555# CONFIG_SATA_SVW is not set 560# CONFIG_SATA_SVW is not set
556# CONFIG_ATA_PIIX is not set 561# CONFIG_ATA_PIIX is not set
557# CONFIG_SATA_MV is not set 562CONFIG_SATA_MV=y
558# CONFIG_SATA_NV is not set 563# CONFIG_SATA_NV is not set
559# CONFIG_PDC_ADMA is not set 564# CONFIG_PDC_ADMA is not set
560# CONFIG_SATA_QSTOR is not set 565# CONFIG_SATA_QSTOR is not set
@@ -590,6 +595,7 @@ CONFIG_ATA=m
590# CONFIG_PATA_MPIIX is not set 595# CONFIG_PATA_MPIIX is not set
591# CONFIG_PATA_OLDPIIX is not set 596# CONFIG_PATA_OLDPIIX is not set
592# CONFIG_PATA_NETCELL is not set 597# CONFIG_PATA_NETCELL is not set
598# CONFIG_PATA_NINJA32 is not set
593# CONFIG_PATA_NS87410 is not set 599# CONFIG_PATA_NS87410 is not set
594# CONFIG_PATA_NS87415 is not set 600# CONFIG_PATA_NS87415 is not set
595# CONFIG_PATA_OPTI is not set 601# CONFIG_PATA_OPTI is not set
@@ -622,7 +628,6 @@ CONFIG_NETDEVICES=y
622# CONFIG_EQUALIZER is not set 628# CONFIG_EQUALIZER is not set
623# CONFIG_TUN is not set 629# CONFIG_TUN is not set
624# CONFIG_VETH is not set 630# CONFIG_VETH is not set
625# CONFIG_IP1000 is not set
626# CONFIG_ARCNET is not set 631# CONFIG_ARCNET is not set
627# CONFIG_PHYLIB is not set 632# CONFIG_PHYLIB is not set
628CONFIG_NET_ETHERNET=y 633CONFIG_NET_ETHERNET=y
@@ -653,6 +658,7 @@ CONFIG_E100=y
653# CONFIG_NE2K_PCI is not set 658# CONFIG_NE2K_PCI is not set
654# CONFIG_8139CP is not set 659# CONFIG_8139CP is not set
655# CONFIG_8139TOO is not set 660# CONFIG_8139TOO is not set
661# CONFIG_R6040 is not set
656# CONFIG_SIS900 is not set 662# CONFIG_SIS900 is not set
657# CONFIG_EPIC100 is not set 663# CONFIG_EPIC100 is not set
658# CONFIG_SUNDANCE is not set 664# CONFIG_SUNDANCE is not set
@@ -666,6 +672,9 @@ CONFIG_E1000=y
666CONFIG_E1000_NAPI=y 672CONFIG_E1000_NAPI=y
667# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 673# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
668# CONFIG_E1000E is not set 674# CONFIG_E1000E is not set
675# CONFIG_E1000E_ENABLED is not set
676# CONFIG_IP1000 is not set
677# CONFIG_IGB is not set
669# CONFIG_NS83820 is not set 678# CONFIG_NS83820 is not set
670# CONFIG_HAMACHI is not set 679# CONFIG_HAMACHI is not set
671# CONFIG_YELLOWFIN is not set 680# CONFIG_YELLOWFIN is not set
@@ -691,6 +700,7 @@ CONFIG_NETDEV_10000=y
691# CONFIG_NIU is not set 700# CONFIG_NIU is not set
692# CONFIG_MLX4_CORE is not set 701# CONFIG_MLX4_CORE is not set
693# CONFIG_TEHUTI is not set 702# CONFIG_TEHUTI is not set
703# CONFIG_BNX2X is not set
694# CONFIG_TR is not set 704# CONFIG_TR is not set
695 705
696# 706#
@@ -713,7 +723,6 @@ CONFIG_NETDEV_10000=y
713# CONFIG_PPP is not set 723# CONFIG_PPP is not set
714# CONFIG_SLIP is not set 724# CONFIG_SLIP is not set
715# CONFIG_NET_FC is not set 725# CONFIG_NET_FC is not set
716# CONFIG_SHAPER is not set
717# CONFIG_NETCONSOLE is not set 726# CONFIG_NETCONSOLE is not set
718# CONFIG_NETPOLL is not set 727# CONFIG_NETPOLL is not set
719# CONFIG_NET_POLL_CONTROLLER is not set 728# CONFIG_NET_POLL_CONTROLLER is not set
@@ -761,6 +770,7 @@ CONFIG_VT_CONSOLE=y
761CONFIG_HW_CONSOLE=y 770CONFIG_HW_CONSOLE=y
762# CONFIG_VT_HW_CONSOLE_BINDING is not set 771# CONFIG_VT_HW_CONSOLE_BINDING is not set
763# CONFIG_SERIAL_NONSTANDARD is not set 772# CONFIG_SERIAL_NONSTANDARD is not set
773# CONFIG_NOZOMI is not set
764 774
765# 775#
766# Serial drivers 776# Serial drivers
@@ -832,13 +842,12 @@ CONFIG_I2C_MV64XXX=y
832# 842#
833# Miscellaneous I2C Chip support 843# Miscellaneous I2C Chip support
834# 844#
835# CONFIG_SENSORS_DS1337 is not set
836# CONFIG_SENSORS_DS1374 is not set
837# CONFIG_DS1682 is not set 845# CONFIG_DS1682 is not set
838# CONFIG_SENSORS_EEPROM is not set 846# CONFIG_SENSORS_EEPROM is not set
839# CONFIG_SENSORS_PCF8574 is not set 847# CONFIG_SENSORS_PCF8574 is not set
840# CONFIG_SENSORS_PCA9539 is not set 848# CONFIG_PCF8575 is not set
841# CONFIG_SENSORS_PCF8591 is not set 849# CONFIG_SENSORS_PCF8591 is not set
850# CONFIG_TPS65010 is not set
842# CONFIG_SENSORS_MAX6875 is not set 851# CONFIG_SENSORS_MAX6875 is not set
843# CONFIG_SENSORS_TSL2550 is not set 852# CONFIG_SENSORS_TSL2550 is not set
844# CONFIG_I2C_DEBUG_CORE is not set 853# CONFIG_I2C_DEBUG_CORE is not set
@@ -967,6 +976,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
967CONFIG_USB_ARCH_HAS_EHCI=y 976CONFIG_USB_ARCH_HAS_EHCI=y
968CONFIG_USB=y 977CONFIG_USB=y
969# CONFIG_USB_DEBUG is not set 978# CONFIG_USB_DEBUG is not set
979# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
970 980
971# 981#
972# Miscellaneous USB options 982# Miscellaneous USB options
@@ -980,16 +990,12 @@ CONFIG_USB_DEVICE_CLASS=y
980# USB Host Controller Drivers 990# USB Host Controller Drivers
981# 991#
982CONFIG_USB_EHCI_HCD=y 992CONFIG_USB_EHCI_HCD=y
983CONFIG_USB_EHCI_SPLIT_ISO=y
984CONFIG_USB_EHCI_ROOT_HUB_TT=y 993CONFIG_USB_EHCI_ROOT_HUB_TT=y
985CONFIG_USB_EHCI_TT_NEWSCHED=y 994CONFIG_USB_EHCI_TT_NEWSCHED=y
986# CONFIG_USB_ISP116X_HCD is not set 995# CONFIG_USB_ISP116X_HCD is not set
987CONFIG_USB_OHCI_HCD=y 996# CONFIG_USB_OHCI_HCD is not set
988# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set 997# CONFIG_USB_UHCI_HCD is not set
989# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set 998# CONFIG_USB_SL811_HCD is not set
990CONFIG_USB_OHCI_LITTLE_ENDIAN=y
991CONFIG_USB_UHCI_HCD=y
992CONFIG_USB_SL811_HCD=y
993# CONFIG_USB_R8A66597_HCD is not set 999# CONFIG_USB_R8A66597_HCD is not set
994 1000
995# 1001#
@@ -1029,10 +1035,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1029# 1035#
1030# USB port drivers 1036# USB port drivers
1031# 1037#
1032
1033#
1034# USB Serial Converter support
1035#
1036# CONFIG_USB_SERIAL is not set 1038# CONFIG_USB_SERIAL is not set
1037 1039
1038# 1040#
@@ -1058,14 +1060,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1058# CONFIG_USB_TRANCEVIBRATOR is not set 1060# CONFIG_USB_TRANCEVIBRATOR is not set
1059# CONFIG_USB_IOWARRIOR is not set 1061# CONFIG_USB_IOWARRIOR is not set
1060# CONFIG_USB_TEST is not set 1062# CONFIG_USB_TEST is not set
1061
1062#
1063# USB DSL modem support
1064#
1065
1066#
1067# USB Gadget Support
1068#
1069# CONFIG_USB_GADGET is not set 1063# CONFIG_USB_GADGET is not set
1070# CONFIG_MMC is not set 1064# CONFIG_MMC is not set
1071CONFIG_NEW_LEDS=y 1065CONFIG_NEW_LEDS=y
@@ -1120,9 +1114,10 @@ CONFIG_RTC_DRV_M41T80=y
1120# Platform RTC drivers 1114# Platform RTC drivers
1121# 1115#
1122# CONFIG_RTC_DRV_CMOS is not set 1116# CONFIG_RTC_DRV_CMOS is not set
1117# CONFIG_RTC_DRV_DS1511 is not set
1123# CONFIG_RTC_DRV_DS1553 is not set 1118# CONFIG_RTC_DRV_DS1553 is not set
1124# CONFIG_RTC_DRV_STK17TA8 is not set
1125# CONFIG_RTC_DRV_DS1742 is not set 1119# CONFIG_RTC_DRV_DS1742 is not set
1120# CONFIG_RTC_DRV_STK17TA8 is not set
1126# CONFIG_RTC_DRV_M48T86 is not set 1121# CONFIG_RTC_DRV_M48T86 is not set
1127# CONFIG_RTC_DRV_M48T59 is not set 1122# CONFIG_RTC_DRV_M48T59 is not set
1128# CONFIG_RTC_DRV_V3020 is not set 1123# CONFIG_RTC_DRV_V3020 is not set
@@ -1298,9 +1293,6 @@ CONFIG_NLS_ISO8859_2=y
1298# CONFIG_NLS_KOI8_U is not set 1293# CONFIG_NLS_KOI8_U is not set
1299# CONFIG_NLS_UTF8 is not set 1294# CONFIG_NLS_UTF8 is not set
1300# CONFIG_DLM is not set 1295# CONFIG_DLM is not set
1301CONFIG_INSTRUMENTATION=y
1302# CONFIG_PROFILING is not set
1303# CONFIG_MARKERS is not set
1304 1296
1305# 1297#
1306# Kernel hacking 1298# Kernel hacking
@@ -1327,6 +1319,7 @@ CONFIG_DEBUG_USER=y
1327CONFIG_CRYPTO=y 1319CONFIG_CRYPTO=y
1328CONFIG_CRYPTO_ALGAPI=m 1320CONFIG_CRYPTO_ALGAPI=m
1329CONFIG_CRYPTO_BLKCIPHER=m 1321CONFIG_CRYPTO_BLKCIPHER=m
1322# CONFIG_CRYPTO_SEQIV is not set
1330CONFIG_CRYPTO_MANAGER=m 1323CONFIG_CRYPTO_MANAGER=m
1331# CONFIG_CRYPTO_HMAC is not set 1324# CONFIG_CRYPTO_HMAC is not set
1332# CONFIG_CRYPTO_XCBC is not set 1325# CONFIG_CRYPTO_XCBC is not set
@@ -1344,6 +1337,9 @@ CONFIG_CRYPTO_CBC=m
1344CONFIG_CRYPTO_PCBC=m 1337CONFIG_CRYPTO_PCBC=m
1345# CONFIG_CRYPTO_LRW is not set 1338# CONFIG_CRYPTO_LRW is not set
1346# CONFIG_CRYPTO_XTS is not set 1339# CONFIG_CRYPTO_XTS is not set
1340# CONFIG_CRYPTO_CTR is not set
1341# CONFIG_CRYPTO_GCM is not set
1342# CONFIG_CRYPTO_CCM is not set
1347# CONFIG_CRYPTO_CRYPTD is not set 1343# CONFIG_CRYPTO_CRYPTD is not set
1348# CONFIG_CRYPTO_DES is not set 1344# CONFIG_CRYPTO_DES is not set
1349# CONFIG_CRYPTO_FCRYPT is not set 1345# CONFIG_CRYPTO_FCRYPT is not set
@@ -1358,13 +1354,16 @@ CONFIG_CRYPTO_PCBC=m
1358# CONFIG_CRYPTO_KHAZAD is not set 1354# CONFIG_CRYPTO_KHAZAD is not set
1359# CONFIG_CRYPTO_ANUBIS is not set 1355# CONFIG_CRYPTO_ANUBIS is not set
1360# CONFIG_CRYPTO_SEED is not set 1356# CONFIG_CRYPTO_SEED is not set
1357# CONFIG_CRYPTO_SALSA20 is not set
1361# CONFIG_CRYPTO_DEFLATE is not set 1358# CONFIG_CRYPTO_DEFLATE is not set
1362# CONFIG_CRYPTO_MICHAEL_MIC is not set 1359# CONFIG_CRYPTO_MICHAEL_MIC is not set
1363# CONFIG_CRYPTO_CRC32C is not set 1360# CONFIG_CRYPTO_CRC32C is not set
1364# CONFIG_CRYPTO_CAMELLIA is not set 1361# CONFIG_CRYPTO_CAMELLIA is not set
1365# CONFIG_CRYPTO_TEST is not set 1362# CONFIG_CRYPTO_TEST is not set
1366# CONFIG_CRYPTO_AUTHENC is not set 1363# CONFIG_CRYPTO_AUTHENC is not set
1364# CONFIG_CRYPTO_LZO is not set
1367CONFIG_CRYPTO_HW=y 1365CONFIG_CRYPTO_HW=y
1366# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1368 1367
1369# 1368#
1370# Library routines 1369# Library routines
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index d3941a7b0455..b7b0720bc1bb 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -1001,7 +1001,7 @@ static void c_stop(struct seq_file *m, void *v)
1001{ 1001{
1002} 1002}
1003 1003
1004struct seq_operations cpuinfo_op = { 1004const struct seq_operations cpuinfo_op = {
1005 .start = c_start, 1005 .start = c_start,
1006 .next = c_next, 1006 .next = c_next,
1007 .stop = c_stop, 1007 .stop = c_stop,
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index ec76eeaafd45..de6424e9ac02 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -343,7 +343,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
343EXPORT_SYMBOL(clk_set_parent); 343EXPORT_SYMBOL(clk_set_parent);
344 344
345/* establish PCK0..PCK3 parentage and rate */ 345/* establish PCK0..PCK3 parentage and rate */
346static void init_programmable_clock(struct clk *clk) 346static void __init init_programmable_clock(struct clk *clk)
347{ 347{
348 struct clk *parent; 348 struct clk *parent;
349 u32 pckr; 349 u32 pckr;
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 139ceaa35e24..4143828a9684 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -290,7 +290,7 @@ static int davinci_ck_show(struct seq_file *m, void *v)
290 return 0; 290 return 0;
291} 291}
292 292
293static struct seq_operations davinci_ck_op = { 293static const struct seq_operations davinci_ck_op = {
294 .start = davinci_ck_start, 294 .start = davinci_ck_start,
295 .next = davinci_ck_next, 295 .next = davinci_ck_next,
296 .stop = davinci_ck_stop, 296 .stop = davinci_ck_stop,
@@ -302,7 +302,7 @@ static int davinci_ck_open(struct inode *inode, struct file *file)
302 return seq_open(file, &davinci_ck_op); 302 return seq_open(file, &davinci_ck_op);
303} 303}
304 304
305static struct file_operations proc_davinci_ck_operations = { 305static const struct file_operations proc_davinci_ck_operations = {
306 .open = davinci_ck_open, 306 .open = davinci_ck_open,
307 .read = seq_read, 307 .read = seq_read,
308 .llseek = seq_lseek, 308 .llseek = seq_lseek,
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 391b6f4827f6..015a66b3ca8e 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -13,20 +13,20 @@ obj-$(CONFIG_PM) += pm.o sleep.o
13led-y := leds.o 13led-y := leds.o
14 14
15# Specific board support 15# Specific board support
16obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o 16obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o
17obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o 17obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o
18obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 18obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
19obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o 19obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o
20obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o 20obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o
21obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o 21obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o
22obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o 22obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o
23obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o 23obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o
24obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o 24obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o
25obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o 25obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o
26obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o 26obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o
27obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o 27obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o
28obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o 28obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o
29obj-$(CONFIG_MACH_SX1) += board-sx1.o 29obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o
30 30
31ifeq ($(CONFIG_ARCH_OMAP15XX),y) 31ifeq ($(CONFIG_ARCH_OMAP15XX),y)
32# Innovator-1510 FPGA 32# Innovator-1510 FPGA
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index c73ca61e585e..8b102ad59c14 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -135,21 +135,21 @@ static void __init ams_delta_init_irq(void)
135} 135}
136 136
137static struct map_desc ams_delta_io_desc[] __initdata = { 137static struct map_desc ams_delta_io_desc[] __initdata = {
138 // AMS_DELTA_LATCH1 138 /* AMS_DELTA_LATCH1 */
139 { 139 {
140 .virtual = AMS_DELTA_LATCH1_VIRT, 140 .virtual = AMS_DELTA_LATCH1_VIRT,
141 .pfn = __phys_to_pfn(AMS_DELTA_LATCH1_PHYS), 141 .pfn = __phys_to_pfn(AMS_DELTA_LATCH1_PHYS),
142 .length = 0x01000000, 142 .length = 0x01000000,
143 .type = MT_DEVICE 143 .type = MT_DEVICE
144 }, 144 },
145 // AMS_DELTA_LATCH2 145 /* AMS_DELTA_LATCH2 */
146 { 146 {
147 .virtual = AMS_DELTA_LATCH2_VIRT, 147 .virtual = AMS_DELTA_LATCH2_VIRT,
148 .pfn = __phys_to_pfn(AMS_DELTA_LATCH2_PHYS), 148 .pfn = __phys_to_pfn(AMS_DELTA_LATCH2_PHYS),
149 .length = 0x01000000, 149 .length = 0x01000000,
150 .type = MT_DEVICE 150 .type = MT_DEVICE
151 }, 151 },
152 // AMS_DELTA_MODEM 152 /* AMS_DELTA_MODEM */
153 { 153 {
154 .virtual = AMS_DELTA_MODEM_VIRT, 154 .virtual = AMS_DELTA_MODEM_VIRT,
155 .pfn = __phys_to_pfn(AMS_DELTA_MODEM_PHYS), 155 .pfn = __phys_to_pfn(AMS_DELTA_MODEM_PHYS),
@@ -227,6 +227,7 @@ static void __init ams_delta_init(void)
227 omap_board_config = ams_delta_config; 227 omap_board_config = ams_delta_config;
228 omap_board_config_size = ARRAY_SIZE(ams_delta_config); 228 omap_board_config_size = ARRAY_SIZE(ams_delta_config);
229 omap_serial_init(); 229 omap_serial_init();
230 omap_register_i2c_bus(1, 100, NULL, 0);
230 231
231 /* Clear latch2 (NAND, LCD, modem enable) */ 232 /* Clear latch2 (NAND, LCD, modem enable) */
232 ams_delta_latch2_write(~0, 0); 233 ams_delta_latch2_write(~0, 0);
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index f550b19e1ecd..1bdb66638e29 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -30,6 +30,7 @@
30#include <asm/arch/gpio.h> 30#include <asm/arch/gpio.h>
31#include <asm/arch/mux.h> 31#include <asm/arch/mux.h>
32#include <asm/arch/fpga.h> 32#include <asm/arch/fpga.h>
33#include <asm/arch/nand.h>
33#include <asm/arch/keypad.h> 34#include <asm/arch/keypad.h>
34#include <asm/arch/common.h> 35#include <asm/arch/common.h>
35#include <asm/arch/board.h> 36#include <asm/arch/board.h>
@@ -134,7 +135,7 @@ static struct platform_device nor_device = {
134 .resource = &nor_resource, 135 .resource = &nor_resource,
135}; 136};
136 137
137static struct nand_platform_data nand_data = { 138static struct omap_nand_platform_data nand_data = {
138 .options = NAND_SAMSUNG_LP_OPTIONS, 139 .options = NAND_SAMSUNG_LP_OPTIONS,
139}; 140};
140 141
@@ -202,7 +203,7 @@ static struct platform_device *devices[] __initdata = {
202 203
203#define P2_NAND_RB_GPIO_PIN 62 204#define P2_NAND_RB_GPIO_PIN 62
204 205
205static int nand_dev_ready(struct nand_platform_data *data) 206static int nand_dev_ready(struct omap_nand_platform_data *data)
206{ 207{
207 return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN); 208 return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN);
208} 209}
@@ -233,6 +234,7 @@ static void __init omap_fsample_init(void)
233 omap_board_config = fsample_config; 234 omap_board_config = fsample_config;
234 omap_board_config_size = ARRAY_SIZE(fsample_config); 235 omap_board_config_size = ARRAY_SIZE(fsample_config);
235 omap_serial_init(); 236 omap_serial_init();
237 omap_register_i2c_bus(1, 100, NULL, 0);
236} 238}
237 239
238static void __init fsample_init_smc91x(void) 240static void __init fsample_init_smc91x(void)
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 33d01adab1ed..c711bf23f7b4 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -55,33 +55,14 @@ static struct omap_usb_config generic1610_usb_config __initdata = {
55 .hmc_mode = 16, 55 .hmc_mode = 16,
56 .pins[0] = 6, 56 .pins[0] = 6,
57}; 57};
58
59static struct omap_mmc_config generic_mmc_config __initdata = {
60 .mmc [0] = {
61 .enabled = 0,
62 .wire4 = 0,
63 .wp_pin = -1,
64 .power_pin = -1,
65 .switch_pin = -1,
66 },
67 .mmc [1] = {
68 .enabled = 0,
69 .wire4 = 0,
70 .wp_pin = -1,
71 .power_pin = -1,
72 .switch_pin = -1,
73 },
74};
75
76#endif 58#endif
77 59
78static struct omap_uart_config generic_uart_config __initdata = { 60static struct omap_uart_config generic_uart_config __initdata = {
79 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), 61 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
80}; 62};
81 63
82static struct omap_board_config_kernel generic_config[] = { 64static struct omap_board_config_kernel generic_config[] __initdata = {
83 { OMAP_TAG_USB, NULL }, 65 { OMAP_TAG_USB, NULL },
84 { OMAP_TAG_MMC, &generic_mmc_config },
85 { OMAP_TAG_UART, &generic_uart_config }, 66 { OMAP_TAG_UART, &generic_uart_config },
86}; 67};
87 68
@@ -101,6 +82,7 @@ static void __init omap_generic_init(void)
101 omap_board_config = generic_config; 82 omap_board_config = generic_config;
102 omap_board_config_size = ARRAY_SIZE(generic_config); 83 omap_board_config_size = ARRAY_SIZE(generic_config);
103 omap_serial_init(); 84 omap_serial_init();
85 omap_register_i2c_bus(1, 100, NULL, 0);
104} 86}
105 87
106static void __init omap_generic_map_io(void) 88static void __init omap_generic_map_io(void)
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c
new file mode 100644
index 000000000000..6fdc78406b21
--- /dev/null
+++ b/arch/arm/mach-omap1/board-h2-mmc.c
@@ -0,0 +1,110 @@
1/*
2 * linux/arch/arm/mach-omap1/board-h2-mmc.c
3 *
4 * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT
5 * Author: Felipe Balbi <felipe.lima@indt.org.br>
6 *
7 * This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is:
8 * Copyright (C) 2006 Nokia Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <asm/arch/mmc.h>
16#include <asm/arch/gpio.h>
17
18#ifdef CONFIG_MMC_OMAP
19static int slot_cover_open;
20static struct device *mmc_device;
21
22static int h2_mmc_set_power(struct device *dev, int slot, int power_on,
23 int vdd)
24{
25#ifdef CONFIG_MMC_DEBUG
26 dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
27 power_on ? "on" : "off", vdd);
28#endif
29 if (slot != 0) {
30 dev_err(dev, "No such slot %d\n", slot + 1);
31 return -ENODEV;
32 }
33
34 return 0;
35}
36
37static int h2_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode)
38{
39#ifdef CONFIG_MMC_DEBUG
40 dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1,
41 bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull");
42#endif
43 if (slot != 0) {
44 dev_err(dev, "No such slot %d\n", slot + 1);
45 return -ENODEV;
46 }
47
48 return 0;
49}
50
51static int h2_mmc_get_cover_state(struct device *dev, int slot)
52{
53 BUG_ON(slot != 0);
54
55 return slot_cover_open;
56}
57
58void h2_mmc_slot_cover_handler(void *arg, int state)
59{
60 if (mmc_device == NULL)
61 return;
62
63 slot_cover_open = state;
64 omap_mmc_notify_cover_event(mmc_device, 0, state);
65}
66
67static int h2_mmc_late_init(struct device *dev)
68{
69 int ret = 0;
70
71 mmc_device = dev;
72
73 return ret;
74}
75
76static void h2_mmc_cleanup(struct device *dev)
77{
78}
79
80static struct omap_mmc_platform_data h2_mmc_data = {
81 .nr_slots = 1,
82 .switch_slot = NULL,
83 .init = h2_mmc_late_init,
84 .cleanup = h2_mmc_cleanup,
85 .slots[0] = {
86 .set_power = h2_mmc_set_power,
87 .set_bus_mode = h2_mmc_set_bus_mode,
88 .get_ro = NULL,
89 .get_cover_state = h2_mmc_get_cover_state,
90 .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 |
91 MMC_VDD_32_33 | MMC_VDD_33_34,
92 .name = "mmcblk",
93 },
94};
95
96void __init h2_mmc_init(void)
97{
98 omap_set_mmc_info(1, &h2_mmc_data);
99}
100
101#else
102
103void __init h2_mmc_init(void)
104{
105}
106
107void h2_mmc_slot_cover_handler(void *arg, int state)
108{
109}
110#endif
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index bfa04fa25524..070345ee39a5 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -37,8 +37,10 @@
37#include <asm/mach/flash.h> 37#include <asm/mach/flash.h>
38#include <asm/mach/map.h> 38#include <asm/mach/map.h>
39 39
40#include <asm/arch/gpio-switch.h>
40#include <asm/arch/mux.h> 41#include <asm/arch/mux.h>
41#include <asm/arch/tc.h> 42#include <asm/arch/tc.h>
43#include <asm/arch/nand.h>
42#include <asm/arch/irda.h> 44#include <asm/arch/irda.h>
43#include <asm/arch/usb.h> 45#include <asm/arch/usb.h>
44#include <asm/arch/keypad.h> 46#include <asm/arch/keypad.h>
@@ -46,8 +48,6 @@
46#include <asm/arch/mcbsp.h> 48#include <asm/arch/mcbsp.h>
47#include <asm/arch/omap-alsa.h> 49#include <asm/arch/omap-alsa.h>
48 50
49extern int omap_gpio_init(void);
50
51static int h2_keymap[] = { 51static int h2_keymap[] = {
52 KEY(0, 0, KEY_LEFT), 52 KEY(0, 0, KEY_LEFT),
53 KEY(0, 1, KEY_RIGHT), 53 KEY(0, 1, KEY_RIGHT),
@@ -140,8 +140,6 @@ static struct platform_device h2_nor_device = {
140 .resource = &h2_nor_resource, 140 .resource = &h2_nor_resource,
141}; 141};
142 142
143#if 0 /* REVISIT: Enable when nand_platform_data is applied */
144
145static struct mtd_partition h2_nand_partitions[] = { 143static struct mtd_partition h2_nand_partitions[] = {
146#if 0 144#if 0
147 /* REVISIT: enable these partitions if you make NAND BOOT 145 /* REVISIT: enable these partitions if you make NAND BOOT
@@ -179,7 +177,7 @@ static struct mtd_partition h2_nand_partitions[] = {
179}; 177};
180 178
181/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */ 179/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */
182static struct nand_platform_data h2_nand_data = { 180static struct omap_nand_platform_data h2_nand_data = {
183 .options = NAND_SAMSUNG_LP_OPTIONS, 181 .options = NAND_SAMSUNG_LP_OPTIONS,
184 .parts = h2_nand_partitions, 182 .parts = h2_nand_partitions,
185 .nr_parts = ARRAY_SIZE(h2_nand_partitions), 183 .nr_parts = ARRAY_SIZE(h2_nand_partitions),
@@ -198,7 +196,6 @@ static struct platform_device h2_nand_device = {
198 .num_resources = 1, 196 .num_resources = 1,
199 .resource = &h2_nand_resource, 197 .resource = &h2_nand_resource,
200}; 198};
201#endif
202 199
203static struct resource h2_smc91x_resources[] = { 200static struct resource h2_smc91x_resources[] = {
204 [0] = { 201 [0] = {
@@ -311,18 +308,18 @@ static struct omap_mcbsp_reg_cfg mcbsp_regs = {
311 .srgr2 = GSYNC | CLKSP | FSGM | FPER(31), 308 .srgr2 = GSYNC | CLKSP | FSGM | FPER(31),
312 309
313 .pcr0 = CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP, 310 .pcr0 = CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP,
314 //.pcr0 = CLKXP | CLKRP, /* mcbsp: slave */ 311 /*.pcr0 = CLKXP | CLKRP,*/ /* mcbsp: slave */
315}; 312};
316 313
317static struct omap_alsa_codec_config alsa_config = { 314static struct omap_alsa_codec_config alsa_config = {
318 .name = "H2 TSC2101", 315 .name = "H2 TSC2101",
319 .mcbsp_regs_alsa = &mcbsp_regs, 316 .mcbsp_regs_alsa = &mcbsp_regs,
320 .codec_configure_dev = NULL, // tsc2101_configure, 317 .codec_configure_dev = NULL, /* tsc2101_configure, */
321 .codec_set_samplerate = NULL, // tsc2101_set_samplerate, 318 .codec_set_samplerate = NULL, /* tsc2101_set_samplerate, */
322 .codec_clock_setup = NULL, // tsc2101_clock_setup, 319 .codec_clock_setup = NULL, /* tsc2101_clock_setup, */
323 .codec_clock_on = NULL, // tsc2101_clock_on, 320 .codec_clock_on = NULL, /* tsc2101_clock_on, */
324 .codec_clock_off = NULL, // tsc2101_clock_off, 321 .codec_clock_off = NULL, /* tsc2101_clock_off, */
325 .get_default_samplerate = NULL, // tsc2101_get_default_samplerate, 322 .get_default_samplerate = NULL, /* tsc2101_get_default_samplerate, */
326}; 323};
327 324
328static struct platform_device h2_mcbsp1_device = { 325static struct platform_device h2_mcbsp1_device = {
@@ -335,7 +332,7 @@ static struct platform_device h2_mcbsp1_device = {
335 332
336static struct platform_device *h2_devices[] __initdata = { 333static struct platform_device *h2_devices[] __initdata = {
337 &h2_nor_device, 334 &h2_nor_device,
338 //&h2_nand_device, 335 &h2_nand_device,
339 &h2_smc91x_device, 336 &h2_smc91x_device,
340 &h2_irda_device, 337 &h2_irda_device,
341 &h2_kp_device, 338 &h2_kp_device,
@@ -343,22 +340,6 @@ static struct platform_device *h2_devices[] __initdata = {
343 &h2_mcbsp1_device, 340 &h2_mcbsp1_device,
344}; 341};
345 342
346#ifdef CONFIG_I2C_BOARDINFO
347static struct i2c_board_info __initdata h2_i2c_board_info[] = {
348 {
349 I2C_BOARD_INFO("tps65010", 0x48),
350 .type = "tps65010",
351 .irq = OMAP_GPIO_IRQ(58),
352 },
353 /* TODO when driver support is ready:
354 * - isp1301 OTG transceiver
355 * - optional ov9640 camera sensor at 0x30
356 * - pcf9754 for aGPS control
357 * - ... etc
358 */
359};
360#endif
361
362static void __init h2_init_smc91x(void) 343static void __init h2_init_smc91x(void)
363{ 344{
364 if ((omap_request_gpio(0)) < 0) { 345 if ((omap_request_gpio(0)) < 0) {
@@ -367,6 +348,14 @@ static void __init h2_init_smc91x(void)
367 } 348 }
368} 349}
369 350
351static struct i2c_board_info __initdata h2_i2c_board_info[] = {
352 {
353 I2C_BOARD_INFO("isp1301_omap", 0x2d),
354 .type = "isp1301_omap",
355 .irq = OMAP_GPIO_IRQ(2),
356 },
357};
358
370static void __init h2_init_irq(void) 359static void __init h2_init_irq(void)
371{ 360{
372 omap1_init_common_hw(); 361 omap1_init_common_hw();
@@ -380,26 +369,25 @@ static struct omap_usb_config h2_usb_config __initdata = {
380 .otg = 2, 369 .otg = 2,
381 370
382#ifdef CONFIG_USB_GADGET_OMAP 371#ifdef CONFIG_USB_GADGET_OMAP
383 .hmc_mode = 19, // 0:host(off) 1:dev|otg 2:disabled 372 .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
384 // .hmc_mode = 21, // 0:host(off) 1:dev(loopback) 2:host(loopback) 373 /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
385#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 374#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
386 /* needs OTG cable, or NONSTANDARD (B-to-MiniB) */ 375 /* needs OTG cable, or NONSTANDARD (B-to-MiniB) */
387 .hmc_mode = 20, // 1:dev|otg(off) 1:host 2:disabled 376 .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
388#endif 377#endif
389 378
390 .pins[1] = 3, 379 .pins[1] = 3,
391}; 380};
392 381
393static struct omap_mmc_config h2_mmc_config __initdata = { 382static struct omap_mmc_config h2_mmc_config __initdata = {
394 .mmc [0] = { 383 .mmc[0] = {
395 .enabled = 1, 384 .enabled = 1,
396 .wire4 = 1, 385 .wire4 = 1,
397 .wp_pin = OMAP_MPUIO(3),
398 .power_pin = -1, /* tps65010 gpio3 */
399 .switch_pin = OMAP_MPUIO(1),
400 }, 386 },
401}; 387};
402 388
389extern struct omap_mmc_platform_data h2_mmc_data;
390
403static struct omap_uart_config h2_uart_config __initdata = { 391static struct omap_uart_config h2_uart_config __initdata = {
404 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), 392 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
405}; 393};
@@ -409,15 +397,15 @@ static struct omap_lcd_config h2_lcd_config __initdata = {
409}; 397};
410 398
411static struct omap_board_config_kernel h2_config[] __initdata = { 399static struct omap_board_config_kernel h2_config[] __initdata = {
412 { OMAP_TAG_USB, &h2_usb_config }, 400 { OMAP_TAG_USB, &h2_usb_config },
413 { OMAP_TAG_MMC, &h2_mmc_config }, 401 { OMAP_TAG_MMC, &h2_mmc_config },
414 { OMAP_TAG_UART, &h2_uart_config }, 402 { OMAP_TAG_UART, &h2_uart_config },
415 { OMAP_TAG_LCD, &h2_lcd_config }, 403 { OMAP_TAG_LCD, &h2_lcd_config },
416}; 404};
417 405
418#define H2_NAND_RB_GPIO_PIN 62 406#define H2_NAND_RB_GPIO_PIN 62
419 407
420static int h2_nand_dev_ready(struct nand_platform_data *data) 408static int h2_nand_dev_ready(struct omap_nand_platform_data *data)
421{ 409{
422 return omap_get_gpio_datain(H2_NAND_RB_GPIO_PIN); 410 return omap_get_gpio_datain(H2_NAND_RB_GPIO_PIN);
423} 411}
@@ -436,18 +424,16 @@ static void __init h2_init(void)
436 h2_nor_resource.end = h2_nor_resource.start = omap_cs3_phys(); 424 h2_nor_resource.end = h2_nor_resource.start = omap_cs3_phys();
437 h2_nor_resource.end += SZ_32M - 1; 425 h2_nor_resource.end += SZ_32M - 1;
438 426
439#if 0 /* REVISIT: Enable when nand_platform_data is applied */
440 h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS; 427 h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS;
441 h2_nand_resource.end += SZ_4K - 1; 428 h2_nand_resource.end += SZ_4K - 1;
442 if (!(omap_request_gpio(H2_NAND_RB_GPIO_PIN))) 429 if (!(omap_request_gpio(H2_NAND_RB_GPIO_PIN)))
443 h2_nand_data.dev_ready = h2_nand_dev_ready; 430 h2_nand_data.dev_ready = h2_nand_dev_ready;
444#endif
445 431
446 omap_cfg_reg(L3_1610_FLASH_CS2B_OE); 432 omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
447 omap_cfg_reg(M8_1610_FLASH_CS2B_WE); 433 omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
448 434
449 /* MMC: card detect and WP */ 435 /* MMC: card detect and WP */
450 // omap_cfg_reg(U19_ARMIO1); /* CD */ 436 /* omap_cfg_reg(U19_ARMIO1); */ /* CD */
451 omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */ 437 omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */
452 438
453 /* Irda */ 439 /* Irda */
@@ -463,16 +449,9 @@ static void __init h2_init(void)
463 omap_board_config = h2_config; 449 omap_board_config = h2_config;
464 omap_board_config_size = ARRAY_SIZE(h2_config); 450 omap_board_config_size = ARRAY_SIZE(h2_config);
465 omap_serial_init(); 451 omap_serial_init();
466 452 omap_register_i2c_bus(1, 100, h2_i2c_board_info,
467 /* irq for tps65010 chip */ 453 ARRAY_SIZE(h2_i2c_board_info));
468 omap_cfg_reg(W4_GPIO58); 454 h2_mmc_init();
469 if (gpio_request(58, "tps65010") == 0)
470 gpio_direction_input(58);
471
472#ifdef CONFIG_I2C_BOARDINFO
473 i2c_register_board_info(1, h2_i2c_board_info,
474 ARRAY_SIZE(h2_i2c_board_info));
475#endif
476} 455}
477 456
478static void __init h2_map_io(void) 457static void __init h2_map_io(void)
@@ -480,22 +459,6 @@ static void __init h2_map_io(void)
480 omap1_map_common_io(); 459 omap1_map_common_io();
481} 460}
482 461
483#ifdef CONFIG_TPS65010
484static int __init h2_tps_init(void)
485{
486 if (!machine_is_omap_h2())
487 return 0;
488
489 /* gpio3 for SD, gpio4 for VDD_DSP */
490 /* FIXME send power to DSP iff it's configured */
491
492 /* Enable LOW_PWR */
493 tps65010_set_low_pwr(ON);
494 return 0;
495}
496fs_initcall(h2_tps_init);
497#endif
498
499MACHINE_START(OMAP_H2, "TI-H2") 462MACHINE_START(OMAP_H2, "TI-H2")
500 /* Maintainer: Imre Deak <imre.deak@nokia.com> */ 463 /* Maintainer: Imre Deak <imre.deak@nokia.com> */
501 .phys_io = 0xfff00000, 464 .phys_io = 0xfff00000,
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c
new file mode 100644
index 000000000000..66ecc437928f
--- /dev/null
+++ b/arch/arm/mach-omap1/board-h3-mmc.c
@@ -0,0 +1,114 @@
1/*
2 * linux/arch/arm/mach-omap1/board-h3-mmc.c
3 *
4 * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT
5 * Author: Felipe Balbi <felipe.lima@indt.org.br>
6 *
7 * This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is:
8 * Copyright (C) 2006 Nokia Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <asm/arch/mmc.h>
16#include <asm/arch/gpio.h>
17
18#ifdef CONFIG_MMC_OMAP
19static int slot_cover_open;
20static struct device *mmc_device;
21
22static int h3_mmc_set_power(struct device *dev, int slot, int power_on,
23 int vdd)
24{
25#ifdef CONFIG_MMC_DEBUG
26 dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
27 power_on ? "on" : "off", vdd);
28#endif
29 if (slot != 0) {
30 dev_err(dev, "No such slot %d\n", slot + 1);
31 return -ENODEV;
32 }
33
34 return 0;
35}
36
37static int h3_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode)
38{
39 int ret = 0;
40
41#ifdef CONFIG_MMC_DEBUG
42 dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1,
43 bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull");
44#endif
45 if (slot != 0) {
46 dev_err(dev, "No such slot %d\n", slot + 1);
47 return -ENODEV;
48 }
49
50 /* Treated on upper level */
51
52 return bus_mode;
53}
54
55static int h3_mmc_get_cover_state(struct device *dev, int slot)
56{
57 BUG_ON(slot != 0);
58
59 return slot_cover_open;
60}
61
62void h3_mmc_slot_cover_handler(void *arg, int state)
63{
64 if (mmc_device == NULL)
65 return;
66
67 slot_cover_open = state;
68 omap_mmc_notify_cover_event(mmc_device, 0, state);
69}
70
71static int h3_mmc_late_init(struct device *dev)
72{
73 int ret = 0;
74
75 mmc_device = dev;
76
77 return ret;
78}
79
80static void h3_mmc_cleanup(struct device *dev)
81{
82}
83
84static struct omap_mmc_platform_data h3_mmc_data = {
85 .nr_slots = 1,
86 .switch_slot = NULL,
87 .init = h3_mmc_late_init,
88 .cleanup = h3_mmc_cleanup,
89 .slots[0] = {
90 .set_power = h3_mmc_set_power,
91 .set_bus_mode = h3_mmc_set_bus_mode,
92 .get_ro = NULL,
93 .get_cover_state = h3_mmc_get_cover_state,
94 .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 |
95 MMC_VDD_32_33 | MMC_VDD_33_34,
96 .name = "mmcblk",
97 },
98};
99
100void __init h3_mmc_init(void)
101{
102 omap_set_mmc_info(1, &h3_mmc_data);
103}
104
105#else
106
107void __init h3_mmc_init(void)
108{
109}
110
111void h3_mmc_slot_cover_handler(void *arg, int state)
112{
113}
114#endif
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 056519860565..6fc516855a8c 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -42,6 +42,7 @@
42#include <asm/arch/irqs.h> 42#include <asm/arch/irqs.h>
43#include <asm/arch/mux.h> 43#include <asm/arch/mux.h>
44#include <asm/arch/tc.h> 44#include <asm/arch/tc.h>
45#include <asm/arch/nand.h>
45#include <asm/arch/irda.h> 46#include <asm/arch/irda.h>
46#include <asm/arch/usb.h> 47#include <asm/arch/usb.h>
47#include <asm/arch/keypad.h> 48#include <asm/arch/keypad.h>
@@ -50,8 +51,6 @@
50#include <asm/arch/mcbsp.h> 51#include <asm/arch/mcbsp.h>
51#include <asm/arch/omap-alsa.h> 52#include <asm/arch/omap-alsa.h>
52 53
53extern int omap_gpio_init(void);
54
55static int h3_keymap[] = { 54static int h3_keymap[] = {
56 KEY(0, 0, KEY_LEFT), 55 KEY(0, 0, KEY_LEFT),
57 KEY(0, 1, KEY_RIGHT), 56 KEY(0, 1, KEY_RIGHT),
@@ -179,7 +178,7 @@ static struct mtd_partition nand_partitions[] = {
179}; 178};
180 179
181/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */ 180/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */
182static struct nand_platform_data nand_data = { 181static struct omap_nand_platform_data nand_data = {
183 .options = NAND_SAMSUNG_LP_OPTIONS, 182 .options = NAND_SAMSUNG_LP_OPTIONS,
184 .parts = nand_partitions, 183 .parts = nand_partitions,
185 .nr_parts = ARRAY_SIZE(nand_partitions), 184 .nr_parts = ARRAY_SIZE(nand_partitions),
@@ -387,18 +386,18 @@ static struct omap_mcbsp_reg_cfg mcbsp_regs = {
387 .srgr2 = GSYNC | CLKSP | FSGM | FPER(31), 386 .srgr2 = GSYNC | CLKSP | FSGM | FPER(31),
388 387
389 .pcr0 = CLKRM | SCLKME | FSXP | FSRP | CLKXP | CLKRP, 388 .pcr0 = CLKRM | SCLKME | FSXP | FSRP | CLKXP | CLKRP,
390 //.pcr0 = CLKXP | CLKRP, /* mcbsp: slave */ 389 /*.pcr0 = CLKXP | CLKRP,*/ /* mcbsp: slave */
391}; 390};
392 391
393static struct omap_alsa_codec_config alsa_config = { 392static struct omap_alsa_codec_config alsa_config = {
394 .name = "H3 TSC2101", 393 .name = "H3 TSC2101",
395 .mcbsp_regs_alsa = &mcbsp_regs, 394 .mcbsp_regs_alsa = &mcbsp_regs,
396 .codec_configure_dev = NULL, // tsc2101_configure, 395 .codec_configure_dev = NULL, /* tsc2101_configure, */
397 .codec_set_samplerate = NULL, // tsc2101_set_samplerate, 396 .codec_set_samplerate = NULL, /* tsc2101_set_samplerate, */
398 .codec_clock_setup = NULL, // tsc2101_clock_setup, 397 .codec_clock_setup = NULL, /* tsc2101_clock_setup, */
399 .codec_clock_on = NULL, // tsc2101_clock_on, 398 .codec_clock_on = NULL, /* tsc2101_clock_on, */
400 .codec_clock_off = NULL, // tsc2101_clock_off, 399 .codec_clock_off = NULL, /* tsc2101_clock_off, */
401 .get_default_samplerate = NULL, // tsc2101_get_default_samplerate, 400 .get_default_samplerate = NULL, /* tsc2101_get_default_samplerate, */
402}; 401};
403 402
404static struct platform_device h3_mcbsp1_device = { 403static struct platform_device h3_mcbsp1_device = {
@@ -436,12 +435,13 @@ static struct omap_usb_config h3_usb_config __initdata = {
436 435
437static struct omap_mmc_config h3_mmc_config __initdata = { 436static struct omap_mmc_config h3_mmc_config __initdata = {
438 .mmc[0] = { 437 .mmc[0] = {
439 .enabled = 1, 438 .enabled = 1,
440 .power_pin = -1, /* tps65010 GPIO4 */ 439 .wire4 = 1,
441 .switch_pin = OMAP_MPUIO(1), 440 },
442 },
443}; 441};
444 442
443extern struct omap_mmc_platform_data h3_mmc_data;
444
445static struct omap_uart_config h3_uart_config __initdata = { 445static struct omap_uart_config h3_uart_config __initdata = {
446 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), 446 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
447}; 447};
@@ -450,29 +450,28 @@ static struct omap_lcd_config h3_lcd_config __initdata = {
450 .ctrl_name = "internal", 450 .ctrl_name = "internal",
451}; 451};
452 452
453static struct omap_board_config_kernel h3_config[] = { 453static struct omap_board_config_kernel h3_config[] __initdata = {
454 { OMAP_TAG_USB, &h3_usb_config }, 454 { OMAP_TAG_USB, &h3_usb_config },
455 { OMAP_TAG_MMC, &h3_mmc_config }, 455 { OMAP_TAG_MMC, &h3_mmc_config },
456 { OMAP_TAG_UART, &h3_uart_config }, 456 { OMAP_TAG_UART, &h3_uart_config },
457 { OMAP_TAG_LCD, &h3_lcd_config }, 457 { OMAP_TAG_LCD, &h3_lcd_config },
458}; 458};
459 459
460static struct i2c_board_info __initdata h3_i2c_board_info[] = { 460static struct omap_gpio_switch h3_gpio_switches[] __initdata = {
461 { 461 {
462 I2C_BOARD_INFO("tps65010", 0x48), 462 .name = "mmc_slot",
463 .type = "tps65013", 463 .gpio = OMAP_MPUIO(1),
464 /* .irq = OMAP_GPIO_IRQ(??), */ 464 .type = OMAP_GPIO_SWITCH_TYPE_COVER,
465 .debounce_rising = 100,
466 .debounce_falling = 0,
467 .notify = h3_mmc_slot_cover_handler,
468 .notify_data = NULL,
465 }, 469 },
466 /* TODO when driver support is ready:
467 * - isp1301 OTG transceiver
468 * - optional ov9640 camera sensor at 0x30
469 * - ...
470 */
471}; 470};
472 471
473#define H3_NAND_RB_GPIO_PIN 10 472#define H3_NAND_RB_GPIO_PIN 10
474 473
475static int nand_dev_ready(struct nand_platform_data *data) 474static int nand_dev_ready(struct omap_nand_platform_data *data)
476{ 475{
477 return omap_get_gpio_datain(H3_NAND_RB_GPIO_PIN); 476 return omap_get_gpio_datain(H3_NAND_RB_GPIO_PIN);
478} 477}
@@ -500,13 +499,14 @@ static void __init h3_init(void)
500 omap_cfg_reg(V2_1710_GPIO10); 499 omap_cfg_reg(V2_1710_GPIO10);
501 500
502 platform_add_devices(devices, ARRAY_SIZE(devices)); 501 platform_add_devices(devices, ARRAY_SIZE(devices));
502 spi_register_board_info(h3_spi_board_info,
503 ARRAY_SIZE(h3_spi_board_info));
503 omap_board_config = h3_config; 504 omap_board_config = h3_config;
504 omap_board_config_size = ARRAY_SIZE(h3_config); 505 omap_board_config_size = ARRAY_SIZE(h3_config);
505 omap_serial_init(); 506 omap_serial_init();
506 507 omap_register_i2c_bus(1, 100, h3_i2c_board_info,
507 /* FIXME setup irq for tps65013 chip */ 508 ARRAY_SIZE(h3_i2c_board_info));
508 i2c_register_board_info(1, h3_i2c_board_info, 509 h3_mmc_init();
509 ARRAY_SIZE(h3_i2c_board_info));
510} 510}
511 511
512static void __init h3_init_smc91x(void) 512static void __init h3_init_smc91x(void)
@@ -531,23 +531,6 @@ static void __init h3_map_io(void)
531 omap1_map_common_io(); 531 omap1_map_common_io();
532} 532}
533 533
534#ifdef CONFIG_TPS65010
535static int __init h3_tps_init(void)
536{
537 if (!machine_is_omap_h3())
538 return 0;
539
540 /* gpio4 for SD, gpio3 for VDD_DSP */
541 /* FIXME send power to DSP iff it's configured */
542
543 /* Enable LOW_PWR */
544 tps65013_set_low_pwr(ON);
545
546 return 0;
547}
548fs_initcall(h3_tps_init);
549#endif
550
551MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") 534MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
552 /* Maintainer: Texas Instruments, Inc. */ 535 /* Maintainer: Texas Instruments, Inc. */
553 .phys_io = 0xfff00000, 536 .phys_io = 0xfff00000,
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 7d2d8af155a3..4b8ae3ee0d05 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -134,12 +134,12 @@ static struct omap_mcbsp_reg_cfg mcbsp_regs = {
134static struct omap_alsa_codec_config alsa_config = { 134static struct omap_alsa_codec_config alsa_config = {
135 .name = "OMAP Innovator AIC23", 135 .name = "OMAP Innovator AIC23",
136 .mcbsp_regs_alsa = &mcbsp_regs, 136 .mcbsp_regs_alsa = &mcbsp_regs,
137 .codec_configure_dev = NULL, // aic23_configure, 137 .codec_configure_dev = NULL, /* aic23_configure, */
138 .codec_set_samplerate = NULL, // aic23_set_samplerate, 138 .codec_set_samplerate = NULL, /* aic23_set_samplerate, */
139 .codec_clock_setup = NULL, // aic23_clock_setup, 139 .codec_clock_setup = NULL, /* aic23_clock_setup, */
140 .codec_clock_on = NULL, // aic23_clock_on, 140 .codec_clock_on = NULL, /* aic23_clock_on, */
141 .codec_clock_off = NULL, // aic23_clock_off, 141 .codec_clock_off = NULL, /* aic23_clock_off, */
142 .get_default_samplerate = NULL, // aic23_get_default_samplerate, 142 .get_default_samplerate = NULL, /* aic23_get_default_samplerate, */
143}; 143};
144 144
145static struct platform_device innovator_mcbsp1_device = { 145static struct platform_device innovator_mcbsp1_device = {
@@ -345,11 +345,11 @@ static struct omap_usb_config h2_usb_config __initdata = {
345 .otg = 2, 345 .otg = 2,
346 346
347#ifdef CONFIG_USB_GADGET_OMAP 347#ifdef CONFIG_USB_GADGET_OMAP
348 .hmc_mode = 19, // 0:host(off) 1:dev|otg 2:disabled 348 .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
349 // .hmc_mode = 21, // 0:host(off) 1:dev(loopback) 2:host(loopback) 349 /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
350#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 350#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
351 /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */ 351 /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
352 .hmc_mode = 20, // 1:dev|otg(off) 1:host 2:disabled 352 .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
353#endif 353#endif
354 354
355 .pins[1] = 3, 355 .pins[1] = 3,
@@ -411,6 +411,7 @@ static void __init innovator_init(void)
411 omap_board_config = innovator_config; 411 omap_board_config = innovator_config;
412 omap_board_config_size = ARRAY_SIZE(innovator_config); 412 omap_board_config_size = ARRAY_SIZE(innovator_config);
413 omap_serial_init(); 413 omap_serial_init();
414 omap_register_i2c_bus(1, 100, NULL, 0);
414} 415}
415 416
416static void __init innovator_map_io(void) 417static void __init innovator_map_io(void)
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index e2c8ffd75cff..bcb984f2300f 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -189,7 +189,7 @@ static struct omap_mmc_config nokia770_mmc_config __initdata = {
189 }, 189 },
190}; 190};
191 191
192static struct omap_board_config_kernel nokia770_config[] = { 192static struct omap_board_config_kernel nokia770_config[] __initdata = {
193 { OMAP_TAG_USB, NULL }, 193 { OMAP_TAG_USB, NULL },
194 { OMAP_TAG_MMC, &nokia770_mmc_config }, 194 { OMAP_TAG_MMC, &nokia770_mmc_config },
195}; 195};
@@ -330,6 +330,7 @@ static void __init omap_nokia770_init(void)
330 omap_board_config_size = ARRAY_SIZE(nokia770_config); 330 omap_board_config_size = ARRAY_SIZE(nokia770_config);
331 omap_gpio_init(); 331 omap_gpio_init();
332 omap_serial_init(); 332 omap_serial_init();
333 omap_register_i2c_bus(1, 100, NULL, 0);
333 omap_dsp_init(); 334 omap_dsp_init();
334 ads7846_dev_init(); 335 ads7846_dev_init();
335 mipid_dev_init(); 336 mipid_dev_init();
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 84333440008c..5279e35a8aec 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -160,12 +160,12 @@ static struct omap_mcbsp_reg_cfg mcbsp_regs = {
160static struct omap_alsa_codec_config alsa_config = { 160static struct omap_alsa_codec_config alsa_config = {
161 .name = "OSK AIC23", 161 .name = "OSK AIC23",
162 .mcbsp_regs_alsa = &mcbsp_regs, 162 .mcbsp_regs_alsa = &mcbsp_regs,
163 .codec_configure_dev = NULL, // aic23_configure, 163 .codec_configure_dev = NULL, /* aic23_configure, */
164 .codec_set_samplerate = NULL, // aic23_set_samplerate, 164 .codec_set_samplerate = NULL, /* aic23_set_samplerate, */
165 .codec_clock_setup = NULL, // aic23_clock_setup, 165 .codec_clock_setup = NULL, /* aic23_clock_setup, */
166 .codec_clock_on = NULL, // aic23_clock_on, 166 .codec_clock_on = NULL, /* aic23_clock_on, */
167 .codec_clock_off = NULL, // aic23_clock_off, 167 .codec_clock_off = NULL, /* aic23_clock_off, */
168 .get_default_samplerate = NULL, // aic23_get_default_samplerate, 168 .get_default_samplerate = NULL, /* aic23_get_default_samplerate, */
169}; 169};
170 170
171static struct platform_device osk5912_mcbsp1_device = { 171static struct platform_device osk5912_mcbsp1_device = {
@@ -253,7 +253,7 @@ static struct omap_lcd_config osk_lcd_config __initdata = {
253}; 253};
254#endif 254#endif
255 255
256static struct omap_board_config_kernel osk_config[] = { 256static struct omap_board_config_kernel osk_config[] __initdata = {
257 { OMAP_TAG_USB, &osk_usb_config }, 257 { OMAP_TAG_USB, &osk_usb_config },
258 { OMAP_TAG_UART, &osk_uart_config }, 258 { OMAP_TAG_UART, &osk_uart_config },
259#ifdef CONFIG_OMAP_OSK_MISTRAL 259#ifdef CONFIG_OMAP_OSK_MISTRAL
@@ -392,7 +392,7 @@ static void __init osk_mistral_init(void)
392 omap_cfg_reg(W13_1610_CCP_CLKM); 392 omap_cfg_reg(W13_1610_CCP_CLKM);
393 omap_cfg_reg(Y12_1610_CCP_CLKP); 393 omap_cfg_reg(Y12_1610_CCP_CLKP);
394 /* CCP_DATAM CONFLICTS WITH UART1.TX (and serial console) */ 394 /* CCP_DATAM CONFLICTS WITH UART1.TX (and serial console) */
395 // omap_cfg_reg(Y14_1610_CCP_DATAM); 395 /* omap_cfg_reg(Y14_1610_CCP_DATAM); */
396 omap_cfg_reg(W14_1610_CCP_DATAP); 396 omap_cfg_reg(W14_1610_CCP_DATAP);
397 397
398 /* CAM_PWDN */ 398 /* CAM_PWDN */
@@ -404,8 +404,8 @@ static void __init osk_mistral_init(void)
404 pr_debug("OSK+Mistral: CAM_PWDN is awol\n"); 404 pr_debug("OSK+Mistral: CAM_PWDN is awol\n");
405 405
406 406
407 // omap_cfg_reg(P19_1610_GPIO6); // BUSY 407 /* omap_cfg_reg(P19_1610_GPIO6); */ /* BUSY */
408 omap_cfg_reg(P20_1610_GPIO4); // PENIRQ 408 omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */
409 set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING); 409 set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING);
410 spi_register_board_info(mistral_boardinfo, 410 spi_register_board_info(mistral_boardinfo,
411 ARRAY_SIZE(mistral_boardinfo)); 411 ARRAY_SIZE(mistral_boardinfo));
@@ -473,10 +473,9 @@ static void __init osk_init(void)
473 if (gpio_request(OMAP_MPUIO(1), "tps65010") == 0) 473 if (gpio_request(OMAP_MPUIO(1), "tps65010") == 0)
474 gpio_direction_input(OMAP_MPUIO(1)); 474 gpio_direction_input(OMAP_MPUIO(1));
475 475
476 i2c_register_board_info(1, osk_i2c_board_info,
477 ARRAY_SIZE(osk_i2c_board_info));
478
479 omap_serial_init(); 476 omap_serial_init();
477 omap_register_i2c_bus(1, 400, osk_i2c_board_info,
478 ARRAY_SIZE(osk_i2c_board_info));
480 osk_mistral_init(); 479 osk_mistral_init();
481} 480}
482 481
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 2f9d00a00135..ca1a4bf78a10 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -10,6 +10,8 @@
10 * Maintainers : http://palmtelinux.sf.net 10 * Maintainers : http://palmtelinux.sf.net
11 * palmtelinux-developpers@lists.sf.net 11 * palmtelinux-developpers@lists.sf.net
12 * 12 *
13 * Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org>
14 *
13 * This program is free software; you can redistribute it and/or modify 15 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as 16 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
@@ -24,8 +26,8 @@
24#include <linux/spi/spi.h> 26#include <linux/spi/spi.h>
25#include <linux/spi/tsc2102.h> 27#include <linux/spi/tsc2102.h>
26#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/apm-emulation.h>
27 30
28#include <asm/apm.h>
29#include <asm/hardware.h> 31#include <asm/hardware.h>
30#include <asm/mach-types.h> 32#include <asm/mach-types.h>
31#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
@@ -51,11 +53,11 @@ static void __init omap_palmte_init_irq(void)
51 omap_gpio_init(); 53 omap_gpio_init();
52} 54}
53 55
54static int palmte_keymap[] = { 56static const int palmte_keymap[] = {
55 KEY(0, 0, KEY_F1), 57 KEY(0, 0, KEY_F1), /* Calendar */
56 KEY(0, 1, KEY_F2), 58 KEY(0, 1, KEY_F2), /* Contacts */
57 KEY(0, 2, KEY_F3), 59 KEY(0, 2, KEY_F3), /* Tasks List */
58 KEY(0, 3, KEY_F4), 60 KEY(0, 3, KEY_F4), /* Note Pad */
59 KEY(0, 4, KEY_POWER), 61 KEY(0, 4, KEY_POWER),
60 KEY(1, 0, KEY_LEFT), 62 KEY(1, 0, KEY_LEFT),
61 KEY(1, 1, KEY_DOWN), 63 KEY(1, 1, KEY_DOWN),
@@ -68,7 +70,7 @@ static int palmte_keymap[] = {
68static struct omap_kp_platform_data palmte_kp_data = { 70static struct omap_kp_platform_data palmte_kp_data = {
69 .rows = 8, 71 .rows = 8,
70 .cols = 8, 72 .cols = 8,
71 .keymap = palmte_keymap, 73 .keymap = (int *) palmte_keymap,
72 .rep = 1, 74 .rep = 1,
73 .delay = 12, 75 .delay = 12,
74}; 76};
@@ -180,7 +182,7 @@ static struct platform_device palmte_irda_device = {
180 .resource = palmte_irda_resources, 182 .resource = palmte_irda_resources,
181}; 183};
182 184
183static struct platform_device *devices[] __initdata = { 185static struct platform_device *palmte_devices[] __initdata = {
184 &palmte_rom_device, 186 &palmte_rom_device,
185 &palmte_kp_device, 187 &palmte_kp_device,
186 &palmte_lcd_device, 188 &palmte_lcd_device,
@@ -273,7 +275,7 @@ static void palmte_get_power_status(struct apm_power_info *info, int *battery)
273 info->time = 0; 275 info->time = 0;
274 } else { 276 } else {
275 while (hi > lo + 1) { 277 while (hi > lo + 1) {
276 mid = (hi + lo) >> 2; 278 mid = (hi + lo) >> 1;
277 if (batt <= palmte_battery_sample[mid]) 279 if (batt <= palmte_battery_sample[mid])
278 lo = mid; 280 lo = mid;
279 else 281 else
@@ -321,7 +323,7 @@ static struct tsc2102_config palmte_tsc2102_config = {
321 .alsa_config = &palmte_alsa_config, 323 .alsa_config = &palmte_alsa_config,
322}; 324};
323 325
324static struct omap_board_config_kernel palmte_config[] = { 326static struct omap_board_config_kernel palmte_config[] __initdata = {
325 { OMAP_TAG_USB, &palmte_usb_config }, 327 { OMAP_TAG_USB, &palmte_usb_config },
326 { OMAP_TAG_MMC, &palmte_mmc_config }, 328 { OMAP_TAG_MMC, &palmte_mmc_config },
327 { OMAP_TAG_LCD, &palmte_lcd_config }, 329 { OMAP_TAG_LCD, &palmte_lcd_config },
@@ -339,74 +341,34 @@ static struct spi_board_info palmte_spi_info[] __initdata = {
339 }, 341 },
340}; 342};
341 343
342/* Periodically check for changes on important input pins */ 344static void palmte_headphones_detect(void *data, int state)
343struct timer_list palmte_pin_timer; 345{
344int prev_power, prev_headphones; 346 if (state) {
345
346static void palmte_pin_handler(unsigned long data) {
347 int power, headphones;
348
349 power = !omap_get_gpio_datain(PALMTE_DC_GPIO);
350 headphones = omap_get_gpio_datain(PALMTE_HEADPHONES_GPIO);
351
352 if (power && !prev_power)
353 printk(KERN_INFO "PM: cable connected\n");
354 else if (!power && prev_power)
355 printk(KERN_INFO "PM: cable disconnected\n");
356
357 if (headphones && !prev_headphones) {
358 /* Headphones connected, disable speaker */ 347 /* Headphones connected, disable speaker */
359 omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 0); 348 omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 0);
360 printk(KERN_INFO "PM: speaker off\n"); 349 printk(KERN_INFO "PM: speaker off\n");
361 } else if (!headphones && prev_headphones) { 350 } else {
362 /* Headphones unplugged, re-enable speaker */ 351 /* Headphones unplugged, re-enable speaker */
363 omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 1); 352 omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 1);
364 printk(KERN_INFO "PM: speaker on\n"); 353 printk(KERN_INFO "PM: speaker on\n");
365 } 354 }
366
367 prev_power = power;
368 prev_headphones = headphones;
369 mod_timer(&palmte_pin_timer, jiffies + msecs_to_jiffies(500));
370} 355}
371 356
372static void __init palmte_gpio_setup(void) 357static void __init palmte_misc_gpio_setup(void)
373{ 358{
374 /* Set TSC2102 PINTDAV pin as input */ 359 /* Set TSC2102 PINTDAV pin as input (used by TSC2102 driver) */
375 if (omap_request_gpio(PALMTE_PINTDAV_GPIO)) { 360 if (omap_request_gpio(PALMTE_PINTDAV_GPIO)) {
376 printk(KERN_ERR "Could not reserve PINTDAV GPIO!\n"); 361 printk(KERN_ERR "Could not reserve PINTDAV GPIO!\n");
377 return; 362 return;
378 } 363 }
379 omap_set_gpio_direction(PALMTE_PINTDAV_GPIO, 1); 364 omap_set_gpio_direction(PALMTE_PINTDAV_GPIO, 1);
380 365
381 /* Monitor cable-connected signals */ 366 /* Set USB-or-DC-IN pin as input (unused) */
382 if (omap_request_gpio(PALMTE_DC_GPIO) || 367 if (omap_request_gpio(PALMTE_USB_OR_DC_GPIO)) {
383 omap_request_gpio(PALMTE_USB_OR_DC_GPIO) ||
384 omap_request_gpio(PALMTE_USBDETECT_GPIO)) {
385 printk(KERN_ERR "Could not reserve cable signal GPIO!\n"); 368 printk(KERN_ERR "Could not reserve cable signal GPIO!\n");
386 return; 369 return;
387 } 370 }
388 omap_set_gpio_direction(PALMTE_DC_GPIO, 1);
389 omap_set_gpio_direction(PALMTE_USB_OR_DC_GPIO, 1); 371 omap_set_gpio_direction(PALMTE_USB_OR_DC_GPIO, 1);
390 omap_set_gpio_direction(PALMTE_USBDETECT_GPIO, 1);
391
392 /* Set speaker-enable pin as output */
393 if (omap_request_gpio(PALMTE_SPEAKER_GPIO)) {
394 printk(KERN_ERR "Could not reserve speaker GPIO!\n");
395 return;
396 }
397 omap_set_gpio_direction(PALMTE_SPEAKER_GPIO, 0);
398
399 /* Monitor the headphones-connected signal */
400 if (omap_request_gpio(PALMTE_HEADPHONES_GPIO)) {
401 printk(KERN_ERR "Could not reserve headphones signal GPIO!\n");
402 return;
403 }
404 omap_set_gpio_direction(PALMTE_HEADPHONES_GPIO, 1);
405
406 prev_power = omap_get_gpio_datain(PALMTE_DC_GPIO);
407 prev_headphones = !omap_get_gpio_datain(PALMTE_HEADPHONES_GPIO);
408 setup_timer(&palmte_pin_timer, palmte_pin_handler, 0);
409 palmte_pin_handler(0);
410} 372}
411 373
412static void __init omap_palmte_init(void) 374static void __init omap_palmte_init(void)
@@ -414,12 +376,12 @@ static void __init omap_palmte_init(void)
414 omap_board_config = palmte_config; 376 omap_board_config = palmte_config;
415 omap_board_config_size = ARRAY_SIZE(palmte_config); 377 omap_board_config_size = ARRAY_SIZE(palmte_config);
416 378
417 platform_add_devices(devices, ARRAY_SIZE(devices)); 379 platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices));
418 380
419 spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); 381 spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
420 382 palmte_misc_gpio_setup();
421 omap_serial_init(); 383 omap_serial_init();
422 palmte_gpio_setup(); 384 omap_register_i2c_bus(1, 100, NULL, 0);
423} 385}
424 386
425static void __init omap_palmte_map_io(void) 387static void __init omap_palmte_map_io(void)
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index ed7094a70064..2a033689f9f4 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -144,12 +144,12 @@ static struct omap_mcbsp_reg_cfg mcbsp_regs = {
144static struct omap_alsa_codec_config alsa_config = { 144static struct omap_alsa_codec_config alsa_config = {
145 .name = "PalmTT AIC23", 145 .name = "PalmTT AIC23",
146 .mcbsp_regs_alsa = &mcbsp_regs, 146 .mcbsp_regs_alsa = &mcbsp_regs,
147 .codec_configure_dev = NULL, // aic23_configure, 147 .codec_configure_dev = NULL, /* aic23_configure, */
148 .codec_set_samplerate = NULL, // aic23_set_samplerate, 148 .codec_set_samplerate = NULL, /* aic23_set_samplerate, */
149 .codec_clock_setup = NULL, // aic23_clock_setup, 149 .codec_clock_setup = NULL, /* aic23_clock_setup, */
150 .codec_clock_on = NULL, // aic23_clock_on, 150 .codec_clock_on = NULL, /* aic23_clock_on, */
151 .codec_clock_off = NULL, // aic23_clock_off, 151 .codec_clock_off = NULL, /* aic23_clock_off, */
152 .get_default_samplerate = NULL, // aic23_get_default_samplerate, 152 .get_default_samplerate = NULL, /* aic23_get_default_samplerate, */
153}; 153};
154 154
155static struct platform_device palmtt_mcbsp1_device = { 155static struct platform_device palmtt_mcbsp1_device = {
@@ -312,7 +312,7 @@ static struct omap_uart_config palmtt_uart_config __initdata = {
312 .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), 312 .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2),
313}; 313};
314 314
315static struct omap_board_config_kernel palmtt_config[] = { 315static struct omap_board_config_kernel palmtt_config[] __initdata = {
316 { OMAP_TAG_USB, &palmtt_usb_config }, 316 { OMAP_TAG_USB, &palmtt_usb_config },
317 { OMAP_TAG_LCD, &palmtt_lcd_config }, 317 { OMAP_TAG_LCD, &palmtt_lcd_config },
318 { OMAP_TAG_UART, &palmtt_uart_config }, 318 { OMAP_TAG_UART, &palmtt_uart_config },
@@ -338,6 +338,7 @@ static void __init omap_palmtt_init(void)
338 338
339 spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); 339 spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
340 omap_serial_init(); 340 omap_serial_init();
341 omap_register_i2c_bus(1, 100, NULL, 0);
341} 342}
342 343
343static void __init omap_palmtt_map_io(void) 344static void __init omap_palmtt_map_io(void)
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index a9a0f6610c3d..156510777ffe 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -285,7 +285,7 @@ static struct omap_uart_config palmz71_uart_config __initdata = {
285 .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), 285 .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2),
286}; 286};
287 287
288static struct omap_board_config_kernel palmz71_config[] = { 288static struct omap_board_config_kernel palmz71_config[] __initdata = {
289 {OMAP_TAG_USB, &palmz71_usb_config}, 289 {OMAP_TAG_USB, &palmz71_usb_config},
290 {OMAP_TAG_MMC, &palmz71_mmc_config}, 290 {OMAP_TAG_MMC, &palmz71_mmc_config},
291 {OMAP_TAG_LCD, &palmz71_lcd_config}, 291 {OMAP_TAG_LCD, &palmz71_lcd_config},
@@ -363,6 +363,7 @@ omap_palmz71_init(void)
363 spi_register_board_info(palmz71_boardinfo, 363 spi_register_board_info(palmz71_boardinfo,
364 ARRAY_SIZE(palmz71_boardinfo)); 364 ARRAY_SIZE(palmz71_boardinfo));
365 omap_serial_init(); 365 omap_serial_init();
366 omap_register_i2c_bus(1, 100, NULL, 0);
366 palmz71_gpio_setup(0); 367 palmz71_gpio_setup(0);
367} 368}
368 369
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 534dcfb9d263..94bc0745ab2c 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -30,6 +30,7 @@
30#include <asm/arch/gpio.h> 30#include <asm/arch/gpio.h>
31#include <asm/arch/mux.h> 31#include <asm/arch/mux.h>
32#include <asm/arch/fpga.h> 32#include <asm/arch/fpga.h>
33#include <asm/arch/nand.h>
33#include <asm/arch/keypad.h> 34#include <asm/arch/keypad.h>
34#include <asm/arch/common.h> 35#include <asm/arch/common.h>
35#include <asm/arch/board.h> 36#include <asm/arch/board.h>
@@ -133,7 +134,7 @@ static struct platform_device nor_device = {
133 .resource = &nor_resource, 134 .resource = &nor_resource,
134}; 135};
135 136
136static struct nand_platform_data nand_data = { 137static struct omap_nand_platform_data nand_data = {
137 .options = NAND_SAMSUNG_LP_OPTIONS, 138 .options = NAND_SAMSUNG_LP_OPTIONS,
138}; 139};
139 140
@@ -202,7 +203,7 @@ static struct platform_device *devices[] __initdata = {
202 203
203#define P2_NAND_RB_GPIO_PIN 62 204#define P2_NAND_RB_GPIO_PIN 62
204 205
205static int nand_dev_ready(struct nand_platform_data *data) 206static int nand_dev_ready(struct omap_nand_platform_data *data)
206{ 207{
207 return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN); 208 return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN);
208} 209}
@@ -215,7 +216,7 @@ static struct omap_lcd_config perseus2_lcd_config __initdata = {
215 .ctrl_name = "internal", 216 .ctrl_name = "internal",
216}; 217};
217 218
218static struct omap_board_config_kernel perseus2_config[] = { 219static struct omap_board_config_kernel perseus2_config[] __initdata = {
219 { OMAP_TAG_UART, &perseus2_uart_config }, 220 { OMAP_TAG_UART, &perseus2_uart_config },
220 { OMAP_TAG_LCD, &perseus2_lcd_config }, 221 { OMAP_TAG_LCD, &perseus2_lcd_config },
221}; 222};
@@ -233,6 +234,7 @@ static void __init omap_perseus2_init(void)
233 omap_board_config = perseus2_config; 234 omap_board_config = perseus2_config;
234 omap_board_config_size = ARRAY_SIZE(perseus2_config); 235 omap_board_config_size = ARRAY_SIZE(perseus2_config);
235 omap_serial_init(); 236 omap_serial_init();
237 omap_register_i2c_bus(1, 100, NULL, 0);
236} 238}
237 239
238static void __init perseus2_init_smc91x(void) 240static void __init perseus2_init_smc91x(void)
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c
new file mode 100644
index 000000000000..8c93d47719e8
--- /dev/null
+++ b/arch/arm/mach-omap1/board-sx1-mmc.c
@@ -0,0 +1,124 @@
1/*
2 * linux/arch/arm/mach-omap1/board-sx1-mmc.c
3 *
4 * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT
5 * Author: Carlos Eduardo Aguiar <carlos.aguiar@indt.org.br>
6 *
7 * This code is based on linux/arch/arm/mach-omap1/board-h2-mmc.c, which is:
8 * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <asm/arch/hardware.h>
16#include <asm/arch/mmc.h>
17#include <asm/arch/gpio.h>
18
19#ifdef CONFIG_MMC_OMAP
20static int slot_cover_open;
21static struct device *mmc_device;
22
23static int sx1_mmc_set_power(struct device *dev, int slot, int power_on,
24 int vdd)
25{
26 int err;
27 u8 dat = 0;
28
29#ifdef CONFIG_MMC_DEBUG
30 dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
31 power_on ? "on" : "off", vdd);
32#endif
33
34 if (slot != 0) {
35 dev_err(dev, "No such slot %d\n", slot + 1);
36 return -ENODEV;
37 }
38
39 err = sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat);
40 if (err < 0)
41 return err;
42
43 if (power_on)
44 dat |= SOFIA_MMC_POWER;
45 else
46 dat &= ~SOFIA_MMC_POWER;
47
48 return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat);
49}
50
51static int sx1_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode)
52{
53#ifdef CONFIG_MMC_DEBUG
54 dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1,
55 bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull");
56#endif
57 if (slot != 0) {
58 dev_err(dev, "No such slot %d\n", slot + 1);
59 return -ENODEV;
60 }
61
62 return 0;
63}
64
65static int sx1_mmc_get_cover_state(struct device *dev, int slot)
66{
67 BUG_ON(slot != 0);
68
69 return slot_cover_open;
70}
71
72void sx1_mmc_slot_cover_handler(void *arg, int state)
73{
74 if (mmc_device == NULL)
75 return;
76
77 slot_cover_open = state;
78 omap_mmc_notify_cover_event(mmc_device, 0, state);
79}
80
81static int sx1_mmc_late_init(struct device *dev)
82{
83 int ret = 0;
84
85 mmc_device = dev;
86
87 return ret;
88}
89
90static void sx1_mmc_cleanup(struct device *dev)
91{
92}
93
94static struct omap_mmc_platform_data sx1_mmc_data = {
95 .nr_slots = 1,
96 .switch_slot = NULL,
97 .init = sx1_mmc_late_init,
98 .cleanup = sx1_mmc_cleanup,
99 .slots[0] = {
100 .set_power = sx1_mmc_set_power,
101 .set_bus_mode = sx1_mmc_set_bus_mode,
102 .get_ro = NULL,
103 .get_cover_state = sx1_mmc_get_cover_state,
104 .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 |
105 MMC_VDD_32_33 | MMC_VDD_33_34,
106 .name = "mmcblk",
107 },
108};
109
110void __init sx1_mmc_init(void)
111{
112 omap_set_mmc_info(1, &sx1_mmc_data);
113}
114
115#else
116
117void __init sx1_mmc_init(void)
118{
119}
120
121void sx1_mmc_slot_cover_handler(void *arg, int state)
122{
123}
124#endif
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 2743d639aa05..1c7f09aedf07 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -44,7 +44,7 @@
44#include <asm/arch/keypad.h> 44#include <asm/arch/keypad.h>
45 45
46/* Write to I2C device */ 46/* Write to I2C device */
47int i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) 47int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
48{ 48{
49 struct i2c_adapter *adap; 49 struct i2c_adapter *adap;
50 int err; 50 int err;
@@ -67,7 +67,7 @@ int i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
67} 67}
68 68
69/* Read from I2C device */ 69/* Read from I2C device */
70int i2c_read_byte(u8 devaddr, u8 regoffset, u8 * value) 70int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value)
71{ 71{
72 struct i2c_adapter *adap; 72 struct i2c_adapter *adap;
73 int err; 73 int err;
@@ -101,66 +101,55 @@ int sx1_setkeylight(u8 keylight)
101{ 101{
102 if (keylight > SOFIA_MAX_LIGHT_VAL) 102 if (keylight > SOFIA_MAX_LIGHT_VAL)
103 keylight = SOFIA_MAX_LIGHT_VAL; 103 keylight = SOFIA_MAX_LIGHT_VAL;
104 return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight); 104 return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight);
105} 105}
106/* get current keylight intensity */ 106/* get current keylight intensity */
107int sx1_getkeylight(u8 * keylight) 107int sx1_getkeylight(u8 * keylight)
108{ 108{
109 return i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight); 109 return sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight);
110} 110}
111/* set LCD backlight intensity */ 111/* set LCD backlight intensity */
112int sx1_setbacklight(u8 backlight) 112int sx1_setbacklight(u8 backlight)
113{ 113{
114 if (backlight > SOFIA_MAX_LIGHT_VAL) 114 if (backlight > SOFIA_MAX_LIGHT_VAL)
115 backlight = SOFIA_MAX_LIGHT_VAL; 115 backlight = SOFIA_MAX_LIGHT_VAL;
116 return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, backlight); 116 return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG,
117 backlight);
117} 118}
118/* get current LCD backlight intensity */ 119/* get current LCD backlight intensity */
119int sx1_getbacklight (u8 * backlight) 120int sx1_getbacklight (u8 * backlight)
120{ 121{
121 return i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, backlight); 122 return sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG,
123 backlight);
122} 124}
123/* set LCD backlight power on/off */ 125/* set LCD backlight power on/off */
124int sx1_setmmipower(u8 onoff) 126int sx1_setmmipower(u8 onoff)
125{ 127{
126 int err; 128 int err;
127 u8 dat = 0; 129 u8 dat = 0;
128 err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); 130 err = sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat);
129 if (err < 0) 131 if (err < 0)
130 return err; 132 return err;
131 if (onoff) 133 if (onoff)
132 dat |= SOFIA_MMILIGHT_POWER; 134 dat |= SOFIA_MMILIGHT_POWER;
133 else 135 else
134 dat &= ~SOFIA_MMILIGHT_POWER; 136 dat &= ~SOFIA_MMILIGHT_POWER;
135 return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); 137 return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat);
136}
137/* set MMC power on/off */
138int sx1_setmmcpower(u8 onoff)
139{
140 int err;
141 u8 dat = 0;
142 err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat);
143 if (err < 0)
144 return err;
145 if (onoff)
146 dat |= SOFIA_MMC_POWER;
147 else
148 dat &= ~SOFIA_MMC_POWER;
149 return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat);
150} 138}
139
151/* set USB power on/off */ 140/* set USB power on/off */
152int sx1_setusbpower(u8 onoff) 141int sx1_setusbpower(u8 onoff)
153{ 142{
154 int err; 143 int err;
155 u8 dat = 0; 144 u8 dat = 0;
156 err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); 145 err = sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat);
157 if (err < 0) 146 if (err < 0)
158 return err; 147 return err;
159 if (onoff) 148 if (onoff)
160 dat |= SOFIA_USB_POWER; 149 dat |= SOFIA_USB_POWER;
161 else 150 else
162 dat &= ~SOFIA_USB_POWER; 151 dat &= ~SOFIA_USB_POWER;
163 return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); 152 return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat);
164} 153}
165 154
166EXPORT_SYMBOL(sx1_setkeylight); 155EXPORT_SYMBOL(sx1_setkeylight);
@@ -168,7 +157,6 @@ EXPORT_SYMBOL(sx1_getkeylight);
168EXPORT_SYMBOL(sx1_setbacklight); 157EXPORT_SYMBOL(sx1_setbacklight);
169EXPORT_SYMBOL(sx1_getbacklight); 158EXPORT_SYMBOL(sx1_getbacklight);
170EXPORT_SYMBOL(sx1_setmmipower); 159EXPORT_SYMBOL(sx1_setmmipower);
171EXPORT_SYMBOL(sx1_setmmcpower);
172EXPORT_SYMBOL(sx1_setusbpower); 160EXPORT_SYMBOL(sx1_setusbpower);
173 161
174/*----------- Keypad -------------------------*/ 162/*----------- Keypad -------------------------*/
@@ -280,21 +268,6 @@ static struct omap_mcbsp_reg_cfg mcbsp1_regs = {
280 /* PCR0 =0f0f */ 268 /* PCR0 =0f0f */
281}; 269};
282 270
283/* TODO: PCM interface - McBSP2 */
284static struct omap_mcbsp_reg_cfg mcbsp2_regs = {
285 .spcr2 = FRST | GRST | XRST | XINTM(3), /* SPCR2=F1 */
286 .spcr1 = RINTM(3) | RRST, /* SPCR1=30 */
287 .rcr2 = 0, /* RCR2 =00 */
288 .rcr1 = RFRLEN1(1) | RWDLEN1(OMAP_MCBSP_WORD_16), /* RCR1 = 140 */
289 .xcr2 = 0, /* XCR2 = 0 */
290 .xcr1 = XFRLEN1(1) | XWDLEN1(OMAP_MCBSP_WORD_16), /* XCR1 = 140 */
291 .srgr1 = FWID(15) | CLKGDV(12), /* SRGR1=0f0c */
292 .srgr2 = FSGM | FPER(31), /* SRGR2=101f */
293 .pcr0 = FSXM | FSRM | CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP,
294 /* PCR0=0f0f */
295 /* mcbsp: slave */
296};
297
298static struct omap_alsa_codec_config sx1_alsa_config = { 271static struct omap_alsa_codec_config sx1_alsa_config = {
299 .name = "SX1 EGold", 272 .name = "SX1 EGold",
300 .mcbsp_regs_alsa = &mcbsp1_regs, 273 .mcbsp_regs_alsa = &mcbsp1_regs,
@@ -407,11 +380,8 @@ static struct omap_usb_config sx1_usb_config __initdata = {
407 380
408static struct omap_mmc_config sx1_mmc_config __initdata = { 381static struct omap_mmc_config sx1_mmc_config __initdata = {
409 .mmc [0] = { 382 .mmc [0] = {
410 .enabled = 1, 383 .enabled = 1,
411 .wire4 = 0, 384 .wire4 = 0,
412 .wp_pin = -1,
413 .power_pin = -1, /* power is in Sofia */
414 .switch_pin = OMAP_MPUIO(3),
415 }, 385 },
416}; 386};
417 387
@@ -440,13 +410,15 @@ static struct omap_uart_config sx1_uart_config __initdata = {
440 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), 410 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
441}; 411};
442 412
443static struct omap_board_config_kernel sx1_config[] = { 413static struct omap_board_config_kernel sx1_config[] __initdata = {
444 { OMAP_TAG_USB, &sx1_usb_config }, 414 { OMAP_TAG_USB, &sx1_usb_config },
445 { OMAP_TAG_MMC, &sx1_mmc_config }, 415 { OMAP_TAG_MMC, &sx1_mmc_config },
446 { OMAP_TAG_LCD, &sx1_lcd_config }, 416 { OMAP_TAG_LCD, &sx1_lcd_config },
447 { OMAP_TAG_UART, &sx1_uart_config }, 417 { OMAP_TAG_UART, &sx1_uart_config },
448}; 418};
419
449/*-----------------------------------------*/ 420/*-----------------------------------------*/
421
450static void __init omap_sx1_init(void) 422static void __init omap_sx1_init(void)
451{ 423{
452 platform_add_devices(sx1_devices, ARRAY_SIZE(sx1_devices)); 424 platform_add_devices(sx1_devices, ARRAY_SIZE(sx1_devices));
@@ -454,6 +426,8 @@ static void __init omap_sx1_init(void)
454 omap_board_config = sx1_config; 426 omap_board_config = sx1_config;
455 omap_board_config_size = ARRAY_SIZE(sx1_config); 427 omap_board_config_size = ARRAY_SIZE(sx1_config);
456 omap_serial_init(); 428 omap_serial_init();
429 omap_register_i2c_bus(1, 100, NULL, 0);
430 sx1_mmc_init();
457 431
458 /* turn on USB power */ 432 /* turn on USB power */
459 /* sx1_setusbpower(1); cant do it here because i2c is not ready */ 433 /* sx1_setusbpower(1); cant do it here because i2c is not ready */
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index c82a1cd20ad4..5c00b3f39cdd 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -34,9 +34,6 @@
34#include <asm/arch/tc.h> 34#include <asm/arch/tc.h>
35#include <asm/arch/usb.h> 35#include <asm/arch/usb.h>
36 36
37extern void omap_init_time(void);
38extern int omap_gpio_init(void);
39
40static struct plat_serial8250_port voiceblue_ports[] = { 37static struct plat_serial8250_port voiceblue_ports[] = {
41 { 38 {
42 .mapbase = (unsigned long)(OMAP_CS1_PHYS + 0x40000), 39 .mapbase = (unsigned long)(OMAP_CS1_PHYS + 0x40000),
@@ -198,6 +195,7 @@ static void __init voiceblue_init(void)
198 omap_board_config = voiceblue_config; 195 omap_board_config = voiceblue_config;
199 omap_board_config_size = ARRAY_SIZE(voiceblue_config); 196 omap_board_config_size = ARRAY_SIZE(voiceblue_config);
200 omap_serial_init(); 197 omap_serial_init();
198 omap_register_i2c_bus(1, 100, NULL, 0);
201 199
202 /* There is a good chance board is going up, so enable power LED 200 /* There is a good chance board is going up, so enable power LED
203 * (it is connected through invertor) */ 201 * (it is connected through invertor) */
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 5d9faa68d2ec..4ea2933f887d 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -1,4 +1,3 @@
1//kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text)
2/* 1/*
3 * linux/arch/arm/mach-omap1/clock.c 2 * linux/arch/arm/mach-omap1/clock.c
4 * 3 *
@@ -650,9 +649,9 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
650 649
651 /* FIXME: This clock seems to be necessary but no-one 650 /* FIXME: This clock seems to be necessary but no-one
652 * has asked for its activation. */ 651 * has asked for its activation. */
653 if (clk == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera 652 if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */
654 || clk == &ck_dpll1out.clk // FIX: SoSSI, SSR 653 || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */
655 || clk == &arm_gpio_ck // FIX: GPIO code for 1510 654 || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */
656 ) { 655 ) {
657 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n", 656 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
658 clk->name); 657 clk->name);
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
index 6939d5e7569a..026685ed461a 100644
--- a/arch/arm/mach-omap1/leds-osk.c
+++ b/arch/arm/mach-omap1/leds-osk.c
@@ -82,7 +82,7 @@ static void mistral_setled(void)
82 red = 1; 82 red = 1;
83 else if (hw_led_state & IDLE_LED) 83 else if (hw_led_state & IDLE_LED)
84 green = 1; 84 green = 1;
85 // else both sides are disabled 85 /* else both sides are disabled */
86 86
87 omap_set_gpio_dataout(GPIO_LED_GREEN, green); 87 omap_set_gpio_dataout(GPIO_LED_GREEN, green);
88 omap_set_gpio_dataout(GPIO_LED_RED, red); 88 omap_set_gpio_dataout(GPIO_LED_RED, red);
@@ -112,7 +112,7 @@ void osk_leds_event(led_event_t evt)
112 case led_stop: 112 case led_stop:
113 led_state &= ~LED_STATE_ENABLED; 113 led_state &= ~LED_STATE_ENABLED;
114 hw_led_state = 0; 114 hw_led_state = 0;
115 // NOTE: work may still be pending!! 115 /* NOTE: work may still be pending!! */
116 break; 116 break;
117 117
118 case led_claim: 118 case led_claim:
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index d3abf5609902..bad1e7152d8e 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -51,7 +51,7 @@ static inline void mbox_write_reg(unsigned int val, unsigned int reg)
51} 51}
52 52
53/* msg */ 53/* msg */
54static inline mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox) 54static mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox)
55{ 55{
56 struct omap_mbox1_fifo *fifo = 56 struct omap_mbox1_fifo *fifo =
57 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; 57 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
@@ -63,7 +63,7 @@ static inline mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox)
63 return msg; 63 return msg;
64} 64}
65 65
66static inline void 66static void
67omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) 67omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
68{ 68{
69 struct omap_mbox1_fifo *fifo = 69 struct omap_mbox1_fifo *fifo =
@@ -73,12 +73,12 @@ omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
73 mbox_write_reg(msg >> 16, fifo->cmd); 73 mbox_write_reg(msg >> 16, fifo->cmd);
74} 74}
75 75
76static inline int omap1_mbox_fifo_empty(struct omap_mbox *mbox) 76static int omap1_mbox_fifo_empty(struct omap_mbox *mbox)
77{ 77{
78 return 0; 78 return 0;
79} 79}
80 80
81static inline int omap1_mbox_fifo_full(struct omap_mbox *mbox) 81static int omap1_mbox_fifo_full(struct omap_mbox *mbox)
82{ 82{
83 struct omap_mbox1_fifo *fifo = 83 struct omap_mbox1_fifo *fifo =
84 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; 84 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
@@ -87,21 +87,21 @@ static inline int omap1_mbox_fifo_full(struct omap_mbox *mbox)
87} 87}
88 88
89/* irq */ 89/* irq */
90static inline void 90static void
91omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) 91omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
92{ 92{
93 if (irq == IRQ_RX) 93 if (irq == IRQ_RX)
94 enable_irq(mbox->irq); 94 enable_irq(mbox->irq);
95} 95}
96 96
97static inline void 97static void
98omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) 98omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
99{ 99{
100 if (irq == IRQ_RX) 100 if (irq == IRQ_RX)
101 disable_irq(mbox->irq); 101 disable_irq(mbox->irq);
102} 102}
103 103
104static inline int 104static int
105omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) 105omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
106{ 106{
107 if (irq == IRQ_TX) 107 if (irq == IRQ_TX)
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 06b7e54a0128..8eb5dcdaead2 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -57,7 +57,6 @@
57#include <asm/arch/pm.h> 57#include <asm/arch/pm.h>
58#include <asm/arch/mux.h> 58#include <asm/arch/mux.h>
59#include <asm/arch/dma.h> 59#include <asm/arch/dma.h>
60#include <asm/arch/dsp_common.h>
61#include <asm/arch/dmtimer.h> 60#include <asm/arch/dmtimer.h>
62 61
63static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; 62static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
@@ -67,6 +66,8 @@ static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
67static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; 66static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
68static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; 67static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
69 68
69#ifdef CONFIG_OMAP_32K_TIMER
70
70static unsigned short enable_dyn_sleep = 1; 71static unsigned short enable_dyn_sleep = 1;
71 72
72static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr, 73static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
@@ -91,7 +92,8 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
91static struct kobj_attribute sleep_while_idle_attr = 92static struct kobj_attribute sleep_while_idle_attr =
92 __ATTR(sleep_while_idle, 0644, idle_show, idle_store); 93 __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
93 94
94static void (*omap_sram_idle)(void) = NULL; 95#endif
96
95static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; 97static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
96 98
97/* 99/*
@@ -104,9 +106,7 @@ void omap_pm_idle(void)
104{ 106{
105 extern __u32 arm_idlect1_mask; 107 extern __u32 arm_idlect1_mask;
106 __u32 use_idlect1 = arm_idlect1_mask; 108 __u32 use_idlect1 = arm_idlect1_mask;
107#ifndef CONFIG_OMAP_MPU_TIMER 109 int do_sleep = 0;
108 int do_sleep;
109#endif
110 110
111 local_irq_disable(); 111 local_irq_disable();
112 local_fiq_disable(); 112 local_fiq_disable();
@@ -128,7 +128,6 @@ void omap_pm_idle(void)
128 use_idlect1 = use_idlect1 & ~(1 << 9); 128 use_idlect1 = use_idlect1 & ~(1 << 9);
129#else 129#else
130 130
131 do_sleep = 0;
132 while (enable_dyn_sleep) { 131 while (enable_dyn_sleep) {
133 132
134#ifdef CONFIG_CBUS_TAHVO_USB 133#ifdef CONFIG_CBUS_TAHVO_USB
@@ -141,6 +140,8 @@ void omap_pm_idle(void)
141 break; 140 break;
142 } 141 }
143 142
143#endif
144
144#ifdef CONFIG_OMAP_DM_TIMER 145#ifdef CONFIG_OMAP_DM_TIMER
145 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1); 146 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
146#endif 147#endif
@@ -168,7 +169,6 @@ void omap_pm_idle(void)
168 } 169 }
169 omap_sram_suspend(omap_readl(ARM_IDLECT1), 170 omap_sram_suspend(omap_readl(ARM_IDLECT1),
170 omap_readl(ARM_IDLECT2)); 171 omap_readl(ARM_IDLECT2));
171#endif
172 172
173 local_fiq_enable(); 173 local_fiq_enable();
174 local_irq_enable(); 174 local_irq_enable();
@@ -661,7 +661,10 @@ static struct platform_suspend_ops omap_pm_ops ={
661 661
662static int __init omap_pm_init(void) 662static int __init omap_pm_init(void)
663{ 663{
664
665#ifdef CONFIG_OMAP_32K_TIMER
664 int error; 666 int error;
667#endif
665 668
666 printk("Power Management for TI OMAP.\n"); 669 printk("Power Management for TI OMAP.\n");
667 670
@@ -671,23 +674,17 @@ static int __init omap_pm_init(void)
671 * memory the MPU can see when it wakes up. 674 * memory the MPU can see when it wakes up.
672 */ 675 */
673 if (cpu_is_omap730()) { 676 if (cpu_is_omap730()) {
674 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
675 omap730_idle_loop_suspend_sz);
676 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend, 677 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
677 omap730_cpu_suspend_sz); 678 omap730_cpu_suspend_sz);
678 } else if (cpu_is_omap15xx()) { 679 } else if (cpu_is_omap15xx()) {
679 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
680 omap1510_idle_loop_suspend_sz);
681 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, 680 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
682 omap1510_cpu_suspend_sz); 681 omap1510_cpu_suspend_sz);
683 } else if (cpu_is_omap16xx()) { 682 } else if (cpu_is_omap16xx()) {
684 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
685 omap1610_idle_loop_suspend_sz);
686 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend, 683 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
687 omap1610_cpu_suspend_sz); 684 omap1610_cpu_suspend_sz);
688 } 685 }
689 686
690 if (omap_sram_idle == NULL || omap_sram_suspend == NULL) { 687 if (omap_sram_suspend == NULL) {
691 printk(KERN_ERR "PM not initialized: Missing SRAM support\n"); 688 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
692 return -ENODEV; 689 return -ENODEV;
693 } 690 }
@@ -719,9 +716,11 @@ static int __init omap_pm_init(void)
719 omap_pm_init_proc(); 716 omap_pm_init_proc();
720#endif 717#endif
721 718
719#ifdef CONFIG_OMAP_32K_TIMER
722 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr); 720 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr);
723 if (error) 721 if (error)
724 printk(KERN_ERR "sysfs_create_file failed: %d\n", error); 722 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
723#endif
725 724
726 if (cpu_is_omap16xx()) { 725 if (cpu_is_omap16xx()) {
727 /* configure LOW_PWR pin */ 726 /* configure LOW_PWR pin */
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
index abef33d10f01..68f5b39030b6 100644
--- a/arch/arm/mach-omap1/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -39,167 +39,6 @@
39 39
40 .text 40 .text
41 41
42/*
43 * Forces OMAP into idle state
44 *
45 * omapXXXX_idle_loop_suspend()
46 *
47 * Note: This code get's copied to internal SRAM at boot. When the OMAP
48 * wakes up it continues execution at the point it went to sleep.
49 *
50 * Note: Because of slightly different configuration values we have
51 * processor specific functions here.
52 */
53
54#if defined(CONFIG_ARCH_OMAP730)
55ENTRY(omap730_idle_loop_suspend)
56
57 stmfd sp!, {r0 - r12, lr} @ save registers on stack
58
59 @ load base address of ARM_IDLECT1 and ARM_IDLECT2
60 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
61 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
62 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
63
64 @ turn off clock domains
65 @ get ARM_IDLECT2 into r2
66 ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
67 mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff
68 orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00
69 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
70
71 @ request ARM idle
72 @ get ARM_IDLECT1 into r1
73 ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
74 orr r3, r1, #OMAP730_IDLE_LOOP_REQUEST & 0xffff
75 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
76
77 mov r5, #IDLE_WAIT_CYCLES & 0xff
78 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
79l_730: subs r5, r5, #1
80 bne l_730
81/*
82 * Let's wait for the next clock tick to wake us up.
83 */
84 mov r0, #0
85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
86/*
87 * omap730_idle_loop_suspend()'s resume point.
88 *
89 * It will just start executing here, so we'll restore stuff from the
90 * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
91 */
92
93 @ restore ARM_IDLECT1 and ARM_IDLECT2 and return
94 @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
95 strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
96 strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
97
98 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
99
100ENTRY(omap730_idle_loop_suspend_sz)
101 .word . - omap730_idle_loop_suspend
102#endif /* CONFIG_ARCH_OMAP730 */
103
104#ifdef CONFIG_ARCH_OMAP15XX
105ENTRY(omap1510_idle_loop_suspend)
106
107 stmfd sp!, {r0 - r12, lr} @ save registers on stack
108
109 @ load base address of ARM_IDLECT1 and ARM_IDLECT2
110 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
111 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
112 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
113
114 @ turn off clock domains
115 @ get ARM_IDLECT2 into r2
116 ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
117 mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
118 orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
119 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
120
121 @ request ARM idle
122 @ get ARM_IDLECT1 into r1
123 ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
124 orr r3, r1, #OMAP1510_IDLE_LOOP_REQUEST & 0xffff
125 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
126
127 mov r5, #IDLE_WAIT_CYCLES & 0xff
128 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
129l_1510: subs r5, r5, #1
130 bne l_1510
131/*
132 * Let's wait for the next clock tick to wake us up.
133 */
134 mov r0, #0
135 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
136/*
137 * omap1510_idle_loop_suspend()'s resume point.
138 *
139 * It will just start executing here, so we'll restore stuff from the
140 * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
141 */
142
143 @ restore ARM_IDLECT1 and ARM_IDLECT2 and return
144 @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
145 strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
146 strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
147
148 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
149
150ENTRY(omap1510_idle_loop_suspend_sz)
151 .word . - omap1510_idle_loop_suspend
152#endif /* CONFIG_ARCH_OMAP15XX */
153
154#if defined(CONFIG_ARCH_OMAP16XX)
155ENTRY(omap1610_idle_loop_suspend)
156
157 stmfd sp!, {r0 - r12, lr} @ save registers on stack
158
159 @ load base address of ARM_IDLECT1 and ARM_IDLECT2
160 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
161 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
162 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
163
164 @ turn off clock domains
165 @ get ARM_IDLECT2 into r2
166 ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
167 mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
168 orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
169 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
170
171 @ request ARM idle
172 @ get ARM_IDLECT1 into r1
173 ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
174 orr r3, r1, #OMAP1610_IDLE_LOOP_REQUEST & 0xffff
175 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
176
177 mov r5, #IDLE_WAIT_CYCLES & 0xff
178 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
179l_1610: subs r5, r5, #1
180 bne l_1610
181/*
182 * Let's wait for the next clock tick to wake us up.
183 */
184 mov r0, #0
185 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
186/*
187 * omap1610_idle_loop_suspend()'s resume point.
188 *
189 * It will just start executing here, so we'll restore stuff from the
190 * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
191 */
192
193 @ restore ARM_IDLECT1 and ARM_IDLECT2 and return
194 @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
195 strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
196 strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
197
198 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
199
200ENTRY(omap1610_idle_loop_suspend_sz)
201 .word . - omap1610_idle_loop_suspend
202#endif /* CONFIG_ARCH_OMAP16XX */
203 42
204/* 43/*
205 * Forces OMAP into deep sleep state 44 * Forces OMAP into deep sleep state
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c
index 488da3811a68..2e2fd63643c3 100644
--- a/arch/arm/mach-orion/addr-map.c
+++ b/arch/arm/mach-orion/addr-map.c
@@ -265,15 +265,15 @@ void __init orion_setup_cpu_wins(void)
265 } 265 }
266 266
267 /* 267 /*
268 * Setup windows for PCI+PCIE IO+MAM space 268 * Setup windows for PCI+PCIe IO+MEM space.
269 */ 269 */
270 orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE, 270 orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
271 ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP); 271 ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
272 orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE, 272 orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
273 ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP); 273 ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
274 orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE, 274 orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
275 ORION_PCIE_MEM_SIZE, -1); 275 ORION_PCIE_MEM_SIZE, -1);
276 orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE, 276 orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
277 ORION_PCI_MEM_SIZE, -1); 277 ORION_PCI_MEM_SIZE, -1);
278} 278}
279 279
diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c
index 5e20b6b32508..5f0ee4b8a9b7 100644
--- a/arch/arm/mach-orion/common.c
+++ b/arch/arm/mach-orion/common.c
@@ -19,7 +19,7 @@
19#include <asm/page.h> 19#include <asm/page.h>
20#include <asm/timex.h> 20#include <asm/timex.h>
21#include <asm/mach/map.h> 21#include <asm/mach/map.h>
22#include <asm/arch/orion.h> 22#include <asm/arch/hardware.h>
23#include "common.h" 23#include "common.h"
24 24
25/***************************************************************************** 25/*****************************************************************************
@@ -27,26 +27,26 @@
27 ****************************************************************************/ 27 ****************************************************************************/
28static struct map_desc orion_io_desc[] __initdata = { 28static struct map_desc orion_io_desc[] __initdata = {
29 { 29 {
30 .virtual = ORION_REGS_BASE, 30 .virtual = ORION_REGS_VIRT_BASE,
31 .pfn = __phys_to_pfn(ORION_REGS_BASE), 31 .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE),
32 .length = ORION_REGS_SIZE, 32 .length = ORION_REGS_SIZE,
33 .type = MT_DEVICE 33 .type = MT_DEVICE
34 }, 34 },
35 { 35 {
36 .virtual = ORION_PCIE_IO_BASE, 36 .virtual = ORION_PCIE_IO_VIRT_BASE,
37 .pfn = __phys_to_pfn(ORION_PCIE_IO_BASE), 37 .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE),
38 .length = ORION_PCIE_IO_SIZE, 38 .length = ORION_PCIE_IO_SIZE,
39 .type = MT_DEVICE 39 .type = MT_DEVICE
40 }, 40 },
41 { 41 {
42 .virtual = ORION_PCI_IO_BASE, 42 .virtual = ORION_PCI_IO_VIRT_BASE,
43 .pfn = __phys_to_pfn(ORION_PCI_IO_BASE), 43 .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE),
44 .length = ORION_PCI_IO_SIZE, 44 .length = ORION_PCI_IO_SIZE,
45 .type = MT_DEVICE 45 .type = MT_DEVICE
46 }, 46 },
47 { 47 {
48 .virtual = ORION_PCIE_WA_BASE, 48 .virtual = ORION_PCIE_WA_VIRT_BASE,
49 .pfn = __phys_to_pfn(ORION_PCIE_WA_BASE), 49 .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE),
50 .length = ORION_PCIE_WA_SIZE, 50 .length = ORION_PCIE_WA_SIZE,
51 .type = MT_DEVICE 51 .type = MT_DEVICE
52 }, 52 },
@@ -63,8 +63,8 @@ void __init orion_map_io(void)
63 63
64static struct resource orion_uart_resources[] = { 64static struct resource orion_uart_resources[] = {
65 { 65 {
66 .start = UART0_BASE, 66 .start = UART0_PHYS_BASE,
67 .end = UART0_BASE + 0xff, 67 .end = UART0_PHYS_BASE + 0xff,
68 .flags = IORESOURCE_MEM, 68 .flags = IORESOURCE_MEM,
69 }, 69 },
70 { 70 {
@@ -73,8 +73,8 @@ static struct resource orion_uart_resources[] = {
73 .flags = IORESOURCE_IRQ, 73 .flags = IORESOURCE_IRQ,
74 }, 74 },
75 { 75 {
76 .start = UART1_BASE, 76 .start = UART1_PHYS_BASE,
77 .end = UART1_BASE + 0xff, 77 .end = UART1_PHYS_BASE + 0xff,
78 .flags = IORESOURCE_MEM, 78 .flags = IORESOURCE_MEM,
79 }, 79 },
80 { 80 {
@@ -86,8 +86,8 @@ static struct resource orion_uart_resources[] = {
86 86
87static struct plat_serial8250_port orion_uart_data[] = { 87static struct plat_serial8250_port orion_uart_data[] = {
88 { 88 {
89 .mapbase = UART0_BASE, 89 .mapbase = UART0_PHYS_BASE,
90 .membase = (char *)UART0_BASE, 90 .membase = (char *)UART0_VIRT_BASE,
91 .irq = IRQ_ORION_UART0, 91 .irq = IRQ_ORION_UART0,
92 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 92 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
93 .iotype = UPIO_MEM, 93 .iotype = UPIO_MEM,
@@ -95,8 +95,8 @@ static struct plat_serial8250_port orion_uart_data[] = {
95 .uartclk = ORION_TCLK, 95 .uartclk = ORION_TCLK,
96 }, 96 },
97 { 97 {
98 .mapbase = UART1_BASE, 98 .mapbase = UART1_PHYS_BASE,
99 .membase = (char *)UART1_BASE, 99 .membase = (char *)UART1_VIRT_BASE,
100 .irq = IRQ_ORION_UART1, 100 .irq = IRQ_ORION_UART1,
101 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 101 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
102 .iotype = UPIO_MEM, 102 .iotype = UPIO_MEM,
@@ -122,8 +122,8 @@ static struct platform_device orion_uart = {
122 122
123static struct resource orion_ehci0_resources[] = { 123static struct resource orion_ehci0_resources[] = {
124 { 124 {
125 .start = ORION_USB0_REG_BASE, 125 .start = ORION_USB0_PHYS_BASE,
126 .end = ORION_USB0_REG_BASE + SZ_4K, 126 .end = ORION_USB0_PHYS_BASE + SZ_4K,
127 .flags = IORESOURCE_MEM, 127 .flags = IORESOURCE_MEM,
128 }, 128 },
129 { 129 {
@@ -135,8 +135,8 @@ static struct resource orion_ehci0_resources[] = {
135 135
136static struct resource orion_ehci1_resources[] = { 136static struct resource orion_ehci1_resources[] = {
137 { 137 {
138 .start = ORION_USB1_REG_BASE, 138 .start = ORION_USB1_PHYS_BASE,
139 .end = ORION_USB1_REG_BASE + SZ_4K, 139 .end = ORION_USB1_PHYS_BASE + SZ_4K,
140 .flags = IORESOURCE_MEM, 140 .flags = IORESOURCE_MEM,
141 }, 141 },
142 { 142 {
@@ -177,8 +177,8 @@ static struct platform_device orion_ehci1 = {
177 177
178static struct resource orion_eth_shared_resources[] = { 178static struct resource orion_eth_shared_resources[] = {
179 { 179 {
180 .start = ORION_ETH_REG_BASE, 180 .start = ORION_ETH_PHYS_BASE,
181 .end = ORION_ETH_REG_BASE + 0xffff, 181 .end = ORION_ETH_PHYS_BASE + 0xffff,
182 .flags = IORESOURCE_MEM, 182 .flags = IORESOURCE_MEM,
183 }, 183 },
184}; 184};
@@ -227,8 +227,8 @@ static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
227static struct resource orion_i2c_resources[] = { 227static struct resource orion_i2c_resources[] = {
228 { 228 {
229 .name = "i2c base", 229 .name = "i2c base",
230 .start = I2C_BASE, 230 .start = I2C_PHYS_BASE,
231 .end = I2C_BASE + 0x20 -1, 231 .end = I2C_PHYS_BASE + 0x20 -1,
232 .flags = IORESOURCE_MEM, 232 .flags = IORESOURCE_MEM,
233 }, 233 },
234 { 234 {
@@ -250,6 +250,40 @@ static struct platform_device orion_i2c = {
250}; 250};
251 251
252/***************************************************************************** 252/*****************************************************************************
253 * Sata port
254 ****************************************************************************/
255static struct resource orion_sata_resources[] = {
256 {
257 .name = "sata base",
258 .start = ORION_SATA_PHYS_BASE,
259 .end = ORION_SATA_PHYS_BASE + 0x5000 - 1,
260 .flags = IORESOURCE_MEM,
261 },
262 {
263 .name = "sata irq",
264 .start = IRQ_ORION_SATA,
265 .end = IRQ_ORION_SATA,
266 .flags = IORESOURCE_IRQ,
267 },
268};
269
270static struct platform_device orion_sata = {
271 .name = "sata_mv",
272 .id = 0,
273 .dev = {
274 .coherent_dma_mask = 0xffffffff,
275 },
276 .num_resources = ARRAY_SIZE(orion_sata_resources),
277 .resource = orion_sata_resources,
278};
279
280void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
281{
282 orion_sata.dev.platform_data = sata_data;
283 platform_device_register(&orion_sata);
284}
285
286/*****************************************************************************
253 * General 287 * General
254 ****************************************************************************/ 288 ****************************************************************************/
255 289
diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h
index 06c10c06f03e..10154ec885df 100644
--- a/arch/arm/mach-orion/common.h
+++ b/arch/arm/mach-orion/common.h
@@ -75,4 +75,12 @@ struct mv643xx_eth_platform_data;
75 75
76void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data); 76void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
77 77
78/*
79 * Orion Sata platform_data, used by machine-setup
80 */
81
82struct mv_sata_platform_data;
83
84void __init orion_sata_init(struct mv_sata_platform_data *sata_data);
85
78#endif /* __ARCH_ORION_COMMON_H__ */ 86#endif /* __ARCH_ORION_COMMON_H__ */
diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c
index cb2a95ce5b57..5ef44e1a2d36 100644
--- a/arch/arm/mach-orion/db88f5281-setup.c
+++ b/arch/arm/mach-orion/db88f5281-setup.c
@@ -354,8 +354,8 @@ static void __init db88f5281_init(void)
354 354
355MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") 355MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
356 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ 356 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
357 .phys_io = ORION_REGS_BASE, 357 .phys_io = ORION_REGS_PHYS_BASE,
358 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc, 358 .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc,
359 .boot_params = 0x00000100, 359 .boot_params = 0x00000100,
360 .init_machine = db88f5281_init, 360 .init_machine = db88f5281_init,
361 .map_io = orion_map_io, 361 .map_io = orion_map_io,
diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c
index c8a806f249c6..02b280c24820 100644
--- a/arch/arm/mach-orion/dns323-setup.c
+++ b/arch/arm/mach-orion/dns323-setup.c
@@ -259,8 +259,8 @@ static void __init dns323_init(void)
259 * 259 *
260 * Open a special address decode windows for the PCIE WA. 260 * Open a special address decode windows for the PCIE WA.
261 */ 261 */
262 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 262 orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
263 orion_write(ORION_REGS_BASE | 0x20070, 263 orion_write(ORION_REGS_VIRT_BASE | 0x20070,
264 (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 264 (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
265 265
266 /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ 266 /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
@@ -312,8 +312,8 @@ static void __init dns323_init(void)
312/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ 312/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
313MACHINE_START(DNS323, "D-Link DNS-323") 313MACHINE_START(DNS323, "D-Link DNS-323")
314 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ 314 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
315 .phys_io = ORION_REGS_BASE, 315 .phys_io = ORION_REGS_PHYS_BASE,
316 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 316 .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
317 .boot_params = 0x00000100, 317 .boot_params = 0x00000100,
318 .init_machine = dns323_init, 318 .init_machine = dns323_init,
319 .map_io = orion_map_io, 319 .map_io = orion_map_io,
diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c
index 2d812ed6b5c7..6817aca4aa26 100644
--- a/arch/arm/mach-orion/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion/kurobox_pro-setup.c
@@ -17,6 +17,7 @@
17#include <linux/mtd/nand.h> 17#include <linux/mtd/nand.h>
18#include <linux/mv643xx_eth.h> 18#include <linux/mv643xx_eth.h>
19#include <linux/i2c.h> 19#include <linux/i2c.h>
20#include <linux/ata_platform.h>
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21#include <asm/gpio.h> 22#include <asm/gpio.h>
22#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
@@ -167,6 +168,13 @@ static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = {
167}; 168};
168 169
169/***************************************************************************** 170/*****************************************************************************
171 * SATA
172 ****************************************************************************/
173static struct mv_sata_platform_data kurobox_pro_sata_data = {
174 .n_ports = 2,
175};
176
177/*****************************************************************************
170 * General Setup 178 * General Setup
171 ****************************************************************************/ 179 ****************************************************************************/
172 180
@@ -192,8 +200,8 @@ static void __init kurobox_pro_init(void)
192 /* 200 /*
193 * Open a special address decode windows for the PCIE WA. 201 * Open a special address decode windows for the PCIE WA.
194 */ 202 */
195 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 203 orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
196 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 204 orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
197 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 205 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
198 206
199 /* 207 /*
@@ -220,12 +228,13 @@ static void __init kurobox_pro_init(void)
220 platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); 228 platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices));
221 i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); 229 i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
222 orion_eth_init(&kurobox_pro_eth_data); 230 orion_eth_init(&kurobox_pro_eth_data);
231 orion_sata_init(&kurobox_pro_sata_data);
223} 232}
224 233
225MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") 234MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
226 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 235 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
227 .phys_io = ORION_REGS_BASE, 236 .phys_io = ORION_REGS_PHYS_BASE,
228 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 237 .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
229 .boot_params = 0x00000100, 238 .boot_params = 0x00000100,
230 .init_machine = kurobox_pro_init, 239 .init_machine = kurobox_pro_init,
231 .map_io = orion_map_io, 240 .map_io = orion_map_io,
diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c
index 0498d7c69b30..b109bb46681e 100644
--- a/arch/arm/mach-orion/pci.c
+++ b/arch/arm/mach-orion/pci.c
@@ -156,7 +156,7 @@ static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
156 orion_pcie_id(&dev, &rev); 156 orion_pcie_id(&dev, &rev);
157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 /* extended register space */ 158 /* extended register space */
159 pcie_addr = ORION_PCIE_WA_BASE; 159 pcie_addr = ORION_PCIE_WA_VIRT_BASE;
160 pcie_addr |= PCIE_CONF_BUS(bus->number) | 160 pcie_addr |= PCIE_CONF_BUS(bus->number) |
161 PCIE_CONF_DEV(PCI_SLOT(devfn)) | 161 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
162 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | 162 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
@@ -241,7 +241,7 @@ static int orion_pcie_setup(struct pci_sys_data *sys)
241 */ 241 */
242 res[0].name = "PCI-EX I/O Space"; 242 res[0].name = "PCI-EX I/O Space";
243 res[0].flags = IORESOURCE_IO; 243 res[0].flags = IORESOURCE_IO;
244 res[0].start = ORION_PCIE_IO_REMAP; 244 res[0].start = ORION_PCIE_IO_BUS_BASE;
245 res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; 245 res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
246 if (request_resource(&ioport_resource, &res[0])) 246 if (request_resource(&ioport_resource, &res[0]))
247 panic("Request PCIE IO resource failed\n"); 247 panic("Request PCIE IO resource failed\n");
@@ -252,7 +252,7 @@ static int orion_pcie_setup(struct pci_sys_data *sys)
252 */ 252 */
253 res[1].name = "PCI-EX Memory Space"; 253 res[1].name = "PCI-EX Memory Space";
254 res[1].flags = IORESOURCE_MEM; 254 res[1].flags = IORESOURCE_MEM;
255 res[1].start = ORION_PCIE_MEM_BASE; 255 res[1].start = ORION_PCIE_MEM_PHYS_BASE;
256 res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; 256 res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
257 if (request_resource(&iomem_resource, &res[1])) 257 if (request_resource(&iomem_resource, &res[1]))
258 panic("Request PCIE Memory resource failed\n"); 258 panic("Request PCIE Memory resource failed\n");
@@ -477,7 +477,7 @@ static int orion_pci_setup(struct pci_sys_data *sys)
477 */ 477 */
478 res[0].name = "PCI I/O Space"; 478 res[0].name = "PCI I/O Space";
479 res[0].flags = IORESOURCE_IO; 479 res[0].flags = IORESOURCE_IO;
480 res[0].start = ORION_PCI_IO_REMAP; 480 res[0].start = ORION_PCI_IO_BUS_BASE;
481 res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; 481 res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
482 if (request_resource(&ioport_resource, &res[0])) 482 if (request_resource(&ioport_resource, &res[0]))
483 panic("Request PCI IO resource failed\n"); 483 panic("Request PCI IO resource failed\n");
@@ -488,7 +488,7 @@ static int orion_pci_setup(struct pci_sys_data *sys)
488 */ 488 */
489 res[1].name = "PCI Memory Space"; 489 res[1].name = "PCI Memory Space";
490 res[1].flags = IORESOURCE_MEM; 490 res[1].flags = IORESOURCE_MEM;
491 res[1].start = ORION_PCI_MEM_BASE; 491 res[1].start = ORION_PCI_MEM_PHYS_BASE;
492 res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; 492 res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
493 if (request_resource(&iomem_resource, &res[1])) 493 if (request_resource(&iomem_resource, &res[1]))
494 panic("Request PCI Memory resource failed\n"); 494 panic("Request PCI Memory resource failed\n");
diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c
index 026d74325d01..e851b8ca5ac6 100644
--- a/arch/arm/mach-orion/rd88f5182-setup.c
+++ b/arch/arm/mach-orion/rd88f5182-setup.c
@@ -17,6 +17,7 @@
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/mtd/physmap.h> 18#include <linux/mtd/physmap.h>
19#include <linux/mv643xx_eth.h> 19#include <linux/mv643xx_eth.h>
20#include <linux/ata_platform.h>
20#include <linux/i2c.h> 21#include <linux/i2c.h>
21#include <asm/mach-types.h> 22#include <asm/mach-types.h>
22#include <asm/gpio.h> 23#include <asm/gpio.h>
@@ -230,6 +231,13 @@ static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
230}; 231};
231 232
232/***************************************************************************** 233/*****************************************************************************
234 * Sata
235 ****************************************************************************/
236static struct mv_sata_platform_data rd88f5182_sata_data = {
237 .n_ports = 2,
238};
239
240/*****************************************************************************
233 * General Setup 241 * General Setup
234 ****************************************************************************/ 242 ****************************************************************************/
235 243
@@ -255,8 +263,8 @@ static void __init rd88f5182_init(void)
255 /* 263 /*
256 * Open a special address decode windows for the PCIE WA. 264 * Open a special address decode windows for the PCIE WA.
257 */ 265 */
258 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 266 orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
259 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 267 orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
260 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 268 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
261 269
262 /* 270 /*
@@ -292,12 +300,13 @@ static void __init rd88f5182_init(void)
292 platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); 300 platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
293 i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); 301 i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
294 orion_eth_init(&rd88f5182_eth_data); 302 orion_eth_init(&rd88f5182_eth_data);
303 orion_sata_init(&rd88f5182_sata_data);
295} 304}
296 305
297MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") 306MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
298 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 307 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
299 .phys_io = ORION_REGS_BASE, 308 .phys_io = ORION_REGS_PHYS_BASE,
300 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 309 .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
301 .boot_params = 0x00000100, 310 .boot_params = 0x00000100,
302 .init_machine = rd88f5182_init, 311 .init_machine = rd88f5182_init,
303 .map_io = orion_map_io, 312 .map_io = orion_map_io,
diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c
index e3e930efd155..306dbcd1e37b 100644
--- a/arch/arm/mach-orion/ts209-setup.c
+++ b/arch/arm/mach-orion/ts209-setup.c
@@ -21,6 +21,7 @@
21#include <linux/input.h> 21#include <linux/input.h>
22#include <linux/i2c.h> 22#include <linux/i2c.h>
23#include <linux/serial_reg.h> 23#include <linux/serial_reg.h>
24#include <linux/ata_platform.h>
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
25#include <asm/gpio.h> 26#include <asm/gpio.h>
26#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
@@ -232,6 +233,14 @@ static struct platform_device qnap_ts209_button_device = {
232}; 233};
233 234
234/***************************************************************************** 235/*****************************************************************************
236 * SATA
237 ****************************************************************************/
238static struct mv_sata_platform_data qnap_ts209_sata_data = {
239 .n_ports = 2,
240};
241
242/*****************************************************************************
243
235 * General Setup 244 * General Setup
236 ****************************************************************************/ 245 ****************************************************************************/
237 246
@@ -244,7 +253,7 @@ static struct platform_device *qnap_ts209_devices[] __initdata = {
244 * QNAP TS-[12]09 specific power off method via UART1-attached PIC 253 * QNAP TS-[12]09 specific power off method via UART1-attached PIC
245 */ 254 */
246 255
247#define UART1_REG(x) (UART1_BASE + ((UART_##x) << 2)) 256#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
248 257
249static void qnap_ts209_power_off(void) 258static void qnap_ts209_power_off(void)
250{ 259{
@@ -282,8 +291,8 @@ static void __init qnap_ts209_init(void)
282 /* 291 /*
283 * Open a special address decode windows for the PCIE WA. 292 * Open a special address decode windows for the PCIE WA.
284 */ 293 */
285 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 294 orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
286 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 295 orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
287 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 296 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
288 297
289 /* 298 /*
@@ -321,12 +330,13 @@ static void __init qnap_ts209_init(void)
321 ARRAY_SIZE(qnap_ts209_devices)); 330 ARRAY_SIZE(qnap_ts209_devices));
322 i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); 331 i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
323 orion_eth_init(&qnap_ts209_eth_data); 332 orion_eth_init(&qnap_ts209_eth_data);
333 orion_sata_init(&qnap_ts209_sata_data);
324} 334}
325 335
326MACHINE_START(TS209, "QNAP TS-109/TS-209") 336MACHINE_START(TS209, "QNAP TS-109/TS-209")
327 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ 337 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
328 .phys_io = ORION_REGS_BASE, 338 .phys_io = ORION_REGS_PHYS_BASE,
329 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 339 .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
330 .boot_params = 0x00000100, 340 .boot_params = 0x00000100,
331 .init_machine = qnap_ts209_init, 341 .init_machine = qnap_ts209_init,
332 .map_io = orion_map_io, 342 .map_io = orion_map_io,
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index e47e67c11afe..7cd9ef8deb02 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -266,8 +266,6 @@ static void pxa3xx_cpu_standby(unsigned int pwrmode)
266 266
267 AD2D0ER = 0; 267 AD2D0ER = 0;
268 AD2D1ER = 0; 268 AD2D1ER = 0;
269
270 printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
271} 269}
272 270
273/* 271/*
@@ -515,6 +513,14 @@ static int __init pxa3xx_init(void)
515 int i, ret = 0; 513 int i, ret = 0;
516 514
517 if (cpu_is_pxa3xx()) { 515 if (cpu_is_pxa3xx()) {
516 /*
517 * clear RDH bit every time after reset
518 *
519 * Note: the last 3 bits DxS are write-1-to-clear so carefully
520 * preserve them here in case they will be referenced later
521 */
522 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
523
518 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 524 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
519 525
520 if ((ret = pxa_init_dma(32))) 526 if ((ret = pxa_init_dma(32)))
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 2549129aabc6..ce17df31b845 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
19obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 19obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
20obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o 20obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
21obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o 21obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
22obj-$(CONFIG_I2C_OMAP) += i2c.o
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index dcbba07cf98a..a46676db8113 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -6,7 +6,7 @@
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations 7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com> 8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc. 9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> 10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. 11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 * 12 *
@@ -33,12 +33,14 @@
33 33
34#include <asm/arch/tc.h> 34#include <asm/arch/tc.h>
35 35
36#define DEBUG_PRINTS 36#undef DEBUG
37#undef DEBUG_PRINTS 37
38#ifdef DEBUG_PRINTS 38#ifndef CONFIG_ARCH_OMAP1
39#define debug_printk(x) printk x 39enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
40#else 40 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
41#define debug_printk(x) 41};
42
43enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
42#endif 44#endif
43 45
44#define OMAP_DMA_ACTIVE 0x01 46#define OMAP_DMA_ACTIVE 0x01
@@ -57,9 +59,66 @@ struct omap_dma_lch {
57 const char *dev_name; 59 const char *dev_name;
58 void (* callback)(int lch, u16 ch_status, void *data); 60 void (* callback)(int lch, u16 ch_status, void *data);
59 void *data; 61 void *data;
62
63#ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
65 int prev_linked_ch;
66 int next_linked_ch;
67 int state;
68 int chain_id;
69
70 int status;
71#endif
60 long flags; 72 long flags;
61}; 73};
62 74
75#ifndef CONFIG_ARCH_OMAP1
76struct dma_link_info {
77 int *linked_dmach_q;
78 int no_of_lchs_linked;
79
80 int q_count;
81 int q_tail;
82 int q_head;
83
84 int chain_state;
85 int chain_mode;
86
87};
88
89static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
90
91/* Chain handling macros */
92#define OMAP_DMA_CHAIN_QINIT(chain_id) \
93 do { \
94 dma_linked_lch[chain_id].q_head = \
95 dma_linked_lch[chain_id].q_tail = \
96 dma_linked_lch[chain_id].q_count = 0; \
97 } while (0)
98#define OMAP_DMA_CHAIN_QFULL(chain_id) \
99 (dma_linked_lch[chain_id].no_of_lchs_linked == \
100 dma_linked_lch[chain_id].q_count)
101#define OMAP_DMA_CHAIN_QLAST(chain_id) \
102 do { \
103 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
104 dma_linked_lch[chain_id].q_count) \
105 } while (0)
106#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
107 (0 == dma_linked_lch[chain_id].q_count)
108#define __OMAP_DMA_CHAIN_INCQ(end) \
109 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
110#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
111 do { \
112 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
113 dma_linked_lch[chain_id].q_count--; \
114 } while (0)
115
116#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
117 do { \
118 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
119 dma_linked_lch[chain_id].q_count++; \
120 } while (0)
121#endif
63static int dma_chan_count; 122static int dma_chan_count;
64 123
65static spinlock_t dma_chan_lock; 124static spinlock_t dma_chan_lock;
@@ -73,6 +132,10 @@ static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
73 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD 132 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
74}; 133};
75 134
135static inline void disable_lnk(int lch);
136static void omap_disable_channel_irq(int lch);
137static inline void omap_enable_channel_irq(int lch);
138
76#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ 139#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
77 __FUNCTION__); 140 __FUNCTION__);
78 141
@@ -148,7 +211,7 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
148 omap_writel(l, reg); 211 omap_writel(l, reg);
149 } 212 }
150 213
151 if (cpu_is_omap24xx()) { 214 if (cpu_class_is_omap2()) {
152 if (priority) 215 if (priority)
153 OMAP_DMA_CCR_REG(lch) |= (1 << 6); 216 OMAP_DMA_CCR_REG(lch) |= (1 << 6);
154 else 217 else
@@ -173,7 +236,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
173 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2; 236 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
174 } 237 }
175 238
176 if (cpu_is_omap24xx() && dma_trigger) { 239 if (cpu_class_is_omap2() && dma_trigger) {
177 u32 val = OMAP_DMA_CCR_REG(lch); 240 u32 val = OMAP_DMA_CCR_REG(lch);
178 241
179 val &= ~(3 << 19); 242 val &= ~(3 << 19);
@@ -213,7 +276,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
213 276
214 BUG_ON(omap_dma_in_1510_mode()); 277 BUG_ON(omap_dma_in_1510_mode());
215 278
216 if (cpu_is_omap24xx()) { 279 if (cpu_class_is_omap2()) {
217 REVISIT_24XX(); 280 REVISIT_24XX();
218 return; 281 return;
219 } 282 }
@@ -245,7 +308,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
245 308
246void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) 309void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
247{ 310{
248 if (cpu_is_omap24xx()) { 311 if (cpu_class_is_omap2()) {
249 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16); 312 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
250 OMAP_DMA_CSDP_REG(lch) |= (mode << 16); 313 OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
251 } 314 }
@@ -269,7 +332,7 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
269 OMAP1_DMA_CSSA_L_REG(lch) = src_start; 332 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
270 } 333 }
271 334
272 if (cpu_is_omap24xx()) 335 if (cpu_class_is_omap2())
273 OMAP2_DMA_CSSA_REG(lch) = src_start; 336 OMAP2_DMA_CSSA_REG(lch) = src_start;
274 337
275 OMAP_DMA_CSEI_REG(lch) = src_ei; 338 OMAP_DMA_CSEI_REG(lch) = src_ei;
@@ -289,11 +352,14 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
289 omap_set_dma_dest_params(lch, params->dst_port, 352 omap_set_dma_dest_params(lch, params->dst_port,
290 params->dst_amode, params->dst_start, 353 params->dst_amode, params->dst_start,
291 params->dst_ei, params->dst_fi); 354 params->dst_ei, params->dst_fi);
355 if (params->read_prio || params->write_prio)
356 omap_dma_set_prio_lch(lch, params->read_prio,
357 params->write_prio);
292} 358}
293 359
294void omap_set_dma_src_index(int lch, int eidx, int fidx) 360void omap_set_dma_src_index(int lch, int eidx, int fidx)
295{ 361{
296 if (cpu_is_omap24xx()) { 362 if (cpu_class_is_omap2()) {
297 REVISIT_24XX(); 363 REVISIT_24XX();
298 return; 364 return;
299 } 365 }
@@ -317,13 +383,13 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
317 case OMAP_DMA_DATA_BURST_DIS: 383 case OMAP_DMA_DATA_BURST_DIS:
318 break; 384 break;
319 case OMAP_DMA_DATA_BURST_4: 385 case OMAP_DMA_DATA_BURST_4:
320 if (cpu_is_omap24xx()) 386 if (cpu_class_is_omap2())
321 burst = 0x1; 387 burst = 0x1;
322 else 388 else
323 burst = 0x2; 389 burst = 0x2;
324 break; 390 break;
325 case OMAP_DMA_DATA_BURST_8: 391 case OMAP_DMA_DATA_BURST_8:
326 if (cpu_is_omap24xx()) { 392 if (cpu_class_is_omap2()) {
327 burst = 0x2; 393 burst = 0x2;
328 break; 394 break;
329 } 395 }
@@ -332,7 +398,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
332 * fall through 398 * fall through
333 */ 399 */
334 case OMAP_DMA_DATA_BURST_16: 400 case OMAP_DMA_DATA_BURST_16:
335 if (cpu_is_omap24xx()) { 401 if (cpu_class_is_omap2()) {
336 burst = 0x3; 402 burst = 0x3;
337 break; 403 break;
338 } 404 }
@@ -363,7 +429,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
363 OMAP1_DMA_CDSA_L_REG(lch) = dest_start; 429 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
364 } 430 }
365 431
366 if (cpu_is_omap24xx()) 432 if (cpu_class_is_omap2())
367 OMAP2_DMA_CDSA_REG(lch) = dest_start; 433 OMAP2_DMA_CDSA_REG(lch) = dest_start;
368 434
369 OMAP_DMA_CDEI_REG(lch) = dst_ei; 435 OMAP_DMA_CDEI_REG(lch) = dst_ei;
@@ -372,7 +438,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
372 438
373void omap_set_dma_dest_index(int lch, int eidx, int fidx) 439void omap_set_dma_dest_index(int lch, int eidx, int fidx)
374{ 440{
375 if (cpu_is_omap24xx()) { 441 if (cpu_class_is_omap2()) {
376 REVISIT_24XX(); 442 REVISIT_24XX();
377 return; 443 return;
378 } 444 }
@@ -396,19 +462,19 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
396 case OMAP_DMA_DATA_BURST_DIS: 462 case OMAP_DMA_DATA_BURST_DIS:
397 break; 463 break;
398 case OMAP_DMA_DATA_BURST_4: 464 case OMAP_DMA_DATA_BURST_4:
399 if (cpu_is_omap24xx()) 465 if (cpu_class_is_omap2())
400 burst = 0x1; 466 burst = 0x1;
401 else 467 else
402 burst = 0x2; 468 burst = 0x2;
403 break; 469 break;
404 case OMAP_DMA_DATA_BURST_8: 470 case OMAP_DMA_DATA_BURST_8:
405 if (cpu_is_omap24xx()) 471 if (cpu_class_is_omap2())
406 burst = 0x2; 472 burst = 0x2;
407 else 473 else
408 burst = 0x3; 474 burst = 0x3;
409 break; 475 break;
410 case OMAP_DMA_DATA_BURST_16: 476 case OMAP_DMA_DATA_BURST_16:
411 if (cpu_is_omap24xx()) { 477 if (cpu_class_is_omap2()) {
412 burst = 0x3; 478 burst = 0x3;
413 break; 479 break;
414 } 480 }
@@ -430,7 +496,7 @@ static inline void omap_enable_channel_irq(int lch)
430 /* Clear CSR */ 496 /* Clear CSR */
431 if (cpu_class_is_omap1()) 497 if (cpu_class_is_omap1())
432 status = OMAP_DMA_CSR_REG(lch); 498 status = OMAP_DMA_CSR_REG(lch);
433 else if (cpu_is_omap24xx()) 499 else if (cpu_class_is_omap2())
434 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; 500 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
435 501
436 /* Enable some nice interrupts. */ 502 /* Enable some nice interrupts. */
@@ -441,7 +507,7 @@ static inline void omap_enable_channel_irq(int lch)
441 507
442static void omap_disable_channel_irq(int lch) 508static void omap_disable_channel_irq(int lch)
443{ 509{
444 if (cpu_is_omap24xx()) 510 if (cpu_class_is_omap2())
445 OMAP_DMA_CICR_REG(lch) = 0; 511 OMAP_DMA_CICR_REG(lch) = 0;
446} 512}
447 513
@@ -464,6 +530,12 @@ static inline void enable_lnk(int lch)
464 if (dma_chan[lch].next_lch != -1) 530 if (dma_chan[lch].next_lch != -1)
465 OMAP_DMA_CLNK_CTRL_REG(lch) = 531 OMAP_DMA_CLNK_CTRL_REG(lch) =
466 dma_chan[lch].next_lch | (1 << 15); 532 dma_chan[lch].next_lch | (1 << 15);
533
534#ifndef CONFIG_ARCH_OMAP1
535 if (dma_chan[lch].next_linked_ch != -1)
536 OMAP_DMA_CLNK_CTRL_REG(lch) =
537 dma_chan[lch].next_linked_ch | (1 << 15);
538#endif
467} 539}
468 540
469static inline void disable_lnk(int lch) 541static inline void disable_lnk(int lch)
@@ -475,7 +547,7 @@ static inline void disable_lnk(int lch)
475 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14; 547 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
476 } 548 }
477 549
478 if (cpu_is_omap24xx()) { 550 if (cpu_class_is_omap2()) {
479 omap_disable_channel_irq(lch); 551 omap_disable_channel_irq(lch);
480 /* Clear the ENABLE_LNK bit */ 552 /* Clear the ENABLE_LNK bit */
481 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15); 553 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
@@ -488,7 +560,7 @@ static inline void omap2_enable_irq_lch(int lch)
488{ 560{
489 u32 val; 561 u32 val;
490 562
491 if (!cpu_is_omap24xx()) 563 if (!cpu_class_is_omap2())
492 return; 564 return;
493 565
494 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); 566 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
@@ -522,7 +594,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
522 if (cpu_class_is_omap1()) 594 if (cpu_class_is_omap1())
523 clear_lch_regs(free_ch); 595 clear_lch_regs(free_ch);
524 596
525 if (cpu_is_omap24xx()) 597 if (cpu_class_is_omap2())
526 omap_clear_dma(free_ch); 598 omap_clear_dma(free_ch);
527 599
528 spin_unlock_irqrestore(&dma_chan_lock, flags); 600 spin_unlock_irqrestore(&dma_chan_lock, flags);
@@ -530,11 +602,14 @@ int omap_request_dma(int dev_id, const char *dev_name,
530 chan->dev_name = dev_name; 602 chan->dev_name = dev_name;
531 chan->callback = callback; 603 chan->callback = callback;
532 chan->data = data; 604 chan->data = data;
605#ifndef CONFIG_ARCH_OMAP1
606 chan->chain_id = -1;
607#endif
533 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; 608 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
534 609
535 if (cpu_class_is_omap1()) 610 if (cpu_class_is_omap1())
536 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; 611 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
537 else if (cpu_is_omap24xx()) 612 else if (cpu_class_is_omap2())
538 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | 613 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
539 OMAP2_DMA_TRANS_ERR_IRQ; 614 OMAP2_DMA_TRANS_ERR_IRQ;
540 615
@@ -551,7 +626,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
551 OMAP_DMA_CCR_REG(free_ch) = dev_id; 626 OMAP_DMA_CCR_REG(free_ch) = dev_id;
552 } 627 }
553 628
554 if (cpu_is_omap24xx()) { 629 if (cpu_class_is_omap2()) {
555 omap2_enable_irq_lch(free_ch); 630 omap2_enable_irq_lch(free_ch);
556 631
557 omap_enable_channel_irq(free_ch); 632 omap_enable_channel_irq(free_ch);
@@ -588,7 +663,7 @@ void omap_free_dma(int lch)
588 OMAP_DMA_CCR_REG(lch) = 0; 663 OMAP_DMA_CCR_REG(lch) = 0;
589 } 664 }
590 665
591 if (cpu_is_omap24xx()) { 666 if (cpu_class_is_omap2()) {
592 u32 val; 667 u32 val;
593 /* Disable interrupts */ 668 /* Disable interrupts */
594 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); 669 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
@@ -608,6 +683,67 @@ void omap_free_dma(int lch)
608 } 683 }
609} 684}
610 685
686/**
687 * @brief omap_dma_set_global_params : Set global priority settings for dma
688 *
689 * @param arb_rate
690 * @param max_fifo_depth
691 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
692 * DMA_THREAD_RESERVE_ONET
693 * DMA_THREAD_RESERVE_TWOT
694 * DMA_THREAD_RESERVE_THREET
695 */
696void
697omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
698{
699 u32 reg;
700
701 if (!cpu_class_is_omap2()) {
702 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __FUNCTION__);
703 return;
704 }
705
706 if (arb_rate == 0)
707 arb_rate = 1;
708
709 reg = (arb_rate & 0xff) << 16;
710 reg |= (0xff & max_fifo_depth);
711
712 omap_writel(reg, OMAP_DMA4_GCR_REG);
713}
714EXPORT_SYMBOL(omap_dma_set_global_params);
715
716/**
717 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
718 *
719 * @param lch
720 * @param read_prio - Read priority
721 * @param write_prio - Write priority
722 * Both of the above can be set with one of the following values :
723 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
724 */
725int
726omap_dma_set_prio_lch(int lch, unsigned char read_prio,
727 unsigned char write_prio)
728{
729 u32 w;
730
731 if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) {
732 printk(KERN_ERR "Invalid channel id\n");
733 return -EINVAL;
734 }
735 w = OMAP_DMA_CCR_REG(lch);
736 w &= ~((1 << 6) | (1 << 26));
737 if (cpu_is_omap2430() || cpu_is_omap34xx())
738 w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
739 else
740 w |= ((read_prio & 0x1) << 6);
741
742 OMAP_DMA_CCR_REG(lch) = w;
743 return 0;
744}
745EXPORT_SYMBOL(omap_dma_set_prio_lch);
746
611/* 747/*
612 * Clears any DMA state so the DMA engine is ready to restart with new buffers 748 * Clears any DMA state so the DMA engine is ready to restart with new buffers
613 * through omap_start_dma(). Any buffers in flight are discarded. 749 * through omap_start_dma(). Any buffers in flight are discarded.
@@ -626,9 +762,9 @@ void omap_clear_dma(int lch)
626 status = OMAP_DMA_CSR_REG(lch); 762 status = OMAP_DMA_CSR_REG(lch);
627 } 763 }
628 764
629 if (cpu_is_omap24xx()) { 765 if (cpu_class_is_omap2()) {
630 int i; 766 int i;
631 u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80; 767 u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80;
632 for (i = 0; i < 0x44; i += 4) 768 for (i = 0; i < 0x44; i += 4)
633 omap_writel(0, lch_base + i); 769 omap_writel(0, lch_base + i);
634 } 770 }
@@ -662,7 +798,7 @@ void omap_start_dma(int lch)
662 798
663 cur_lch = next_lch; 799 cur_lch = next_lch;
664 } while (next_lch != -1); 800 } while (next_lch != -1);
665 } else if (cpu_is_omap24xx()) { 801 } else if (cpu_class_is_omap2()) {
666 /* Errata: Need to write lch even if not using chaining */ 802 /* Errata: Need to write lch even if not using chaining */
667 OMAP_DMA_CLNK_CTRL_REG(lch) = lch; 803 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
668 } 804 }
@@ -753,7 +889,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
753 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) | 889 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
754 (OMAP1_DMA_CSSA_U_REG(lch) << 16)); 890 (OMAP1_DMA_CSSA_U_REG(lch) << 16));
755 891
756 if (cpu_is_omap24xx()) 892 if (cpu_class_is_omap2())
757 offset = OMAP_DMA_CSAC_REG(lch); 893 offset = OMAP_DMA_CSAC_REG(lch);
758 894
759 return offset; 895 return offset;
@@ -775,8 +911,8 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
775 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) | 911 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
776 (OMAP1_DMA_CDSA_U_REG(lch) << 16)); 912 (OMAP1_DMA_CDSA_U_REG(lch) << 16));
777 913
778 if (cpu_is_omap24xx()) 914 if (cpu_class_is_omap2())
779 offset = OMAP2_DMA_CDSA_REG(lch); 915 offset = OMAP_DMA_CDAC_REG(lch);
780 916
781 return offset; 917 return offset;
782} 918}
@@ -859,6 +995,605 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
859 dma_chan[lch_head].next_lch = -1; 995 dma_chan[lch_head].next_lch = -1;
860} 996}
861 997
998#ifndef CONFIG_ARCH_OMAP1
999/* Create chain of DMA channesls */
1000static void create_dma_lch_chain(int lch_head, int lch_queue)
1001{
1002 u32 w;
1003
1004 /* Check if this is the first link in chain */
1005 if (dma_chan[lch_head].next_linked_ch == -1) {
1006 dma_chan[lch_head].next_linked_ch = lch_queue;
1007 dma_chan[lch_head].prev_linked_ch = lch_queue;
1008 dma_chan[lch_queue].next_linked_ch = lch_head;
1009 dma_chan[lch_queue].prev_linked_ch = lch_head;
1010 }
1011
1012 /* a link exists, link the new channel in circular chain */
1013 else {
1014 dma_chan[lch_queue].next_linked_ch =
1015 dma_chan[lch_head].next_linked_ch;
1016 dma_chan[lch_queue].prev_linked_ch = lch_head;
1017 dma_chan[lch_head].next_linked_ch = lch_queue;
1018 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1019 lch_queue;
1020 }
1021
1022 w = OMAP_DMA_CLNK_CTRL_REG(lch_head);
1023 w &= ~(0x0f);
1024 w |= lch_queue;
1025 OMAP_DMA_CLNK_CTRL_REG(lch_head) = w;
1026
1027 w = OMAP_DMA_CLNK_CTRL_REG(lch_queue);
1028 w &= ~(0x0f);
1029 w |= (dma_chan[lch_queue].next_linked_ch);
1030 OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w;
1031}
1032
1033/**
1034 * @brief omap_request_dma_chain : Request a chain of DMA channels
1035 *
1036 * @param dev_id - Device id using the dma channel
1037 * @param dev_name - Device name
1038 * @param callback - Call back function
1039 * @chain_id -
1040 * @no_of_chans - Number of channels requested
1041 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1042 * OMAP_DMA_DYNAMIC_CHAIN
1043 * @params - Channel parameters
1044 *
1045 * @return - Succes : 0
1046 * Failure: -EINVAL/-ENOMEM
1047 */
1048int omap_request_dma_chain(int dev_id, const char *dev_name,
1049 void (*callback) (int chain_id, u16 ch_status,
1050 void *data),
1051 int *chain_id, int no_of_chans, int chain_mode,
1052 struct omap_dma_channel_params params)
1053{
1054 int *channels;
1055 int i, err;
1056
1057 /* Is the chain mode valid ? */
1058 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1059 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1060 printk(KERN_ERR "Invalid chain mode requested\n");
1061 return -EINVAL;
1062 }
1063
1064 if (unlikely((no_of_chans < 1
1065 || no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) {
1066 printk(KERN_ERR "Invalid Number of channels requested\n");
1067 return -EINVAL;
1068 }
1069
1070 /* Allocate a queue to maintain the status of the channels
1071 * in the chain */
1072 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1073 if (channels == NULL) {
1074 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1075 return -ENOMEM;
1076 }
1077
1078 /* request and reserve DMA channels for the chain */
1079 for (i = 0; i < no_of_chans; i++) {
1080 err = omap_request_dma(dev_id, dev_name,
1081 callback, 0, &channels[i]);
1082 if (err < 0) {
1083 int j;
1084 for (j = 0; j < i; j++)
1085 omap_free_dma(channels[j]);
1086 kfree(channels);
1087 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1088 return err;
1089 }
1090 dma_chan[channels[i]].next_linked_ch = -1;
1091 dma_chan[channels[i]].prev_linked_ch = -1;
1092 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1093
1094 /*
1095 * Allowing client drivers to set common parameters now,
1096 * so that later only relevant (src_start, dest_start
1097 * and element count) can be set
1098 */
1099 omap_set_dma_params(channels[i], &params);
1100 }
1101
1102 *chain_id = channels[0];
1103 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1104 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1105 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1106 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1107
1108 for (i = 0; i < no_of_chans; i++)
1109 dma_chan[channels[i]].chain_id = *chain_id;
1110
1111 /* Reset the Queue pointers */
1112 OMAP_DMA_CHAIN_QINIT(*chain_id);
1113
1114 /* Set up the chain */
1115 if (no_of_chans == 1)
1116 create_dma_lch_chain(channels[0], channels[0]);
1117 else {
1118 for (i = 0; i < (no_of_chans - 1); i++)
1119 create_dma_lch_chain(channels[i], channels[i + 1]);
1120 }
1121 return 0;
1122}
1123EXPORT_SYMBOL(omap_request_dma_chain);
1124
1125/**
1126 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1127 * params after setting it. Dont do this while dma is running!!
1128 *
1129 * @param chain_id - Chained logical channel id.
1130 * @param params
1131 *
1132 * @return - Success : 0
1133 * Failure : -EINVAL
1134 */
1135int omap_modify_dma_chain_params(int chain_id,
1136 struct omap_dma_channel_params params)
1137{
1138 int *channels;
1139 u32 i;
1140
1141 /* Check for input params */
1142 if (unlikely((chain_id < 0
1143 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1144 printk(KERN_ERR "Invalid chain id\n");
1145 return -EINVAL;
1146 }
1147
1148 /* Check if the chain exists */
1149 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1150 printk(KERN_ERR "Chain doesn't exists\n");
1151 return -EINVAL;
1152 }
1153 channels = dma_linked_lch[chain_id].linked_dmach_q;
1154
1155 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1156 /*
1157 * Allowing client drivers to set common parameters now,
1158 * so that later only relevant (src_start, dest_start
1159 * and element count) can be set
1160 */
1161 omap_set_dma_params(channels[i], &params);
1162 }
1163 return 0;
1164}
1165EXPORT_SYMBOL(omap_modify_dma_chain_params);
1166
1167/**
1168 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1169 *
1170 * @param chain_id
1171 *
1172 * @return - Success : 0
1173 * Failure : -EINVAL
1174 */
1175int omap_free_dma_chain(int chain_id)
1176{
1177 int *channels;
1178 u32 i;
1179
1180 /* Check for input params */
1181 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1182 printk(KERN_ERR "Invalid chain id\n");
1183 return -EINVAL;
1184 }
1185
1186 /* Check if the chain exists */
1187 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1188 printk(KERN_ERR "Chain doesn't exists\n");
1189 return -EINVAL;
1190 }
1191
1192 channels = dma_linked_lch[chain_id].linked_dmach_q;
1193 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1194 dma_chan[channels[i]].next_linked_ch = -1;
1195 dma_chan[channels[i]].prev_linked_ch = -1;
1196 dma_chan[channels[i]].chain_id = -1;
1197 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1198 omap_free_dma(channels[i]);
1199 }
1200
1201 kfree(channels);
1202
1203 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1204 dma_linked_lch[chain_id].chain_mode = -1;
1205 dma_linked_lch[chain_id].chain_state = -1;
1206 return (0);
1207}
1208EXPORT_SYMBOL(omap_free_dma_chain);
1209
1210/**
1211 * @brief omap_dma_chain_status - Check if the chain is in
1212 * active / inactive state.
1213 * @param chain_id
1214 *
1215 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1216 * Failure : -EINVAL
1217 */
1218int omap_dma_chain_status(int chain_id)
1219{
1220 /* Check for input params */
1221 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1222 printk(KERN_ERR "Invalid chain id\n");
1223 return -EINVAL;
1224 }
1225
1226 /* Check if the chain exists */
1227 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1228 printk(KERN_ERR "Chain doesn't exists\n");
1229 return -EINVAL;
1230 }
1231 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1232 dma_linked_lch[chain_id].q_count);
1233
1234 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1235 return OMAP_DMA_CHAIN_INACTIVE;
1236 return OMAP_DMA_CHAIN_ACTIVE;
1237}
1238EXPORT_SYMBOL(omap_dma_chain_status);
1239
1240/**
1241 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1242 * set the params and start the transfer.
1243 *
1244 * @param chain_id
1245 * @param src_start - buffer start address
1246 * @param dest_start - Dest address
1247 * @param elem_count
1248 * @param frame_count
1249 * @param callbk_data - channel callback parameter data.
1250 *
1251 * @return - Success : start_dma status
1252 * Failure: -EINVAL/-EBUSY
1253 */
1254int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1255 int elem_count, int frame_count, void *callbk_data)
1256{
1257 int *channels;
1258 u32 w, lch;
1259 int start_dma = 0;
1260
1261 /* if buffer size is less than 1 then there is
1262 * no use of starting the chain */
1263 if (elem_count < 1) {
1264 printk(KERN_ERR "Invalid buffer size\n");
1265 return -EINVAL;
1266 }
1267
1268 /* Check for input params */
1269 if (unlikely((chain_id < 0
1270 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1271 printk(KERN_ERR "Invalid chain id\n");
1272 return -EINVAL;
1273 }
1274
1275 /* Check if the chain exists */
1276 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1277 printk(KERN_ERR "Chain doesn't exist\n");
1278 return -EINVAL;
1279 }
1280
1281 /* Check if all the channels in chain are in use */
1282 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1283 return -EBUSY;
1284
1285 /* Frame count may be negative in case of indexed transfers */
1286 channels = dma_linked_lch[chain_id].linked_dmach_q;
1287
1288 /* Get a free channel */
1289 lch = channels[dma_linked_lch[chain_id].q_tail];
1290
1291 /* Store the callback data */
1292 dma_chan[lch].data = callbk_data;
1293
1294 /* Increment the q_tail */
1295 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1296
1297 /* Set the params to the free channel */
1298 if (src_start != 0)
1299 OMAP2_DMA_CSSA_REG(lch) = src_start;
1300 if (dest_start != 0)
1301 OMAP2_DMA_CDSA_REG(lch) = dest_start;
1302
1303 /* Write the buffer size */
1304 OMAP_DMA_CEN_REG(lch) = elem_count;
1305 OMAP_DMA_CFN_REG(lch) = frame_count;
1306
1307 /* If the chain is dynamically linked,
1308 * then we may have to start the chain if its not active */
1309 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1310
1311 /* In Dynamic chain, if the chain is not started,
1312 * queue the channel */
1313 if (dma_linked_lch[chain_id].chain_state ==
1314 DMA_CHAIN_NOTSTARTED) {
1315 /* Enable the link in previous channel */
1316 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1317 DMA_CH_QUEUED)
1318 enable_lnk(dma_chan[lch].prev_linked_ch);
1319 dma_chan[lch].state = DMA_CH_QUEUED;
1320 }
1321
1322 /* Chain is already started, make sure its active,
1323 * if not then start the chain */
1324 else {
1325 start_dma = 1;
1326
1327 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1328 DMA_CH_STARTED) {
1329 enable_lnk(dma_chan[lch].prev_linked_ch);
1330 dma_chan[lch].state = DMA_CH_QUEUED;
1331 start_dma = 0;
1332 if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG
1333 (dma_chan[lch].prev_linked_ch)))) {
1334 disable_lnk(dma_chan[lch].
1335 prev_linked_ch);
1336 pr_debug("\n prev ch is stopped\n");
1337 start_dma = 1;
1338 }
1339 }
1340
1341 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1342 == DMA_CH_QUEUED) {
1343 enable_lnk(dma_chan[lch].prev_linked_ch);
1344 dma_chan[lch].state = DMA_CH_QUEUED;
1345 start_dma = 0;
1346 }
1347 omap_enable_channel_irq(lch);
1348
1349 w = OMAP_DMA_CCR_REG(lch);
1350
1351 if ((0 == (w & (1 << 24))))
1352 w &= ~(1 << 25);
1353 else
1354 w |= (1 << 25);
1355 if (start_dma == 1) {
1356 if (0 == (w & (1 << 7))) {
1357 w |= (1 << 7);
1358 dma_chan[lch].state = DMA_CH_STARTED;
1359 pr_debug("starting %d\n", lch);
1360 OMAP_DMA_CCR_REG(lch) = w;
1361 } else
1362 start_dma = 0;
1363 } else {
1364 if (0 == (w & (1 << 7)))
1365 OMAP_DMA_CCR_REG(lch) = w;
1366 }
1367 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1368 }
1369 }
1370 return start_dma;
1371}
1372EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1373
1374/**
1375 * @brief omap_start_dma_chain_transfers - Start the chain
1376 *
1377 * @param chain_id
1378 *
1379 * @return - Success : 0
1380 * Failure : -EINVAL/-EBUSY
1381 */
1382int omap_start_dma_chain_transfers(int chain_id)
1383{
1384 int *channels;
1385 u32 w, i;
1386
1387 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1388 printk(KERN_ERR "Invalid chain id\n");
1389 return -EINVAL;
1390 }
1391
1392 channels = dma_linked_lch[chain_id].linked_dmach_q;
1393
1394 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1395 printk(KERN_ERR "Chain is already started\n");
1396 return -EBUSY;
1397 }
1398
1399 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1400 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1401 i++) {
1402 enable_lnk(channels[i]);
1403 omap_enable_channel_irq(channels[i]);
1404 }
1405 } else {
1406 omap_enable_channel_irq(channels[0]);
1407 }
1408
1409 w = OMAP_DMA_CCR_REG(channels[0]);
1410 w |= (1 << 7);
1411 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1412 dma_chan[channels[0]].state = DMA_CH_STARTED;
1413
1414 if ((0 == (w & (1 << 24))))
1415 w &= ~(1 << 25);
1416 else
1417 w |= (1 << 25);
1418 OMAP_DMA_CCR_REG(channels[0]) = w;
1419
1420 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1421 return 0;
1422}
1423EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1424
1425/**
1426 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1427 *
1428 * @param chain_id
1429 *
1430 * @return - Success : 0
1431 * Failure : EINVAL
1432 */
1433int omap_stop_dma_chain_transfers(int chain_id)
1434{
1435 int *channels;
1436 u32 w, i;
1437 u32 sys_cf;
1438
1439 /* Check for input params */
1440 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1441 printk(KERN_ERR "Invalid chain id\n");
1442 return -EINVAL;
1443 }
1444
1445 /* Check if the chain exists */
1446 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1447 printk(KERN_ERR "Chain doesn't exists\n");
1448 return -EINVAL;
1449 }
1450 channels = dma_linked_lch[chain_id].linked_dmach_q;
1451
1452 /* DMA Errata:
1453 * Special programming model needed to disable DMA before end of block
1454 */
1455 sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG);
1456 w = sys_cf;
1457 /* Middle mode reg set no Standby */
1458 w &= ~((1 << 12)|(1 << 13));
1459 omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG);
1460
1461 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1462
1463 /* Stop the Channel transmission */
1464 w = OMAP_DMA_CCR_REG(channels[i]);
1465 w &= ~(1 << 7);
1466 OMAP_DMA_CCR_REG(channels[i]) = w;
1467
1468 /* Disable the link in all the channels */
1469 disable_lnk(channels[i]);
1470 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1471
1472 }
1473 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1474
1475 /* Reset the Queue pointers */
1476 OMAP_DMA_CHAIN_QINIT(chain_id);
1477
1478 /* Errata - put in the old value */
1479 omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG);
1480 return 0;
1481}
1482EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1483
1484/* Get the index of the ongoing DMA in chain */
1485/**
1486 * @brief omap_get_dma_chain_index - Get the element and frame index
1487 * of the ongoing DMA in chain
1488 *
1489 * @param chain_id
1490 * @param ei - Element index
1491 * @param fi - Frame index
1492 *
1493 * @return - Success : 0
1494 * Failure : -EINVAL
1495 */
1496int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1497{
1498 int lch;
1499 int *channels;
1500
1501 /* Check for input params */
1502 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1503 printk(KERN_ERR "Invalid chain id\n");
1504 return -EINVAL;
1505 }
1506
1507 /* Check if the chain exists */
1508 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1509 printk(KERN_ERR "Chain doesn't exists\n");
1510 return -EINVAL;
1511 }
1512 if ((!ei) || (!fi))
1513 return -EINVAL;
1514
1515 channels = dma_linked_lch[chain_id].linked_dmach_q;
1516
1517 /* Get the current channel */
1518 lch = channels[dma_linked_lch[chain_id].q_head];
1519
1520 *ei = OMAP2_DMA_CCEN_REG(lch);
1521 *fi = OMAP2_DMA_CCFN_REG(lch);
1522
1523 return 0;
1524}
1525EXPORT_SYMBOL(omap_get_dma_chain_index);
1526
1527/**
1528 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1529 * ongoing DMA in chain
1530 *
1531 * @param chain_id
1532 *
1533 * @return - Success : Destination position
1534 * Failure : -EINVAL
1535 */
1536int omap_get_dma_chain_dst_pos(int chain_id)
1537{
1538 int lch;
1539 int *channels;
1540
1541 /* Check for input params */
1542 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1543 printk(KERN_ERR "Invalid chain id\n");
1544 return -EINVAL;
1545 }
1546
1547 /* Check if the chain exists */
1548 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1549 printk(KERN_ERR "Chain doesn't exists\n");
1550 return -EINVAL;
1551 }
1552
1553 channels = dma_linked_lch[chain_id].linked_dmach_q;
1554
1555 /* Get the current channel */
1556 lch = channels[dma_linked_lch[chain_id].q_head];
1557
1558 return (OMAP_DMA_CDAC_REG(lch));
1559}
1560EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1561
1562/**
1563 * @brief omap_get_dma_chain_src_pos - Get the source position
1564 * of the ongoing DMA in chain
1565 * @param chain_id
1566 *
1567 * @return - Success : Destination position
1568 * Failure : -EINVAL
1569 */
1570int omap_get_dma_chain_src_pos(int chain_id)
1571{
1572 int lch;
1573 int *channels;
1574
1575 /* Check for input params */
1576 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1577 printk(KERN_ERR "Invalid chain id\n");
1578 return -EINVAL;
1579 }
1580
1581 /* Check if the chain exists */
1582 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1583 printk(KERN_ERR "Chain doesn't exists\n");
1584 return -EINVAL;
1585 }
1586
1587 channels = dma_linked_lch[chain_id].linked_dmach_q;
1588
1589 /* Get the current channel */
1590 lch = channels[dma_linked_lch[chain_id].q_head];
1591
1592 return (OMAP_DMA_CSAC_REG(lch));
1593}
1594EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1595#endif
1596
862/*----------------------------------------------------------------------------*/ 1597/*----------------------------------------------------------------------------*/
863 1598
864#ifdef CONFIG_ARCH_OMAP1 1599#ifdef CONFIG_ARCH_OMAP1
@@ -919,7 +1654,7 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
919#define omap1_dma_irq_handler NULL 1654#define omap1_dma_irq_handler NULL
920#endif 1655#endif
921 1656
922#ifdef CONFIG_ARCH_OMAP2 1657#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
923 1658
924static int omap2_dma_handle_ch(int ch) 1659static int omap2_dma_handle_ch(int ch)
925{ 1660{
@@ -953,8 +1688,33 @@ static int omap2_dma_handle_ch(int ch)
953 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK; 1688 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
954 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); 1689 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
955 1690
956 if (likely(dma_chan[ch].callback != NULL)) 1691 /* If the ch is not chained then chain_id will be -1 */
957 dma_chan[ch].callback(ch, status, dma_chan[ch].data); 1692 if (dma_chan[ch].chain_id != -1) {
1693 int chain_id = dma_chan[ch].chain_id;
1694 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1695 if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15))
1696 dma_chan[dma_chan[ch].next_linked_ch].state =
1697 DMA_CH_STARTED;
1698 if (dma_linked_lch[chain_id].chain_mode ==
1699 OMAP_DMA_DYNAMIC_CHAIN)
1700 disable_lnk(ch);
1701
1702 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1703 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1704
1705 status = OMAP_DMA_CSR_REG(ch);
1706 }
1707
1708 if (likely(dma_chan[ch].callback != NULL)) {
1709 if (dma_chan[ch].chain_id != -1)
1710 dma_chan[ch].callback(dma_chan[ch].chain_id, status,
1711 dma_chan[ch].data);
1712 else
1713 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1714
1715 }
1716
1717 OMAP_DMA_CSR_REG(ch) = status;
958 1718
959 return 0; 1719 return 0;
960} 1720}
@@ -1385,7 +2145,7 @@ static int __init omap_init_dma(void)
1385 w &= ~(1 << 8); 2145 w &= ~(1 << 8);
1386 omap_writew(w, OMAP1610_DMA_LCD_CTRL); 2146 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1387 } 2147 }
1388 } else if (cpu_is_omap24xx()) { 2148 } else if (cpu_class_is_omap2()) {
1389 u8 revision = omap_readb(OMAP_DMA4_REVISION); 2149 u8 revision = omap_readb(OMAP_DMA4_REVISION);
1390 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 2150 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
1391 revision >> 4, revision & 0xf); 2151 revision >> 4, revision & 0xf);
@@ -1428,7 +2188,11 @@ static int __init omap_init_dma(void)
1428 } 2188 }
1429 } 2189 }
1430 2190
1431 if (cpu_is_omap24xx()) 2191 if (cpu_is_omap2430() || cpu_is_omap34xx())
2192 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2193 DMA_DEFAULT_FIFO_DEPTH, 0);
2194
2195 if (cpu_class_is_omap2())
1432 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq); 2196 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
1433 2197
1434 /* FIXME: Update LCD DMA to work on 24xx */ 2198 /* FIXME: Update LCD DMA to work on 24xx */
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 3856f5aedfc1..e719d0eeb5c8 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -48,7 +48,7 @@
48#define OMAP_TIMER_COUNTER_REG 0x28 48#define OMAP_TIMER_COUNTER_REG 0x28
49#define OMAP_TIMER_LOAD_REG 0x2c 49#define OMAP_TIMER_LOAD_REG 0x2c
50#define OMAP_TIMER_TRIGGER_REG 0x30 50#define OMAP_TIMER_TRIGGER_REG 0x30
51#define OMAP_TIMER_WRITE_PEND_REG 0x34 51#define OMAP_TIMER_WRITE_PEND_REG 0x34
52#define OMAP_TIMER_MATCH_REG 0x38 52#define OMAP_TIMER_MATCH_REG 0x38
53#define OMAP_TIMER_CAPTURE_REG 0x3c 53#define OMAP_TIMER_CAPTURE_REG 0x3c
54#define OMAP_TIMER_IF_CTRL_REG 0x40 54#define OMAP_TIMER_IF_CTRL_REG 0x40
@@ -70,7 +70,7 @@
70struct omap_dm_timer { 70struct omap_dm_timer {
71 unsigned long phys_base; 71 unsigned long phys_base;
72 int irq; 72 int irq;
73#ifdef CONFIG_ARCH_OMAP2 73#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
74 struct clk *iclk, *fclk; 74 struct clk *iclk, *fclk;
75#endif 75#endif
76 void __iomem *io_base; 76 void __iomem *io_base;
@@ -82,8 +82,14 @@ struct omap_dm_timer {
82 82
83#define omap_dm_clk_enable(x) 83#define omap_dm_clk_enable(x)
84#define omap_dm_clk_disable(x) 84#define omap_dm_clk_disable(x)
85 85#define omap2_dm_timers NULL
86static struct omap_dm_timer dm_timers[] = { 86#define omap2_dm_source_names NULL
87#define omap2_dm_source_clocks NULL
88#define omap3_dm_timers NULL
89#define omap3_dm_source_names NULL
90#define omap3_dm_source_clocks NULL
91
92static struct omap_dm_timer omap1_dm_timers[] = {
87 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, 93 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
88 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, 94 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
89 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 }, 95 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
@@ -94,12 +100,18 @@ static struct omap_dm_timer dm_timers[] = {
94 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, 100 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
95}; 101};
96 102
103static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
104
97#elif defined(CONFIG_ARCH_OMAP2) 105#elif defined(CONFIG_ARCH_OMAP2)
98 106
99#define omap_dm_clk_enable(x) clk_enable(x) 107#define omap_dm_clk_enable(x) clk_enable(x)
100#define omap_dm_clk_disable(x) clk_disable(x) 108#define omap_dm_clk_disable(x) clk_disable(x)
109#define omap1_dm_timers NULL
110#define omap3_dm_timers NULL
111#define omap3_dm_source_names NULL
112#define omap3_dm_source_clocks NULL
101 113
102static struct omap_dm_timer dm_timers[] = { 114static struct omap_dm_timer omap2_dm_timers[] = {
103 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, 115 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
104 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, 116 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
105 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 }, 117 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
@@ -114,13 +126,48 @@ static struct omap_dm_timer dm_timers[] = {
114 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 }, 126 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
115}; 127};
116 128
117static const char *dm_source_names[] = { 129static const char *omap2_dm_source_names[] __initdata = {
118 "sys_ck", 130 "sys_ck",
119 "func_32k_ck", 131 "func_32k_ck",
120 "alt_ck" 132 "alt_ck",
133 NULL
134};
135
136static struct clk **omap2_dm_source_clocks[3];
137static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
138
139#elif defined(CONFIG_ARCH_OMAP3)
140
141#define omap_dm_clk_enable(x) clk_enable(x)
142#define omap_dm_clk_disable(x) clk_disable(x)
143#define omap1_dm_timers NULL
144#define omap2_dm_timers NULL
145#define omap2_dm_source_names NULL
146#define omap2_dm_source_clocks NULL
147
148static struct omap_dm_timer omap3_dm_timers[] = {
149 { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
150 { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
151 { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
152 { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
153 { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
154 { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
155 { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
156 { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
157 { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
158 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
159 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
160 { .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 },
161};
162
163static const char *omap3_dm_source_names[] __initdata = {
164 "sys_ck",
165 "omap_32k_fck",
166 NULL
121}; 167};
122 168
123static struct clk *dm_source_clocks[3]; 169static struct clk **omap3_dm_source_clocks[2];
170static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
124 171
125#else 172#else
126 173
@@ -128,7 +175,10 @@ static struct clk *dm_source_clocks[3];
128 175
129#endif 176#endif
130 177
131static const int dm_timer_count = ARRAY_SIZE(dm_timers); 178static struct omap_dm_timer *dm_timers;
179static char **dm_source_names;
180static struct clk **dm_source_clocks;
181
132static spinlock_t dm_timer_lock; 182static spinlock_t dm_timer_lock;
133 183
134static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg) 184static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
@@ -299,7 +349,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
299 return inputmask; 349 return inputmask;
300} 350}
301 351
302#elif defined(CONFIG_ARCH_OMAP2) 352#elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3)
303 353
304struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 354struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
305{ 355{
@@ -486,36 +536,46 @@ int omap_dm_timers_active(void)
486 return 0; 536 return 0;
487} 537}
488 538
489int omap_dm_timer_init(void) 539int __init omap_dm_timer_init(void)
490{ 540{
491 struct omap_dm_timer *timer; 541 struct omap_dm_timer *timer;
492 int i; 542 int i;
493 543
494 if (!(cpu_is_omap16xx() || cpu_is_omap24xx())) 544 if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
495 return -ENODEV; 545 return -ENODEV;
496 546
497 spin_lock_init(&dm_timer_lock); 547 spin_lock_init(&dm_timer_lock);
498#ifdef CONFIG_ARCH_OMAP2 548
499 for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) { 549 if (cpu_class_is_omap1())
500 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); 550 dm_timers = omap1_dm_timers;
501 BUG_ON(dm_source_clocks[i] == NULL); 551 else if (cpu_is_omap24xx()) {
552 dm_timers = omap2_dm_timers;
553 dm_source_names = (char **)omap2_dm_source_names;
554 dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
555 } else if (cpu_is_omap34xx()) {
556 dm_timers = omap3_dm_timers;
557 dm_source_names = (char **)omap3_dm_source_names;
558 dm_source_clocks = (struct clk **)omap3_dm_source_clocks;
502 } 559 }
503#endif 560
561 if (cpu_class_is_omap2())
562 for (i = 0; dm_source_names[i] != NULL; i++)
563 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
564
504 if (cpu_is_omap243x()) 565 if (cpu_is_omap243x())
505 dm_timers[0].phys_base = 0x49018000; 566 dm_timers[0].phys_base = 0x49018000;
506 567
507 for (i = 0; i < dm_timer_count; i++) { 568 for (i = 0; i < dm_timer_count; i++) {
508#ifdef CONFIG_ARCH_OMAP2
509 char clk_name[16];
510#endif
511
512 timer = &dm_timers[i]; 569 timer = &dm_timers[i];
513 timer->io_base = (void __iomem *) io_p2v(timer->phys_base); 570 timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
514#ifdef CONFIG_ARCH_OMAP2 571#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
515 sprintf(clk_name, "gpt%d_ick", i + 1); 572 if (cpu_class_is_omap2()) {
516 timer->iclk = clk_get(NULL, clk_name); 573 char clk_name[16];
517 sprintf(clk_name, "gpt%d_fck", i + 1); 574 sprintf(clk_name, "gpt%d_ick", i + 1);
518 timer->fclk = clk_get(NULL, clk_name); 575 timer->iclk = clk_get(NULL, clk_name);
576 sprintf(clk_name, "gpt%d_fck", i + 1);
577 timer->fclk = clk_get(NULL, clk_name);
578 }
519#endif 579#endif
520 } 580 }
521 581
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index b2a87b8ef673..56f4d1394d56 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -110,6 +110,8 @@
110#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 110#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111#define OMAP24XX_GPIO_RISINGDETECT 0x0048 111#define OMAP24XX_GPIO_RISINGDETECT 0x0048
112#define OMAP24XX_GPIO_FALLINGDETECT 0x004c 112#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
113#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 115#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
114#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 116#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
115#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 117#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
@@ -117,17 +119,29 @@
117#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 119#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
118#define OMAP24XX_GPIO_SETDATAOUT 0x0094 120#define OMAP24XX_GPIO_SETDATAOUT 0x0094
119 121
122/*
123 * omap34xx specific GPIO registers
124 */
125
126#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
132
133
120struct gpio_bank { 134struct gpio_bank {
121 void __iomem *base; 135 void __iomem *base;
122 u16 irq; 136 u16 irq;
123 u16 virtual_irq_start; 137 u16 virtual_irq_start;
124 int method; 138 int method;
125 u32 reserved_map; 139 u32 reserved_map;
126#if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX) 140#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
127 u32 suspend_wakeup; 141 u32 suspend_wakeup;
128 u32 saved_wakeup; 142 u32 saved_wakeup;
129#endif 143#endif
130#ifdef CONFIG_ARCH_OMAP24XX 144#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
131 u32 non_wakeup_gpios; 145 u32 non_wakeup_gpios;
132 u32 enabled_non_wakeup_gpios; 146 u32 enabled_non_wakeup_gpios;
133 147
@@ -192,48 +206,52 @@ static struct gpio_bank gpio_bank_243x[5] = {
192 206
193#endif 207#endif
194 208
209#ifdef CONFIG_ARCH_OMAP34XX
210static struct gpio_bank gpio_bank_34xx[6] = {
211 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
217};
218
219#endif
220
195static struct gpio_bank *gpio_bank; 221static struct gpio_bank *gpio_bank;
196static int gpio_bank_count; 222static int gpio_bank_count;
197 223
198static inline struct gpio_bank *get_gpio_bank(int gpio) 224static inline struct gpio_bank *get_gpio_bank(int gpio)
199{ 225{
200#ifdef CONFIG_ARCH_OMAP15XX
201 if (cpu_is_omap15xx()) { 226 if (cpu_is_omap15xx()) {
202 if (OMAP_GPIO_IS_MPUIO(gpio)) 227 if (OMAP_GPIO_IS_MPUIO(gpio))
203 return &gpio_bank[0]; 228 return &gpio_bank[0];
204 return &gpio_bank[1]; 229 return &gpio_bank[1];
205 } 230 }
206#endif
207#if defined(CONFIG_ARCH_OMAP16XX)
208 if (cpu_is_omap16xx()) { 231 if (cpu_is_omap16xx()) {
209 if (OMAP_GPIO_IS_MPUIO(gpio)) 232 if (OMAP_GPIO_IS_MPUIO(gpio))
210 return &gpio_bank[0]; 233 return &gpio_bank[0];
211 return &gpio_bank[1 + (gpio >> 4)]; 234 return &gpio_bank[1 + (gpio >> 4)];
212 } 235 }
213#endif
214#ifdef CONFIG_ARCH_OMAP730
215 if (cpu_is_omap730()) { 236 if (cpu_is_omap730()) {
216 if (OMAP_GPIO_IS_MPUIO(gpio)) 237 if (OMAP_GPIO_IS_MPUIO(gpio))
217 return &gpio_bank[0]; 238 return &gpio_bank[0];
218 return &gpio_bank[1 + (gpio >> 5)]; 239 return &gpio_bank[1 + (gpio >> 5)];
219 } 240 }
220#endif
221#ifdef CONFIG_ARCH_OMAP24XX
222 if (cpu_is_omap24xx()) 241 if (cpu_is_omap24xx())
223 return &gpio_bank[gpio >> 5]; 242 return &gpio_bank[gpio >> 5];
224#endif 243 if (cpu_is_omap34xx())
244 return &gpio_bank[gpio >> 5];
225} 245}
226 246
227static inline int get_gpio_index(int gpio) 247static inline int get_gpio_index(int gpio)
228{ 248{
229#ifdef CONFIG_ARCH_OMAP730
230 if (cpu_is_omap730()) 249 if (cpu_is_omap730())
231 return gpio & 0x1f; 250 return gpio & 0x1f;
232#endif
233#ifdef CONFIG_ARCH_OMAP24XX
234 if (cpu_is_omap24xx()) 251 if (cpu_is_omap24xx())
235 return gpio & 0x1f; 252 return gpio & 0x1f;
236#endif 253 if (cpu_is_omap34xx())
254 return gpio & 0x1f;
237 return gpio & 0x0f; 255 return gpio & 0x0f;
238} 256}
239 257
@@ -241,29 +259,21 @@ static inline int gpio_valid(int gpio)
241{ 259{
242 if (gpio < 0) 260 if (gpio < 0)
243 return -1; 261 return -1;
244#ifndef CONFIG_ARCH_OMAP24XX 262 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
245 if (OMAP_GPIO_IS_MPUIO(gpio)) {
246 if (gpio >= OMAP_MAX_GPIO_LINES + 16) 263 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
247 return -1; 264 return -1;
248 return 0; 265 return 0;
249 } 266 }
250#endif
251#ifdef CONFIG_ARCH_OMAP15XX
252 if (cpu_is_omap15xx() && gpio < 16) 267 if (cpu_is_omap15xx() && gpio < 16)
253 return 0; 268 return 0;
254#endif
255#if defined(CONFIG_ARCH_OMAP16XX)
256 if ((cpu_is_omap16xx()) && gpio < 64) 269 if ((cpu_is_omap16xx()) && gpio < 64)
257 return 0; 270 return 0;
258#endif
259#ifdef CONFIG_ARCH_OMAP730
260 if (cpu_is_omap730() && gpio < 192) 271 if (cpu_is_omap730() && gpio < 192)
261 return 0; 272 return 0;
262#endif
263#ifdef CONFIG_ARCH_OMAP24XX
264 if (cpu_is_omap24xx() && gpio < 128) 273 if (cpu_is_omap24xx() && gpio < 128)
265 return 0; 274 return 0;
266#endif 275 if (cpu_is_omap34xx() && gpio < 160)
276 return 0;
267 return -1; 277 return -1;
268} 278}
269 279
@@ -303,7 +313,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
303 reg += OMAP730_GPIO_DIR_CONTROL; 313 reg += OMAP730_GPIO_DIR_CONTROL;
304 break; 314 break;
305#endif 315#endif
306#ifdef CONFIG_ARCH_OMAP24XX 316#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
307 case METHOD_GPIO_24XX: 317 case METHOD_GPIO_24XX:
308 reg += OMAP24XX_GPIO_OE; 318 reg += OMAP24XX_GPIO_OE;
309 break; 319 break;
@@ -377,7 +387,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
377 l &= ~(1 << gpio); 387 l &= ~(1 << gpio);
378 break; 388 break;
379#endif 389#endif
380#ifdef CONFIG_ARCH_OMAP24XX 390#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
381 case METHOD_GPIO_24XX: 391 case METHOD_GPIO_24XX:
382 if (enable) 392 if (enable)
383 reg += OMAP24XX_GPIO_SETDATAOUT; 393 reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -435,7 +445,7 @@ int omap_get_gpio_datain(int gpio)
435 reg += OMAP730_GPIO_DATA_INPUT; 445 reg += OMAP730_GPIO_DATA_INPUT;
436 break; 446 break;
437#endif 447#endif
438#ifdef CONFIG_ARCH_OMAP24XX 448#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
439 case METHOD_GPIO_24XX: 449 case METHOD_GPIO_24XX:
440 reg += OMAP24XX_GPIO_DATAIN; 450 reg += OMAP24XX_GPIO_DATAIN;
441 break; 451 break;
@@ -455,8 +465,50 @@ do { \
455 __raw_writel(l, base + reg); \ 465 __raw_writel(l, base + reg); \
456} while(0) 466} while(0)
457 467
458#ifdef CONFIG_ARCH_OMAP24XX 468void omap_set_gpio_debounce(int gpio, int enable)
459static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 469{
470 struct gpio_bank *bank;
471 void __iomem *reg;
472 u32 val, l = 1 << get_gpio_index(gpio);
473
474 if (cpu_class_is_omap1())
475 return;
476
477 bank = get_gpio_bank(gpio);
478 reg = bank->base;
479
480 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
481 val = __raw_readl(reg);
482
483 if (enable)
484 val |= l;
485 else
486 val &= ~l;
487
488 __raw_writel(val, reg);
489}
490EXPORT_SYMBOL(omap_set_gpio_debounce);
491
492void omap_set_gpio_debounce_time(int gpio, int enc_time)
493{
494 struct gpio_bank *bank;
495 void __iomem *reg;
496
497 if (cpu_class_is_omap1())
498 return;
499
500 bank = get_gpio_bank(gpio);
501 reg = bank->base;
502
503 enc_time &= 0xff;
504 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
505 __raw_writel(enc_time, reg);
506}
507EXPORT_SYMBOL(omap_set_gpio_debounce_time);
508
509#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
510static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
511 int trigger)
460{ 512{
461 void __iomem *base = bank->base; 513 void __iomem *base = bank->base;
462 u32 gpio_bit = 1 << gpio; 514 u32 gpio_bit = 1 << gpio;
@@ -469,19 +521,25 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, in
469 trigger & __IRQT_RISEDGE); 521 trigger & __IRQT_RISEDGE);
470 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 522 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
471 trigger & __IRQT_FALEDGE); 523 trigger & __IRQT_FALEDGE);
524
472 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 525 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
473 if (trigger != 0) 526 if (trigger != 0)
474 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA); 527 __raw_writel(1 << gpio, bank->base
528 + OMAP24XX_GPIO_SETWKUENA);
475 else 529 else
476 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA); 530 __raw_writel(1 << gpio, bank->base
531 + OMAP24XX_GPIO_CLEARWKUENA);
477 } else { 532 } else {
478 if (trigger != 0) 533 if (trigger != 0)
479 bank->enabled_non_wakeup_gpios |= gpio_bit; 534 bank->enabled_non_wakeup_gpios |= gpio_bit;
480 else 535 else
481 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 536 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
482 } 537 }
483 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level 538
484 * triggering requested. */ 539 /*
540 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
541 * level triggering requested.
542 */
485} 543}
486#endif 544#endif
487 545
@@ -547,7 +605,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
547 goto bad; 605 goto bad;
548 break; 606 break;
549#endif 607#endif
550#ifdef CONFIG_ARCH_OMAP24XX 608#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
551 case METHOD_GPIO_24XX: 609 case METHOD_GPIO_24XX:
552 set_24xx_gpio_triggering(bank, gpio, trigger); 610 set_24xx_gpio_triggering(bank, gpio, trigger);
553 break; 611 break;
@@ -567,7 +625,7 @@ static int gpio_irq_type(unsigned irq, unsigned type)
567 unsigned gpio; 625 unsigned gpio;
568 int retval; 626 int retval;
569 627
570 if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE) 628 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
571 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 629 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
572 else 630 else
573 gpio = irq - IH_GPIO_BASE; 631 gpio = irq - IH_GPIO_BASE;
@@ -579,7 +637,7 @@ static int gpio_irq_type(unsigned irq, unsigned type)
579 return -EINVAL; 637 return -EINVAL;
580 638
581 /* OMAP1 allows only only edge triggering */ 639 /* OMAP1 allows only only edge triggering */
582 if (!cpu_is_omap24xx() 640 if (!cpu_class_is_omap2()
583 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 641 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
584 return -EINVAL; 642 return -EINVAL;
585 643
@@ -620,7 +678,7 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
620 reg += OMAP730_GPIO_INT_STATUS; 678 reg += OMAP730_GPIO_INT_STATUS;
621 break; 679 break;
622#endif 680#endif
623#ifdef CONFIG_ARCH_OMAP24XX 681#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
624 case METHOD_GPIO_24XX: 682 case METHOD_GPIO_24XX:
625 reg += OMAP24XX_GPIO_IRQSTATUS1; 683 reg += OMAP24XX_GPIO_IRQSTATUS1;
626 break; 684 break;
@@ -632,8 +690,10 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
632 __raw_writel(gpio_mask, reg); 690 __raw_writel(gpio_mask, reg);
633 691
634 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 692 /* Workaround for clearing DSP GPIO interrupts to allow retention */
635 if (cpu_is_omap2420()) 693#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
694 if (cpu_is_omap24xx() || cpu_is_omap34xx())
636 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); 695 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
696#endif
637} 697}
638 698
639static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 699static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@ -676,7 +736,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
676 inv = 1; 736 inv = 1;
677 break; 737 break;
678#endif 738#endif
679#ifdef CONFIG_ARCH_OMAP24XX 739#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
680 case METHOD_GPIO_24XX: 740 case METHOD_GPIO_24XX:
681 reg += OMAP24XX_GPIO_IRQENABLE1; 741 reg += OMAP24XX_GPIO_IRQENABLE1;
682 mask = 0xffffffff; 742 mask = 0xffffffff;
@@ -739,7 +799,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
739 l |= gpio_mask; 799 l |= gpio_mask;
740 break; 800 break;
741#endif 801#endif
742#ifdef CONFIG_ARCH_OMAP24XX 802#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
743 case METHOD_GPIO_24XX: 803 case METHOD_GPIO_24XX:
744 if (enable) 804 if (enable)
745 reg += OMAP24XX_GPIO_SETIRQENABLE1; 805 reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -785,7 +845,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
785 spin_unlock(&bank->lock); 845 spin_unlock(&bank->lock);
786 return 0; 846 return 0;
787#endif 847#endif
788#ifdef CONFIG_ARCH_OMAP24XX 848#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
789 case METHOD_GPIO_24XX: 849 case METHOD_GPIO_24XX:
790 if (bank->non_wakeup_gpios & (1 << gpio)) { 850 if (bank->non_wakeup_gpios & (1 << gpio)) {
791 printk(KERN_ERR "Unable to modify wakeup on " 851 printk(KERN_ERR "Unable to modify wakeup on "
@@ -891,7 +951,7 @@ void omap_free_gpio(int gpio)
891 __raw_writel(1 << get_gpio_index(gpio), reg); 951 __raw_writel(1 << get_gpio_index(gpio), reg);
892 } 952 }
893#endif 953#endif
894#ifdef CONFIG_ARCH_OMAP24XX 954#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
895 if (bank->method == METHOD_GPIO_24XX) { 955 if (bank->method == METHOD_GPIO_24XX) {
896 /* Disable wake-up during idle for dynamic tick */ 956 /* Disable wake-up during idle for dynamic tick */
897 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 957 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
@@ -940,7 +1000,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
940 if (bank->method == METHOD_GPIO_730) 1000 if (bank->method == METHOD_GPIO_730)
941 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; 1001 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
942#endif 1002#endif
943#ifdef CONFIG_ARCH_OMAP24XX 1003#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
944 if (bank->method == METHOD_GPIO_24XX) 1004 if (bank->method == METHOD_GPIO_24XX)
945 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; 1005 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
946#endif 1006#endif
@@ -954,7 +1014,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
954 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) 1014 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
955 isr &= 0x0000ffff; 1015 isr &= 0x0000ffff;
956 1016
957 if (cpu_is_omap24xx()) { 1017 if (cpu_class_is_omap2()) {
958 level_mask = 1018 level_mask =
959 __raw_readl(bank->base + 1019 __raw_readl(bank->base +
960 OMAP24XX_GPIO_LEVELDETECT0) | 1020 OMAP24XX_GPIO_LEVELDETECT0) |
@@ -1023,7 +1083,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1023 } 1083 }
1024 } 1084 }
1025 1085
1026 if (cpu_is_omap24xx()) { 1086 if (cpu_class_is_omap2()) {
1027 /* clear level sensitive interrupts after handler(s) */ 1087 /* clear level sensitive interrupts after handler(s) */
1028 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0); 1088 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1029 _clear_gpio_irqbank(bank, isr_saved & level_mask); 1089 _clear_gpio_irqbank(bank, isr_saved & level_mask);
@@ -1199,21 +1259,35 @@ static inline void mpuio_init(void) {}
1199/*---------------------------------------------------------------------*/ 1259/*---------------------------------------------------------------------*/
1200 1260
1201static int initialized; 1261static int initialized;
1262#if !defined(CONFIG_ARCH_OMAP3)
1202static struct clk * gpio_ick; 1263static struct clk * gpio_ick;
1264#endif
1265
1266#if defined(CONFIG_ARCH_OMAP2)
1203static struct clk * gpio_fck; 1267static struct clk * gpio_fck;
1268#endif
1204 1269
1205#ifdef CONFIG_ARCH_OMAP2430 1270#if defined(CONFIG_ARCH_OMAP2430)
1206static struct clk * gpio5_ick; 1271static struct clk * gpio5_ick;
1207static struct clk * gpio5_fck; 1272static struct clk * gpio5_fck;
1208#endif 1273#endif
1209 1274
1275#if defined(CONFIG_ARCH_OMAP3)
1276static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1277static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1278#endif
1279
1210static int __init _omap_gpio_init(void) 1280static int __init _omap_gpio_init(void)
1211{ 1281{
1212 int i; 1282 int i;
1213 struct gpio_bank *bank; 1283 struct gpio_bank *bank;
1284#if defined(CONFIG_ARCH_OMAP3)
1285 char clk_name[11];
1286#endif
1214 1287
1215 initialized = 1; 1288 initialized = 1;
1216 1289
1290#if defined(CONFIG_ARCH_OMAP1)
1217 if (cpu_is_omap15xx()) { 1291 if (cpu_is_omap15xx()) {
1218 gpio_ick = clk_get(NULL, "arm_gpio_ck"); 1292 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1219 if (IS_ERR(gpio_ick)) 1293 if (IS_ERR(gpio_ick))
@@ -1221,7 +1295,9 @@ static int __init _omap_gpio_init(void)
1221 else 1295 else
1222 clk_enable(gpio_ick); 1296 clk_enable(gpio_ick);
1223 } 1297 }
1224 if (cpu_is_omap24xx()) { 1298#endif
1299#if defined(CONFIG_ARCH_OMAP2)
1300 if (cpu_class_is_omap2()) {
1225 gpio_ick = clk_get(NULL, "gpios_ick"); 1301 gpio_ick = clk_get(NULL, "gpios_ick");
1226 if (IS_ERR(gpio_ick)) 1302 if (IS_ERR(gpio_ick))
1227 printk("Could not get gpios_ick\n"); 1303 printk("Could not get gpios_ick\n");
@@ -1234,9 +1310,9 @@ static int __init _omap_gpio_init(void)
1234 clk_enable(gpio_fck); 1310 clk_enable(gpio_fck);
1235 1311
1236 /* 1312 /*
1237 * On 2430 GPIO 5 uses CORE L4 ICLK 1313 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1238 */ 1314 */
1239#ifdef CONFIG_ARCH_OMAP2430 1315#if defined(CONFIG_ARCH_OMAP2430)
1240 if (cpu_is_omap2430()) { 1316 if (cpu_is_omap2430()) {
1241 gpio5_ick = clk_get(NULL, "gpio5_ick"); 1317 gpio5_ick = clk_get(NULL, "gpio5_ick");
1242 if (IS_ERR(gpio5_ick)) 1318 if (IS_ERR(gpio5_ick))
@@ -1250,7 +1326,28 @@ static int __init _omap_gpio_init(void)
1250 clk_enable(gpio5_fck); 1326 clk_enable(gpio5_fck);
1251 } 1327 }
1252#endif 1328#endif
1253} 1329 }
1330#endif
1331
1332#if defined(CONFIG_ARCH_OMAP3)
1333 if (cpu_is_omap34xx()) {
1334 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1335 sprintf(clk_name, "gpio%d_ick", i + 1);
1336 gpio_iclks[i] = clk_get(NULL, clk_name);
1337 if (IS_ERR(gpio_iclks[i]))
1338 printk(KERN_ERR "Could not get %s\n", clk_name);
1339 else
1340 clk_enable(gpio_iclks[i]);
1341 sprintf(clk_name, "gpio%d_fck", i + 1);
1342 gpio_fclks[i] = clk_get(NULL, clk_name);
1343 if (IS_ERR(gpio_fclks[i]))
1344 printk(KERN_ERR "Could not get %s\n", clk_name);
1345 else
1346 clk_enable(gpio_fclks[i]);
1347 }
1348 }
1349#endif
1350
1254 1351
1255#ifdef CONFIG_ARCH_OMAP15XX 1352#ifdef CONFIG_ARCH_OMAP15XX
1256 if (cpu_is_omap15xx()) { 1353 if (cpu_is_omap15xx()) {
@@ -1298,6 +1395,17 @@ static int __init _omap_gpio_init(void)
1298 (rev >> 4) & 0x0f, rev & 0x0f); 1395 (rev >> 4) & 0x0f, rev & 0x0f);
1299 } 1396 }
1300#endif 1397#endif
1398#ifdef CONFIG_ARCH_OMAP34XX
1399 if (cpu_is_omap34xx()) {
1400 int rev;
1401
1402 gpio_bank_count = OMAP34XX_NR_GPIOS;
1403 gpio_bank = gpio_bank_34xx;
1404 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1405 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1406 (rev >> 4) & 0x0f, rev & 0x0f);
1407 }
1408#endif
1301 for (i = 0; i < gpio_bank_count; i++) { 1409 for (i = 0; i < gpio_bank_count; i++) {
1302 int j, gpio_count = 16; 1410 int j, gpio_count = 16;
1303 1411
@@ -1307,28 +1415,23 @@ static int __init _omap_gpio_init(void)
1307 spin_lock_init(&bank->lock); 1415 spin_lock_init(&bank->lock);
1308 if (bank_is_mpuio(bank)) 1416 if (bank_is_mpuio(bank))
1309 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); 1417 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1310#ifdef CONFIG_ARCH_OMAP15XX 1418 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1311 if (bank->method == METHOD_GPIO_1510) {
1312 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); 1419 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1313 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); 1420 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1314 } 1421 }
1315#endif 1422 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1316#if defined(CONFIG_ARCH_OMAP16XX)
1317 if (bank->method == METHOD_GPIO_1610) {
1318 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); 1423 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1319 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); 1424 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1320 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); 1425 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1321 } 1426 }
1322#endif 1427 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1323#ifdef CONFIG_ARCH_OMAP730
1324 if (bank->method == METHOD_GPIO_730) {
1325 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); 1428 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1326 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); 1429 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1327 1430
1328 gpio_count = 32; /* 730 has 32-bit GPIOs */ 1431 gpio_count = 32; /* 730 has 32-bit GPIOs */
1329 } 1432 }
1330#endif 1433
1331#ifdef CONFIG_ARCH_OMAP24XX 1434#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1332 if (bank->method == METHOD_GPIO_24XX) { 1435 if (bank->method == METHOD_GPIO_24XX) {
1333 static const u32 non_wakeup_gpios[] = { 1436 static const u32 non_wakeup_gpios[] = {
1334 0xe203ffc0, 0x08700040 1437 0xe203ffc0, 0x08700040
@@ -1364,21 +1467,21 @@ static int __init _omap_gpio_init(void)
1364 if (cpu_is_omap16xx()) 1467 if (cpu_is_omap16xx())
1365 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); 1468 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1366 1469
1367#ifdef CONFIG_ARCH_OMAP24XX
1368 /* Enable autoidle for the OCP interface */ 1470 /* Enable autoidle for the OCP interface */
1369 if (cpu_is_omap24xx()) 1471 if (cpu_is_omap24xx())
1370 omap_writel(1 << 0, 0x48019010); 1472 omap_writel(1 << 0, 0x48019010);
1371#endif 1473 if (cpu_is_omap34xx())
1474 omap_writel(1 << 0, 0x48306814);
1372 1475
1373 return 0; 1476 return 0;
1374} 1477}
1375 1478
1376#if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX) 1479#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1377static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) 1480static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1378{ 1481{
1379 int i; 1482 int i;
1380 1483
1381 if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) 1484 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1382 return 0; 1485 return 0;
1383 1486
1384 for (i = 0; i < gpio_bank_count; i++) { 1487 for (i = 0; i < gpio_bank_count; i++) {
@@ -1395,7 +1498,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1395 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1498 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1396 break; 1499 break;
1397#endif 1500#endif
1398#ifdef CONFIG_ARCH_OMAP24XX 1501#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1399 case METHOD_GPIO_24XX: 1502 case METHOD_GPIO_24XX:
1400 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA; 1503 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1401 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1504 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
@@ -1435,7 +1538,7 @@ static int omap_gpio_resume(struct sys_device *dev)
1435 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1538 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1436 break; 1539 break;
1437#endif 1540#endif
1438#ifdef CONFIG_ARCH_OMAP24XX 1541#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1439 case METHOD_GPIO_24XX: 1542 case METHOD_GPIO_24XX:
1440 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1543 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1441 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1544 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
@@ -1467,7 +1570,7 @@ static struct sys_device omap_gpio_device = {
1467 1570
1468#endif 1571#endif
1469 1572
1470#ifdef CONFIG_ARCH_OMAP24XX 1573#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1471 1574
1472static int workaround_enabled; 1575static int workaround_enabled;
1473 1576
@@ -1483,15 +1586,19 @@ void omap2_gpio_prepare_for_retention(void)
1483 1586
1484 if (!(bank->enabled_non_wakeup_gpios)) 1587 if (!(bank->enabled_non_wakeup_gpios))
1485 continue; 1588 continue;
1589#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1486 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1590 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1487 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1591 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1488 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); 1592 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1593#endif
1489 bank->saved_fallingdetect = l1; 1594 bank->saved_fallingdetect = l1;
1490 bank->saved_risingdetect = l2; 1595 bank->saved_risingdetect = l2;
1491 l1 &= ~bank->enabled_non_wakeup_gpios; 1596 l1 &= ~bank->enabled_non_wakeup_gpios;
1492 l2 &= ~bank->enabled_non_wakeup_gpios; 1597 l2 &= ~bank->enabled_non_wakeup_gpios;
1598#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1493 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1599 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1494 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); 1600 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1601#endif
1495 c++; 1602 c++;
1496 } 1603 }
1497 if (!c) { 1604 if (!c) {
@@ -1513,26 +1620,31 @@ void omap2_gpio_resume_after_retention(void)
1513 1620
1514 if (!(bank->enabled_non_wakeup_gpios)) 1621 if (!(bank->enabled_non_wakeup_gpios))
1515 continue; 1622 continue;
1623#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1516 __raw_writel(bank->saved_fallingdetect, 1624 __raw_writel(bank->saved_fallingdetect,
1517 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1625 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1518 __raw_writel(bank->saved_risingdetect, 1626 __raw_writel(bank->saved_risingdetect,
1519 bank->base + OMAP24XX_GPIO_RISINGDETECT); 1627 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1628#endif
1520 /* Check if any of the non-wakeup interrupt GPIOs have changed 1629 /* Check if any of the non-wakeup interrupt GPIOs have changed
1521 * state. If so, generate an IRQ by software. This is 1630 * state. If so, generate an IRQ by software. This is
1522 * horribly racy, but it's the best we can do to work around 1631 * horribly racy, but it's the best we can do to work around
1523 * this silicon bug. */ 1632 * this silicon bug. */
1633#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1524 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1634 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1635#endif
1525 l ^= bank->saved_datain; 1636 l ^= bank->saved_datain;
1526 l &= bank->non_wakeup_gpios; 1637 l &= bank->non_wakeup_gpios;
1527 if (l) { 1638 if (l) {
1528 u32 old0, old1; 1639 u32 old0, old1;
1529 1640#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1530 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1641 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1531 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1642 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1532 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1643 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1533 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1644 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1534 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1645 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1535 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1646 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1647#endif
1536 } 1648 }
1537 } 1649 }
1538 1650
@@ -1561,8 +1673,8 @@ static int __init omap_gpio_sysinit(void)
1561 1673
1562 mpuio_init(); 1674 mpuio_init();
1563 1675
1564#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) 1676#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1565 if (cpu_is_omap16xx() || cpu_is_omap24xx()) { 1677 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1566 if (ret == 0) { 1678 if (ret == 0) {
1567 ret = sysdev_class_register(&omap_gpio_sysclass); 1679 ret = sysdev_class_register(&omap_gpio_sysclass);
1568 if (ret == 0) 1680 if (ret == 0)
@@ -1624,7 +1736,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
1624 1736
1625 if (bank_is_mpuio(bank)) 1737 if (bank_is_mpuio(bank))
1626 gpio = OMAP_MPUIO(0); 1738 gpio = OMAP_MPUIO(0);
1627 else if (cpu_is_omap24xx() || cpu_is_omap730()) 1739 else if (cpu_class_is_omap2() || cpu_is_omap730())
1628 bankwidth = 32; 1740 bankwidth = 32;
1629 1741
1630 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { 1742 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
new file mode 100644
index 000000000000..7990ab185bb1
--- /dev/null
+++ b/arch/arm/plat-omap/i2c.c
@@ -0,0 +1,148 @@
1/*
2 * linux/arch/arm/plat-omap/i2c.c
3 *
4 * Helper module for board specific I2C bus registration
5 *
6 * Copyright (C) 2007 Nokia Corporation.
7 *
8 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * 02110-1301 USA
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/platform_device.h>
28#include <linux/i2c.h>
29#include <asm/mach-types.h>
30#include <asm/arch/mux.h>
31
32#define OMAP_I2C_SIZE 0x3f
33#define OMAP1_I2C_BASE 0xfffb3800
34#define OMAP2_I2C_BASE1 0x48070000
35#define OMAP2_I2C_BASE2 0x48072000
36#define OMAP2_I2C_BASE3 0x48060000
37
38static const char name[] = "i2c_omap";
39
40#define I2C_RESOURCE_BUILDER(base, irq) \
41 { \
42 .start = (base), \
43 .end = (base) + OMAP_I2C_SIZE, \
44 .flags = IORESOURCE_MEM, \
45 }, \
46 { \
47 .start = (irq), \
48 .flags = IORESOURCE_IRQ, \
49 },
50
51static struct resource i2c_resources[][2] = {
52 { I2C_RESOURCE_BUILDER(0, 0) },
53#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
54 { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) },
55#endif
56#if defined(CONFIG_ARCH_OMAP34XX)
57 { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) },
58#endif
59};
60
61#define I2C_DEV_BUILDER(bus_id, res, data) \
62 { \
63 .id = (bus_id), \
64 .name = name, \
65 .num_resources = ARRAY_SIZE(res), \
66 .resource = (res), \
67 .dev = { \
68 .platform_data = (data), \
69 }, \
70 }
71
72static u32 i2c_rate[ARRAY_SIZE(i2c_resources)];
73static struct platform_device omap_i2c_devices[] = {
74 I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]),
75#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
76 I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]),
77#endif
78#if defined(CONFIG_ARCH_OMAP34XX)
79 I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]),
80#endif
81};
82
83static void __init omap_i2c_mux_pins(int bus_id)
84{
85 /* TODO: Muxing for OMAP3 */
86 switch (bus_id) {
87 case 1:
88 if (cpu_class_is_omap1()) {
89 omap_cfg_reg(I2C_SCL);
90 omap_cfg_reg(I2C_SDA);
91 } else if (cpu_is_omap24xx()) {
92 omap_cfg_reg(M19_24XX_I2C1_SCL);
93 omap_cfg_reg(L15_24XX_I2C1_SDA);
94 }
95 break;
96 case 2:
97 if (cpu_is_omap24xx()) {
98 omap_cfg_reg(J15_24XX_I2C2_SCL);
99 omap_cfg_reg(H19_24XX_I2C2_SDA);
100 }
101 break;
102 }
103}
104
105int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
106 struct i2c_board_info const *info,
107 unsigned len)
108{
109 int ports, err;
110 struct platform_device *pdev;
111 struct resource *res;
112 resource_size_t base, irq;
113
114 if (cpu_class_is_omap1())
115 ports = 1;
116 else if (cpu_is_omap24xx())
117 ports = 2;
118 else if (cpu_is_omap34xx())
119 ports = 3;
120
121 BUG_ON(bus_id < 1 || bus_id > ports);
122
123 if (info) {
124 err = i2c_register_board_info(bus_id, info, len);
125 if (err)
126 return err;
127 }
128
129 pdev = &omap_i2c_devices[bus_id - 1];
130 *(u32 *)pdev->dev.platform_data = clkrate;
131
132 if (bus_id == 1) {
133 res = pdev->resource;
134 if (cpu_class_is_omap1()) {
135 base = OMAP1_I2C_BASE;
136 irq = INT_I2C;
137 } else {
138 base = OMAP2_I2C_BASE1;
139 irq = INT_24XX_I2C1_IRQ;
140 }
141 res[0].start = base;
142 res[0].end = base + OMAP_I2C_SIZE;
143 res[1].start = irq;
144 }
145
146 omap_i2c_mux_pins(bus_id);
147 return platform_device_register(pdev);
148}
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 2af5bd5a1344..9cf83c4da9fa 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -201,6 +201,14 @@ static int omap_mcbsp_check(unsigned int id)
201static void omap_mcbsp_dsp_request(void) 201static void omap_mcbsp_dsp_request(void)
202{ 202{
203 if (cpu_is_omap15xx() || cpu_is_omap16xx()) { 203 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
204 int ret;
205
206 ret = omap_dsp_request_mem();
207 if (ret < 0) {
208 printk(KERN_ERR "Could not get dsp memory: %i\n", ret);
209 return;
210 }
211
204 clk_enable(mcbsp_dsp_ck); 212 clk_enable(mcbsp_dsp_ck);
205 clk_enable(mcbsp_api_ck); 213 clk_enable(mcbsp_api_ck);
206 214
@@ -219,6 +227,7 @@ static void omap_mcbsp_dsp_request(void)
219static void omap_mcbsp_dsp_free(void) 227static void omap_mcbsp_dsp_free(void)
220{ 228{
221 if (cpu_is_omap15xx() || cpu_is_omap16xx()) { 229 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
230 omap_dsp_release_mem();
222 clk_disable(mcbsp_dspxor_ck); 231 clk_disable(mcbsp_dspxor_ck);
223 clk_disable(mcbsp_dsp_ck); 232 clk_disable(mcbsp_dsp_ck);
224 clk_disable(mcbsp_api_ck); 233 clk_disable(mcbsp_api_ck);
@@ -1024,6 +1033,8 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type);
1024EXPORT_SYMBOL(omap_mcbsp_free); 1033EXPORT_SYMBOL(omap_mcbsp_free);
1025EXPORT_SYMBOL(omap_mcbsp_start); 1034EXPORT_SYMBOL(omap_mcbsp_start);
1026EXPORT_SYMBOL(omap_mcbsp_stop); 1035EXPORT_SYMBOL(omap_mcbsp_stop);
1036EXPORT_SYMBOL(omap_mcbsp_pollread);
1037EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1027EXPORT_SYMBOL(omap_mcbsp_xmit_word); 1038EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1028EXPORT_SYMBOL(omap_mcbsp_recv_word); 1039EXPORT_SYMBOL(omap_mcbsp_recv_word);
1029EXPORT_SYMBOL(omap_mcbsp_xmit_buffer); 1040EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
diff --git a/include/asm-arm/arch-omap/board-apollon.h b/include/asm-arm/arch-omap/board-apollon.h
index dcb587b311f1..547125a4695e 100644
--- a/include/asm-arm/arch-omap/board-apollon.h
+++ b/include/asm-arm/arch-omap/board-apollon.h
@@ -29,6 +29,8 @@
29#ifndef __ASM_ARCH_OMAP_APOLLON_H 29#ifndef __ASM_ARCH_OMAP_APOLLON_H
30#define __ASM_ARCH_OMAP_APOLLON_H 30#define __ASM_ARCH_OMAP_APOLLON_H
31 31
32extern void apollon_mmc_init(void);
33
32/* Placeholder for APOLLON specific defines */ 34/* Placeholder for APOLLON specific defines */
33#define APOLLON_ETHR_GPIO_IRQ 74 35#define APOLLON_ETHR_GPIO_IRQ 74
34 36
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h
index b2888ef9e9b4..c322796d0d26 100644
--- a/include/asm-arm/arch-omap/board-h2.h
+++ b/include/asm-arm/arch-omap/board-h2.h
@@ -34,5 +34,8 @@
34/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ 34/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
35#define OMAP1610_ETHR_START 0x04000300 35#define OMAP1610_ETHR_START 0x04000300
36 36
37extern void h2_mmc_init(void);
38extern void h2_mmc_slot_cover_handler(void *arg, int state);
39
37#endif /* __ASM_ARCH_OMAP_H2_H */ 40#endif /* __ASM_ARCH_OMAP_H2_H */
38 41
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index 761ea0a17897..1c2b55c61ca0 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -36,5 +36,7 @@
36 36
37#define NR_IRQS (MAXIRQNUM + 1) 37#define NR_IRQS (MAXIRQNUM + 1)
38 38
39extern void __init h3_mmc_init(void);
40extern void h3_mmc_slot_cover_handler(void *arg, int state);
39 41
40#endif /* __ASM_ARCH_OMAP_H3_H */ 42#endif /* __ASM_ARCH_OMAP_H3_H */
diff --git a/include/asm-arm/arch-omap/board-sx1.h b/include/asm-arm/arch-omap/board-sx1.h
index 2bb8dd6e2d14..355adbdaae33 100644
--- a/include/asm-arm/arch-omap/board-sx1.h
+++ b/include/asm-arm/arch-omap/board-sx1.h
@@ -41,6 +41,12 @@ int sx1_getkeylight(u8 *keylight);
41 41
42int sx1_setmmipower(u8 onoff); 42int sx1_setmmipower(u8 onoff);
43int sx1_setusbpower(u8 onoff); 43int sx1_setusbpower(u8 onoff);
44int sx1_setmmcpower(u8 onoff); 44int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
45int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
46
47/* MMC prototypes */
48
49extern void sx1_mmc_init(void);
50extern void sx1_mmc_slot_cover_handler(void *arg, int state);
45 51
46#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */ 52#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 08d58abd8218..442aecbb8f44 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -27,10 +27,21 @@
27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H 27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
28#define __ARCH_ARM_MACH_OMAP_COMMON_H 28#define __ARCH_ARM_MACH_OMAP_COMMON_H
29 29
30#ifdef CONFIG_I2C_OMAP
31#include <linux/i2c.h>
32#endif
33
30struct sys_timer; 34struct sys_timer;
31 35
32extern void omap_map_common_io(void); 36extern void omap_map_common_io(void);
33extern struct sys_timer omap_timer; 37extern struct sys_timer omap_timer;
34extern void omap_serial_init(void); 38extern void omap_serial_init(void);
39#ifdef CONFIG_I2C_OMAP
40extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
41 struct i2c_board_info const *info,
42 unsigned len);
43#else
44#define omap_register_i2c_bus(a, b, c, d) 0
45#endif
35 46
36#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 47#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index ec7eb675d922..e8a4cf52778b 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -28,7 +28,7 @@
28 28
29extern unsigned int system_rev; 29extern unsigned int system_rev;
30 30
31#define omap2_cpu_rev() ((system_rev >> 8) & 0x0f) 31#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f)
32 32
33/* 33/*
34 * Test if multicore OMAP support is needed 34 * Test if multicore OMAP support is needed
@@ -61,12 +61,33 @@ extern unsigned int system_rev;
61# define OMAP_NAME omap16xx 61# define OMAP_NAME omap16xx
62# endif 62# endif
63#endif 63#endif
64#ifdef CONFIG_ARCH_OMAP24XX 64#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) 65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
66# error "OMAP1 and OMAP2 can't be selected at the same time" 66# error "OMAP1 and OMAP2 can't be selected at the same time"
67# endif
68#endif
69#ifdef CONFIG_ARCH_OMAP2420
70# ifdef OMAP_NAME
71# undef MULTI_OMAP2
72# define MULTI_OMAP2
67# else 73# else
74# define OMAP_NAME omap2420
75# endif
76#endif
77#ifdef CONFIG_ARCH_OMAP2430
78# ifdef OMAP_NAME
79# undef MULTI_OMAP2
80# define MULTI_OMAP2
81# else
82# define OMAP_NAME omap2430
83# endif
84#endif
85#ifdef CONFIG_ARCH_OMAP3430
86# ifdef OMAP_NAME
68# undef MULTI_OMAP2 87# undef MULTI_OMAP2
69# define OMAP_NAME omap24xx 88# define MULTI_OMAP2
89# else
90# define OMAP_NAME omap3430
70# endif 91# endif
71#endif 92#endif
72 93
@@ -79,8 +100,9 @@ extern unsigned int system_rev;
79 * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 100 * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
80 * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 101 * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
81 * cpu_is_omap243x(): True for OMAP2430 102 * cpu_is_omap243x(): True for OMAP2430
103 * cpu_is_omap343x(): True for OMAP3430
82 */ 104 */
83#define GET_OMAP_CLASS (system_rev & 0xff) 105#define GET_OMAP_CLASS ((system_rev >> 24) & 0xff)
84 106
85#define IS_OMAP_CLASS(class, id) \ 107#define IS_OMAP_CLASS(class, id) \
86static inline int is_omap ##class (void) \ 108static inline int is_omap ##class (void) \
@@ -100,9 +122,11 @@ IS_OMAP_CLASS(7xx, 0x07)
100IS_OMAP_CLASS(15xx, 0x15) 122IS_OMAP_CLASS(15xx, 0x15)
101IS_OMAP_CLASS(16xx, 0x16) 123IS_OMAP_CLASS(16xx, 0x16)
102IS_OMAP_CLASS(24xx, 0x24) 124IS_OMAP_CLASS(24xx, 0x24)
125IS_OMAP_CLASS(34xx, 0x34)
103 126
104IS_OMAP_SUBCLASS(242x, 0x242) 127IS_OMAP_SUBCLASS(242x, 0x242)
105IS_OMAP_SUBCLASS(243x, 0x243) 128IS_OMAP_SUBCLASS(243x, 0x243)
129IS_OMAP_SUBCLASS(343x, 0x343)
106 130
107#define cpu_is_omap7xx() 0 131#define cpu_is_omap7xx() 0
108#define cpu_is_omap15xx() 0 132#define cpu_is_omap15xx() 0
@@ -110,6 +134,8 @@ IS_OMAP_SUBCLASS(243x, 0x243)
110#define cpu_is_omap24xx() 0 134#define cpu_is_omap24xx() 0
111#define cpu_is_omap242x() 0 135#define cpu_is_omap242x() 0
112#define cpu_is_omap243x() 0 136#define cpu_is_omap243x() 0
137#define cpu_is_omap34xx() 0
138#define cpu_is_omap343x() 0
113 139
114#if defined(MULTI_OMAP1) 140#if defined(MULTI_OMAP1)
115# if defined(CONFIG_ARCH_OMAP730) 141# if defined(CONFIG_ARCH_OMAP730)
@@ -137,14 +163,44 @@ IS_OMAP_SUBCLASS(243x, 0x243)
137# undef cpu_is_omap16xx 163# undef cpu_is_omap16xx
138# define cpu_is_omap16xx() 1 164# define cpu_is_omap16xx() 1
139# endif 165# endif
166#endif
167
168#if defined(MULTI_OMAP2)
140# if defined(CONFIG_ARCH_OMAP24XX) 169# if defined(CONFIG_ARCH_OMAP24XX)
141# undef cpu_is_omap24xx 170# undef cpu_is_omap24xx
142# undef cpu_is_omap242x 171# undef cpu_is_omap242x
143# undef cpu_is_omap243x 172# undef cpu_is_omap243x
144# define cpu_is_omap24xx() 1 173# define cpu_is_omap24xx() is_omap24xx()
145# define cpu_is_omap242x() is_omap242x() 174# define cpu_is_omap242x() is_omap242x()
146# define cpu_is_omap243x() is_omap243x() 175# define cpu_is_omap243x() is_omap243x()
147# endif 176# endif
177# if defined(CONFIG_ARCH_OMAP34XX)
178# undef cpu_is_omap34xx
179# undef cpu_is_omap343x
180# define cpu_is_omap34xx() is_omap34xx()
181# define cpu_is_omap343x() is_omap343x()
182# endif
183#else
184# if defined(CONFIG_ARCH_OMAP24XX)
185# undef cpu_is_omap24xx
186# define cpu_is_omap24xx() 1
187# endif
188# if defined(CONFIG_ARCH_OMAP2420)
189# undef cpu_is_omap242x
190# define cpu_is_omap242x() 1
191# endif
192# if defined(CONFIG_ARCH_OMAP2430)
193# undef cpu_is_omap243x
194# define cpu_is_omap243x() 1
195# endif
196# if defined(CONFIG_ARCH_OMAP34XX)
197# undef cpu_is_omap34xx
198# define cpu_is_omap34xx() 1
199# endif
200# if defined(CONFIG_ARCH_OMAP3430)
201# undef cpu_is_omap343x
202# define cpu_is_omap343x() 1
203# endif
148#endif 204#endif
149 205
150/* 206/*
@@ -162,6 +218,7 @@ IS_OMAP_SUBCLASS(243x, 0x243)
162 * cpu_is_omap2422(): True for OMAP2422 218 * cpu_is_omap2422(): True for OMAP2422
163 * cpu_is_omap2423(): True for OMAP2423 219 * cpu_is_omap2423(): True for OMAP2423
164 * cpu_is_omap2430(): True for OMAP2430 220 * cpu_is_omap2430(): True for OMAP2430
221 * cpu_is_omap3430(): True for OMAP3430
165 */ 222 */
166#define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff) 223#define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff)
167 224
@@ -183,6 +240,7 @@ IS_OMAP_TYPE(2420, 0x2420)
183IS_OMAP_TYPE(2422, 0x2422) 240IS_OMAP_TYPE(2422, 0x2422)
184IS_OMAP_TYPE(2423, 0x2423) 241IS_OMAP_TYPE(2423, 0x2423)
185IS_OMAP_TYPE(2430, 0x2430) 242IS_OMAP_TYPE(2430, 0x2430)
243IS_OMAP_TYPE(3430, 0x3430)
186 244
187#define cpu_is_omap310() 0 245#define cpu_is_omap310() 0
188#define cpu_is_omap730() 0 246#define cpu_is_omap730() 0
@@ -196,6 +254,7 @@ IS_OMAP_TYPE(2430, 0x2430)
196#define cpu_is_omap2422() 0 254#define cpu_is_omap2422() 0
197#define cpu_is_omap2423() 0 255#define cpu_is_omap2423() 0
198#define cpu_is_omap2430() 0 256#define cpu_is_omap2430() 0
257#define cpu_is_omap3430() 0
199 258
200#if defined(MULTI_OMAP1) 259#if defined(MULTI_OMAP1)
201# if defined(CONFIG_ARCH_OMAP730) 260# if defined(CONFIG_ARCH_OMAP730)
@@ -244,9 +303,65 @@ IS_OMAP_TYPE(2430, 0x2430)
244# define cpu_is_omap2430() is_omap2430() 303# define cpu_is_omap2430() is_omap2430()
245#endif 304#endif
246 305
306#if defined(CONFIG_ARCH_OMAP34XX)
307# undef cpu_is_omap3430
308# define cpu_is_omap3430() is_omap3430()
309#endif
310
247/* Macros to detect if we have OMAP1 or OMAP2 */ 311/* Macros to detect if we have OMAP1 or OMAP2 */
248#define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \ 312#define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \
249 cpu_is_omap16xx()) 313 cpu_is_omap16xx())
250#define cpu_class_is_omap2() cpu_is_omap24xx() 314#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx())
315
316#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
317/*
318 * Macros to detect silicon revision of OMAP2/3 processors.
319 * is_sil_rev_greater_than: true if passed cpu type & its rev is greater.
320 * is_sil_rev_lesser_than: true if passed cpu type & its rev is lesser.
321 * is_sil_rev_equal_to: true if passed cpu type & its rev is equal.
322 * get_sil_rev: return the silicon rev value.
323 */
324#define get_sil_omap_type(rev) ((rev & 0xffff0000) >> 16)
325#define get_sil_revision(rev) ((rev & 0x0000f000) >> 12)
326
327#define is_sil_rev_greater_than(rev) \
328 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
329 (get_sil_revision(system_rev) > get_sil_revision(rev)))
330
331#define is_sil_rev_less_than(rev) \
332 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
333 (get_sil_revision(system_rev) < get_sil_revision(rev)))
334
335#define is_sil_rev_equal_to(rev) \
336 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
337 (get_sil_revision(system_rev) == get_sil_revision(rev)))
338
339#define get_sil_rev() \
340 get_sil_revision(system_rev)
341
342/* Various silicon macros defined here */
343#define OMAP2420_REV_ES1_0 0x24200000
344#define OMAP2420_REV_ES2_0 0x24201000
345#define OMAP2430_REV_ES1_0 0x24300000
346#define OMAP3430_REV_ES1_0 0x34300000
347#define OMAP3430_REV_ES2_0 0x34301000
348
349/*
350 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
351 */
352#define DEVICE_TYPE_TEST 0
353#define DEVICE_TYPE_EMU 1
354#define DEVICE_TYPE_SEC 2
355#define DEVICE_TYPE_GP 3
356#define DEVICE_TYPE_BAD 4
357
358#define get_device_type() ((system_rev & 0x700) >> 8)
359#define is_device_type_test() (get_device_type() == DEVICE_TYPE_TEST)
360#define is_device_type_emu() (get_device_type() == DEVICE_TYPE_EMU)
361#define is_device_type_sec() (get_device_type() == DEVICE_TYPE_SEC)
362#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP)
363#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD)
364
365#endif
251 366
252#endif 367#endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index f33b467fddb7..24acf090030d 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -45,22 +45,28 @@
45#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) 45#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
46 46
47/* Hardware registers for omap2 */ 47/* Hardware registers for omap2 */
48#define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000) 48#if defined(CONFIG_ARCH_OMAP3)
49#define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00) 49#define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000)
50#define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78) 50#else /* CONFIG_ARCH_OMAP2 */
51#define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08) 51#define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000)
52#define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c) 52#endif
53#define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10) 53
54#define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14) 54#define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00)
55#define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18) 55#define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78)
56#define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c) 56#define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08)
57#define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20) 57#define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c)
58#define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24) 58#define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10)
59#define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28) 59#define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14)
60#define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64) 60#define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18)
61#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c) 61#define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c)
62#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70) 62#define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20)
63#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74) 63#define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24)
64#define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28)
65#define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c)
66#define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64)
67#define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c)
68#define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70)
69#define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74)
64 70
65#ifdef CONFIG_ARCH_OMAP1 71#ifdef CONFIG_ARCH_OMAP1
66 72
@@ -86,19 +92,19 @@
86#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ 92#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
87 93
88/* Common channel specific registers for omap2 */ 94/* Common channel specific registers for omap2 */
89#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80) 95#define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
90#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84) 96#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
91#define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88) 97#define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
92#define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c) 98#define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
93#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90) 99#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
94#define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94) 100#define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
95#define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98) 101#define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
96#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4) 102#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
97#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8) 103#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
98#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac) 104#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
99#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0) 105#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
100#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4) 106#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
101#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8) 107#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
102 108
103#endif 109#endif
104 110
@@ -113,11 +119,11 @@
113#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) 119#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
114 120
115/* Channel specific registers only on omap2 */ 121/* Channel specific registers only on omap2 */
116#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c) 122#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
117#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0) 123#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
118#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc) 124#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
119#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0) 125#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
120#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4) 126#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
121 127
122/*----------------------------------------------------------------------------*/ 128/*----------------------------------------------------------------------------*/
123 129
@@ -297,6 +303,10 @@
297#define OMAP_DMA_SYNC_ELEMENT 0x00 303#define OMAP_DMA_SYNC_ELEMENT 0x00
298#define OMAP_DMA_SYNC_FRAME 0x01 304#define OMAP_DMA_SYNC_FRAME 0x01
299#define OMAP_DMA_SYNC_BLOCK 0x02 305#define OMAP_DMA_SYNC_BLOCK 0x02
306#define OMAP_DMA_SYNC_PACKET 0x03
307
308#define OMAP_DMA_SRC_SYNC 0x01
309#define OMAP_DMA_DST_SYNC 0x00
300 310
301#define OMAP_DMA_PORT_EMIFF 0x00 311#define OMAP_DMA_PORT_EMIFF 0x00
302#define OMAP_DMA_PORT_EMIFS 0x01 312#define OMAP_DMA_PORT_EMIFS 0x01
@@ -310,6 +320,29 @@
310#define OMAP_DMA_AMODE_SINGLE_IDX 0x02 320#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
311#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 321#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
312 322
323#define DMA_DEFAULT_FIFO_DEPTH 0x10
324#define DMA_DEFAULT_ARB_RATE 0x01
325/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
326#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
327#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
328#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
329#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
330#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
331#define DMA_THREAD_FIFO_75 (0x01 << 14)
332#define DMA_THREAD_FIFO_25 (0x02 << 14)
333#define DMA_THREAD_FIFO_50 (0x03 << 14)
334
335/* Chaining modes*/
336#ifndef CONFIG_ARCH_OMAP1
337#define OMAP_DMA_STATIC_CHAIN 0x1
338#define OMAP_DMA_DYNAMIC_CHAIN 0x2
339#define OMAP_DMA_CHAIN_ACTIVE 0x1
340#define OMAP_DMA_CHAIN_INACTIVE 0x0
341#endif
342
343#define DMA_CH_PRIO_HIGH 0x1
344#define DMA_CH_PRIO_LOW 0x0 /* Def */
345
313/* LCD DMA block numbers */ 346/* LCD DMA block numbers */
314enum { 347enum {
315 OMAP_LCD_DMA_B1_TOP, 348 OMAP_LCD_DMA_B1_TOP,
@@ -359,6 +392,13 @@ struct omap_dma_channel_params {
359 int src_or_dst_synch; /* source synch(1) or destination synch(0) */ 392 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
360 393
361 int ie; /* interrupt enabled */ 394 int ie; /* interrupt enabled */
395
396 unsigned char read_prio;/* read priority */
397 unsigned char write_prio;/* write priority */
398
399#ifndef CONFIG_ARCH_OMAP1
400 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
401#endif
362}; 402};
363 403
364 404
@@ -409,6 +449,33 @@ extern dma_addr_t omap_get_dma_dst_pos(int lch);
409extern int omap_get_dma_src_addr_counter(int lch); 449extern int omap_get_dma_src_addr_counter(int lch);
410extern void omap_clear_dma(int lch); 450extern void omap_clear_dma(int lch);
411extern int omap_dma_running(void); 451extern int omap_dma_running(void);
452extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
453 int tparams);
454extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
455 unsigned char write_prio);
456
457/* Chaining APIs */
458#ifndef CONFIG_ARCH_OMAP1
459extern int omap_request_dma_chain(int dev_id, const char *dev_name,
460 void (*callback) (int chain_id, u16 ch_status,
461 void *data),
462 int *chain_id, int no_of_chans,
463 int chain_mode,
464 struct omap_dma_channel_params params);
465extern int omap_free_dma_chain(int chain_id);
466extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
467 int dest_start, int elem_count,
468 int frame_count, void *callbk_data);
469extern int omap_start_dma_chain_transfers(int chain_id);
470extern int omap_stop_dma_chain_transfers(int chain_id);
471extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
472extern int omap_get_dma_chain_dst_pos(int chain_id);
473extern int omap_get_dma_chain_src_pos(int chain_id);
474
475extern int omap_modify_dma_chain_params(int chain_id,
476 struct omap_dma_channel_params params);
477extern int omap_dma_chain_status(int chain_id);
478#endif
412 479
413/* LCD DMA functions */ 480/* LCD DMA functions */
414extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), 481extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
index 97b397dd7e87..164da09be095 100644
--- a/include/asm-arm/arch-omap/gpio.h
+++ b/include/asm-arm/arch-omap/gpio.h
@@ -62,6 +62,8 @@
62#define OMAP_MPUIO_LATCH 0x34 62#define OMAP_MPUIO_LATCH 0x34
63#endif 63#endif
64 64
65#define OMAP34XX_NR_GPIOS 6
66
65#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) 67#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
66#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) 68#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
67 69
@@ -75,6 +77,8 @@ extern void omap_free_gpio(int gpio);
75extern void omap_set_gpio_direction(int gpio, int is_input); 77extern void omap_set_gpio_direction(int gpio, int is_input);
76extern void omap_set_gpio_dataout(int gpio, int enable); 78extern void omap_set_gpio_dataout(int gpio, int enable);
77extern int omap_get_gpio_datain(int gpio); 79extern int omap_get_gpio_datain(int gpio);
80extern void omap_set_gpio_debounce(int gpio, int enable);
81extern void omap_set_gpio_debounce_time(int gpio, int enable);
78 82
79/*-------------------------------------------------------------------------*/ 83/*-------------------------------------------------------------------------*/
80 84
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 3ede58b51db2..87973654e625 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -263,6 +263,8 @@
263#define INT_24XX_GPTIMER10 46 263#define INT_24XX_GPTIMER10 46
264#define INT_24XX_GPTIMER11 47 264#define INT_24XX_GPTIMER11 47
265#define INT_24XX_GPTIMER12 48 265#define INT_24XX_GPTIMER12 48
266#define INT_24XX_I2C1_IRQ 56
267#define INT_24XX_I2C2_IRQ 57
266#define INT_24XX_MCBSP1_IRQ_TX 59 268#define INT_24XX_MCBSP1_IRQ_TX 59
267#define INT_24XX_MCBSP1_IRQ_RX 60 269#define INT_24XX_MCBSP1_IRQ_RX 60
268#define INT_24XX_MCBSP2_IRQ_TX 62 270#define INT_24XX_MCBSP2_IRQ_TX 62
diff --git a/include/asm-arm/arch-omap/nand.h b/include/asm-arm/arch-omap/nand.h
new file mode 100644
index 000000000000..17ae26e35353
--- /dev/null
+++ b/include/asm-arm/arch-omap/nand.h
@@ -0,0 +1,24 @@
1/*
2 * include/asm-arm/arch-omap/nand.h
3 *
4 * Copyright (C) 2006 Micron Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/mtd/partitions.h>
12
13struct omap_nand_platform_data {
14 unsigned int options;
15 int cs;
16 int gpio_irq;
17 struct mtd_partition *parts;
18 int nr_parts;
19 int (*nand_setup)(void __iomem *);
20 int (*dev_ready)(struct omap_nand_platform_data *);
21 int dma_channel;
22 void __iomem *gpmc_cs_baseaddr;
23 void __iomem *gpmc_baseaddr;
24};
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S
index e2a80641f214..2746220f5d85 100644
--- a/include/asm-arm/arch-orion/debug-macro.S
+++ b/include/asm-arm/arch-orion/debug-macro.S
@@ -8,9 +8,14 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9*/ 9*/
10 10
11#include <asm/arch/orion.h>
12
11 .macro addruart,rx 13 .macro addruart,rx
12 mov \rx, #0xf1000000 14 mrc p15, 0, \rx, c1, c0
13 orr \rx, \rx, #0x00012000 15 tst \rx, #1 @ MMU enabled?
16 ldreq \rx, =ORION_REGS_PHYS_BASE
17 ldrne \rx, =ORION_REGS_VIRT_BASE
18 orr \rx, \rx, #0x00012000
14 .endm 19 .endm
15 20
16#define UART_SHIFT 2 21#define UART_SHIFT 2
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion/entry-macro.S
index b76075a7e44b..cda096b2acfd 100644
--- a/include/asm-arm/arch-orion/entry-macro.S
+++ b/include/asm-arm/arch-orion/entry-macro.S
@@ -3,8 +3,8 @@
3 * 3 *
4 * Low-level IRQ helper macros for Orion platforms 4 * Low-level IRQ helper macros for Orion platforms
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any 7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 10
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h
index 8a12d213fbdc..65da374de735 100644
--- a/include/asm-arm/arch-orion/hardware.h
+++ b/include/asm-arm/arch-orion/hardware.h
@@ -4,7 +4,6 @@
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 *
8 */ 7 */
9 8
10#ifndef __ASM_ARCH_HARDWARE_H__ 9#ifndef __ASM_ARCH_HARDWARE_H__
@@ -12,13 +11,11 @@
12 11
13#include "orion.h" 12#include "orion.h"
14 13
15#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE 14#define pcibios_assign_all_busses() 1
16#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
17 15
18#define pcibios_assign_all_busses() 1 16#define PCIBIOS_MIN_IO 0x00001000
17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE
19 19
20#define PCIBIOS_MIN_IO 0x1000
21#define PCIBIOS_MIN_MEM 0x01000000
22#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
23 20
24#endif /* _ASM_ARCH_HARDWARE_H */ 21#endif
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
index f787f752e58c..673a418a7419 100644
--- a/include/asm-arm/arch-orion/orion.h
+++ b/include/asm-arm/arch-orion/orion.h
@@ -14,32 +14,40 @@
14#ifndef __ASM_ARCH_ORION_H__ 14#ifndef __ASM_ARCH_ORION_H__
15#define __ASM_ARCH_ORION_H__ 15#define __ASM_ARCH_ORION_H__
16 16
17/******************************************************************************* 17/*****************************************************************************
18 * Orion Address Map 18 * Orion Address Map
19 * Use the same mapping (1:1 virtual:physical) of internal registers and 19 *
20 * PCI system (PCI+PCIE) for all machines. 20 * virt phys size
21 * Each machine defines the rest of its mapping (e.g. device bus flashes) 21 * fdd00000 f1000000 1M on-chip peripheral registers
22 ******************************************************************************/ 22 * fde00000 f2000000 1M PCIe I/O space
23#define ORION_REGS_BASE 0xf1000000 23 * fdf00000 f2100000 1M PCI I/O space
24 * fe000000 f0000000 16M PCIe WA space (Orion-NAS only)
25 ****************************************************************************/
26#define ORION_REGS_PHYS_BASE 0xf1000000
27#define ORION_REGS_VIRT_BASE 0xfdd00000
24#define ORION_REGS_SIZE SZ_1M 28#define ORION_REGS_SIZE SZ_1M
25 29
26#define ORION_PCI_SYS_MEM_BASE 0xe0000000 30#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
27#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE 31#define ORION_PCIE_IO_VIRT_BASE 0xfde00000
28#define ORION_PCIE_MEM_SIZE SZ_128M 32#define ORION_PCIE_IO_BUS_BASE 0x00000000
29#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
30#define ORION_PCI_MEM_SIZE SZ_128M
31
32#define ORION_PCI_SYS_IO_BASE 0xf2000000
33#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
34#define ORION_PCIE_IO_SIZE SZ_1M 33#define ORION_PCIE_IO_SIZE SZ_1M
35#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE) 34
36#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE) 35#define ORION_PCI_IO_PHYS_BASE 0xf2100000
36#define ORION_PCI_IO_VIRT_BASE 0xfdf00000
37#define ORION_PCI_IO_BUS_BASE 0x00100000
37#define ORION_PCI_IO_SIZE SZ_1M 38#define ORION_PCI_IO_SIZE SZ_1M
38#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE) 39
39/* Relevant only for Orion-NAS */ 40/* Relevant only for Orion-NAS */
40#define ORION_PCIE_WA_BASE 0xf0000000 41#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
42#define ORION_PCIE_WA_VIRT_BASE 0xfe000000
41#define ORION_PCIE_WA_SIZE SZ_16M 43#define ORION_PCIE_WA_SIZE SZ_16M
42 44
45#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000
46#define ORION_PCIE_MEM_SIZE SZ_128M
47
48#define ORION_PCI_MEM_PHYS_BASE 0xe8000000
49#define ORION_PCI_MEM_SIZE SZ_128M
50
43/******************************************************************************* 51/*******************************************************************************
44 * Supported Devices & Revisions 52 * Supported Devices & Revisions
45 ******************************************************************************/ 53 ******************************************************************************/
@@ -57,25 +65,42 @@
57/******************************************************************************* 65/*******************************************************************************
58 * Orion Registers Map 66 * Orion Registers Map
59 ******************************************************************************/ 67 ******************************************************************************/
60#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000) 68#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000)
61#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000) 69#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x))
62#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000) 70
63#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000) 71#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000)
64#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000) 72#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000)
65#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000) 73#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x))
66#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000) 74#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000)
67#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000) 75#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000)
68#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000) 76#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000)
69 77#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100)
70#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x)) 78#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100)
71#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x)) 79
72#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x)) 80#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
73#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x)) 81#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
74#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x)) 82
75#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x)) 83#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
76#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x)) 84#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
77#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x)) 85
78#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x)) 86#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000)
87#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x))
88
89#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000)
90#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000)
91#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x))
92
93#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000)
94#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000)
95#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x))
96
97#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000)
98#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000)
99#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x))
100
101#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000)
102#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000)
103#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x))
79 104
80/******************************************************************************* 105/*******************************************************************************
81 * Device Bus Registers 106 * Device Bus Registers
@@ -100,9 +125,6 @@
100#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) 125#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
101#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) 126#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
102#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) 127#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
103#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
104#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
105#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
106#define GPIO_MAX 32 128#define GPIO_MAX 32
107 129
108/*************************************************************************** 130/***************************************************************************
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h
index a1a222fb438c..59f44039909a 100644
--- a/include/asm-arm/arch-orion/uncompress.h
+++ b/include/asm-arm/arch-orion/uncompress.h
@@ -10,8 +10,8 @@
10 10
11#include <asm/arch/orion.h> 11#include <asm/arch/orion.h>
12 12
13#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14)) 13#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
14#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0)) 14#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
15 15
16#define LSR_THRE 0x20 16#define LSR_THRE 0x20
17 17
@@ -27,16 +27,6 @@ static void flush(void)
27{ 27{
28} 28}
29 29
30static void orion_early_putstr(const char *ptr)
31{
32 char c;
33 while ((c = *ptr++) != '\0') {
34 if (c == '\n')
35 putc('\r');
36 putc(c);
37 }
38}
39
40/* 30/*
41 * nothing to do 31 * nothing to do
42 */ 32 */
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion/vmalloc.h
index 23e2a102fe0c..9d580278d2bc 100644
--- a/include/asm-arm/arch-orion/vmalloc.h
+++ b/include/asm-arm/arch-orion/vmalloc.h
@@ -2,4 +2,4 @@
2 * include/asm-arm/arch-orion/vmalloc.h 2 * include/asm-arm/arch-orion/vmalloc.h
3 */ 3 */
4 4
5#define VMALLOC_END 0xf0000000 5#define VMALLOC_END 0xfd800000
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 18:59:57 -0500