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-rw-r--r--Documentation/feature-removal-schedule.txt10
-rw-r--r--arch/mips/Kconfig47
-rw-r--r--arch/mips/Makefile13
-rw-r--r--arch/mips/configs/it8172_defconfig964
-rw-r--r--arch/mips/configs/ivr_defconfig920
-rw-r--r--arch/mips/ite-boards/Kconfig8
-rw-r--r--arch/mips/ite-boards/generic/Makefile15
-rw-r--r--arch/mips/ite-boards/generic/dbg_io.c124
-rw-r--r--arch/mips/ite-boards/generic/irq.c308
-rw-r--r--arch/mips/ite-boards/generic/it8172_cir.c170
-rw-r--r--arch/mips/ite-boards/generic/it8172_setup.c352
-rw-r--r--arch/mips/ite-boards/generic/lpc.c144
-rw-r--r--arch/mips/ite-boards/generic/pmon_prom.c135
-rw-r--r--arch/mips/ite-boards/generic/puts.c139
-rw-r--r--arch/mips/ite-boards/generic/reset.c60
-rw-r--r--arch/mips/ite-boards/generic/time.c249
-rw-r--r--arch/mips/ite-boards/ivr/Makefile10
-rw-r--r--arch/mips/ite-boards/ivr/README3
-rw-r--r--arch/mips/ite-boards/ivr/init.c81
-rw-r--r--arch/mips/ite-boards/qed-4n-s01b/Makefile10
-rw-r--r--arch/mips/ite-boards/qed-4n-s01b/README2
-rw-r--r--arch/mips/ite-boards/qed-4n-s01b/init.c82
-rw-r--r--arch/mips/pci/Makefile3
-rw-r--r--arch/mips/pci/fixup-ite8172g.c80
-rw-r--r--arch/mips/pci/fixup-ivr.c75
-rw-r--r--arch/mips/pci/ops-it8172.c213
-rw-r--r--drivers/char/.gitignore1
-rw-r--r--drivers/char/Kconfig30
-rw-r--r--drivers/char/Makefile6
-rw-r--r--drivers/char/ite_gpio.c419
-rw-r--r--drivers/char/qtronixmap.c_shipped265
-rw-r--r--drivers/char/qtronixmap.map287
-rw-r--r--drivers/ide/Kconfig9
-rw-r--r--drivers/ide/pci/Makefile1
-rw-r--r--drivers/ide/pci/it8172.c307
-rw-r--r--include/asm-mips/bootinfo.h12
-rw-r--r--include/asm-mips/it8172/it8172.h348
-rw-r--r--include/asm-mips/it8172/it8172_cir.h140
-rw-r--r--include/asm-mips/it8172/it8172_dbg.h38
-rw-r--r--include/asm-mips/it8172/it8172_int.h144
-rw-r--r--include/asm-mips/it8172/it8172_pci.h108
-rw-r--r--include/asm-mips/it8712.h28
-rw-r--r--include/asm-mips/serial.h34
-rw-r--r--include/linux/ite_gpio.h66
-rw-r--r--include/linux/pci_ids.h2
-rw-r--r--sound/oss/Kconfig4
-rw-r--r--sound/oss/Makefile1
-rw-r--r--sound/oss/ite8172.c2261
48 files changed, 2 insertions, 8726 deletions
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt
index 68d2ee743ba4..2e410f5aa750 100644
--- a/Documentation/feature-removal-schedule.txt
+++ b/Documentation/feature-removal-schedule.txt
@@ -211,16 +211,6 @@ Who: Nick Piggin <npiggin@suse.de>
211 211
212--------------------------- 212---------------------------
213 213
214What: Support for the IT8172-based platforms, ITE 8172G and Globespan IVR
215When: September 2006
216Why: Code does no longer build since at least 2.6.0, apparently there is
217 no user base left for these platforms. Hardware out of production
218 since several years and hardly a trace of the manufacturer left on
219 the net.
220Who: Ralf Baechle <ralf@linux-mips.org>
221
222---------------------------
223
224What: Interrupt only SA_* flags 214What: Interrupt only SA_* flags
225When: Januar 2007 215When: Januar 2007
226Why: The interrupt related SA_* flags are replaced by IRQF_* to move them 216Why: The interrupt related SA_* flags are replaced by IRQF_* to move them
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 87cee341eb54..9fe90507e6c7 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -203,39 +203,6 @@ config MIPS_EV64120
203 <http://www.marvell.com/>. Say Y here if you wish to build a 203 <http://www.marvell.com/>. Say Y here if you wish to build a
204 kernel for this platform. 204 kernel for this platform.
205 205
206config MIPS_IVR
207 bool "Globespan IVR board"
208 select DMA_NONCOHERENT
209 select HW_HAS_PCI
210 select ITE_BOARD_GEN
211 select SYS_HAS_CPU_NEVADA
212 select SYS_SUPPORTS_32BIT_KERNEL
213 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
214 select SYS_SUPPORTS_LITTLE_ENDIAN
215 help
216 This is an evaluation board built by Globespan to showcase thir
217 iVR (Internet Video Recorder) design. It utilizes a QED RM5231
218 R5000 MIPS core. More information can be found out their website
219 located at <http://www.globespan.net/>. Say Y here if you wish to
220 build a kernel for this platform.
221
222config MIPS_ITE8172
223 bool "ITE 8172G board"
224 select DMA_NONCOHERENT
225 select HW_HAS_PCI
226 select ITE_BOARD_GEN
227 select SYS_HAS_CPU_R5432
228 select SYS_HAS_CPU_NEVADA
229 select SYS_SUPPORTS_32BIT_KERNEL
230 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
231 select SYS_SUPPORTS_LITTLE_ENDIAN
232 help
233 Ths is an evaluation board made by ITE <http://www.ite.com.tw/>
234 with ATX form factor that utilizes a MIPS R5000 to work with its
235 ITE8172G companion internet appliance chip. The MIPS core can be
236 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
237 a kernel for this platform.
238
239config MACH_JAZZ 206config MACH_JAZZ
240 bool "Jazz family of machines" 207 bool "Jazz family of machines"
241 select ARC 208 select ARC
@@ -804,7 +771,6 @@ endchoice
804source "arch/mips/ddb5xxx/Kconfig" 771source "arch/mips/ddb5xxx/Kconfig"
805source "arch/mips/gt64120/ev64120/Kconfig" 772source "arch/mips/gt64120/ev64120/Kconfig"
806source "arch/mips/jazz/Kconfig" 773source "arch/mips/jazz/Kconfig"
807source "arch/mips/ite-boards/Kconfig"
808source "arch/mips/lasat/Kconfig" 774source "arch/mips/lasat/Kconfig"
809source "arch/mips/momentum/Kconfig" 775source "arch/mips/momentum/Kconfig"
810source "arch/mips/pmc-sierra/Kconfig" 776source "arch/mips/pmc-sierra/Kconfig"
@@ -964,9 +930,6 @@ config MIPS_RM9122
964config PCI_MARVELL 930config PCI_MARVELL
965 bool 931 bool
966 932
967config ITE_BOARD_GEN
968 bool
969
970config SOC_AU1000 933config SOC_AU1000
971 bool 934 bool
972 select SOC_AU1X00 935 select SOC_AU1X00
@@ -1050,16 +1013,6 @@ config AU1X00_USB_DEVICE
1050 depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 1013 depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000
1051 default n 1014 default n
1052 1015
1053config IT8172_CIR
1054 bool
1055 depends on MIPS_ITE8172 || MIPS_IVR
1056 default y
1057
1058config IT8712
1059 bool
1060 depends on MIPS_ITE8172
1061 default y
1062
1063config BOOT_ELF32 1016config BOOT_ELF32
1064 bool 1017 bool
1065 1018
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index e521826b4234..2124350ab94d 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -287,19 +287,6 @@ cflags-$(CONFIG_WR_PPMC) += -Iinclude/asm-mips/mach-wrppmc
287load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 287load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
288 288
289# 289#
290# Globespan IVR eval board with QED 5231 CPU
291#
292core-$(CONFIG_ITE_BOARD_GEN) += arch/mips/ite-boards/generic/
293core-$(CONFIG_MIPS_IVR) += arch/mips/ite-boards/ivr/
294load-$(CONFIG_MIPS_IVR) += 0xffffffff80100000
295
296#
297# ITE 8172 eval board with QED 5231 CPU
298#
299core-$(CONFIG_MIPS_ITE8172) += arch/mips/ite-boards/qed-4n-s01b/
300load-$(CONFIG_MIPS_ITE8172) += 0xffffffff80100000
301
302#
303# For all MIPS, Inc. eval boards 290# For all MIPS, Inc. eval boards
304# 291#
305core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/ 292core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/
diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig
deleted file mode 100644
index 18d20fb7d5f0..000000000000
--- a/arch/mips/configs/it8172_defconfig
+++ /dev/null
@@ -1,964 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.18-rc1
4# Thu Jul 6 10:04:11 2006
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MIPS_MTX1 is not set
12# CONFIG_MIPS_BOSPORUS is not set
13# CONFIG_MIPS_PB1000 is not set
14# CONFIG_MIPS_PB1100 is not set
15# CONFIG_MIPS_PB1500 is not set
16# CONFIG_MIPS_PB1550 is not set
17# CONFIG_MIPS_PB1200 is not set
18# CONFIG_MIPS_DB1000 is not set
19# CONFIG_MIPS_DB1100 is not set
20# CONFIG_MIPS_DB1500 is not set
21# CONFIG_MIPS_DB1550 is not set
22# CONFIG_MIPS_DB1200 is not set
23# CONFIG_MIPS_MIRAGE is not set
24# CONFIG_BASLER_EXCITE is not set
25# CONFIG_MIPS_COBALT is not set
26# CONFIG_MACH_DECSTATION is not set
27# CONFIG_MIPS_EV64120 is not set
28# CONFIG_MIPS_IVR is not set
29CONFIG_MIPS_ITE8172=y
30# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set
35# CONFIG_WR_PPMC is not set
36# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_V2PCI is not set
44# CONFIG_PNX8550_JBS is not set
45# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set
48# CONFIG_QEMU is not set
49# CONFIG_MARKEINS is not set
50# CONFIG_SGI_IP22 is not set
51# CONFIG_SGI_IP27 is not set
52# CONFIG_SGI_IP32 is not set
53# CONFIG_SIBYTE_BIGSUR is not set
54# CONFIG_SIBYTE_SWARM is not set
55# CONFIG_SIBYTE_SENTOSA is not set
56# CONFIG_SIBYTE_RHONE is not set
57# CONFIG_SIBYTE_CARMEL is not set
58# CONFIG_SIBYTE_PTSWARM is not set
59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set
63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set
66# CONFIG_IT8172_REVC is not set
67CONFIG_RWSEM_GENERIC_SPINLOCK=y
68CONFIG_GENERIC_FIND_NEXT_BIT=y
69CONFIG_GENERIC_HWEIGHT=y
70CONFIG_GENERIC_CALIBRATE_DELAY=y
71CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
72CONFIG_DMA_NONCOHERENT=y
73CONFIG_DMA_NEED_PCI_MAP_STATE=y
74# CONFIG_CPU_BIG_ENDIAN is not set
75CONFIG_CPU_LITTLE_ENDIAN=y
76CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
77CONFIG_ITE_BOARD_GEN=y
78CONFIG_IT8172_CIR=y
79CONFIG_IT8712=y
80CONFIG_MIPS_L1_CACHE_SHIFT=5
81
82#
83# CPU selection
84#
85# CONFIG_CPU_MIPS32_R1 is not set
86# CONFIG_CPU_MIPS32_R2 is not set
87# CONFIG_CPU_MIPS64_R1 is not set
88# CONFIG_CPU_MIPS64_R2 is not set
89# CONFIG_CPU_R3000 is not set
90# CONFIG_CPU_TX39XX is not set
91# CONFIG_CPU_VR41XX is not set
92# CONFIG_CPU_R4300 is not set
93# CONFIG_CPU_R4X00 is not set
94# CONFIG_CPU_TX49XX is not set
95# CONFIG_CPU_R5000 is not set
96# CONFIG_CPU_R5432 is not set
97# CONFIG_CPU_R6000 is not set
98CONFIG_CPU_NEVADA=y
99# CONFIG_CPU_R8000 is not set
100# CONFIG_CPU_R10000 is not set
101# CONFIG_CPU_RM7000 is not set
102# CONFIG_CPU_RM9000 is not set
103# CONFIG_CPU_SB1 is not set
104CONFIG_SYS_HAS_CPU_R5432=y
105CONFIG_SYS_HAS_CPU_NEVADA=y
106CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
107CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
108CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
109CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
110
111#
112# Kernel type
113#
114CONFIG_32BIT=y
115# CONFIG_64BIT is not set
116CONFIG_PAGE_SIZE_4KB=y
117# CONFIG_PAGE_SIZE_8KB is not set
118# CONFIG_PAGE_SIZE_16KB is not set
119# CONFIG_PAGE_SIZE_64KB is not set
120CONFIG_MIPS_MT_DISABLED=y
121# CONFIG_MIPS_MT_SMTC is not set
122# CONFIG_MIPS_MT_SMP is not set
123# CONFIG_MIPS_VPE_LOADER is not set
124CONFIG_CPU_HAS_LLSC=y
125CONFIG_CPU_HAS_SYNC=y
126CONFIG_GENERIC_HARDIRQS=y
127CONFIG_GENERIC_IRQ_PROBE=y
128CONFIG_ARCH_FLATMEM_ENABLE=y
129CONFIG_SELECT_MEMORY_MODEL=y
130CONFIG_FLATMEM_MANUAL=y
131# CONFIG_DISCONTIGMEM_MANUAL is not set
132# CONFIG_SPARSEMEM_MANUAL is not set
133CONFIG_FLATMEM=y
134CONFIG_FLAT_NODE_MEM_MAP=y
135# CONFIG_SPARSEMEM_STATIC is not set
136CONFIG_SPLIT_PTLOCK_CPUS=4
137# CONFIG_RESOURCES_64BIT is not set
138# CONFIG_HZ_48 is not set
139# CONFIG_HZ_100 is not set
140# CONFIG_HZ_128 is not set
141# CONFIG_HZ_250 is not set
142# CONFIG_HZ_256 is not set
143CONFIG_HZ_1000=y
144# CONFIG_HZ_1024 is not set
145CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
146CONFIG_HZ=1000
147CONFIG_PREEMPT_NONE=y
148# CONFIG_PREEMPT_VOLUNTARY is not set
149# CONFIG_PREEMPT is not set
150CONFIG_LOCKDEP_SUPPORT=y
151CONFIG_STACKTRACE_SUPPORT=y
152CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
153
154#
155# Code maturity level options
156#
157CONFIG_EXPERIMENTAL=y
158CONFIG_BROKEN_ON_SMP=y
159CONFIG_INIT_ENV_ARG_LIMIT=32
160
161#
162# General setup
163#
164CONFIG_LOCALVERSION=""
165CONFIG_LOCALVERSION_AUTO=y
166CONFIG_SWAP=y
167CONFIG_SYSVIPC=y
168# CONFIG_POSIX_MQUEUE is not set
169CONFIG_BSD_PROCESS_ACCT=y
170# CONFIG_BSD_PROCESS_ACCT_V3 is not set
171CONFIG_SYSCTL=y
172# CONFIG_AUDIT is not set
173# CONFIG_IKCONFIG is not set
174CONFIG_RELAY=y
175CONFIG_INITRAMFS_SOURCE=""
176# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
177CONFIG_EMBEDDED=y
178CONFIG_KALLSYMS=y
179# CONFIG_KALLSYMS_EXTRA_PASS is not set
180# CONFIG_HOTPLUG is not set
181CONFIG_PRINTK=y
182CONFIG_BUG=y
183CONFIG_ELF_CORE=y
184CONFIG_BASE_FULL=y
185CONFIG_RT_MUTEXES=y
186CONFIG_FUTEX=y
187CONFIG_EPOLL=y
188CONFIG_SHMEM=y
189CONFIG_SLAB=y
190CONFIG_VM_EVENT_COUNTERS=y
191# CONFIG_TINY_SHMEM is not set
192CONFIG_BASE_SMALL=0
193# CONFIG_SLOB is not set
194
195#
196# Loadable module support
197#
198CONFIG_MODULES=y
199CONFIG_MODULE_UNLOAD=y
200# CONFIG_MODULE_FORCE_UNLOAD is not set
201CONFIG_MODVERSIONS=y
202CONFIG_MODULE_SRCVERSION_ALL=y
203CONFIG_KMOD=y
204
205#
206# Block layer
207#
208# CONFIG_LBD is not set
209# CONFIG_BLK_DEV_IO_TRACE is not set
210# CONFIG_LSF is not set
211
212#
213# IO Schedulers
214#
215CONFIG_IOSCHED_NOOP=y
216CONFIG_IOSCHED_AS=y
217CONFIG_IOSCHED_DEADLINE=y
218CONFIG_IOSCHED_CFQ=y
219CONFIG_DEFAULT_AS=y
220# CONFIG_DEFAULT_DEADLINE is not set
221# CONFIG_DEFAULT_CFQ is not set
222# CONFIG_DEFAULT_NOOP is not set
223CONFIG_DEFAULT_IOSCHED="anticipatory"
224
225#
226# Bus options (PCI, PCMCIA, EISA, ISA, TC)
227#
228CONFIG_HW_HAS_PCI=y
229# CONFIG_PCI is not set
230CONFIG_MMU=y
231
232#
233# PCCARD (PCMCIA/CardBus) support
234#
235# CONFIG_PCCARD is not set
236
237#
238# PCI Hotplug Support
239#
240
241#
242# Executable file formats
243#
244CONFIG_BINFMT_ELF=y
245# CONFIG_BINFMT_MISC is not set
246CONFIG_TRAD_SIGNALS=y
247
248#
249# Networking
250#
251CONFIG_NET=y
252
253#
254# Networking options
255#
256# CONFIG_NETDEBUG is not set
257CONFIG_PACKET=y
258CONFIG_PACKET_MMAP=y
259CONFIG_UNIX=y
260CONFIG_XFRM=y
261CONFIG_XFRM_USER=m
262CONFIG_NET_KEY=y
263CONFIG_INET=y
264# CONFIG_IP_MULTICAST is not set
265# CONFIG_IP_ADVANCED_ROUTER is not set
266CONFIG_IP_FIB_HASH=y
267CONFIG_IP_PNP=y
268# CONFIG_IP_PNP_DHCP is not set
269CONFIG_IP_PNP_BOOTP=y
270# CONFIG_IP_PNP_RARP is not set
271# CONFIG_NET_IPIP is not set
272# CONFIG_NET_IPGRE is not set
273# CONFIG_ARPD is not set
274# CONFIG_SYN_COOKIES is not set
275# CONFIG_INET_AH is not set
276# CONFIG_INET_ESP is not set
277# CONFIG_INET_IPCOMP is not set
278# CONFIG_INET_XFRM_TUNNEL is not set
279# CONFIG_INET_TUNNEL is not set
280CONFIG_INET_XFRM_MODE_TRANSPORT=m
281CONFIG_INET_XFRM_MODE_TUNNEL=m
282CONFIG_INET_DIAG=y
283CONFIG_INET_TCP_DIAG=y
284# CONFIG_TCP_CONG_ADVANCED is not set
285CONFIG_TCP_CONG_BIC=y
286# CONFIG_IPV6 is not set
287# CONFIG_INET6_XFRM_TUNNEL is not set
288# CONFIG_INET6_TUNNEL is not set
289CONFIG_NETWORK_SECMARK=y
290# CONFIG_NETFILTER is not set
291
292#
293# DCCP Configuration (EXPERIMENTAL)
294#
295# CONFIG_IP_DCCP is not set
296
297#
298# SCTP Configuration (EXPERIMENTAL)
299#
300# CONFIG_IP_SCTP is not set
301
302#
303# TIPC Configuration (EXPERIMENTAL)
304#
305# CONFIG_TIPC is not set
306# CONFIG_ATM is not set
307# CONFIG_BRIDGE is not set
308# CONFIG_VLAN_8021Q is not set
309# CONFIG_DECNET is not set
310# CONFIG_LLC2 is not set
311# CONFIG_IPX is not set
312# CONFIG_ATALK is not set
313# CONFIG_X25 is not set
314# CONFIG_LAPB is not set
315# CONFIG_NET_DIVERT is not set
316# CONFIG_ECONET is not set
317# CONFIG_WAN_ROUTER is not set
318
319#
320# QoS and/or fair queueing
321#
322# CONFIG_NET_SCHED is not set
323
324#
325# Network testing
326#
327# CONFIG_NET_PKTGEN is not set
328# CONFIG_HAMRADIO is not set
329# CONFIG_IRDA is not set
330# CONFIG_BT is not set
331CONFIG_IEEE80211=m
332# CONFIG_IEEE80211_DEBUG is not set
333CONFIG_IEEE80211_CRYPT_WEP=m
334CONFIG_IEEE80211_CRYPT_CCMP=m
335CONFIG_IEEE80211_SOFTMAC=m
336# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
337CONFIG_WIRELESS_EXT=y
338
339#
340# Device Drivers
341#
342
343#
344# Generic Driver Options
345#
346CONFIG_STANDALONE=y
347CONFIG_PREVENT_FIRMWARE_BUILD=y
348# CONFIG_FW_LOADER is not set
349# CONFIG_SYS_HYPERVISOR is not set
350
351#
352# Connector - unified userspace <-> kernelspace linker
353#
354CONFIG_CONNECTOR=m
355
356#
357# Memory Technology Devices (MTD)
358#
359CONFIG_MTD=y
360# CONFIG_MTD_DEBUG is not set
361# CONFIG_MTD_CONCAT is not set
362# CONFIG_MTD_PARTITIONS is not set
363
364#
365# User Modules And Translation Layers
366#
367CONFIG_MTD_CHAR=y
368# CONFIG_MTD_BLOCK is not set
369# CONFIG_MTD_BLOCK_RO is not set
370# CONFIG_FTL is not set
371# CONFIG_NFTL is not set
372# CONFIG_INFTL is not set
373# CONFIG_RFD_FTL is not set
374
375#
376# RAM/ROM/Flash chip drivers
377#
378CONFIG_MTD_CFI=y
379# CONFIG_MTD_JEDECPROBE is not set
380CONFIG_MTD_GEN_PROBE=y
381# CONFIG_MTD_CFI_ADV_OPTIONS is not set
382CONFIG_MTD_MAP_BANK_WIDTH_1=y
383CONFIG_MTD_MAP_BANK_WIDTH_2=y
384CONFIG_MTD_MAP_BANK_WIDTH_4=y
385# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
386# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
387# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
388CONFIG_MTD_CFI_I1=y
389CONFIG_MTD_CFI_I2=y
390# CONFIG_MTD_CFI_I4 is not set
391# CONFIG_MTD_CFI_I8 is not set
392CONFIG_MTD_CFI_INTELEXT=y
393# CONFIG_MTD_CFI_AMDSTD is not set
394# CONFIG_MTD_CFI_STAA is not set
395CONFIG_MTD_CFI_UTIL=y
396# CONFIG_MTD_RAM is not set
397# CONFIG_MTD_ROM is not set
398# CONFIG_MTD_ABSENT is not set
399# CONFIG_MTD_OBSOLETE_CHIPS is not set
400
401#
402# Mapping drivers for chip access
403#
404# CONFIG_MTD_COMPLEX_MAPPINGS is not set
405CONFIG_MTD_PHYSMAP=y
406CONFIG_MTD_PHYSMAP_START=0x8000000
407CONFIG_MTD_PHYSMAP_LEN=0x2000000
408CONFIG_MTD_PHYSMAP_BANKWIDTH=2
409# CONFIG_MTD_PLATRAM is not set
410
411#
412# Self-contained MTD device drivers
413#
414# CONFIG_MTD_SLRAM is not set
415# CONFIG_MTD_PHRAM is not set
416# CONFIG_MTD_MTDRAM is not set
417# CONFIG_MTD_BLOCK2MTD is not set
418
419#
420# Disk-On-Chip Device Drivers
421#
422# CONFIG_MTD_DOC2000 is not set
423# CONFIG_MTD_DOC2001 is not set
424# CONFIG_MTD_DOC2001PLUS is not set
425
426#
427# NAND Flash Device Drivers
428#
429# CONFIG_MTD_NAND is not set
430
431#
432# OneNAND Flash Device Drivers
433#
434# CONFIG_MTD_ONENAND is not set
435
436#
437# Parallel port support
438#
439# CONFIG_PARPORT is not set
440
441#
442# Plug and Play support
443#
444
445#
446# Block devices
447#
448# CONFIG_BLK_DEV_COW_COMMON is not set
449CONFIG_BLK_DEV_LOOP=y
450# CONFIG_BLK_DEV_CRYPTOLOOP is not set
451# CONFIG_BLK_DEV_NBD is not set
452# CONFIG_BLK_DEV_RAM is not set
453# CONFIG_BLK_DEV_INITRD is not set
454CONFIG_CDROM_PKTCDVD=m
455CONFIG_CDROM_PKTCDVD_BUFFERS=8
456# CONFIG_CDROM_PKTCDVD_WCACHE is not set
457CONFIG_ATA_OVER_ETH=m
458
459#
460# ATA/ATAPI/MFM/RLL support
461#
462CONFIG_IDE=y
463CONFIG_BLK_DEV_IDE=y
464
465#
466# Please see Documentation/ide.txt for help/info on IDE drives
467#
468# CONFIG_BLK_DEV_IDE_SATA is not set
469CONFIG_BLK_DEV_IDEDISK=y
470# CONFIG_IDEDISK_MULTI_MODE is not set
471# CONFIG_BLK_DEV_IDECD is not set
472# CONFIG_BLK_DEV_IDETAPE is not set
473# CONFIG_BLK_DEV_IDEFLOPPY is not set
474# CONFIG_IDE_TASK_IOCTL is not set
475
476#
477# IDE chipset support/bugfixes
478#
479CONFIG_IDE_GENERIC=y
480# CONFIG_IDE_ARM is not set
481# CONFIG_BLK_DEV_IDEDMA is not set
482# CONFIG_IDEDMA_AUTO is not set
483# CONFIG_BLK_DEV_HD is not set
484
485#
486# SCSI device support
487#
488CONFIG_RAID_ATTRS=m
489# CONFIG_SCSI is not set
490
491#
492# Multi-device support (RAID and LVM)
493#
494# CONFIG_MD is not set
495
496#
497# Fusion MPT device support
498#
499# CONFIG_FUSION is not set
500
501#
502# IEEE 1394 (FireWire) support
503#
504
505#
506# I2O device support
507#
508
509#
510# Network device support
511#
512CONFIG_NETDEVICES=y
513# CONFIG_DUMMY is not set
514# CONFIG_BONDING is not set
515# CONFIG_EQUALIZER is not set
516# CONFIG_TUN is not set
517
518#
519# PHY device support
520#
521CONFIG_PHYLIB=m
522
523#
524# MII PHY device drivers
525#
526CONFIG_MARVELL_PHY=m
527CONFIG_DAVICOM_PHY=m
528CONFIG_QSEMI_PHY=m
529CONFIG_LXT_PHY=m
530CONFIG_CICADA_PHY=m
531CONFIG_VITESSE_PHY=m
532CONFIG_SMSC_PHY=m
533
534#
535# Ethernet (10 or 100Mbit)
536#
537CONFIG_NET_ETHERNET=y
538# CONFIG_MII is not set
539# CONFIG_DM9000 is not set
540
541#
542# Ethernet (1000 Mbit)
543#
544
545#
546# Ethernet (10000 Mbit)
547#
548
549#
550# Token Ring devices
551#
552
553#
554# Wireless LAN (non-hamradio)
555#
556# CONFIG_NET_RADIO is not set
557
558#
559# Wan interfaces
560#
561# CONFIG_WAN is not set
562# CONFIG_PPP is not set
563# CONFIG_SLIP is not set
564# CONFIG_SHAPER is not set
565# CONFIG_NETCONSOLE is not set
566# CONFIG_NETPOLL is not set
567# CONFIG_NET_POLL_CONTROLLER is not set
568
569#
570# ISDN subsystem
571#
572# CONFIG_ISDN is not set
573
574#
575# Telephony Support
576#
577# CONFIG_PHONE is not set
578
579#
580# Input device support
581#
582CONFIG_INPUT=y
583
584#
585# Userland interfaces
586#
587CONFIG_INPUT_MOUSEDEV=y
588CONFIG_INPUT_MOUSEDEV_PSAUX=y
589CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
590CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
591# CONFIG_INPUT_JOYDEV is not set
592# CONFIG_INPUT_TSDEV is not set
593# CONFIG_INPUT_EVDEV is not set
594# CONFIG_INPUT_EVBUG is not set
595
596#
597# Input Device Drivers
598#
599# CONFIG_INPUT_KEYBOARD is not set
600# CONFIG_INPUT_MOUSE is not set
601# CONFIG_INPUT_JOYSTICK is not set
602# CONFIG_INPUT_TOUCHSCREEN is not set
603# CONFIG_INPUT_MISC is not set
604
605#
606# Hardware I/O ports
607#
608CONFIG_SERIO=y
609# CONFIG_SERIO_I8042 is not set
610CONFIG_SERIO_SERPORT=y
611# CONFIG_SERIO_LIBPS2 is not set
612CONFIG_SERIO_RAW=m
613# CONFIG_GAMEPORT is not set
614
615#
616# Character devices
617#
618CONFIG_VT=y
619CONFIG_VT_CONSOLE=y
620CONFIG_HW_CONSOLE=y
621CONFIG_VT_HW_CONSOLE_BINDING=y
622# CONFIG_SERIAL_NONSTANDARD is not set
623# CONFIG_QTRONIX_KEYBOARD is not set
624# CONFIG_IT8172_SCR0 is not set
625# CONFIG_IT8172_SCR1 is not set
626# CONFIG_ITE_GPIO is not set
627
628#
629# Serial drivers
630#
631CONFIG_SERIAL_8250=y
632CONFIG_SERIAL_8250_CONSOLE=y
633CONFIG_SERIAL_8250_NR_UARTS=4
634CONFIG_SERIAL_8250_RUNTIME_UARTS=4
635# CONFIG_SERIAL_8250_EXTENDED is not set
636
637#
638# Non-8250 serial port support
639#
640CONFIG_SERIAL_CORE=y
641CONFIG_SERIAL_CORE_CONSOLE=y
642CONFIG_UNIX98_PTYS=y
643CONFIG_LEGACY_PTYS=y
644CONFIG_LEGACY_PTY_COUNT=256
645
646#
647# IPMI
648#
649# CONFIG_IPMI_HANDLER is not set
650
651#
652# Watchdog Cards
653#
654# CONFIG_WATCHDOG is not set
655# CONFIG_HW_RANDOM is not set
656# CONFIG_RTC is not set
657# CONFIG_GEN_RTC is not set
658# CONFIG_DTLK is not set
659# CONFIG_R3964 is not set
660
661#
662# Ftape, the floppy tape device driver
663#
664# CONFIG_RAW_DRIVER is not set
665
666#
667# TPM devices
668#
669# CONFIG_TCG_TPM is not set
670# CONFIG_TELCLOCK is not set
671
672#
673# I2C support
674#
675# CONFIG_I2C is not set
676
677#
678# SPI support
679#
680# CONFIG_SPI is not set
681# CONFIG_SPI_MASTER is not set
682
683#
684# Dallas's 1-wire bus
685#
686# CONFIG_W1 is not set
687
688#
689# Hardware Monitoring support
690#
691# CONFIG_HWMON is not set
692# CONFIG_HWMON_VID is not set
693
694#
695# Misc devices
696#
697
698#
699# Multimedia devices
700#
701# CONFIG_VIDEO_DEV is not set
702CONFIG_VIDEO_V4L2=y
703
704#
705# Digital Video Broadcasting Devices
706#
707# CONFIG_DVB is not set
708
709#
710# Graphics support
711#
712# CONFIG_FIRMWARE_EDID is not set
713# CONFIG_FB is not set
714
715#
716# Console display driver support
717#
718# CONFIG_VGA_CONSOLE is not set
719CONFIG_DUMMY_CONSOLE=y
720
721#
722# Sound
723#
724CONFIG_SOUND=y
725
726#
727# Advanced Linux Sound Architecture
728#
729# CONFIG_SND is not set
730
731#
732# Open Sound System
733#
734CONFIG_SOUND_PRIME=y
735CONFIG_SOUND_IT8172=y
736# CONFIG_SOUND_MSNDCLAS is not set
737# CONFIG_SOUND_MSNDPIN is not set
738
739#
740# USB support
741#
742# CONFIG_USB_ARCH_HAS_HCD is not set
743# CONFIG_USB_ARCH_HAS_OHCI is not set
744# CONFIG_USB_ARCH_HAS_EHCI is not set
745
746#
747# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
748#
749
750#
751# USB Gadget Support
752#
753# CONFIG_USB_GADGET is not set
754
755#
756# MMC/SD Card support
757#
758# CONFIG_MMC is not set
759
760#
761# LED devices
762#
763# CONFIG_NEW_LEDS is not set
764
765#
766# LED drivers
767#
768
769#
770# LED Triggers
771#
772
773#
774# InfiniBand support
775#
776
777#
778# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
779#
780
781#
782# Real Time Clock
783#
784# CONFIG_RTC_CLASS is not set
785
786#
787# DMA Engine support
788#
789# CONFIG_DMA_ENGINE is not set
790
791#
792# DMA Clients
793#
794
795#
796# DMA Devices
797#
798
799#
800# File systems
801#
802CONFIG_EXT2_FS=y
803# CONFIG_EXT2_FS_XATTR is not set
804# CONFIG_EXT2_FS_XIP is not set
805# CONFIG_EXT3_FS is not set
806# CONFIG_REISERFS_FS is not set
807# CONFIG_JFS_FS is not set
808# CONFIG_FS_POSIX_ACL is not set
809# CONFIG_XFS_FS is not set
810# CONFIG_OCFS2_FS is not set
811# CONFIG_MINIX_FS is not set
812# CONFIG_ROMFS_FS is not set
813CONFIG_INOTIFY=y
814CONFIG_INOTIFY_USER=y
815# CONFIG_QUOTA is not set
816CONFIG_DNOTIFY=y
817# CONFIG_AUTOFS_FS is not set
818# CONFIG_AUTOFS4_FS is not set
819CONFIG_FUSE_FS=m
820
821#
822# CD-ROM/DVD Filesystems
823#
824# CONFIG_ISO9660_FS is not set
825# CONFIG_UDF_FS is not set
826
827#
828# DOS/FAT/NT Filesystems
829#
830# CONFIG_MSDOS_FS is not set
831# CONFIG_VFAT_FS is not set
832# CONFIG_NTFS_FS is not set
833
834#
835# Pseudo filesystems
836#
837CONFIG_PROC_FS=y
838CONFIG_PROC_KCORE=y
839CONFIG_SYSFS=y
840# CONFIG_TMPFS is not set
841# CONFIG_HUGETLB_PAGE is not set
842CONFIG_RAMFS=y
843# CONFIG_CONFIGFS_FS is not set
844
845#
846# Miscellaneous filesystems
847#
848# CONFIG_ADFS_FS is not set
849# CONFIG_AFFS_FS is not set
850# CONFIG_HFS_FS is not set
851# CONFIG_HFSPLUS_FS is not set
852# CONFIG_BEFS_FS is not set
853# CONFIG_BFS_FS is not set
854# CONFIG_EFS_FS is not set
855# CONFIG_JFFS_FS is not set
856# CONFIG_JFFS2_FS is not set
857# CONFIG_CRAMFS is not set
858# CONFIG_VXFS_FS is not set
859# CONFIG_HPFS_FS is not set
860# CONFIG_QNX4FS_FS is not set
861# CONFIG_SYSV_FS is not set
862# CONFIG_UFS_FS is not set
863
864#
865# Network File Systems
866#
867CONFIG_NFS_FS=y
868# CONFIG_NFS_V3 is not set
869# CONFIG_NFS_V4 is not set
870# CONFIG_NFS_DIRECTIO is not set
871# CONFIG_NFSD is not set
872CONFIG_ROOT_NFS=y
873CONFIG_LOCKD=y
874CONFIG_NFS_COMMON=y
875CONFIG_SUNRPC=y
876# CONFIG_RPCSEC_GSS_KRB5 is not set
877# CONFIG_RPCSEC_GSS_SPKM3 is not set
878# CONFIG_SMB_FS is not set
879# CONFIG_CIFS is not set
880# CONFIG_CIFS_DEBUG2 is not set
881# CONFIG_NCP_FS is not set
882# CONFIG_CODA_FS is not set
883# CONFIG_AFS_FS is not set
884# CONFIG_9P_FS is not set
885
886#
887# Partition Types
888#
889# CONFIG_PARTITION_ADVANCED is not set
890CONFIG_MSDOS_PARTITION=y
891
892#
893# Native Language Support
894#
895# CONFIG_NLS is not set
896
897#
898# Profiling support
899#
900# CONFIG_PROFILING is not set
901
902#
903# Kernel hacking
904#
905CONFIG_TRACE_IRQFLAGS_SUPPORT=y
906# CONFIG_PRINTK_TIME is not set
907# CONFIG_MAGIC_SYSRQ is not set
908# CONFIG_UNUSED_SYMBOLS is not set
909# CONFIG_DEBUG_KERNEL is not set
910CONFIG_LOG_BUF_SHIFT=14
911# CONFIG_DEBUG_FS is not set
912CONFIG_CROSSCOMPILE=y
913CONFIG_CMDLINE=""
914
915#
916# Security options
917#
918CONFIG_KEYS=y
919CONFIG_KEYS_DEBUG_PROC_KEYS=y
920# CONFIG_SECURITY is not set
921
922#
923# Cryptographic options
924#
925CONFIG_CRYPTO=y
926CONFIG_CRYPTO_HMAC=y
927CONFIG_CRYPTO_NULL=m
928CONFIG_CRYPTO_MD4=m
929CONFIG_CRYPTO_MD5=m
930CONFIG_CRYPTO_SHA1=m
931CONFIG_CRYPTO_SHA256=m
932CONFIG_CRYPTO_SHA512=m
933CONFIG_CRYPTO_WP512=m
934CONFIG_CRYPTO_TGR192=m
935CONFIG_CRYPTO_DES=m
936CONFIG_CRYPTO_BLOWFISH=m
937CONFIG_CRYPTO_TWOFISH=m
938CONFIG_CRYPTO_SERPENT=m
939CONFIG_CRYPTO_AES=m
940CONFIG_CRYPTO_CAST5=m
941CONFIG_CRYPTO_CAST6=m
942CONFIG_CRYPTO_TEA=m
943CONFIG_CRYPTO_ARC4=m
944CONFIG_CRYPTO_KHAZAD=m
945CONFIG_CRYPTO_ANUBIS=m
946CONFIG_CRYPTO_DEFLATE=m
947CONFIG_CRYPTO_MICHAEL_MIC=m
948CONFIG_CRYPTO_CRC32C=m
949# CONFIG_CRYPTO_TEST is not set
950
951#
952# Hardware crypto devices
953#
954
955#
956# Library routines
957#
958# CONFIG_CRC_CCITT is not set
959CONFIG_CRC16=m
960CONFIG_CRC32=m
961CONFIG_LIBCRC32C=m
962CONFIG_ZLIB_INFLATE=m
963CONFIG_ZLIB_DEFLATE=m
964CONFIG_PLIST=y
diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig
deleted file mode 100644
index 99831d0bf76b..000000000000
--- a/arch/mips/configs/ivr_defconfig
+++ /dev/null
@@ -1,920 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.18-rc1
4# Thu Jul 6 10:04:12 2006
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MIPS_MTX1 is not set
12# CONFIG_MIPS_BOSPORUS is not set
13# CONFIG_MIPS_PB1000 is not set
14# CONFIG_MIPS_PB1100 is not set
15# CONFIG_MIPS_PB1500 is not set
16# CONFIG_MIPS_PB1550 is not set
17# CONFIG_MIPS_PB1200 is not set
18# CONFIG_MIPS_DB1000 is not set
19# CONFIG_MIPS_DB1100 is not set
20# CONFIG_MIPS_DB1500 is not set
21# CONFIG_MIPS_DB1550 is not set
22# CONFIG_MIPS_DB1200 is not set
23# CONFIG_MIPS_MIRAGE is not set
24# CONFIG_BASLER_EXCITE is not set
25# CONFIG_MIPS_COBALT is not set
26# CONFIG_MACH_DECSTATION is not set
27# CONFIG_MIPS_EV64120 is not set
28CONFIG_MIPS_IVR=y
29# CONFIG_MIPS_ITE8172 is not set
30# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set
35# CONFIG_WR_PPMC is not set
36# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_V2PCI is not set
44# CONFIG_PNX8550_JBS is not set
45# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set
48# CONFIG_QEMU is not set
49# CONFIG_MARKEINS is not set
50# CONFIG_SGI_IP22 is not set
51# CONFIG_SGI_IP27 is not set
52# CONFIG_SGI_IP32 is not set
53# CONFIG_SIBYTE_BIGSUR is not set
54# CONFIG_SIBYTE_SWARM is not set
55# CONFIG_SIBYTE_SENTOSA is not set
56# CONFIG_SIBYTE_RHONE is not set
57# CONFIG_SIBYTE_CARMEL is not set
58# CONFIG_SIBYTE_PTSWARM is not set
59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set
63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set
66CONFIG_RWSEM_GENERIC_SPINLOCK=y
67CONFIG_GENERIC_FIND_NEXT_BIT=y
68CONFIG_GENERIC_HWEIGHT=y
69CONFIG_GENERIC_CALIBRATE_DELAY=y
70CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
71CONFIG_DMA_NONCOHERENT=y
72CONFIG_DMA_NEED_PCI_MAP_STATE=y
73# CONFIG_CPU_BIG_ENDIAN is not set
74CONFIG_CPU_LITTLE_ENDIAN=y
75CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
76CONFIG_ITE_BOARD_GEN=y
77CONFIG_IT8172_CIR=y
78CONFIG_MIPS_L1_CACHE_SHIFT=5
79
80#
81# CPU selection
82#
83# CONFIG_CPU_MIPS32_R1 is not set
84# CONFIG_CPU_MIPS32_R2 is not set
85# CONFIG_CPU_MIPS64_R1 is not set
86# CONFIG_CPU_MIPS64_R2 is not set
87# CONFIG_CPU_R3000 is not set
88# CONFIG_CPU_TX39XX is not set
89# CONFIG_CPU_VR41XX is not set
90# CONFIG_CPU_R4300 is not set
91# CONFIG_CPU_R4X00 is not set
92# CONFIG_CPU_TX49XX is not set
93# CONFIG_CPU_R5000 is not set
94# CONFIG_CPU_R5432 is not set
95# CONFIG_CPU_R6000 is not set
96CONFIG_CPU_NEVADA=y
97# CONFIG_CPU_R8000 is not set
98# CONFIG_CPU_R10000 is not set
99# CONFIG_CPU_RM7000 is not set
100# CONFIG_CPU_RM9000 is not set
101# CONFIG_CPU_SB1 is not set
102CONFIG_SYS_HAS_CPU_NEVADA=y
103CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
104CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
105CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
106CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
107
108#
109# Kernel type
110#
111CONFIG_32BIT=y
112# CONFIG_64BIT is not set
113CONFIG_PAGE_SIZE_4KB=y
114# CONFIG_PAGE_SIZE_8KB is not set
115# CONFIG_PAGE_SIZE_16KB is not set
116# CONFIG_PAGE_SIZE_64KB is not set
117CONFIG_MIPS_MT_DISABLED=y
118# CONFIG_MIPS_MT_SMTC is not set
119# CONFIG_MIPS_MT_SMP is not set
120# CONFIG_MIPS_VPE_LOADER is not set
121CONFIG_CPU_HAS_LLSC=y
122CONFIG_CPU_HAS_SYNC=y
123CONFIG_GENERIC_HARDIRQS=y
124CONFIG_GENERIC_IRQ_PROBE=y
125CONFIG_ARCH_FLATMEM_ENABLE=y
126CONFIG_SELECT_MEMORY_MODEL=y
127CONFIG_FLATMEM_MANUAL=y
128# CONFIG_DISCONTIGMEM_MANUAL is not set
129# CONFIG_SPARSEMEM_MANUAL is not set
130CONFIG_FLATMEM=y
131CONFIG_FLAT_NODE_MEM_MAP=y
132# CONFIG_SPARSEMEM_STATIC is not set
133CONFIG_SPLIT_PTLOCK_CPUS=4
134# CONFIG_RESOURCES_64BIT is not set
135# CONFIG_HZ_48 is not set
136# CONFIG_HZ_100 is not set
137# CONFIG_HZ_128 is not set
138# CONFIG_HZ_250 is not set
139# CONFIG_HZ_256 is not set
140CONFIG_HZ_1000=y
141# CONFIG_HZ_1024 is not set
142CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
143CONFIG_HZ=1000
144CONFIG_PREEMPT_NONE=y
145# CONFIG_PREEMPT_VOLUNTARY is not set
146# CONFIG_PREEMPT is not set
147CONFIG_LOCKDEP_SUPPORT=y
148CONFIG_STACKTRACE_SUPPORT=y
149CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
150
151#
152# Code maturity level options
153#
154CONFIG_EXPERIMENTAL=y
155CONFIG_BROKEN_ON_SMP=y
156CONFIG_INIT_ENV_ARG_LIMIT=32
157
158#
159# General setup
160#
161CONFIG_LOCALVERSION=""
162CONFIG_LOCALVERSION_AUTO=y
163CONFIG_SWAP=y
164CONFIG_SYSVIPC=y
165# CONFIG_POSIX_MQUEUE is not set
166CONFIG_BSD_PROCESS_ACCT=y
167# CONFIG_BSD_PROCESS_ACCT_V3 is not set
168CONFIG_SYSCTL=y
169# CONFIG_AUDIT is not set
170# CONFIG_IKCONFIG is not set
171CONFIG_RELAY=y
172CONFIG_INITRAMFS_SOURCE=""
173# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
174CONFIG_EMBEDDED=y
175CONFIG_KALLSYMS=y
176# CONFIG_KALLSYMS_EXTRA_PASS is not set
177CONFIG_HOTPLUG=y
178CONFIG_PRINTK=y
179CONFIG_BUG=y
180CONFIG_ELF_CORE=y
181CONFIG_BASE_FULL=y
182CONFIG_RT_MUTEXES=y
183CONFIG_FUTEX=y
184CONFIG_EPOLL=y
185CONFIG_SHMEM=y
186CONFIG_SLAB=y
187CONFIG_VM_EVENT_COUNTERS=y
188# CONFIG_TINY_SHMEM is not set
189CONFIG_BASE_SMALL=0
190# CONFIG_SLOB is not set
191
192#
193# Loadable module support
194#
195CONFIG_MODULES=y
196CONFIG_MODULE_UNLOAD=y
197# CONFIG_MODULE_FORCE_UNLOAD is not set
198CONFIG_MODVERSIONS=y
199CONFIG_MODULE_SRCVERSION_ALL=y
200CONFIG_KMOD=y
201
202#
203# Block layer
204#
205# CONFIG_LBD is not set
206# CONFIG_BLK_DEV_IO_TRACE is not set
207# CONFIG_LSF is not set
208
209#
210# IO Schedulers
211#
212CONFIG_IOSCHED_NOOP=y
213CONFIG_IOSCHED_AS=y
214CONFIG_IOSCHED_DEADLINE=y
215CONFIG_IOSCHED_CFQ=y
216CONFIG_DEFAULT_AS=y
217# CONFIG_DEFAULT_DEADLINE is not set
218# CONFIG_DEFAULT_CFQ is not set
219# CONFIG_DEFAULT_NOOP is not set
220CONFIG_DEFAULT_IOSCHED="anticipatory"
221
222#
223# Bus options (PCI, PCMCIA, EISA, ISA, TC)
224#
225CONFIG_HW_HAS_PCI=y
226CONFIG_PCI=y
227CONFIG_MMU=y
228
229#
230# PCCARD (PCMCIA/CardBus) support
231#
232# CONFIG_PCCARD is not set
233
234#
235# PCI Hotplug Support
236#
237# CONFIG_HOTPLUG_PCI is not set
238
239#
240# Executable file formats
241#
242CONFIG_BINFMT_ELF=y
243# CONFIG_BINFMT_MISC is not set
244CONFIG_TRAD_SIGNALS=y
245
246#
247# Networking
248#
249CONFIG_NET=y
250
251#
252# Networking options
253#
254# CONFIG_NETDEBUG is not set
255CONFIG_PACKET=y
256CONFIG_PACKET_MMAP=y
257CONFIG_UNIX=y
258CONFIG_XFRM=y
259CONFIG_XFRM_USER=m
260CONFIG_NET_KEY=y
261CONFIG_INET=y
262# CONFIG_IP_MULTICAST is not set
263# CONFIG_IP_ADVANCED_ROUTER is not set
264CONFIG_IP_FIB_HASH=y
265CONFIG_IP_PNP=y
266# CONFIG_IP_PNP_DHCP is not set
267CONFIG_IP_PNP_BOOTP=y
268# CONFIG_IP_PNP_RARP is not set
269# CONFIG_NET_IPIP is not set
270# CONFIG_NET_IPGRE is not set
271# CONFIG_ARPD is not set
272# CONFIG_SYN_COOKIES is not set
273# CONFIG_INET_AH is not set
274# CONFIG_INET_ESP is not set
275# CONFIG_INET_IPCOMP is not set
276# CONFIG_INET_XFRM_TUNNEL is not set
277# CONFIG_INET_TUNNEL is not set
278CONFIG_INET_XFRM_MODE_TRANSPORT=m
279CONFIG_INET_XFRM_MODE_TUNNEL=m
280CONFIG_INET_DIAG=y
281CONFIG_INET_TCP_DIAG=y
282# CONFIG_TCP_CONG_ADVANCED is not set
283CONFIG_TCP_CONG_BIC=y
284# CONFIG_IPV6 is not set
285# CONFIG_INET6_XFRM_TUNNEL is not set
286# CONFIG_INET6_TUNNEL is not set
287CONFIG_NETWORK_SECMARK=y
288# CONFIG_NETFILTER is not set
289
290#
291# DCCP Configuration (EXPERIMENTAL)
292#
293# CONFIG_IP_DCCP is not set
294
295#
296# SCTP Configuration (EXPERIMENTAL)
297#
298# CONFIG_IP_SCTP is not set
299
300#
301# TIPC Configuration (EXPERIMENTAL)
302#
303# CONFIG_TIPC is not set
304# CONFIG_ATM is not set
305# CONFIG_BRIDGE is not set
306# CONFIG_VLAN_8021Q is not set
307# CONFIG_DECNET is not set
308# CONFIG_LLC2 is not set
309# CONFIG_IPX is not set
310# CONFIG_ATALK is not set
311# CONFIG_X25 is not set
312# CONFIG_LAPB is not set
313# CONFIG_NET_DIVERT is not set
314# CONFIG_ECONET is not set
315# CONFIG_WAN_ROUTER is not set
316
317#
318# QoS and/or fair queueing
319#
320# CONFIG_NET_SCHED is not set
321
322#
323# Network testing
324#
325# CONFIG_NET_PKTGEN is not set
326# CONFIG_HAMRADIO is not set
327# CONFIG_IRDA is not set
328# CONFIG_BT is not set
329CONFIG_IEEE80211=m
330# CONFIG_IEEE80211_DEBUG is not set
331CONFIG_IEEE80211_CRYPT_WEP=m
332CONFIG_IEEE80211_CRYPT_CCMP=m
333CONFIG_IEEE80211_SOFTMAC=m
334# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
335CONFIG_WIRELESS_EXT=y
336
337#
338# Device Drivers
339#
340
341#
342# Generic Driver Options
343#
344CONFIG_STANDALONE=y
345CONFIG_PREVENT_FIRMWARE_BUILD=y
346CONFIG_FW_LOADER=m
347# CONFIG_SYS_HYPERVISOR is not set
348
349#
350# Connector - unified userspace <-> kernelspace linker
351#
352CONFIG_CONNECTOR=m
353
354#
355# Memory Technology Devices (MTD)
356#
357# CONFIG_MTD is not set
358
359#
360# Parallel port support
361#
362# CONFIG_PARPORT is not set
363
364#
365# Plug and Play support
366#
367
368#
369# Block devices
370#
371# CONFIG_BLK_CPQ_DA is not set
372# CONFIG_BLK_CPQ_CISS_DA is not set
373# CONFIG_BLK_DEV_DAC960 is not set
374# CONFIG_BLK_DEV_UMEM is not set
375# CONFIG_BLK_DEV_COW_COMMON is not set
376# CONFIG_BLK_DEV_LOOP is not set
377# CONFIG_BLK_DEV_NBD is not set
378# CONFIG_BLK_DEV_SX8 is not set
379# CONFIG_BLK_DEV_RAM is not set
380# CONFIG_BLK_DEV_INITRD is not set
381CONFIG_CDROM_PKTCDVD=m
382CONFIG_CDROM_PKTCDVD_BUFFERS=8
383# CONFIG_CDROM_PKTCDVD_WCACHE is not set
384CONFIG_ATA_OVER_ETH=m
385
386#
387# ATA/ATAPI/MFM/RLL support
388#
389CONFIG_IDE=y
390CONFIG_BLK_DEV_IDE=y
391
392#
393# Please see Documentation/ide.txt for help/info on IDE drives
394#
395# CONFIG_BLK_DEV_IDE_SATA is not set
396CONFIG_BLK_DEV_IDEDISK=y
397# CONFIG_IDEDISK_MULTI_MODE is not set
398# CONFIG_BLK_DEV_IDECD is not set
399# CONFIG_BLK_DEV_IDETAPE is not set
400# CONFIG_BLK_DEV_IDEFLOPPY is not set
401# CONFIG_IDE_TASK_IOCTL is not set
402
403#
404# IDE chipset support/bugfixes
405#
406CONFIG_IDE_GENERIC=y
407# CONFIG_BLK_DEV_IDEPCI is not set
408# CONFIG_IDE_ARM is not set
409# CONFIG_BLK_DEV_IDEDMA is not set
410# CONFIG_IDEDMA_AUTO is not set
411# CONFIG_BLK_DEV_HD is not set
412
413#
414# SCSI device support
415#
416CONFIG_RAID_ATTRS=m
417# CONFIG_SCSI is not set
418
419#
420# Multi-device support (RAID and LVM)
421#
422# CONFIG_MD is not set
423
424#
425# Fusion MPT device support
426#
427# CONFIG_FUSION is not set
428
429#
430# IEEE 1394 (FireWire) support
431#
432# CONFIG_IEEE1394 is not set
433
434#
435# I2O device support
436#
437# CONFIG_I2O is not set
438
439#
440# Network device support
441#
442CONFIG_NETDEVICES=y
443# CONFIG_DUMMY is not set
444# CONFIG_BONDING is not set
445# CONFIG_EQUALIZER is not set
446# CONFIG_TUN is not set
447
448#
449# ARCnet devices
450#
451# CONFIG_ARCNET is not set
452
453#
454# PHY device support
455#
456CONFIG_PHYLIB=m
457
458#
459# MII PHY device drivers
460#
461CONFIG_MARVELL_PHY=m
462CONFIG_DAVICOM_PHY=m
463CONFIG_QSEMI_PHY=m
464CONFIG_LXT_PHY=m
465CONFIG_CICADA_PHY=m
466CONFIG_VITESSE_PHY=m
467CONFIG_SMSC_PHY=m
468
469#
470# Ethernet (10 or 100Mbit)
471#
472CONFIG_NET_ETHERNET=y
473# CONFIG_MII is not set
474# CONFIG_HAPPYMEAL is not set
475# CONFIG_SUNGEM is not set
476# CONFIG_CASSINI is not set
477# CONFIG_NET_VENDOR_3COM is not set
478# CONFIG_DM9000 is not set
479
480#
481# Tulip family network device support
482#
483# CONFIG_NET_TULIP is not set
484# CONFIG_HP100 is not set
485# CONFIG_NET_PCI is not set
486
487#
488# Ethernet (1000 Mbit)
489#
490# CONFIG_ACENIC is not set
491# CONFIG_DL2K is not set
492# CONFIG_E1000 is not set
493# CONFIG_NS83820 is not set
494# CONFIG_HAMACHI is not set
495# CONFIG_YELLOWFIN is not set
496# CONFIG_R8169 is not set
497# CONFIG_SIS190 is not set
498# CONFIG_SKGE is not set
499# CONFIG_SKY2 is not set
500# CONFIG_SK98LIN is not set
501# CONFIG_TIGON3 is not set
502# CONFIG_BNX2 is not set
503
504#
505# Ethernet (10000 Mbit)
506#
507# CONFIG_CHELSIO_T1 is not set
508# CONFIG_IXGB is not set
509# CONFIG_S2IO is not set
510# CONFIG_MYRI10GE is not set
511
512#
513# Token Ring devices
514#
515# CONFIG_TR is not set
516
517#
518# Wireless LAN (non-hamradio)
519#
520# CONFIG_NET_RADIO is not set
521
522#
523# Wan interfaces
524#
525# CONFIG_WAN is not set
526# CONFIG_FDDI is not set
527# CONFIG_HIPPI is not set
528# CONFIG_PPP is not set
529# CONFIG_SLIP is not set
530# CONFIG_SHAPER is not set
531# CONFIG_NETCONSOLE is not set
532# CONFIG_NETPOLL is not set
533# CONFIG_NET_POLL_CONTROLLER is not set
534
535#
536# ISDN subsystem
537#
538# CONFIG_ISDN is not set
539
540#
541# Telephony Support
542#
543# CONFIG_PHONE is not set
544
545#
546# Input device support
547#
548CONFIG_INPUT=y
549
550#
551# Userland interfaces
552#
553CONFIG_INPUT_MOUSEDEV=y
554CONFIG_INPUT_MOUSEDEV_PSAUX=y
555CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
556CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
557# CONFIG_INPUT_JOYDEV is not set
558# CONFIG_INPUT_TSDEV is not set
559# CONFIG_INPUT_EVDEV is not set
560# CONFIG_INPUT_EVBUG is not set
561
562#
563# Input Device Drivers
564#
565# CONFIG_INPUT_KEYBOARD is not set
566# CONFIG_INPUT_MOUSE is not set
567# CONFIG_INPUT_JOYSTICK is not set
568# CONFIG_INPUT_TOUCHSCREEN is not set
569# CONFIG_INPUT_MISC is not set
570
571#
572# Hardware I/O ports
573#
574CONFIG_SERIO=y
575# CONFIG_SERIO_I8042 is not set
576CONFIG_SERIO_SERPORT=y
577# CONFIG_SERIO_PCIPS2 is not set
578# CONFIG_SERIO_LIBPS2 is not set
579CONFIG_SERIO_RAW=m
580# CONFIG_GAMEPORT is not set
581
582#
583# Character devices
584#
585CONFIG_VT=y
586CONFIG_VT_CONSOLE=y
587CONFIG_HW_CONSOLE=y
588CONFIG_VT_HW_CONSOLE_BINDING=y
589# CONFIG_SERIAL_NONSTANDARD is not set
590CONFIG_QTRONIX_KEYBOARD=y
591CONFIG_IT8172_SCR0=y
592CONFIG_IT8172_SCR1=y
593
594#
595# Serial drivers
596#
597CONFIG_SERIAL_8250=y
598CONFIG_SERIAL_8250_CONSOLE=y
599CONFIG_SERIAL_8250_PCI=y
600CONFIG_SERIAL_8250_NR_UARTS=4
601CONFIG_SERIAL_8250_RUNTIME_UARTS=4
602# CONFIG_SERIAL_8250_EXTENDED is not set
603
604#
605# Non-8250 serial port support
606#
607CONFIG_SERIAL_CORE=y
608CONFIG_SERIAL_CORE_CONSOLE=y
609# CONFIG_SERIAL_JSM is not set
610CONFIG_UNIX98_PTYS=y
611CONFIG_LEGACY_PTYS=y
612CONFIG_LEGACY_PTY_COUNT=256
613
614#
615# IPMI
616#
617# CONFIG_IPMI_HANDLER is not set
618
619#
620# Watchdog Cards
621#
622# CONFIG_WATCHDOG is not set
623# CONFIG_HW_RANDOM is not set
624CONFIG_RTC=y
625# CONFIG_DTLK is not set
626# CONFIG_R3964 is not set
627# CONFIG_APPLICOM is not set
628
629#
630# Ftape, the floppy tape device driver
631#
632# CONFIG_DRM is not set
633# CONFIG_RAW_DRIVER is not set
634
635#
636# TPM devices
637#
638# CONFIG_TCG_TPM is not set
639# CONFIG_TELCLOCK is not set
640
641#
642# I2C support
643#
644# CONFIG_I2C is not set
645
646#
647# SPI support
648#
649# CONFIG_SPI is not set
650# CONFIG_SPI_MASTER is not set
651
652#
653# Dallas's 1-wire bus
654#
655# CONFIG_W1 is not set
656
657#
658# Hardware Monitoring support
659#
660# CONFIG_HWMON is not set
661# CONFIG_HWMON_VID is not set
662
663#
664# Misc devices
665#
666
667#
668# Multimedia devices
669#
670# CONFIG_VIDEO_DEV is not set
671CONFIG_VIDEO_V4L2=y
672
673#
674# Digital Video Broadcasting Devices
675#
676# CONFIG_DVB is not set
677
678#
679# Graphics support
680#
681# CONFIG_FIRMWARE_EDID is not set
682# CONFIG_FB is not set
683
684#
685# Console display driver support
686#
687# CONFIG_VGA_CONSOLE is not set
688CONFIG_DUMMY_CONSOLE=y
689
690#
691# Sound
692#
693# CONFIG_SOUND is not set
694
695#
696# USB support
697#
698CONFIG_USB_ARCH_HAS_HCD=y
699CONFIG_USB_ARCH_HAS_OHCI=y
700CONFIG_USB_ARCH_HAS_EHCI=y
701# CONFIG_USB is not set
702
703#
704# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
705#
706
707#
708# USB Gadget Support
709#
710# CONFIG_USB_GADGET is not set
711
712#
713# MMC/SD Card support
714#
715# CONFIG_MMC is not set
716
717#
718# LED devices
719#
720# CONFIG_NEW_LEDS is not set
721
722#
723# LED drivers
724#
725
726#
727# LED Triggers
728#
729
730#
731# InfiniBand support
732#
733# CONFIG_INFINIBAND is not set
734
735#
736# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
737#
738
739#
740# Real Time Clock
741#
742# CONFIG_RTC_CLASS is not set
743
744#
745# DMA Engine support
746#
747# CONFIG_DMA_ENGINE is not set
748
749#
750# DMA Clients
751#
752
753#
754# DMA Devices
755#
756
757#
758# File systems
759#
760CONFIG_EXT2_FS=y
761# CONFIG_EXT2_FS_XATTR is not set
762# CONFIG_EXT2_FS_XIP is not set
763# CONFIG_EXT3_FS is not set
764# CONFIG_REISERFS_FS is not set
765# CONFIG_JFS_FS is not set
766# CONFIG_FS_POSIX_ACL is not set
767# CONFIG_XFS_FS is not set
768# CONFIG_OCFS2_FS is not set
769# CONFIG_MINIX_FS is not set
770# CONFIG_ROMFS_FS is not set
771CONFIG_INOTIFY=y
772CONFIG_INOTIFY_USER=y
773# CONFIG_QUOTA is not set
774CONFIG_DNOTIFY=y
775# CONFIG_AUTOFS_FS is not set
776# CONFIG_AUTOFS4_FS is not set
777CONFIG_FUSE_FS=m
778
779#
780# CD-ROM/DVD Filesystems
781#
782# CONFIG_ISO9660_FS is not set
783# CONFIG_UDF_FS is not set
784
785#
786# DOS/FAT/NT Filesystems
787#
788# CONFIG_MSDOS_FS is not set
789# CONFIG_VFAT_FS is not set
790# CONFIG_NTFS_FS is not set
791
792#
793# Pseudo filesystems
794#
795CONFIG_PROC_FS=y
796CONFIG_PROC_KCORE=y
797CONFIG_SYSFS=y
798# CONFIG_TMPFS is not set
799# CONFIG_HUGETLB_PAGE is not set
800CONFIG_RAMFS=y
801# CONFIG_CONFIGFS_FS is not set
802
803#
804# Miscellaneous filesystems
805#
806# CONFIG_ADFS_FS is not set
807# CONFIG_AFFS_FS is not set
808# CONFIG_HFS_FS is not set
809# CONFIG_HFSPLUS_FS is not set
810# CONFIG_BEFS_FS is not set
811# CONFIG_BFS_FS is not set
812# CONFIG_EFS_FS is not set
813# CONFIG_CRAMFS is not set
814# CONFIG_VXFS_FS is not set
815# CONFIG_HPFS_FS is not set
816# CONFIG_QNX4FS_FS is not set
817# CONFIG_SYSV_FS is not set
818# CONFIG_UFS_FS is not set
819
820#
821# Network File Systems
822#
823CONFIG_NFS_FS=y
824# CONFIG_NFS_V3 is not set
825# CONFIG_NFS_V4 is not set
826# CONFIG_NFS_DIRECTIO is not set
827# CONFIG_NFSD is not set
828CONFIG_ROOT_NFS=y
829CONFIG_LOCKD=y
830CONFIG_NFS_COMMON=y
831CONFIG_SUNRPC=y
832# CONFIG_RPCSEC_GSS_KRB5 is not set
833# CONFIG_RPCSEC_GSS_SPKM3 is not set
834# CONFIG_SMB_FS is not set
835# CONFIG_CIFS is not set
836# CONFIG_CIFS_DEBUG2 is not set
837# CONFIG_NCP_FS is not set
838# CONFIG_CODA_FS is not set
839# CONFIG_AFS_FS is not set
840# CONFIG_9P_FS is not set
841
842#
843# Partition Types
844#
845# CONFIG_PARTITION_ADVANCED is not set
846CONFIG_MSDOS_PARTITION=y
847
848#
849# Native Language Support
850#
851# CONFIG_NLS is not set
852
853#
854# Profiling support
855#
856# CONFIG_PROFILING is not set
857
858#
859# Kernel hacking
860#
861CONFIG_TRACE_IRQFLAGS_SUPPORT=y
862# CONFIG_PRINTK_TIME is not set
863# CONFIG_MAGIC_SYSRQ is not set
864# CONFIG_UNUSED_SYMBOLS is not set
865# CONFIG_DEBUG_KERNEL is not set
866CONFIG_LOG_BUF_SHIFT=14
867# CONFIG_DEBUG_FS is not set
868CONFIG_CROSSCOMPILE=y
869CONFIG_CMDLINE=""
870
871#
872# Security options
873#
874CONFIG_KEYS=y
875CONFIG_KEYS_DEBUG_PROC_KEYS=y
876# CONFIG_SECURITY is not set
877
878#
879# Cryptographic options
880#
881CONFIG_CRYPTO=y
882CONFIG_CRYPTO_HMAC=y
883CONFIG_CRYPTO_NULL=m
884CONFIG_CRYPTO_MD4=m
885CONFIG_CRYPTO_MD5=m
886CONFIG_CRYPTO_SHA1=m
887CONFIG_CRYPTO_SHA256=m
888CONFIG_CRYPTO_SHA512=m
889CONFIG_CRYPTO_WP512=m
890CONFIG_CRYPTO_TGR192=m
891CONFIG_CRYPTO_DES=m
892CONFIG_CRYPTO_BLOWFISH=m
893CONFIG_CRYPTO_TWOFISH=m
894CONFIG_CRYPTO_SERPENT=m
895CONFIG_CRYPTO_AES=m
896CONFIG_CRYPTO_CAST5=m
897CONFIG_CRYPTO_CAST6=m
898CONFIG_CRYPTO_TEA=m
899CONFIG_CRYPTO_ARC4=m
900CONFIG_CRYPTO_KHAZAD=m
901CONFIG_CRYPTO_ANUBIS=m
902CONFIG_CRYPTO_DEFLATE=m
903CONFIG_CRYPTO_MICHAEL_MIC=m
904CONFIG_CRYPTO_CRC32C=m
905# CONFIG_CRYPTO_TEST is not set
906
907#
908# Hardware crypto devices
909#
910
911#
912# Library routines
913#
914# CONFIG_CRC_CCITT is not set
915CONFIG_CRC16=m
916CONFIG_CRC32=m
917CONFIG_LIBCRC32C=m
918CONFIG_ZLIB_INFLATE=m
919CONFIG_ZLIB_DEFLATE=m
920CONFIG_PLIST=y
diff --git a/arch/mips/ite-boards/Kconfig b/arch/mips/ite-boards/Kconfig
deleted file mode 100644
index a6d59ad8f846..000000000000
--- a/arch/mips/ite-boards/Kconfig
+++ /dev/null
@@ -1,8 +0,0 @@
1config IT8172_REVC
2 bool "Support for older IT8172 (Rev C)"
3 depends on MIPS_ITE8172
4 help
5 Say Y here to support the older, Revision C version of the Integrated
6 Technology Express, Inc. ITE8172 SBC. Vendor page at
7 <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
8 board at <http://www.mvista.com/partners/semiconductor/ite.html>.
diff --git a/arch/mips/ite-boards/generic/Makefile b/arch/mips/ite-boards/generic/Makefile
deleted file mode 100644
index 63431538d0ec..000000000000
--- a/arch/mips/ite-boards/generic/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
1#
2# Copyright 2000 MontaVista Software Inc.
3# Author: MontaVista Software, Inc.
4# ppopov@mvista.com or source@mvista.com
5#
6# Makefile for the ITE 8172 (qed-4n-s01b) board, generic files.
7#
8
9obj-y += it8172_setup.o irq.o pmon_prom.o \
10 time.o lpc.o puts.o reset.o
11
12obj-$(CONFIG_IT8172_CIR)+= it8172_cir.o
13obj-$(CONFIG_KGDB) += dbg_io.o
14
15EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ite-boards/generic/dbg_io.c b/arch/mips/ite-boards/generic/dbg_io.c
deleted file mode 100644
index 8e9cd8a9670a..000000000000
--- a/arch/mips/ite-boards/generic/dbg_io.c
+++ /dev/null
@@ -1,124 +0,0 @@
1
2
3#ifdef CONFIG_KGDB
4
5/* --- CONFIG --- */
6
7/* we need uint32 uint8 */
8/* #include "types.h" */
9typedef unsigned char uint8;
10typedef unsigned int uint32;
11
12/* --- END OF CONFIG --- */
13
14#define UART16550_BAUD_2400 2400
15#define UART16550_BAUD_4800 4800
16#define UART16550_BAUD_9600 9600
17#define UART16550_BAUD_19200 19200
18#define UART16550_BAUD_38400 38400
19#define UART16550_BAUD_57600 57600
20#define UART16550_BAUD_115200 115200
21
22#define UART16550_PARITY_NONE 0
23#define UART16550_PARITY_ODD 0x08
24#define UART16550_PARITY_EVEN 0x18
25#define UART16550_PARITY_MARK 0x28
26#define UART16550_PARITY_SPACE 0x38
27
28#define UART16550_DATA_5BIT 0x0
29#define UART16550_DATA_6BIT 0x1
30#define UART16550_DATA_7BIT 0x2
31#define UART16550_DATA_8BIT 0x3
32
33#define UART16550_STOP_1BIT 0x0
34#define UART16550_STOP_2BIT 0x4
35
36/* ----------------------------------------------------- */
37
38/* === CONFIG === */
39
40/* [stevel] we use the IT8712 serial port for kgdb */
41#define DEBUG_BASE 0xB40003F8 /* 8712 serial port 1 base address */
42#define MAX_BAUD 115200
43
44/* === END OF CONFIG === */
45
46/* register offset */
47#define OFS_RCV_BUFFER 0
48#define OFS_TRANS_HOLD 0
49#define OFS_SEND_BUFFER 0
50#define OFS_INTR_ENABLE 1
51#define OFS_INTR_ID 2
52#define OFS_DATA_FORMAT 3
53#define OFS_LINE_CONTROL 3
54#define OFS_MODEM_CONTROL 4
55#define OFS_RS232_OUTPUT 4
56#define OFS_LINE_STATUS 5
57#define OFS_MODEM_STATUS 6
58#define OFS_RS232_INPUT 6
59#define OFS_SCRATCH_PAD 7
60
61#define OFS_DIVISOR_LSB 0
62#define OFS_DIVISOR_MSB 1
63
64
65/* memory-mapped read/write of the port */
66#define UART16550_READ(y) (*((volatile uint8*)(DEBUG_BASE + y)))
67#define UART16550_WRITE(y,z) ((*((volatile uint8*)(DEBUG_BASE + y))) = z)
68
69void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
70{
71 /* disable interrupts */
72 UART16550_WRITE(OFS_INTR_ENABLE, 0);
73
74 /* set up baud rate */
75 {
76 uint32 divisor;
77
78 /* set DIAB bit */
79 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
80
81 /* set divisor */
82 divisor = MAX_BAUD / baud;
83 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
84 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
85
86 /* clear DIAB bit */
87 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
88 }
89
90 /* set data format */
91 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
92}
93
94static int remoteDebugInitialized = 0;
95
96uint8 getDebugChar(void)
97{
98 if (!remoteDebugInitialized) {
99 remoteDebugInitialized = 1;
100 debugInit(UART16550_BAUD_115200,
101 UART16550_DATA_8BIT,
102 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
103 }
104
105 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
106 return UART16550_READ(OFS_RCV_BUFFER);
107}
108
109
110int putDebugChar(uint8 byte)
111{
112 if (!remoteDebugInitialized) {
113 remoteDebugInitialized = 1;
114 debugInit(UART16550_BAUD_115200,
115 UART16550_DATA_8BIT,
116 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
117 }
118
119 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
120 UART16550_WRITE(OFS_SEND_BUFFER, byte);
121 return 1;
122}
123
124#endif
diff --git a/arch/mips/ite-boards/generic/irq.c b/arch/mips/ite-boards/generic/irq.c
deleted file mode 100644
index cb59ca4f76f0..000000000000
--- a/arch/mips/ite-boards/generic/irq.c
+++ /dev/null
@@ -1,308 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * ITE 8172G interrupt/setup routines.
4 *
5 * Copyright 2000,2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * Part of this file was derived from Carsten Langgaard's
10 * arch/mips/mips-boards/atlas/atlas_int.c.
11 *
12 * Carsten Langgaard, carstenl@mips.com
13 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35#include <linux/errno.h>
36#include <linux/init.h>
37#include <linux/irq.h>
38#include <linux/kernel_stat.h>
39#include <linux/module.h>
40#include <linux/signal.h>
41#include <linux/sched.h>
42#include <linux/types.h>
43#include <linux/interrupt.h>
44#include <linux/ioport.h>
45#include <linux/timex.h>
46#include <linux/slab.h>
47#include <linux/random.h>
48#include <linux/serial_reg.h>
49#include <linux/bitops.h>
50
51#include <asm/bootinfo.h>
52#include <asm/io.h>
53#include <asm/mipsregs.h>
54#include <asm/system.h>
55#include <asm/it8172/it8172.h>
56#include <asm/it8172/it8172_int.h>
57#include <asm/it8172/it8172_dbg.h>
58
59/* revisit */
60#define EXT_IRQ0_TO_IP 2 /* IP 2 */
61#define EXT_IRQ5_TO_IP 7 /* IP 7 */
62
63#define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
64
65extern void set_debug_traps(void);
66extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
67
68struct it8172_intc_regs volatile *it8172_hw0_icregs =
69 (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE));
70
71static void disable_it8172_irq(unsigned int irq_nr)
72{
73 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
74 /* LPC interrupt */
75 it8172_hw0_icregs->lpc_mask |=
76 (1 << (irq_nr - IT8172_LPC_IRQ_BASE));
77 } else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
78 /* Local Bus interrupt */
79 it8172_hw0_icregs->lb_mask |=
80 (1 << (irq_nr - IT8172_LB_IRQ_BASE));
81 } else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
82 /* PCI and other interrupts */
83 it8172_hw0_icregs->pci_mask |=
84 (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
85 } else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
86 /* NMI interrupts */
87 it8172_hw0_icregs->nmi_mask |=
88 (1 << (irq_nr - IT8172_NMI_IRQ_BASE));
89 } else {
90 panic("disable_it8172_irq: bad irq %d", irq_nr);
91 }
92}
93
94static void enable_it8172_irq(unsigned int irq_nr)
95{
96 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
97 /* LPC interrupt */
98 it8172_hw0_icregs->lpc_mask &=
99 ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
100 }
101 else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
102 /* Local Bus interrupt */
103 it8172_hw0_icregs->lb_mask &=
104 ~(1 << (irq_nr - IT8172_LB_IRQ_BASE));
105 }
106 else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
107 /* PCI and other interrupts */
108 it8172_hw0_icregs->pci_mask &=
109 ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
110 }
111 else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
112 /* NMI interrupts */
113 it8172_hw0_icregs->nmi_mask &=
114 ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
115 }
116 else {
117 panic("enable_it8172_irq: bad irq %d", irq_nr);
118 }
119}
120
121static unsigned int startup_ite_irq(unsigned int irq)
122{
123 enable_it8172_irq(irq);
124 return 0;
125}
126
127#define shutdown_ite_irq disable_it8172_irq
128#define mask_and_ack_ite_irq disable_it8172_irq
129
130static void end_ite_irq(unsigned int irq)
131{
132 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
133 enable_it8172_irq(irq);
134}
135
136static struct irq_chip it8172_irq_type = {
137 .typename = "ITE8172",
138 .startup = startup_ite_irq,
139 .shutdown = shutdown_ite_irq,
140 .enable = enable_it8172_irq,
141 .disable = disable_it8172_irq,
142 .ack = mask_and_ack_ite_irq,
143 .end = end_ite_irq,
144};
145
146
147static void enable_none(unsigned int irq) { }
148static unsigned int startup_none(unsigned int irq) { return 0; }
149static void disable_none(unsigned int irq) { }
150static void ack_none(unsigned int irq) { }
151
152/* startup is the same as "enable", shutdown is same as "disable" */
153#define shutdown_none disable_none
154#define end_none enable_none
155
156static struct irq_chip cp0_irq_type = {
157 .typename = "CP0 Count",
158 .startup = startup_none,
159 .shutdown = shutdown_none,
160 .enable = enable_none,
161 .disable = disable_none,
162 .ack = ack_none,
163 .end = end_none
164};
165
166void enable_cpu_timer(void)
167{
168 unsigned long flags;
169
170 local_irq_save(flags);
171 set_c0_status(0x100 << EXT_IRQ5_TO_IP);
172 local_irq_restore(flags);
173}
174
175void __init arch_init_irq(void)
176{
177 int i;
178 unsigned long flags;
179
180 /* mask all interrupts */
181 it8172_hw0_icregs->lb_mask = 0xffff;
182 it8172_hw0_icregs->lpc_mask = 0xffff;
183 it8172_hw0_icregs->pci_mask = 0xffff;
184 it8172_hw0_icregs->nmi_mask = 0xffff;
185
186 /* make all interrupts level triggered */
187 it8172_hw0_icregs->lb_trigger = 0;
188 it8172_hw0_icregs->lpc_trigger = 0;
189 it8172_hw0_icregs->pci_trigger = 0;
190 it8172_hw0_icregs->nmi_trigger = 0;
191
192 /* active level setting */
193 /* uart, keyboard, and mouse are active high */
194 it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000);
195 it8172_hw0_icregs->lb_level |= 0x20;
196
197 /* keyboard and mouse are edge triggered */
198 it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000);
199
200
201#if 0
202 // Enable this piece of code to make internal USB interrupt
203 // edge triggered.
204 it8172_hw0_icregs->pci_trigger |=
205 (1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
206 it8172_hw0_icregs->pci_level &=
207 ~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
208#endif
209
210 for (i = 0; i <= IT8172_LAST_IRQ; i++) {
211 irq_desc[i].chip = &it8172_irq_type;
212 spin_lock_init(&irq_desc[i].lock);
213 }
214 irq_desc[MIPS_CPU_TIMER_IRQ].chip = &cp0_irq_type;
215 set_c0_status(ALLINTS_NOTIMER);
216}
217
218void mips_spurious_interrupt(struct pt_regs *regs)
219{
220#if 1
221 return;
222#else
223 unsigned long status, cause;
224
225 printk("got spurious interrupt\n");
226 status = read_c0_status();
227 cause = read_c0_cause();
228 printk("status %x cause %x\n", status, cause);
229 printk("epc %x badvaddr %x \n", regs->cp0_epc, regs->cp0_badvaddr);
230#endif
231}
232
233void it8172_hw0_irqdispatch(struct pt_regs *regs)
234{
235 int irq;
236 unsigned short intstatus = 0, status = 0;
237
238 intstatus = it8172_hw0_icregs->intstatus;
239 if (intstatus & 0x8) {
240 panic("Got NMI interrupt");
241 } else if (intstatus & 0x4) {
242 /* PCI interrupt */
243 irq = 0;
244 status |= it8172_hw0_icregs->pci_req;
245 while (!(status & 0x1)) {
246 irq++;
247 status >>= 1;
248 }
249 irq += IT8172_PCI_DEV_IRQ_BASE;
250 } else if (intstatus & 0x1) {
251 /* Local Bus interrupt */
252 irq = 0;
253 status |= it8172_hw0_icregs->lb_req;
254 while (!(status & 0x1)) {
255 irq++;
256 status >>= 1;
257 }
258 irq += IT8172_LB_IRQ_BASE;
259 } else if (intstatus & 0x2) {
260 /* LPC interrupt */
261 /* Since some lpc interrupts are edge triggered,
262 * we could lose an interrupt this way because
263 * we acknowledge all ints at onces. Revisit.
264 */
265 status |= it8172_hw0_icregs->lpc_req;
266 it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */
267 irq = 0;
268 while (!(status & 0x1)) {
269 irq++;
270 status >>= 1;
271 }
272 irq += IT8172_LPC_IRQ_BASE;
273 } else
274 return;
275
276 do_IRQ(irq, regs);
277}
278
279asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
280{
281 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
282
283 if (!pending)
284 mips_spurious_interrupt(regs);
285 else if (pending & CAUSEF_IP7)
286 ll_timer_interrupt(127, regs);
287 else if (pending & CAUSEF_IP2)
288 it8172_hw0_irqdispatch(regs);
289}
290
291void show_pending_irqs(void)
292{
293 fputs("intstatus: ");
294 put32(it8172_hw0_icregs->intstatus);
295 puts("");
296
297 fputs("pci_req: ");
298 put32(it8172_hw0_icregs->pci_req);
299 puts("");
300
301 fputs("lb_req: ");
302 put32(it8172_hw0_icregs->lb_req);
303 puts("");
304
305 fputs("lpc_req: ");
306 put32(it8172_hw0_icregs->lpc_req);
307 puts("");
308}
diff --git a/arch/mips/ite-boards/generic/it8172_cir.c b/arch/mips/ite-boards/generic/it8172_cir.c
deleted file mode 100644
index bfc25adcfec6..000000000000
--- a/arch/mips/ite-boards/generic/it8172_cir.c
+++ /dev/null
@@ -1,170 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 Consumer IR port generic routines.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31
32#ifdef CONFIG_IT8172_CIR
33
34#include <linux/types.h>
35#include <linux/pci.h>
36#include <linux/kernel.h>
37#include <linux/init.h>
38
39#include <asm/it8172/it8172.h>
40#include <asm/it8172/it8172_cir.h>
41
42
43volatile struct it8172_cir_regs *cir_regs[NUM_CIR_PORTS] = {
44 (volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR0_BASE)),
45 (volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR1_BASE))};
46
47
48/*
49 * Initialize Consumer IR Port.
50 */
51int cir_port_init(struct cir_port *cir)
52{
53 int port = cir->port;
54 unsigned char data;
55
56 /* set baud rate */
57 cir_regs[port]->bdlr = cir->baud_rate & 0xff;
58 cir_regs[port]->bdhr = (cir->baud_rate >> 8) & 0xff;
59
60 /* set receiver control register */
61 cir_regs[port]->rcr = (CIR_SET_RDWOS(cir->rdwos) | CIR_SET_RXDCR(cir->rxdcr));
62
63 /* set carrier frequency register */
64 cir_regs[port]->cfr = (CIR_SET_CF(cir->cfq) | CIR_SET_HS(cir->hcfs));
65
66 /* set fifo threshold */
67 data = cir_regs[port]->mstcr & 0xf3;
68 data |= CIR_SET_FIFO_TL(cir->fifo_tl);
69 cir_regs[port]->mstcr = data;
70
71 clear_fifo(cir);
72 enable_receiver(cir);
73 disable_rx_demodulation(cir);
74
75 set_rx_active(cir);
76 int_enable(cir);
77 rx_int_enable(cir);
78
79 return 0;
80}
81
82
83void clear_fifo(struct cir_port *cir)
84{
85 cir_regs[cir->port]->mstcr |= CIR_FIFO_CLEAR;
86}
87
88void enable_receiver(struct cir_port *cir)
89{
90 cir_regs[cir->port]->rcr |= CIR_RXEN;
91}
92
93void disable_receiver(struct cir_port *cir)
94{
95 cir_regs[cir->port]->rcr &= ~CIR_RXEN;
96}
97
98void enable_rx_demodulation(struct cir_port *cir)
99{
100 cir_regs[cir->port]->rcr |= CIR_RXEND;
101}
102
103void disable_rx_demodulation(struct cir_port *cir)
104{
105 cir_regs[cir->port]->rcr &= ~CIR_RXEND;
106}
107
108void set_rx_active(struct cir_port *cir)
109{
110 cir_regs[cir->port]->rcr |= CIR_RXACT;
111}
112
113void int_enable(struct cir_port *cir)
114{
115 cir_regs[cir->port]->ier |= CIR_IEC;
116}
117
118void rx_int_enable(struct cir_port *cir)
119{
120 cir_regs[cir->port]->ier |= CIR_RDAIE;
121}
122
123void dump_regs(struct cir_port *cir)
124{
125 printk("mstcr %x ier %x iir %x cfr %x rcr %x tcr %x tfsr %x rfsr %x\n",
126 cir_regs[cir->port]->mstcr,
127 cir_regs[cir->port]->ier,
128 cir_regs[cir->port]->iir,
129 cir_regs[cir->port]->cfr,
130 cir_regs[cir->port]->rcr,
131 cir_regs[cir->port]->tcr,
132 cir_regs[cir->port]->tfsr,
133 cir_regs[cir->port]->rfsr);
134
135 while (cir_regs[cir->port]->iir & CIR_RDAI) {
136 printk("data %x\n", cir_regs[cir->port]->dr);
137 }
138}
139
140void dump_reg_addr(struct cir_port *cir)
141{
142 printk("dr %x mstcr %x ier %x iir %x cfr %x rcr %x tcr %x bdlr %x bdhr %x tfsr %x rfsr %x\n",
143 (unsigned)&cir_regs[cir->port]->dr,
144 (unsigned)&cir_regs[cir->port]->mstcr,
145 (unsigned)&cir_regs[cir->port]->ier,
146 (unsigned)&cir_regs[cir->port]->iir,
147 (unsigned)&cir_regs[cir->port]->cfr,
148 (unsigned)&cir_regs[cir->port]->rcr,
149 (unsigned)&cir_regs[cir->port]->tcr,
150 (unsigned)&cir_regs[cir->port]->bdlr,
151 (unsigned)&cir_regs[cir->port]->bdhr,
152 (unsigned)&cir_regs[cir->port]->tfsr,
153 (unsigned)&cir_regs[cir->port]->rfsr);
154}
155
156int cir_get_rx_count(struct cir_port *cir)
157{
158 return cir_regs[cir->port]->rfsr & CIR_RXFBC_MASK;
159}
160
161char cir_read_data(struct cir_port *cir)
162{
163 return cir_regs[cir->port]->dr;
164}
165
166char get_int_status(struct cir_port *cir)
167{
168 return cir_regs[cir->port]->iir;
169}
170#endif
diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c
deleted file mode 100644
index 07faf3cacff2..000000000000
--- a/arch/mips/ite-boards/generic/it8172_setup.c
+++ /dev/null
@@ -1,352 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * IT8172/QED5231 board setup.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/init.h>
30#include <linux/sched.h>
31#include <linux/ioport.h>
32#include <linux/irq.h>
33#include <linux/serial_reg.h>
34#include <linux/major.h>
35#include <linux/kdev_t.h>
36#include <linux/root_dev.h>
37#include <linux/pm.h>
38
39#include <asm/cpu.h>
40#include <asm/time.h>
41#include <asm/io.h>
42#include <asm/bootinfo.h>
43#include <asm/irq.h>
44#include <asm/mipsregs.h>
45#include <asm/reboot.h>
46#include <asm/traps.h>
47#include <asm/it8172/it8172.h>
48#include <asm/it8712.h>
49
50extern struct resource ioport_resource;
51#ifdef CONFIG_SERIO_I8042
52int init_8712_keyboard(void);
53#endif
54
55extern int SearchIT8712(void);
56extern void InitLPCInterface(void);
57extern char * __init prom_getcmdline(void);
58extern void it8172_restart(char *command);
59extern void it8172_halt(void);
60extern void it8172_power_off(void);
61
62extern void it8172_time_init(void);
63
64#ifdef CONFIG_IT8172_REVC
65struct {
66 struct resource ram;
67 struct resource pci_mem;
68 struct resource pci_io;
69 struct resource flash;
70 struct resource boot;
71} it8172_resources = {
72 {
73 .start = 0, /* to be initted */
74 .end = 0,
75 .name = "RAM",
76 .flags = IORESOURCE_MEM
77 }, {
78 .start = 0x10000000,
79 .end = 0x13FFFFFF,
80 .name = "PCI Mem",
81 .flags = IORESOURCE_MEM
82 }, {
83 .start = 0x14000000,
84 .end = 0x17FFFFFF
85 .name = "PCI I/O",
86 }, {
87 .start = 0x08000000,
88 .end = 0x0CFFFFFF
89 .name = "Flash",
90 }, {
91 .start = 0x1FC00000,
92 .end = 0x1FFFFFFF
93 .name = "Boot ROM",
94 }
95};
96#else
97struct {
98 struct resource ram;
99 struct resource pci_mem0;
100 struct resource pci_mem1;
101 struct resource pci_io;
102 struct resource pci_mem2;
103 struct resource pci_mem3;
104 struct resource flash;
105 struct resource boot;
106} it8172_resources = {
107 {
108 .start = 0, /* to be initted */
109 .end = 0,
110 .name = "RAM",
111 .flags = IORESOURCE_MEM
112 }, {
113 .start = 0x0C000000,
114 .end = 0x0FFFFFFF,
115 .name = "PCI Mem0",
116 .flags = IORESOURCE_MEM
117 }, {
118 .start = 0x10000000,
119 .end = 0x13FFFFFF,
120 .name = "PCI Mem1",
121 .flags = IORESOURCE_MEM
122 }, {
123 .start = 0x14000000,
124 .end = 0x17FFFFFF
125 .name = "PCI I/O",
126 }, {
127 .start = 0x1A000000,
128 .end = 0x1BFFFFFF,
129 .name = "PCI Mem2",
130 .flags = IORESOURCE_MEM
131 }, {
132 .start = 0x1C000000,
133 .end = 0x1FBFFFFF,
134 .name = "PCI Mem3",
135 .flags = IORESOURCE_MEM
136 }, {
137 .start = 0x08000000,
138 .end = 0x0CFFFFFF
139 .name = "Flash",
140 }, {
141 .start = 0x1FC00000,
142 .end = 0x1FFFFFFF
143 .name = "Boot ROM",
144 }
145};
146#endif
147
148
149void __init it8172_init_ram_resource(unsigned long memsize)
150{
151 it8172_resources.ram.end = memsize;
152}
153
154void __init plat_mem_setup(void)
155{
156 unsigned short dsr;
157 char *argptr;
158
159 argptr = prom_getcmdline();
160#ifdef CONFIG_SERIAL_CONSOLE
161 if ((argptr = strstr(argptr, "console=")) == NULL) {
162 argptr = prom_getcmdline();
163 strcat(argptr, " console=ttyS0,115200");
164 }
165#endif
166
167 clear_c0_status(ST0_FR);
168
169 board_time_init = it8172_time_init;
170
171 _machine_restart = it8172_restart;
172 _machine_halt = it8172_halt;
173 pm_power_off = it8172_power_off;
174
175 /*
176 * IO/MEM resources.
177 *
178 * revisit this area.
179 */
180 set_io_port_base(KSEG1);
181 ioport_resource.start = it8172_resources.pci_io.start;
182 ioport_resource.end = it8172_resources.pci_io.end;
183#ifdef CONFIG_IT8172_REVC
184 iomem_resource.start = it8172_resources.pci_mem.start;
185 iomem_resource.end = it8172_resources.pci_mem.end;
186#else
187 iomem_resource.start = it8172_resources.pci_mem0.start;
188 iomem_resource.end = it8172_resources.pci_mem3.end;
189#endif
190
191#ifdef CONFIG_BLK_DEV_INITRD
192 ROOT_DEV = Root_RAM0;
193#endif
194
195 /*
196 * Pull enabled devices out of standby
197 */
198 IT_IO_READ16(IT_PM_DSR, dsr);
199
200 /*
201 * Fixme: This breaks when these drivers are modules!!!
202 */
203#ifdef CONFIG_SOUND_IT8172
204 dsr &= ~IT_PM_DSR_ACSB;
205#else
206 dsr |= IT_PM_DSR_ACSB;
207#endif
208#ifdef CONFIG_BLK_DEV_IT8172
209 dsr &= ~IT_PM_DSR_IDESB;
210#else
211 dsr |= IT_PM_DSR_IDESB;
212#endif
213 IT_IO_WRITE16(IT_PM_DSR, dsr);
214
215 InitLPCInterface();
216
217#ifdef CONFIG_MIPS_ITE8172
218 if (SearchIT8712()) {
219 printk("Found IT8712 Super IO\n");
220 /* enable IT8712 serial port */
221 LPCSetConfig(LDN_SERIAL1, 0x30, 0x01); /* enable */
222 LPCSetConfig(LDN_SERIAL1, 0x23, 0x01); /* clock selection */
223#ifdef CONFIG_SERIO_I8042
224 if (init_8712_keyboard()) {
225 printk("Unable to initialize keyboard\n");
226 LPCSetConfig(LDN_KEYBOARD, 0x30, 0x0); /* disable keyboard */
227 } else {
228 LPCSetConfig(LDN_KEYBOARD, 0x30, 0x1); /* enable keyboard */
229 LPCSetConfig(LDN_KEYBOARD, 0xf0, 0x2);
230 LPCSetConfig(LDN_KEYBOARD, 0x71, 0x3);
231
232 LPCSetConfig(LDN_MOUSE, 0x30, 0x1); /* enable mouse */
233
234 LPCSetConfig(0x4, 0x30, 0x1);
235 LPCSetConfig(0x4, 0xf4, LPCGetConfig(0x4, 0xf4) | 0x80);
236
237 if ((LPCGetConfig(LDN_KEYBOARD, 0x30) == 0) ||
238 (LPCGetConfig(LDN_MOUSE, 0x30) == 0))
239 printk("Error: keyboard or mouse not enabled\n");
240
241 }
242#endif
243 }
244 else {
245 printk("IT8712 Super IO not found\n");
246 }
247#endif
248
249#ifdef CONFIG_IT8172_CIR
250 {
251 unsigned long data;
252 //printk("Enabling CIR0\n");
253 IT_IO_READ16(IT_PM_DSR, data);
254 data &= ~IT_PM_DSR_CIR0SB;
255 IT_IO_WRITE16(IT_PM_DSR, data);
256 //printk("DSR register: %x\n", (unsigned)IT_IO_READ16(IT_PM_DSR, data));
257 }
258#endif
259#ifdef CONFIG_IT8172_SCR0
260 {
261 unsigned i;
262 /* Enable Smart Card Reader 0 */
263 /* First power it up */
264 IT_IO_READ16(IT_PM_DSR, i);
265 i &= ~IT_PM_DSR_SCR0SB;
266 IT_IO_WRITE16(IT_PM_DSR, i);
267 /* Then initialize its registers */
268 outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
269 |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
270 |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
271 |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
272 |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
273 IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SFR);
274 outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
275 IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SCDR);
276 }
277#endif /* CONFIG_IT8172_SCR0 */
278#ifdef CONFIG_IT8172_SCR1
279 {
280 unsigned i;
281 /* Enable Smart Card Reader 1 */
282 /* First power it up */
283 IT_IO_READ16(IT_PM_DSR, i);
284 i &= ~IT_PM_DSR_SCR1SB;
285 IT_IO_WRITE16(IT_PM_DSR, i);
286 /* Then initialize its registers */
287 outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
288 |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
289 |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
290 |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
291 |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
292 IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SFR);
293 outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
294 IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SCDR);
295 }
296#endif /* CONFIG_IT8172_SCR1 */
297}
298
299#ifdef CONFIG_SERIO_I8042
300/*
301 * According to the ITE Special BIOS Note for waking up the
302 * keyboard controller...
303 */
304static int init_8712_keyboard(void)
305{
306 unsigned int cmd_port = 0x14000064;
307 unsigned int data_port = 0x14000060;
308 ^^^^^^^^^^^
309 Somebody here doesn't grok the concept of io ports.
310
311 unsigned char data;
312 int i;
313
314 outb(0xaa, cmd_port); /* send self-test cmd */
315 i = 0;
316 while (!(inb(cmd_port) & 0x1)) { /* wait output buffer full */
317 i++;
318 if (i > 0xffffff)
319 return 1;
320 }
321
322 data = inb(data_port);
323 outb(0xcb, cmd_port); /* set ps2 mode */
324 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
325 i++;
326 if (i > 0xffffff)
327 return 1;
328 }
329 outb(0x01, data_port);
330 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
331 i++;
332 if (i > 0xffffff)
333 return 1;
334 }
335
336 outb(0x60, cmd_port); /* write 8042 command byte */
337 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
338 i++;
339 if (i > 0xffffff)
340 return 1;
341 }
342 outb(0x45, data_port); /* at interface, keyboard enabled, system flag */
343 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
344 i++;
345 if (i > 0xffffff)
346 return 1;
347 }
348
349 outb(0xae, cmd_port); /* enable interface */
350 return 0;
351}
352#endif
diff --git a/arch/mips/ite-boards/generic/lpc.c b/arch/mips/ite-boards/generic/lpc.c
deleted file mode 100644
index cc7584fbef8a..000000000000
--- a/arch/mips/ite-boards/generic/lpc.c
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * ITE Semi IT8712 Super I/O functions.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <asm/io.h>
32#include <asm/types.h>
33#include <asm/it8712.h>
34#include <asm/it8172/it8172.h>
35
36#ifndef TRUE
37#define TRUE 1
38#endif
39
40#ifndef FALSE
41#define FALSE 0
42#endif
43
44void LPCEnterMBPnP(void)
45{
46 int i;
47 unsigned char key[4] = {0x87, 0x01, 0x55, 0x55};
48
49 for (i = 0; i<4; i++)
50 outb(key[i], LPC_KEY_ADDR);
51
52}
53
54void LPCExitMBPnP(void)
55{
56 outb(0x02, LPC_KEY_ADDR);
57 outb(0x02, LPC_DATA_ADDR);
58}
59
60void LPCSetConfig(char LdnNumber, char Index, char data)
61{
62 LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
63 outb(0x07, LPC_KEY_ADDR);
64 outb(LdnNumber, LPC_DATA_ADDR);
65 outb(Index, LPC_KEY_ADDR);
66 outb(data, LPC_DATA_ADDR);
67 LPCExitMBPnP();
68}
69
70char LPCGetConfig(char LdnNumber, char Index)
71{
72 char rtn;
73
74 LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
75 outb(0x07, LPC_KEY_ADDR);
76 outb(LdnNumber, LPC_DATA_ADDR);
77 outb(Index, LPC_KEY_ADDR);
78 rtn = inb(LPC_DATA_ADDR);
79 LPCExitMBPnP();
80 return rtn;
81}
82
83int SearchIT8712(void)
84{
85 unsigned char Id1, Id2;
86 unsigned short Id;
87
88 LPCEnterMBPnP();
89 outb(0x20, LPC_KEY_ADDR); /* chip id byte 1 */
90 Id1 = inb(LPC_DATA_ADDR);
91 outb(0x21, LPC_KEY_ADDR); /* chip id byte 2 */
92 Id2 = inb(LPC_DATA_ADDR);
93 Id = (Id1 << 8) | Id2;
94 LPCExitMBPnP();
95 if (Id == 0x8712)
96 return TRUE;
97 else
98 return FALSE;
99}
100
101void InitLPCInterface(void)
102{
103 unsigned char bus, dev_fn;
104 unsigned long data;
105
106 bus = 0;
107 dev_fn = 1<<3 | 4;
108
109
110 /* pci cmd, SERR# Enable */
111 IT_WRITE(IT_CONFADDR,
112 (bus << IT_BUSNUM_SHF) |
113 (dev_fn << IT_FUNCNUM_SHF) |
114 ((0x4 / 4) << IT_REGNUM_SHF));
115 IT_READ(IT_CONFDATA, data);
116 data |= 0x0100;
117 IT_WRITE(IT_CONFADDR,
118 (bus << IT_BUSNUM_SHF) |
119 (dev_fn << IT_FUNCNUM_SHF) |
120 ((0x4 / 4) << IT_REGNUM_SHF));
121 IT_WRITE(IT_CONFDATA, data);
122
123 /* setup serial irq control register */
124 IT_WRITE(IT_CONFADDR,
125 (bus << IT_BUSNUM_SHF) |
126 (dev_fn << IT_FUNCNUM_SHF) |
127 ((0x48 / 4) << IT_REGNUM_SHF));
128 IT_READ(IT_CONFDATA, data);
129 data = (data & 0xffff00ff) | 0xc400;
130 IT_WRITE(IT_CONFADDR,
131 (bus << IT_BUSNUM_SHF) |
132 (dev_fn << IT_FUNCNUM_SHF) |
133 ((0x48 / 4) << IT_REGNUM_SHF));
134 IT_WRITE(IT_CONFDATA, data);
135
136
137 /* Enable I/O Space Subtractive Decode */
138 /* default 0x4C is 0x3f220000 */
139 IT_WRITE(IT_CONFADDR,
140 (bus << IT_BUSNUM_SHF) |
141 (dev_fn << IT_FUNCNUM_SHF) |
142 ((0x4C / 4) << IT_REGNUM_SHF));
143 IT_WRITE(IT_CONFDATA, 0x3f2200f3);
144}
diff --git a/arch/mips/ite-boards/generic/pmon_prom.c b/arch/mips/ite-boards/generic/pmon_prom.c
deleted file mode 100644
index 7d0a79be34d8..000000000000
--- a/arch/mips/ite-boards/generic/pmon_prom.c
+++ /dev/null
@@ -1,135 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PROM library initialisation code, assuming a version of
5 * pmon is the boot code.
6 *
7 * Copyright 2000 MontaVista Software Inc.
8 * Author: MontaVista Software, Inc.
9 * ppopov@mvista.com or source@mvista.com
10 *
11 * This file was derived from Carsten Langgaard's
12 * arch/mips/mips-boards/xx files.
13 *
14 * Carsten Langgaard, carstenl@mips.com
15 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
21 *
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38#include <linux/kernel.h>
39#include <linux/init.h>
40#include <linux/string.h>
41
42#include <asm/bootinfo.h>
43
44extern int prom_argc;
45extern char **prom_argv, **prom_envp;
46
47typedef struct
48{
49 char *name;
50/* char *val; */
51}t_env_var;
52
53
54char * __init prom_getcmdline(void)
55{
56 return &(arcs_cmdline[0]);
57}
58
59void __init prom_init_cmdline(void)
60{
61 char *cp;
62 int actr;
63
64 actr = 1; /* Always ignore argv[0] */
65
66 cp = &(arcs_cmdline[0]);
67 while(actr < prom_argc) {
68 strcpy(cp, prom_argv[actr]);
69 cp += strlen(prom_argv[actr]);
70 *cp++ = ' ';
71 actr++;
72 }
73 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
74 --cp;
75 *cp = '\0';
76
77}
78
79
80char *prom_getenv(char *envname)
81{
82 /*
83 * Return a pointer to the given environment variable.
84 * Environment variables are stored in the form of "memsize=64".
85 */
86
87 t_env_var *env = (t_env_var *)prom_envp;
88 int i;
89
90 i = strlen(envname);
91
92 while(env->name) {
93 if(strncmp(envname, env->name, i) == 0) {
94 return(env->name + strlen(envname) + 1);
95 }
96 env++;
97 }
98 return(NULL);
99}
100
101static inline unsigned char str2hexnum(unsigned char c)
102{
103 if(c >= '0' && c <= '9')
104 return c - '0';
105 if(c >= 'a' && c <= 'f')
106 return c - 'a' + 10;
107 return 0; /* foo */
108}
109
110unsigned long __init prom_free_prom_memory(void)
111{
112 return 0;
113}
114
115unsigned long __init prom_get_memsize(void)
116{
117 char *memsize_str;
118 unsigned int memsize;
119
120 memsize_str = prom_getenv("memsize");
121 if (!memsize_str) {
122#ifdef CONFIG_MIPS_ITE8172
123 memsize = 32;
124#elif defined(CONFIG_MIPS_IVR)
125 memsize = 64;
126#else
127 memsize = 8;
128#endif
129 printk("memsize unknown: setting to %dMB\n", memsize);
130 } else {
131 printk("memsize: %s\n", memsize_str);
132 memsize = simple_strtol(memsize_str, NULL, 0);
133 }
134 return memsize;
135}
diff --git a/arch/mips/ite-boards/generic/puts.c b/arch/mips/ite-boards/generic/puts.c
deleted file mode 100644
index 20b02df6b414..000000000000
--- a/arch/mips/ite-boards/generic/puts.c
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Low level uart routines to directly access a 16550 uart.
5 *
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/types.h>
32
33#define SERIAL_BASE 0xB4011800 /* it8172 */
34#define SER_CMD 5
35#define SER_DATA 0x00
36#define TX_BUSY 0x20
37
38#define TIMEOUT 0xffff
39#undef SLOW_DOWN
40
41static const char digits[16] = "0123456789abcdef";
42static volatile unsigned char *const com1 = (unsigned char *) SERIAL_BASE;
43
44
45#ifdef SLOW_DOWN
46static inline void slow_down()
47{
48 int k;
49 for (k = 0; k < 10000; k++);
50}
51#else
52#define slow_down()
53#endif
54
55void putch(const unsigned char c)
56{
57 unsigned char ch;
58 int i = 0;
59
60 do {
61 ch = com1[SER_CMD];
62 slow_down();
63 i++;
64 if (i > TIMEOUT) {
65 break;
66 }
67 } while (0 == (ch & TX_BUSY));
68 com1[SER_DATA] = c;
69}
70
71void puts(unsigned char *cp)
72{
73 unsigned char ch;
74 int i = 0;
75
76 while (*cp) {
77 do {
78 ch = com1[SER_CMD];
79 slow_down();
80 i++;
81 if (i > TIMEOUT) {
82 break;
83 }
84 } while (0 == (ch & TX_BUSY));
85 com1[SER_DATA] = *cp++;
86 }
87 putch('\r');
88 putch('\n');
89}
90
91void fputs(unsigned char *cp)
92{
93 unsigned char ch;
94 int i = 0;
95
96 while (*cp) {
97
98 do {
99 ch = com1[SER_CMD];
100 slow_down();
101 i++;
102 if (i > TIMEOUT) {
103 break;
104 }
105 } while (0 == (ch & TX_BUSY));
106 com1[SER_DATA] = *cp++;
107 }
108}
109
110
111void put64(uint64_t ul)
112{
113 int cnt;
114 unsigned ch;
115
116 cnt = 16; /* 16 nibbles in a 64 bit long */
117 putch('0');
118 putch('x');
119 do {
120 cnt--;
121 ch = (unsigned char) (ul >> cnt * 4) & 0x0F;
122 putch(digits[ch]);
123 } while (cnt > 0);
124}
125
126void put32(unsigned u)
127{
128 int cnt;
129 unsigned ch;
130
131 cnt = 8; /* 8 nibbles in a 32 bit long */
132 putch('0');
133 putch('x');
134 do {
135 cnt--;
136 ch = (unsigned char) (u >> cnt * 4) & 0x0F;
137 putch(digits[ch]);
138 } while (cnt > 0);
139}
diff --git a/arch/mips/ite-boards/generic/reset.c b/arch/mips/ite-boards/generic/reset.c
deleted file mode 100644
index 03bd5ba8c913..000000000000
--- a/arch/mips/ite-boards/generic/reset.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * ITE 8172 reset routines.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/sched.h>
32#include <linux/mm.h>
33#include <asm/cacheflush.h>
34#include <asm/io.h>
35#include <asm/processor.h>
36#include <asm/reboot.h>
37#include <asm/system.h>
38
39void it8172_restart()
40{
41 set_c0_status(ST0_BEV | ST0_ERL);
42 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
43 flush_cache_all();
44 write_c0_wired(0);
45 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
46}
47
48void it8172_halt(void)
49{
50 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
51 while (1)
52 __asm__(".set\tmips3\n\t"
53 "wait\n\t"
54 ".set\tmips0");
55}
56
57void it8172_power_off(void)
58{
59 it8172_halt();
60}
diff --git a/arch/mips/ite-boards/generic/time.c b/arch/mips/ite-boards/generic/time.c
deleted file mode 100644
index 3dc55569ff7f..000000000000
--- a/arch/mips/ite-boards/generic/time.c
+++ /dev/null
@@ -1,249 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * Copyright (C) 2003 MontaVista Software Inc.
6 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 * Setting up the clock on the MIPS boards.
26 */
27#include <linux/init.h>
28#include <linux/kernel_stat.h>
29#include <linux/sched.h>
30#include <linux/time.h>
31#include <linux/spinlock.h>
32#include <linux/mc146818rtc.h>
33
34#include <asm/time.h>
35#include <asm/mipsregs.h>
36#include <asm/ptrace.h>
37#include <asm/it8172/it8172.h>
38#include <asm/it8172/it8172_int.h>
39#include <asm/debug.h>
40
41#define IT8172_RTC_ADR_REG (IT8172_PCI_IO_BASE + IT_RTC_BASE)
42#define IT8172_RTC_DAT_REG (IT8172_RTC_ADR_REG + 1)
43#define IT8172_RTC_CENTURY_REG (IT8172_PCI_IO_BASE + IT_RTC_CENTURY)
44
45static volatile char *rtc_adr_reg = (char*)KSEG1ADDR(IT8172_RTC_ADR_REG);
46static volatile char *rtc_dat_reg = (char*)KSEG1ADDR(IT8172_RTC_DAT_REG);
47static volatile char *rtc_century_reg = (char*)KSEG1ADDR(IT8172_RTC_CENTURY_REG);
48
49unsigned char it8172_rtc_read_data(unsigned long addr)
50{
51 unsigned char retval;
52
53 *rtc_adr_reg = addr;
54 retval = *rtc_dat_reg;
55 return retval;
56}
57
58void it8172_rtc_write_data(unsigned char data, unsigned long addr)
59{
60 *rtc_adr_reg = addr;
61 *rtc_dat_reg = data;
62}
63
64#undef CMOS_READ
65#undef CMOS_WRITE
66#define CMOS_READ(addr) it8172_rtc_read_data(addr)
67#define CMOS_WRITE(data, addr) it8172_rtc_write_data(data, addr)
68
69static unsigned char saved_control; /* remember rtc control reg */
70static inline int rtc_24h(void) { return saved_control & RTC_24H; }
71static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; }
72
73static inline unsigned char
74bin_to_hw(unsigned char c)
75{
76 if (rtc_dm_binary())
77 return c;
78 else
79 return ((c/10) << 4) + (c%10);
80}
81
82static inline unsigned char
83hw_to_bin(unsigned char c)
84{
85 if (rtc_dm_binary())
86 return c;
87 else
88 return (c>>4)*10 + (c &0xf);
89}
90
91/* 0x80 bit indicates pm in 12-hour format */
92static inline unsigned char
93hour_bin_to_hw(unsigned char c)
94{
95 if (rtc_24h())
96 return bin_to_hw(c);
97 if (c >= 12)
98 return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */
99 else
100 return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */
101}
102
103static inline unsigned char
104hour_hw_to_bin(unsigned char c)
105{
106 unsigned char tmp = hw_to_bin(c&0x3f);
107 if (rtc_24h())
108 return tmp;
109 if (c & 0x80)
110 return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */
111 else
112 return (tmp==12)?0:tmp; /* 12am is 0 */
113}
114
115static unsigned long r4k_offset; /* Amount to increment compare reg each time */
116static unsigned long r4k_cur; /* What counter should be at next timer irq */
117extern unsigned int mips_hpt_frequency;
118
119/*
120 * Figure out the r4k offset, the amount to increment the compare
121 * register for each time tick.
122 * Use the RTC to calculate offset.
123 */
124static unsigned long __init cal_r4koff(void)
125{
126 unsigned int flags;
127
128 local_irq_save(flags);
129
130 /* Start counter exactly on falling edge of update flag */
131 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
132 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
133
134 /* Start r4k counter. */
135 write_c0_count(0);
136
137 /* Read counter exactly on falling edge of update flag */
138 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
139 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
140
141 mips_hpt_frequency = read_c0_count();
142
143 /* restore interrupts */
144 local_irq_restore(flags);
145
146 return (mips_hpt_frequency / HZ);
147}
148
149static unsigned long
150it8172_rtc_get_time(void)
151{
152 unsigned int year, mon, day, hour, min, sec;
153 unsigned int flags;
154
155 /* avoid update-in-progress. */
156 for (;;) {
157 local_irq_save(flags);
158 if (! (CMOS_READ(RTC_REG_A) & RTC_UIP))
159 break;
160 /* don't hold intr closed all the time */
161 local_irq_restore(flags);
162 }
163
164 /* Read regs. */
165 sec = hw_to_bin(CMOS_READ(RTC_SECONDS));
166 min = hw_to_bin(CMOS_READ(RTC_MINUTES));
167 hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS));
168 day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH));
169 mon = hw_to_bin(CMOS_READ(RTC_MONTH));
170 year = hw_to_bin(CMOS_READ(RTC_YEAR)) +
171 hw_to_bin(*rtc_century_reg) * 100;
172
173 /* restore interrupts */
174 local_irq_restore(flags);
175
176 return mktime(year, mon, day, hour, min, sec);
177}
178
179static int
180it8172_rtc_set_time(unsigned long t)
181{
182 struct rtc_time tm;
183 unsigned int flags;
184
185 /* convert */
186 to_tm(t, &tm);
187
188 /* avoid update-in-progress. */
189 for (;;) {
190 local_irq_save(flags);
191 if (! (CMOS_READ(RTC_REG_A) & RTC_UIP))
192 break;
193 /* don't hold intr closed all the time */
194 local_irq_restore(flags);
195 }
196
197 *rtc_century_reg = bin_to_hw(tm.tm_year/100);
198 CMOS_WRITE(bin_to_hw(tm.tm_sec), RTC_SECONDS);
199 CMOS_WRITE(bin_to_hw(tm.tm_min), RTC_MINUTES);
200 CMOS_WRITE(hour_bin_to_hw(tm.tm_hour), RTC_HOURS);
201 CMOS_WRITE(bin_to_hw(tm.tm_mday), RTC_DAY_OF_MONTH);
202 CMOS_WRITE(bin_to_hw(tm.tm_mon+1), RTC_MONTH); /* tm_mon starts from 0 */
203 CMOS_WRITE(bin_to_hw(tm.tm_year%100), RTC_YEAR);
204
205 /* restore interrupts */
206 local_irq_restore(flags);
207
208 return 0;
209}
210
211void __init it8172_time_init(void)
212{
213 unsigned int est_freq, flags;
214
215 local_irq_save(flags);
216
217 saved_control = CMOS_READ(RTC_CONTROL);
218
219 printk("calculating r4koff... ");
220 r4k_offset = cal_r4koff();
221 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
222
223 est_freq = 2*r4k_offset*HZ;
224 est_freq += 5000; /* round */
225 est_freq -= est_freq%10000;
226 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
227 (est_freq%1000000)*100/1000000);
228
229 local_irq_restore(flags);
230
231 rtc_mips_get_time = it8172_rtc_get_time;
232 rtc_mips_set_time = it8172_rtc_set_time;
233}
234
235#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
236
237void __init plat_timer_setup(struct irqaction *irq)
238{
239 puts("timer_setup\n");
240 put32(NR_IRQS);
241 puts("");
242 /* we are using the cpu counter for timer interrupts */
243 setup_irq(MIPS_CPU_TIMER_IRQ, irq);
244
245 /* to generate the first timer interrupt */
246 r4k_cur = (read_c0_count() + r4k_offset);
247 write_c0_compare(r4k_cur);
248 set_c0_status(ALLINTS);
249}
diff --git a/arch/mips/ite-boards/ivr/Makefile b/arch/mips/ite-boards/ivr/Makefile
deleted file mode 100644
index e4fa6042b472..000000000000
--- a/arch/mips/ite-boards/ivr/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
1#
2# Copyright 2000 MontaVista Software Inc.
3# Author: MontaVista Software, Inc.
4# ppopov@mvista.com or source@mvista.com
5#
6# Makefile for the Globespan IVR board,
7# board-specific files.
8#
9
10obj-y += init.o
diff --git a/arch/mips/ite-boards/ivr/README b/arch/mips/ite-boards/ivr/README
deleted file mode 100644
index aa7d8db855bb..000000000000
--- a/arch/mips/ite-boards/ivr/README
+++ /dev/null
@@ -1,3 +0,0 @@
1This is not really a board made by ITE Semi, but it's very
2similar to the ITE QED-4N-S01B board. The IVR board is made
3by Globespan and it's a reference board for the PVR chip.
diff --git a/arch/mips/ite-boards/ivr/init.c b/arch/mips/ite-boards/ivr/init.c
deleted file mode 100644
index 05cf9218c432..000000000000
--- a/arch/mips/ite-boards/ivr/init.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * IVR board setup.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/init.h>
30#include <linux/mm.h>
31#include <linux/sched.h>
32#include <linux/bootmem.h>
33#include <asm/addrspace.h>
34#include <asm/bootinfo.h>
35#include <linux/string.h>
36#include <linux/kernel.h>
37#include <asm/sections.h>
38#include <asm/it8172/it8172.h>
39#include <asm/it8172/it8172_dbg.h>
40
41int prom_argc;
42char **prom_argv, **prom_envp;
43
44extern void __init prom_init_cmdline(void);
45extern unsigned long __init prom_get_memsize(void);
46extern void __init it8172_init_ram_resource(unsigned long memsize);
47
48const char *get_system_type(void)
49{
50 return "Globespan IVR";
51}
52
53void __init prom_init(void)
54{
55 unsigned long mem_size;
56 unsigned long pcicr;
57
58 prom_argc = fw_arg0;
59 prom_argv = (char **) fw_arg1;
60 prom_envp = (int *) fw_arg3;
61
62 mips_machgroup = MACH_GROUP_GLOBESPAN;
63 mips_machtype = MACH_IVR; /* Globespan's iTVC15 reference board */
64
65 prom_init_cmdline();
66
67 /* pmon does not set memsize */
68 mem_size = prom_get_memsize();
69 mem_size = mem_size << 20;
70
71 /*
72 * make the entire physical memory visible to pci bus masters
73 */
74 IT_READ(IT_MC_PCICR, pcicr);
75 pcicr &= ~0x1f;
76 pcicr |= (mem_size - 1) >> 22;
77 IT_WRITE(IT_MC_PCICR, pcicr);
78
79 it8172_init_ram_resource(mem_size);
80 add_memory_region(0, mem_size, BOOT_MEM_RAM);
81}
diff --git a/arch/mips/ite-boards/qed-4n-s01b/Makefile b/arch/mips/ite-boards/qed-4n-s01b/Makefile
deleted file mode 100644
index bb9972ad9c45..000000000000
--- a/arch/mips/ite-boards/qed-4n-s01b/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
1#
2# Copyright 2000 MontaVista Software Inc.
3# Author: MontaVista Software, Inc.
4# ppopov@mvista.com or source@mvista.com
5#
6# Makefile for the ITE 8172 (qed-4n-s01b) board, board
7# specific files.
8#
9
10obj-y := init.o
diff --git a/arch/mips/ite-boards/qed-4n-s01b/README b/arch/mips/ite-boards/qed-4n-s01b/README
deleted file mode 100644
index fb4b5197e800..000000000000
--- a/arch/mips/ite-boards/qed-4n-s01b/README
+++ /dev/null
@@ -1,2 +0,0 @@
1This is an ITE (www.iteusa.com) eval board for the ITE 8172G
2system controller, with a QED 5231 CPU.
diff --git a/arch/mips/ite-boards/qed-4n-s01b/init.c b/arch/mips/ite-boards/qed-4n-s01b/init.c
deleted file mode 100644
index ea2a754cafe5..000000000000
--- a/arch/mips/ite-boards/qed-4n-s01b/init.c
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * IT8172/QED5231 board setup.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/init.h>
30#include <linux/mm.h>
31#include <linux/sched.h>
32#include <linux/bootmem.h>
33#include <asm/addrspace.h>
34#include <asm/bootinfo.h>
35#include <linux/string.h>
36#include <linux/kernel.h>
37#include <asm/sections.h>
38#include <asm/it8172/it8172.h>
39#include <asm/it8172/it8172_dbg.h>
40
41int prom_argc;
42char **prom_argv, **prom_envp;
43
44extern void __init prom_init_cmdline(void);
45extern unsigned long __init prom_get_memsize(void);
46extern void __init it8172_init_ram_resource(unsigned long memsize);
47
48const char *get_system_type(void)
49{
50 return "ITE QED-4N-S01B";
51}
52
53void __init prom_init(void)
54{
55 unsigned long mem_size;
56 unsigned long pcicr;
57
58 prom_argc = fw_arg0;
59 prom_argv = (char **) fw_arg1;
60 prom_envp = (int *) fw_arg3;
61
62 mips_machgroup = MACH_GROUP_ITE;
63 mips_machtype = MACH_QED_4N_S01B; /* ITE board name/number */
64
65 prom_init_cmdline();
66 mem_size = prom_get_memsize();
67
68 printk("Memory size: %dMB\n", (unsigned)mem_size);
69
70 mem_size <<= 20; /* MB */
71
72 /*
73 * make the entire physical memory visible to pci bus masters
74 */
75 IT_READ(IT_MC_PCICR, pcicr);
76 pcicr &= ~0x1f;
77 pcicr |= (mem_size - 1) >> 22;
78 IT_WRITE(IT_MC_PCICR, pcicr);
79
80 it8172_init_ram_resource(mem_size);
81 add_memory_region(0, mem_size, BOOT_MEM_RAM);
82}
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index edefa97b2330..3cf0dd4ba548 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -7,7 +7,6 @@ obj-y += pci.o
7# 7#
8# PCI bus host bridge specific code 8# PCI bus host bridge specific code
9# 9#
10obj-$(CONFIG_ITE_BOARD_GEN) += ops-it8172.o
11obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o 10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
12obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o 11obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o
13obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o 12obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o
@@ -28,8 +27,6 @@ obj-$(CONFIG_LASAT) += pci-lasat.o
28obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o 27obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
29obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 28obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
30obj-$(CONFIG_MIPS_EV64120) += fixup-ev64120.o 29obj-$(CONFIG_MIPS_EV64120) += fixup-ev64120.o
31obj-$(CONFIG_MIPS_ITE8172) += fixup-ite8172g.o
32obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o
33obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 30obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
34obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 31obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
35obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 32obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
diff --git a/arch/mips/pci/fixup-ite8172g.c b/arch/mips/pci/fixup-ite8172g.c
deleted file mode 100644
index 2290ea4228dd..000000000000
--- a/arch/mips/pci/fixup-ite8172g.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Board specific pci fixups.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/types.h>
30#include <linux/pci.h>
31#include <linux/kernel.h>
32#include <linux/init.h>
33
34#include <asm/it8172/it8172.h>
35#include <asm/it8172/it8172_pci.h>
36#include <asm/it8172/it8172_int.h>
37
38/*
39 * Shortcuts
40 */
41#define INTA IT8172_PCI_INTA_IRQ
42#define INTB IT8172_PCI_INTB_IRQ
43#define INTC IT8172_PCI_INTC_IRQ
44#define INTD IT8172_PCI_INTD_IRQ
45
46static const int internal_func_irqs[7] __initdata = {
47 IT8172_AC97_IRQ,
48 IT8172_DMA_IRQ,
49 IT8172_CDMA_IRQ,
50 IT8172_USB_IRQ,
51 IT8172_BRIDGE_MASTER_IRQ,
52 IT8172_IDE_IRQ,
53 IT8172_MC68K_IRQ
54};
55
56static char irq_tab_ite8172g[][5] __initdata = {
57 [0x10] = { 0, INTA, INTB, INTC, INTD },
58 [0x11] = { 0, INTA, INTB, INTC, INTD },
59 [0x12] = { 0, INTB, INTC, INTD, INTA },
60 [0x13] = { 0, INTC, INTD, INTA, INTB },
61 [0x14] = { 0, INTD, INTA, INTB, INTC },
62};
63
64int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
65{
66 /*
67 * Internal device 1 is actually 7 different internal devices on the
68 * IT8172G (a multifunction device).
69 */
70 if (slot == 1)
71 return internal_func_irqs[PCI_FUNC(dev->devfn)];
72
73 return irq_tab_ite8172g[slot][pin];
74}
75
76/* Do platform specific device initialization at pci_enable_device() time */
77int pcibios_plat_dev_init(struct pci_dev *dev)
78{
79 return 0;
80}
diff --git a/arch/mips/pci/fixup-ivr.c b/arch/mips/pci/fixup-ivr.c
deleted file mode 100644
index 0c7c16464c11..000000000000
--- a/arch/mips/pci/fixup-ivr.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Globespan IVR board-specific pci fixups.
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30#include <linux/types.h>
31#include <linux/pci.h>
32#include <linux/kernel.h>
33#include <linux/init.h>
34
35#include <asm/it8172/it8172.h>
36#include <asm/it8172/it8172_pci.h>
37#include <asm/it8172/it8172_int.h>
38
39/*
40 * Shortcuts
41 */
42#define INTA IT8172_PCI_INTA_IRQ
43#define INTB IT8172_PCI_INTB_IRQ
44#define INTC IT8172_PCI_INTC_IRQ
45#define INTD IT8172_PCI_INTD_IRQ
46
47static const int internal_func_irqs[7] __initdata = {
48 IT8172_AC97_IRQ,
49 IT8172_DMA_IRQ,
50 IT8172_CDMA_IRQ,
51 IT8172_USB_IRQ,
52 IT8172_BRIDGE_MASTER_IRQ,
53 IT8172_IDE_IRQ,
54 IT8172_MC68K_IRQ
55};
56
57static char irq_tab_ivr[][5] __initdata = {
58 [0x11] = { INTC, INTC, INTD, INTA, INTB }, /* Realtek RTL-8139 */
59 [0x12] = { INTB, INTB, INTB, INTC, INTC }, /* IVR slot */
60 [0x13] = { INTA, INTA, INTB, INTC, INTD } /* Expansion slot */
61};
62
63int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
64{
65 if (slot == 1)
66 return internal_func_irqs[PCI_FUNC(dev->devfn)];
67
68 return irq_tab_ivr[slot][pin];
69}
70
71/* Do platform specific device initialization at pci_enable_device() time */
72int pcibios_plat_dev_init(struct pci_dev *dev)
73{
74 return 0;
75}
diff --git a/arch/mips/pci/ops-it8172.c b/arch/mips/pci/ops-it8172.c
deleted file mode 100644
index ba8328505a0a..000000000000
--- a/arch/mips/pci/ops-it8172.c
+++ /dev/null
@@ -1,213 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 system controller specific pci support.
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/kernel.h>
35#include <linux/init.h>
36
37#include <asm/it8172/it8172.h>
38#include <asm/it8172/it8172_pci.h>
39
40#define PCI_ACCESS_READ 0
41#define PCI_ACCESS_WRITE 1
42
43#undef DEBUG
44#ifdef DEBUG
45#define DBG(x...) printk(x)
46#else
47#define DBG(x...)
48#endif
49
50static struct resource pci_mem_resource_1;
51
52static struct resource pci_io_resource = {
53 .start = 0x14018000,
54 .end = 0x17FFFFFF,
55 .name = "io pci IO space",
56 .flags = IORESOURCE_IO
57};
58
59static struct resource pci_mem_resource_0 = {
60 .start = 0x10101000,
61 .end = 0x13FFFFFF,
62 .name = "ext pci memory space 0/1",
63 .flags = IORESOURCE_MEM,
64 .parent = &pci_mem_resource_0,
65 .sibling = NULL,
66 .child = &pci_mem_resource_1
67};
68
69static struct resource pci_mem_resource_1 = {
70 .start = 0x1A000000,
71 .end = 0x1FBFFFFF,
72 .name = "ext pci memory space 2/3",
73 .flags = IORESOURCE_MEM,
74 .parent = &pci_mem_resource_0
75};
76
77extern struct pci_ops it8172_pci_ops;
78
79struct pci_controller it8172_controller = {
80 .pci_ops = &it8172_pci_ops,
81 .io_resource = &pci_io_resource,
82 .mem_resource = &pci_mem_resource_0,
83};
84
85static int it8172_pcibios_config_access(unsigned char access_type,
86 struct pci_bus *bus,
87 unsigned int devfn, int where,
88 u32 * data)
89{
90 /*
91 * config cycles are on 4 byte boundary only
92 */
93
94 /* Setup address */
95 IT_WRITE(IT_CONFADDR, (bus->number << IT_BUSNUM_SHF) |
96 (devfn << IT_FUNCNUM_SHF) | (where & ~0x3));
97
98 if (access_type == PCI_ACCESS_WRITE) {
99 IT_WRITE(IT_CONFDATA, *data);
100 } else {
101 IT_READ(IT_CONFDATA, *data);
102 }
103
104 /*
105 * Revisit: check for master or target abort.
106 */
107 return 0;
108}
109
110
111/*
112 * We can't address 8 and 16 bit words directly. Instead we have to
113 * read/write a 32bit word and mask/modify the data we actually want.
114 */
115static write_config(struct pci_bus *bus, unsigned int devfn, int where,
116 int size, u32 val)
117{
118 u32 data = 0;
119
120 switch (size) {
121 case 1:
122 if (it8172_pcibios_config_access
123 (PCI_ACCESS_READ, dev, where, &data))
124 return -1;
125
126 *val = (data >> ((where & 3) << 3)) & 0xff;
127
128 return PCIBIOS_SUCCESSFUL;
129
130 case 2:
131
132 if (where & 1)
133 return PCIBIOS_BAD_REGISTER_NUMBER;
134
135 if (it8172_pcibios_config_access
136 (PCI_ACCESS_READ, dev, where, &data))
137 return -1;
138
139 *val = (data >> ((where & 3) << 3)) & 0xffff;
140 DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n",
141 dev->bus->number, dev->devfn, where, *val);
142
143 return PCIBIOS_SUCCESSFUL;
144
145 case 4:
146
147 if (where & 3)
148 return PCIBIOS_BAD_REGISTER_NUMBER;
149
150 if (it8172_pcibios_config_access
151 (PCI_ACCESS_READ, dev, where, &data))
152 return -1;
153
154 *val = data;
155
156 return PCIBIOS_SUCCESSFUL;
157 }
158}
159
160
161static write_config(struct pci_bus *bus, unsigned int devfn, int where,
162 int size, u32 val)
163{
164 u32 data = 0;
165
166 switch (size) {
167 case 1:
168 if (it8172_pcibios_config_access
169 (PCI_ACCESS_READ, dev, where, &data))
170 return -1;
171
172 data = (data & ~(0xff << ((where & 3) << 3))) |
173 (val << ((where & 3) << 3));
174
175 if (it8172_pcibios_config_access
176 (PCI_ACCESS_WRITE, dev, where, &data))
177 return -1;
178
179 return PCIBIOS_SUCCESSFUL;
180
181 case 2:
182 if (where & 1)
183 return PCIBIOS_BAD_REGISTER_NUMBER;
184
185 if (it8172_pcibios_config_access
186 (PCI_ACCESS_READ, dev, where, &data))
187 eturn - 1;
188
189 data = (data & ~(0xffff << ((where & 3) << 3))) |
190 (val << ((where & 3) << 3));
191
192 if (it8172_pcibios_config_access
193 (PCI_ACCESS_WRITE, dev, where, &data))
194 return -1;
195
196 return PCIBIOS_SUCCESSFUL;
197
198 case 4:
199 if (where & 3)
200 return PCIBIOS_BAD_REGISTER_NUMBER;
201
202 if (it8172_pcibios_config_access
203 (PCI_ACCESS_WRITE, dev, where, &val))
204 return -1;
205
206 return PCIBIOS_SUCCESSFUL;
207 }
208}
209
210struct pci_ops it8172_pci_ops = {
211 .read = read_config,
212 .write = write_config,
213};
diff --git a/drivers/char/.gitignore b/drivers/char/.gitignore
index 73dfdcebfbba..83683a2d8e6a 100644
--- a/drivers/char/.gitignore
+++ b/drivers/char/.gitignore
@@ -1,3 +1,2 @@
1consolemap_deftbl.c 1consolemap_deftbl.c
2defkeymap.c 2defkeymap.c
3qtronixmap.c
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index bde1c665d9f4..0e6f35fcc2eb 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -371,36 +371,6 @@ config AU1000_SERIAL_CONSOLE
371 If you have an Alchemy AU1000 processor (MIPS based) and you want 371 If you have an Alchemy AU1000 processor (MIPS based) and you want
372 to use a console on a serial port, say Y. Otherwise, say N. 372 to use a console on a serial port, say Y. Otherwise, say N.
373 373
374config QTRONIX_KEYBOARD
375 bool "Enable Qtronix 990P Keyboard Support"
376 depends on IT8712
377 help
378 Images of Qtronix keyboards are at
379 <http://www.qtronix.com/keyboard.html>.
380
381config IT8172_CIR
382 bool
383 depends on QTRONIX_KEYBOARD
384 default y
385
386config IT8172_SCR0
387 bool "Enable Smart Card Reader 0 Support "
388 depends on IT8712
389 help
390 Say Y here to support smart-card reader 0 (SCR0) on the Integrated
391 Technology Express, Inc. ITE8172 SBC. Vendor page at
392 <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
393 board at <http://www.mvista.com/partners/semiconductor/ite.html>.
394
395config IT8172_SCR1
396 bool "Enable Smart Card Reader 1 Support "
397 depends on IT8712
398 help
399 Say Y here to support smart-card reader 1 (SCR1) on the Integrated
400 Technology Express, Inc. ITE8172 SBC. Vendor page at
401 <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
402 board at <http://www.mvista.com/partners/semiconductor/ite.html>.
403
404config A2232 374config A2232
405 tristate "Commodore A2232 serial support (EXPERIMENTAL)" 375 tristate "Commodore A2232 serial support (EXPERIMENTAL)"
406 depends on EXPERIMENTAL && ZORRO && BROKEN_ON_SMP 376 depends on EXPERIMENTAL && ZORRO && BROKEN_ON_SMP
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 19114df59bbd..777cad045094 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -102,7 +102,7 @@ obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o
102obj-$(CONFIG_TCG_TPM) += tpm/ 102obj-$(CONFIG_TCG_TPM) += tpm/
103 103
104# Files generated that shall be removed upon make clean 104# Files generated that shall be removed upon make clean
105clean-files := consolemap_deftbl.c defkeymap.c qtronixmap.c 105clean-files := consolemap_deftbl.c defkeymap.c
106 106
107quiet_cmd_conmk = CONMK $@ 107quiet_cmd_conmk = CONMK $@
108 cmd_conmk = scripts/conmakehash $< > $@ 108 cmd_conmk = scripts/conmakehash $< > $@
@@ -112,8 +112,6 @@ $(obj)/consolemap_deftbl.c: $(src)/$(FONTMAPFILE)
112 112
113$(obj)/defkeymap.o: $(obj)/defkeymap.c 113$(obj)/defkeymap.o: $(obj)/defkeymap.c
114 114
115$(obj)/qtronixmap.o: $(obj)/qtronixmap.c
116
117# Uncomment if you're changing the keymap and have an appropriate 115# Uncomment if you're changing the keymap and have an appropriate
118# loadkeys version for the map. By default, we'll use the shipped 116# loadkeys version for the map. By default, we'll use the shipped
119# versions. 117# versions.
@@ -121,7 +119,7 @@ $(obj)/qtronixmap.o: $(obj)/qtronixmap.c
121 119
122ifdef GENERATE_KEYMAP 120ifdef GENERATE_KEYMAP
123 121
124$(obj)/defkeymap.c $(obj)/qtronixmap.c: $(obj)/%.c: $(src)/%.map 122$(obj)/defkeymap.c $(obj)/%.c: $(src)/%.map
125 loadkeys --mktable $< > $@.tmp 123 loadkeys --mktable $< > $@.tmp
126 sed -e 's/^static *//' $@.tmp > $@ 124 sed -e 's/^static *//' $@.tmp > $@
127 rm $@.tmp 125 rm $@.tmp
diff --git a/drivers/char/ite_gpio.c b/drivers/char/ite_gpio.c
deleted file mode 100644
index cde562d70c4f..000000000000
--- a/drivers/char/ite_gpio.c
+++ /dev/null
@@ -1,419 +0,0 @@
1/*
2 * FILE NAME ite_gpio.c
3 *
4 * BRIEF MODULE DESCRIPTION
5 * API for ITE GPIO device.
6 * Driver for ITE GPIO device.
7 *
8 * Author: MontaVista Software, Inc. <source@mvista.com>
9 * Hai-Pao Fan <haipao@mvista.com>
10 *
11 * Copyright 2001 MontaVista Software Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33#include <linux/module.h>
34#include <linux/types.h>
35#include <linux/kernel.h>
36#include <linux/miscdevice.h>
37#include <linux/init.h>
38#include <linux/ioport.h>
39#include <asm/uaccess.h>
40#include <asm/addrspace.h>
41#include <asm/it8172/it8172_int.h>
42#include <linux/sched.h>
43#include <linux/ite_gpio.h>
44
45#define ite_gpio_base 0x14013800
46
47#define ITE_GPADR (*(volatile __u8 *)(0x14013800 + KSEG1))
48#define ITE_GPBDR (*(volatile __u8 *)(0x14013808 + KSEG1))
49#define ITE_GPCDR (*(volatile __u8 *)(0x14013810 + KSEG1))
50#define ITE_GPACR (*(volatile __u16 *)(0x14013802 + KSEG1))
51#define ITE_GPBCR (*(volatile __u16 *)(0x1401380a + KSEG1))
52#define ITE_GPCCR (*(volatile __u16 *)(0x14013812 + KSEG1))
53#define ITE_GPAICR (*(volatile __u16 *)(0x14013804 + KSEG1))
54#define ITE_GPBICR (*(volatile __u16 *)(0x1401380c + KSEG1))
55#define ITE_GPCICR (*(volatile __u16 *)(0x14013814 + KSEG1))
56#define ITE_GPAISR (*(volatile __u8 *)(0x14013806 + KSEG1))
57#define ITE_GPBISR (*(volatile __u8 *)(0x1401380e + KSEG1))
58#define ITE_GPCISR (*(volatile __u8 *)(0x14013816 + KSEG1))
59#define ITE_GCR (*(volatile __u8 *)(0x14013818 + KSEG1))
60
61#define MAX_GPIO_LINE 21
62static int ite_gpio_irq=IT8172_GPIO_IRQ;
63
64static long ite_irq_counter[MAX_GPIO_LINE];
65wait_queue_head_t ite_gpio_wait[MAX_GPIO_LINE];
66static int ite_gpio_irq_pending[MAX_GPIO_LINE];
67
68static int ite_gpio_debug=0;
69#define DEB(x) if (ite_gpio_debug>=1) x
70
71int ite_gpio_in(__u32 device, __u32 mask, volatile __u32 *data)
72{
73 DEB(printk("ite_gpio_in mask=0x%x\n",mask));
74
75 switch (device) {
76 case ITE_GPIO_PORTA:
77 ITE_GPACR = (__u16)mask; /* 0xffff */
78 *data = ITE_GPADR;
79 break;
80 case ITE_GPIO_PORTB:
81 ITE_GPBCR = (__u16)mask; /* 0xffff */
82 *data = ITE_GPBDR;
83 break;
84 case ITE_GPIO_PORTC:
85 ITE_GPCCR = (__u16)mask; /* 0x03ff */
86 *data = ITE_GPCDR;
87 break;
88 default:
89 return -EFAULT;
90 }
91
92 return 0;
93}
94
95
96int ite_gpio_out(__u32 device, __u32 mask, __u32 data)
97{
98 switch (device) {
99 case ITE_GPIO_PORTA:
100 ITE_GPACR = (__u16)mask; /* 0x5555 */
101 ITE_GPADR = (__u8)data;
102 break;
103 case ITE_GPIO_PORTB:
104 ITE_GPBCR = (__u16)mask; /* 0x5555 */
105 ITE_GPBDR = (__u8)data;
106 break;
107 case ITE_GPIO_PORTC:
108 ITE_GPCCR = (__u16)mask; /* 0x0155 */
109 ITE_GPCDR = (__u8)data;
110 break;
111 default:
112 return -EFAULT;
113 }
114
115 return 0;
116}
117
118int ite_gpio_int_ctrl(__u32 device, __u32 mask, __u32 data)
119{
120 switch (device) {
121 case ITE_GPIO_PORTA:
122 ITE_GPAICR = (ITE_GPAICR & ~mask) | (data & mask);
123 break;
124 case ITE_GPIO_PORTB:
125 ITE_GPBICR = (ITE_GPBICR & ~mask) | (data & mask);
126 break;
127 case ITE_GPIO_PORTC:
128 ITE_GPCICR = (ITE_GPCICR & ~mask) | (data & mask);
129 break;
130 default:
131 return -EFAULT;
132 }
133
134 return 0;
135}
136
137int ite_gpio_in_status(__u32 device, __u32 mask, volatile __u32 *data)
138{
139 int ret=-1;
140
141 if ((MAX_GPIO_LINE > *data) && (*data >= 0))
142 ret=ite_gpio_irq_pending[*data];
143
144 DEB(printk("ite_gpio_in_status %d ret=%d\n",*data, ret));
145
146 switch (device) {
147 case ITE_GPIO_PORTA:
148 *data = ITE_GPAISR & mask;
149 break;
150 case ITE_GPIO_PORTB:
151 *data = ITE_GPBISR & mask;
152 break;
153 case ITE_GPIO_PORTC:
154 *data = ITE_GPCISR & mask;
155 break;
156 default:
157 return -EFAULT;
158 }
159
160 return ret;
161}
162
163int ite_gpio_out_status(__u32 device, __u32 mask, __u32 data)
164{
165 switch (device) {
166 case ITE_GPIO_PORTA:
167 ITE_GPAISR = (ITE_GPAISR & ~mask) | (data & mask);
168 break;
169 case ITE_GPIO_PORTB:
170 ITE_GPBISR = (ITE_GPBISR & ~mask) | (data & mask);
171 break;
172 case ITE_GPIO_PORTC:
173 ITE_GPCISR = (ITE_GPCISR & ~mask) | (data & mask);
174 break;
175 default:
176 return -EFAULT;
177 }
178
179 return 0;
180}
181
182int ite_gpio_gen_ctrl(__u32 device, __u32 mask, __u32 data)
183{
184 ITE_GCR = (ITE_GCR & ~mask) | (data & mask);
185
186 return 0;
187}
188
189int ite_gpio_int_wait (__u32 device, __u32 mask, __u32 data)
190{
191 int i,line=0, ret=0;
192 unsigned long flags;
193
194 switch (device) {
195 case ITE_GPIO_PORTA:
196 line = data & mask;
197 break;
198 case ITE_GPIO_PORTB:
199 line = (data & mask) <<8;
200 break;
201 case ITE_GPIO_PORTC:
202 line = (data & mask) <<16;
203 break;
204 }
205 for (i=MAX_GPIO_LINE-1; i >= 0; i--) {
206 if ( (line) & (1 << i))
207 break;
208 }
209
210 DEB(printk("wait device=0x%d mask=0x%x data=0x%x index %d\n",
211 device, mask, data, i));
212
213 if (line & ~(1<<i))
214 return -EFAULT;
215
216 if (ite_gpio_irq_pending[i]==1)
217 return -EFAULT;
218
219 save_flags (flags);
220 cli();
221 ite_gpio_irq_pending[i] = 1;
222 ret = interruptible_sleep_on_timeout(&ite_gpio_wait[i], 3*HZ);
223 restore_flags (flags);
224 ite_gpio_irq_pending[i] = 0;
225
226 return ret;
227}
228
229EXPORT_SYMBOL(ite_gpio_in);
230EXPORT_SYMBOL(ite_gpio_out);
231EXPORT_SYMBOL(ite_gpio_int_ctrl);
232EXPORT_SYMBOL(ite_gpio_in_status);
233EXPORT_SYMBOL(ite_gpio_out_status);
234EXPORT_SYMBOL(ite_gpio_gen_ctrl);
235EXPORT_SYMBOL(ite_gpio_int_wait);
236
237static int ite_gpio_open(struct inode *inode, struct file *file)
238{
239 return 0;
240}
241
242
243static int ite_gpio_release(struct inode *inode, struct file *file)
244{
245 return 0;
246}
247
248
249static int ite_gpio_ioctl(struct inode *inode, struct file *file,
250 unsigned int cmd, unsigned long arg)
251{
252 static struct ite_gpio_ioctl_data ioctl_data;
253
254 if (copy_from_user(&ioctl_data, (struct ite_gpio_ioctl_data *)arg,
255 sizeof(ioctl_data)))
256 return -EFAULT;
257 if ((ioctl_data.device < ITE_GPIO_PORTA) ||
258 (ioctl_data.device > ITE_GPIO_PORTC) )
259 return -EFAULT;
260
261 switch(cmd) {
262 case ITE_GPIO_IN:
263 if (ite_gpio_in(ioctl_data.device, ioctl_data.mask,
264 &ioctl_data.data))
265 return -EFAULT;
266
267 if (copy_to_user((struct ite_gpio_ioctl_data *)arg,
268 &ioctl_data, sizeof(ioctl_data)))
269 return -EFAULT;
270 break;
271
272 case ITE_GPIO_OUT:
273 return ite_gpio_out(ioctl_data.device,
274 ioctl_data.mask, ioctl_data.data);
275 break;
276
277 case ITE_GPIO_INT_CTRL:
278 return ite_gpio_int_ctrl(ioctl_data.device,
279 ioctl_data.mask, ioctl_data.data);
280 break;
281
282 case ITE_GPIO_IN_STATUS:
283 if (ite_gpio_in_status(ioctl_data.device, ioctl_data.mask,
284 &ioctl_data.data))
285 return -EFAULT;
286 if (copy_to_user((struct ite_gpio_ioctl_data *)arg,
287 &ioctl_data, sizeof(ioctl_data)))
288 return -EFAULT;
289 break;
290
291 case ITE_GPIO_OUT_STATUS:
292 return ite_gpio_out_status(ioctl_data.device,
293 ioctl_data.mask, ioctl_data.data);
294 break;
295
296 case ITE_GPIO_GEN_CTRL:
297 return ite_gpio_gen_ctrl(ioctl_data.device,
298 ioctl_data.mask, ioctl_data.data);
299 break;
300
301 case ITE_GPIO_INT_WAIT:
302 return ite_gpio_int_wait(ioctl_data.device,
303 ioctl_data.mask, ioctl_data.data);
304 break;
305
306 default:
307 return -ENOIOCTLCMD;
308
309 }
310
311 return 0;
312}
313
314static void ite_gpio_irq_handler(int this_irq, void *dev_id,
315 struct pt_regs *regs)
316{
317 int i,line;
318
319 line = ITE_GPCISR & 0x1f;
320 for (i=4; i >=0; i--) {
321 if ( line & (1 << i)) {
322 ++ite_irq_counter[i+16];
323 ite_gpio_irq_pending[i+16] = 2;
324 wake_up_interruptible(&ite_gpio_wait[i+16]);
325
326DEB(printk("interrupt 0x%x %d\n", &ite_gpio_wait[i+16], i+16));
327
328 ITE_GPCISR = ITE_GPCISR & (1<<i);
329 return;
330 }
331 }
332 line = ITE_GPBISR;
333 for (i=7; i >= 0; i--) {
334 if ( line & (1 << i)) {
335 ++ite_irq_counter[i+8];
336 ite_gpio_irq_pending[i+8] = 2;
337 wake_up_interruptible(&ite_gpio_wait[i+8]);
338
339DEB(printk("interrupt 0x%x %d\n",ITE_GPBISR, i+8));
340
341 ITE_GPBISR = ITE_GPBISR & (1<<i);
342 return;
343 }
344 }
345 line = ITE_GPAISR;
346 for (i=7; i >= 0; i--) {
347 if ( line & (1 << i)) {
348 ++ite_irq_counter[i];
349 ite_gpio_irq_pending[i] = 2;
350 wake_up_interruptible(&ite_gpio_wait[i]);
351
352DEB(printk("interrupt 0x%x %d\n",ITE_GPAISR, i));
353
354 ITE_GPAISR = ITE_GPAISR & (1<<i);
355 return;
356 }
357 }
358}
359
360static const struct file_operations ite_gpio_fops = {
361 .owner = THIS_MODULE,
362 .ioctl = ite_gpio_ioctl,
363 .open = ite_gpio_open,
364 .release = ite_gpio_release,
365};
366
367static struct miscdevice ite_gpio_miscdev = {
368 MISC_DYNAMIC_MINOR,
369 "ite_gpio",
370 &ite_gpio_fops
371};
372
373int __init ite_gpio_init(void)
374{
375 int i;
376
377 if (misc_register(&ite_gpio_miscdev))
378 return -ENODEV;
379
380 if (!request_region(ite_gpio_base, 0x1c, "ITE GPIO"))
381 {
382 misc_deregister(&ite_gpio_miscdev);
383 return -EIO;
384 }
385
386 /* initialize registers */
387 ITE_GPACR = 0xffff;
388 ITE_GPBCR = 0xffff;
389 ITE_GPCCR = 0xffff;
390 ITE_GPAICR = 0x00ff;
391 ITE_GPBICR = 0x00ff;
392 ITE_GPCICR = 0x00ff;
393 ITE_GCR = 0;
394
395 for (i = 0; i < MAX_GPIO_LINE; i++) {
396 ite_gpio_irq_pending[i]=0;
397 init_waitqueue_head(&ite_gpio_wait[i]);
398 }
399
400 if (request_irq(ite_gpio_irq, ite_gpio_irq_handler, IRQF_SHARED, "gpio", 0) < 0) {
401 misc_deregister(&ite_gpio_miscdev);
402 release_region(ite_gpio_base, 0x1c);
403 return 0;
404 }
405
406 printk("GPIO at 0x%x (irq = %d)\n", ite_gpio_base, ite_gpio_irq);
407
408 return 0;
409}
410
411static void __exit ite_gpio_exit(void)
412{
413 misc_deregister(&ite_gpio_miscdev);
414}
415
416module_init(ite_gpio_init);
417module_exit(ite_gpio_exit);
418
419MODULE_LICENSE("GPL");
diff --git a/drivers/char/qtronixmap.c_shipped b/drivers/char/qtronixmap.c_shipped
deleted file mode 100644
index 1e2b92b7d57a..000000000000
--- a/drivers/char/qtronixmap.c_shipped
+++ /dev/null
@@ -1,265 +0,0 @@
1
2/* Do not edit this file! It was automatically generated by */
3/* loadkeys --mktable defkeymap.map > defkeymap.c */
4
5#include <linux/types.h>
6#include <linux/keyboard.h>
7#include <linux/kd.h>
8
9u_short plain_map[NR_KEYS] = {
10 0xf200, 0xf060, 0xf031, 0xf032, 0xf033, 0xf034, 0xf035, 0xf036,
11 0xf037, 0xf038, 0xf039, 0xf030, 0xf02d, 0xf03d, 0xf200, 0xf07f,
12 0xf009, 0xfb71, 0xfb77, 0xfb65, 0xfb72, 0xfb74, 0xfb79, 0xfb75,
13 0xfb69, 0xfb6f, 0xfb70, 0xf05b, 0xf05d, 0xf05c, 0xf207, 0xfb61,
14 0xfb73, 0xfb64, 0xfb66, 0xfb67, 0xfb68, 0xfb6a, 0xfb6b, 0xfb6c,
15 0xf03b, 0xf027, 0xf060, 0xf201, 0xf700, 0xf200, 0xfb7a, 0xfb78,
16 0xfb63, 0xfb76, 0xfb62, 0xfb6e, 0xfb6d, 0xf02c, 0xf02e, 0xf02f,
17 0xf200, 0xf700, 0xf702, 0xf200, 0xf703, 0xf020, 0xf703, 0xf200,
18 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
19 0xf200, 0xf200, 0xf200, 0xf115, 0xf07f, 0xf200, 0xf200, 0xf601,
20 0xf200, 0xf200, 0xf200, 0xf603, 0xf600, 0xf118, 0xf119, 0xf200,
21 0xf200, 0xf602, 0xf208, 0xf02d, 0xf02b, 0xf30c, 0xf02e, 0xf30d,
22 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
23 0xf200, 0xf200, 0xf200, 0xf117, 0xf600, 0xf200, 0xf01b, 0xf200,
24 0xf100, 0xf101, 0xf102, 0xf103, 0xf104, 0xf105, 0xf106, 0xf107,
25 0xf108, 0xf109, 0xf200, 0xf200, 0xf200, 0xf200, 0xf11d, 0xf200,
26};
27
28u_short shift_map[NR_KEYS] = {
29 0xf200, 0xf07e, 0xf021, 0xf040, 0xf023, 0xf024, 0xf025, 0xf05e,
30 0xf026, 0xf02a, 0xf028, 0xf029, 0xf05f, 0xf02b, 0xf200, 0xf07f,
31 0xf009, 0xfb51, 0xfb57, 0xfb45, 0xfb52, 0xfb54, 0xfb59, 0xfb55,
32 0xfb49, 0xfb4f, 0xfb50, 0xf07b, 0xf07d, 0xf07c, 0xf207, 0xfb41,
33 0xfb53, 0xfb44, 0xfb46, 0xfb47, 0xfb48, 0xfb4a, 0xfb4b, 0xfb4c,
34 0xf03a, 0xf022, 0xf07e, 0xf201, 0xf700, 0xf200, 0xfb5a, 0xfb58,
35 0xfb43, 0xfb56, 0xfb42, 0xfb4e, 0xfb4d, 0xf03c, 0xf03e, 0xf03f,
36 0xf200, 0xf700, 0xf702, 0xf200, 0xf703, 0xf020, 0xf703, 0xf200,
37 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
38 0xf200, 0xf200, 0xf200, 0xf115, 0xf07f, 0xf200, 0xf200, 0xf601,
39 0xf200, 0xf200, 0xf200, 0xf603, 0xf600, 0xf20b, 0xf20a, 0xf200,
40 0xf200, 0xf602, 0xf213, 0xf02d, 0xf02b, 0xf30c, 0xf02e, 0xf30d,
41 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
42 0xf200, 0xf200, 0xf200, 0xf117, 0xf600, 0xf200, 0xf01b, 0xf200,
43 0xf10a, 0xf10b, 0xf10c, 0xf10d, 0xf10e, 0xf10f, 0xf110, 0xf111,
44 0xf112, 0xf113, 0xf200, 0xf200, 0xf200, 0xf200, 0xf11d, 0xf200,
45};
46
47u_short altgr_map[NR_KEYS] = {
48 0xf200, 0xf200, 0xf200, 0xf040, 0xf200, 0xf024, 0xf200, 0xf200,
49 0xf07b, 0xf05b, 0xf05d, 0xf07d, 0xf05c, 0xf200, 0xf200, 0xf200,
50 0xf200, 0xfb71, 0xfb77, 0xfb65, 0xfb72, 0xfb74, 0xfb79, 0xfb75,
51 0xfb69, 0xfb6f, 0xfb70, 0xf200, 0xf200, 0xf200, 0xf207, 0xfb61,
52 0xfb73, 0xfb64, 0xfb66, 0xfb67, 0xfb68, 0xfb6a, 0xfb6b, 0xfb6c,
53 0xf200, 0xf200, 0xf200, 0xf201, 0xf700, 0xf200, 0xfb7a, 0xfb78,
54 0xfb63, 0xfb76, 0xfb62, 0xfb6e, 0xfb6d, 0xf200, 0xf200, 0xf200,
55 0xf200, 0xf700, 0xf702, 0xf200, 0xf703, 0xf200, 0xf703, 0xf200,
56 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
57 0xf200, 0xf200, 0xf200, 0xf115, 0xf07f, 0xf200, 0xf200, 0xf601,
58 0xf200, 0xf200, 0xf200, 0xf603, 0xf600, 0xf118, 0xf119, 0xf200,
59 0xf200, 0xf602, 0xf208, 0xf02d, 0xf02b, 0xf30c, 0xf02e, 0xf30d,
60 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
61 0xf200, 0xf200, 0xf200, 0xf117, 0xf600, 0xf200, 0xf200, 0xf200,
62 0xf50c, 0xf50d, 0xf50e, 0xf50f, 0xf510, 0xf511, 0xf512, 0xf513,
63 0xf514, 0xf515, 0xf200, 0xf200, 0xf200, 0xf200, 0xf11d, 0xf200,
64};
65
66u_short ctrl_map[NR_KEYS] = {
67 0xf200, 0xf200, 0xf200, 0xf000, 0xf01b, 0xf01c, 0xf01d, 0xf01e,
68 0xf01f, 0xf07f, 0xf200, 0xf200, 0xf01f, 0xf200, 0xf200, 0xf008,
69 0xf200, 0xf011, 0xf017, 0xf005, 0xf012, 0xf014, 0xf019, 0xf015,
70 0xf009, 0xf00f, 0xf010, 0xf01b, 0xf01d, 0xf01c, 0xf207, 0xf001,
71 0xf013, 0xf004, 0xf006, 0xf007, 0xf008, 0xf00a, 0xf00b, 0xf00c,
72 0xf007, 0xf000, 0xf200, 0xf201, 0xf700, 0xf200, 0xf01a, 0xf018,
73 0xf003, 0xf016, 0xf002, 0xf00e, 0xf20e, 0xf07f, 0xf200, 0xf200,
74 0xf200, 0xf700, 0xf702, 0xf200, 0xf703, 0xf000, 0xf703, 0xf200,
75 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
76 0xf200, 0xf200, 0xf200, 0xf115, 0xf07f, 0xf200, 0xf200, 0xf601,
77 0xf200, 0xf200, 0xf200, 0xf603, 0xf600, 0xf118, 0xf119, 0xf200,
78 0xf200, 0xf602, 0xf208, 0xf02d, 0xf02b, 0xf30c, 0xf02e, 0xf30d,
79 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
80 0xf200, 0xf200, 0xf200, 0xf117, 0xf600, 0xf200, 0xf200, 0xf200,
81 0xf100, 0xf101, 0xf102, 0xf103, 0xf104, 0xf105, 0xf106, 0xf107,
82 0xf108, 0xf109, 0xf200, 0xf200, 0xf200, 0xf200, 0xf11d, 0xf200,
83};
84
85u_short shift_ctrl_map[NR_KEYS] = {
86 0xf200, 0xf200, 0xf200, 0xf000, 0xf200, 0xf200, 0xf200, 0xf200,
87 0xf200, 0xf200, 0xf200, 0xf200, 0xf01f, 0xf200, 0xf200, 0xf200,
88 0xf200, 0xf011, 0xf017, 0xf005, 0xf012, 0xf014, 0xf019, 0xf015,
89 0xf009, 0xf00f, 0xf010, 0xf200, 0xf200, 0xf200, 0xf207, 0xf001,
90 0xf013, 0xf004, 0xf006, 0xf007, 0xf008, 0xf00a, 0xf00b, 0xf00c,
91 0xf200, 0xf200, 0xf200, 0xf201, 0xf700, 0xf200, 0xf01a, 0xf018,
92 0xf003, 0xf016, 0xf002, 0xf00e, 0xf00d, 0xf200, 0xf200, 0xf200,
93 0xf200, 0xf700, 0xf702, 0xf200, 0xf703, 0xf200, 0xf703, 0xf200,
94 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
95 0xf200, 0xf200, 0xf200, 0xf115, 0xf07f, 0xf200, 0xf200, 0xf601,
96 0xf200, 0xf200, 0xf200, 0xf603, 0xf600, 0xf118, 0xf119, 0xf200,
97 0xf200, 0xf602, 0xf208, 0xf02d, 0xf02b, 0xf30c, 0xf02e, 0xf30d,
98 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
99 0xf200, 0xf200, 0xf200, 0xf117, 0xf600, 0xf200, 0xf200, 0xf200,
100 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
101 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf11d, 0xf200,
102};
103
104u_short alt_map[NR_KEYS] = {
105 0xf200, 0xf81b, 0xf831, 0xf832, 0xf833, 0xf834, 0xf835, 0xf836,
106 0xf837, 0xf838, 0xf839, 0xf830, 0xf82d, 0xf83d, 0xf200, 0xf87f,
107 0xf809, 0xf871, 0xf877, 0xf865, 0xf872, 0xf874, 0xf879, 0xf875,
108 0xf869, 0xf86f, 0xf870, 0xf85b, 0xf85d, 0xf85c, 0xf207, 0xf861,
109 0xf873, 0xf864, 0xf866, 0xf867, 0xf868, 0xf86a, 0xf86b, 0xf83b,
110 0xf827, 0xf860, 0xf200, 0xf80d, 0xf700, 0xf200, 0xf87a, 0xf878,
111 0xf863, 0xf876, 0xf862, 0xf82c, 0xf82e, 0xf82f, 0xf200, 0xf200,
112 0xf200, 0xf700, 0xf702, 0xf200, 0xf703, 0xf820, 0xf703, 0xf200,
113 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
114 0xf200, 0xf200, 0xf200, 0xf115, 0xf07f, 0xf200, 0xf200, 0xf210,
115 0xf200, 0xf200, 0xf200, 0xf603, 0xf600, 0xf118, 0xf119, 0xf200,
116 0xf200, 0xf211, 0xf208, 0xf02d, 0xf02b, 0xf30c, 0xf02e, 0xf30d,
117 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
118 0xf200, 0xf200, 0xf200, 0xf117, 0xf600, 0xf200, 0xf200, 0xf200,
119 0xf500, 0xf501, 0xf502, 0xf503, 0xf504, 0xf505, 0xf506, 0xf507,
120 0xf508, 0xf509, 0xf200, 0xf200, 0xf200, 0xf200, 0xf11d, 0xf200,
121};
122
123u_short ctrl_alt_map[NR_KEYS] = {
124 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
125 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
126 0xf200, 0xf811, 0xf817, 0xf805, 0xf812, 0xf814, 0xf819, 0xf815,
127 0xf809, 0xf80f, 0xf810, 0xf200, 0xf200, 0xf200, 0xf207, 0xf801,
128 0xf813, 0xf804, 0xf806, 0xf807, 0xf808, 0xf80a, 0xf80b, 0xf80c,
129 0xf200, 0xf200, 0xf200, 0xf201, 0xf700, 0xf200, 0xf81a, 0xf818,
130 0xf803, 0xf816, 0xf802, 0xf80e, 0xf80d, 0xf200, 0xf200, 0xf200,
131 0xf200, 0xf700, 0xf702, 0xf200, 0xf703, 0xf200, 0xf703, 0xf200,
132 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
133 0xf200, 0xf200, 0xf200, 0xf115, 0xf07f, 0xf200, 0xf200, 0xf601,
134 0xf200, 0xf200, 0xf200, 0xf603, 0xf600, 0xf118, 0xf119, 0xf200,
135 0xf200, 0xf602, 0xf208, 0xf02d, 0xf02b, 0xf30c, 0xf02e, 0xf30d,
136 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
137 0xf200, 0xf200, 0xf200, 0xf117, 0xf600, 0xf200, 0xf200, 0xf200,
138 0xf500, 0xf501, 0xf502, 0xf503, 0xf504, 0xf505, 0xf506, 0xf507,
139 0xf508, 0xf509, 0xf200, 0xf200, 0xf200, 0xf200, 0xf11d, 0xf200,
140};
141
142ushort *key_maps[MAX_NR_KEYMAPS] = {
143 plain_map, shift_map, altgr_map, 0,
144 ctrl_map, shift_ctrl_map, 0, 0,
145 alt_map, 0, 0, 0,
146 ctrl_alt_map, 0
147};
148
149unsigned int keymap_count = 7;
150
151
152/*
153 * Philosophy: most people do not define more strings, but they who do
154 * often want quite a lot of string space. So, we statically allocate
155 * the default and allocate dynamically in chunks of 512 bytes.
156 */
157
158char func_buf[] = {
159 '\033', '[', '[', 'A', 0,
160 '\033', '[', '[', 'B', 0,
161 '\033', '[', '[', 'C', 0,
162 '\033', '[', '[', 'D', 0,
163 '\033', '[', '[', 'E', 0,
164 '\033', '[', '1', '7', '~', 0,
165 '\033', '[', '1', '8', '~', 0,
166 '\033', '[', '1', '9', '~', 0,
167 '\033', '[', '2', '0', '~', 0,
168 '\033', '[', '2', '1', '~', 0,
169 '\033', '[', '2', '3', '~', 0,
170 '\033', '[', '2', '4', '~', 0,
171 '\033', '[', '2', '5', '~', 0,
172 '\033', '[', '2', '6', '~', 0,
173 '\033', '[', '2', '8', '~', 0,
174 '\033', '[', '2', '9', '~', 0,
175 '\033', '[', '3', '1', '~', 0,
176 '\033', '[', '3', '2', '~', 0,
177 '\033', '[', '3', '3', '~', 0,
178 '\033', '[', '3', '4', '~', 0,
179 '\033', '[', '1', '~', 0,
180 '\033', '[', '2', '~', 0,
181 '\033', '[', '3', '~', 0,
182 '\033', '[', '4', '~', 0,
183 '\033', '[', '5', '~', 0,
184 '\033', '[', '6', '~', 0,
185 '\033', '[', 'M', 0,
186 '\033', '[', 'P', 0,
187};
188
189
190char *funcbufptr = func_buf;
191int funcbufsize = sizeof(func_buf);
192int funcbufleft = 0; /* space left */
193
194char *func_table[MAX_NR_FUNC] = {
195 func_buf + 0,
196 func_buf + 5,
197 func_buf + 10,
198 func_buf + 15,
199 func_buf + 20,
200 func_buf + 25,
201 func_buf + 31,
202 func_buf + 37,
203 func_buf + 43,
204 func_buf + 49,
205 func_buf + 55,
206 func_buf + 61,
207 func_buf + 67,
208 func_buf + 73,
209 func_buf + 79,
210 func_buf + 85,
211 func_buf + 91,
212 func_buf + 97,
213 func_buf + 103,
214 func_buf + 109,
215 func_buf + 115,
216 func_buf + 120,
217 func_buf + 125,
218 func_buf + 130,
219 func_buf + 135,
220 func_buf + 140,
221 func_buf + 145,
222 0,
223 0,
224 func_buf + 149,
225 0,
226};
227
228struct kbdiacr accent_table[MAX_DIACR] = {
229 {'`', 'A', 'À'}, {'`', 'a', 'à'},
230 {'\'', 'A', 'Á'}, {'\'', 'a', 'á'},
231 {'^', 'A', 'Â'}, {'^', 'a', 'â'},
232 {'~', 'A', 'Ã'}, {'~', 'a', 'ã'},
233 {'"', 'A', 'Ä'}, {'"', 'a', 'ä'},
234 {'O', 'A', 'Å'}, {'o', 'a', 'å'},
235 {'0', 'A', 'Å'}, {'0', 'a', 'å'},
236 {'A', 'A', 'Å'}, {'a', 'a', 'å'},
237 {'A', 'E', 'Æ'}, {'a', 'e', 'æ'},
238 {',', 'C', 'Ç'}, {',', 'c', 'ç'},
239 {'`', 'E', 'È'}, {'`', 'e', 'è'},
240 {'\'', 'E', 'É'}, {'\'', 'e', 'é'},
241 {'^', 'E', 'Ê'}, {'^', 'e', 'ê'},
242 {'"', 'E', 'Ë'}, {'"', 'e', 'ë'},
243 {'`', 'I', 'Ì'}, {'`', 'i', 'ì'},
244 {'\'', 'I', 'Í'}, {'\'', 'i', 'í'},
245 {'^', 'I', 'Î'}, {'^', 'i', 'î'},
246 {'"', 'I', 'Ï'}, {'"', 'i', 'ï'},
247 {'-', 'D', 'Ð'}, {'-', 'd', 'ð'},
248 {'~', 'N', 'Ñ'}, {'~', 'n', 'ñ'},
249 {'`', 'O', 'Ò'}, {'`', 'o', 'ò'},
250 {'\'', 'O', 'Ó'}, {'\'', 'o', 'ó'},
251 {'^', 'O', 'Ô'}, {'^', 'o', 'ô'},
252 {'~', 'O', 'Õ'}, {'~', 'o', 'õ'},
253 {'"', 'O', 'Ö'}, {'"', 'o', 'ö'},
254 {'/', 'O', 'Ø'}, {'/', 'o', 'ø'},
255 {'`', 'U', 'Ù'}, {'`', 'u', 'ù'},
256 {'\'', 'U', 'Ú'}, {'\'', 'u', 'ú'},
257 {'^', 'U', 'Û'}, {'^', 'u', 'û'},
258 {'"', 'U', 'Ü'}, {'"', 'u', 'ü'},
259 {'\'', 'Y', 'Ý'}, {'\'', 'y', 'ý'},
260 {'T', 'H', 'Þ'}, {'t', 'h', 'þ'},
261 {'s', 's', 'ß'}, {'"', 'y', 'ÿ'},
262 {'s', 'z', 'ß'}, {'i', 'j', 'ÿ'},
263};
264
265unsigned int accent_table_size = 68;
diff --git a/drivers/char/qtronixmap.map b/drivers/char/qtronixmap.map
deleted file mode 100644
index 8d1ff5c1e281..000000000000
--- a/drivers/char/qtronixmap.map
+++ /dev/null
@@ -1,287 +0,0 @@
1# Default kernel keymap. This uses 7 modifier combinations.
2keymaps 0-2,4-5,8,12
3# Change the above line into
4# keymaps 0-2,4-6,8,12
5# in case you want the entries
6# altgr control keycode 83 = Boot
7# altgr control keycode 111 = Boot
8# below.
9#
10# In fact AltGr is used very little, and one more keymap can
11# be saved by mapping AltGr to Alt (and adapting a few entries):
12# keycode 100 = Alt
13#
14keycode 1 = grave asciitilde
15 alt keycode 1 = Meta_Escape
16keycode 2 = one exclam
17 alt keycode 2 = Meta_one
18keycode 3 = two at at
19 control keycode 3 = nul
20 shift control keycode 3 = nul
21 alt keycode 3 = Meta_two
22keycode 4 = three numbersign
23 control keycode 4 = Escape
24 alt keycode 4 = Meta_three
25keycode 5 = four dollar dollar
26 control keycode 5 = Control_backslash
27 alt keycode 5 = Meta_four
28keycode 6 = five percent
29 control keycode 6 = Control_bracketright
30 alt keycode 6 = Meta_five
31keycode 7 = six asciicircum
32 control keycode 7 = Control_asciicircum
33 alt keycode 7 = Meta_six
34keycode 8 = seven ampersand braceleft
35 control keycode 8 = Control_underscore
36 alt keycode 8 = Meta_seven
37keycode 9 = eight asterisk bracketleft
38 control keycode 9 = Delete
39 alt keycode 9 = Meta_eight
40keycode 10 = nine parenleft bracketright
41 alt keycode 10 = Meta_nine
42keycode 11 = zero parenright braceright
43 alt keycode 11 = Meta_zero
44keycode 12 = minus underscore backslash
45 control keycode 12 = Control_underscore
46 shift control keycode 12 = Control_underscore
47 alt keycode 12 = Meta_minus
48keycode 13 = equal plus
49 alt keycode 13 = Meta_equal
50keycode 15 = Delete Delete
51 control keycode 15 = BackSpace
52 alt keycode 15 = Meta_Delete
53keycode 16 = Tab Tab
54 alt keycode 16 = Meta_Tab
55keycode 17 = q
56keycode 18 = w
57keycode 19 = e
58keycode 20 = r
59keycode 21 = t
60keycode 22 = y
61keycode 23 = u
62keycode 24 = i
63keycode 25 = o
64keycode 26 = p
65keycode 27 = bracketleft braceleft
66 control keycode 27 = Escape
67 alt keycode 27 = Meta_bracketleft
68keycode 28 = bracketright braceright
69 control keycode 28 = Control_bracketright
70 alt keycode 28 = Meta_bracketright
71keycode 29 = backslash bar
72 control keycode 29 = Control_backslash
73 alt keycode 29 = Meta_backslash
74keycode 30 = Caps_Lock
75keycode 31 = a
76keycode 32 = s
77keycode 33 = d
78keycode 34 = f
79keycode 35 = g
80keycode 36 = h
81keycode 37 = j
82keycode 38 = k
83keycode 39 = l
84keycode 40 = semicolon colon
85 alt keycode 39 = Meta_semicolon
86keycode 41 = apostrophe quotedbl
87 control keycode 40 = Control_g
88 alt keycode 40 = Meta_apostrophe
89keycode 42 = grave asciitilde
90 control keycode 41 = nul
91 alt keycode 41 = Meta_grave
92keycode 43 = Return
93 alt keycode 43 = Meta_Control_m
94keycode 44 = Shift
95keycode 46 = z
96keycode 47 = x
97keycode 48 = c
98keycode 49 = v
99keycode 50 = b
100keycode 51 = n
101keycode 52 = m
102keycode 53 = comma less
103 alt keycode 51 = Meta_comma
104keycode 54 = period greater
105 control keycode 52 = Compose
106 alt keycode 52 = Meta_period
107keycode 55 = slash question
108 control keycode 53 = Delete
109 alt keycode 53 = Meta_slash
110keycode 57 = Shift
111keycode 58 = Control
112keycode 60 = Alt
113keycode 61 = space space
114 control keycode 61 = nul
115 alt keycode 61 = Meta_space
116keycode 62 = Alt
117
118keycode 75 = Insert
119keycode 76 = Delete
120
121keycode 83 = Up
122keycode 84 = Down
123
124keycode 85 = Prior
125 shift keycode 85 = Scroll_Backward
126keycode 86 = Next
127 shift keycode 86 = Scroll_Forward
128keycode 89 = Right
129 alt keycode 89 = Incr_Console
130keycode 79 = Left
131 alt keycode 79 = Decr_Console
132
133keycode 90 = Num_Lock
134 shift keycode 90 = Bare_Num_Lock
135
136keycode 91 = minus
137keycode 92 = plus
138keycode 93 = KP_Multiply
139keycode 94 = period
140keycode 95 = KP_Divide
141
142keycode 107 = Select
143keycode 108 = Down
144
145keycode 110 = Escape Escape
146 alt keycode 1 = Meta_Escape
147
148keycode 112 = F1 F11 Console_13
149 control keycode 112 = F1
150 alt keycode 112 = Console_1
151 control alt keycode 112 = Console_1
152keycode 113 = F2 F12 Console_14
153 control keycode 113 = F2
154 alt keycode 113 = Console_2
155 control alt keycode 113 = Console_2
156keycode 114 = F3 F13 Console_15
157 control keycode 114 = F3
158 alt keycode 114 = Console_3
159 control alt keycode 114 = Console_3
160keycode 115 = F4 F14 Console_16
161 control keycode 115 = F4
162 alt keycode 115 = Console_4
163 control alt keycode 115 = Console_4
164keycode 116 = F5 F15 Console_17
165 control keycode 116 = F5
166 alt keycode 116 = Console_5
167 control alt keycode 116 = Console_5
168keycode 117 = F6 F16 Console_18
169 control keycode 117 = F6
170 alt keycode 117 = Console_6
171 control alt keycode 117 = Console_6
172keycode 118 = F7 F17 Console_19
173 control keycode 118 = F7
174 alt keycode 118 = Console_7
175 control alt keycode 118 = Console_7
176keycode 119 = F8 F18 Console_20
177 control keycode 119 = F8
178 alt keycode 119 = Console_8
179 control alt keycode 119 = Console_8
180keycode 120 = F9 F19 Console_21
181 control keycode 120 = F9
182 alt keycode 120 = Console_9
183 control alt keycode 120 = Console_9
184keycode 121 = F10 F20 Console_22
185 control keycode 121 = F10
186 alt keycode 121 = Console_10
187 control alt keycode 121 = Console_10
188
189keycode 126 = Pause
190
191
192string F1 = "\033[[A"
193string F2 = "\033[[B"
194string F3 = "\033[[C"
195string F4 = "\033[[D"
196string F5 = "\033[[E"
197string F6 = "\033[17~"
198string F7 = "\033[18~"
199string F8 = "\033[19~"
200string F9 = "\033[20~"
201string F10 = "\033[21~"
202string F11 = "\033[23~"
203string F12 = "\033[24~"
204string F13 = "\033[25~"
205string F14 = "\033[26~"
206string F15 = "\033[28~"
207string F16 = "\033[29~"
208string F17 = "\033[31~"
209string F18 = "\033[32~"
210string F19 = "\033[33~"
211string F20 = "\033[34~"
212string Find = "\033[1~"
213string Insert = "\033[2~"
214string Remove = "\033[3~"
215string Select = "\033[4~"
216string Prior = "\033[5~"
217string Next = "\033[6~"
218string Macro = "\033[M"
219string Pause = "\033[P"
220compose '`' 'A' to 'À'
221compose '`' 'a' to 'à'
222compose '\'' 'A' to 'Á'
223compose '\'' 'a' to 'á'
224compose '^' 'A' to 'Â'
225compose '^' 'a' to 'â'
226compose '~' 'A' to 'Ã'
227compose '~' 'a' to 'ã'
228compose '"' 'A' to 'Ä'
229compose '"' 'a' to 'ä'
230compose 'O' 'A' to 'Å'
231compose 'o' 'a' to 'å'
232compose '0' 'A' to 'Å'
233compose '0' 'a' to 'å'
234compose 'A' 'A' to 'Å'
235compose 'a' 'a' to 'å'
236compose 'A' 'E' to 'Æ'
237compose 'a' 'e' to 'æ'
238compose ',' 'C' to 'Ç'
239compose ',' 'c' to 'ç'
240compose '`' 'E' to 'È'
241compose '`' 'e' to 'è'
242compose '\'' 'E' to 'É'
243compose '\'' 'e' to 'é'
244compose '^' 'E' to 'Ê'
245compose '^' 'e' to 'ê'
246compose '"' 'E' to 'Ë'
247compose '"' 'e' to 'ë'
248compose '`' 'I' to 'Ì'
249compose '`' 'i' to 'ì'
250compose '\'' 'I' to 'Í'
251compose '\'' 'i' to 'í'
252compose '^' 'I' to 'Î'
253compose '^' 'i' to 'î'
254compose '"' 'I' to 'Ï'
255compose '"' 'i' to 'ï'
256compose '-' 'D' to 'Ð'
257compose '-' 'd' to 'ð'
258compose '~' 'N' to 'Ñ'
259compose '~' 'n' to 'ñ'
260compose '`' 'O' to 'Ò'
261compose '`' 'o' to 'ò'
262compose '\'' 'O' to 'Ó'
263compose '\'' 'o' to 'ó'
264compose '^' 'O' to 'Ô'
265compose '^' 'o' to 'ô'
266compose '~' 'O' to 'Õ'
267compose '~' 'o' to 'õ'
268compose '"' 'O' to 'Ö'
269compose '"' 'o' to 'ö'
270compose '/' 'O' to 'Ø'
271compose '/' 'o' to 'ø'
272compose '`' 'U' to 'Ù'
273compose '`' 'u' to 'ù'
274compose '\'' 'U' to 'Ú'
275compose '\'' 'u' to 'ú'
276compose '^' 'U' to 'Û'
277compose '^' 'u' to 'û'
278compose '"' 'U' to 'Ü'
279compose '"' 'u' to 'ü'
280compose '\'' 'Y' to 'Ý'
281compose '\'' 'y' to 'ý'
282compose 'T' 'H' to 'Þ'
283compose 't' 'h' to 'þ'
284compose 's' 's' to 'ß'
285compose '"' 'y' to 'ÿ'
286compose 's' 'z' to 'ß'
287compose 'i' 'j' to 'ÿ'
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index abcabb295592..0c68d0f0d8e5 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -614,15 +614,6 @@ config BLK_DEV_PIIX
614 the kernel to change PIO, DMA and UDMA speeds and to configure 614 the kernel to change PIO, DMA and UDMA speeds and to configure
615 the chip to optimum performance. 615 the chip to optimum performance.
616 616
617config BLK_DEV_IT8172
618 bool "IT8172 IDE support"
619 depends on (MIPS_ITE8172 || MIPS_IVR)
620 help
621 Say Y here to support the on-board IDE controller on the Integrated
622 Technology Express, Inc. ITE8172 SBC. Vendor page at
623 <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
624 board at <http://www.mvista.com/partners/semiconductor/ite.html>.
625
626config BLK_DEV_IT821X 617config BLK_DEV_IT821X
627 tristate "IT821X IDE support" 618 tristate "IT821X IDE support"
628 help 619 help
diff --git a/drivers/ide/pci/Makefile b/drivers/ide/pci/Makefile
index 640a54b09b5a..fef08960aa4c 100644
--- a/drivers/ide/pci/Makefile
+++ b/drivers/ide/pci/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_BLK_DEV_CY82C693) += cy82c693.o
12obj-$(CONFIG_BLK_DEV_HPT34X) += hpt34x.o 12obj-$(CONFIG_BLK_DEV_HPT34X) += hpt34x.o
13obj-$(CONFIG_BLK_DEV_HPT366) += hpt366.o 13obj-$(CONFIG_BLK_DEV_HPT366) += hpt366.o
14#obj-$(CONFIG_BLK_DEV_HPT37X) += hpt37x.o 14#obj-$(CONFIG_BLK_DEV_HPT37X) += hpt37x.o
15obj-$(CONFIG_BLK_DEV_IT8172) += it8172.o
16obj-$(CONFIG_BLK_DEV_IT821X) += it821x.o 15obj-$(CONFIG_BLK_DEV_IT821X) += it821x.o
17obj-$(CONFIG_BLK_DEV_JMICRON) += jmicron.o 16obj-$(CONFIG_BLK_DEV_JMICRON) += jmicron.o
18obj-$(CONFIG_BLK_DEV_NS87415) += ns87415.o 17obj-$(CONFIG_BLK_DEV_NS87415) += ns87415.o
diff --git a/drivers/ide/pci/it8172.c b/drivers/ide/pci/it8172.c
deleted file mode 100644
index 0fc89fafad65..000000000000
--- a/drivers/ide/pci/it8172.c
+++ /dev/null
@@ -1,307 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 IDE controller support
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * stevel@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/kernel.h>
34#include <linux/ioport.h>
35#include <linux/pci.h>
36#include <linux/hdreg.h>
37#include <linux/ide.h>
38#include <linux/delay.h>
39#include <linux/init.h>
40
41#include <asm/io.h>
42#include <asm/it8172/it8172_int.h>
43
44/*
45 * Prototypes
46 */
47static u8 it8172_ratemask (ide_drive_t *drive)
48{
49 return 1;
50}
51
52static void it8172_tune_drive (ide_drive_t *drive, u8 pio)
53{
54 ide_hwif_t *hwif = HWIF(drive);
55 struct pci_dev *dev = hwif->pci_dev;
56 int is_slave = (&hwif->drives[1] == drive);
57 unsigned long flags;
58 u16 drive_enables;
59 u32 drive_timing;
60
61 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
62 spin_lock_irqsave(&ide_lock, flags);
63 pci_read_config_word(dev, 0x40, &drive_enables);
64 pci_read_config_dword(dev, 0x44, &drive_timing);
65
66 /*
67 * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
68 * are being left at the default values of 8 PCI clocks (242 nsec
69 * for a 33 MHz clock). These can be safely shortened at higher
70 * PIO modes. The DIOR/DIOW pulse width and recovery times only
71 * apply to PIO modes, not to the DMA modes.
72 */
73
74 /*
75 * Enable port 0x44. The IT8172G spec is confused; it calls
76 * this register the "Slave IDE Timing Register", but in fact,
77 * it controls timing for both master and slave drives.
78 */
79 drive_enables |= 0x4000;
80
81 if (is_slave) {
82 drive_enables &= 0xc006;
83 if (pio > 1)
84 /* enable prefetch and IORDY sample-point */
85 drive_enables |= 0x0060;
86 } else {
87 drive_enables &= 0xc060;
88 if (pio > 1)
89 /* enable prefetch and IORDY sample-point */
90 drive_enables |= 0x0006;
91 }
92
93 pci_write_config_word(dev, 0x40, drive_enables);
94 spin_unlock_irqrestore(&ide_lock, flags);
95}
96
97static u8 it8172_dma_2_pio (u8 xfer_rate)
98{
99 switch(xfer_rate) {
100 case XFER_UDMA_5:
101 case XFER_UDMA_4:
102 case XFER_UDMA_3:
103 case XFER_UDMA_2:
104 case XFER_UDMA_1:
105 case XFER_UDMA_0:
106 case XFER_MW_DMA_2:
107 case XFER_PIO_4:
108 return 4;
109 case XFER_MW_DMA_1:
110 case XFER_PIO_3:
111 return 3;
112 case XFER_SW_DMA_2:
113 case XFER_PIO_2:
114 return 2;
115 case XFER_MW_DMA_0:
116 case XFER_SW_DMA_1:
117 case XFER_SW_DMA_0:
118 case XFER_PIO_1:
119 case XFER_PIO_0:
120 case XFER_PIO_SLOW:
121 default:
122 return 0;
123 }
124}
125
126static int it8172_tune_chipset (ide_drive_t *drive, u8 xferspeed)
127{
128 ide_hwif_t *hwif = HWIF(drive);
129 struct pci_dev *dev = hwif->pci_dev;
130 u8 speed = ide_rate_filter(it8172_ratemask(drive), xferspeed);
131 int a_speed = 3 << (drive->dn * 4);
132 int u_flag = 1 << drive->dn;
133 int u_speed = 0;
134 u8 reg48, reg4a;
135
136 pci_read_config_byte(dev, 0x48, &reg48);
137 pci_read_config_byte(dev, 0x4a, &reg4a);
138
139 /*
140 * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
141 * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
142 * transfers on some drives, even though both numbers meet the minimum
143 * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
144 * So the faster times are just commented out here. The good news is
145 * that the slower cycle time has very little affect on transfer
146 * performance.
147 */
148
149 switch(speed) {
150 case XFER_UDMA_4:
151 case XFER_UDMA_2: //u_speed = 2 << (drive->dn * 4); break;
152 case XFER_UDMA_5:
153 case XFER_UDMA_3:
154 case XFER_UDMA_1: //u_speed = 1 << (drive->dn * 4); break;
155 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
156 case XFER_MW_DMA_2:
157 case XFER_MW_DMA_1:
158 case XFER_MW_DMA_0:
159 case XFER_SW_DMA_2: break;
160 case XFER_PIO_4:
161 case XFER_PIO_3:
162 case XFER_PIO_2:
163 case XFER_PIO_0: break;
164 default: return -1;
165 }
166
167 if (speed >= XFER_UDMA_0) {
168 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
169 reg4a &= ~a_speed;
170 pci_write_config_byte(dev, 0x4a, reg4a | u_speed);
171 } else {
172 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
173 pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);
174 }
175
176 it8172_tune_drive(drive, it8172_dma_2_pio(speed));
177 return (ide_config_drive_speed(drive, speed));
178}
179
180static int it8172_config_chipset_for_dma (ide_drive_t *drive)
181{
182 u8 speed = ide_dma_speed(drive, it8172_ratemask(drive));
183
184 if (!(speed)) {
185 u8 tspeed = ide_get_best_pio_mode(drive, 255, 4, NULL);
186 speed = it8172_dma_2_pio(XFER_PIO_0 + tspeed);
187 }
188
189 (void) it8172_tune_chipset(drive, speed);
190 return ide_dma_enable(drive);
191}
192
193static int it8172_config_drive_xfer_rate (ide_drive_t *drive)
194{
195 ide_hwif_t *hwif = HWIF(drive);
196 struct hd_driveid *id = drive->id;
197
198 drive->init_speed = 0;
199
200 if (id && (id->capability & 1) && drive->autodma) {
201
202 if (ide_use_dma(drive)) {
203 if (it8172_config_chipset_for_dma(drive))
204 return hwif->ide_dma_on(drive);
205 }
206
207 goto fast_ata_pio;
208
209 } else if ((id->capability & 8) || (id->field_valid & 2)) {
210fast_ata_pio:
211 it8172_tune_drive(drive, 5);
212 return hwif->ide_dma_off_quietly(drive);
213 }
214 /* IORDY not supported */
215 return 0;
216}
217
218static unsigned int __devinit init_chipset_it8172 (struct pci_dev *dev, const char *name)
219{
220 unsigned char progif;
221
222 /*
223 * Place both IDE interfaces into PCI "native" mode
224 */
225 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
226 pci_write_config_byte(dev, PCI_CLASS_PROG, progif | 0x05);
227
228 return IT8172_IDE_IRQ;
229}
230
231
232static void __devinit init_hwif_it8172 (ide_hwif_t *hwif)
233{
234 struct pci_dev* dev = hwif->pci_dev;
235 unsigned long cmdBase, ctrlBase;
236
237 hwif->autodma = 0;
238 hwif->tuneproc = &it8172_tune_drive;
239 hwif->speedproc = &it8172_tune_chipset;
240
241 cmdBase = dev->resource[0].start;
242 ctrlBase = dev->resource[1].start;
243
244 ide_init_hwif_ports(&hwif->hw, cmdBase, ctrlBase | 2, NULL);
245 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
246 hwif->noprobe = 0;
247
248 if (!hwif->dma_base) {
249 hwif->drives[0].autotune = 1;
250 hwif->drives[1].autotune = 1;
251 return;
252 }
253
254 hwif->atapi_dma = 1;
255 hwif->ultra_mask = 0x07;
256 hwif->mwdma_mask = 0x06;
257 hwif->swdma_mask = 0x04;
258
259 hwif->ide_dma_check = &it8172_config_drive_xfer_rate;
260 if (!noautodma)
261 hwif->autodma = 1;
262 hwif->drives[0].autodma = hwif->autodma;
263 hwif->drives[1].autodma = hwif->autodma;
264}
265
266static ide_pci_device_t it8172_chipsets[] __devinitdata = {
267 { /* 0 */
268 .name = "IT8172G",
269 .init_chipset = init_chipset_it8172,
270 .init_hwif = init_hwif_it8172,
271 .channels = 2,
272 .autodma = AUTODMA,
273 .enablebits = {{0x00,0x00,0x00}, {0x40,0x00,0x01}},
274 .bootable = ON_BOARD,
275 }
276};
277
278static int __devinit it8172_init_one(struct pci_dev *dev, const struct pci_device_id *id)
279{
280 if ((!(PCI_FUNC(dev->devfn) & 1) ||
281 (!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))
282 return -ENODEV; /* IT8172 is more than an IDE controller */
283 return ide_setup_pci_device(dev, &it8172_chipsets[id->driver_data]);
284}
285
286static struct pci_device_id it8172_pci_tbl[] = {
287 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
288 { 0, },
289};
290MODULE_DEVICE_TABLE(pci, it8172_pci_tbl);
291
292static struct pci_driver driver = {
293 .name = "IT8172_IDE",
294 .id_table = it8172_pci_tbl,
295 .probe = it8172_init_one,
296};
297
298static int it8172_ide_init(void)
299{
300 return ide_pci_register_driver(&driver);
301}
302
303module_init(it8172_ide_init);
304
305MODULE_AUTHOR("SteveL@mvista.com");
306MODULE_DESCRIPTION("PCI driver module for ITE 8172 IDE");
307MODULE_LICENSE("GPL");
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 78c35ec46362..1e5ccdad3b02 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -125,12 +125,6 @@
125#define MACH_MOMENCO_OCELOT_3 4 125#define MACH_MOMENCO_OCELOT_3 4
126 126
127/* 127/*
128 * Valid machtype for group ITE
129 */
130#define MACH_GROUP_ITE 13 /* ITE Semi Eval Boards */
131#define MACH_QED_4N_S01B 0 /* ITE8172 based eval board */
132
133/*
134 * Valid machtype for group PHILIPS 128 * Valid machtype for group PHILIPS
135 */ 129 */
136#define MACH_GROUP_PHILIPS 14 130#define MACH_GROUP_PHILIPS 14
@@ -139,12 +133,6 @@
139#define MACH_PHILIPS_JBS 2 /* JBS */ 133#define MACH_PHILIPS_JBS 2 /* JBS */
140 134
141/* 135/*
142 * Valid machtype for group Globespan
143 */
144#define MACH_GROUP_GLOBESPAN 15 /* Globespan */
145#define MACH_IVR 0 /* IVR eval board */
146
147/*
148 * Valid machtype for group SIBYTE 136 * Valid machtype for group SIBYTE
149 */ 137 */
150#define MACH_GROUP_SIBYTE 16 /* Sibyte / Broadcom */ 138#define MACH_GROUP_SIBYTE 16 /* Sibyte / Broadcom */
diff --git a/include/asm-mips/it8172/it8172.h b/include/asm-mips/it8172/it8172.h
deleted file mode 100644
index 8f23af0a1ee8..000000000000
--- a/include/asm-mips/it8172/it8172.h
+++ /dev/null
@@ -1,348 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 system controller defines.
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#ifndef __IT8172__H__
32#define __IT8172__H__
33
34#include <asm/addrspace.h>
35
36#define IT8172_BASE 0x18000000
37#define IT8172_PCI_IO_BASE 0x14000000
38#define IT8172_PCI_MEM_BASE 0x10000000
39
40// System registers offsets from IT8172_BASE
41#define IT_CMFPCR 0x0
42#define IT_DSRR 0x2
43#define IT_PCDCR 0x4
44#define IT_SPLLCR 0x6
45#define IT_CIDR 0x10
46#define IT_CRNR 0x12
47#define IT_CPUTR 0x14
48#define IT_CTCR 0x16
49#define IT_SDPR 0xF0
50
51// Power management register offset from IT8172_PCI_IO_BASE
52// Power Management Device Standby Register
53#define IT_PM_DSR 0x15800
54
55#define IT_PM_DSR_TMR0SB 0x0001
56#define IT_PM_DSR_TMR1SB 0x0002
57#define IT_PM_DSR_CIR0SB 0x0004
58#define IT_PM_DSR_CIR1SB 0x0008
59#define IT_PM_DSR_SCR0SB 0x0010
60#define IT_PM_DSR_SCR1SB 0x0020
61#define IT_PM_DSR_PPSB 0x0040
62#define IT_PM_DSR_I2CSB 0x0080
63#define IT_PM_DSR_UARTSB 0x0100
64#define IT_PM_DSR_IDESB 0x0200
65#define IT_PM_DSR_ACSB 0x0400
66#define IT_PM_DSR_M68KSB 0x0800
67
68// Power Management PCI Device Software Reset Register
69#define IT_PM_PCISR 0x15802
70
71#define IT_PM_PCISR_IDESR 0x0001
72#define IT_PM_PCISR_CDMASR 0x0002
73#define IT_PM_PCISR_USBSR 0x0004
74#define IT_PM_PCISR_DMASR 0x0008
75#define IT_PM_PCISR_ACSR 0x0010
76#define IT_PM_PCISR_MEMSR 0x0020
77#define IT_PM_PCISR_68KSR 0x0040
78
79
80// PCI Configuration address and data register offsets
81// from IT8172_BASE
82#define IT_CONFADDR 0x4000
83#define IT_BUSNUM_SHF 16
84#define IT_DEVNUM_SHF 11
85#define IT_FUNCNUM_SHF 8
86#define IT_REGNUM_SHF 2
87
88#define IT_CONFDATA 0x4004
89
90// PCI configuration header common register offsets
91#define IT_VID 0x00
92#define IT_DID 0x02
93#define IT_PCICMD 0x04
94#define IT_PCISTS 0x06
95#define IT_RID 0x08
96#define IT_CLASSC 0x09
97#define IT_HEADT 0x0E
98#define IT_SERIRQC 0x49
99
100// PCI to Internal/LPC Bus Bridge configuration header register offset
101#define IT_P2I_BCR 0x4C
102#define IT_P2I_D0IOSC 0x50
103#define IT_P2I_D1IOSC 0x54
104#define IT_P2I_D2IOSC 0x58
105#define IT_P2I_D3IOSC 0x5C
106#define IT_P2I_D4IOSC 0x60
107#define IT_P2I_D5IOSC 0x64
108#define IT_P2I_D6IOSC 0x68
109#define IT_P2I_D7IOSC 0x6C
110#define IT_P2I_D8IOSC 0x70
111#define IT_P2I_D9IOSC 0x74
112#define IT_P2I_D10IOSC 0x78
113#define IT_P2I_D11IOSC 0x7C
114
115// Memory controller register offsets from IT8172_BASE
116#define IT_MC_SDRMR 0x1000
117#define IT_MC_SDRTR 0x1004
118#define IT_MC_MCR 0x1008
119#define IT_MC_SDTYPE 0x100C
120#define IT_MC_WPBA 0x1010
121#define IT_MC_WPTA 0x1014
122#define IT_MC_HATR 0x1018
123#define IT_MC_PCICR 0x101C
124
125// Flash/ROM control register offsets from IT8172_BASE
126#define IT_FC_BRCR 0x2000
127#define IT_FC_FCR 0x2004
128#define IT_FC_DCR 0x2008
129
130// M68K interface bridge configuration header register offset
131#define IT_M68K_MBCSR 0x54
132#define IT_M68K_TMR 0x58
133#define IT_M68K_BCR 0x5C
134#define IT_M68K_BSR 0x5D
135#define IT_M68K_DTR 0x5F
136
137// Register offset from IT8172_PCI_IO_BASE
138// These registers are accessible through 8172 PCI IO window.
139
140// INTC
141#define IT_INTC_BASE 0x10000
142#define IT_INTC_LBDNIRR 0x10000
143#define IT_INTC_LBDNIMR 0x10002
144#define IT_INTC_LBDNITR 0x10004
145#define IT_INTC_LBDNIAR 0x10006
146#define IT_INTC_LPCNIRR 0x10010
147#define IT_INTC_LPCNIMR 0x10012
148#define IT_INTC_LPCNITR 0x10014
149#define IT_INTC_LPCNIAR 0x10016
150#define IT_INTC_PDNIRR 0x10020
151#define IT_INTC_PDNIMR 0x10022
152#define IT_INTC_PDNITR 0x10024
153#define IT_INTC_PDNIAR 0x10026
154#define IT_INTC_UMNIRR 0x10030
155#define IT_INTC_UMNITR 0x10034
156#define IT_INTC_UMNIAR 0x10036
157#define IT_INTC_TYPER 0x107FE
158
159// IT8172 PCI device number
160#define IT_C2P_DEVICE 0
161#define IT_AUDIO_DEVICE 1
162#define IT_DMAC_DEVICE 1
163#define IT_CDMAC_DEVICE 1
164#define IT_USB_DEVICE 1
165#define IT_P2I_DEVICE 1
166#define IT_IDE_DEVICE 1
167#define IT_M68K_DEVICE 1
168
169// IT8172 PCI function number
170#define IT_C2P_FUNCION 0
171#define IT_AUDIO_FUNCTION 0
172#define IT_DMAC_FUNCTION 1
173#define IT_CDMAC_FUNCTION 2
174#define IT_USB_FUNCTION 3
175#define IT_P2I_FUNCTION 4
176#define IT_IDE_FUNCTION 5
177#define IT_M68K_FUNCTION 6
178
179// IT8172 GPIO
180#define IT_GPADR 0x13800
181#define IT_GPBDR 0x13808
182#define IT_GPCDR 0x13810
183#define IT_GPACR 0x13802
184#define IT_GPBCR 0x1380A
185#define IT_GPCCR 0x13812
186#define IT_GPAICR 0x13804
187#define IT_GPBICR 0x1380C
188#define IT_GPCICR 0x13814
189#define IT_GPAISR 0x13806
190#define IT_GPBISR 0x1380E
191#define IT_GPCISR 0x13816
192#define IT_GCR 0x13818
193
194// IT8172 RTC
195#define IT_RTC_BASE 0x14800
196#define IT_RTC_CENTURY 0x14808
197
198#define IT_RTC_RIR0 0x00
199#define IT_RTC_RTR0 0x01
200#define IT_RTC_RIR1 0x02
201#define IT_RTC_RTR1 0x03
202#define IT_RTC_RIR2 0x04
203#define IT_RTC_RTR2 0x05
204#define IT_RTC_RCTR 0x08
205#define IT_RTC_RA 0x0A
206#define IT_RTC_RB 0x0B
207#define IT_RTC_RC 0x0C
208#define IT_RTC_RD 0x0D
209
210#define RTC_SEC_INDEX 0x00
211#define RTC_MIN_INDEX 0x02
212#define RTC_HOUR_INDEX 0x04
213#define RTC_DAY_INDEX 0x06
214#define RTC_DATE_INDEX 0x07
215#define RTC_MONTH_INDEX 0x08
216#define RTC_YEAR_INDEX 0x09
217
218// IT8172 internal device registers
219#define IT_TIMER_BASE 0x10800
220#define IT_CIR0_BASE 0x11000
221#define IT_UART_BASE 0x11800
222#define IT_SCR0_BASE 0x12000
223#define IT_SCR1_BASE 0x12800
224#define IT_PP_BASE 0x13000
225#define IT_I2C_BASE 0x14000
226#define IT_CIR1_BASE 0x15000
227
228// IT8172 Smart Card Reader offsets from IT_SCR*_BASE
229#define IT_SCR_SFR 0x08
230#define IT_SCR_SCDR 0x09
231
232// IT8172 IT_SCR_SFR bit definition & mask
233#define IT_SCR_SFR_GATE_UART 0x40
234#define IT_SCR_SFR_GATE_UART_BIT 6
235#define IT_SCR_SFR_GATE_UART_OFF 0
236#define IT_SCR_SFR_GATE_UART_ON 1
237#define IT_SCR_SFR_FET_CHARGE 0x30
238#define IT_SCR_SFR_FET_CHARGE_BIT 4
239#define IT_SCR_SFR_FET_CHARGE_3_3_US 3
240#define IT_SCR_SFR_FET_CHARGE_13_US 2
241#define IT_SCR_SFR_FET_CHARGE_53_US 1
242#define IT_SCR_SFR_FET_CHARGE_213_US 0
243#define IT_SCR_SFR_CARD_FREQ 0x0C
244#define IT_SCR_SFR_CARD_FREQ_BIT 2
245#define IT_SCR_SFR_CARD_FREQ_STOP 3
246#define IT_SCR_SFR_CARD_FREQ_3_5_MHZ 0
247#define IT_SCR_SFR_CARD_FREQ_7_1_MHZ 2
248#define IT_SCR_SFR_CARD_FREQ_96_DIV_MHZ 1
249#define IT_SCR_SFR_FET_ACTIVE 0x02
250#define IT_SCR_SFR_FET_ACTIVE_BIT 1
251#define IT_SCR_SFR_FET_ACTIVE_INVERT 0
252#define IT_SCR_SFR_FET_ACTIVE_NONINVERT 1
253#define IT_SCR_SFR_ENABLE 0x01
254#define IT_SCR_SFR_ENABLE_BIT 0
255#define IT_SCR_SFR_ENABLE_OFF 0
256#define IT_SCR_SFR_ENABLE_ON 1
257
258// IT8172 IT_SCR_SCDR bit definition & mask
259#define IT_SCR_SCDR_RESET_MODE 0x80
260#define IT_SCR_SCDR_RESET_MODE_BIT 7
261#define IT_SCR_SCDR_RESET_MODE_ASYNC 0
262#define IT_SCR_SCDR_RESET_MODE_SYNC 1
263#define IT_SCR_SCDR_DIVISOR 0x7F
264#define IT_SCR_SCDR_DIVISOR_BIT 0
265#define IT_SCR_SCDR_DIVISOR_STOP_VAL_1 0x00
266#define IT_SCR_SCDR_DIVISOR_STOP_VAL_2 0x01
267#define IT_SCR_SCDR_DIVISOR_STOP_VAL_3 0x7F
268
269// IT8172 DMA
270#define IT_DMAC_BASE 0x16000
271#define IT_DMAC_BCAR0 0x00
272#define IT_DMAC_BCAR1 0x04
273#define IT_DMAC_BCAR2 0x08
274#define IT_DMAC_BCAR3 0x0C
275#define IT_DMAC_BCCR0 0x02
276#define IT_DMAC_BCCR1 0x06
277#define IT_DMAC_BCCR2 0x0a
278#define IT_DMAC_BCCR3 0x0e
279#define IT_DMAC_CR 0x10
280#define IT_DMAC_SR 0x12
281#define IT_DMAC_ESR 0x13
282#define IT_DMAC_RQR 0x14
283#define IT_DMAC_MR 0x16
284#define IT_DMAC_EMR 0x17
285#define IT_DMAC_MKR 0x18
286#define IT_DMAC_PAR0 0x20
287#define IT_DMAC_PAR1 0x22
288#define IT_DMAC_PAR2 0x24
289#define IT_DMAC_PAR3 0x26
290
291// IT8172 IDE
292#define IT_IDE_BASE 0x17800
293#define IT_IDE_STATUS 0x1F7
294
295// IT8172 Audio Controller
296#define IT_AC_BASE 0x17000
297#define IT_AC_PCMOV 0x00
298#define IT_AC_FMOV 0x02
299#define IT_AC_I2SV 0x04
300#define IT_AC_DRSS 0x06
301#define IT_AC_PCC 0x08
302#define IT_AC_PCDL 0x0A
303#define IT_AC_PCB1STA 0x0C
304#define IT_AC_PCB2STA 0x10
305#define IT_AC_CAPCC 0x14
306#define IT_AC_CAPCDL 0x16
307#define IT_AC_CAPB1STA 0x18
308#define IT_AC_CAPB2STA 0x1C
309#define IT_AC_CODECC 0x22
310#define IT_AC_I2SMC 0x24
311#define IT_AC_VS 0x26
312#define IT_AC_SRCS 0x28
313#define IT_AC_CIRCP 0x2A
314#define IT_AC_CIRDP 0x2C
315#define IT_AC_TM 0x4A
316#define IT_AC_PFDP 0x4C
317#define IT_AC_GC 0x54
318#define IT_AC_IMC 0x56
319#define IT_AC_ISC 0x5B
320#define IT_AC_OPL3SR 0x68
321#define IT_AC_OPL3DWDR 0x69
322#define IT_AC_OPL3AB1W 0x6A
323#define IT_AC_OPL3DW 0x6B
324#define IT_AC_BPDC 0x70
325
326
327// IT8172 Timer
328#define IT_TIMER_BASE 0x10800
329#define TIMER_TCVR0 0x00
330#define TIMER_TRVR0 0x02
331#define TIMER_TCR0 0x04
332#define TIMER_TIRR 0x06
333#define TIMER_TCVR1 0x08
334#define TIMER_TRVR1 0x0A
335#define TIMER_TCR1 0x0C
336#define TIMER_TIDR 0x0E
337
338
339#define IT_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data
340#define IT_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs))
341
342#define IT_IO_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
343#define IT_IO_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
344
345#define IT_IO_WRITE16(ofs, data) *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
346#define IT_IO_READ16(ofs, data) data = *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
347
348#endif
diff --git a/include/asm-mips/it8172/it8172_cir.h b/include/asm-mips/it8172/it8172_cir.h
deleted file mode 100644
index 6a1dbd29f6d1..000000000000
--- a/include/asm-mips/it8172/it8172_cir.h
+++ /dev/null
@@ -1,140 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 Consumer IR port defines.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#define NUM_CIR_PORTS 2
32
33/* Master Control Register */
34#define CIR_RESET 0x1
35#define CIR_FIFO_CLEAR 0x2
36#define CIR_SET_FIFO_TL(x) (((x)&0x3)<<2)
37#define CIR_ILE 0x10
38#define CIR_ILSEL 0x20
39
40/* Interrupt Enable Register */
41#define CIR_TLDLIE 0x1
42#define CIR_RDAIE 0x2
43#define CIR_RFOIE 0x4
44#define CIR_IEC 0x80
45
46/* Interrupt Identification Register */
47#define CIR_TLDLI 0x1
48#define CIR_RDAI 0x2
49#define CIR_RFOI 0x4
50#define CIR_NIP 0x80
51
52/* Carrier Frequency Register */
53#define CIR_SET_CF(x) ((x)&0x1f)
54 #define CFQ_38_480 0xB /* 38 KHz low, 480 KHz high */
55#define CIR_HCFS 0x20
56 #define CIR_SET_HS(x) (((x)&0x1)<<5)
57
58
59/* Receiver Control Register */
60#define CIR_SET_RXDCR(x) ((x)&0x7)
61#define CIR_RXACT 0x8
62#define CIR_RXEND 0x10
63#define CIR_RDWOS 0x20
64 #define CIR_SET_RDWOS(x) (((x)&0x1)<<5)
65#define CIR_RXEN 0x80
66
67/* Transmitter Control Register */
68#define CIR_SET_TXMPW(x) ((x)&0x7)
69#define CIR_SET_TXMPM(x) (((x)&0x3)<<3)
70#define CIR_TXENDF 0x20
71#define CIR_TXRLE 0x40
72
73/* Receiver FIFO Status Register */
74#define CIR_RXFBC_MASK 0x3f
75#define CIR_RXFTO 0x80
76
77/* Wakeup Code Length Register */
78#define CIR_SET_WCL ((x)&0x3f)
79#define CIR_WCL_MASK(x) ((x)&0x3f)
80
81/* Wakeup Power Control/Status Register */
82#define CIR_BTMON 0x2
83#define CIR_CIRON 0x4
84#define CIR_RCRST 0x10
85#define CIR_WCRST 0x20
86
87struct cir_port {
88 int port;
89 unsigned short baud_rate;
90 unsigned char fifo_tl;
91 unsigned char cfq;
92 unsigned char hcfs;
93 unsigned char rdwos;
94 unsigned char rxdcr;
95};
96
97struct it8172_cir_regs {
98 unsigned char dr; /* data */
99 char pad;
100 unsigned char mstcr; /* master control */
101 char pad1;
102 unsigned char ier; /* interrupt enable */
103 char pad2;
104 unsigned char iir; /* interrupt identification */
105 char pad3;
106 unsigned char cfr; /* carrier frequency */
107 char pad4;
108 unsigned char rcr; /* receiver control */
109 char pad5;
110 unsigned char tcr; /* transmitter control */
111 char pad6;
112 char pad7;
113 char pad8;
114 unsigned char bdlr; /* baud rate divisor low byte */
115 char pad9;
116 unsigned char bdhr; /* baud rate divisor high byte */
117 char pad10;
118 unsigned char tfsr; /* tx fifo byte count */
119 char pad11;
120 unsigned char rfsr; /* rx fifo status */
121 char pad12;
122 unsigned char wcl; /* wakeup code length */
123 char pad13;
124 unsigned char wcr; /* wakeup code read/write */
125 char pad14;
126 unsigned char wps; /* wakeup power control/status */
127};
128
129int cir_port_init(struct cir_port *cir);
130extern void clear_fifo(struct cir_port *cir);
131extern void enable_receiver(struct cir_port *cir);
132extern void disable_receiver(struct cir_port *cir);
133extern void enable_rx_demodulation(struct cir_port *cir);
134extern void disable_rx_demodulation(struct cir_port *cir);
135extern void set_rx_active(struct cir_port *cir);
136extern void int_enable(struct cir_port *cir);
137extern void rx_int_enable(struct cir_port *cir);
138extern char get_int_status(struct cir_port *cir);
139extern int cir_get_rx_count(struct cir_port *cir);
140extern char cir_read_data(struct cir_port *cir);
diff --git a/include/asm-mips/it8172/it8172_dbg.h b/include/asm-mips/it8172/it8172_dbg.h
deleted file mode 100644
index f404ec7c03ac..000000000000
--- a/include/asm-mips/it8172/it8172_dbg.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Function prototypes for low level uart routines to
5 * directly access a 16550 uart.
6 *
7 * Copyright 2000 MontaVista Software Inc.
8 * Author: MontaVista Software, Inc.
9 * ppopov@mvista.com or source@mvista.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */
31
32#include <linux/types.h>
33
34extern void putch(const unsigned char c);
35extern void puts(unsigned char *cp);
36extern void fputs(unsigned char *cp);
37extern void put64(uint64_t ul);
38extern void put32(unsigned u);
diff --git a/include/asm-mips/it8172/it8172_int.h b/include/asm-mips/it8172/it8172_int.h
deleted file mode 100644
index 837e83ac25f5..000000000000
--- a/include/asm-mips/it8172/it8172_int.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * ITE 8172 Interrupt Numbering
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#ifndef _MIPS_ITEINT_H
32#define _MIPS_ITEINT_H
33
34/*
35 * Here's the "strategy":
36 * We number the LPC serial irqs from 0 to 15,
37 * the local bus irqs from 16 to 31,
38 * the pci dev register interrupts from 32 to 47,
39 * and the non-maskable ints from 48 to 53.
40 */
41
42#define IT8172_LPC_IRQ_BASE 0 /* first LPC int number */
43#define IT8172_SERIRQ_0 (IT8172_LPC_IRQ_BASE + 0)
44#define IT8172_SERIRQ_1 (IT8172_LPC_IRQ_BASE + 1)
45#define IT8172_SERIRQ_2 (IT8172_LPC_IRQ_BASE + 2)
46#define IT8172_SERIRQ_3 (IT8172_LPC_IRQ_BASE + 3)
47#define IT8172_SERIRQ_4 (IT8172_LPC_IRQ_BASE + 4)
48#define IT8172_SERIRQ_5 (IT8172_LPC_IRQ_BASE + 5)
49#define IT8172_SERIRQ_6 (IT8172_LPC_IRQ_BASE + 6)
50#define IT8172_SERIRQ_7 (IT8172_LPC_IRQ_BASE + 7)
51#define IT8172_SERIRQ_8 (IT8172_LPC_IRQ_BASE + 8)
52#define IT8172_SERIRQ_9 (IT8172_LPC_IRQ_BASE + 9)
53#define IT8172_SERIRQ_10 (IT8172_LPC_IRQ_BASE + 10)
54#define IT8172_SERIRQ_11 (IT8172_LPC_IRQ_BASE + 11)
55#define IT8172_SERIRQ_12 (IT8172_LPC_IRQ_BASE + 12)
56#define IT8172_SERIRQ_13 (IT8172_LPC_IRQ_BASE + 13)
57#define IT8172_SERIRQ_14 (IT8172_LPC_IRQ_BASE + 14)
58#define IT8172_SERIRQ_15 (IT8172_LPC_IRQ_BASE + 15)
59
60#define IT8172_LB_IRQ_BASE 16 /* first local bus int number */
61#define IT8172_PPR_IRQ (IT8172_LB_IRQ_BASE + 0) /* parallel port */
62#define IT8172_TIMER0_IRQ (IT8172_LB_IRQ_BASE + 1)
63#define IT8172_TIMER1_IRQ (IT8172_LB_IRQ_BASE + 2)
64#define IT8172_I2C_IRQ (IT8172_LB_IRQ_BASE + 3)
65#define IT8172_GPIO_IRQ (IT8172_LB_IRQ_BASE + 4)
66#define IT8172_CIR0_IRQ (IT8172_LB_IRQ_BASE + 5)
67#define IT8172_CIR1_IRQ (IT8172_LB_IRQ_BASE + 6)
68#define IT8172_UART_IRQ (IT8172_LB_IRQ_BASE + 7)
69#define IT8172_SCR0_IRQ (IT8172_LB_IRQ_BASE + 8)
70#define IT8172_SCR1_IRQ (IT8172_LB_IRQ_BASE + 9)
71#define IT8172_RTC_IRQ (IT8172_LB_IRQ_BASE + 10)
72#define IT8172_IOCHK_IRQ (IT8172_LB_IRQ_BASE + 11)
73/* 12 - 15 reserved */
74
75/*
76 * Note here that the pci dev registers includes bits for more than
77 * just the pci devices.
78 */
79#define IT8172_PCI_DEV_IRQ_BASE 32 /* first pci dev irq */
80#define IT8172_AC97_IRQ (IT8172_PCI_DEV_IRQ_BASE + 0)
81#define IT8172_MC68K_IRQ (IT8172_PCI_DEV_IRQ_BASE + 1)
82#define IT8172_IDE_IRQ (IT8172_PCI_DEV_IRQ_BASE + 2)
83#define IT8172_USB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 3)
84#define IT8172_BRIDGE_MASTER_IRQ (IT8172_PCI_DEV_IRQ_BASE + 4)
85#define IT8172_BRIDGE_TARGET_IRQ (IT8172_PCI_DEV_IRQ_BASE + 5)
86#define IT8172_PCI_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 6)
87#define IT8172_PCI_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 7)
88#define IT8172_PCI_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 8)
89#define IT8172_PCI_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 9)
90#define IT8172_S_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 10)
91#define IT8172_S_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 11)
92#define IT8172_S_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 12)
93#define IT8172_S_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 13)
94#define IT8172_CDMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 14)
95#define IT8172_DMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 15)
96
97#define IT8172_NMI_IRQ_BASE 48
98#define IT8172_SER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 0)
99#define IT8172_PCI_NMI_IRQ (IT8172_NMI_IRQ_BASE + 1)
100#define IT8172_RTC_NMI_IRQ (IT8172_NMI_IRQ_BASE + 2)
101#define IT8172_CPUIF_NMI_IRQ (IT8172_NMI_IRQ_BASE + 3)
102#define IT8172_PMER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 4)
103#define IT8172_POWER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 5)
104
105#define IT8172_LAST_IRQ (IT8172_POWER_NMI_IRQ)
106/* Finally, let's move over here the mips cpu timer interrupt.
107 */
108#define MIPS_CPU_TIMER_IRQ (NR_IRQS-1)
109
110/*
111 * IT8172 Interrupt Controller Registers
112 */
113struct it8172_intc_regs {
114 volatile unsigned short lb_req; /* offset 0 */
115 volatile unsigned short lb_mask;
116 volatile unsigned short lb_trigger;
117 volatile unsigned short lb_level;
118 unsigned char pad0[8];
119
120 volatile unsigned short lpc_req; /* offset 0x10 */
121 volatile unsigned short lpc_mask;
122 volatile unsigned short lpc_trigger;
123 volatile unsigned short lpc_level;
124 unsigned char pad1[8];
125
126 volatile unsigned short pci_req; /* offset 0x20 */
127 volatile unsigned short pci_mask;
128 volatile unsigned short pci_trigger;
129 volatile unsigned short pci_level;
130 unsigned char pad2[8];
131
132 volatile unsigned short nmi_req; /* offset 0x30 */
133 volatile unsigned short nmi_mask;
134 volatile unsigned short nmi_trigger;
135 volatile unsigned short nmi_level;
136 unsigned char pad3[6];
137
138 volatile unsigned short nmi_redir; /* offset 0x3E */
139 unsigned char pad4[0xBE];
140
141 volatile unsigned short intstatus; /* offset 0xFE */
142};
143
144#endif /* _MIPS_ITEINT_H */
diff --git a/include/asm-mips/it8172/it8172_pci.h b/include/asm-mips/it8172/it8172_pci.h
deleted file mode 100644
index 42c61f56eeba..000000000000
--- a/include/asm-mips/it8172/it8172_pci.h
+++ /dev/null
@@ -1,108 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 system controller specific pci defines.
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#ifndef _8172PCI_H_
32#define _8172PCI_H_
33
34// PCI configuration space Type0
35#define PCI_IDREG 0x00
36#define PCI_CMDSTSREG 0x04
37#define PCI_CLASSREG 0x08
38#define PCI_BHLCREG 0x0C
39#define PCI_BASE1REG 0x10
40#define PCI_BASE2REG 0x14
41#define PCI_BASE3REG 0x18
42#define PCI_BASE4REG 0x1C
43#define PCI_BASE5REG 0x20
44#define PCI_BASE6REG 0x24
45#define PCI_ROMBASEREG 0x30
46#define PCI_INTRREG 0x3C
47
48// PCI configuration space Type1
49#define PCI_BUSNOREG 0x18
50
51#define IT_PCI_VENDORID(x) ((x) & 0xFFFF)
52#define IT_PCI_DEVICEID(x) (((x)>>16) & 0xFFFF)
53
54// Command register
55#define PCI_CMD_IOEN 0x00000001
56#define PCI_CMD_MEMEN 0x00000002
57#define PCI_CMD_BUSMASTER 0x00000004
58#define PCI_CMD_SPCYCLE 0x00000008
59#define PCI_CMD_WRINV 0x00000010
60#define PCI_CMD_VGASNOOP 0x00000020
61#define PCI_CMD_PERR 0x00000040
62#define PCI_CMD_WAITCTRL 0x00000080
63#define PCI_CMD_SERR 0x00000100
64#define PCI_CMD_FAST_BACKTOBACK 0x00000200
65
66// Status register
67#define PCI_STS_66MHZ 0x00200000
68#define PCI_STS_SUPPORT_UDF 0x00400000
69#define PCI_STS_FAST_BACKTOBACK 0x00800000
70#define PCI_STS_DATA_PERR 0x01000000
71#define PCI_STS_DEVSEL0 0x02000000
72#define PCI_STS_DEVSEL1 0x04000000
73#define PCI_STS_SIG_TGTABORT 0x08000000
74#define PCI_STS_RCV_TGTABORT 0x10000000
75#define PCI_STS_RCV_MSTABORT 0x20000000
76#define PCI_STS_SYSERR 0x40000000
77#define PCI_STS_DETCT_PERR 0x80000000
78
79#define IT_PCI_CLASS(x) (((x)>>24) & 0xFF)
80#define IT_PCI_SUBCLASS(x) (((x)>>16) & 0xFF)
81#define IT_PCI_INTERFACE(x) (((x)>>8) & 0xFF)
82#define IT_PCI_REVISION(x) ((x) & 0xFF)
83
84// PCI class code
85#define PCI_CLASS_BRIDGE 0x06
86
87// bridge subclass
88#define PCI_SUBCLASS_BRIDGE_HOST 0x00
89#define PCI_SUBCLASS_BRIDGE_PCI 0x04
90
91// BHLCREG
92#define IT_PCI_BIST(x) (((x)>>24) & 0xFF)
93#define IT_PCI_HEADERTYPE(x) (((x)>>16) & 0xFF)
94#define IT_PCI_LATENCYTIMER(x) (((x)>>8) & 0xFF)
95#define IT_PCI_CACHELINESIZE(x) ((x) & 0xFF)
96
97#define PCI_MULTIFUNC 0x80
98
99// INTRREG
100#define IT_PCI_MAXLAT(x) (((x)>>24) & 0xFF)
101#define IT_PCI_MINGNT(x) (((x)>>16) & 0xFF)
102#define IT_PCI_INTRPIN(x) (((x)>>8) & 0xFF)
103#define IT_PCI_INTRLINE(x) ((x) & 0xFF)
104
105#define PCI_VENDOR_NEC 0x1033
106#define PCI_VENDOR_DEC 0x1101
107
108#endif // _8172PCI_H_
diff --git a/include/asm-mips/it8712.h b/include/asm-mips/it8712.h
deleted file mode 100644
index ca2dee02a011..000000000000
--- a/include/asm-mips/it8712.h
+++ /dev/null
@@ -1,28 +0,0 @@
1
2#ifndef __IT8712_H__
3#define __IT8712_H__
4
5#define LPC_BASE_ADDR 0x14000000
6
7// MB PnP configuration register
8#define LPC_KEY_ADDR 0x1400002E
9#define LPC_DATA_ADDR 0x1400002F
10
11// Device LDN
12#define LDN_SERIAL1 0x01
13#define LDN_SERIAL2 0x02
14#define LDN_PARALLEL 0x03
15#define LDN_KEYBOARD 0x05
16#define LDN_MOUSE 0x06
17
18#define IT8712_UART1_PORT 0x3F8
19#define IT8712_UART2_PORT 0x2F8
20
21#ifndef ASM_ONLY
22
23void LPCSetConfig(char LdnNumber, char Index, char data);
24char LPCGetConfig(char LdnNumber, char Index);
25
26#endif
27
28#endif
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index c882e04e1497..d7a65135d837 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -69,38 +69,6 @@
69#define EV64120_SERIAL_PORT_DEFNS 69#define EV64120_SERIAL_PORT_DEFNS
70#endif 70#endif
71 71
72#ifdef CONFIG_MIPS_ITE8172
73#include <asm/it8172/it8172.h>
74#include <asm/it8172/it8172_int.h>
75#include <asm/it8712.h>
76#define ITE_SERIAL_PORT_DEFNS \
77 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
78 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
79 { .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
80 .irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
81 /* Smart Card Reader 0 */ \
82 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
83 .irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
84 /* Smart Card Reader 1 */ \
85 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
86 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 },
87#else
88#define ITE_SERIAL_PORT_DEFNS
89#endif
90
91#ifdef CONFIG_MIPS_IVR
92#include <asm/it8172/it8172.h>
93#include <asm/it8172/it8172_int.h>
94#define IVR_SERIAL_PORT_DEFNS \
95 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
96 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
97 /* Smart Card Reader 1 */ \
98 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
99 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 },
100#else
101#define IVR_SERIAL_PORT_DEFNS
102#endif
103
104#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT 72#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
105#define STD_SERIAL_PORT_DEFNS \ 73#define STD_SERIAL_PORT_DEFNS \
106 /* UART CLK PORT IRQ FLAGS */ \ 74 /* UART CLK PORT IRQ FLAGS */ \
@@ -240,8 +208,6 @@
240 DDB5477_SERIAL_PORT_DEFNS \ 208 DDB5477_SERIAL_PORT_DEFNS \
241 EV64120_SERIAL_PORT_DEFNS \ 209 EV64120_SERIAL_PORT_DEFNS \
242 IP32_SERIAL_PORT_DEFNS \ 210 IP32_SERIAL_PORT_DEFNS \
243 ITE_SERIAL_PORT_DEFNS \
244 IVR_SERIAL_PORT_DEFNS \
245 JAZZ_SERIAL_PORT_DEFNS \ 211 JAZZ_SERIAL_PORT_DEFNS \
246 STD_SERIAL_PORT_DEFNS \ 212 STD_SERIAL_PORT_DEFNS \
247 MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ 213 MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
diff --git a/include/linux/ite_gpio.h b/include/linux/ite_gpio.h
deleted file mode 100644
index b123a14292d3..000000000000
--- a/include/linux/ite_gpio.h
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * FILE NAME ite_gpio.h
3 *
4 * BRIEF MODULE DESCRIPTION
5 * Generic gpio.
6 *
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Hai-Pao Fan <haipao@mvista.com>
9 *
10 * Copyright 2001 MontaVista Software Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#ifndef __ITE_GPIO_H
34#define __ITE_GPIO_H
35
36#include <linux/ioctl.h>
37
38struct ite_gpio_ioctl_data {
39 __u32 device;
40 __u32 mask;
41 __u32 data;
42};
43
44#define ITE_GPIO_IOCTL_BASE 'Z'
45
46#define ITE_GPIO_IN _IOWR(ITE_GPIO_IOCTL_BASE, 0, struct ite_gpio_ioctl_data)
47#define ITE_GPIO_OUT _IOW (ITE_GPIO_IOCTL_BASE, 1, struct ite_gpio_ioctl_data)
48#define ITE_GPIO_INT_CTRL _IOW (ITE_GPIO_IOCTL_BASE, 2, struct ite_gpio_ioctl_data)
49#define ITE_GPIO_IN_STATUS _IOW (ITE_GPIO_IOCTL_BASE, 3, struct ite_gpio_ioctl_data)
50#define ITE_GPIO_OUT_STATUS _IOW (ITE_GPIO_IOCTL_BASE, 4, struct ite_gpio_ioctl_data)
51#define ITE_GPIO_GEN_CTRL _IOW (ITE_GPIO_IOCTL_BASE, 5, struct ite_gpio_ioctl_data)
52#define ITE_GPIO_INT_WAIT _IOW (ITE_GPIO_IOCTL_BASE, 6, struct ite_gpio_ioctl_data)
53
54#define ITE_GPIO_PORTA 0x01
55#define ITE_GPIO_PORTB 0x02
56#define ITE_GPIO_PORTC 0x04
57
58extern int ite_gpio_in(__u32 device, __u32 mask, volatile __u32 *data);
59extern int ite_gpio_out(__u32 device, __u32 mask, __u32 data);
60extern int ite_gpio_int_ctrl(__u32 device, __u32 mask, __u32 data);
61extern int ite_gpio_in_status(__u32 device, __u32 mask, volatile __u32 *data);
62extern int ite_gpio_out_status(__u32 device, __u32 mask, __u32 data);
63extern int ite_gpio_gen_ctrl(__u32 device, __u32 mask, __u32 data);
64extern int ite_gpio_int_wait(__u32 device, __u32 mask, __u32 data);
65
66#endif
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index dc7f573d36e4..f069df245469 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1615,8 +1615,6 @@
1615#define PCI_VENDOR_ID_ROCKWELL 0x127A 1615#define PCI_VENDOR_ID_ROCKWELL 0x127A
1616 1616
1617#define PCI_VENDOR_ID_ITE 0x1283 1617#define PCI_VENDOR_ID_ITE 0x1283
1618#define PCI_DEVICE_ID_ITE_IT8172G 0x8172
1619#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
1620#define PCI_DEVICE_ID_ITE_8211 0x8211 1618#define PCI_DEVICE_ID_ITE_8211 0x8211
1621#define PCI_DEVICE_ID_ITE_8212 0x8212 1619#define PCI_DEVICE_ID_ITE_8212 0x8212
1622#define PCI_DEVICE_ID_ITE_8872 0x8872 1620#define PCI_DEVICE_ID_ITE_8872 0x8872
diff --git a/sound/oss/Kconfig b/sound/oss/Kconfig
index 97e38b665587..f3b3530402cb 100644
--- a/sound/oss/Kconfig
+++ b/sound/oss/Kconfig
@@ -115,10 +115,6 @@ config SOUND_HAL2
115 Say Y or M if you have an SGI Indy or Indigo2 system and want to be able to 115 Say Y or M if you have an SGI Indy or Indigo2 system and want to be able to
116 use its on-board A2 audio system. 116 use its on-board A2 audio system.
117 117
118config SOUND_IT8172
119 tristate "IT8172G Sound"
120 depends on SOUND_PRIME && (MIPS_ITE8172 || MIPS_IVR)
121
122config SOUND_VRC5477 118config SOUND_VRC5477
123 tristate "NEC Vrc5477 AC97 sound" 119 tristate "NEC Vrc5477 AC97 sound"
124 depends on SOUND_PRIME && DDB5477 120 depends on SOUND_PRIME && DDB5477
diff --git a/sound/oss/Makefile b/sound/oss/Makefile
index 9bf3ee544d86..86811792002f 100644
--- a/sound/oss/Makefile
+++ b/sound/oss/Makefile
@@ -77,7 +77,6 @@ obj-$(CONFIG_SOUND_BCM_CS4297A) += swarm_cs4297a.o
77obj-$(CONFIG_SOUND_RME96XX) += rme96xx.o 77obj-$(CONFIG_SOUND_RME96XX) += rme96xx.o
78obj-$(CONFIG_SOUND_BT878) += btaudio.o 78obj-$(CONFIG_SOUND_BT878) += btaudio.o
79obj-$(CONFIG_SOUND_ALI5455) += ali5455.o ac97_codec.o 79obj-$(CONFIG_SOUND_ALI5455) += ali5455.o ac97_codec.o
80obj-$(CONFIG_SOUND_IT8172) += ite8172.o ac97_codec.o
81obj-$(CONFIG_SOUND_FORTE) += forte.o ac97_codec.o 80obj-$(CONFIG_SOUND_FORTE) += forte.o ac97_codec.o
82 81
83obj-$(CONFIG_SOUND_AD1980) += ac97_plugin_ad1980.o ac97_codec.o 82obj-$(CONFIG_SOUND_AD1980) += ac97_plugin_ad1980.o ac97_codec.o
diff --git a/sound/oss/ite8172.c b/sound/oss/ite8172.c
deleted file mode 100644
index 68aab3605d74..000000000000
--- a/sound/oss/ite8172.c
+++ /dev/null
@@ -1,2261 +0,0 @@
1/*
2 * ite8172.c -- ITE IT8172G Sound Driver.
3 *
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc.
6 * stevel@mvista.com or source@mvista.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *
28 *
29 * Module command line parameters:
30 *
31 * Supported devices:
32 * /dev/dsp standard OSS /dev/dsp device
33 * /dev/mixer standard OSS /dev/mixer device
34 *
35 * Notes:
36 *
37 * 1. Much of the OSS buffer allocation, ioctl's, and mmap'ing are
38 * taken, slightly modified or not at all, from the ES1371 driver,
39 * so refer to the credits in es1371.c for those. The rest of the
40 * code (probe, open, read, write, the ISR, etc.) is new.
41 * 2. The following support is untested:
42 * * Memory mapping the audio buffers, and the ioctl controls that go
43 * with it.
44 * * S/PDIF output.
45 * * I2S support.
46 * 3. The following is not supported:
47 * * legacy audio mode.
48 * 4. Support for volume button interrupts is implemented but doesn't
49 * work yet.
50 *
51 * Revision history
52 * 02.08.2001 Initial release
53 * 06.22.2001 Added I2S support
54 * 07.30.2003 Removed initialisation to zero for static variables
55 * (spdif[NR_DEVICE], i2s_fmt[NR_DEVICE], and devindex)
56 */
57#include <linux/module.h>
58#include <linux/string.h>
59#include <linux/ioport.h>
60#include <linux/sched.h>
61#include <linux/delay.h>
62#include <linux/sound.h>
63#include <linux/slab.h>
64#include <linux/soundcard.h>
65#include <linux/pci.h>
66#include <linux/init.h>
67#include <linux/poll.h>
68#include <linux/bitops.h>
69#include <linux/proc_fs.h>
70#include <linux/spinlock.h>
71#include <linux/smp_lock.h>
72#include <linux/ac97_codec.h>
73#include <linux/interrupt.h>
74#include <linux/mutex.h>
75
76#include <asm/io.h>
77#include <asm/dma.h>
78#include <asm/uaccess.h>
79#include <asm/it8172/it8172.h>
80
81/* --------------------------------------------------------------------- */
82
83#undef OSS_DOCUMENTED_MIXER_SEMANTICS
84#define IT8172_DEBUG
85#undef IT8172_VERBOSE_DEBUG
86#define DBG(x) {}
87
88#define IT8172_MODULE_NAME "IT8172 audio"
89#define PFX IT8172_MODULE_NAME
90
91#ifdef IT8172_DEBUG
92#define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
93#else
94#define dbg(format, arg...) do {} while (0)
95#endif
96#define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
97#define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
98#define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
99
100
101#define IT8172_MODULE_NAME "IT8172 audio"
102#define PFX IT8172_MODULE_NAME
103
104#ifdef IT8172_DEBUG
105#define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
106#else
107#define dbg(format, arg...) do {} while (0)
108#endif
109#define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
110#define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
111#define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
112
113
114static const unsigned sample_shift[] = { 0, 1, 1, 2 };
115
116
117/*
118 * Audio Controller register bit definitions follow. See
119 * include/asm/it8172/it8172.h for register offsets.
120 */
121
122/* PCM Out Volume Reg */
123#define PCMOV_PCMOM (1<<15) /* PCM Out Mute default 1: mute */
124#define PCMOV_PCMRCG_BIT 8 /* PCM Right channel Gain */
125#define PCMOV_PCMRCG_MASK (0x1f<<PCMOV_PCMRCG_BIT)
126#define PCMOV_PCMLCG_BIT 0 /* PCM Left channel gain */
127#define PCMOV_PCMLCG_MASK 0x1f
128
129/* FM Out Volume Reg */
130#define FMOV_FMOM (1<<15) /* FM Out Mute default 1: mute */
131#define FMOV_FMRCG_BIT 8 /* FM Right channel Gain */
132#define FMOV_FMRCG_MASK (0x1f<<FMOV_FMRCG_BIT)
133#define FMOV_FMLCG_BIT 0 /* FM Left channel gain */
134#define FMOV_FMLCG_MASK 0x1f
135
136/* I2S Out Volume Reg */
137#define I2SV_I2SOM (1<<15) /* I2S Out Mute default 1: mute */
138#define I2SV_I2SRCG_BIT 8 /* I2S Right channel Gain */
139#define I2SV_I2SRCG_MASK (0x1f<<I2SV_I2SRCG_BIT)
140#define I2SV_I2SLCG_BIT 0 /* I2S Left channel gain */
141#define I2SV_I2SLCG_MASK 0x1f
142
143/* Digital Recording Source Select Reg */
144#define DRSS_BIT 0
145#define DRSS_MASK 0x07
146#define DRSS_AC97_PRIM 0
147#define DRSS_FM 1
148#define DRSS_I2S 2
149#define DRSS_PCM 3
150#define DRSS_AC97_SEC 4
151
152/* Playback/Capture Channel Control Registers */
153#define CC_SM (1<<15) /* Stereo, Mone 0: mono 1: stereo */
154#define CC_DF (1<<14) /* Data Format 0: 8 bit 1: 16 bit */
155#define CC_FMT_BIT 14
156#define CC_FMT_MASK (0x03<<CC_FMT_BIT)
157#define CC_CF_BIT 12 /* Channel format (Playback only) */
158#define CC_CF_MASK (0x03<<CC_CF_BIT)
159#define CC_CF_2 0
160#define CC_CF_4 (1<<CC_CF_BIT)
161#define CC_CF_6 (2<<CC_CF_BIT)
162#define CC_SR_BIT 8 /* sample Rate */
163#define CC_SR_MASK (0x0f<<CC_SR_BIT)
164#define CC_SR_5500 0
165#define CC_SR_8000 (1<<CC_SR_BIT)
166#define CC_SR_9600 (2<<CC_SR_BIT)
167#define CC_SR_11025 (3<<CC_SR_BIT)
168#define CC_SR_16000 (4<<CC_SR_BIT)
169#define CC_SR_19200 (5<<CC_SR_BIT)
170#define CC_SR_22050 (6<<CC_SR_BIT)
171#define CC_SR_32000 (7<<CC_SR_BIT)
172#define CC_SR_38400 (8<<CC_SR_BIT)
173#define CC_SR_44100 (9<<CC_SR_BIT)
174#define CC_SR_48000 (10<<CC_SR_BIT)
175#define CC_CSP (1<<7) /* Channel stop
176 * 0: End of Current buffer
177 * 1: Immediately stop when rec stop */
178#define CC_CP (1<<6) /* Channel pause 0: normal, 1: pause */
179#define CC_CA (1<<5) /* Channel Action 0: Stop , 1: start */
180#define CC_CB2L (1<<2) /* Cur. buf. 2 xfr is last 0: No, 1: Yes */
181#define CC_CB1L (1<<1) /* Cur. buf. 1 xfr is last 0: No, 1: Yes */
182#define CC_DE 1 /* DFC/DFIFO Data Empty 1: empty, 0: not empty
183 * (Playback only)
184 */
185
186/* Codec Control Reg */
187#define CODECC_GME (1<<9) /* AC97 GPIO Mode enable */
188#define CODECC_ATM (1<<8) /* AC97 ATE test mode 0: test 1: normal */
189#define CODECC_WR (1<<6) /* AC97 Warn reset 1: warm reset , 0: Normal */
190#define CODECC_CR (1<<5) /* AC97 Cold reset 1: Cold reset , 0: Normal */
191
192
193/* I2S Control Reg */
194#define I2SMC_SR_BIT 6 /* I2S Sampling rate
195 * 00: 48KHz, 01: 44.1 KHz, 10: 32 32 KHz */
196#define I2SMC_SR_MASK (0x03<<I2SMC_SR_BIT)
197#define I2SMC_SR_48000 0
198#define I2SMC_SR_44100 (1<<I2SMC_SR_BIT)
199#define I2SMC_SR_32000 (2<<I2SMC_SR_BIT)
200#define I2SMC_SRSS (1<<5) /* Sample Rate Source Select 1:S/W, 0: H/W */
201#define I2SMC_I2SF_BIT 0 /* I2S Format */
202#define I2SMC_I2SF_MASK 0x03
203#define I2SMC_I2SF_DAC 0
204#define I2SMC_I2SF_ADC 2
205#define I2SMC_I2SF_I2S 3
206
207
208/* Volume up, Down, Mute */
209#define VS_VMP (1<<2) /* Volume mute 1: pushed, 0: not */
210#define VS_VDP (1<<1) /* Volume Down 1: pushed, 0: not */
211#define VS_VUP 1 /* Volime Up 1: pushed, 0: not */
212
213/* SRC, Mixer test control/DFC status reg */
214#define SRCS_DPUSC (1<<5) /* DFC Playback underrun Status/clear */
215#define SRCS_DCOSC (1<<4) /* DFC Capture Overrun Status/clear */
216#define SRCS_SIS (1<<3) /* SRC input select 1: Mixer, 0: Codec I/F */
217#define SRCS_CDIS_BIT 0 /* Codec Data Input Select */
218#define SRCS_CDIS_MASK 0x07
219#define SRCS_CDIS_MIXER 0
220#define SRCS_CDIS_PCM 1
221#define SRCS_CDIS_I2S 2
222#define SRCS_CDIS_FM 3
223#define SRCS_CDIS_DFC 4
224
225
226/* Codec Index Reg command Port */
227#define CIRCP_CID_BIT 10
228#define CIRCP_CID_MASK (0x03<<CIRCP_CID_BIT)
229#define CIRCP_CPS (1<<9) /* Command Port Status 0: ready, 1: busy */
230#define CIRCP_DPVF (1<<8) /* Data Port Valid Flag 0: invalis, 1: valid */
231#define CIRCP_RWC (1<<7) /* Read/write command */
232#define CIRCP_CIA_BIT 0
233#define CIRCP_CIA_MASK 0x007F /* Codec Index Address */
234
235/* Test Mode Control/Test group Select Control */
236
237/* General Control Reg */
238#define GC_VDC_BIT 6 /* Volume Division Control */
239#define GC_VDC_MASK (0x03<<GC_VDC_BIT)
240#define GC_VDC_NONE 0
241#define GC_VDC_DIV2 (1<<GC_VDC_BIT)
242#define GC_VDC_DIV4 (2<<GC_VDC_BIT)
243#define GC_SOE (1<<2) /* S/PDIF Output enable */
244#define GC_SWR 1 /* Software warn reset */
245
246/* Interrupt mask Control Reg */
247#define IMC_VCIM (1<<6) /* Volume CNTL interrupt mask */
248#define IMC_CCIM (1<<1) /* Capture Chan. iterrupt mask */
249#define IMC_PCIM 1 /* Playback Chan. interrupt mask */
250
251/* Interrupt status/clear reg */
252#define ISC_VCI (1<<6) /* Volume CNTL interrupt 1: clears */
253#define ISC_CCI (1<<1) /* Capture Chan. interrupt 1: clears */
254#define ISC_PCI 1 /* Playback Chan. interrupt 1: clears */
255
256/* misc stuff */
257#define POLL_COUNT 0x5000
258
259
260/* --------------------------------------------------------------------- */
261
262/*
263 * Define DIGITAL1 as the I2S channel, since it is not listed in
264 * soundcard.h.
265 */
266#define SOUND_MIXER_I2S SOUND_MIXER_DIGITAL1
267#define SOUND_MASK_I2S SOUND_MASK_DIGITAL1
268#define SOUND_MIXER_READ_I2S MIXER_READ(SOUND_MIXER_I2S)
269#define SOUND_MIXER_WRITE_I2S MIXER_WRITE(SOUND_MIXER_I2S)
270
271/* --------------------------------------------------------------------- */
272
273struct it8172_state {
274 /* list of it8172 devices */
275 struct list_head devs;
276
277 /* the corresponding pci_dev structure */
278 struct pci_dev *dev;
279
280 /* soundcore stuff */
281 int dev_audio;
282
283 /* hardware resources */
284 unsigned long io;
285 unsigned int irq;
286
287 /* PCI ID's */
288 u16 vendor;
289 u16 device;
290 u8 rev; /* the chip revision */
291
292 /* options */
293 int spdif_volume; /* S/PDIF output is enabled if != -1 */
294 int i2s_volume; /* current I2S out volume, in OSS format */
295 int i2s_recording;/* 1 = recording from I2S, 0 = not */
296
297#ifdef IT8172_DEBUG
298 /* debug /proc entry */
299 struct proc_dir_entry *ps;
300 struct proc_dir_entry *ac97_ps;
301#endif /* IT8172_DEBUG */
302
303 struct ac97_codec codec;
304
305 unsigned short pcc, capcc;
306 unsigned dacrate, adcrate;
307
308 spinlock_t lock;
309 struct mutex open_mutex;
310 mode_t open_mode;
311 wait_queue_head_t open_wait;
312
313 struct dmabuf {
314 void *rawbuf;
315 dma_addr_t dmaaddr;
316 unsigned buforder;
317 unsigned numfrag;
318 unsigned fragshift;
319 void* nextIn;
320 void* nextOut;
321 int count;
322 int curBufPtr;
323 unsigned total_bytes;
324 unsigned error; /* over/underrun */
325 wait_queue_head_t wait;
326 /* redundant, but makes calculations easier */
327 unsigned fragsize;
328 unsigned dmasize;
329 unsigned fragsamples;
330 /* OSS stuff */
331 unsigned mapped:1;
332 unsigned ready:1;
333 unsigned stopped:1;
334 unsigned ossfragshift;
335 int ossmaxfrags;
336 unsigned subdivision;
337 } dma_dac, dma_adc;
338};
339
340/* --------------------------------------------------------------------- */
341
342static LIST_HEAD(devs);
343
344/* --------------------------------------------------------------------- */
345
346static inline unsigned ld2(unsigned int x)
347{
348 unsigned r = 0;
349
350 if (x >= 0x10000) {
351 x >>= 16;
352 r += 16;
353 }
354 if (x >= 0x100) {
355 x >>= 8;
356 r += 8;
357 }
358 if (x >= 0x10) {
359 x >>= 4;
360 r += 4;
361 }
362 if (x >= 4) {
363 x >>= 2;
364 r += 2;
365 }
366 if (x >= 2)
367 r++;
368 return r;
369}
370
371/* --------------------------------------------------------------------- */
372
373static void it8172_delay(int msec)
374{
375 unsigned long tmo;
376 signed long tmo2;
377
378 if (in_interrupt())
379 return;
380
381 tmo = jiffies + (msec*HZ)/1000;
382 for (;;) {
383 tmo2 = tmo - jiffies;
384 if (tmo2 <= 0)
385 break;
386 schedule_timeout(tmo2);
387 }
388}
389
390
391static unsigned short
392get_compat_rate(unsigned* rate)
393{
394 unsigned rate_out = *rate;
395 unsigned short sr;
396
397 if (rate_out >= 46050) {
398 sr = CC_SR_48000; rate_out = 48000;
399 } else if (rate_out >= 41250) {
400 sr = CC_SR_44100; rate_out = 44100;
401 } else if (rate_out >= 35200) {
402 sr = CC_SR_38400; rate_out = 38400;
403 } else if (rate_out >= 27025) {
404 sr = CC_SR_32000; rate_out = 32000;
405 } else if (rate_out >= 20625) {
406 sr = CC_SR_22050; rate_out = 22050;
407 } else if (rate_out >= 17600) {
408 sr = CC_SR_19200; rate_out = 19200;
409 } else if (rate_out >= 13513) {
410 sr = CC_SR_16000; rate_out = 16000;
411 } else if (rate_out >= 10313) {
412 sr = CC_SR_11025; rate_out = 11025;
413 } else if (rate_out >= 8800) {
414 sr = CC_SR_9600; rate_out = 9600;
415 } else if (rate_out >= 6750) {
416 sr = CC_SR_8000; rate_out = 8000;
417 } else {
418 sr = CC_SR_5500; rate_out = 5500;
419 }
420
421 *rate = rate_out;
422 return sr;
423}
424
425static void set_adc_rate(struct it8172_state *s, unsigned rate)
426{
427 unsigned long flags;
428 unsigned short sr;
429
430 sr = get_compat_rate(&rate);
431
432 spin_lock_irqsave(&s->lock, flags);
433 s->capcc &= ~CC_SR_MASK;
434 s->capcc |= sr;
435 outw(s->capcc, s->io+IT_AC_CAPCC);
436 spin_unlock_irqrestore(&s->lock, flags);
437
438 s->adcrate = rate;
439}
440
441
442static void set_dac_rate(struct it8172_state *s, unsigned rate)
443{
444 unsigned long flags;
445 unsigned short sr;
446
447 sr = get_compat_rate(&rate);
448
449 spin_lock_irqsave(&s->lock, flags);
450 s->pcc &= ~CC_SR_MASK;
451 s->pcc |= sr;
452 outw(s->pcc, s->io+IT_AC_PCC);
453 spin_unlock_irqrestore(&s->lock, flags);
454
455 s->dacrate = rate;
456}
457
458
459/* --------------------------------------------------------------------- */
460
461static u16 rdcodec(struct ac97_codec *codec, u8 addr)
462{
463 struct it8172_state *s = (struct it8172_state *)codec->private_data;
464 unsigned long flags;
465 unsigned short circp, data;
466 int i;
467
468 spin_lock_irqsave(&s->lock, flags);
469
470 for (i = 0; i < POLL_COUNT; i++)
471 if (!(inw(s->io+IT_AC_CIRCP) & CIRCP_CPS))
472 break;
473 if (i == POLL_COUNT)
474 err("rdcodec: codec ready poll expired!");
475
476 circp = addr & CIRCP_CIA_MASK;
477 circp |= (codec->id << CIRCP_CID_BIT);
478 circp |= CIRCP_RWC; // read command
479 outw(circp, s->io+IT_AC_CIRCP);
480
481 /* now wait for the data */
482 for (i = 0; i < POLL_COUNT; i++)
483 if (inw(s->io+IT_AC_CIRCP) & CIRCP_DPVF)
484 break;
485 if (i == POLL_COUNT)
486 err("rdcodec: read poll expired!");
487
488 data = inw(s->io+IT_AC_CIRDP);
489 spin_unlock_irqrestore(&s->lock, flags);
490
491 return data;
492}
493
494
495static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
496{
497 struct it8172_state *s = (struct it8172_state *)codec->private_data;
498 unsigned long flags;
499 unsigned short circp;
500 int i;
501
502 spin_lock_irqsave(&s->lock, flags);
503
504 for (i = 0; i < POLL_COUNT; i++)
505 if (!(inw(s->io+IT_AC_CIRCP) & CIRCP_CPS))
506 break;
507 if (i == POLL_COUNT)
508 err("wrcodec: codec ready poll expired!");
509
510 circp = addr & CIRCP_CIA_MASK;
511 circp |= (codec->id << CIRCP_CID_BIT);
512 circp &= ~CIRCP_RWC; // write command
513
514 outw(data, s->io+IT_AC_CIRDP); // send data first
515 outw(circp, s->io+IT_AC_CIRCP);
516
517 spin_unlock_irqrestore(&s->lock, flags);
518}
519
520
521static void waitcodec(struct ac97_codec *codec)
522{
523 unsigned short temp;
524
525 /* codec_wait is used to wait for a ready state after
526 an AC97_RESET. */
527 it8172_delay(10);
528
529 temp = rdcodec(codec, 0x26);
530
531 // If power down, power up
532 if (temp & 0x3f00) {
533 // Power on
534 wrcodec(codec, 0x26, 0);
535 it8172_delay(100);
536 // Reread
537 temp = rdcodec(codec, 0x26);
538 }
539
540 // Check if Codec REF,ANL,DAC,ADC ready***/
541 if ((temp & 0x3f0f) != 0x000f) {
542 err("codec reg 26 status (0x%x) not ready!!", temp);
543 return;
544 }
545}
546
547
548/* --------------------------------------------------------------------- */
549
550static inline void stop_adc(struct it8172_state *s)
551{
552 struct dmabuf* db = &s->dma_adc;
553 unsigned long flags;
554 unsigned char imc;
555
556 if (db->stopped)
557 return;
558
559 spin_lock_irqsave(&s->lock, flags);
560
561 s->capcc &= ~(CC_CA | CC_CP | CC_CB2L | CC_CB1L);
562 s->capcc |= CC_CSP;
563 outw(s->capcc, s->io+IT_AC_CAPCC);
564
565 // disable capture interrupt
566 imc = inb(s->io+IT_AC_IMC);
567 outb(imc | IMC_CCIM, s->io+IT_AC_IMC);
568
569 db->stopped = 1;
570
571 spin_unlock_irqrestore(&s->lock, flags);
572}
573
574static inline void stop_dac(struct it8172_state *s)
575{
576 struct dmabuf* db = &s->dma_dac;
577 unsigned long flags;
578 unsigned char imc;
579
580 if (db->stopped)
581 return;
582
583 spin_lock_irqsave(&s->lock, flags);
584
585 s->pcc &= ~(CC_CA | CC_CP | CC_CB2L | CC_CB1L);
586 s->pcc |= CC_CSP;
587 outw(s->pcc, s->io+IT_AC_PCC);
588
589 // disable playback interrupt
590 imc = inb(s->io+IT_AC_IMC);
591 outb(imc | IMC_PCIM, s->io+IT_AC_IMC);
592
593 db->stopped = 1;
594
595 spin_unlock_irqrestore(&s->lock, flags);
596}
597
598static void start_dac(struct it8172_state *s)
599{
600 struct dmabuf* db = &s->dma_dac;
601 unsigned long flags;
602 unsigned char imc;
603 unsigned long buf1, buf2;
604
605 if (!db->stopped)
606 return;
607
608 spin_lock_irqsave(&s->lock, flags);
609
610 // reset Buffer 1 and 2 pointers to nextOut and nextOut+fragsize
611 buf1 = virt_to_bus(db->nextOut);
612 buf2 = buf1 + db->fragsize;
613 if (buf2 >= db->dmaaddr + db->dmasize)
614 buf2 -= db->dmasize;
615
616 outl(buf1, s->io+IT_AC_PCB1STA);
617 outl(buf2, s->io+IT_AC_PCB2STA);
618 db->curBufPtr = IT_AC_PCB1STA;
619
620 // enable playback interrupt
621 imc = inb(s->io+IT_AC_IMC);
622 outb(imc & ~IMC_PCIM, s->io+IT_AC_IMC);
623
624 s->pcc &= ~(CC_CSP | CC_CP | CC_CB2L | CC_CB1L);
625 s->pcc |= CC_CA;
626 outw(s->pcc, s->io+IT_AC_PCC);
627
628 db->stopped = 0;
629
630 spin_unlock_irqrestore(&s->lock, flags);
631}
632
633static void start_adc(struct it8172_state *s)
634{
635 struct dmabuf* db = &s->dma_adc;
636 unsigned long flags;
637 unsigned char imc;
638 unsigned long buf1, buf2;
639
640 if (!db->stopped)
641 return;
642
643 spin_lock_irqsave(&s->lock, flags);
644
645 // reset Buffer 1 and 2 pointers to nextIn and nextIn+fragsize
646 buf1 = virt_to_bus(db->nextIn);
647 buf2 = buf1 + db->fragsize;
648 if (buf2 >= db->dmaaddr + db->dmasize)
649 buf2 -= db->dmasize;
650
651 outl(buf1, s->io+IT_AC_CAPB1STA);
652 outl(buf2, s->io+IT_AC_CAPB2STA);
653 db->curBufPtr = IT_AC_CAPB1STA;
654
655 // enable capture interrupt
656 imc = inb(s->io+IT_AC_IMC);
657 outb(imc & ~IMC_CCIM, s->io+IT_AC_IMC);
658
659 s->capcc &= ~(CC_CSP | CC_CP | CC_CB2L | CC_CB1L);
660 s->capcc |= CC_CA;
661 outw(s->capcc, s->io+IT_AC_CAPCC);
662
663 db->stopped = 0;
664
665 spin_unlock_irqrestore(&s->lock, flags);
666}
667
668/* --------------------------------------------------------------------- */
669
670#define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
671#define DMABUF_MINORDER 1
672
673static inline void dealloc_dmabuf(struct it8172_state *s, struct dmabuf *db)
674{
675 struct page *page, *pend;
676
677 if (db->rawbuf) {
678 /* undo marking the pages as reserved */
679 pend = virt_to_page(db->rawbuf +
680 (PAGE_SIZE << db->buforder) - 1);
681 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
682 ClearPageReserved(page);
683 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder,
684 db->rawbuf, db->dmaaddr);
685 }
686 db->rawbuf = db->nextIn = db->nextOut = NULL;
687 db->mapped = db->ready = 0;
688}
689
690static int prog_dmabuf(struct it8172_state *s, struct dmabuf *db,
691 unsigned rate, unsigned fmt, unsigned reg)
692{
693 int order;
694 unsigned bytepersec;
695 unsigned bufs;
696 struct page *page, *pend;
697
698 if (!db->rawbuf) {
699 db->ready = db->mapped = 0;
700 for (order = DMABUF_DEFAULTORDER;
701 order >= DMABUF_MINORDER; order--)
702 if ((db->rawbuf =
703 pci_alloc_consistent(s->dev,
704 PAGE_SIZE << order,
705 &db->dmaaddr)))
706 break;
707 if (!db->rawbuf)
708 return -ENOMEM;
709 db->buforder = order;
710 /* now mark the pages as reserved;
711 otherwise remap_pfn_range doesn't do what we want */
712 pend = virt_to_page(db->rawbuf +
713 (PAGE_SIZE << db->buforder) - 1);
714 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
715 SetPageReserved(page);
716 }
717
718 db->count = 0;
719 db->nextIn = db->nextOut = db->rawbuf;
720
721 bytepersec = rate << sample_shift[fmt];
722 bufs = PAGE_SIZE << db->buforder;
723 if (db->ossfragshift) {
724 if ((1000 << db->ossfragshift) < bytepersec)
725 db->fragshift = ld2(bytepersec/1000);
726 else
727 db->fragshift = db->ossfragshift;
728 } else {
729 db->fragshift = ld2(bytepersec/100/(db->subdivision ?
730 db->subdivision : 1));
731 if (db->fragshift < 3)
732 db->fragshift = 3;
733 }
734 db->numfrag = bufs >> db->fragshift;
735 while (db->numfrag < 4 && db->fragshift > 3) {
736 db->fragshift--;
737 db->numfrag = bufs >> db->fragshift;
738 }
739 db->fragsize = 1 << db->fragshift;
740 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
741 db->numfrag = db->ossmaxfrags;
742 db->fragsamples = db->fragsize >> sample_shift[fmt];
743 db->dmasize = db->numfrag << db->fragshift;
744 memset(db->rawbuf, (fmt & (CC_DF>>CC_FMT_BIT)) ? 0 : 0x80, bufs);
745
746#ifdef IT8172_VERBOSE_DEBUG
747 dbg("rate=%d, fragsize=%d, numfrag=%d, dmasize=%d",
748 rate, db->fragsize, db->numfrag, db->dmasize);
749#endif
750
751 // set data length register
752 outw(db->fragsize, s->io+reg+2);
753 db->ready = 1;
754
755 return 0;
756}
757
758static inline int prog_dmabuf_adc(struct it8172_state *s)
759{
760 stop_adc(s);
761 return prog_dmabuf(s, &s->dma_adc, s->adcrate,
762 (s->capcc & CC_FMT_MASK) >> CC_FMT_BIT,
763 IT_AC_CAPCC);
764}
765
766static inline int prog_dmabuf_dac(struct it8172_state *s)
767{
768 stop_dac(s);
769 return prog_dmabuf(s, &s->dma_dac, s->dacrate,
770 (s->pcc & CC_FMT_MASK) >> CC_FMT_BIT,
771 IT_AC_PCC);
772}
773
774
775/* hold spinlock for the following! */
776
777static irqreturn_t it8172_interrupt(int irq, void *dev_id, struct pt_regs *regs)
778{
779 struct it8172_state *s = (struct it8172_state *)dev_id;
780 struct dmabuf* dac = &s->dma_dac;
781 struct dmabuf* adc = &s->dma_adc;
782 unsigned char isc, vs;
783 unsigned short vol, mute;
784 unsigned long newptr;
785
786 spin_lock(&s->lock);
787
788 isc = inb(s->io+IT_AC_ISC);
789
790 /* fastpath out, to ease interrupt sharing */
791 if (!(isc & (ISC_VCI | ISC_CCI | ISC_PCI))) {
792 spin_unlock(&s->lock);
793 return IRQ_NONE;
794 }
795
796 /* clear audio interrupts first */
797 outb(isc | ISC_VCI | ISC_CCI | ISC_PCI, s->io+IT_AC_ISC);
798
799 /* handle volume button events (ignore if S/PDIF enabled) */
800 if ((isc & ISC_VCI) && s->spdif_volume == -1) {
801 vs = inb(s->io+IT_AC_VS);
802 outb(0, s->io+IT_AC_VS);
803 vol = inw(s->io+IT_AC_PCMOV);
804 mute = vol & PCMOV_PCMOM;
805 vol &= PCMOV_PCMLCG_MASK;
806 if ((vs & VS_VUP) && vol > 0)
807 vol--;
808 if ((vs & VS_VDP) && vol < 0x1f)
809 vol++;
810 vol |= (vol << PCMOV_PCMRCG_BIT);
811 if (vs & VS_VMP)
812 vol |= (mute ^ PCMOV_PCMOM);
813 outw(vol, s->io+IT_AC_PCMOV);
814 }
815
816 /* update capture pointers */
817 if (isc & ISC_CCI) {
818 if (adc->count > adc->dmasize - adc->fragsize) {
819 // Overrun. Stop ADC and log the error
820 stop_adc(s);
821 adc->error++;
822 dbg("adc overrun");
823 } else {
824 newptr = virt_to_bus(adc->nextIn) + 2*adc->fragsize;
825 if (newptr >= adc->dmaaddr + adc->dmasize)
826 newptr -= adc->dmasize;
827
828 outl(newptr, s->io+adc->curBufPtr);
829 adc->curBufPtr = (adc->curBufPtr == IT_AC_CAPB1STA) ?
830 IT_AC_CAPB2STA : IT_AC_CAPB1STA;
831
832 adc->nextIn += adc->fragsize;
833 if (adc->nextIn >= adc->rawbuf + adc->dmasize)
834 adc->nextIn -= adc->dmasize;
835
836 adc->count += adc->fragsize;
837 adc->total_bytes += adc->fragsize;
838
839 /* wake up anybody listening */
840 if (waitqueue_active(&adc->wait))
841 wake_up_interruptible(&adc->wait);
842 }
843 }
844
845 /* update playback pointers */
846 if (isc & ISC_PCI) {
847 newptr = virt_to_bus(dac->nextOut) + 2*dac->fragsize;
848 if (newptr >= dac->dmaaddr + dac->dmasize)
849 newptr -= dac->dmasize;
850
851 outl(newptr, s->io+dac->curBufPtr);
852 dac->curBufPtr = (dac->curBufPtr == IT_AC_PCB1STA) ?
853 IT_AC_PCB2STA : IT_AC_PCB1STA;
854
855 dac->nextOut += dac->fragsize;
856 if (dac->nextOut >= dac->rawbuf + dac->dmasize)
857 dac->nextOut -= dac->dmasize;
858
859 dac->count -= dac->fragsize;
860 dac->total_bytes += dac->fragsize;
861
862 /* wake up anybody listening */
863 if (waitqueue_active(&dac->wait))
864 wake_up_interruptible(&dac->wait);
865
866 if (dac->count <= 0)
867 stop_dac(s);
868 }
869
870 spin_unlock(&s->lock);
871 return IRQ_HANDLED;
872}
873
874/* --------------------------------------------------------------------- */
875
876static int it8172_open_mixdev(struct inode *inode, struct file *file)
877{
878 int minor = iminor(inode);
879 struct list_head *list;
880 struct it8172_state *s;
881
882 for (list = devs.next; ; list = list->next) {
883 if (list == &devs)
884 return -ENODEV;
885 s = list_entry(list, struct it8172_state, devs);
886 if (s->codec.dev_mixer == minor)
887 break;
888 }
889 file->private_data = s;
890 return nonseekable_open(inode, file);
891}
892
893static int it8172_release_mixdev(struct inode *inode, struct file *file)
894{
895 return 0;
896}
897
898
899static u16
900cvt_ossvol(unsigned int gain)
901{
902 u16 ret;
903
904 if (gain == 0)
905 return 0;
906
907 if (gain > 100)
908 gain = 100;
909
910 ret = (100 - gain + 32) / 4;
911 ret = ret > 31 ? 31 : ret;
912 return ret;
913}
914
915
916static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
917 unsigned long arg)
918{
919 struct it8172_state *s = (struct it8172_state *)codec->private_data;
920 unsigned int left, right;
921 unsigned long flags;
922 int val;
923 u16 vol;
924
925 /*
926 * When we are in S/PDIF mode, we want to disable any analog output so
927 * we filter the master/PCM channel volume ioctls.
928 *
929 * Also filter I2S channel, which AC'97 knows nothing about.
930 */
931
932 switch (cmd) {
933 case SOUND_MIXER_WRITE_VOLUME:
934 // if not in S/PDIF mode, pass to AC'97
935 if (s->spdif_volume == -1)
936 break;
937 return 0;
938 case SOUND_MIXER_WRITE_PCM:
939 // if not in S/PDIF mode, pass to AC'97
940 if (s->spdif_volume == -1)
941 break;
942 if (get_user(val, (int *)arg))
943 return -EFAULT;
944 right = ((val >> 8) & 0xff);
945 left = (val & 0xff);
946 if (right > 100)
947 right = 100;
948 if (left > 100)
949 left = 100;
950 s->spdif_volume = (right << 8) | left;
951 vol = cvt_ossvol(left);
952 vol |= (cvt_ossvol(right) << PCMOV_PCMRCG_BIT);
953 if (vol == 0)
954 vol = PCMOV_PCMOM; // mute
955 spin_lock_irqsave(&s->lock, flags);
956 outw(vol, s->io+IT_AC_PCMOV);
957 spin_unlock_irqrestore(&s->lock, flags);
958 return put_user(s->spdif_volume, (int *)arg);
959 case SOUND_MIXER_READ_PCM:
960 // if not in S/PDIF mode, pass to AC'97
961 if (s->spdif_volume == -1)
962 break;
963 return put_user(s->spdif_volume, (int *)arg);
964 case SOUND_MIXER_WRITE_I2S:
965 if (get_user(val, (int *)arg))
966 return -EFAULT;
967 right = ((val >> 8) & 0xff);
968 left = (val & 0xff);
969 if (right > 100)
970 right = 100;
971 if (left > 100)
972 left = 100;
973 s->i2s_volume = (right << 8) | left;
974 vol = cvt_ossvol(left);
975 vol |= (cvt_ossvol(right) << I2SV_I2SRCG_BIT);
976 if (vol == 0)
977 vol = I2SV_I2SOM; // mute
978 outw(vol, s->io+IT_AC_I2SV);
979 return put_user(s->i2s_volume, (int *)arg);
980 case SOUND_MIXER_READ_I2S:
981 return put_user(s->i2s_volume, (int *)arg);
982 case SOUND_MIXER_WRITE_RECSRC:
983 if (get_user(val, (int *)arg))
984 return -EFAULT;
985 if (val & SOUND_MASK_I2S) {
986 s->i2s_recording = 1;
987 outb(DRSS_I2S, s->io+IT_AC_DRSS);
988 return 0;
989 } else {
990 s->i2s_recording = 0;
991 outb(DRSS_AC97_PRIM, s->io+IT_AC_DRSS);
992 // now let AC'97 select record source
993 break;
994 }
995 case SOUND_MIXER_READ_RECSRC:
996 if (s->i2s_recording)
997 return put_user(SOUND_MASK_I2S, (int *)arg);
998 else
999 // let AC'97 report recording source
1000 break;
1001 }
1002
1003 return codec->mixer_ioctl(codec, cmd, arg);
1004}
1005
1006static int it8172_ioctl_mixdev(struct inode *inode, struct file *file,
1007 unsigned int cmd, unsigned long arg)
1008{
1009 struct it8172_state *s = (struct it8172_state *)file->private_data;
1010 struct ac97_codec *codec = &s->codec;
1011
1012 return mixdev_ioctl(codec, cmd, arg);
1013}
1014
1015static /*const*/ struct file_operations it8172_mixer_fops = {
1016 .owner = THIS_MODULE,
1017 .llseek = no_llseek,
1018 .ioctl = it8172_ioctl_mixdev,
1019 .open = it8172_open_mixdev,
1020 .release = it8172_release_mixdev,
1021};
1022
1023/* --------------------------------------------------------------------- */
1024
1025static int drain_dac(struct it8172_state *s, int nonblock)
1026{
1027 unsigned long flags;
1028 int count, tmo;
1029
1030 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
1031 return 0;
1032
1033 for (;;) {
1034 spin_lock_irqsave(&s->lock, flags);
1035 count = s->dma_dac.count;
1036 spin_unlock_irqrestore(&s->lock, flags);
1037 if (count <= 0)
1038 break;
1039 if (signal_pending(current))
1040 break;
1041 //if (nonblock)
1042 //return -EBUSY;
1043 tmo = 1000 * count / s->dacrate;
1044 tmo >>= sample_shift[(s->pcc & CC_FMT_MASK) >> CC_FMT_BIT];
1045 it8172_delay(tmo);
1046 }
1047 if (signal_pending(current))
1048 return -ERESTARTSYS;
1049 return 0;
1050}
1051
1052/* --------------------------------------------------------------------- */
1053
1054
1055/*
1056 * Copy audio data to/from user buffer from/to dma buffer, taking care
1057 * that we wrap when reading/writing the dma buffer. Returns actual byte
1058 * count written to or read from the dma buffer.
1059 */
1060static int copy_dmabuf_user(struct dmabuf *db, char* userbuf,
1061 int count, int to_user)
1062{
1063 char* bufptr = to_user ? db->nextOut : db->nextIn;
1064 char* bufend = db->rawbuf + db->dmasize;
1065
1066 if (bufptr + count > bufend) {
1067 int partial = (int)(bufend - bufptr);
1068 if (to_user) {
1069 if (copy_to_user(userbuf, bufptr, partial))
1070 return -EFAULT;
1071 if (copy_to_user(userbuf + partial, db->rawbuf,
1072 count - partial))
1073 return -EFAULT;
1074 } else {
1075 if (copy_from_user(bufptr, userbuf, partial))
1076 return -EFAULT;
1077 if (copy_from_user(db->rawbuf,
1078 userbuf + partial,
1079 count - partial))
1080 return -EFAULT;
1081 }
1082 } else {
1083 if (to_user) {
1084 if (copy_to_user(userbuf, bufptr, count))
1085 return -EFAULT;
1086 } else {
1087 if (copy_from_user(bufptr, userbuf, count))
1088 return -EFAULT;
1089 }
1090 }
1091
1092 return count;
1093}
1094
1095
1096static ssize_t it8172_read(struct file *file, char *buffer,
1097 size_t count, loff_t *ppos)
1098{
1099 struct it8172_state *s = (struct it8172_state *)file->private_data;
1100 struct dmabuf *db = &s->dma_adc;
1101 ssize_t ret;
1102 unsigned long flags;
1103 int cnt, remainder, avail;
1104
1105 if (db->mapped)
1106 return -ENXIO;
1107 if (!access_ok(VERIFY_WRITE, buffer, count))
1108 return -EFAULT;
1109 ret = 0;
1110
1111 while (count > 0) {
1112 // wait for samples in capture buffer
1113 do {
1114 spin_lock_irqsave(&s->lock, flags);
1115 if (db->stopped)
1116 start_adc(s);
1117 avail = db->count;
1118 spin_unlock_irqrestore(&s->lock, flags);
1119 if (avail <= 0) {
1120 if (file->f_flags & O_NONBLOCK) {
1121 if (!ret)
1122 ret = -EAGAIN;
1123 return ret;
1124 }
1125 interruptible_sleep_on(&db->wait);
1126 if (signal_pending(current)) {
1127 if (!ret)
1128 ret = -ERESTARTSYS;
1129 return ret;
1130 }
1131 }
1132 } while (avail <= 0);
1133
1134 // copy from nextOut to user
1135 if ((cnt = copy_dmabuf_user(db, buffer, count > avail ?
1136 avail : count, 1)) < 0) {
1137 if (!ret)
1138 ret = -EFAULT;
1139 return ret;
1140 }
1141
1142 spin_lock_irqsave(&s->lock, flags);
1143 db->count -= cnt;
1144 spin_unlock_irqrestore(&s->lock, flags);
1145
1146 db->nextOut += cnt;
1147 if (db->nextOut >= db->rawbuf + db->dmasize)
1148 db->nextOut -= db->dmasize;
1149
1150 count -= cnt;
1151 buffer += cnt;
1152 ret += cnt;
1153 } // while (count > 0)
1154
1155 /*
1156 * See if the dma buffer count after this read call is
1157 * aligned on a fragsize boundary. If not, read from
1158 * buffer until we reach a boundary, and let's hope this
1159 * is just the last remainder of an audio record. If not
1160 * it means the user is not reading in fragsize chunks, in
1161 * which case it's his/her fault that there are audio gaps
1162 * in their record.
1163 */
1164 spin_lock_irqsave(&s->lock, flags);
1165 remainder = db->count % db->fragsize;
1166 if (remainder) {
1167 db->nextOut += remainder;
1168 if (db->nextOut >= db->rawbuf + db->dmasize)
1169 db->nextOut -= db->dmasize;
1170 db->count -= remainder;
1171 }
1172 spin_unlock_irqrestore(&s->lock, flags);
1173
1174 return ret;
1175}
1176
1177static ssize_t it8172_write(struct file *file, const char *buffer,
1178 size_t count, loff_t *ppos)
1179{
1180 struct it8172_state *s = (struct it8172_state *)file->private_data;
1181 struct dmabuf *db = &s->dma_dac;
1182 ssize_t ret;
1183 unsigned long flags;
1184 int cnt, remainder, avail;
1185
1186 if (db->mapped)
1187 return -ENXIO;
1188 if (!access_ok(VERIFY_READ, buffer, count))
1189 return -EFAULT;
1190 ret = 0;
1191
1192 while (count > 0) {
1193 // wait for space in playback buffer
1194 do {
1195 spin_lock_irqsave(&s->lock, flags);
1196 avail = db->dmasize - db->count;
1197 spin_unlock_irqrestore(&s->lock, flags);
1198 if (avail <= 0) {
1199 if (file->f_flags & O_NONBLOCK) {
1200 if (!ret)
1201 ret = -EAGAIN;
1202 return ret;
1203 }
1204 interruptible_sleep_on(&db->wait);
1205 if (signal_pending(current)) {
1206 if (!ret)
1207 ret = -ERESTARTSYS;
1208 return ret;
1209 }
1210 }
1211 } while (avail <= 0);
1212
1213 // copy to nextIn
1214 if ((cnt = copy_dmabuf_user(db, (char*)buffer,
1215 count > avail ?
1216 avail : count, 0)) < 0) {
1217 if (!ret)
1218 ret = -EFAULT;
1219 return ret;
1220 }
1221
1222 spin_lock_irqsave(&s->lock, flags);
1223 db->count += cnt;
1224 if (db->stopped)
1225 start_dac(s);
1226 spin_unlock_irqrestore(&s->lock, flags);
1227
1228 db->nextIn += cnt;
1229 if (db->nextIn >= db->rawbuf + db->dmasize)
1230 db->nextIn -= db->dmasize;
1231
1232 count -= cnt;
1233 buffer += cnt;
1234 ret += cnt;
1235 } // while (count > 0)
1236
1237 /*
1238 * See if the dma buffer count after this write call is
1239 * aligned on a fragsize boundary. If not, fill buffer
1240 * with silence to the next boundary, and let's hope this
1241 * is just the last remainder of an audio playback. If not
1242 * it means the user is not sending us fragsize chunks, in
1243 * which case it's his/her fault that there are audio gaps
1244 * in their playback.
1245 */
1246 spin_lock_irqsave(&s->lock, flags);
1247 remainder = db->count % db->fragsize;
1248 if (remainder) {
1249 int fill_cnt = db->fragsize - remainder;
1250 memset(db->nextIn, 0, fill_cnt);
1251 db->nextIn += fill_cnt;
1252 if (db->nextIn >= db->rawbuf + db->dmasize)
1253 db->nextIn -= db->dmasize;
1254 db->count += fill_cnt;
1255 }
1256 spin_unlock_irqrestore(&s->lock, flags);
1257
1258 return ret;
1259}
1260
1261/* No kernel lock - we have our own spinlock */
1262static unsigned int it8172_poll(struct file *file,
1263 struct poll_table_struct *wait)
1264{
1265 struct it8172_state *s = (struct it8172_state *)file->private_data;
1266 unsigned long flags;
1267 unsigned int mask = 0;
1268
1269 if (file->f_mode & FMODE_WRITE) {
1270 if (!s->dma_dac.ready)
1271 return 0;
1272 poll_wait(file, &s->dma_dac.wait, wait);
1273 }
1274 if (file->f_mode & FMODE_READ) {
1275 if (!s->dma_adc.ready)
1276 return 0;
1277 poll_wait(file, &s->dma_adc.wait, wait);
1278 }
1279
1280 spin_lock_irqsave(&s->lock, flags);
1281 if (file->f_mode & FMODE_READ) {
1282 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1283 mask |= POLLIN | POLLRDNORM;
1284 }
1285 if (file->f_mode & FMODE_WRITE) {
1286 if (s->dma_dac.mapped) {
1287 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1288 mask |= POLLOUT | POLLWRNORM;
1289 } else {
1290 if ((signed)s->dma_dac.dmasize >=
1291 s->dma_dac.count + (signed)s->dma_dac.fragsize)
1292 mask |= POLLOUT | POLLWRNORM;
1293 }
1294 }
1295 spin_unlock_irqrestore(&s->lock, flags);
1296 return mask;
1297}
1298
1299static int it8172_mmap(struct file *file, struct vm_area_struct *vma)
1300{
1301 struct it8172_state *s = (struct it8172_state *)file->private_data;
1302 struct dmabuf *db;
1303 unsigned long size;
1304
1305 lock_kernel();
1306 if (vma->vm_flags & VM_WRITE)
1307 db = &s->dma_dac;
1308 else if (vma->vm_flags & VM_READ)
1309 db = &s->dma_adc;
1310 else {
1311 unlock_kernel();
1312 return -EINVAL;
1313 }
1314 if (vma->vm_pgoff != 0) {
1315 unlock_kernel();
1316 return -EINVAL;
1317 }
1318 size = vma->vm_end - vma->vm_start;
1319 if (size > (PAGE_SIZE << db->buforder)) {
1320 unlock_kernel();
1321 return -EINVAL;
1322 }
1323 if (remap_pfn_range(vma, vma->vm_start,
1324 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1325 size, vma->vm_page_prot)) {
1326 unlock_kernel();
1327 return -EAGAIN;
1328 }
1329 db->mapped = 1;
1330 unlock_kernel();
1331 return 0;
1332}
1333
1334
1335#ifdef IT8172_VERBOSE_DEBUG
1336static struct ioctl_str_t {
1337 unsigned int cmd;
1338 const char* str;
1339} ioctl_str[] = {
1340 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1341 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1342 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1343 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1344 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1345 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1346 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1347 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1348 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1349 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1350 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1351 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1352 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1353 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1354 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1355 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1356 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1357 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1358 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1359 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1360 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1361 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1362 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1363 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1364 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1365 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1366 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1367 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1368 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1369 {OSS_GETVERSION, "OSS_GETVERSION"},
1370 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1371 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1372 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1373 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1374};
1375#endif
1376
1377static int it8172_ioctl(struct inode *inode, struct file *file,
1378 unsigned int cmd, unsigned long arg)
1379{
1380 struct it8172_state *s = (struct it8172_state *)file->private_data;
1381 unsigned long flags;
1382 audio_buf_info abinfo;
1383 count_info cinfo;
1384 int count;
1385 int val, mapped, ret, diff;
1386
1387 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1388 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1389
1390#ifdef IT8172_VERBOSE_DEBUG
1391 for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1392 if (ioctl_str[count].cmd == cmd)
1393 break;
1394 }
1395 if (count < sizeof(ioctl_str)/sizeof(ioctl_str[0]))
1396 dbg("ioctl %s, arg=0x%08x",
1397 ioctl_str[count].str, (unsigned int)arg);
1398 else
1399 dbg("ioctl unknown, 0x%x", cmd);
1400#endif
1401
1402 switch (cmd) {
1403 case OSS_GETVERSION:
1404 return put_user(SOUND_VERSION, (int *)arg);
1405
1406 case SNDCTL_DSP_SYNC:
1407 if (file->f_mode & FMODE_WRITE)
1408 return drain_dac(s, file->f_flags & O_NONBLOCK);
1409 return 0;
1410
1411 case SNDCTL_DSP_SETDUPLEX:
1412 return 0;
1413
1414 case SNDCTL_DSP_GETCAPS:
1415 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1416 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1417
1418 case SNDCTL_DSP_RESET:
1419 if (file->f_mode & FMODE_WRITE) {
1420 stop_dac(s);
1421 synchronize_irq(s->irq);
1422 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1423 s->dma_dac.nextIn = s->dma_dac.nextOut =
1424 s->dma_dac.rawbuf;
1425 }
1426 if (file->f_mode & FMODE_READ) {
1427 stop_adc(s);
1428 synchronize_irq(s->irq);
1429 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1430 s->dma_adc.nextIn = s->dma_adc.nextOut =
1431 s->dma_adc.rawbuf;
1432 }
1433 return 0;
1434
1435 case SNDCTL_DSP_SPEED:
1436 if (get_user(val, (int *)arg))
1437 return -EFAULT;
1438 if (val >= 0) {
1439 if (file->f_mode & FMODE_READ) {
1440 stop_adc(s);
1441 set_adc_rate(s, val);
1442 if ((ret = prog_dmabuf_adc(s)))
1443 return ret;
1444 }
1445 if (file->f_mode & FMODE_WRITE) {
1446 stop_dac(s);
1447 set_dac_rate(s, val);
1448 if ((ret = prog_dmabuf_dac(s)))
1449 return ret;
1450 }
1451 }
1452 return put_user((file->f_mode & FMODE_READ) ?
1453 s->adcrate : s->dacrate, (int *)arg);
1454
1455 case SNDCTL_DSP_STEREO:
1456 if (get_user(val, (int *)arg))
1457 return -EFAULT;
1458 if (file->f_mode & FMODE_READ) {
1459 stop_adc(s);
1460 if (val)
1461 s->capcc |= CC_SM;
1462 else
1463 s->capcc &= ~CC_SM;
1464 outw(s->capcc, s->io+IT_AC_CAPCC);
1465 if ((ret = prog_dmabuf_adc(s)))
1466 return ret;
1467 }
1468 if (file->f_mode & FMODE_WRITE) {
1469 stop_dac(s);
1470 if (val)
1471 s->pcc |= CC_SM;
1472 else
1473 s->pcc &= ~CC_SM;
1474 outw(s->pcc, s->io+IT_AC_PCC);
1475 if ((ret = prog_dmabuf_dac(s)))
1476 return ret;
1477 }
1478 return 0;
1479
1480 case SNDCTL_DSP_CHANNELS:
1481 if (get_user(val, (int *)arg))
1482 return -EFAULT;
1483 if (val != 0) {
1484 if (file->f_mode & FMODE_READ) {
1485 stop_adc(s);
1486 if (val >= 2) {
1487 val = 2;
1488 s->capcc |= CC_SM;
1489 }
1490 else
1491 s->capcc &= ~CC_SM;
1492 outw(s->capcc, s->io+IT_AC_CAPCC);
1493 if ((ret = prog_dmabuf_adc(s)))
1494 return ret;
1495 }
1496 if (file->f_mode & FMODE_WRITE) {
1497 stop_dac(s);
1498 switch (val) {
1499 case 1:
1500 s->pcc &= ~CC_SM;
1501 break;
1502 case 2:
1503 s->pcc |= CC_SM;
1504 break;
1505 default:
1506 // FIX! support multichannel???
1507 val = 2;
1508 s->pcc |= CC_SM;
1509 break;
1510 }
1511 outw(s->pcc, s->io+IT_AC_PCC);
1512 if ((ret = prog_dmabuf_dac(s)))
1513 return ret;
1514 }
1515 }
1516 return put_user(val, (int *)arg);
1517
1518 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1519 return put_user(AFMT_S16_LE|AFMT_U8, (int *)arg);
1520
1521 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1522 if (get_user(val, (int *)arg))
1523 return -EFAULT;
1524 if (val != AFMT_QUERY) {
1525 if (file->f_mode & FMODE_READ) {
1526 stop_adc(s);
1527 if (val == AFMT_S16_LE)
1528 s->capcc |= CC_DF;
1529 else {
1530 val = AFMT_U8;
1531 s->capcc &= ~CC_DF;
1532 }
1533 outw(s->capcc, s->io+IT_AC_CAPCC);
1534 if ((ret = prog_dmabuf_adc(s)))
1535 return ret;
1536 }
1537 if (file->f_mode & FMODE_WRITE) {
1538 stop_dac(s);
1539 if (val == AFMT_S16_LE)
1540 s->pcc |= CC_DF;
1541 else {
1542 val = AFMT_U8;
1543 s->pcc &= ~CC_DF;
1544 }
1545 outw(s->pcc, s->io+IT_AC_PCC);
1546 if ((ret = prog_dmabuf_dac(s)))
1547 return ret;
1548 }
1549 } else {
1550 if (file->f_mode & FMODE_READ)
1551 val = (s->capcc & CC_DF) ?
1552 AFMT_S16_LE : AFMT_U8;
1553 else
1554 val = (s->pcc & CC_DF) ?
1555 AFMT_S16_LE : AFMT_U8;
1556 }
1557 return put_user(val, (int *)arg);
1558
1559 case SNDCTL_DSP_POST:
1560 return 0;
1561
1562 case SNDCTL_DSP_GETTRIGGER:
1563 val = 0;
1564 spin_lock_irqsave(&s->lock, flags);
1565 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1566 val |= PCM_ENABLE_INPUT;
1567 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1568 val |= PCM_ENABLE_OUTPUT;
1569 spin_unlock_irqrestore(&s->lock, flags);
1570 return put_user(val, (int *)arg);
1571
1572 case SNDCTL_DSP_SETTRIGGER:
1573 if (get_user(val, (int *)arg))
1574 return -EFAULT;
1575 if (file->f_mode & FMODE_READ) {
1576 if (val & PCM_ENABLE_INPUT)
1577 start_adc(s);
1578 else
1579 stop_adc(s);
1580 }
1581 if (file->f_mode & FMODE_WRITE) {
1582 if (val & PCM_ENABLE_OUTPUT)
1583 start_dac(s);
1584 else
1585 stop_dac(s);
1586 }
1587 return 0;
1588
1589 case SNDCTL_DSP_GETOSPACE:
1590 if (!(file->f_mode & FMODE_WRITE))
1591 return -EINVAL;
1592 abinfo.fragsize = s->dma_dac.fragsize;
1593 spin_lock_irqsave(&s->lock, flags);
1594 count = s->dma_dac.count;
1595 if (!s->dma_dac.stopped)
1596 count -= (s->dma_dac.fragsize -
1597 inw(s->io+IT_AC_PCDL));
1598 spin_unlock_irqrestore(&s->lock, flags);
1599 if (count < 0)
1600 count = 0;
1601 abinfo.bytes = s->dma_dac.dmasize - count;
1602 abinfo.fragstotal = s->dma_dac.numfrag;
1603 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1604 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ?
1605 -EFAULT : 0;
1606
1607 case SNDCTL_DSP_GETISPACE:
1608 if (!(file->f_mode & FMODE_READ))
1609 return -EINVAL;
1610 abinfo.fragsize = s->dma_adc.fragsize;
1611 spin_lock_irqsave(&s->lock, flags);
1612 count = s->dma_adc.count;
1613 if (!s->dma_adc.stopped)
1614 count += (s->dma_adc.fragsize -
1615 inw(s->io+IT_AC_CAPCDL));
1616 spin_unlock_irqrestore(&s->lock, flags);
1617 if (count < 0)
1618 count = 0;
1619 abinfo.bytes = count;
1620 abinfo.fragstotal = s->dma_adc.numfrag;
1621 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1622 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ?
1623 -EFAULT : 0;
1624
1625 case SNDCTL_DSP_NONBLOCK:
1626 file->f_flags |= O_NONBLOCK;
1627 return 0;
1628
1629 case SNDCTL_DSP_GETODELAY:
1630 if (!(file->f_mode & FMODE_WRITE))
1631 return -EINVAL;
1632 spin_lock_irqsave(&s->lock, flags);
1633 count = s->dma_dac.count;
1634 if (!s->dma_dac.stopped)
1635 count -= (s->dma_dac.fragsize -
1636 inw(s->io+IT_AC_PCDL));
1637 spin_unlock_irqrestore(&s->lock, flags);
1638 if (count < 0)
1639 count = 0;
1640 return put_user(count, (int *)arg);
1641
1642 case SNDCTL_DSP_GETIPTR:
1643 if (!(file->f_mode & FMODE_READ))
1644 return -EINVAL;
1645 spin_lock_irqsave(&s->lock, flags);
1646 cinfo.bytes = s->dma_adc.total_bytes;
1647 count = s->dma_adc.count;
1648 if (!s->dma_adc.stopped) {
1649 diff = s->dma_adc.fragsize - inw(s->io+IT_AC_CAPCDL);
1650 count += diff;
1651 cinfo.bytes += diff;
1652 cinfo.ptr = inl(s->io+s->dma_adc.curBufPtr) -
1653 s->dma_adc.dmaaddr;
1654 } else
1655 cinfo.ptr = virt_to_bus(s->dma_adc.nextIn) -
1656 s->dma_adc.dmaaddr;
1657 if (s->dma_adc.mapped)
1658 s->dma_adc.count &= s->dma_adc.fragsize-1;
1659 spin_unlock_irqrestore(&s->lock, flags);
1660 if (count < 0)
1661 count = 0;
1662 cinfo.blocks = count >> s->dma_adc.fragshift;
1663 if (copy_to_user((void *)arg, &cinfo, sizeof(cinfo)))
1664 return -EFAULT;
1665 return 0;
1666
1667 case SNDCTL_DSP_GETOPTR:
1668 if (!(file->f_mode & FMODE_READ))
1669 return -EINVAL;
1670 spin_lock_irqsave(&s->lock, flags);
1671 cinfo.bytes = s->dma_dac.total_bytes;
1672 count = s->dma_dac.count;
1673 if (!s->dma_dac.stopped) {
1674 diff = s->dma_dac.fragsize - inw(s->io+IT_AC_CAPCDL);
1675 count -= diff;
1676 cinfo.bytes += diff;
1677 cinfo.ptr = inl(s->io+s->dma_dac.curBufPtr) -
1678 s->dma_dac.dmaaddr;
1679 } else
1680 cinfo.ptr = virt_to_bus(s->dma_dac.nextOut) -
1681 s->dma_dac.dmaaddr;
1682 if (s->dma_dac.mapped)
1683 s->dma_dac.count &= s->dma_dac.fragsize-1;
1684 spin_unlock_irqrestore(&s->lock, flags);
1685 if (count < 0)
1686 count = 0;
1687 cinfo.blocks = count >> s->dma_dac.fragshift;
1688 if (copy_to_user((void *)arg, &cinfo, sizeof(cinfo)))
1689 return -EFAULT;
1690 return 0;
1691
1692 case SNDCTL_DSP_GETBLKSIZE:
1693 if (file->f_mode & FMODE_WRITE)
1694 return put_user(s->dma_dac.fragsize, (int *)arg);
1695 else
1696 return put_user(s->dma_adc.fragsize, (int *)arg);
1697
1698 case SNDCTL_DSP_SETFRAGMENT:
1699 if (get_user(val, (int *)arg))
1700 return -EFAULT;
1701 if (file->f_mode & FMODE_READ) {
1702 stop_adc(s);
1703 s->dma_adc.ossfragshift = val & 0xffff;
1704 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1705 if (s->dma_adc.ossfragshift < 4)
1706 s->dma_adc.ossfragshift = 4;
1707 if (s->dma_adc.ossfragshift > 15)
1708 s->dma_adc.ossfragshift = 15;
1709 if (s->dma_adc.ossmaxfrags < 4)
1710 s->dma_adc.ossmaxfrags = 4;
1711 if ((ret = prog_dmabuf_adc(s)))
1712 return ret;
1713 }
1714 if (file->f_mode & FMODE_WRITE) {
1715 stop_dac(s);
1716 s->dma_dac.ossfragshift = val & 0xffff;
1717 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1718 if (s->dma_dac.ossfragshift < 4)
1719 s->dma_dac.ossfragshift = 4;
1720 if (s->dma_dac.ossfragshift > 15)
1721 s->dma_dac.ossfragshift = 15;
1722 if (s->dma_dac.ossmaxfrags < 4)
1723 s->dma_dac.ossmaxfrags = 4;
1724 if ((ret = prog_dmabuf_dac(s)))
1725 return ret;
1726 }
1727 return 0;
1728
1729 case SNDCTL_DSP_SUBDIVIDE:
1730 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1731 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1732 return -EINVAL;
1733 if (get_user(val, (int *)arg))
1734 return -EFAULT;
1735 if (val != 1 && val != 2 && val != 4)
1736 return -EINVAL;
1737 if (file->f_mode & FMODE_READ) {
1738 stop_adc(s);
1739 s->dma_adc.subdivision = val;
1740 if ((ret = prog_dmabuf_adc(s)))
1741 return ret;
1742 }
1743 if (file->f_mode & FMODE_WRITE) {
1744 stop_dac(s);
1745 s->dma_dac.subdivision = val;
1746 if ((ret = prog_dmabuf_dac(s)))
1747 return ret;
1748 }
1749 return 0;
1750
1751 case SOUND_PCM_READ_RATE:
1752 return put_user((file->f_mode & FMODE_READ) ?
1753 s->adcrate : s->dacrate, (int *)arg);
1754
1755 case SOUND_PCM_READ_CHANNELS:
1756 if (file->f_mode & FMODE_READ)
1757 return put_user((s->capcc & CC_SM) ? 2 : 1,
1758 (int *)arg);
1759 else
1760 return put_user((s->pcc & CC_SM) ? 2 : 1,
1761 (int *)arg);
1762
1763 case SOUND_PCM_READ_BITS:
1764 if (file->f_mode & FMODE_READ)
1765 return put_user((s->capcc & CC_DF) ? 16 : 8,
1766 (int *)arg);
1767 else
1768 return put_user((s->pcc & CC_DF) ? 16 : 8,
1769 (int *)arg);
1770
1771 case SOUND_PCM_WRITE_FILTER:
1772 case SNDCTL_DSP_SETSYNCRO:
1773 case SOUND_PCM_READ_FILTER:
1774 return -EINVAL;
1775 }
1776
1777 return mixdev_ioctl(&s->codec, cmd, arg);
1778}
1779
1780
1781static int it8172_open(struct inode *inode, struct file *file)
1782{
1783 int minor = iminor(inode);
1784 DECLARE_WAITQUEUE(wait, current);
1785 unsigned long flags;
1786 struct list_head *list;
1787 struct it8172_state *s;
1788 int ret;
1789
1790#ifdef IT8172_VERBOSE_DEBUG
1791 if (file->f_flags & O_NONBLOCK)
1792 dbg("%s: non-blocking", __FUNCTION__);
1793 else
1794 dbg("%s: blocking", __FUNCTION__);
1795#endif
1796
1797 for (list = devs.next; ; list = list->next) {
1798 if (list == &devs)
1799 return -ENODEV;
1800 s = list_entry(list, struct it8172_state, devs);
1801 if (!((s->dev_audio ^ minor) & ~0xf))
1802 break;
1803 }
1804 file->private_data = s;
1805 /* wait for device to become free */
1806 mutex_lock(&s->open_mutex);
1807 while (s->open_mode & file->f_mode) {
1808 if (file->f_flags & O_NONBLOCK) {
1809 mutex_unlock(&s->open_mutex);
1810 return -EBUSY;
1811 }
1812 add_wait_queue(&s->open_wait, &wait);
1813 __set_current_state(TASK_INTERRUPTIBLE);
1814 mutex_unlock(&s->open_mutex);
1815 schedule();
1816 remove_wait_queue(&s->open_wait, &wait);
1817 set_current_state(TASK_RUNNING);
1818 if (signal_pending(current))
1819 return -ERESTARTSYS;
1820 mutex_lock(&s->open_mutex);
1821 }
1822
1823 spin_lock_irqsave(&s->lock, flags);
1824
1825 if (file->f_mode & FMODE_READ) {
1826 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1827 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1828 s->capcc &= ~(CC_SM | CC_DF);
1829 set_adc_rate(s, 8000);
1830 if ((minor & 0xf) == SND_DEV_DSP16)
1831 s->capcc |= CC_DF;
1832 outw(s->capcc, s->io+IT_AC_CAPCC);
1833 if ((ret = prog_dmabuf_adc(s))) {
1834 spin_unlock_irqrestore(&s->lock, flags);
1835 return ret;
1836 }
1837 }
1838 if (file->f_mode & FMODE_WRITE) {
1839 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1840 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1841 s->pcc &= ~(CC_SM | CC_DF);
1842 set_dac_rate(s, 8000);
1843 if ((minor & 0xf) == SND_DEV_DSP16)
1844 s->pcc |= CC_DF;
1845 outw(s->pcc, s->io+IT_AC_PCC);
1846 if ((ret = prog_dmabuf_dac(s))) {
1847 spin_unlock_irqrestore(&s->lock, flags);
1848 return ret;
1849 }
1850 }
1851
1852 spin_unlock_irqrestore(&s->lock, flags);
1853
1854 s->open_mode |= (file->f_mode & (FMODE_READ | FMODE_WRITE));
1855 mutex_unlock(&s->open_mutex);
1856 return nonseekable_open(inode, file);
1857}
1858
1859static int it8172_release(struct inode *inode, struct file *file)
1860{
1861 struct it8172_state *s = (struct it8172_state *)file->private_data;
1862
1863#ifdef IT8172_VERBOSE_DEBUG
1864 dbg("%s", __FUNCTION__);
1865#endif
1866 lock_kernel();
1867 if (file->f_mode & FMODE_WRITE)
1868 drain_dac(s, file->f_flags & O_NONBLOCK);
1869 mutex_lock(&s->open_mutex);
1870 if (file->f_mode & FMODE_WRITE) {
1871 stop_dac(s);
1872 dealloc_dmabuf(s, &s->dma_dac);
1873 }
1874 if (file->f_mode & FMODE_READ) {
1875 stop_adc(s);
1876 dealloc_dmabuf(s, &s->dma_adc);
1877 }
1878 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1879 mutex_unlock(&s->open_mutex);
1880 wake_up(&s->open_wait);
1881 unlock_kernel();
1882 return 0;
1883}
1884
1885static /*const*/ struct file_operations it8172_audio_fops = {
1886 .owner = THIS_MODULE,
1887 .llseek = no_llseek,
1888 .read = it8172_read,
1889 .write = it8172_write,
1890 .poll = it8172_poll,
1891 .ioctl = it8172_ioctl,
1892 .mmap = it8172_mmap,
1893 .open = it8172_open,
1894 .release = it8172_release,
1895};
1896
1897
1898/* --------------------------------------------------------------------- */
1899
1900
1901/* --------------------------------------------------------------------- */
1902
1903/*
1904 * for debugging purposes, we'll create a proc device that dumps the
1905 * CODEC chipstate
1906 */
1907
1908#ifdef IT8172_DEBUG
1909static int proc_it8172_dump (char *buf, char **start, off_t fpos,
1910 int length, int *eof, void *data)
1911{
1912 struct it8172_state *s;
1913 int cnt, len = 0;
1914
1915 if (list_empty(&devs))
1916 return 0;
1917 s = list_entry(devs.next, struct it8172_state, devs);
1918
1919 /* print out header */
1920 len += sprintf(buf + len, "\n\t\tIT8172 Audio Debug\n\n");
1921
1922 // print out digital controller state
1923 len += sprintf (buf + len, "IT8172 Audio Controller registers\n");
1924 len += sprintf (buf + len, "---------------------------------\n");
1925 cnt=0;
1926 while (cnt < 0x72) {
1927 if (cnt == IT_AC_PCB1STA || cnt == IT_AC_PCB2STA ||
1928 cnt == IT_AC_CAPB1STA || cnt == IT_AC_CAPB2STA ||
1929 cnt == IT_AC_PFDP) {
1930 len+= sprintf (buf + len, "reg %02x = %08x\n",
1931 cnt, inl(s->io+cnt));
1932 cnt += 4;
1933 } else {
1934 len+= sprintf (buf + len, "reg %02x = %04x\n",
1935 cnt, inw(s->io+cnt));
1936 cnt += 2;
1937 }
1938 }
1939
1940 /* print out CODEC state */
1941 len += sprintf (buf + len, "\nAC97 CODEC registers\n");
1942 len += sprintf (buf + len, "----------------------\n");
1943 for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
1944 len+= sprintf (buf + len, "reg %02x = %04x\n",
1945 cnt, rdcodec(&s->codec, cnt));
1946
1947 if (fpos >=len){
1948 *start = buf;
1949 *eof =1;
1950 return 0;
1951 }
1952 *start = buf + fpos;
1953 if ((len -= fpos) > length)
1954 return length;
1955 *eof =1;
1956 return len;
1957
1958}
1959#endif /* IT8172_DEBUG */
1960
1961/* --------------------------------------------------------------------- */
1962
1963/* maximum number of devices; only used for command line params */
1964#define NR_DEVICE 5
1965
1966static int spdif[NR_DEVICE];
1967static int i2s_fmt[NR_DEVICE];
1968
1969static unsigned int devindex;
1970
1971module_param_array(spdif, int, NULL, 0);
1972MODULE_PARM_DESC(spdif, "if 1 the S/PDIF digital output is enabled");
1973module_param_array(i2s_fmt, int, NULL, 0);
1974MODULE_PARM_DESC(i2s_fmt, "the format of I2S");
1975
1976MODULE_AUTHOR("Monta Vista Software, stevel@mvista.com");
1977MODULE_DESCRIPTION("IT8172 Audio Driver");
1978
1979/* --------------------------------------------------------------------- */
1980
1981static int __devinit it8172_probe(struct pci_dev *pcidev,
1982 const struct pci_device_id *pciid)
1983{
1984 struct it8172_state *s;
1985 int i, val;
1986 unsigned short pcisr, vol;
1987 unsigned char legacy, imc;
1988 char proc_str[80];
1989
1990 if (pcidev->irq == 0)
1991 return -1;
1992
1993 if (!(s = kmalloc(sizeof(struct it8172_state), GFP_KERNEL))) {
1994 err("alloc of device struct failed");
1995 return -1;
1996 }
1997
1998 memset(s, 0, sizeof(struct it8172_state));
1999 init_waitqueue_head(&s->dma_adc.wait);
2000 init_waitqueue_head(&s->dma_dac.wait);
2001 init_waitqueue_head(&s->open_wait);
2002 mutex_init(&s->open_mutex);
2003 spin_lock_init(&s->lock);
2004 s->dev = pcidev;
2005 s->io = pci_resource_start(pcidev, 0);
2006 s->irq = pcidev->irq;
2007 s->vendor = pcidev->vendor;
2008 s->device = pcidev->device;
2009 pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
2010 s->codec.private_data = s;
2011 s->codec.id = 0;
2012 s->codec.codec_read = rdcodec;
2013 s->codec.codec_write = wrcodec;
2014 s->codec.codec_wait = waitcodec;
2015
2016 if (!request_region(s->io, pci_resource_len(pcidev,0),
2017 IT8172_MODULE_NAME)) {
2018 err("io ports %#lx->%#lx in use",
2019 s->io, s->io + pci_resource_len(pcidev,0)-1);
2020 goto err_region;
2021 }
2022 if (request_irq(s->irq, it8172_interrupt, IRQF_DISABLED,
2023 IT8172_MODULE_NAME, s)) {
2024 err("irq %u in use", s->irq);
2025 goto err_irq;
2026 }
2027
2028 info("IO at %#lx, IRQ %d", s->io, s->irq);
2029
2030 /* register devices */
2031 if ((s->dev_audio = register_sound_dsp(&it8172_audio_fops, -1)) < 0)
2032 goto err_dev1;
2033 if ((s->codec.dev_mixer =
2034 register_sound_mixer(&it8172_mixer_fops, -1)) < 0)
2035 goto err_dev2;
2036
2037#ifdef IT8172_DEBUG
2038 /* initialize the debug proc device */
2039 s->ps = create_proc_read_entry(IT8172_MODULE_NAME, 0, NULL,
2040 proc_it8172_dump, NULL);
2041#endif /* IT8172_DEBUG */
2042
2043 /*
2044 * Reset the Audio device using the IT8172 PCI Reset register. This
2045 * creates an audible double click on a speaker connected to Line-out.
2046 */
2047 IT_IO_READ16(IT_PM_PCISR, pcisr);
2048 pcisr |= IT_PM_PCISR_ACSR;
2049 IT_IO_WRITE16(IT_PM_PCISR, pcisr);
2050 /* wait up to 100msec for reset to complete */
2051 for (i=0; pcisr & IT_PM_PCISR_ACSR; i++) {
2052 it8172_delay(10);
2053 if (i == 10)
2054 break;
2055 IT_IO_READ16(IT_PM_PCISR, pcisr);
2056 }
2057 if (i == 10) {
2058 err("chip reset timeout!");
2059 goto err_dev3;
2060 }
2061
2062 /* enable pci io and bus mastering */
2063 if (pci_enable_device(pcidev))
2064 goto err_dev3;
2065 pci_set_master(pcidev);
2066
2067 /* get out of legacy mode */
2068 pci_read_config_byte (pcidev, 0x40, &legacy);
2069 pci_write_config_byte (pcidev, 0x40, legacy & ~1);
2070
2071 s->spdif_volume = -1;
2072 /* check to see if s/pdif mode is being requested */
2073 if (spdif[devindex]) {
2074 info("enabling S/PDIF output");
2075 s->spdif_volume = 0;
2076 outb(GC_SOE, s->io+IT_AC_GC);
2077 } else {
2078 info("disabling S/PDIF output");
2079 outb(0, s->io+IT_AC_GC);
2080 }
2081
2082 /* check to see if I2S format requested */
2083 if (i2s_fmt[devindex]) {
2084 info("setting I2S format to 0x%02x", i2s_fmt[devindex]);
2085 outb(i2s_fmt[devindex], s->io+IT_AC_I2SMC);
2086 } else {
2087 outb(I2SMC_I2SF_I2S, s->io+IT_AC_I2SMC);
2088 }
2089
2090 /* cold reset the AC97 */
2091 outw(CODECC_CR, s->io+IT_AC_CODECC);
2092 udelay(1000);
2093 outw(0, s->io+IT_AC_CODECC);
2094 /* need to delay around 500msec(bleech) to give
2095 some CODECs enough time to wakeup */
2096 it8172_delay(500);
2097
2098 /* AC97 warm reset to start the bitclk */
2099 outw(CODECC_WR, s->io+IT_AC_CODECC);
2100 udelay(1000);
2101 outw(0, s->io+IT_AC_CODECC);
2102
2103 /* codec init */
2104 if (!ac97_probe_codec(&s->codec))
2105 goto err_dev3;
2106
2107 /* add I2S as allowable recording source */
2108 s->codec.record_sources |= SOUND_MASK_I2S;
2109
2110 /* Enable Volume button interrupts */
2111 imc = inb(s->io+IT_AC_IMC);
2112 outb(imc & ~IMC_VCIM, s->io+IT_AC_IMC);
2113
2114 /* Un-mute PCM and FM out on the controller */
2115 vol = inw(s->io+IT_AC_PCMOV);
2116 outw(vol & ~PCMOV_PCMOM, s->io+IT_AC_PCMOV);
2117 vol = inw(s->io+IT_AC_FMOV);
2118 outw(vol & ~FMOV_FMOM, s->io+IT_AC_FMOV);
2119
2120 /* set channel defaults to 8-bit, mono, 8 Khz */
2121 s->pcc = 0;
2122 s->capcc = 0;
2123 set_dac_rate(s, 8000);
2124 set_adc_rate(s, 8000);
2125
2126 /* set mic to be the recording source */
2127 val = SOUND_MASK_MIC;
2128 mixdev_ioctl(&s->codec, SOUND_MIXER_WRITE_RECSRC,
2129 (unsigned long)&val);
2130
2131 /* mute AC'97 master and PCM when in S/PDIF mode */
2132 if (s->spdif_volume != -1) {
2133 val = 0x0000;
2134 s->codec.mixer_ioctl(&s->codec, SOUND_MIXER_WRITE_VOLUME,
2135 (unsigned long)&val);
2136 s->codec.mixer_ioctl(&s->codec, SOUND_MIXER_WRITE_PCM,
2137 (unsigned long)&val);
2138 }
2139
2140#ifdef IT8172_DEBUG
2141 sprintf(proc_str, "driver/%s/%d/ac97", IT8172_MODULE_NAME,
2142 s->codec.id);
2143 s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL,
2144 ac97_read_proc, &s->codec);
2145#endif
2146
2147 /* store it in the driver field */
2148 pci_set_drvdata(pcidev, s);
2149 pcidev->dma_mask = 0xffffffff;
2150 /* put it into driver list */
2151 list_add_tail(&s->devs, &devs);
2152 /* increment devindex */
2153 if (devindex < NR_DEVICE-1)
2154 devindex++;
2155 return 0;
2156
2157 err_dev3:
2158 unregister_sound_mixer(s->codec.dev_mixer);
2159 err_dev2:
2160 unregister_sound_dsp(s->dev_audio);
2161 err_dev1:
2162 err("cannot register misc device");
2163 free_irq(s->irq, s);
2164 err_irq:
2165 release_region(s->io, pci_resource_len(pcidev,0));
2166 err_region:
2167 kfree(s);
2168 return -1;
2169}
2170
2171static void __devexit it8172_remove(struct pci_dev *dev)
2172{
2173 struct it8172_state *s = pci_get_drvdata(dev);
2174
2175 if (!s)
2176 return;
2177 list_del(&s->devs);
2178#ifdef IT8172_DEBUG
2179 if (s->ps)
2180 remove_proc_entry(IT8172_MODULE_NAME, NULL);
2181#endif /* IT8172_DEBUG */
2182 synchronize_irq(s->irq);
2183 free_irq(s->irq, s);
2184 release_region(s->io, pci_resource_len(dev,0));
2185 unregister_sound_dsp(s->dev_audio);
2186 unregister_sound_mixer(s->codec.dev_mixer);
2187 kfree(s);
2188 pci_set_drvdata(dev, NULL);
2189}
2190
2191
2192
2193static struct pci_device_id id_table[] = {
2194 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G_AUDIO, PCI_ANY_ID,
2195 PCI_ANY_ID, 0, 0 },
2196 { 0, }
2197};
2198
2199MODULE_DEVICE_TABLE(pci, id_table);
2200
2201static struct pci_driver it8172_driver = {
2202 .name = IT8172_MODULE_NAME,
2203 .id_table = id_table,
2204 .probe = it8172_probe,
2205 .remove = __devexit_p(it8172_remove)
2206};
2207
2208static int __init init_it8172(void)
2209{
2210 info("version v0.5 time " __TIME__ " " __DATE__);
2211 return pci_register_driver(&it8172_driver);
2212}
2213
2214static void __exit cleanup_it8172(void)
2215{
2216 info("unloading");
2217 pci_unregister_driver(&it8172_driver);
2218}
2219
2220module_init(init_it8172);
2221module_exit(cleanup_it8172);
2222
2223/* --------------------------------------------------------------------- */
2224
2225#ifndef MODULE
2226
2227/* format is: it8172=[spdif],[i2s:<I2S format>] */
2228
2229static int __init it8172_setup(char *options)
2230{
2231 char* this_opt;
2232 static unsigned __initdata nr_dev = 0;
2233
2234 if (nr_dev >= NR_DEVICE)
2235 return 0;
2236
2237 if (!options || !*options)
2238 return 0;
2239
2240 while (this_opt = strsep(&options, ",")) {
2241 if (!*this_opt)
2242 continue;
2243 if (!strncmp(this_opt, "spdif", 5)) {
2244 spdif[nr_dev] = 1;
2245 } else if (!strncmp(this_opt, "i2s:", 4)) {
2246 if (!strncmp(this_opt+4, "dac", 3))
2247 i2s_fmt[nr_dev] = I2SMC_I2SF_DAC;
2248 else if (!strncmp(this_opt+4, "adc", 3))
2249 i2s_fmt[nr_dev] = I2SMC_I2SF_ADC;
2250 else if (!strncmp(this_opt+4, "i2s", 3))
2251 i2s_fmt[nr_dev] = I2SMC_I2SF_I2S;
2252 }
2253 }
2254
2255 nr_dev++;
2256 return 1;
2257}
2258
2259__setup("it8172=", it8172_setup);
2260
2261#endif /* MODULE */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 19:20:48 -0500