aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/net/tg3.c417
-rw-r--r--drivers/net/tg3.h15
-rw-r--r--drivers/usb/atm/speedtch.c12
-rw-r--r--include/linux/netfilter_ipv4/ip_conntrack.h2
-rw-r--r--include/linux/pci_ids.h2
-rw-r--r--net/xfrm/xfrm_user.c3
6 files changed, 390 insertions, 61 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 54640686e983..201a550f0bcc 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -66,8 +66,8 @@
66 66
67#define DRV_MODULE_NAME "tg3" 67#define DRV_MODULE_NAME "tg3"
68#define PFX DRV_MODULE_NAME ": " 68#define PFX DRV_MODULE_NAME ": "
69#define DRV_MODULE_VERSION "3.33" 69#define DRV_MODULE_VERSION "3.34"
70#define DRV_MODULE_RELDATE "July 5, 2005" 70#define DRV_MODULE_RELDATE "July 25, 2005"
71 71
72#define TG3_DEF_MAC_MODE 0 72#define TG3_DEF_MAC_MODE 0
73#define TG3_DEF_RX_MODE 0 73#define TG3_DEF_RX_MODE 0
@@ -90,7 +90,7 @@
90/* hardware minimum and maximum for a single frame's data payload */ 90/* hardware minimum and maximum for a single frame's data payload */
91#define TG3_MIN_MTU 60 91#define TG3_MIN_MTU 60
92#define TG3_MAX_MTU(tp) \ 92#define TG3_MAX_MTU(tp) \
93 (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500) 93 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
94 94
95/* These numbers seem to be hard coded in the NIC firmware somehow. 95/* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place 96 * You can't change the ring sizes, but you can change where you place
@@ -221,6 +221,10 @@ static struct pci_device_id tg3_pci_tbl[] = {
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
222 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F, 222 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
224 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
226 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
224 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781, 228 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
226 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX, 230 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
@@ -508,6 +512,9 @@ static void tg3_switch_clocks(struct tg3 *tp)
508 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); 512 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
509 u32 orig_clock_ctrl; 513 u32 orig_clock_ctrl;
510 514
515 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
516 return;
517
511 orig_clock_ctrl = clock_ctrl; 518 orig_clock_ctrl = clock_ctrl;
512 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | 519 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
513 CLOCK_CTRL_CLKRUN_OENABLE | 520 CLOCK_CTRL_CLKRUN_OENABLE |
@@ -907,7 +914,7 @@ out:
907 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 914 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
908 /* Cannot do read-modify-write on 5401 */ 915 /* Cannot do read-modify-write on 5401 */
909 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); 916 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
910 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 917 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
911 u32 phy_reg; 918 u32 phy_reg;
912 919
913 /* Set bit 14 with read-modify-write to preserve other bits */ 920 /* Set bit 14 with read-modify-write to preserve other bits */
@@ -919,7 +926,7 @@ out:
919 /* Set phy register 0x10 bit 0 to high fifo elasticity to support 926 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
920 * jumbo frames transmission. 927 * jumbo frames transmission.
921 */ 928 */
922 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 929 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
923 u32 phy_reg; 930 u32 phy_reg;
924 931
925 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) 932 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
@@ -1093,7 +1100,7 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1093 tp->link_config.orig_autoneg = tp->link_config.autoneg; 1100 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1094 } 1101 }
1095 1102
1096 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { 1103 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1097 tp->link_config.speed = SPEED_10; 1104 tp->link_config.speed = SPEED_10;
1098 tp->link_config.duplex = DUPLEX_HALF; 1105 tp->link_config.duplex = DUPLEX_HALF;
1099 tp->link_config.autoneg = AUTONEG_ENABLE; 1106 tp->link_config.autoneg = AUTONEG_ENABLE;
@@ -1145,6 +1152,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1145 CLOCK_CTRL_ALTCLK | 1152 CLOCK_CTRL_ALTCLK |
1146 CLOCK_CTRL_PWRDOWN_PLL133); 1153 CLOCK_CTRL_PWRDOWN_PLL133);
1147 udelay(40); 1154 udelay(40);
1155 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
1156 /* do nothing */
1148 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && 1157 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1149 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { 1158 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1150 u32 newbits1, newbits2; 1159 u32 newbits1, newbits2;
@@ -1238,6 +1247,25 @@ static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv
1238 u32 old_tx_mode = tp->tx_mode; 1247 u32 old_tx_mode = tp->tx_mode;
1239 1248
1240 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) { 1249 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1250
1251 /* Convert 1000BaseX flow control bits to 1000BaseT
1252 * bits before resolving flow control.
1253 */
1254 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1255 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1256 ADVERTISE_PAUSE_ASYM);
1257 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1258
1259 if (local_adv & ADVERTISE_1000XPAUSE)
1260 local_adv |= ADVERTISE_PAUSE_CAP;
1261 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1262 local_adv |= ADVERTISE_PAUSE_ASYM;
1263 if (remote_adv & LPA_1000XPAUSE)
1264 remote_adv |= LPA_PAUSE_CAP;
1265 if (remote_adv & LPA_1000XPAUSE_ASYM)
1266 remote_adv |= LPA_PAUSE_ASYM;
1267 }
1268
1241 if (local_adv & ADVERTISE_PAUSE_CAP) { 1269 if (local_adv & ADVERTISE_PAUSE_CAP) {
1242 if (local_adv & ADVERTISE_PAUSE_ASYM) { 1270 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1243 if (remote_adv & LPA_PAUSE_CAP) 1271 if (remote_adv & LPA_PAUSE_CAP)
@@ -2498,12 +2526,226 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2498 return 0; 2526 return 0;
2499} 2527}
2500 2528
2529static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2530{
2531 int current_link_up, err = 0;
2532 u32 bmsr, bmcr;
2533 u16 current_speed;
2534 u8 current_duplex;
2535
2536 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2537 tw32_f(MAC_MODE, tp->mac_mode);
2538 udelay(40);
2539
2540 tw32(MAC_EVENT, 0);
2541
2542 tw32_f(MAC_STATUS,
2543 (MAC_STATUS_SYNC_CHANGED |
2544 MAC_STATUS_CFG_CHANGED |
2545 MAC_STATUS_MI_COMPLETION |
2546 MAC_STATUS_LNKSTATE_CHANGED));
2547 udelay(40);
2548
2549 if (force_reset)
2550 tg3_phy_reset(tp);
2551
2552 current_link_up = 0;
2553 current_speed = SPEED_INVALID;
2554 current_duplex = DUPLEX_INVALID;
2555
2556 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2557 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2558
2559 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2560
2561 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2562 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2563 /* do nothing, just check for link up at the end */
2564 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2565 u32 adv, new_adv;
2566
2567 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2568 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2569 ADVERTISE_1000XPAUSE |
2570 ADVERTISE_1000XPSE_ASYM |
2571 ADVERTISE_SLCT);
2572
2573 /* Always advertise symmetric PAUSE just like copper */
2574 new_adv |= ADVERTISE_1000XPAUSE;
2575
2576 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2577 new_adv |= ADVERTISE_1000XHALF;
2578 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2579 new_adv |= ADVERTISE_1000XFULL;
2580
2581 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2582 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2583 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2584 tg3_writephy(tp, MII_BMCR, bmcr);
2585
2586 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2587 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2588 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2589
2590 return err;
2591 }
2592 } else {
2593 u32 new_bmcr;
2594
2595 bmcr &= ~BMCR_SPEED1000;
2596 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2597
2598 if (tp->link_config.duplex == DUPLEX_FULL)
2599 new_bmcr |= BMCR_FULLDPLX;
2600
2601 if (new_bmcr != bmcr) {
2602 /* BMCR_SPEED1000 is a reserved bit that needs
2603 * to be set on write.
2604 */
2605 new_bmcr |= BMCR_SPEED1000;
2606
2607 /* Force a linkdown */
2608 if (netif_carrier_ok(tp->dev)) {
2609 u32 adv;
2610
2611 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2612 adv &= ~(ADVERTISE_1000XFULL |
2613 ADVERTISE_1000XHALF |
2614 ADVERTISE_SLCT);
2615 tg3_writephy(tp, MII_ADVERTISE, adv);
2616 tg3_writephy(tp, MII_BMCR, bmcr |
2617 BMCR_ANRESTART |
2618 BMCR_ANENABLE);
2619 udelay(10);
2620 netif_carrier_off(tp->dev);
2621 }
2622 tg3_writephy(tp, MII_BMCR, new_bmcr);
2623 bmcr = new_bmcr;
2624 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2625 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2626 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2627 }
2628 }
2629
2630 if (bmsr & BMSR_LSTATUS) {
2631 current_speed = SPEED_1000;
2632 current_link_up = 1;
2633 if (bmcr & BMCR_FULLDPLX)
2634 current_duplex = DUPLEX_FULL;
2635 else
2636 current_duplex = DUPLEX_HALF;
2637
2638 if (bmcr & BMCR_ANENABLE) {
2639 u32 local_adv, remote_adv, common;
2640
2641 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2642 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2643 common = local_adv & remote_adv;
2644 if (common & (ADVERTISE_1000XHALF |
2645 ADVERTISE_1000XFULL)) {
2646 if (common & ADVERTISE_1000XFULL)
2647 current_duplex = DUPLEX_FULL;
2648 else
2649 current_duplex = DUPLEX_HALF;
2650
2651 tg3_setup_flow_control(tp, local_adv,
2652 remote_adv);
2653 }
2654 else
2655 current_link_up = 0;
2656 }
2657 }
2658
2659 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2660 if (tp->link_config.active_duplex == DUPLEX_HALF)
2661 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2662
2663 tw32_f(MAC_MODE, tp->mac_mode);
2664 udelay(40);
2665
2666 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2667
2668 tp->link_config.active_speed = current_speed;
2669 tp->link_config.active_duplex = current_duplex;
2670
2671 if (current_link_up != netif_carrier_ok(tp->dev)) {
2672 if (current_link_up)
2673 netif_carrier_on(tp->dev);
2674 else {
2675 netif_carrier_off(tp->dev);
2676 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2677 }
2678 tg3_link_report(tp);
2679 }
2680 return err;
2681}
2682
2683static void tg3_serdes_parallel_detect(struct tg3 *tp)
2684{
2685 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2686 /* Give autoneg time to complete. */
2687 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2688 return;
2689 }
2690 if (!netif_carrier_ok(tp->dev) &&
2691 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2692 u32 bmcr;
2693
2694 tg3_readphy(tp, MII_BMCR, &bmcr);
2695 if (bmcr & BMCR_ANENABLE) {
2696 u32 phy1, phy2;
2697
2698 /* Select shadow register 0x1f */
2699 tg3_writephy(tp, 0x1c, 0x7c00);
2700 tg3_readphy(tp, 0x1c, &phy1);
2701
2702 /* Select expansion interrupt status register */
2703 tg3_writephy(tp, 0x17, 0x0f01);
2704 tg3_readphy(tp, 0x15, &phy2);
2705 tg3_readphy(tp, 0x15, &phy2);
2706
2707 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2708 /* We have signal detect and not receiving
2709 * config code words, link is up by parallel
2710 * detection.
2711 */
2712
2713 bmcr &= ~BMCR_ANENABLE;
2714 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2715 tg3_writephy(tp, MII_BMCR, bmcr);
2716 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2717 }
2718 }
2719 }
2720 else if (netif_carrier_ok(tp->dev) &&
2721 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2722 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2723 u32 phy2;
2724
2725 /* Select expansion interrupt status register */
2726 tg3_writephy(tp, 0x17, 0x0f01);
2727 tg3_readphy(tp, 0x15, &phy2);
2728 if (phy2 & 0x20) {
2729 u32 bmcr;
2730
2731 /* Config code words received, turn on autoneg. */
2732 tg3_readphy(tp, MII_BMCR, &bmcr);
2733 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2734
2735 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2736
2737 }
2738 }
2739}
2740
2501static int tg3_setup_phy(struct tg3 *tp, int force_reset) 2741static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2502{ 2742{
2503 int err; 2743 int err;
2504 2744
2505 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { 2745 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2506 err = tg3_setup_fiber_phy(tp, force_reset); 2746 err = tg3_setup_fiber_phy(tp, force_reset);
2747 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2748 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2507 } else { 2749 } else {
2508 err = tg3_setup_copper_phy(tp, force_reset); 2750 err = tg3_setup_copper_phy(tp, force_reset);
2509 } 2751 }
@@ -2612,7 +2854,7 @@ static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2612 map = &tp->rx_std_buffers[dest_idx]; 2854 map = &tp->rx_std_buffers[dest_idx];
2613 if (src_idx >= 0) 2855 if (src_idx >= 0)
2614 src_map = &tp->rx_std_buffers[src_idx]; 2856 src_map = &tp->rx_std_buffers[src_idx];
2615 skb_size = RX_PKT_BUF_SZ; 2857 skb_size = tp->rx_pkt_buf_sz;
2616 break; 2858 break;
2617 2859
2618 case RXD_OPAQUE_RING_JUMBO: 2860 case RXD_OPAQUE_RING_JUMBO:
@@ -3434,10 +3676,18 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3434{ 3676{
3435 dev->mtu = new_mtu; 3677 dev->mtu = new_mtu;
3436 3678
3437 if (new_mtu > ETH_DATA_LEN) 3679 if (new_mtu > ETH_DATA_LEN) {
3438 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE; 3680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
3439 else 3681 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
3440 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE; 3682 ethtool_op_set_tso(dev, 0);
3683 }
3684 else
3685 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
3686 } else {
3687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
3688 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
3689 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
3690 }
3441} 3691}
3442 3692
3443static int tg3_change_mtu(struct net_device *dev, int new_mtu) 3693static int tg3_change_mtu(struct net_device *dev, int new_mtu)
@@ -3491,7 +3741,7 @@ static void tg3_free_rings(struct tg3 *tp)
3491 continue; 3741 continue;
3492 pci_unmap_single(tp->pdev, 3742 pci_unmap_single(tp->pdev,
3493 pci_unmap_addr(rxp, mapping), 3743 pci_unmap_addr(rxp, mapping),
3494 RX_PKT_BUF_SZ - tp->rx_offset, 3744 tp->rx_pkt_buf_sz - tp->rx_offset,
3495 PCI_DMA_FROMDEVICE); 3745 PCI_DMA_FROMDEVICE);
3496 dev_kfree_skb_any(rxp->skb); 3746 dev_kfree_skb_any(rxp->skb);
3497 rxp->skb = NULL; 3747 rxp->skb = NULL;
@@ -3564,6 +3814,11 @@ static void tg3_init_rings(struct tg3 *tp)
3564 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); 3814 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3565 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES); 3815 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3566 3816
3817 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
3818 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) &&
3819 (tp->dev->mtu > ETH_DATA_LEN))
3820 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
3821
3567 /* Initialize invariants of the rings, we only set this 3822 /* Initialize invariants of the rings, we only set this
3568 * stuff once. This works because the card does not 3823 * stuff once. This works because the card does not
3569 * write into the rx buffer posting rings. 3824 * write into the rx buffer posting rings.
@@ -3572,14 +3827,14 @@ static void tg3_init_rings(struct tg3 *tp)
3572 struct tg3_rx_buffer_desc *rxd; 3827 struct tg3_rx_buffer_desc *rxd;
3573 3828
3574 rxd = &tp->rx_std[i]; 3829 rxd = &tp->rx_std[i];
3575 rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64) 3830 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
3576 << RXD_LEN_SHIFT; 3831 << RXD_LEN_SHIFT;
3577 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); 3832 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3578 rxd->opaque = (RXD_OPAQUE_RING_STD | 3833 rxd->opaque = (RXD_OPAQUE_RING_STD |
3579 (i << RXD_OPAQUE_INDEX_SHIFT)); 3834 (i << RXD_OPAQUE_INDEX_SHIFT));
3580 } 3835 }
3581 3836
3582 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { 3837 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3583 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { 3838 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3584 struct tg3_rx_buffer_desc *rxd; 3839 struct tg3_rx_buffer_desc *rxd;
3585 3840
@@ -3600,7 +3855,7 @@ static void tg3_init_rings(struct tg3 *tp)
3600 break; 3855 break;
3601 } 3856 }
3602 3857
3603 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { 3858 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3604 for (i = 0; i < tp->rx_jumbo_pending; i++) { 3859 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3605 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO, 3860 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3606 -1, i) < 0) 3861 -1, i) < 0)
@@ -4056,7 +4311,30 @@ static int tg3_chip_reset(struct tg3 *tp)
4056 val &= ~PCIX_CAPS_RELAXED_ORDERING; 4311 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4057 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val); 4312 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4058 4313
4059 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); 4314 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
4315 u32 val;
4316
4317 /* Chip reset on 5780 will reset MSI enable bit,
4318 * so need to restore it.
4319 */
4320 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4321 u16 ctrl;
4322
4323 pci_read_config_word(tp->pdev,
4324 tp->msi_cap + PCI_MSI_FLAGS,
4325 &ctrl);
4326 pci_write_config_word(tp->pdev,
4327 tp->msi_cap + PCI_MSI_FLAGS,
4328 ctrl | PCI_MSI_FLAGS_ENABLE);
4329 val = tr32(MSGINT_MODE);
4330 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4331 }
4332
4333 val = tr32(MEMARB_MODE);
4334 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4335
4336 } else
4337 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4060 4338
4061 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { 4339 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4062 tg3_stop_fw(tp); 4340 tg3_stop_fw(tp);
@@ -4082,6 +4360,9 @@ static int tg3_chip_reset(struct tg3 *tp)
4082 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { 4360 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4083 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; 4361 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4084 tw32_f(MAC_MODE, tp->mac_mode); 4362 tw32_f(MAC_MODE, tp->mac_mode);
4363 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4364 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4365 tw32_f(MAC_MODE, tp->mac_mode);
4085 } else 4366 } else
4086 tw32_f(MAC_MODE, 0); 4367 tw32_f(MAC_MODE, 0);
4087 udelay(40); 4368 udelay(40);
@@ -5245,7 +5526,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5245 } 5526 }
5246#endif 5527#endif
5247 5528
5248 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) { 5529 if (tp->dev->mtu <= ETH_DATA_LEN) {
5249 tw32(BUFMGR_MB_RDMA_LOW_WATER, 5530 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5250 tp->bufmgr_config.mbuf_read_dma_low_water); 5531 tp->bufmgr_config.mbuf_read_dma_low_water);
5251 tw32(BUFMGR_MB_MACRX_LOW_WATER, 5532 tw32(BUFMGR_MB_MACRX_LOW_WATER,
@@ -5320,7 +5601,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5320 /* Setup replenish threshold. */ 5601 /* Setup replenish threshold. */
5321 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); 5602 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5322 5603
5323 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { 5604 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5324 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, 5605 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5325 ((u64) tp->rx_jumbo_mapping >> 32)); 5606 ((u64) tp->rx_jumbo_mapping >> 32));
5326 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 5607 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
@@ -5381,7 +5662,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5381 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, 5662 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5382 tp->rx_std_ptr); 5663 tp->rx_std_ptr);
5383 5664
5384 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ? 5665 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
5385 tp->rx_jumbo_pending : 0; 5666 tp->rx_jumbo_pending : 0;
5386 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 5667 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5387 tp->rx_jumbo_ptr); 5668 tp->rx_jumbo_ptr);
@@ -5683,7 +5964,8 @@ static int tg3_reset_hw(struct tg3 *tp)
5683 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); 5964 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
5684 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); 5965 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5685 5966
5686 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) 5967 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
5968 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780))
5687 limit = 8; 5969 limit = 8;
5688 else 5970 else
5689 limit = 16; 5971 limit = 16;
@@ -5865,7 +6147,8 @@ static void tg3_timer(unsigned long __opaque)
5865 udelay(40); 6147 udelay(40);
5866 tg3_setup_phy(tp, 0); 6148 tg3_setup_phy(tp, 0);
5867 } 6149 }
5868 } 6150 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6151 tg3_serdes_parallel_detect(tp);
5869 6152
5870 tp->timer_counter = tp->timer_multiplier; 6153 tp->timer_counter = tp->timer_multiplier;
5871 } 6154 }
@@ -8569,8 +8852,12 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
8569 eeprom_phy_id = 0; 8852 eeprom_phy_id = 0;
8570 8853
8571 tp->phy_id = eeprom_phy_id; 8854 tp->phy_id = eeprom_phy_id;
8572 if (eeprom_phy_serdes) 8855 if (eeprom_phy_serdes) {
8573 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; 8856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8857 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
8858 else
8859 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8860 }
8574 8861
8575 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) 8862 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8576 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | 8863 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
@@ -8705,7 +8992,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
8705 } 8992 }
8706 } 8993 }
8707 8994
8708 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && 8995 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
8709 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { 8996 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
8710 u32 bmsr, adv_reg, tg3_ctrl; 8997 u32 bmsr, adv_reg, tg3_ctrl;
8711 8998
@@ -8758,7 +9045,7 @@ skip_phy_reset:
8758 err = tg3_init_5401phy_dsp(tp); 9045 err = tg3_init_5401phy_dsp(tp);
8759 } 9046 }
8760 9047
8761 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) 9048 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8762 tp->link_config.advertising = 9049 tp->link_config.advertising =
8763 (ADVERTISED_1000baseT_Half | 9050 (ADVERTISED_1000baseT_Half |
8764 ADVERTISED_1000baseT_Full | 9051 ADVERTISED_1000baseT_Full |
@@ -8928,6 +9215,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
8928 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) 9215 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
8929 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; 9216 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
8930 9217
9218 /* Find msi capability. */
9219 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9220 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
9221
8931 /* Initialize misc host control in PCI block. */ 9222 /* Initialize misc host control in PCI block. */
8932 tp->misc_host_ctrl |= (misc_ctrl_reg & 9223 tp->misc_host_ctrl |= (misc_ctrl_reg &
8933 MISC_HOST_CTRL_CHIPREV); 9224 MISC_HOST_CTRL_CHIPREV);
@@ -8943,7 +9234,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
8943 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff; 9234 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
8944 9235
8945 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 9236 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8946 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) 9237 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
9238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8947 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; 9239 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
8948 9240
8949 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || 9241 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
@@ -8953,6 +9245,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
8953 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) 9245 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8954 tp->tg3_flags2 |= TG3_FLG2_HW_TSO; 9246 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
8955 9247
9248 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
9249 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
9250 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
9251 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
9252
8956 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0) 9253 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
8957 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; 9254 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
8958 9255
@@ -9079,8 +9376,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
9079 /* Derive initial jumbo mode from MTU assigned in 9376 /* Derive initial jumbo mode from MTU assigned in
9080 * ether_setup() via the alloc_etherdev() call 9377 * ether_setup() via the alloc_etherdev() call
9081 */ 9378 */
9082 if (tp->dev->mtu > ETH_DATA_LEN) 9379 if (tp->dev->mtu > ETH_DATA_LEN &&
9083 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE; 9380 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780)
9381 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
9084 9382
9085 /* Determine WakeOnLan speed to use. */ 9383 /* Determine WakeOnLan speed to use. */
9086 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 9384 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
@@ -9096,7 +9394,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
9096 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || 9394 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9097 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && 9395 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9098 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && 9396 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
9099 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) 9397 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
9398 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9100 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED; 9399 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9101 9400
9102 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || 9401 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
@@ -9305,8 +9604,9 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
9305#endif 9604#endif
9306 9605
9307 mac_offset = 0x7c; 9606 mac_offset = 0x7c;
9308 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && 9607 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9309 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) { 9608 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
9609 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
9310 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) 9610 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9311 mac_offset = 0xcc; 9611 mac_offset = 0xcc;
9312 if (tg3_nvram_lock(tp)) 9612 if (tg3_nvram_lock(tp))
@@ -9620,6 +9920,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
9620 9920
9621 /* Set bit 23 to enable PCIX hw bug fix */ 9921 /* Set bit 23 to enable PCIX hw bug fix */
9622 tp->dma_rwctrl |= 0x009f0000; 9922 tp->dma_rwctrl |= 0x009f0000;
9923 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
9924 /* 5780 always in PCIX mode */
9925 tp->dma_rwctrl |= 0x00144000;
9623 } else { 9926 } else {
9624 tp->dma_rwctrl |= 0x001b000f; 9927 tp->dma_rwctrl |= 0x001b000f;
9625 } 9928 }
@@ -9773,19 +10076,35 @@ static void __devinit tg3_init_link_config(struct tg3 *tp)
9773 10076
9774static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) 10077static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
9775{ 10078{
9776 tp->bufmgr_config.mbuf_read_dma_low_water = 10079 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9777 DEFAULT_MB_RDMA_LOW_WATER; 10080 tp->bufmgr_config.mbuf_read_dma_low_water =
9778 tp->bufmgr_config.mbuf_mac_rx_low_water = 10081 DEFAULT_MB_RDMA_LOW_WATER_5705;
9779 DEFAULT_MB_MACRX_LOW_WATER; 10082 tp->bufmgr_config.mbuf_mac_rx_low_water =
9780 tp->bufmgr_config.mbuf_high_water = 10083 DEFAULT_MB_MACRX_LOW_WATER_5705;
9781 DEFAULT_MB_HIGH_WATER; 10084 tp->bufmgr_config.mbuf_high_water =
10085 DEFAULT_MB_HIGH_WATER_5705;
10086
10087 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10088 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
10089 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10090 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
10091 tp->bufmgr_config.mbuf_high_water_jumbo =
10092 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
10093 } else {
10094 tp->bufmgr_config.mbuf_read_dma_low_water =
10095 DEFAULT_MB_RDMA_LOW_WATER;
10096 tp->bufmgr_config.mbuf_mac_rx_low_water =
10097 DEFAULT_MB_MACRX_LOW_WATER;
10098 tp->bufmgr_config.mbuf_high_water =
10099 DEFAULT_MB_HIGH_WATER;
9782 10100
9783 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = 10101 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
9784 DEFAULT_MB_RDMA_LOW_WATER_JUMBO; 10102 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
9785 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = 10103 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
9786 DEFAULT_MB_MACRX_LOW_WATER_JUMBO; 10104 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
9787 tp->bufmgr_config.mbuf_high_water_jumbo = 10105 tp->bufmgr_config.mbuf_high_water_jumbo =
9788 DEFAULT_MB_HIGH_WATER_JUMBO; 10106 DEFAULT_MB_HIGH_WATER_JUMBO;
10107 }
9789 10108
9790 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; 10109 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
9791 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; 10110 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
@@ -9803,6 +10122,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
9803 case PHY_ID_BCM5705: return "5705"; 10122 case PHY_ID_BCM5705: return "5705";
9804 case PHY_ID_BCM5750: return "5750"; 10123 case PHY_ID_BCM5750: return "5750";
9805 case PHY_ID_BCM5752: return "5752"; 10124 case PHY_ID_BCM5752: return "5752";
10125 case PHY_ID_BCM5780: return "5780";
9806 case PHY_ID_BCM8002: return "8002/serdes"; 10126 case PHY_ID_BCM8002: return "8002/serdes";
9807 case 0: return "serdes"; 10127 case 0: return "serdes";
9808 default: return "unknown"; 10128 default: return "unknown";
@@ -9998,8 +10318,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
9998 10318
9999 tg3_init_link_config(tp); 10319 tg3_init_link_config(tp);
10000 10320
10001 tg3_init_bufmgr_config(tp);
10002
10003 tp->rx_pending = TG3_DEF_RX_RING_PENDING; 10321 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
10004 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; 10322 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
10005 tp->tx_pending = TG3_DEF_TX_RING_PENDING; 10323 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
@@ -10028,14 +10346,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10028 goto err_out_iounmap; 10346 goto err_out_iounmap;
10029 } 10347 }
10030 10348
10031 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 10349 tg3_init_bufmgr_config(tp);
10032 tp->bufmgr_config.mbuf_read_dma_low_water =
10033 DEFAULT_MB_RDMA_LOW_WATER_5705;
10034 tp->bufmgr_config.mbuf_mac_rx_low_water =
10035 DEFAULT_MB_MACRX_LOW_WATER_5705;
10036 tp->bufmgr_config.mbuf_high_water =
10037 DEFAULT_MB_HIGH_WATER_5705;
10038 }
10039 10350
10040#if TG3_TSO_SUPPORT != 0 10351#if TG3_TSO_SUPPORT != 0
10041 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { 10352 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 70ad450733e6..5c4433c147fa 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -136,6 +136,7 @@
136#define ASIC_REV_5705 0x03 136#define ASIC_REV_5705 0x03
137#define ASIC_REV_5750 0x04 137#define ASIC_REV_5750 0x04
138#define ASIC_REV_5752 0x06 138#define ASIC_REV_5752 0x06
139#define ASIC_REV_5780 0x08
139#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) 140#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
140#define CHIPREV_5700_AX 0x70 141#define CHIPREV_5700_AX 0x70
141#define CHIPREV_5700_BX 0x71 142#define CHIPREV_5700_BX 0x71
@@ -984,14 +985,17 @@
984#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 985#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
985#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 986#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
986#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 987#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
988#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
987#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 989#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
988#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 990#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
989#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 991#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
990#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 992#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
993#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
991#define BUFMGR_MB_HIGH_WATER 0x00004418 994#define BUFMGR_MB_HIGH_WATER 0x00004418
992#define DEFAULT_MB_HIGH_WATER 0x00000060 995#define DEFAULT_MB_HIGH_WATER 0x00000060
993#define DEFAULT_MB_HIGH_WATER_5705 0x00000060 996#define DEFAULT_MB_HIGH_WATER_5705 0x00000060
994#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c 997#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
998#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
995#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c 999#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
996#define BUFMGR_MB_ALLOC_BIT 0x10000000 1000#define BUFMGR_MB_ALLOC_BIT 0x10000000
997#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 1001#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
@@ -2087,6 +2091,8 @@ struct tg3 {
2087 struct tg3_rx_buffer_desc *rx_rcb; 2091 struct tg3_rx_buffer_desc *rx_rcb;
2088 dma_addr_t rx_rcb_mapping; 2092 dma_addr_t rx_rcb_mapping;
2089 2093
2094 u32 rx_pkt_buf_sz;
2095
2090 /* begin "everything else" cacheline(s) section */ 2096 /* begin "everything else" cacheline(s) section */
2091 struct net_device_stats net_stats; 2097 struct net_device_stats net_stats;
2092 struct net_device_stats net_stats_prev; 2098 struct net_device_stats net_stats_prev;
@@ -2124,7 +2130,7 @@ struct tg3 {
2124#define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000 2130#define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000
2125#define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000 2131#define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000
2126#define TG3_FLAG_SERDES_WOL_CAP 0x00400000 2132#define TG3_FLAG_SERDES_WOL_CAP 0x00400000
2127#define TG3_FLAG_JUMBO_ENABLE 0x00800000 2133#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
2128#define TG3_FLAG_10_100_ONLY 0x01000000 2134#define TG3_FLAG_10_100_ONLY 0x01000000
2129#define TG3_FLAG_PAUSE_AUTONEG 0x02000000 2135#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
2130#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 2136#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
@@ -2154,6 +2160,11 @@ struct tg3 {
2154#define TG3_FLG2_5750_PLUS 0x00080000 2160#define TG3_FLG2_5750_PLUS 0x00080000
2155#define TG3_FLG2_PROTECTED_NVRAM 0x00100000 2161#define TG3_FLG2_PROTECTED_NVRAM 0x00100000
2156#define TG3_FLG2_USING_MSI 0x00200000 2162#define TG3_FLG2_USING_MSI 0x00200000
2163#define TG3_FLG2_JUMBO_CAPABLE 0x00400000
2164#define TG3_FLG2_MII_SERDES 0x00800000
2165#define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
2166 TG3_FLG2_MII_SERDES)
2167#define TG3_FLG2_PARALLEL_DETECT 0x01000000
2157 2168
2158 u32 split_mode_max_reqs; 2169 u32 split_mode_max_reqs;
2159#define SPLIT_MODE_5704_MAX_REQ 3 2170#define SPLIT_MODE_5704_MAX_REQ 3
@@ -2187,6 +2198,7 @@ struct tg3 {
2187 u8 pci_bist; 2198 u8 pci_bist;
2188 2199
2189 int pm_cap; 2200 int pm_cap;
2201 int msi_cap;
2190 2202
2191 /* PHY info */ 2203 /* PHY info */
2192 u32 phy_id; 2204 u32 phy_id;
@@ -2200,6 +2212,7 @@ struct tg3 {
2200#define PHY_ID_BCM5705 0x600081a0 2212#define PHY_ID_BCM5705 0x600081a0
2201#define PHY_ID_BCM5750 0x60008180 2213#define PHY_ID_BCM5750 0x60008180
2202#define PHY_ID_BCM5752 0x60008100 2214#define PHY_ID_BCM5752 0x60008100
2215#define PHY_ID_BCM5780 0x60008350
2203#define PHY_ID_BCM8002 0x60010140 2216#define PHY_ID_BCM8002 0x60010140
2204#define PHY_ID_INVALID 0xffffffff 2217#define PHY_ID_INVALID 0xffffffff
2205#define PHY_ID_REV_MASK 0x0000000f 2218#define PHY_ID_REV_MASK 0x0000000f
diff --git a/drivers/usb/atm/speedtch.c b/drivers/usb/atm/speedtch.c
index 6bd581e69afd..d0cbbb7f0385 100644
--- a/drivers/usb/atm/speedtch.c
+++ b/drivers/usb/atm/speedtch.c
@@ -448,19 +448,19 @@ static void speedtch_check_status(struct speedtch_instance_data *instance)
448 case 0: 448 case 0:
449 atm_dev->signal = ATM_PHY_SIG_LOST; 449 atm_dev->signal = ATM_PHY_SIG_LOST;
450 if (instance->last_status) 450 if (instance->last_status)
451 atm_info(usbatm, "%s\n", "ADSL line is down"); 451 atm_info(usbatm, "ADSL line is down\n");
452 /* It may never resync again unless we ask it to... */ 452 /* It may never resync again unless we ask it to... */
453 ret = speedtch_start_synchro(instance); 453 ret = speedtch_start_synchro(instance);
454 break; 454 break;
455 455
456 case 0x08: 456 case 0x08:
457 atm_dev->signal = ATM_PHY_SIG_UNKNOWN; 457 atm_dev->signal = ATM_PHY_SIG_UNKNOWN;
458 atm_info(usbatm, "%s\n", "ADSL line is blocked?"); 458 atm_info(usbatm, "ADSL line is blocked?\n");
459 break; 459 break;
460 460
461 case 0x10: 461 case 0x10:
462 atm_dev->signal = ATM_PHY_SIG_LOST; 462 atm_dev->signal = ATM_PHY_SIG_LOST;
463 atm_info(usbatm, "%s\n", "ADSL line is synchronising"); 463 atm_info(usbatm, "ADSL line is synchronising\n");
464 break; 464 break;
465 465
466 case 0x20: 466 case 0x20:
@@ -502,7 +502,7 @@ static void speedtch_status_poll(unsigned long data)
502 if (instance->poll_delay < MAX_POLL_DELAY) 502 if (instance->poll_delay < MAX_POLL_DELAY)
503 mod_timer(&instance->status_checker.timer, jiffies + msecs_to_jiffies(instance->poll_delay)); 503 mod_timer(&instance->status_checker.timer, jiffies + msecs_to_jiffies(instance->poll_delay));
504 else 504 else
505 atm_warn(instance->usbatm, "%s\n", "Too many failures - disabling line status polling"); 505 atm_warn(instance->usbatm, "Too many failures - disabling line status polling\n");
506} 506}
507 507
508static void speedtch_resubmit_int(unsigned long data) 508static void speedtch_resubmit_int(unsigned long data)
@@ -545,9 +545,9 @@ static void speedtch_handle_int(struct urb *int_urb, struct pt_regs *regs)
545 545
546 if ((count == 6) && !memcmp(up_int, instance->int_data, 6)) { 546 if ((count == 6) && !memcmp(up_int, instance->int_data, 6)) {
547 del_timer(&instance->status_checker.timer); 547 del_timer(&instance->status_checker.timer);
548 atm_info(usbatm, "%s\n", "DSL line goes up"); 548 atm_info(usbatm, "DSL line goes up\n");
549 } else if ((count == 6) && !memcmp(down_int, instance->int_data, 6)) { 549 } else if ((count == 6) && !memcmp(down_int, instance->int_data, 6)) {
550 atm_info(usbatm, "%s\n", "DSL line goes down"); 550 atm_info(usbatm, "DSL line goes down\n");
551 } else { 551 } else {
552 int i; 552 int i;
553 553
diff --git a/include/linux/netfilter_ipv4/ip_conntrack.h b/include/linux/netfilter_ipv4/ip_conntrack.h
index f8da7ddeff3a..08fe5f7d14a0 100644
--- a/include/linux/netfilter_ipv4/ip_conntrack.h
+++ b/include/linux/netfilter_ipv4/ip_conntrack.h
@@ -239,7 +239,7 @@ ip_conntrack_get(const struct sk_buff *skb, enum ip_conntrack_info *ctinfo)
239} 239}
240 240
241/* decrement reference count on a conntrack */ 241/* decrement reference count on a conntrack */
242extern inline void ip_conntrack_put(struct ip_conntrack *ct); 242extern void ip_conntrack_put(struct ip_conntrack *ct);
243 243
244/* call to create an explicit dependency on ip_conntrack. */ 244/* call to create an explicit dependency on ip_conntrack. */
245extern void need_ip_conntrack(void); 245extern void need_ip_conntrack(void);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 41aa32b2869c..d2ad2c4f835a 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2107,6 +2107,8 @@
2107#define PCI_DEVICE_ID_TIGON3_5721 0x1659 2107#define PCI_DEVICE_ID_TIGON3_5721 0x1659
2108#define PCI_DEVICE_ID_TIGON3_5705M 0x165d 2108#define PCI_DEVICE_ID_TIGON3_5705M 0x165d
2109#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e 2109#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e
2110#define PCI_DEVICE_ID_TIGON3_5780 0x166a
2111#define PCI_DEVICE_ID_TIGON3_5780S 0x166b
2110#define PCI_DEVICE_ID_TIGON3_5705F 0x166e 2112#define PCI_DEVICE_ID_TIGON3_5705F 0x166e
2111#define PCI_DEVICE_ID_TIGON3_5750 0x1676 2113#define PCI_DEVICE_ID_TIGON3_5750 0x1676
2112#define PCI_DEVICE_ID_TIGON3_5751 0x1677 2114#define PCI_DEVICE_ID_TIGON3_5751 0x1677
diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c
index ecade4893a13..8da3e25b2c4c 100644
--- a/net/xfrm/xfrm_user.c
+++ b/net/xfrm/xfrm_user.c
@@ -1350,6 +1350,9 @@ static struct xfrm_policy *xfrm_compile_policy(u16 family, int opt,
1350 if (nr > XFRM_MAX_DEPTH) 1350 if (nr > XFRM_MAX_DEPTH)
1351 return NULL; 1351 return NULL;
1352 1352
1353 if (p->dir > XFRM_POLICY_OUT)
1354 return NULL;
1355
1353 xp = xfrm_policy_alloc(GFP_KERNEL); 1356 xp = xfrm_policy_alloc(GFP_KERNEL);
1354 if (xp == NULL) { 1357 if (xp == NULL) {
1355 *dir = -ENOBUFS; 1358 *dir = -ENOBUFS;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 07:42:19 -0500