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-rw-r--r--drivers/net/tg3.c10
-rw-r--r--drivers/net/tg3.h1
2 files changed, 7 insertions, 4 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 604f3085d12a..a1aeba2442f5 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -6594,8 +6594,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6594 u32 tmp; 6594 u32 tmp;
6595 6595
6596 /* Clear CRC stats. */ 6596 /* Clear CRC stats. */
6597 if (!tg3_readphy(tp, 0x1e, &tmp)) { 6597 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6598 tg3_writephy(tp, 0x1e, tmp | 0x8000); 6598 tg3_writephy(tp, MII_TG3_TEST1,
6599 tmp | MII_TG3_TEST1_CRC_EN);
6599 tg3_readphy(tp, 0x14, &tmp); 6600 tg3_readphy(tp, 0x14, &tmp);
6600 } 6601 }
6601 } 6602 }
@@ -7419,8 +7420,9 @@ static unsigned long calc_crc_errors(struct tg3 *tp)
7419 u32 val; 7420 u32 val;
7420 7421
7421 spin_lock_bh(&tp->lock); 7422 spin_lock_bh(&tp->lock);
7422 if (!tg3_readphy(tp, 0x1e, &val)) { 7423 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7423 tg3_writephy(tp, 0x1e, val | 0x8000); 7424 tg3_writephy(tp, MII_TG3_TEST1,
7425 val | MII_TG3_TEST1_CRC_EN);
7424 tg3_readphy(tp, 0x14, &val); 7426 tg3_readphy(tp, 0x14, &val);
7425 } else 7427 } else
7426 val = 0; 7428 val = 0;
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 80f59ac7ec58..45d477e8f374 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1660,6 +1660,7 @@
1660 1660
1661#define MII_TG3_TEST1 0x1e 1661#define MII_TG3_TEST1 0x1e
1662#define MII_TG3_TEST1_TRIM_EN 0x0010 1662#define MII_TG3_TEST1_TRIM_EN 0x0010
1663#define MII_TG3_TEST1_CRC_EN 0x8000
1663 1664
1664/* There are two ways to manage the TX descriptors on the tigon3. 1665/* There are two ways to manage the TX descriptors on the tigon3.
1665 * Either the descriptors are in host DMA'able memory, or they 1666 * Either the descriptors are in host DMA'able memory, or they