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-rw-r--r--drivers/video/pm2fb.c17
1 files changed, 5 insertions, 12 deletions
diff --git a/drivers/video/pm2fb.c b/drivers/video/pm2fb.c
index ab5e66890e4e..0a04483aa3e0 100644
--- a/drivers/video/pm2fb.c
+++ b/drivers/video/pm2fb.c
@@ -183,15 +183,17 @@ static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
183 index = PM2VR_RD_INDEXED_DATA; 183 index = PM2VR_RD_INDEXED_DATA;
184 break; 184 break;
185 } 185 }
186 mb(); 186 wmb();
187 pm2_WR(p, index, v); 187 pm2_WR(p, index, v);
188 wmb();
188} 189}
189 190
190static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v) 191static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
191{ 192{
192 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff); 193 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
193 mb(); 194 wmb();
194 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v); 195 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
196 wmb();
195} 197}
196 198
197#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT 199#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
@@ -466,11 +468,9 @@ static void set_memclock(struct pm2fb_par* par, u32 clk)
466 WAIT_FIFO(par, 8); 468 WAIT_FIFO(par, 8);
467 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8); 469 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
468 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0); 470 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
469 wmb();
470 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m); 471 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
471 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n); 472 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
472 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p); 473 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
473 wmb();
474 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1); 474 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
475 rmb(); 475 rmb();
476 for (i = 256; 476 for (i = 256;
@@ -483,12 +483,9 @@ static void set_memclock(struct pm2fb_par* par, u32 clk)
483 pm2_mnp(clk, &m, &n, &p); 483 pm2_mnp(clk, &m, &n, &p);
484 WAIT_FIFO(par, 10); 484 WAIT_FIFO(par, 10);
485 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6); 485 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
486 wmb();
487 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m); 486 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
488 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n); 487 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
489 wmb();
490 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p); 488 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
491 wmb();
492 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS); 489 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
493 rmb(); 490 rmb();
494 for (i = 256; 491 for (i = 256;
@@ -509,12 +506,9 @@ static void set_pixclock(struct pm2fb_par* par, u32 clk)
509 pm2_mnp(clk, &m, &n, &p); 506 pm2_mnp(clk, &m, &n, &p);
510 WAIT_FIFO(par, 8); 507 WAIT_FIFO(par, 8);
511 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0); 508 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
512 wmb();
513 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m); 509 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
514 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n); 510 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
515 wmb();
516 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p); 511 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
517 wmb();
518 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS); 512 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
519 rmb(); 513 rmb();
520 for (i = 256; 514 for (i = 256;
@@ -1066,10 +1060,9 @@ static void pm2fb_block_op(struct fb_info* info, int copy,
1066 1060
1067 if (!w || !h) 1061 if (!w || !h)
1068 return; 1062 return;
1069 WAIT_FIFO(par, 6); 1063 WAIT_FIFO(par, 5);
1070 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE | 1064 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
1071 PM2F_CONFIG_FB_READ_SOURCE_ENABLE); 1065 PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
1072 pm2_WR(par, PM2R_FB_PIXEL_OFFSET, 0);
1073 if (copy) 1066 if (copy)
1074 pm2_WR(par, PM2R_FB_SOURCE_DELTA, 1067 pm2_WR(par, PM2R_FB_SOURCE_DELTA,
1075 ((ysrc-y) & 0xfff) << 16 | ((xsrc-x) & 0xfff)); 1068 ((ysrc-y) & 0xfff) << 16 | ((xsrc-x) & 0xfff));