diff options
-rw-r--r-- | drivers/net/tg3.c | 37 | ||||
-rw-r--r-- | drivers/net/tg3.h | 11 |
2 files changed, 27 insertions, 21 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index b7e03a6ebf25..8ffa5afd4141 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -97,14 +97,12 @@ | |||
97 | * them in the NIC onboard memory. | 97 | * them in the NIC onboard memory. |
98 | */ | 98 | */ |
99 | #define TG3_RX_STD_RING_SIZE(tp) \ | 99 | #define TG3_RX_STD_RING_SIZE(tp) \ |
100 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \ | 100 | ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \ |
101 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \ | 101 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) |
102 | RX_STD_MAX_SIZE_5717 : 512) | ||
103 | #define TG3_DEF_RX_RING_PENDING 200 | 102 | #define TG3_DEF_RX_RING_PENDING 200 |
104 | #define TG3_RX_JMB_RING_SIZE(tp) \ | 103 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
105 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \ | 104 | ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \ |
106 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \ | 105 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) |
107 | 1024 : 256) | ||
108 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 | 106 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
109 | #define TG3_RSS_INDIR_TBL_SIZE 128 | 107 | #define TG3_RSS_INDIR_TBL_SIZE 128 |
110 | 108 | ||
@@ -8115,9 +8113,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
8115 | ((u64) tpr->rx_jmb_mapping >> 32)); | 8113 | ((u64) tpr->rx_jmb_mapping >> 32)); |
8116 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, | 8114 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
8117 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); | 8115 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
8116 | val = TG3_RX_JMB_RING_SIZE(tp) << | ||
8117 | BDINFO_FLAGS_MAXLEN_SHIFT; | ||
8118 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | 8118 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
8119 | (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) | | 8119 | val | BDINFO_FLAGS_USE_EXT_RECV); |
8120 | BDINFO_FLAGS_USE_EXT_RECV); | ||
8121 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) || | 8120 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) || |
8122 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | 8121 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8123 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, | 8122 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
@@ -8129,15 +8128,15 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
8129 | 8128 | ||
8130 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { | 8129 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
8131 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | 8130 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8132 | val = RX_STD_MAX_SIZE_5705; | 8131 | val = TG3_RX_STD_MAX_SIZE_5700; |
8133 | else | 8132 | else |
8134 | val = RX_STD_MAX_SIZE_5717; | 8133 | val = TG3_RX_STD_MAX_SIZE_5717; |
8135 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; | 8134 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
8136 | val |= (TG3_RX_STD_DMA_SZ << 2); | 8135 | val |= (TG3_RX_STD_DMA_SZ << 2); |
8137 | } else | 8136 | } else |
8138 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; | 8137 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
8139 | } else | 8138 | } else |
8140 | val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT; | 8139 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
8141 | 8140 | ||
8142 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | 8141 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); |
8143 | 8142 | ||
@@ -8421,8 +8420,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
8421 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); | 8420 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
8422 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | 8421 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); |
8423 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; | 8422 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
8424 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 8423 | if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) |
8425 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | ||
8426 | val |= RCVDBDI_MODE_LRG_RING_SZ; | 8424 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
8427 | tw32(RCVDBDI_MODE, val); | 8425 | tw32(RCVDBDI_MODE, val); |
8428 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); | 8426 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
@@ -13125,14 +13123,13 @@ static inline void vlan_features_add(struct net_device *dev, unsigned long flags | |||
13125 | 13123 | ||
13126 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) | 13124 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
13127 | { | 13125 | { |
13128 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 13126 | if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) |
13129 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | 13127 | return TG3_RX_RET_MAX_SIZE_5717; |
13130 | return 4096; | ||
13131 | else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && | 13128 | else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
13132 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | 13129 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
13133 | return 1024; | 13130 | return TG3_RX_RET_MAX_SIZE_5700; |
13134 | else | 13131 | else |
13135 | return 512; | 13132 | return TG3_RX_RET_MAX_SIZE_5705; |
13136 | } | 13133 | } |
13137 | 13134 | ||
13138 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { | 13135 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
@@ -13430,6 +13427,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
13430 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; | 13427 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; |
13431 | } | 13428 | } |
13432 | 13429 | ||
13430 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | ||
13431 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | ||
13432 | tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP; | ||
13433 | |||
13433 | if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && | 13434 | if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
13434 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719) | 13435 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719) |
13435 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; | 13436 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 73884b69b749..4c498ed66059 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -25,9 +25,13 @@ | |||
25 | 25 | ||
26 | #define TG3_RX_INTERNAL_RING_SZ_5906 32 | 26 | #define TG3_RX_INTERNAL_RING_SZ_5906 32 |
27 | 27 | ||
28 | #define RX_STD_MAX_SIZE_5705 512 | 28 | #define TG3_RX_STD_MAX_SIZE_5700 512 |
29 | #define RX_STD_MAX_SIZE_5717 2048 | 29 | #define TG3_RX_STD_MAX_SIZE_5717 2048 |
30 | #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */ | 30 | #define TG3_RX_JMB_MAX_SIZE_5700 256 |
31 | #define TG3_RX_JMB_MAX_SIZE_5717 1024 | ||
32 | #define TG3_RX_RET_MAX_SIZE_5700 1024 | ||
33 | #define TG3_RX_RET_MAX_SIZE_5705 512 | ||
34 | #define TG3_RX_RET_MAX_SIZE_5717 4096 | ||
31 | 35 | ||
32 | /* First 256 bytes are a mirror of PCI config space. */ | 36 | /* First 256 bytes are a mirror of PCI config space. */ |
33 | #define TG3PCI_VENDOR 0x00000000 | 37 | #define TG3PCI_VENDOR 0x00000000 |
@@ -2897,6 +2901,7 @@ struct tg3 { | |||
2897 | #define TG3_FLG3_5701_DMA_BUG 0x00000008 | 2901 | #define TG3_FLG3_5701_DMA_BUG 0x00000008 |
2898 | #define TG3_FLG3_USE_PHYLIB 0x00000010 | 2902 | #define TG3_FLG3_USE_PHYLIB 0x00000010 |
2899 | #define TG3_FLG3_MDIOBUS_INITED 0x00000020 | 2903 | #define TG3_FLG3_MDIOBUS_INITED 0x00000020 |
2904 | #define TG3_FLG3_LRG_PROD_RING_CAP 0x00000080 | ||
2900 | #define TG3_FLG3_RGMII_INBAND_DISABLE 0x00000100 | 2905 | #define TG3_FLG3_RGMII_INBAND_DISABLE 0x00000100 |
2901 | #define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200 | 2906 | #define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200 |
2902 | #define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400 | 2907 | #define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400 |