8 files changed, 438 insertions, 226 deletions

diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index aa995a49e567..bfc8f537db18 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -21,6 +21,7 @@ obj-y				+= gpio-config.o
 # PM support
 
 obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_PM)                += pm-gpio.o
 obj-$(CONFIG_S3C2410_PM_CHECK)  += pm-check.o
 
 # devices
diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c
index d71dd6d9ce5c..260fdc6ad685 100644
--- a/arch/arm/plat-s3c/gpio.c
+++ b/arch/arm/plat-s3c/gpio.c
@@ -16,7 +16,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-#include <plat/gpio-core.h>
+#include <mach/gpio-core.h>
 
 #ifdef CONFIG_S3C_GPIO_TRACK
 struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
@@ -140,6 +140,15 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
         if (!gc->get)
                 gc->get = s3c_gpiolib_get;
 
+#ifdef CONFIG_PM
+        if (chip->pm != NULL) {
+                if (!chip->pm->save || !chip->pm->resume)
+                        printk(KERN_ERR "gpio: %s has missing PM functions\n",
+                               gc->label);
+        } else
+                printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
+#endif
+
         /* gpiochip_add() prints own failure message on error. */
         ret = gpiochip_add(gc);
         if (ret >= 0)
diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-s3c/include/plat/gpio-core.h
index 2fc60a580ac8..32af612767aa 100644
--- a/arch/arm/plat-s3c/include/plat/gpio-core.h
+++ b/arch/arm/plat-s3c/include/plat/gpio-core.h
@@ -20,6 +20,18 @@
  * specific code.
 */
 
+struct s3c_gpio_chip;
+
+/**
+ * struct s3c_gpio_pm - power management (suspend/resume) information
+ * @save: Routine to save the state of the GPIO block
+ * @resume: Routine to resume the GPIO block.
+ */
+struct s3c_gpio_pm {
+        void (*save)(struct s3c_gpio_chip *chip);
+        void (*resume)(struct s3c_gpio_chip *chip);
+};
+
 struct s3c_gpio_cfg;
 
 /**
@@ -27,6 +39,7 @@ struct s3c_gpio_cfg;
  * @chip: The chip structure to be exported via gpiolib.
  * @base: The base pointer to the gpio configuration registers.
  * @config: special function and pull-resistor control information.
+ * @pm_save: Save information for suspend/resume support.
  *
  * This wrapper provides the necessary information for the Samsung
  * specific gpios being registered with gpiolib.
@@ -34,7 +47,11 @@ struct s3c_gpio_cfg;
 struct s3c_gpio_chip {
         struct gpio_chip        chip;
         struct s3c_gpio_cfg     *config;
+        struct s3c_gpio_pm      *pm;
         void __iomem            *base;
+#ifdef CONFIG_PM
+        u32                     pm_save[4];
+#endif
 };
 
 static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
@@ -75,3 +92,16 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
 
 static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
 #endif
+
+#ifdef CONFIG_PM
+extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
+extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
+extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
+#define __gpio_pm(x) x
+#else
+#define s3c_gpio_pm_1bit NULL
+#define s3c_gpio_pm_2bit NULL
+#define s3c_gpio_pm_4bit NULL
+#define __gpio_pm(x) NULL
+
+#endif /* CONFIG_PM */
diff --git a/arch/arm/plat-s3c/pm-gpio.c b/arch/arm/plat-s3c/pm-gpio.c
new file mode 100644
index 000000000000..cfd326a8b693
--- /dev/null
+++ b/arch/arm/plat-s3c/pm-gpio.c
@@ -0,0 +1,380 @@
+
+/* linux/arch/arm/plat-s3c/pm-gpio.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series GPIO PM code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/sysdev.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/gpio-core.h>
+#include <plat/pm.h>
+
+/* PM GPIO helpers */
+
+#define OFFS_CON        (0x00)
+#define OFFS_DAT        (0x04)
+#define OFFS_UP         (0x08)
+
+static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
+{
+        chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+        chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+}
+
+static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
+{
+        void __iomem *base = chip->base;
+        u32 old_gpcon = __raw_readl(base + OFFS_CON);
+        u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+        u32 gps_gpcon = chip->pm_save[0];
+        u32 gps_gpdat = chip->pm_save[1];
+        u32 gpcon;
+
+        /* GPACON only has one bit per control / data and no PULLUPs.
+         * GPACON[x] = 0 => Output, 1 => SFN */
+
+        /* first set all SFN bits to SFN */
+
+        gpcon = old_gpcon | gps_gpcon;
+        __raw_writel(gpcon, base + OFFS_CON);
+
+        /* now set all the other bits */
+
+        __raw_writel(gps_gpdat, base + OFFS_DAT);
+        __raw_writel(gps_gpcon, base + OFFS_CON);
+
+        S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
+                  chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_1bit = {
+        .save   = s3c_gpio_pm_1bit_save,
+        .resume = s3c_gpio_pm_1bit_resume,
+};
+
+static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
+{
+        chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+        chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+        chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
+}
+
+/* Test whether the given masked+shifted bits of an GPIO configuration
+ * are one of the SFN (special function) modes. */
+
+static inline int is_sfn(unsigned long con)
+{
+        return con >= 2;
+}
+
+/* Test if the given masked+shifted GPIO configuration is an input */
+
+static inline int is_in(unsigned long con)
+{
+        return con == 0;
+}
+
+/* Test if the given masked+shifted GPIO configuration is an output */
+
+static inline int is_out(unsigned long con)
+{
+        return con == 1;
+}
+
+/**
+ * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
+ * @chip: The chip information to resume.
+ *
+ * Restore one of the GPIO banks that was saved during suspend. This is
+ * not as simple as once thought, due to the possibility of glitches
+ * from the order that the CON and DAT registers are set in.
+ *
+ * The three states the pin can be are {IN,OUT,SFN} which gives us 9
+ * combinations of changes to check. Three of these, if the pin stays
+ * in the same configuration can be discounted. This leaves us with
+ * the following:
+ *
+ * { IN => OUT }  Change DAT first
+ * { IN => SFN }  Change CON first
+ * { OUT => SFN } Change CON first, so new data will not glitch
+ * { OUT => IN }  Change CON first, so new data will not glitch
+ * { SFN => IN }  Change CON first
+ * { SFN => OUT } Change DAT first, so new data will not glitch [1]
+ *
+ * We do not currently deal with the UP registers as these control
+ * weak resistors, so a small delay in change should not need to bring
+ * these into the calculations.
+ *
+ * [1] this assumes that writing to a pin DAT whilst in SFN will set the
+ *     state for when it is next output.
+ */
+static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
+{
+        void __iomem *base = chip->base;
+        u32 old_gpcon = __raw_readl(base + OFFS_CON);
+        u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+        u32 gps_gpcon = chip->pm_save[0];
+        u32 gps_gpdat = chip->pm_save[1];
+        u32 gpcon, old, new, mask;
+        u32 change_mask = 0x0;
+        int nr;
+
+        /* restore GPIO pull-up settings */
+        __raw_writel(chip->pm_save[2], base + OFFS_UP);
+
+        /* Create a change_mask of all the items that need to have
+         * their CON value changed before their DAT value, so that
+         * we minimise the work between the two settings.
+         */
+
+        for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
+                old = (old_gpcon & mask) >> nr;
+                new = (gps_gpcon & mask) >> nr;
+
+                /* If there is no change, then skip */
+
+                if (old == new)
+                        continue;
+
+                /* If both are special function, then skip */
+
+                if (is_sfn(old) && is_sfn(new))
+                        continue;
+
+                /* Change is IN => OUT, do not change now */
+
+                if (is_in(old) && is_out(new))
+                        continue;
+
+                /* Change is SFN => OUT, do not change now */
+
+                if (is_sfn(old) && is_out(new))
+                        continue;
+
+                /* We should now be at the case of IN=>SFN,
+                 * OUT=>SFN, OUT=>IN, SFN=>IN. */
+
+                change_mask |= mask;
+        }
+
+
+        /* Write the new CON settings */
+
+        gpcon = old_gpcon & ~change_mask;
+        gpcon |= gps_gpcon & change_mask;
+
+        __raw_writel(gpcon, base + OFFS_CON);
+
+        /* Now change any items that require DAT,CON */
+
+        __raw_writel(gps_gpdat, base + OFFS_DAT);
+        __raw_writel(gps_gpcon, base + OFFS_CON);
+
+        S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
+                  chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_2bit = {
+        .save   = s3c_gpio_pm_2bit_save,
+        .resume = s3c_gpio_pm_2bit_resume,
+};
+
+#ifdef CONFIG_ARCH_S3C64XX
+static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
+{
+        chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
+        chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
+        chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
+
+        if (chip->chip.ngpio > 8)
+                chip->pm_save[0] = __raw_readl(chip->base - 4);
+}
+
+static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
+{
+        u32 old, new, mask;
+        u32 change_mask = 0x0;
+        int nr;
+
+        for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
+                old = (old_gpcon & mask) >> nr;
+                new = (gps_gpcon & mask) >> nr;
+
+                /* If there is no change, then skip */
+
+                if (old == new)
+                        continue;
+
+                /* If both are special function, then skip */
+
+                if (is_sfn(old) && is_sfn(new))
+                        continue;
+
+                /* Change is IN => OUT, do not change now */
+
+                if (is_in(old) && is_out(new))
+                        continue;
+
+                /* Change is SFN => OUT, do not change now */
+
+                if (is_sfn(old) && is_out(new))
+                        continue;
+
+                /* We should now be at the case of IN=>SFN,
+                 * OUT=>SFN, OUT=>IN, SFN=>IN. */
+
+                change_mask |= mask;
+        }
+
+        return change_mask;
+}
+
+static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
+{
+        void __iomem *con = chip->base + (index * 4);
+        u32 old_gpcon = __raw_readl(con);
+        u32 gps_gpcon = chip->pm_save[index + 1];
+        u32 gpcon, mask;
+
+        mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
+
+        gpcon = old_gpcon & ~mask;
+        gpcon |= gps_gpcon & mask;
+
+        __raw_writel(gpcon, con);
+}
+
+static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
+{
+        void __iomem *base = chip->base;
+        u32 old_gpcon[2];
+        u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+        u32 gps_gpdat = chip->pm_save[2];
+
+        /* First, modify the CON settings */
+
+        old_gpcon[0] = 0;
+        old_gpcon[1] = __raw_readl(base + OFFS_CON);
+
+        s3c_gpio_pm_4bit_con(chip, 0);
+        if (chip->chip.ngpio > 8) {
+                old_gpcon[0] = __raw_readl(base - 4);
+                s3c_gpio_pm_4bit_con(chip, -1);
+        }
+
+        /* Now change the configurations that require DAT,CON */
+
+        __raw_writel(chip->pm_save[2], base + OFFS_DAT);
+        __raw_writel(chip->pm_save[1], base + OFFS_CON);
+        if (chip->chip.ngpio > 8)
+                __raw_writel(chip->pm_save[0], base - 4);
+
+        __raw_writel(chip->pm_save[2], base + OFFS_DAT);
+        __raw_writel(chip->pm_save[3], base + OFFS_UP);
+
+        if (chip->chip.ngpio > 8) {
+                S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
+                          chip->chip.label, old_gpcon[0], old_gpcon[1],
+                          __raw_readl(base - 4),
+                          __raw_readl(base + OFFS_CON),
+                          old_gpdat, gps_gpdat);
+        } else
+                S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
+                          chip->chip.label, old_gpcon[1],
+                          __raw_readl(base + OFFS_CON),
+                          old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_4bit = {
+        .save   = s3c_gpio_pm_4bit_save,
+        .resume = s3c_gpio_pm_4bit_resume,
+};
+#endif /* CONFIG_ARCH_S3C64XX */
+
+/**
+ * s3c_pm_save_gpio() - save gpio chip data for suspend
+ * @ourchip: The chip for suspend.
+ */
+static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
+{
+        struct s3c_gpio_pm *pm = ourchip->pm;
+
+        if (pm == NULL || pm->save == NULL)
+                S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+        else
+                pm->save(ourchip);
+}
+
+/**
+ * s3c_pm_save_gpios() - Save the state of the GPIO banks.
+ *
+ * For all the GPIO banks, save the state of each one ready for going
+ * into a suspend mode.
+ */
+void s3c_pm_save_gpios(void)
+{
+        struct s3c_gpio_chip *ourchip;
+        unsigned int gpio_nr;
+
+        for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+                ourchip = s3c_gpiolib_getchip(gpio_nr);
+                if (!ourchip)
+                        continue;
+
+                s3c_pm_save_gpio(ourchip);
+
+                S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
+                          ourchip->chip.label,
+                          ourchip->pm_save[0],
+                          ourchip->pm_save[1],
+                          ourchip->pm_save[2],
+                          ourchip->pm_save[3]);
+
+                gpio_nr += ourchip->chip.ngpio;
+                gpio_nr += CONFIG_S3C_GPIO_SPACE;
+        }
+}
+
+/**
+ * s3c_pm_resume_gpio() - restore gpio chip data after suspend
+ * @ourchip: The suspended chip.
+ */
+static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
+{
+        struct s3c_gpio_pm *pm = ourchip->pm;
+
+        if (pm == NULL || pm->resume == NULL)
+                S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+        else
+                pm->resume(ourchip);
+}
+
+void s3c_pm_restore_gpios(void)
+{
+        struct s3c_gpio_chip *ourchip;
+        unsigned int gpio_nr;
+
+        for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+                ourchip = s3c_gpiolib_getchip(gpio_nr);
+                if (!ourchip)
+                        continue;
+
+                s3c_pm_resume_gpio(ourchip);
+
+                gpio_nr += ourchip->chip.ngpio;
+                gpio_nr += CONFIG_S3C_GPIO_SPACE;
+        }
+}
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 5c0491bf738b..4bac12dc0733 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -22,6 +22,7 @@
 #include <mach/gpio-core.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <plat/pm.h>
 
 #include <mach/regs-gpio.h>
 
@@ -78,6 +79,7 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
 struct s3c_gpio_chip s3c24xx_gpios[] = {
         [0] = {
                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPA0),
+                .pm     = __gpio_pm(&s3c_gpio_pm_1bit),
                 .chip   = {
                         .base                   = S3C2410_GPA0,
                         .owner                  = THIS_MODULE,
@@ -89,6 +91,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
         },
         [1] = {
                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPB0),
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
                         .base                   = S3C2410_GPB0,
                         .owner                  = THIS_MODULE,
@@ -98,6 +101,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
         },
         [2] = {
                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPC0),
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
                         .base                   = S3C2410_GPC0,
                         .owner                  = THIS_MODULE,
@@ -107,6 +111,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
         },
         [3] = {
                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPD0),
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
                         .base                   = S3C2410_GPD0,
                         .owner                  = THIS_MODULE,
@@ -116,6 +121,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
         },
         [4] = {
                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPE0),
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
                         .base                   = S3C2410_GPE0,
                         .label                  = "GPIOE",
@@ -125,6 +131,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
         },
         [5] = {
                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPF0),
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
                         .base                   = S3C2410_GPF0,
                         .owner                  = THIS_MODULE,
@@ -135,6 +142,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
         },
         [6] = {
                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPG0),
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
                         .base                   = S3C2410_GPG0,
                         .owner                  = THIS_MODULE,
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 062a29339a91..5135c40a1b90 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -75,43 +75,10 @@ static struct sleep_save core_save[] = {
         SAVE_ITEM(S3C2410_CLKSLOW),
 };
 
-static struct gpio_sleep {
-        void __iomem    *base;
-        unsigned int     gpcon;
-        unsigned int     gpdat;
-        unsigned int     gpup;
-} gpio_save[] = {
-        [0] = {
-                .base   = S3C2410_GPACON,
-        },
-        [1] = {
-                .base   = S3C2410_GPBCON,
-        },
-        [2] = {
-                .base   = S3C2410_GPCCON,
-        },
-        [3] = {
-                .base   = S3C2410_GPDCON,
-        },
-        [4] = {
-                .base   = S3C2410_GPECON,
-        },
-        [5] = {
-                .base   = S3C2410_GPFCON,
-        },
-        [6] = {
-                .base   = S3C2410_GPGCON,
-        },
-        [7] = {
-                .base   = S3C2410_GPHCON,
-        },
-};
-
 static struct sleep_save misc_save[] = {
         SAVE_ITEM(S3C2410_DCLKCON),
 };
 
-
 /* s3c_pm_check_resume_pin
  *
  * check to see if the pin is configured correctly for sleep mode, and
@@ -165,186 +132,6 @@ void s3c_pm_configure_extint(void)
         }
 }
 
-/* offsets for CON/DAT/UP registers */
-
-#define OFFS_CON        (S3C2410_GPACON - S3C2410_GPACON)
-#define OFFS_DAT        (S3C2410_GPADAT - S3C2410_GPACON)
-#define OFFS_UP         (S3C2410_GPBUP  - S3C2410_GPBCON)
-
-/* s3c_pm_save_gpios()
- *
- * Save the state of the GPIOs
- */
-
-void s3c_pm_save_gpios(void)
-{
-        struct gpio_sleep *gps = gpio_save;
-        unsigned int gpio;
-
-        for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
-                void __iomem *base = gps->base;
-
-                gps->gpcon = __raw_readl(base + OFFS_CON);
-                gps->gpdat = __raw_readl(base + OFFS_DAT);
-
-                if (gpio > 0)
-                        gps->gpup = __raw_readl(base + OFFS_UP);
-
-        }
-}
-
-/* Test whether the given masked+shifted bits of an GPIO configuration
- * are one of the SFN (special function) modes. */
-
-static inline int is_sfn(unsigned long con)
-{
-        return (con == 2 || con == 3);
-}
-
-/* Test if the given masked+shifted GPIO configuration is an input */
-
-static inline int is_in(unsigned long con)
-{
-        return con == 0;
-}
-
-/* Test if the given masked+shifted GPIO configuration is an output */
-
-static inline int is_out(unsigned long con)
-{
-        return con == 1;
-}
-
-/**
- * s3c2410_pm_restore_gpio() - restore the given GPIO bank
- * @index: The number of the GPIO bank being resumed.
- * @gps: The sleep confgiuration for the bank.
- *
- * Restore one of the GPIO banks that was saved during suspend. This is
- * not as simple as once thought, due to the possibility of glitches
- * from the order that the CON and DAT registers are set in.
- *
- * The three states the pin can be are {IN,OUT,SFN} which gives us 9
- * combinations of changes to check. Three of these, if the pin stays
- * in the same configuration can be discounted. This leaves us with
- * the following:
- *
- * { IN => OUT }  Change DAT first
- * { IN => SFN }  Change CON first
- * { OUT => SFN } Change CON first, so new data will not glitch
- * { OUT => IN }  Change CON first, so new data will not glitch
- * { SFN => IN }  Change CON first
- * { SFN => OUT } Change DAT first, so new data will not glitch [1]
- *
- * We do not currently deal with the UP registers as these control
- * weak resistors, so a small delay in change should not need to bring
- * these into the calculations.
- *
- * [1] this assumes that writing to a pin DAT whilst in SFN will set the
- *     state for when it is next output.
- */
-
-static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
-{
-        void __iomem *base = gps->base;
-        unsigned long gps_gpcon = gps->gpcon;
-        unsigned long gps_gpdat = gps->gpdat;
-        unsigned long old_gpcon;
-        unsigned long old_gpdat;
-        unsigned long old_gpup = 0x0;
-        unsigned long gpcon;
-        int nr;
-
-        old_gpcon = __raw_readl(base + OFFS_CON);
-        old_gpdat = __raw_readl(base + OFFS_DAT);
-
-        if (base == S3C2410_GPACON) {
-                /* GPACON only has one bit per control / data and no PULLUPs.
-                 * GPACON[x] = 0 => Output, 1 => SFN */
-
-                /* first set all SFN bits to SFN */
-
-                gpcon = old_gpcon | gps->gpcon;
-                __raw_writel(gpcon, base + OFFS_CON);
-
-                /* now set all the other bits */
-
-                __raw_writel(gps_gpdat, base + OFFS_DAT);
-                __raw_writel(gps_gpcon, base + OFFS_CON);
-        } else {
-                unsigned long old, new, mask;
-                unsigned long change_mask = 0x0;
-
-                old_gpup = __raw_readl(base + OFFS_UP);
-
-                /* Create a change_mask of all the items that need to have
-                 * their CON value changed before their DAT value, so that
-                 * we minimise the work between the two settings.
-                 */
-
-                for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
-                        old = (old_gpcon & mask) >> nr;
-                        new = (gps_gpcon & mask) >> nr;
-
-                        /* If there is no change, then skip */
-
-                        if (old == new)
-                                continue;
-
-                        /* If both are special function, then skip */
-
-                        if (is_sfn(old) && is_sfn(new))
-                                continue;
-
-                        /* Change is IN => OUT, do not change now */
-
-                        if (is_in(old) && is_out(new))
-                                continue;
-
-                        /* Change is SFN => OUT, do not change now */
-
-                        if (is_sfn(old) && is_out(new))
-                                continue;
-
-                        /* We should now be at the case of IN=>SFN,
-                         * OUT=>SFN, OUT=>IN, SFN=>IN. */
-
-                        change_mask |= mask;
-                }
-
-                /* Write the new CON settings */
-
-                gpcon = old_gpcon & ~change_mask;
-                gpcon |= gps_gpcon & change_mask;
-
-                __raw_writel(gpcon, base + OFFS_CON);
-
-                /* Now change any items that require DAT,CON */
-
-                __raw_writel(gps_gpdat, base + OFFS_DAT);
-                __raw_writel(gps_gpcon, base + OFFS_CON);
-                __raw_writel(gps->gpup, base + OFFS_UP);
-        }
-
-        S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
-                  index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
-}
-
-
-/** s3c2410_pm_restore_gpios()
- *
- * Restore the state of the GPIOs
- */
-
-void s3c_pm_restore_gpios(void)
-{
-        struct gpio_sleep *gps = gpio_save;
-        int gpio;
-
-        for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
-                s3c2410_pm_restore_gpio(gpio, gps);
-        }
-}
 
 void s3c_pm_restore_core(void)
 {
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c
index ee9188add8fb..ccb82e854962 100644
--- a/arch/arm/plat-s3c64xx/gpiolib.c
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -385,12 +385,19 @@ static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
 {
         chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
         chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
+        chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
 }
 
 static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
 {
         chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
         chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
+        chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
+}
+
+static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
+{
+        chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
 }
 
 static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
@@ -412,7 +419,8 @@ static __init int s3c64xx_gpiolib_init(void)
         s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
                             s3c64xx_gpiolib_add_4bit2);
 
-        s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL);
+        s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
+                            s3c64xx_gpiolib_add_2bit);
 
         return 0;
 }
diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/plat-s3c64xx/pm.c
index 98190aa364ae..07a6516a4f3c 100644
--- a/arch/arm/plat-s3c64xx/pm.c
+++ b/arch/arm/plat-s3c64xx/pm.c
@@ -96,17 +96,6 @@ void s3c_pm_configure_extint(void)
         __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
 }
 
-void s3c_pm_save_gpios(void)
-{
-        /* currently, unless the bootloader does something really stupid
-         * the gpio blocks should be maintained over their sleep.
-         */
-}
-
-void s3c_pm_restore_gpios(void)
-{
-}
-
 void s3c_pm_restore_core(void)
 {
         __raw_writel(0, S3C64XX_EINT_MASK);