diff options
-rw-r--r-- | arch/blackfin/mach-bf518/include/mach/blackfin.h | 10 | ||||
-rw-r--r-- | arch/blackfin/mach-bf527/include/mach/blackfin.h | 10 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/dma.c | 8 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h | 8 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/blackfin.h | 7 | ||||
-rw-r--r-- | arch/blackfin/mach-bf537/dma.c | 8 | ||||
-rw-r--r-- | arch/blackfin/mach-bf537/include/mach/blackfin.h | 90 | ||||
-rw-r--r-- | arch/blackfin/mach-bf538/include/mach/blackfin.h | 10 | ||||
-rw-r--r-- | arch/blackfin/mach-bf548/include/mach/blackfin.h | 89 |
9 files changed, 12 insertions, 228 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h index e8e14c2769ed..83421d393148 100644 --- a/arch/blackfin/mach-bf518/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h | |||
@@ -68,11 +68,6 @@ | |||
68 | #endif | 68 | #endif |
69 | #endif | 69 | #endif |
70 | 70 | ||
71 | /* UART_IIR Register */ | ||
72 | #define STATUS(x) ((x << 1) & 0x06) | ||
73 | #define STATUS_P1 0x02 | ||
74 | #define STATUS_P0 0x01 | ||
75 | |||
76 | #define BFIN_UART_NR_PORTS 2 | 71 | #define BFIN_UART_NR_PORTS 2 |
77 | 72 | ||
78 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 73 | #define OFFSET_THR 0x00 /* Transmit Holding register */ |
@@ -88,11 +83,6 @@ | |||
88 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | 83 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ |
89 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | 84 | #define OFFSET_GCTL 0x24 /* Global Control Register */ |
90 | 85 | ||
91 | /* DPMC*/ | ||
92 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | ||
93 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | ||
94 | #define STOPCK_OFF STOPCK | ||
95 | |||
96 | /* PLL_DIV Masks */ | 86 | /* PLL_DIV Masks */ |
97 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | 87 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ |
98 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | 88 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ |
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h index 03665a8e16be..ea9cb0fef8bc 100644 --- a/arch/blackfin/mach-bf527/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h | |||
@@ -56,11 +56,6 @@ | |||
56 | #endif | 56 | #endif |
57 | #endif | 57 | #endif |
58 | 58 | ||
59 | /* UART_IIR Register */ | ||
60 | #define STATUS(x) ((x << 1) & 0x06) | ||
61 | #define STATUS_P1 0x02 | ||
62 | #define STATUS_P0 0x01 | ||
63 | |||
64 | #define BFIN_UART_NR_PORTS 2 | 59 | #define BFIN_UART_NR_PORTS 2 |
65 | 60 | ||
66 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 61 | #define OFFSET_THR 0x00 /* Transmit Holding register */ |
@@ -76,11 +71,6 @@ | |||
76 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | 71 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ |
77 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | 72 | #define OFFSET_GCTL 0x24 /* Global Control Register */ |
78 | 73 | ||
79 | /* DPMC*/ | ||
80 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | ||
81 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | ||
82 | #define STOPCK_OFF STOPCK | ||
83 | |||
84 | /* PLL_DIV Masks */ | 74 | /* PLL_DIV Masks */ |
85 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | 75 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ |
86 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | 76 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ |
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c index 0a6eb8f24d98..7a443c37fb9f 100644 --- a/arch/blackfin/mach-bf533/dma.c +++ b/arch/blackfin/mach-bf533/dma.c | |||
@@ -76,12 +76,12 @@ int channel2irq(unsigned int channel) | |||
76 | ret_irq = IRQ_SPI; | 76 | ret_irq = IRQ_SPI; |
77 | break; | 77 | break; |
78 | 78 | ||
79 | case CH_UART_RX: | 79 | case CH_UART0_RX: |
80 | ret_irq = IRQ_UART_RX; | 80 | ret_irq = IRQ_UART0_RX; |
81 | break; | 81 | break; |
82 | 82 | ||
83 | case CH_UART_TX: | 83 | case CH_UART0_TX: |
84 | ret_irq = IRQ_UART_TX; | 84 | ret_irq = IRQ_UART0_TX; |
85 | break; | 85 | break; |
86 | 86 | ||
87 | case CH_MEM_STREAM0_SRC: | 87 | case CH_MEM_STREAM0_SRC: |
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h index 4062e24e759b..6965b4088c44 100644 --- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h | |||
@@ -131,11 +131,11 @@ struct bfin_serial_res { | |||
131 | struct bfin_serial_res bfin_serial_resource[] = { | 131 | struct bfin_serial_res bfin_serial_resource[] = { |
132 | { | 132 | { |
133 | 0xFFC00400, | 133 | 0xFFC00400, |
134 | IRQ_UART_RX, | 134 | IRQ_UART0_RX, |
135 | IRQ_UART_ERROR, | 135 | IRQ_UART0_ERROR, |
136 | #ifdef CONFIG_SERIAL_BFIN_DMA | 136 | #ifdef CONFIG_SERIAL_BFIN_DMA |
137 | CH_UART_TX, | 137 | CH_UART0_TX, |
138 | CH_UART_RX, | 138 | CH_UART0_RX, |
139 | #endif | 139 | #endif |
140 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | 140 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
141 | CONFIG_UART0_CTS_PIN, | 141 | CONFIG_UART0_CTS_PIN, |
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h index 39aa175f19f5..499e897a4f4f 100644 --- a/arch/blackfin/mach-bf533/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h | |||
@@ -43,13 +43,6 @@ | |||
43 | 43 | ||
44 | #define BFIN_UART_NR_PORTS 1 | 44 | #define BFIN_UART_NR_PORTS 1 |
45 | 45 | ||
46 | #define CH_UART_RX CH_UART0_RX | ||
47 | #define CH_UART_TX CH_UART0_TX | ||
48 | |||
49 | #define IRQ_UART_ERROR IRQ_UART0_ERROR | ||
50 | #define IRQ_UART_RX IRQ_UART0_RX | ||
51 | #define IRQ_UART_TX IRQ_UART0_TX | ||
52 | |||
53 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 46 | #define OFFSET_THR 0x00 /* Transmit Holding register */ |
54 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ | 47 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ |
55 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | 48 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ |
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c index 81185051de91..d23fc0edf2b9 100644 --- a/arch/blackfin/mach-bf537/dma.c +++ b/arch/blackfin/mach-bf537/dma.c | |||
@@ -96,12 +96,12 @@ int channel2irq(unsigned int channel) | |||
96 | ret_irq = IRQ_SPI; | 96 | ret_irq = IRQ_SPI; |
97 | break; | 97 | break; |
98 | 98 | ||
99 | case CH_UART_RX: | 99 | case CH_UART0_RX: |
100 | ret_irq = IRQ_UART_RX; | 100 | ret_irq = IRQ_UART0_RX; |
101 | break; | 101 | break; |
102 | 102 | ||
103 | case CH_UART_TX: | 103 | case CH_UART0_TX: |
104 | ret_irq = IRQ_UART_TX; | 104 | ret_irq = IRQ_UART0_TX; |
105 | break; | 105 | break; |
106 | 106 | ||
107 | case CH_MEM_STREAM0_SRC: | 107 | case CH_MEM_STREAM0_SRC: |
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h index f5e5015ad831..9ee8834c8f1a 100644 --- a/arch/blackfin/mach-bf537/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h | |||
@@ -45,96 +45,11 @@ | |||
45 | #if !defined(__ASSEMBLY__) | 45 | #if !defined(__ASSEMBLY__) |
46 | #include "cdefBF534.h" | 46 | #include "cdefBF534.h" |
47 | 47 | ||
48 | /* UART 0*/ | ||
49 | #define bfin_read_UART_THR() bfin_read_UART0_THR() | ||
50 | #define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) | ||
51 | #define bfin_read_UART_RBR() bfin_read_UART0_RBR() | ||
52 | #define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) | ||
53 | #define bfin_read_UART_DLL() bfin_read_UART0_DLL() | ||
54 | #define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) | ||
55 | #define bfin_read_UART_IER() bfin_read_UART0_IER() | ||
56 | #define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) | ||
57 | #define bfin_read_UART_DLH() bfin_read_UART0_DLH() | ||
58 | #define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) | ||
59 | #define bfin_read_UART_IIR() bfin_read_UART0_IIR() | ||
60 | #define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) | ||
61 | #define bfin_read_UART_LCR() bfin_read_UART0_LCR() | ||
62 | #define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) | ||
63 | #define bfin_read_UART_MCR() bfin_read_UART0_MCR() | ||
64 | #define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) | ||
65 | #define bfin_read_UART_LSR() bfin_read_UART0_LSR() | ||
66 | #define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) | ||
67 | #define bfin_read_UART_SCR() bfin_read_UART0_SCR() | ||
68 | #define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) | ||
69 | #define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() | ||
70 | #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) | ||
71 | |||
72 | #if defined(CONFIG_BF537) || defined(CONFIG_BF536) | 48 | #if defined(CONFIG_BF537) || defined(CONFIG_BF536) |
73 | #include "cdefBF537.h" | 49 | #include "cdefBF537.h" |
74 | #endif | 50 | #endif |
75 | #endif | 51 | #endif |
76 | 52 | ||
77 | /* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */ | ||
78 | |||
79 | /* UART_IIR Register */ | ||
80 | #define STATUS(x) ((x << 1) & 0x06) | ||
81 | #define STATUS_P1 0x02 | ||
82 | #define STATUS_P0 0x01 | ||
83 | |||
84 | /* DMA Channel */ | ||
85 | #define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX() | ||
86 | #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val) | ||
87 | #define CH_UART_RX CH_UART0_RX | ||
88 | #define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX() | ||
89 | #define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val) | ||
90 | #define CH_UART_TX CH_UART0_TX | ||
91 | |||
92 | /* System Interrupt Controller */ | ||
93 | #define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX() | ||
94 | #define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val) | ||
95 | #define IRQ_UART_RX IRQ_UART0_RX | ||
96 | #define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX() | ||
97 | #define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val) | ||
98 | #define IRQ_UART_TX IRQ_UART0_TX | ||
99 | #define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR() | ||
100 | #define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val) | ||
101 | #define IRQ_UART_ERROR IRQ_UART0_ERROR | ||
102 | |||
103 | /* MMR Registers*/ | ||
104 | #define bfin_read_UART_THR() bfin_read_UART0_THR() | ||
105 | #define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) | ||
106 | #define BFIN_UART_THR UART0_THR | ||
107 | #define bfin_read_UART_RBR() bfin_read_UART0_RBR() | ||
108 | #define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) | ||
109 | #define BFIN_UART_RBR UART0_RBR | ||
110 | #define bfin_read_UART_DLL() bfin_read_UART0_DLL() | ||
111 | #define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) | ||
112 | #define BFIN_UART_DLL UART0_DLL | ||
113 | #define bfin_read_UART_IER() bfin_read_UART0_IER() | ||
114 | #define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) | ||
115 | #define BFIN_UART_IER UART0_IER | ||
116 | #define bfin_read_UART_DLH() bfin_read_UART0_DLH() | ||
117 | #define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) | ||
118 | #define BFIN_UART_DLH UART0_DLH | ||
119 | #define bfin_read_UART_IIR() bfin_read_UART0_IIR() | ||
120 | #define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) | ||
121 | #define BFIN_UART_IIR UART0_IIR | ||
122 | #define bfin_read_UART_LCR() bfin_read_UART0_LCR() | ||
123 | #define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) | ||
124 | #define BFIN_UART_LCR UART0_LCR | ||
125 | #define bfin_read_UART_MCR() bfin_read_UART0_MCR() | ||
126 | #define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) | ||
127 | #define BFIN_UART_MCR UART0_MCR | ||
128 | #define bfin_read_UART_LSR() bfin_read_UART0_LSR() | ||
129 | #define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) | ||
130 | #define BFIN_UART_LSR UART0_LSR | ||
131 | #define bfin_read_UART_SCR() bfin_read_UART0_SCR() | ||
132 | #define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) | ||
133 | #define BFIN_UART_SCR UART0_SCR | ||
134 | #define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() | ||
135 | #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) | ||
136 | #define BFIN_UART_GCTL UART0_GCTL | ||
137 | |||
138 | #define BFIN_UART_NR_PORTS 2 | 53 | #define BFIN_UART_NR_PORTS 2 |
139 | 54 | ||
140 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 55 | #define OFFSET_THR 0x00 /* Transmit Holding register */ |
@@ -150,11 +65,6 @@ | |||
150 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | 65 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ |
151 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | 66 | #define OFFSET_GCTL 0x24 /* Global Control Register */ |
152 | 67 | ||
153 | /* DPMC*/ | ||
154 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | ||
155 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | ||
156 | #define STOPCK_OFF STOPCK | ||
157 | |||
158 | /* PLL_DIV Masks */ | 68 | /* PLL_DIV Masks */ |
159 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | 69 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ |
160 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | 70 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ |
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h index 9496196ac164..5ecee1690957 100644 --- a/arch/blackfin/mach-bf538/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h | |||
@@ -47,11 +47,6 @@ | |||
47 | #endif | 47 | #endif |
48 | #endif | 48 | #endif |
49 | 49 | ||
50 | /* UART_IIR Register */ | ||
51 | #define STATUS(x) ((x << 1) & 0x06) | ||
52 | #define STATUS_P1 0x02 | ||
53 | #define STATUS_P0 0x01 | ||
54 | |||
55 | #define BFIN_UART_NR_PORTS 3 | 50 | #define BFIN_UART_NR_PORTS 3 |
56 | 51 | ||
57 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 52 | #define OFFSET_THR 0x00 /* Transmit Holding register */ |
@@ -67,11 +62,6 @@ | |||
67 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | 62 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ |
68 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | 63 | #define OFFSET_GCTL 0x24 /* Global Control Register */ |
69 | 64 | ||
70 | /* DPMC*/ | ||
71 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | ||
72 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | ||
73 | #define STOPCK_OFF STOPCK | ||
74 | |||
75 | /* PLL_DIV Masks */ | 65 | /* PLL_DIV Masks */ |
76 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | 66 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ |
77 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | 67 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ |
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h index 6b97396d817f..318667b2f036 100644 --- a/arch/blackfin/mach-bf548/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h | |||
@@ -72,97 +72,8 @@ | |||
72 | #include "cdefBF549.h" | 72 | #include "cdefBF549.h" |
73 | #endif | 73 | #endif |
74 | 74 | ||
75 | /* UART 1*/ | ||
76 | #define bfin_read_UART_THR() bfin_read_UART1_THR() | ||
77 | #define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) | ||
78 | #define bfin_read_UART_RBR() bfin_read_UART1_RBR() | ||
79 | #define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) | ||
80 | #define bfin_read_UART_DLL() bfin_read_UART1_DLL() | ||
81 | #define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) | ||
82 | #define bfin_read_UART_IER() bfin_read_UART1_IER() | ||
83 | #define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) | ||
84 | #define bfin_read_UART_DLH() bfin_read_UART1_DLH() | ||
85 | #define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) | ||
86 | #define bfin_read_UART_IIR() bfin_read_UART1_IIR() | ||
87 | #define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) | ||
88 | #define bfin_read_UART_LCR() bfin_read_UART1_LCR() | ||
89 | #define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) | ||
90 | #define bfin_read_UART_MCR() bfin_read_UART1_MCR() | ||
91 | #define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) | ||
92 | #define bfin_read_UART_LSR() bfin_read_UART1_LSR() | ||
93 | #define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) | ||
94 | #define bfin_read_UART_SCR() bfin_read_UART1_SCR() | ||
95 | #define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) | ||
96 | #define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() | ||
97 | #define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) | ||
98 | |||
99 | #endif | 75 | #endif |
100 | 76 | ||
101 | /* MAP used DEFINES from BF533 to BF54x - so we don't need to change | ||
102 | * them in the driver, kernel, etc. */ | ||
103 | |||
104 | /* UART_IIR Register */ | ||
105 | #define STATUS(x) ((x << 1) & 0x06) | ||
106 | #define STATUS_P1 0x02 | ||
107 | #define STATUS_P0 0x01 | ||
108 | |||
109 | /* UART 0*/ | ||
110 | |||
111 | /* DMA Channel */ | ||
112 | #define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() | ||
113 | #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) | ||
114 | #define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() | ||
115 | #define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val) | ||
116 | #define CH_UART_RX CH_UART1_RX | ||
117 | #define CH_UART_TX CH_UART1_TX | ||
118 | |||
119 | /* System Interrupt Controller */ | ||
120 | #define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX() | ||
121 | #define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val) | ||
122 | #define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX() | ||
123 | #define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val) | ||
124 | #define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR() | ||
125 | #define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val) | ||
126 | #define IRQ_UART_RX IRQ_UART1_RX | ||
127 | #define IRQ_UART_TX IRQ_UART1_TX | ||
128 | #define IRQ_UART_ERROR IRQ_UART1_ERROR | ||
129 | |||
130 | /* MMR Registers*/ | ||
131 | #define bfin_read_UART_THR() bfin_read_UART1_THR() | ||
132 | #define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) | ||
133 | #define bfin_read_UART_RBR() bfin_read_UART1_RBR() | ||
134 | #define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) | ||
135 | #define bfin_read_UART_DLL() bfin_read_UART1_DLL() | ||
136 | #define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) | ||
137 | #define bfin_read_UART_IER() bfin_read_UART1_IER() | ||
138 | #define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) | ||
139 | #define bfin_read_UART_DLH() bfin_read_UART1_DLH() | ||
140 | #define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) | ||
141 | #define bfin_read_UART_IIR() bfin_read_UART1_IIR() | ||
142 | #define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) | ||
143 | #define bfin_read_UART_LCR() bfin_read_UART1_LCR() | ||
144 | #define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) | ||
145 | #define bfin_read_UART_MCR() bfin_read_UART1_MCR() | ||
146 | #define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) | ||
147 | #define bfin_read_UART_LSR() bfin_read_UART1_LSR() | ||
148 | #define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) | ||
149 | #define bfin_read_UART_SCR() bfin_read_UART1_SCR() | ||
150 | #define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) | ||
151 | #define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() | ||
152 | #define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) | ||
153 | |||
154 | #define BFIN_UART_THR UART1_THR | ||
155 | #define BFIN_UART_RBR UART1_RBR | ||
156 | #define BFIN_UART_DLL UART1_DLL | ||
157 | #define BFIN_UART_IER UART1_IER | ||
158 | #define BFIN_UART_DLH UART1_DLH | ||
159 | #define BFIN_UART_IIR UART1_IIR | ||
160 | #define BFIN_UART_LCR UART1_LCR | ||
161 | #define BFIN_UART_MCR UART1_MCR | ||
162 | #define BFIN_UART_LSR UART1_LSR | ||
163 | #define BFIN_UART_SCR UART1_SCR | ||
164 | #define BFIN_UART_GCTL UART1_GCTL | ||
165 | |||
166 | #define BFIN_UART_NR_PORTS 4 | 77 | #define BFIN_UART_NR_PORTS 4 |
167 | 78 | ||
168 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | 79 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ |