diff options
-rw-r--r-- | drivers/mfd/Kconfig | 7 | ||||
-rw-r--r-- | drivers/mfd/Makefile | 1 | ||||
-rw-r--r-- | drivers/mfd/asic3.c | 588 | ||||
-rw-r--r-- | include/linux/mfd/asic3.h | 497 |
4 files changed, 1093 insertions, 0 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 25716193a534..0c886c882385 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig | |||
@@ -15,6 +15,13 @@ config MFD_SM501 | |||
15 | interface. The device may be connected by PCI or local bus with | 15 | interface. The device may be connected by PCI or local bus with |
16 | varying functions enabled. | 16 | varying functions enabled. |
17 | 17 | ||
18 | config MFD_ASIC3 | ||
19 | bool "Support for Compaq ASIC3" | ||
20 | depends on GENERIC_HARDIRQS && ARM | ||
21 | ---help--- | ||
22 | This driver supports the ASIC3 multifunction chip found on many | ||
23 | PDAs (mainly iPAQ and HTC based ones) | ||
24 | |||
18 | endmenu | 25 | endmenu |
19 | 26 | ||
20 | menu "Multimedia Capabilities Port drivers" | 27 | menu "Multimedia Capabilities Port drivers" |
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 51432091b323..521cd5cb68af 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile | |||
@@ -3,6 +3,7 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | obj-$(CONFIG_MFD_SM501) += sm501.o | 5 | obj-$(CONFIG_MFD_SM501) += sm501.o |
6 | obj-$(CONFIG_MFD_ASIC3) += asic3.o | ||
6 | 7 | ||
7 | obj-$(CONFIG_MCP) += mcp-core.o | 8 | obj-$(CONFIG_MCP) += mcp-core.o |
8 | obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o | 9 | obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o |
diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c new file mode 100644 index 000000000000..63fb1ff3ad10 --- /dev/null +++ b/drivers/mfd/asic3.c | |||
@@ -0,0 +1,588 @@ | |||
1 | /* | ||
2 | * driver/mfd/asic3.c | ||
3 | * | ||
4 | * Compaq ASIC3 support. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Copyright 2001 Compaq Computer Corporation. | ||
11 | * Copyright 2004-2005 Phil Blundell | ||
12 | * Copyright 2007 OpenedHand Ltd. | ||
13 | * | ||
14 | * Authors: Phil Blundell <pb@handhelds.org>, | ||
15 | * Samuel Ortiz <sameo@openedhand.com> | ||
16 | * | ||
17 | */ | ||
18 | |||
19 | #include <linux/version.h> | ||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/irq.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/spinlock.h> | ||
24 | #include <linux/platform_device.h> | ||
25 | |||
26 | #include <linux/mfd/asic3.h> | ||
27 | |||
28 | static inline void asic3_write_register(struct asic3 *asic, | ||
29 | unsigned int reg, u32 value) | ||
30 | { | ||
31 | iowrite16(value, (unsigned long)asic->mapping + | ||
32 | (reg >> asic->bus_shift)); | ||
33 | } | ||
34 | |||
35 | static inline u32 asic3_read_register(struct asic3 *asic, | ||
36 | unsigned int reg) | ||
37 | { | ||
38 | return ioread16((unsigned long)asic->mapping + | ||
39 | (reg >> asic->bus_shift)); | ||
40 | } | ||
41 | |||
42 | /* IRQs */ | ||
43 | #define MAX_ASIC_ISR_LOOPS 20 | ||
44 | #define ASIC3_GPIO_Base_INCR \ | ||
45 | (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base) | ||
46 | |||
47 | static void asic3_irq_flip_edge(struct asic3 *asic, | ||
48 | u32 base, int bit) | ||
49 | { | ||
50 | u16 edge; | ||
51 | unsigned long flags; | ||
52 | |||
53 | spin_lock_irqsave(&asic->lock, flags); | ||
54 | edge = asic3_read_register(asic, | ||
55 | base + ASIC3_GPIO_EdgeTrigger); | ||
56 | edge ^= bit; | ||
57 | asic3_write_register(asic, | ||
58 | base + ASIC3_GPIO_EdgeTrigger, edge); | ||
59 | spin_unlock_irqrestore(&asic->lock, flags); | ||
60 | } | ||
61 | |||
62 | static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc) | ||
63 | { | ||
64 | int iter, i; | ||
65 | unsigned long flags; | ||
66 | struct asic3 *asic; | ||
67 | |||
68 | desc->chip->ack(irq); | ||
69 | |||
70 | asic = desc->handler_data; | ||
71 | |||
72 | for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) { | ||
73 | u32 status; | ||
74 | int bank; | ||
75 | |||
76 | spin_lock_irqsave(&asic->lock, flags); | ||
77 | status = asic3_read_register(asic, | ||
78 | ASIC3_OFFSET(INTR, PIntStat)); | ||
79 | spin_unlock_irqrestore(&asic->lock, flags); | ||
80 | |||
81 | /* Check all ten register bits */ | ||
82 | if ((status & 0x3ff) == 0) | ||
83 | break; | ||
84 | |||
85 | /* Handle GPIO IRQs */ | ||
86 | for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) { | ||
87 | if (status & (1 << bank)) { | ||
88 | unsigned long base, istat; | ||
89 | |||
90 | base = ASIC3_GPIO_A_Base | ||
91 | + bank * ASIC3_GPIO_Base_INCR; | ||
92 | |||
93 | spin_lock_irqsave(&asic->lock, flags); | ||
94 | istat = asic3_read_register(asic, | ||
95 | base + | ||
96 | ASIC3_GPIO_IntStatus); | ||
97 | /* Clearing IntStatus */ | ||
98 | asic3_write_register(asic, | ||
99 | base + | ||
100 | ASIC3_GPIO_IntStatus, 0); | ||
101 | spin_unlock_irqrestore(&asic->lock, flags); | ||
102 | |||
103 | for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) { | ||
104 | int bit = (1 << i); | ||
105 | unsigned int irqnr; | ||
106 | |||
107 | if (!(istat & bit)) | ||
108 | continue; | ||
109 | |||
110 | irqnr = asic->irq_base + | ||
111 | (ASIC3_GPIOS_PER_BANK * bank) | ||
112 | + i; | ||
113 | desc = irq_desc + irqnr; | ||
114 | desc->handle_irq(irqnr, desc); | ||
115 | if (asic->irq_bothedge[bank] & bit) | ||
116 | asic3_irq_flip_edge(asic, base, | ||
117 | bit); | ||
118 | } | ||
119 | } | ||
120 | } | ||
121 | |||
122 | /* Handle remaining IRQs in the status register */ | ||
123 | for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) { | ||
124 | /* They start at bit 4 and go up */ | ||
125 | if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) { | ||
126 | desc = irq_desc + + i; | ||
127 | desc->handle_irq(asic->irq_base + i, | ||
128 | desc); | ||
129 | } | ||
130 | } | ||
131 | } | ||
132 | |||
133 | if (iter >= MAX_ASIC_ISR_LOOPS) | ||
134 | printk(KERN_ERR "%s: interrupt processing overrun\n", | ||
135 | __FUNCTION__); | ||
136 | } | ||
137 | |||
138 | static inline int asic3_irq_to_bank(struct asic3 *asic, int irq) | ||
139 | { | ||
140 | int n; | ||
141 | |||
142 | n = (irq - asic->irq_base) >> 4; | ||
143 | |||
144 | return (n * (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base)); | ||
145 | } | ||
146 | |||
147 | static inline int asic3_irq_to_index(struct asic3 *asic, int irq) | ||
148 | { | ||
149 | return (irq - asic->irq_base) & 0xf; | ||
150 | } | ||
151 | |||
152 | static void asic3_mask_gpio_irq(unsigned int irq) | ||
153 | { | ||
154 | struct asic3 *asic = get_irq_chip_data(irq); | ||
155 | u32 val, bank, index; | ||
156 | unsigned long flags; | ||
157 | |||
158 | bank = asic3_irq_to_bank(asic, irq); | ||
159 | index = asic3_irq_to_index(asic, irq); | ||
160 | |||
161 | spin_lock_irqsave(&asic->lock, flags); | ||
162 | val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask); | ||
163 | val |= 1 << index; | ||
164 | asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val); | ||
165 | spin_unlock_irqrestore(&asic->lock, flags); | ||
166 | } | ||
167 | |||
168 | static void asic3_mask_irq(unsigned int irq) | ||
169 | { | ||
170 | struct asic3 *asic = get_irq_chip_data(irq); | ||
171 | int regval; | ||
172 | unsigned long flags; | ||
173 | |||
174 | spin_lock_irqsave(&asic->lock, flags); | ||
175 | regval = asic3_read_register(asic, | ||
176 | ASIC3_INTR_Base + | ||
177 | ASIC3_INTR_IntMask); | ||
178 | |||
179 | regval &= ~(ASIC3_INTMASK_MASK0 << | ||
180 | (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); | ||
181 | |||
182 | asic3_write_register(asic, | ||
183 | ASIC3_INTR_Base + | ||
184 | ASIC3_INTR_IntMask, | ||
185 | regval); | ||
186 | spin_unlock_irqrestore(&asic->lock, flags); | ||
187 | } | ||
188 | |||
189 | static void asic3_unmask_gpio_irq(unsigned int irq) | ||
190 | { | ||
191 | struct asic3 *asic = get_irq_chip_data(irq); | ||
192 | u32 val, bank, index; | ||
193 | unsigned long flags; | ||
194 | |||
195 | bank = asic3_irq_to_bank(asic, irq); | ||
196 | index = asic3_irq_to_index(asic, irq); | ||
197 | |||
198 | spin_lock_irqsave(&asic->lock, flags); | ||
199 | val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask); | ||
200 | val &= ~(1 << index); | ||
201 | asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val); | ||
202 | spin_unlock_irqrestore(&asic->lock, flags); | ||
203 | } | ||
204 | |||
205 | static void asic3_unmask_irq(unsigned int irq) | ||
206 | { | ||
207 | struct asic3 *asic = get_irq_chip_data(irq); | ||
208 | int regval; | ||
209 | unsigned long flags; | ||
210 | |||
211 | spin_lock_irqsave(&asic->lock, flags); | ||
212 | regval = asic3_read_register(asic, | ||
213 | ASIC3_INTR_Base + | ||
214 | ASIC3_INTR_IntMask); | ||
215 | |||
216 | regval |= (ASIC3_INTMASK_MASK0 << | ||
217 | (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); | ||
218 | |||
219 | asic3_write_register(asic, | ||
220 | ASIC3_INTR_Base + | ||
221 | ASIC3_INTR_IntMask, | ||
222 | regval); | ||
223 | spin_unlock_irqrestore(&asic->lock, flags); | ||
224 | } | ||
225 | |||
226 | static int asic3_gpio_irq_type(unsigned int irq, unsigned int type) | ||
227 | { | ||
228 | struct asic3 *asic = get_irq_chip_data(irq); | ||
229 | u32 bank, index; | ||
230 | u16 trigger, level, edge, bit; | ||
231 | unsigned long flags; | ||
232 | |||
233 | bank = asic3_irq_to_bank(asic, irq); | ||
234 | index = asic3_irq_to_index(asic, irq); | ||
235 | bit = 1<<index; | ||
236 | |||
237 | spin_lock_irqsave(&asic->lock, flags); | ||
238 | level = asic3_read_register(asic, | ||
239 | bank + ASIC3_GPIO_LevelTrigger); | ||
240 | edge = asic3_read_register(asic, | ||
241 | bank + ASIC3_GPIO_EdgeTrigger); | ||
242 | trigger = asic3_read_register(asic, | ||
243 | bank + ASIC3_GPIO_TriggerType); | ||
244 | asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit; | ||
245 | |||
246 | if (type == IRQT_RISING) { | ||
247 | trigger |= bit; | ||
248 | edge |= bit; | ||
249 | } else if (type == IRQT_FALLING) { | ||
250 | trigger |= bit; | ||
251 | edge &= ~bit; | ||
252 | } else if (type == IRQT_BOTHEDGE) { | ||
253 | trigger |= bit; | ||
254 | if (asic3_gpio_get_value(asic, irq - asic->irq_base)) | ||
255 | edge &= ~bit; | ||
256 | else | ||
257 | edge |= bit; | ||
258 | asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit; | ||
259 | } else if (type == IRQT_LOW) { | ||
260 | trigger &= ~bit; | ||
261 | level &= ~bit; | ||
262 | } else if (type == IRQT_HIGH) { | ||
263 | trigger &= ~bit; | ||
264 | level |= bit; | ||
265 | } else { | ||
266 | /* | ||
267 | * if type == IRQT_NOEDGE, we should mask interrupts, but | ||
268 | * be careful to not unmask them if mask was also called. | ||
269 | * Probably need internal state for mask. | ||
270 | */ | ||
271 | printk(KERN_NOTICE "asic3: irq type not changed.\n"); | ||
272 | } | ||
273 | asic3_write_register(asic, bank + ASIC3_GPIO_LevelTrigger, | ||
274 | level); | ||
275 | asic3_write_register(asic, bank + ASIC3_GPIO_EdgeTrigger, | ||
276 | edge); | ||
277 | asic3_write_register(asic, bank + ASIC3_GPIO_TriggerType, | ||
278 | trigger); | ||
279 | spin_unlock_irqrestore(&asic->lock, flags); | ||
280 | return 0; | ||
281 | } | ||
282 | |||
283 | static struct irq_chip asic3_gpio_irq_chip = { | ||
284 | .name = "ASIC3-GPIO", | ||
285 | .ack = asic3_mask_gpio_irq, | ||
286 | .mask = asic3_mask_gpio_irq, | ||
287 | .unmask = asic3_unmask_gpio_irq, | ||
288 | .set_type = asic3_gpio_irq_type, | ||
289 | }; | ||
290 | |||
291 | static struct irq_chip asic3_irq_chip = { | ||
292 | .name = "ASIC3", | ||
293 | .ack = asic3_mask_irq, | ||
294 | .mask = asic3_mask_irq, | ||
295 | .unmask = asic3_unmask_irq, | ||
296 | }; | ||
297 | |||
298 | static int asic3_irq_probe(struct platform_device *pdev) | ||
299 | { | ||
300 | struct asic3 *asic = platform_get_drvdata(pdev); | ||
301 | unsigned long clksel = 0; | ||
302 | unsigned int irq, irq_base; | ||
303 | |||
304 | asic->irq_nr = platform_get_irq(pdev, 0); | ||
305 | if (asic->irq_nr < 0) | ||
306 | return asic->irq_nr; | ||
307 | |||
308 | /* turn on clock to IRQ controller */ | ||
309 | clksel |= CLOCK_SEL_CX; | ||
310 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), | ||
311 | clksel); | ||
312 | |||
313 | irq_base = asic->irq_base; | ||
314 | |||
315 | for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { | ||
316 | if (irq < asic->irq_base + ASIC3_NUM_GPIOS) | ||
317 | set_irq_chip(irq, &asic3_gpio_irq_chip); | ||
318 | else | ||
319 | set_irq_chip(irq, &asic3_irq_chip); | ||
320 | |||
321 | set_irq_chip_data(irq, asic); | ||
322 | set_irq_handler(irq, handle_level_irq); | ||
323 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
324 | } | ||
325 | |||
326 | asic3_write_register(asic, ASIC3_OFFSET(INTR, IntMask), | ||
327 | ASIC3_INTMASK_GINTMASK); | ||
328 | |||
329 | set_irq_chained_handler(asic->irq_nr, asic3_irq_demux); | ||
330 | set_irq_type(asic->irq_nr, IRQT_RISING); | ||
331 | set_irq_data(asic->irq_nr, asic); | ||
332 | |||
333 | return 0; | ||
334 | } | ||
335 | |||
336 | static void asic3_irq_remove(struct platform_device *pdev) | ||
337 | { | ||
338 | struct asic3 *asic = platform_get_drvdata(pdev); | ||
339 | unsigned int irq, irq_base; | ||
340 | |||
341 | irq_base = asic->irq_base; | ||
342 | |||
343 | for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { | ||
344 | set_irq_flags(irq, 0); | ||
345 | set_irq_handler(irq, NULL); | ||
346 | set_irq_chip(irq, NULL); | ||
347 | set_irq_chip_data(irq, NULL); | ||
348 | } | ||
349 | set_irq_chained_handler(asic->irq_nr, NULL); | ||
350 | } | ||
351 | |||
352 | /* GPIOs */ | ||
353 | static inline u32 asic3_get_gpio(struct asic3 *asic, unsigned int base, | ||
354 | unsigned int function) | ||
355 | { | ||
356 | return asic3_read_register(asic, base + function); | ||
357 | } | ||
358 | |||
359 | static void asic3_set_gpio(struct asic3 *asic, unsigned int base, | ||
360 | unsigned int function, u32 bits, u32 val) | ||
361 | { | ||
362 | unsigned long flags; | ||
363 | |||
364 | spin_lock_irqsave(&asic->lock, flags); | ||
365 | val |= (asic3_read_register(asic, base + function) & ~bits); | ||
366 | |||
367 | asic3_write_register(asic, base + function, val); | ||
368 | spin_unlock_irqrestore(&asic->lock, flags); | ||
369 | } | ||
370 | |||
371 | #define asic3_get_gpio_a(asic, fn) \ | ||
372 | asic3_get_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn) | ||
373 | #define asic3_get_gpio_b(asic, fn) \ | ||
374 | asic3_get_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn) | ||
375 | #define asic3_get_gpio_c(asic, fn) \ | ||
376 | asic3_get_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn) | ||
377 | #define asic3_get_gpio_d(asic, fn) \ | ||
378 | asic3_get_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn) | ||
379 | |||
380 | #define asic3_set_gpio_a(asic, fn, bits, val) \ | ||
381 | asic3_set_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn, bits, val) | ||
382 | #define asic3_set_gpio_b(asic, fn, bits, val) \ | ||
383 | asic3_set_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn, bits, val) | ||
384 | #define asic3_set_gpio_c(asic, fn, bits, val) \ | ||
385 | asic3_set_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn, bits, val) | ||
386 | #define asic3_set_gpio_d(asic, fn, bits, val) \ | ||
387 | asic3_set_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn, bits, val) | ||
388 | |||
389 | #define asic3_set_gpio_banks(asic, fn, bits, pdata, field) \ | ||
390 | do { \ | ||
391 | asic3_set_gpio_a((asic), fn, (bits), (pdata)->gpio_a.field); \ | ||
392 | asic3_set_gpio_b((asic), fn, (bits), (pdata)->gpio_b.field); \ | ||
393 | asic3_set_gpio_c((asic), fn, (bits), (pdata)->gpio_c.field); \ | ||
394 | asic3_set_gpio_d((asic), fn, (bits), (pdata)->gpio_d.field); \ | ||
395 | } while (0) | ||
396 | |||
397 | int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio) | ||
398 | { | ||
399 | u32 mask = ASIC3_GPIO_bit(gpio); | ||
400 | |||
401 | switch (gpio >> 4) { | ||
402 | case ASIC3_GPIO_BANK_A: | ||
403 | return asic3_get_gpio_a(asic, Status) & mask; | ||
404 | case ASIC3_GPIO_BANK_B: | ||
405 | return asic3_get_gpio_b(asic, Status) & mask; | ||
406 | case ASIC3_GPIO_BANK_C: | ||
407 | return asic3_get_gpio_c(asic, Status) & mask; | ||
408 | case ASIC3_GPIO_BANK_D: | ||
409 | return asic3_get_gpio_d(asic, Status) & mask; | ||
410 | default: | ||
411 | printk(KERN_ERR "%s: invalid GPIO value 0x%x", | ||
412 | __FUNCTION__, gpio); | ||
413 | return -EINVAL; | ||
414 | } | ||
415 | } | ||
416 | EXPORT_SYMBOL(asic3_gpio_get_value); | ||
417 | |||
418 | void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val) | ||
419 | { | ||
420 | u32 mask = ASIC3_GPIO_bit(gpio); | ||
421 | u32 bitval = 0; | ||
422 | if (val) | ||
423 | bitval = mask; | ||
424 | |||
425 | switch (gpio >> 4) { | ||
426 | case ASIC3_GPIO_BANK_A: | ||
427 | asic3_set_gpio_a(asic, Out, mask, bitval); | ||
428 | return; | ||
429 | case ASIC3_GPIO_BANK_B: | ||
430 | asic3_set_gpio_b(asic, Out, mask, bitval); | ||
431 | return; | ||
432 | case ASIC3_GPIO_BANK_C: | ||
433 | asic3_set_gpio_c(asic, Out, mask, bitval); | ||
434 | return; | ||
435 | case ASIC3_GPIO_BANK_D: | ||
436 | asic3_set_gpio_d(asic, Out, mask, bitval); | ||
437 | return; | ||
438 | default: | ||
439 | printk(KERN_ERR "%s: invalid GPIO value 0x%x", | ||
440 | __FUNCTION__, gpio); | ||
441 | return; | ||
442 | } | ||
443 | } | ||
444 | EXPORT_SYMBOL(asic3_gpio_set_value); | ||
445 | |||
446 | static int asic3_gpio_probe(struct platform_device *pdev) | ||
447 | { | ||
448 | struct asic3_platform_data *pdata = pdev->dev.platform_data; | ||
449 | struct asic3 *asic = platform_get_drvdata(pdev); | ||
450 | |||
451 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff); | ||
452 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff); | ||
453 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff); | ||
454 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff); | ||
455 | |||
456 | asic3_set_gpio_a(asic, SleepMask, 0xffff, 0xffff); | ||
457 | asic3_set_gpio_b(asic, SleepMask, 0xffff, 0xffff); | ||
458 | asic3_set_gpio_c(asic, SleepMask, 0xffff, 0xffff); | ||
459 | asic3_set_gpio_d(asic, SleepMask, 0xffff, 0xffff); | ||
460 | |||
461 | if (pdata) { | ||
462 | asic3_set_gpio_banks(asic, Out, 0xffff, pdata, init); | ||
463 | asic3_set_gpio_banks(asic, Direction, 0xffff, pdata, dir); | ||
464 | asic3_set_gpio_banks(asic, SleepMask, 0xffff, pdata, | ||
465 | sleep_mask); | ||
466 | asic3_set_gpio_banks(asic, SleepOut, 0xffff, pdata, sleep_out); | ||
467 | asic3_set_gpio_banks(asic, BattFaultOut, 0xffff, pdata, | ||
468 | batt_fault_out); | ||
469 | asic3_set_gpio_banks(asic, SleepConf, 0xffff, pdata, | ||
470 | sleep_conf); | ||
471 | asic3_set_gpio_banks(asic, AltFunction, 0xffff, pdata, | ||
472 | alt_function); | ||
473 | } | ||
474 | |||
475 | return 0; | ||
476 | } | ||
477 | |||
478 | static void asic3_gpio_remove(struct platform_device *pdev) | ||
479 | { | ||
480 | return; | ||
481 | } | ||
482 | |||
483 | |||
484 | /* Core */ | ||
485 | static int asic3_probe(struct platform_device *pdev) | ||
486 | { | ||
487 | struct asic3_platform_data *pdata = pdev->dev.platform_data; | ||
488 | struct asic3 *asic; | ||
489 | struct resource *mem; | ||
490 | unsigned long clksel; | ||
491 | int ret; | ||
492 | |||
493 | asic = kzalloc(sizeof(struct asic3), GFP_KERNEL); | ||
494 | if (!asic) | ||
495 | return -ENOMEM; | ||
496 | |||
497 | spin_lock_init(&asic->lock); | ||
498 | platform_set_drvdata(pdev, asic); | ||
499 | asic->dev = &pdev->dev; | ||
500 | |||
501 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
502 | if (!mem) { | ||
503 | ret = -ENOMEM; | ||
504 | printk(KERN_ERR "asic3: no MEM resource\n"); | ||
505 | goto err_out_1; | ||
506 | } | ||
507 | |||
508 | asic->mapping = ioremap(mem->start, PAGE_SIZE); | ||
509 | if (!asic->mapping) { | ||
510 | ret = -ENOMEM; | ||
511 | printk(KERN_ERR "asic3: couldn't ioremap\n"); | ||
512 | goto err_out_1; | ||
513 | } | ||
514 | |||
515 | asic->irq_base = pdata->irq_base; | ||
516 | |||
517 | if (pdata && pdata->bus_shift) | ||
518 | asic->bus_shift = 2 - pdata->bus_shift; | ||
519 | else | ||
520 | asic->bus_shift = 0; | ||
521 | |||
522 | clksel = 0; | ||
523 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); | ||
524 | |||
525 | ret = asic3_irq_probe(pdev); | ||
526 | if (ret < 0) { | ||
527 | printk(KERN_ERR "asic3: couldn't probe IRQs\n"); | ||
528 | goto err_out_2; | ||
529 | } | ||
530 | asic3_gpio_probe(pdev); | ||
531 | |||
532 | if (pdata->children) { | ||
533 | int i; | ||
534 | for (i = 0; i < pdata->n_children; i++) { | ||
535 | pdata->children[i]->dev.parent = &pdev->dev; | ||
536 | platform_device_register(pdata->children[i]); | ||
537 | } | ||
538 | } | ||
539 | |||
540 | printk(KERN_INFO "ASIC3 Core driver\n"); | ||
541 | |||
542 | return 0; | ||
543 | |||
544 | err_out_2: | ||
545 | iounmap(asic->mapping); | ||
546 | err_out_1: | ||
547 | kfree(asic); | ||
548 | |||
549 | return ret; | ||
550 | } | ||
551 | |||
552 | static int asic3_remove(struct platform_device *pdev) | ||
553 | { | ||
554 | struct asic3 *asic = platform_get_drvdata(pdev); | ||
555 | |||
556 | asic3_gpio_remove(pdev); | ||
557 | asic3_irq_remove(pdev); | ||
558 | |||
559 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); | ||
560 | |||
561 | iounmap(asic->mapping); | ||
562 | |||
563 | kfree(asic); | ||
564 | |||
565 | return 0; | ||
566 | } | ||
567 | |||
568 | static void asic3_shutdown(struct platform_device *pdev) | ||
569 | { | ||
570 | } | ||
571 | |||
572 | static struct platform_driver asic3_device_driver = { | ||
573 | .driver = { | ||
574 | .name = "asic3", | ||
575 | }, | ||
576 | .probe = asic3_probe, | ||
577 | .remove = __devexit_p(asic3_remove), | ||
578 | .shutdown = asic3_shutdown, | ||
579 | }; | ||
580 | |||
581 | static int __init asic3_init(void) | ||
582 | { | ||
583 | int retval = 0; | ||
584 | retval = platform_driver_register(&asic3_device_driver); | ||
585 | return retval; | ||
586 | } | ||
587 | |||
588 | subsys_initcall(asic3_init); | ||
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h new file mode 100644 index 000000000000..4ab2162db13b --- /dev/null +++ b/include/linux/mfd/asic3.h | |||
@@ -0,0 +1,497 @@ | |||
1 | /* | ||
2 | * include/linux/mfd/asic3.h | ||
3 | * | ||
4 | * Compaq ASIC3 headers. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Copyright 2001 Compaq Computer Corporation. | ||
11 | * Copyright 2007 OpendHand. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASIC3_H__ | ||
15 | #define __ASIC3_H__ | ||
16 | |||
17 | #include <linux/types.h> | ||
18 | |||
19 | struct asic3 { | ||
20 | void __iomem *mapping; | ||
21 | unsigned int bus_shift; | ||
22 | unsigned int irq_nr; | ||
23 | unsigned int irq_base; | ||
24 | spinlock_t lock; | ||
25 | u16 irq_bothedge[4]; | ||
26 | struct device *dev; | ||
27 | }; | ||
28 | |||
29 | struct asic3_platform_data { | ||
30 | struct { | ||
31 | u32 dir; | ||
32 | u32 init; | ||
33 | u32 sleep_mask; | ||
34 | u32 sleep_out; | ||
35 | u32 batt_fault_out; | ||
36 | u32 sleep_conf; | ||
37 | u32 alt_function; | ||
38 | } gpio_a, gpio_b, gpio_c, gpio_d; | ||
39 | |||
40 | unsigned int bus_shift; | ||
41 | |||
42 | unsigned int irq_base; | ||
43 | |||
44 | struct platform_device **children; | ||
45 | unsigned int n_children; | ||
46 | }; | ||
47 | |||
48 | int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio); | ||
49 | void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val); | ||
50 | |||
51 | #define ASIC3_NUM_GPIO_BANKS 4 | ||
52 | #define ASIC3_GPIOS_PER_BANK 16 | ||
53 | #define ASIC3_NUM_GPIOS 64 | ||
54 | #define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6 | ||
55 | |||
56 | #define ASIC3_GPIO_BANK_A 0 | ||
57 | #define ASIC3_GPIO_BANK_B 1 | ||
58 | #define ASIC3_GPIO_BANK_C 2 | ||
59 | #define ASIC3_GPIO_BANK_D 3 | ||
60 | |||
61 | #define ASIC3_GPIO(bank, gpio) \ | ||
62 | ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio)) | ||
63 | #define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf)) | ||
64 | /* All offsets below are specified with this address bus shift */ | ||
65 | #define ASIC3_DEFAULT_ADDR_SHIFT 2 | ||
66 | |||
67 | #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg) | ||
68 | #define ASIC3_GPIO_OFFSET(base, reg) \ | ||
69 | (ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg) | ||
70 | |||
71 | #define ASIC3_GPIO_A_Base 0x0000 | ||
72 | #define ASIC3_GPIO_B_Base 0x0100 | ||
73 | #define ASIC3_GPIO_C_Base 0x0200 | ||
74 | #define ASIC3_GPIO_D_Base 0x0300 | ||
75 | |||
76 | #define ASIC3_GPIO_Mask 0x00 /* R/W 0:don't mask */ | ||
77 | #define ASIC3_GPIO_Direction 0x04 /* R/W 0:input */ | ||
78 | #define ASIC3_GPIO_Out 0x08 /* R/W 0:output low */ | ||
79 | #define ASIC3_GPIO_TriggerType 0x0c /* R/W 0:level */ | ||
80 | #define ASIC3_GPIO_EdgeTrigger 0x10 /* R/W 0:falling */ | ||
81 | #define ASIC3_GPIO_LevelTrigger 0x14 /* R/W 0:low level detect */ | ||
82 | #define ASIC3_GPIO_SleepMask 0x18 /* R/W 0:don't mask in sleep mode */ | ||
83 | #define ASIC3_GPIO_SleepOut 0x1c /* R/W level 0:low in sleep mode */ | ||
84 | #define ASIC3_GPIO_BattFaultOut 0x20 /* R/W level 0:low in batt_fault */ | ||
85 | #define ASIC3_GPIO_IntStatus 0x24 /* R/W 0:none, 1:detect */ | ||
86 | #define ASIC3_GPIO_AltFunction 0x28 /* R/W 1:LED register control */ | ||
87 | #define ASIC3_GPIO_SleepConf 0x2c /* | ||
88 | * R/W bit 1: autosleep | ||
89 | * 0: disable gposlpout in normal mode, | ||
90 | * enable gposlpout in sleep mode. | ||
91 | */ | ||
92 | #define ASIC3_GPIO_Status 0x30 /* R Pin status */ | ||
93 | |||
94 | #define ASIC3_SPI_Base 0x0400 | ||
95 | #define ASIC3_SPI_Control 0x0000 | ||
96 | #define ASIC3_SPI_TxData 0x0004 | ||
97 | #define ASIC3_SPI_RxData 0x0008 | ||
98 | #define ASIC3_SPI_Int 0x000c | ||
99 | #define ASIC3_SPI_Status 0x0010 | ||
100 | |||
101 | #define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */ | ||
102 | |||
103 | #define ASIC3_PWM_0_Base 0x0500 | ||
104 | #define ASIC3_PWM_1_Base 0x0600 | ||
105 | #define ASIC3_PWM_TimeBase 0x0000 | ||
106 | #define ASIC3_PWM_PeriodTime 0x0004 | ||
107 | #define ASIC3_PWM_DutyTime 0x0008 | ||
108 | |||
109 | #define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */ | ||
110 | #define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */ | ||
111 | |||
112 | #define ASIC3_LED_0_Base 0x0700 | ||
113 | #define ASIC3_LED_1_Base 0x0800 | ||
114 | #define ASIC3_LED_2_Base 0x0900 | ||
115 | #define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */ | ||
116 | #define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */ | ||
117 | #define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */ | ||
118 | #define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */ | ||
119 | |||
120 | /* LED TimeBase bits - match ASIC2 */ | ||
121 | #define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */ | ||
122 | /* Note: max = 5 on hx4700 */ | ||
123 | /* 0: maximum time base */ | ||
124 | /* 1: maximum time base / 2 */ | ||
125 | /* n: maximum time base / 2^n */ | ||
126 | |||
127 | #define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */ | ||
128 | #define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */ | ||
129 | #define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */ | ||
130 | |||
131 | #define ASIC3_CLOCK_Base 0x0A00 | ||
132 | #define ASIC3_CLOCK_CDEX 0x00 | ||
133 | #define ASIC3_CLOCK_SEL 0x04 | ||
134 | |||
135 | #define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */ | ||
136 | #define CLOCK_CDEX_SOURCE0 (1 << 0) | ||
137 | #define CLOCK_CDEX_SOURCE1 (1 << 1) | ||
138 | #define CLOCK_CDEX_SPI (1 << 2) | ||
139 | #define CLOCK_CDEX_OWM (1 << 3) | ||
140 | #define CLOCK_CDEX_PWM0 (1 << 4) | ||
141 | #define CLOCK_CDEX_PWM1 (1 << 5) | ||
142 | #define CLOCK_CDEX_LED0 (1 << 6) | ||
143 | #define CLOCK_CDEX_LED1 (1 << 7) | ||
144 | #define CLOCK_CDEX_LED2 (1 << 8) | ||
145 | |||
146 | /* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */ | ||
147 | #define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */ | ||
148 | #define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */ | ||
149 | #define CLOCK_CDEX_SMBUS (1 << 11) | ||
150 | #define CLOCK_CDEX_CONTROL_CX (1 << 12) | ||
151 | |||
152 | #define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */ | ||
153 | #define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */ | ||
154 | |||
155 | #define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */ | ||
156 | #define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */ | ||
157 | |||
158 | /* R/W: INT clock source control (32.768 kHz) */ | ||
159 | #define CLOCK_SEL_CX (1 << 2) | ||
160 | |||
161 | |||
162 | #define ASIC3_INTR_Base 0x0B00 | ||
163 | |||
164 | #define ASIC3_INTR_IntMask 0x00 /* Interrupt mask control */ | ||
165 | #define ASIC3_INTR_PIntStat 0x04 /* Peripheral interrupt status */ | ||
166 | #define ASIC3_INTR_IntCPS 0x08 /* Interrupt timer clock pre-scale */ | ||
167 | #define ASIC3_INTR_IntTBS 0x0c /* Interrupt timer set */ | ||
168 | |||
169 | #define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */ | ||
170 | #define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */ | ||
171 | #define ASIC3_INTMASK_MASK0 (1 << 2) | ||
172 | #define ASIC3_INTMASK_MASK1 (1 << 3) | ||
173 | #define ASIC3_INTMASK_MASK2 (1 << 4) | ||
174 | #define ASIC3_INTMASK_MASK3 (1 << 5) | ||
175 | #define ASIC3_INTMASK_MASK4 (1 << 6) | ||
176 | #define ASIC3_INTMASK_MASK5 (1 << 7) | ||
177 | |||
178 | #define ASIC3_INTR_PERIPHERAL_A (1 << 0) | ||
179 | #define ASIC3_INTR_PERIPHERAL_B (1 << 1) | ||
180 | #define ASIC3_INTR_PERIPHERAL_C (1 << 2) | ||
181 | #define ASIC3_INTR_PERIPHERAL_D (1 << 3) | ||
182 | #define ASIC3_INTR_LED0 (1 << 4) | ||
183 | #define ASIC3_INTR_LED1 (1 << 5) | ||
184 | #define ASIC3_INTR_LED2 (1 << 6) | ||
185 | #define ASIC3_INTR_SPI (1 << 7) | ||
186 | #define ASIC3_INTR_SMBUS (1 << 8) | ||
187 | #define ASIC3_INTR_OWM (1 << 9) | ||
188 | |||
189 | #define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */ | ||
190 | #define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */ | ||
191 | |||
192 | |||
193 | /* Basic control of the SD ASIC */ | ||
194 | #define ASIC3_SDHWCTRL_Base 0x0E00 | ||
195 | #define ASIC3_SDHWCTRL_SDConf 0x00 | ||
196 | |||
197 | #define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */ | ||
198 | #define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */ | ||
199 | #define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */ | ||
200 | #define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */ | ||
201 | |||
202 | /* SD card write protection: 0=high */ | ||
203 | #define ASIC3_SDHWCTRL_LEVWP (1 << 4) | ||
204 | #define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */ | ||
205 | |||
206 | /* SD card power supply ctrl 1=enable */ | ||
207 | #define ASIC3_SDHWCTRL_SDPWR (1 << 6) | ||
208 | |||
209 | #define ASIC3_EXTCF_Base 0x1100 | ||
210 | |||
211 | #define ASIC3_EXTCF_Select 0x00 | ||
212 | #define ASIC3_EXTCF_Reset 0x04 | ||
213 | |||
214 | #define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */ | ||
215 | #define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */ | ||
216 | #define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */ | ||
217 | #define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */ | ||
218 | #define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */ | ||
219 | #define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */ | ||
220 | #define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */ | ||
221 | #define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */ | ||
222 | #define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */ | ||
223 | #define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */ | ||
224 | #define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */ | ||
225 | #define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */ | ||
226 | #define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14) | ||
227 | #define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */ | ||
228 | |||
229 | /********************************************* | ||
230 | * The Onewire interface registers | ||
231 | * | ||
232 | * OWM_CMD | ||
233 | * OWM_DAT | ||
234 | * OWM_INTR | ||
235 | * OWM_INTEN | ||
236 | * OWM_CLKDIV | ||
237 | * | ||
238 | *********************************************/ | ||
239 | |||
240 | #define ASIC3_OWM_Base 0xC00 | ||
241 | |||
242 | #define ASIC3_OWM_CMD 0x00 | ||
243 | #define ASIC3_OWM_DAT 0x04 | ||
244 | #define ASIC3_OWM_INTR 0x08 | ||
245 | #define ASIC3_OWM_INTEN 0x0C | ||
246 | #define ASIC3_OWM_CLKDIV 0x10 | ||
247 | |||
248 | #define ASIC3_OWM_CMD_ONEWR (1 << 0) | ||
249 | #define ASIC3_OWM_CMD_SRA (1 << 1) | ||
250 | #define ASIC3_OWM_CMD_DQO (1 << 2) | ||
251 | #define ASIC3_OWM_CMD_DQI (1 << 3) | ||
252 | |||
253 | #define ASIC3_OWM_INTR_PD (1 << 0) | ||
254 | #define ASIC3_OWM_INTR_PDR (1 << 1) | ||
255 | #define ASIC3_OWM_INTR_TBE (1 << 2) | ||
256 | #define ASIC3_OWM_INTR_TEMP (1 << 3) | ||
257 | #define ASIC3_OWM_INTR_RBF (1 << 4) | ||
258 | |||
259 | #define ASIC3_OWM_INTEN_EPD (1 << 0) | ||
260 | #define ASIC3_OWM_INTEN_IAS (1 << 1) | ||
261 | #define ASIC3_OWM_INTEN_ETBE (1 << 2) | ||
262 | #define ASIC3_OWM_INTEN_ETMT (1 << 3) | ||
263 | #define ASIC3_OWM_INTEN_ERBF (1 << 4) | ||
264 | |||
265 | #define ASIC3_OWM_CLKDIV_PRE (3 << 0) /* two bits wide at bit 0 */ | ||
266 | #define ASIC3_OWM_CLKDIV_DIV (7 << 2) /* 3 bits wide at bit 2 */ | ||
267 | |||
268 | |||
269 | /***************************************************************************** | ||
270 | * The SD configuration registers are at a completely different location | ||
271 | * in memory. They are divided into three sets of registers: | ||
272 | * | ||
273 | * SD_CONFIG Core configuration register | ||
274 | * SD_CTRL Control registers for SD operations | ||
275 | * SDIO_CTRL Control registers for SDIO operations | ||
276 | * | ||
277 | *****************************************************************************/ | ||
278 | #define ASIC3_SD_CONFIG_Base 0x0400 /* Assumes 32 bit addressing */ | ||
279 | |||
280 | #define ASIC3_SD_CONFIG_Command 0x08 /* R/W: Command */ | ||
281 | |||
282 | /* [0:8] SD Control Register Base Address */ | ||
283 | #define ASIC3_SD_CONFIG_Addr0 0x20 | ||
284 | |||
285 | /* [9:31] SD Control Register Base Address */ | ||
286 | #define ASIC3_SD_CONFIG_Addr1 0x24 | ||
287 | |||
288 | /* R/O: interrupt assigned to pin */ | ||
289 | #define ASIC3_SD_CONFIG_IntPin 0x78 | ||
290 | |||
291 | /* | ||
292 | * Set to 0x1f to clock SD controller, 0 otherwise. | ||
293 | * At 0x82 - Gated Clock Ctrl | ||
294 | */ | ||
295 | #define ASIC3_SD_CONFIG_ClkStop 0x80 | ||
296 | |||
297 | /* Control clock of SD controller */ | ||
298 | #define ASIC3_SD_CONFIG_ClockMode 0x84 | ||
299 | #define ASIC3_SD_CONFIG_SDHC_PinStatus 0x88 /* R/0: SD pins status */ | ||
300 | #define ASIC3_SD_CONFIG_SDHC_Power1 0x90 /* Power1 - manual pwr ctrl */ | ||
301 | |||
302 | /* auto power up after card inserted */ | ||
303 | #define ASIC3_SD_CONFIG_SDHC_Power2 0x92 | ||
304 | |||
305 | /* auto power down when card removed */ | ||
306 | #define ASIC3_SD_CONFIG_SDHC_Power3 0x94 | ||
307 | #define ASIC3_SD_CONFIG_SDHC_CardDetect 0x98 | ||
308 | #define ASIC3_SD_CONFIG_SDHC_Slot 0xA0 /* R/O: support slot number */ | ||
309 | #define ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0x1E0 /* Not used */ | ||
310 | #define ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0x1E2 /* Not used*/ | ||
311 | |||
312 | /* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */ | ||
313 | #define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable 0x1E8 | ||
314 | #define ASIC3_SD_CONFIG_SDHC_GPIO_Status 0x1EC /* GPIO Status Reg. */ | ||
315 | |||
316 | /* Bit 1: double buffer/single buffer */ | ||
317 | #define ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0x1F0 | ||
318 | |||
319 | /* Memory access enable (set to 1 to access SD Controller) */ | ||
320 | #define SD_CONFIG_COMMAND_MAE (1<<1) | ||
321 | |||
322 | #define SD_CONFIG_CLK_ENABLE_ALL 0x1f | ||
323 | |||
324 | #define SD_CONFIG_POWER1_PC_33V 0x0200 /* Set for 3.3 volts */ | ||
325 | #define SD_CONFIG_POWER1_PC_OFF 0x0000 /* Turn off power */ | ||
326 | |||
327 | /* two bits - number of cycles for card detection */ | ||
328 | #define SD_CONFIG_CARDDETECTMODE_CLK ((x) & 0x3) | ||
329 | |||
330 | |||
331 | #define ASIC3_SD_CTRL_Base 0x1000 | ||
332 | |||
333 | #define ASIC3_SD_CTRL_Cmd 0x00 | ||
334 | #define ASIC3_SD_CTRL_Arg0 0x08 | ||
335 | #define ASIC3_SD_CTRL_Arg1 0x0C | ||
336 | #define ASIC3_SD_CTRL_StopInternal 0x10 | ||
337 | #define ASIC3_SD_CTRL_TransferSectorCount 0x14 | ||
338 | #define ASIC3_SD_CTRL_Response0 0x18 | ||
339 | #define ASIC3_SD_CTRL_Response1 0x1C | ||
340 | #define ASIC3_SD_CTRL_Response2 0x20 | ||
341 | #define ASIC3_SD_CTRL_Response3 0x24 | ||
342 | #define ASIC3_SD_CTRL_Response4 0x28 | ||
343 | #define ASIC3_SD_CTRL_Response5 0x2C | ||
344 | #define ASIC3_SD_CTRL_Response6 0x30 | ||
345 | #define ASIC3_SD_CTRL_Response7 0x34 | ||
346 | #define ASIC3_SD_CTRL_CardStatus 0x38 | ||
347 | #define ASIC3_SD_CTRL_BufferCtrl 0x3C | ||
348 | #define ASIC3_SD_CTRL_IntMaskCard 0x40 | ||
349 | #define ASIC3_SD_CTRL_IntMaskBuffer 0x44 | ||
350 | #define ASIC3_SD_CTRL_CardClockCtrl 0x48 | ||
351 | #define ASIC3_SD_CTRL_MemCardXferDataLen 0x4C | ||
352 | #define ASIC3_SD_CTRL_MemCardOptionSetup 0x50 | ||
353 | #define ASIC3_SD_CTRL_ErrorStatus0 0x58 | ||
354 | #define ASIC3_SD_CTRL_ErrorStatus1 0x5C | ||
355 | #define ASIC3_SD_CTRL_DataPort 0x60 | ||
356 | #define ASIC3_SD_CTRL_TransactionCtrl 0x68 | ||
357 | #define ASIC3_SD_CTRL_SoftwareReset 0x1C0 | ||
358 | |||
359 | #define SD_CTRL_SOFTWARE_RESET_CLEAR (1<<0) | ||
360 | |||
361 | #define SD_CTRL_TRANSACTIONCONTROL_SET (1<<8) | ||
362 | |||
363 | #define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD (1<<15) | ||
364 | #define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK (1<<8) | ||
365 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512 (1<<7) | ||
366 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256 (1<<6) | ||
367 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128 (1<<5) | ||
368 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64 (1<<4) | ||
369 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32 (1<<3) | ||
370 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16 (1<<2) | ||
371 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8 (1<<1) | ||
372 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4 (1<<0) | ||
373 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2 (0<<0) | ||
374 | |||
375 | #define MEM_CARD_OPTION_REQUIRED 0x000e | ||
376 | #define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x) (((x) & 0x0f) << 4) | ||
377 | #define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT (1<<14) | ||
378 | #define MEM_CARD_OPTION_DATA_XFR_WIDTH_1 (1<<15) | ||
379 | #define MEM_CARD_OPTION_DATA_XFR_WIDTH_4 0 | ||
380 | |||
381 | #define SD_CTRL_COMMAND_INDEX(x) ((x) & 0x3f) | ||
382 | #define SD_CTRL_COMMAND_TYPE_CMD (0 << 6) | ||
383 | #define SD_CTRL_COMMAND_TYPE_ACMD (1 << 6) | ||
384 | #define SD_CTRL_COMMAND_TYPE_AUTHENTICATION (2 << 6) | ||
385 | #define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL (0 << 8) | ||
386 | #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1 (4 << 8) | ||
387 | #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B (5 << 8) | ||
388 | #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2 (6 << 8) | ||
389 | #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3 (7 << 8) | ||
390 | #define SD_CTRL_COMMAND_DATA_PRESENT (1 << 11) | ||
391 | #define SD_CTRL_COMMAND_TRANSFER_READ (1 << 12) | ||
392 | #define SD_CTRL_COMMAND_TRANSFER_WRITE (0 << 12) | ||
393 | #define SD_CTRL_COMMAND_MULTI_BLOCK (1 << 13) | ||
394 | #define SD_CTRL_COMMAND_SECURITY_CMD (1 << 14) | ||
395 | |||
396 | #define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12 (1 << 0) | ||
397 | #define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12 (1 << 8) | ||
398 | |||
399 | #define SD_CTRL_CARDSTATUS_RESPONSE_END (1 << 0) | ||
400 | #define SD_CTRL_CARDSTATUS_RW_END (1 << 2) | ||
401 | #define SD_CTRL_CARDSTATUS_CARD_REMOVED_0 (1 << 3) | ||
402 | #define SD_CTRL_CARDSTATUS_CARD_INSERTED_0 (1 << 4) | ||
403 | #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0 (1 << 5) | ||
404 | #define SD_CTRL_CARDSTATUS_WRITE_PROTECT (1 << 7) | ||
405 | #define SD_CTRL_CARDSTATUS_CARD_REMOVED_3 (1 << 8) | ||
406 | #define SD_CTRL_CARDSTATUS_CARD_INSERTED_3 (1 << 9) | ||
407 | #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3 (1 << 10) | ||
408 | |||
409 | #define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR (1 << 0) | ||
410 | #define SD_CTRL_BUFFERSTATUS_CRC_ERROR (1 << 1) | ||
411 | #define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR (1 << 2) | ||
412 | #define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT (1 << 3) | ||
413 | #define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW (1 << 4) | ||
414 | #define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW (1 << 5) | ||
415 | #define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT (1 << 6) | ||
416 | #define SD_CTRL_BUFFERSTATUS_UNK7 (1 << 7) | ||
417 | #define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE (1 << 8) | ||
418 | #define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE (1 << 9) | ||
419 | #define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION (1 << 13) | ||
420 | #define SD_CTRL_BUFFERSTATUS_CMD_BUSY (1 << 14) | ||
421 | #define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS (1 << 15) | ||
422 | |||
423 | #define SD_CTRL_INTMASKCARD_RESPONSE_END (1 << 0) | ||
424 | #define SD_CTRL_INTMASKCARD_RW_END (1 << 2) | ||
425 | #define SD_CTRL_INTMASKCARD_CARD_REMOVED_0 (1 << 3) | ||
426 | #define SD_CTRL_INTMASKCARD_CARD_INSERTED_0 (1 << 4) | ||
427 | #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5) | ||
428 | #define SD_CTRL_INTMASKCARD_UNK6 (1 << 6) | ||
429 | #define SD_CTRL_INTMASKCARD_WRITE_PROTECT (1 << 7) | ||
430 | #define SD_CTRL_INTMASKCARD_CARD_REMOVED_3 (1 << 8) | ||
431 | #define SD_CTRL_INTMASKCARD_CARD_INSERTED_3 (1 << 9) | ||
432 | #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10) | ||
433 | |||
434 | #define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR (1 << 0) | ||
435 | #define SD_CTRL_INTMASKBUFFER_CRC_ERROR (1 << 1) | ||
436 | #define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR (1 << 2) | ||
437 | #define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT (1 << 3) | ||
438 | #define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW (1 << 4) | ||
439 | #define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW (1 << 5) | ||
440 | #define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT (1 << 6) | ||
441 | #define SD_CTRL_INTMASKBUFFER_UNK7 (1 << 7) | ||
442 | #define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE (1 << 8) | ||
443 | #define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE (1 << 9) | ||
444 | #define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION (1 << 13) | ||
445 | #define SD_CTRL_INTMASKBUFFER_CMD_BUSY (1 << 14) | ||
446 | #define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS (1 << 15) | ||
447 | |||
448 | #define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR (1 << 0) | ||
449 | #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2) | ||
450 | #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12 (1 << 3) | ||
451 | #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA (1 << 4) | ||
452 | #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS (1 << 5) | ||
453 | #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 8) | ||
454 | #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12 (1 << 9) | ||
455 | #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA (1 << 10) | ||
456 | #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD (1 << 11) | ||
457 | |||
458 | #define SD_CTRL_DETAIL1_NO_CMD_RESPONSE (1 << 0) | ||
459 | #define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA (1 << 4) | ||
460 | #define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS (1 << 5) | ||
461 | #define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY (1 << 6) | ||
462 | |||
463 | #define ASIC3_SDIO_CTRL_Base 0x1200 | ||
464 | |||
465 | #define ASIC3_SDIO_CTRL_Cmd 0x00 | ||
466 | #define ASIC3_SDIO_CTRL_CardPortSel 0x04 | ||
467 | #define ASIC3_SDIO_CTRL_Arg0 0x08 | ||
468 | #define ASIC3_SDIO_CTRL_Arg1 0x0C | ||
469 | #define ASIC3_SDIO_CTRL_TransferBlockCount 0x14 | ||
470 | #define ASIC3_SDIO_CTRL_Response0 0x18 | ||
471 | #define ASIC3_SDIO_CTRL_Response1 0x1C | ||
472 | #define ASIC3_SDIO_CTRL_Response2 0x20 | ||
473 | #define ASIC3_SDIO_CTRL_Response3 0x24 | ||
474 | #define ASIC3_SDIO_CTRL_Response4 0x28 | ||
475 | #define ASIC3_SDIO_CTRL_Response5 0x2C | ||
476 | #define ASIC3_SDIO_CTRL_Response6 0x30 | ||
477 | #define ASIC3_SDIO_CTRL_Response7 0x34 | ||
478 | #define ASIC3_SDIO_CTRL_CardStatus 0x38 | ||
479 | #define ASIC3_SDIO_CTRL_BufferCtrl 0x3C | ||
480 | #define ASIC3_SDIO_CTRL_IntMaskCard 0x40 | ||
481 | #define ASIC3_SDIO_CTRL_IntMaskBuffer 0x44 | ||
482 | #define ASIC3_SDIO_CTRL_CardXferDataLen 0x4C | ||
483 | #define ASIC3_SDIO_CTRL_CardOptionSetup 0x50 | ||
484 | #define ASIC3_SDIO_CTRL_ErrorStatus0 0x54 | ||
485 | #define ASIC3_SDIO_CTRL_ErrorStatus1 0x58 | ||
486 | #define ASIC3_SDIO_CTRL_DataPort 0x60 | ||
487 | #define ASIC3_SDIO_CTRL_TransactionCtrl 0x68 | ||
488 | #define ASIC3_SDIO_CTRL_CardIntCtrl 0x6C | ||
489 | #define ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x70 | ||
490 | #define ASIC3_SDIO_CTRL_HostInformation 0x74 | ||
491 | #define ASIC3_SDIO_CTRL_ErrorCtrl 0x78 | ||
492 | #define ASIC3_SDIO_CTRL_LEDCtrl 0x7C | ||
493 | #define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0 | ||
494 | |||
495 | #define ASIC3_MAP_SIZE 0x2000 | ||
496 | |||
497 | #endif /* __ASIC3_H__ */ | ||