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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/common/dmabounce.c2
-rw-r--r--arch/arm/common/gic.c22
-rw-r--r--arch/arm/common/sharpsl_param.c2
-rw-r--r--arch/arm/common/sharpsl_pm.c22
-rw-r--r--arch/arm/kernel/asm-offsets.c2
-rw-r--r--arch/arm/kernel/calls.S4
-rw-r--r--arch/arm/kernel/setup.c2
-rw-r--r--arch/arm/kernel/sys_arm.c2
-rw-r--r--arch/arm/lib/bitops.h2
-rw-r--r--arch/arm/mach-at91/board-carmeva.c8
-rw-r--r--arch/arm/mach-h720x/cpu-h7202.c4
-rw-r--r--arch/arm/mach-imx/cpufreq.c2
-rw-r--r--arch/arm/mach-imx/dma.c8
-rw-r--r--arch/arm/mach-integrator/Makefile1
-rw-r--r--arch/arm/mach-integrator/core.c18
-rw-r--r--arch/arm/mach-integrator/headsmp.S37
-rw-r--r--arch/arm/mach-integrator/pci_v3.c1
-rw-r--r--arch/arm/mach-integrator/platsmp.c204
-rw-r--r--arch/arm/mach-iop13xx/irq.c54
-rw-r--r--arch/arm/mach-iop13xx/msi.c18
-rw-r--r--arch/arm/mach-iop13xx/pci.c10
-rw-r--r--arch/arm/mach-iop32x/glantank.c2
-rw-r--r--arch/arm/mach-iop32x/iq31244.c4
-rw-r--r--arch/arm/mach-iop32x/iq80321.c2
-rw-r--r--arch/arm/mach-iop32x/irq.c4
-rw-r--r--arch/arm/mach-iop32x/n2100.c2
-rw-r--r--arch/arm/mach-iop33x/iq80331.c2
-rw-r--r--arch/arm/mach-iop33x/iq80332.c2
-rw-r--r--arch/arm/mach-iop33x/irq.c12
-rw-r--r--arch/arm/mach-ixp2000/enp2611.c2
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x00.c4
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c6
-rw-r--r--arch/arm/mach-ixp2000/pci.c2
-rw-r--r--arch/arm/mach-ixp23xx/core.c2
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-setup.c2
-rw-r--r--arch/arm/mach-lh7a40x/lcd-panel.h6
-rw-r--r--arch/arm/mach-ns9xxx/time.c2
-rw-r--r--arch/arm/mach-omap1/Kconfig2
-rw-r--r--arch/arm/mach-omap1/board-osk.c2
-rw-r--r--arch/arm/mach-omap1/board-palmte.c2
-rw-r--r--arch/arm/mach-omap1/pm.c2
-rw-r--r--arch/arm/mach-omap2/clock.c2
-rw-r--r--arch/arm/mach-omap2/clock.h4
-rw-r--r--arch/arm/mach-pxa/corgi_lcd.c10
-rw-r--r--arch/arm/mach-pxa/corgi_ssp.c2
-rw-r--r--arch/arm/mach-realview/localtimer.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c1
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c1
-rw-r--r--arch/arm/mach-s3c2412/dma.c4
-rw-r--r--arch/arm/mach-s3c2412/s3c2412.c9
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c1
-rw-r--r--arch/arm/mach-s3c2443/clock.c22
-rw-r--r--arch/arm/mach-s3c2443/mach-smdk2443.c1
-rw-r--r--arch/arm/mach-s3c2443/s3c2443.c4
-rw-r--r--arch/arm/mach-sa1100/time.c2
-rw-r--r--arch/arm/mm/Kconfig8
-rw-r--r--arch/arm/mm/alignment.c2
-rw-r--r--arch/arm/mm/ioremap.c2
-rw-r--r--arch/arm/mm/mmu.c2
-rw-r--r--arch/arm/plat-iop/pci.c6
-rw-r--r--arch/arm/plat-omap/common.c2
-rw-r--r--arch/arm/plat-omap/dma.c2
-rw-r--r--arch/arm/plat-omap/sram.c6
-rw-r--r--arch/arm/plat-omap/usb.c2
-rw-r--r--arch/arm/plat-s3c24xx/common-smdk.c5
-rw-r--r--arch/arm/plat-s3c24xx/devs.c35
-rw-r--r--arch/arm/plat-s3c24xx/dma.c2
-rw-r--r--arch/arm/plat-s3c24xx/pm-simtec.c1
-rw-r--r--arch/arm/plat-s3c24xx/pm.c2
-rw-r--r--drivers/serial/serial_ks8695.c4
-rw-r--r--include/asm-arm/arch-at91/at91_adc.h2
-rw-r--r--include/asm-arm/arch-integrator/smp.h18
-rw-r--r--include/asm-arm/arch-s3c2410/irqs.h2
-rw-r--r--include/asm-arm/arch-s3c2410/regs-spi.h2
-rw-r--r--include/asm-arm/io.h2
-rw-r--r--include/asm-arm/mmu.h4
-rw-r--r--include/asm-arm/mmu_context.h2
-rw-r--r--include/asm-arm/plat-s3c24xx/devs.h1
-rw-r--r--include/asm-arm/unistd.h10
81 files changed, 237 insertions, 444 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e55bbd32dcac..50d9f3e4e0f1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -287,6 +287,7 @@ config ARCH_IXP2000
287config ARCH_IXP4XX 287config ARCH_IXP4XX
288 bool "IXP4xx-based" 288 bool "IXP4xx-based"
289 depends on MMU 289 depends on MMU
290 select GENERIC_GPIO
290 select GENERIC_TIME 291 select GENERIC_TIME
291 select GENERIC_CLOCKEVENTS 292 select GENERIC_CLOCKEVENTS
292 help 293 help
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 6fbe7722aa44..b36b1e8a105d 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -6,7 +6,7 @@
6 * copy data to/from buffers located outside the DMA region. This 6 * copy data to/from buffers located outside the DMA region. This
7 * only works for systems in which DMA memory is at the bottom of 7 * only works for systems in which DMA memory is at the bottom of
8 * RAM, the remainder of memory is at the top and the DMA memory 8 * RAM, the remainder of memory is at the top and the DMA memory
9 * can be marked as ZONE_DMA. Anything beyond that such as discontigous 9 * can be marked as ZONE_DMA. Anything beyond that such as discontiguous
10 * DMA windows will require custom implementations that reserve memory 10 * DMA windows will require custom implementations that reserve memory
11 * areas at early bootup. 11 * areas at early bootup.
12 * 12 *
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 4deece5fbdf4..0c89bd35e06f 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -72,7 +72,7 @@ static inline unsigned int gic_irq(unsigned int irq)
72 * unmask it, in the same way we need to unmask an interrupt when 72 * unmask it, in the same way we need to unmask an interrupt when
73 * we first enable it. 73 * we first enable it.
74 * 74 *
75 * The GIC has a seperate notion of "end of interrupt" to re-enable 75 * The GIC has a separate notion of "end of interrupt" to re-enable
76 * an interrupt after handling, in order to support hardware 76 * an interrupt after handling, in order to support hardware
77 * prioritisation. 77 * prioritisation.
78 * 78 *
@@ -125,12 +125,11 @@ static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
125} 125}
126#endif 126#endif
127 127
128static void fastcall gic_handle_cascade_irq(unsigned int irq, 128static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
129 struct irq_desc *desc)
130{ 129{
131 struct gic_chip_data *chip_data = get_irq_data(irq); 130 struct gic_chip_data *chip_data = get_irq_data(irq);
132 struct irq_chip *chip = get_irq_chip(irq); 131 struct irq_chip *chip = get_irq_chip(irq);
133 unsigned int cascade_irq; 132 unsigned int cascade_irq, gic_irq;
134 unsigned long status; 133 unsigned long status;
135 134
136 /* primary controller ack'ing */ 135 /* primary controller ack'ing */
@@ -140,16 +139,15 @@ static void fastcall gic_handle_cascade_irq(unsigned int irq,
140 status = readl(chip_data->cpu_base + GIC_CPU_INTACK); 139 status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
141 spin_unlock(&irq_controller_lock); 140 spin_unlock(&irq_controller_lock);
142 141
143 cascade_irq = (status & 0x3ff); 142 gic_irq = (status & 0x3ff);
144 if (cascade_irq > 1020) 143 if (gic_irq == 1023)
145 goto out; 144 goto out;
146 if (cascade_irq < 32 || cascade_irq >= NR_IRQS) {
147 do_bad_IRQ(cascade_irq, desc);
148 goto out;
149 }
150 145
151 cascade_irq += chip_data->irq_offset; 146 cascade_irq = gic_irq + chip_data->irq_offset;
152 generic_handle_irq(cascade_irq); 147 if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
148 do_bad_IRQ(cascade_irq, desc);
149 else
150 generic_handle_irq(cascade_irq);
153 151
154 out: 152 out:
155 /* primary controller unmasking */ 153 /* primary controller unmasking */
diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c
index c94864c5b1af..aad4d94ba8f5 100644
--- a/arch/arm/common/sharpsl_param.c
+++ b/arch/arm/common/sharpsl_param.c
@@ -20,7 +20,7 @@
20 * typically including LCD parameters are loaded by the bootloader at the 20 * typically including LCD parameters are loaded by the bootloader at the
21 * address PARAM_BASE. As the kernel will overwrite them, we need to store 21 * address PARAM_BASE. As the kernel will overwrite them, we need to store
22 * them early in the boot process, then pass them to the appropriate drivers. 22 * them early in the boot process, then pass them to the appropriate drivers.
23 * Not all devices use all paramaters but the format is common to all. 23 * Not all devices use all parameters but the format is common to all.
24 */ 24 */
25#ifdef CONFIG_ARCH_SA1100 25#ifdef CONFIG_ARCH_SA1100
26#define PARAM_BASE 0xe8ffc000 26#define PARAM_BASE 0xe8ffc000
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c
index 5972df2b9af4..3bf3a927ae22 100644
--- a/arch/arm/common/sharpsl_pm.c
+++ b/arch/arm/common/sharpsl_pm.c
@@ -153,7 +153,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
153 sharpsl_pm.battstat.mainbat_percent = percent; 153 sharpsl_pm.battstat.mainbat_percent = percent;
154 } 154 }
155 155
156 dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %d\n", voltage, 156 dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
157 sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies); 157 sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
158 158
159 /* If battery is low. limit backlight intensity to save power. */ 159 /* If battery is low. limit backlight intensity to save power. */
@@ -291,7 +291,7 @@ static void sharpsl_chrg_full_timer(unsigned long data)
291} 291}
292 292
293/* Charging Finished Interrupt (Not present on Corgi) */ 293/* Charging Finished Interrupt (Not present on Corgi) */
294/* Can trigger at the same time as an AC staus change so 294/* Can trigger at the same time as an AC status change so
295 delay until after that has been processed */ 295 delay until after that has been processed */
296irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id) 296irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id)
297{ 297{
@@ -625,7 +625,7 @@ static int sharpsl_fatal_check(void)
625 } 625 }
626 626
627 temp = get_select_val(buff); 627 temp = get_select_val(buff);
628 dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %d\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT)); 628 dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %ld\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT));
629 629
630 if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) || 630 if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) ||
631 (!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt))) 631 (!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt)))
@@ -635,7 +635,7 @@ static int sharpsl_fatal_check(void)
635 635
636static int sharpsl_off_charge_error(void) 636static int sharpsl_off_charge_error(void)
637{ 637{
638 dev_err(sharpsl_pm.dev, "Offline Charger: Error occured.\n"); 638 dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n");
639 sharpsl_pm.machinfo->charge(0); 639 sharpsl_pm.machinfo->charge(0);
640 sharpsl_pm_led(SHARPSL_LED_ERROR); 640 sharpsl_pm_led(SHARPSL_LED_ERROR);
641 sharpsl_pm.charge_mode = CHRG_ERROR; 641 sharpsl_pm.charge_mode = CHRG_ERROR;
@@ -691,14 +691,14 @@ static int sharpsl_off_charge_battery(void)
691 691
692 time = RCNR; 692 time = RCNR;
693 while(1) { 693 while(1) {
694 /* Check if any wakeup event had occured */ 694 /* Check if any wakeup event had occurred */
695 if (sharpsl_pm.machinfo->charger_wakeup() != 0) 695 if (sharpsl_pm.machinfo->charger_wakeup() != 0)
696 return 0; 696 return 0;
697 /* Check for timeout */ 697 /* Check for timeout */
698 if ((RCNR - time) > SHARPSL_WAIT_CO_TIME) 698 if ((RCNR - time) > SHARPSL_WAIT_CO_TIME)
699 return 1; 699 return 1;
700 if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) { 700 if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
701 dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occured. Retrying to check\n"); 701 dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occurred. Retrying to check\n");
702 sharpsl_pm.full_count++; 702 sharpsl_pm.full_count++;
703 sharpsl_pm.machinfo->charge(0); 703 sharpsl_pm.machinfo->charge(0);
704 mdelay(SHARPSL_CHARGE_WAIT_TIME); 704 mdelay(SHARPSL_CHARGE_WAIT_TIME);
@@ -714,7 +714,7 @@ static int sharpsl_off_charge_battery(void)
714 714
715 time = RCNR; 715 time = RCNR;
716 while(1) { 716 while(1) {
717 /* Check if any wakeup event had occured */ 717 /* Check if any wakeup event had occurred */
718 if (sharpsl_pm.machinfo->charger_wakeup() != 0) 718 if (sharpsl_pm.machinfo->charger_wakeup() != 0)
719 return 0; 719 return 0;
720 /* Check for timeout */ 720 /* Check for timeout */
@@ -774,6 +774,8 @@ static struct pm_ops sharpsl_pm_ops = {
774 774
775static int __init sharpsl_pm_probe(struct platform_device *pdev) 775static int __init sharpsl_pm_probe(struct platform_device *pdev)
776{ 776{
777 int ret;
778
777 if (!pdev->dev.platform_data) 779 if (!pdev->dev.platform_data)
778 return -EINVAL; 780 return -EINVAL;
779 781
@@ -792,8 +794,10 @@ static int __init sharpsl_pm_probe(struct platform_device *pdev)
792 794
793 sharpsl_pm.machinfo->init(); 795 sharpsl_pm.machinfo->init();
794 796
795 device_create_file(&pdev->dev, &dev_attr_battery_percentage); 797 ret = device_create_file(&pdev->dev, &dev_attr_battery_percentage);
796 device_create_file(&pdev->dev, &dev_attr_battery_voltage); 798 ret |= device_create_file(&pdev->dev, &dev_attr_battery_voltage);
799 if (ret != 0)
800 dev_warn(&pdev->dev, "Failed to register attributes (%d)\n", ret);
797 801
798 apm_get_power_status = sharpsl_apm_get_power_status; 802 apm_get_power_status = sharpsl_apm_get_power_status;
799 803
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 3c078e346753..3278e713c32a 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -85,7 +85,7 @@ int main(void)
85 DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0)); 85 DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0));
86 DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); 86 DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
87 BLANK(); 87 BLANK();
88#if __LINUX_ARM_ARCH__ >= 6 88#ifdef CONFIG_CPU_HAS_ASID
89 DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); 89 DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id));
90 BLANK(); 90 BLANK();
91#endif 91#endif
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index ae89cdd82b16..19326d7cdeb3 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -357,6 +357,10 @@
357/* 345 */ CALL(sys_getcpu) 357/* 345 */ CALL(sys_getcpu)
358 CALL(sys_ni_syscall) /* eventually epoll_pwait */ 358 CALL(sys_ni_syscall) /* eventually epoll_pwait */
359 CALL(sys_kexec_load) 359 CALL(sys_kexec_load)
360 CALL(sys_utimensat)
361 CALL(sys_signalfd)
362/* 350 */ CALL(sys_timerfd)
363 CALL(sys_eventfd)
360#ifndef syscalls_counted 364#ifndef syscalls_counted
361.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 365.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
362#define syscalls_counted 366#define syscalls_counted
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 0453dcc757b4..650eac1bc0a6 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -918,7 +918,7 @@ static int c_show(struct seq_file *m, void *v)
918 918
919 if ((processor_id & 0x0008f000) == 0x00000000) { 919 if ((processor_id & 0x0008f000) == 0x00000000) {
920 /* pre-ARM7 */ 920 /* pre-ARM7 */
921 seq_printf(m, "CPU part\t\t: %07x\n", processor_id >> 4); 921 seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4);
922 } else { 922 } else {
923 if ((processor_id & 0x0008f000) == 0x00007000) { 923 if ((processor_id & 0x0008f000) == 0x00007000) {
924 /* ARM7 */ 924 /* ARM7 */
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index 3d4fcbc16276..1ca2d5174fcb 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -320,7 +320,7 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[])
320EXPORT_SYMBOL(kernel_execve); 320EXPORT_SYMBOL(kernel_execve);
321 321
322/* 322/*
323 * Since loff_t is a 64 bit type we avoid a lot of ABI hastle 323 * Since loff_t is a 64 bit type we avoid a lot of ABI hassle
324 * with a different argument ordering. 324 * with a different argument ordering.
325 */ 325 */
326asmlinkage long sys_arm_fadvise64_64(int fd, int advice, 326asmlinkage long sys_arm_fadvise64_64(int fd, int advice,
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index 542251021744..2e787d40d599 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -47,7 +47,7 @@
47 * @store: store instruction 47 * @store: store instruction
48 * 48 *
49 * Note: we can trivially conditionalise the store instruction 49 * Note: we can trivially conditionalise the store instruction
50 * to avoid dirting the data cache. 50 * to avoid dirtying the data cache.
51 */ 51 */
52 .macro testop, instr, store 52 .macro testop, instr, store
53 add r1, r1, r0, lsr #3 53 add r1, r1, r0, lsr #3
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index b4518619063a..76ec856cd4f9 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -79,7 +79,7 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
79 .pullup_pin = AT91_PIN_PD9, 79 .pullup_pin = AT91_PIN_PD9,
80}; 80};
81 81
82/* FIXME: user dependend */ 82/* FIXME: user dependant */
83// static struct at91_cf_data __initdata carmeva_cf_data = { 83// static struct at91_cf_data __initdata carmeva_cf_data = {
84// .det_pin = AT91_PIN_PB0, 84// .det_pin = AT91_PIN_PB0,
85// .rst_pin = AT91_PIN_PC5, 85// .rst_pin = AT91_PIN_PC5,
@@ -100,17 +100,17 @@ static struct spi_board_info carmeva_spi_devices[] = {
100 .chip_select = 0, 100 .chip_select = 0,
101 .max_speed_hz = 10 * 1000 * 1000, 101 .max_speed_hz = 10 * 1000 * 1000,
102 }, 102 },
103 { /* User accessable spi - cs1 (250KHz) */ 103 { /* User accessible spi - cs1 (250KHz) */
104 .modalias = "spi-cs1", 104 .modalias = "spi-cs1",
105 .chip_select = 1, 105 .chip_select = 1,
106 .max_speed_hz = 250 * 1000, 106 .max_speed_hz = 250 * 1000,
107 }, 107 },
108 { /* User accessable spi - cs2 (1MHz) */ 108 { /* User accessible spi - cs2 (1MHz) */
109 .modalias = "spi-cs2", 109 .modalias = "spi-cs2",
110 .chip_select = 2, 110 .chip_select = 2,
111 .max_speed_hz = 1 * 1000 * 1000, 111 .max_speed_hz = 1 * 1000 * 1000,
112 }, 112 },
113 { /* User accessable spi - cs3 (10MHz) */ 113 { /* User accessible spi - cs3 (10MHz) */
114 .modalias = "spi-cs3", 114 .modalias = "spi-cs3",
115 .chip_select = 3, 115 .chip_select = 3,
116 .max_speed_hz = 10 * 1000 * 1000, 116 .max_speed_hz = 10 * 1000 * 1000,
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index 82e420d6fd19..0a1a25fb8ba8 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -143,7 +143,7 @@ h7202_timer_interrupt(int irq, void *dev_id)
143} 143}
144 144
145/* 145/*
146 * mask multiplexed timer irq's 146 * mask multiplexed timer IRQs
147 */ 147 */
148static void inline mask_timerx_irq (u32 irq) 148static void inline mask_timerx_irq (u32 irq)
149{ 149{
@@ -153,7 +153,7 @@ static void inline mask_timerx_irq (u32 irq)
153} 153}
154 154
155/* 155/*
156 * unmask multiplexed timer irq's 156 * unmask multiplexed timer IRQs
157 */ 157 */
158static void inline unmask_timerx_irq (u32 irq) 158static void inline unmask_timerx_irq (u32 irq)
159{ 159{
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
index 7e70e0b0b989..467d899fbe75 100644
--- a/arch/arm/mach-imx/cpufreq.c
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -245,7 +245,7 @@ static int imx_set_target(struct cpufreq_policy *policy,
245 if(mpctl0) { 245 if(mpctl0) {
246 CSCR |= CSCR_MPLL_RESTART; 246 CSCR |= CSCR_MPLL_RESTART;
247 247
248 /* Wait until MPLL is stablized */ 248 /* Wait until MPLL is stabilized */
249 while( CSCR & CSCR_MPLL_RESTART ); 249 while( CSCR & CSCR_MPLL_RESTART );
250 250
251 imx_set_async_mode(); 251 imx_set_async_mode();
diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c
index 6d50d85a618c..bc6fb02d213b 100644
--- a/arch/arm/mach-imx/dma.c
+++ b/arch/arm/mach-imx/dma.c
@@ -131,7 +131,7 @@ imx_dma_setup_sg_base(imx_dmach_t dma_ch,
131 * The function setups DMA channel source and destination addresses for transfer 131 * The function setups DMA channel source and destination addresses for transfer
132 * specified by provided parameters. The scatter-gather emulation is disabled, 132 * specified by provided parameters. The scatter-gather emulation is disabled,
133 * because linear data block 133 * because linear data block
134 * form the physical address range is transfered. 134 * form the physical address range is transferred.
135 * Return value: if incorrect parameters are provided -%EINVAL. 135 * Return value: if incorrect parameters are provided -%EINVAL.
136 * Zero indicates success. 136 * Zero indicates success.
137 */ 137 */
@@ -192,7 +192,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
192 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory 192 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
193 * or %DMA_MODE_WRITE from memory to the device 193 * or %DMA_MODE_WRITE from memory to the device
194 * 194 *
195 * The function setups DMA channel state and registers to be ready for transfer 195 * The function sets up DMA channel state and registers to be ready for transfer
196 * specified by provided parameters. The scatter-gather emulation is set up 196 * specified by provided parameters. The scatter-gather emulation is set up
197 * according to the parameters. 197 * according to the parameters.
198 * 198 *
@@ -212,7 +212,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
212 * 212 *
213 * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x 213 * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
214 * 214 *
215 * Be carefull there and do not mistakenly mix source and target device 215 * Be careful here and do not mistakenly mix source and target device
216 * port sizes constants, they are really different: 216 * port sizes constants, they are really different:
217 * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, 217 * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
218 * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 218 * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
@@ -495,7 +495,7 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id)
495 /* 495 /*
496 * The cleaning of @sg field would be questionable 496 * The cleaning of @sg field would be questionable
497 * there, because its value can help to compute 497 * there, because its value can help to compute
498 * remaining/transfered bytes count in the handler 498 * remaining/transferred bytes count in the handler
499 */ 499 */
500 /*imx_dma_channels[i].sg = NULL;*/ 500 /*imx_dma_channels[i].sg = NULL;*/
501 501
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index ebb255bdce8a..158daaf9e3b0 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -12,4 +12,3 @@ obj-$(CONFIG_LEDS) += leds.o
12obj-$(CONFIG_PCI) += pci_v3.o pci.o 12obj-$(CONFIG_PCI) += pci_v3.o pci.o
13obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o 13obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o
14obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o 14obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
15obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 897c21c2fb5b..e9c82deb791d 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -257,23 +257,7 @@ integrator_timer_interrupt(int irq, void *dev_id)
257 */ 257 */
258 writel(1, TIMER1_VA_BASE + TIMER_INTCLR); 258 writel(1, TIMER1_VA_BASE + TIMER_INTCLR);
259 259
260 /* 260 timer_tick();
261 * the clock tick routines are only processed on the
262 * primary CPU
263 */
264 if (hard_smp_processor_id() == 0) {
265 timer_tick();
266#ifdef CONFIG_SMP
267 smp_send_timer();
268#endif
269 }
270
271#ifdef CONFIG_SMP
272 /*
273 * this is the ARM equivalent of the APIC timer interrupt
274 */
275 update_process_times(user_mode(get_irq_regs()));
276#endif /* CONFIG_SMP */
277 261
278 write_sequnlock(&xtime_lock); 262 write_sequnlock(&xtime_lock);
279 263
diff --git a/arch/arm/mach-integrator/headsmp.S b/arch/arm/mach-integrator/headsmp.S
deleted file mode 100644
index ceaa88e30d70..000000000000
--- a/arch/arm/mach-integrator/headsmp.S
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * linux/arch/arm/mach-integrator/headsmp.S
3 *
4 * Copyright (c) 2003 ARM Limited
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13
14 __INIT
15
16/*
17 * Integrator specific entry point for secondary CPUs. This provides
18 * a "holding pen" into which all secondary cores are held until we're
19 * ready for them to initialise.
20 */
21ENTRY(integrator_secondary_startup)
22 adr r4, 1f
23 ldmia r4, {r5, r6}
24 sub r4, r4, r5
25 ldr r6, [r6, r4]
26pen: ldr r7, [r6]
27 cmp r7, r0
28 bne pen
29
30 /*
31 * we've been released from the holding pen: secondary_stack
32 * should now contain the SVC stack for this core
33 */
34 b secondary_startup
35
361: .long .
37 .long phys_pen_release
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index af9ebccac7c1..d4d8134ce567 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -33,6 +33,7 @@
33#include <asm/irq.h> 33#include <asm/irq.h>
34#include <asm/system.h> 34#include <asm/system.h>
35#include <asm/mach/pci.h> 35#include <asm/mach/pci.h>
36#include <asm/irq_regs.h>
36 37
37#include <asm/hardware/pci_v3.h> 38#include <asm/hardware/pci_v3.h>
38 39
diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c
deleted file mode 100644
index 613b841a10f3..000000000000
--- a/arch/arm/mach-integrator/platsmp.c
+++ /dev/null
@@ -1,204 +0,0 @@
1/*
2 * linux/arch/arm/mach-cintegrator/platsmp.c
3 *
4 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/errno.h>
15#include <linux/mm.h>
16
17#include <asm/atomic.h>
18#include <asm/cacheflush.h>
19#include <asm/delay.h>
20#include <asm/mmu_context.h>
21#include <asm/ptrace.h>
22#include <asm/smp.h>
23
24extern void integrator_secondary_startup(void);
25
26/*
27 * control for which core is the next to come out of the secondary
28 * boot "holding pen"
29 */
30volatile int __cpuinitdata pen_release = -1;
31unsigned long __cpuinitdata phys_pen_release = 0;
32
33static DEFINE_SPINLOCK(boot_lock);
34
35void __cpuinit platform_secondary_init(unsigned int cpu)
36{
37 /*
38 * the primary core may have used a "cross call" soft interrupt
39 * to get this processor out of WFI in the BootMonitor - make
40 * sure that we are no longer being sent this soft interrupt
41 */
42 smp_cross_call_done(cpumask_of_cpu(cpu));
43
44 /*
45 * if any interrupts are already enabled for the primary
46 * core (e.g. timer irq), then they will not have been enabled
47 * for us: do so
48 */
49 secondary_scan_irqs();
50
51 /*
52 * let the primary processor know we're out of the
53 * pen, then head off into the C entry point
54 */
55 pen_release = -1;
56
57 /*
58 * Synchronise with the boot thread.
59 */
60 spin_lock(&boot_lock);
61 spin_unlock(&boot_lock);
62}
63
64int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
65{
66 unsigned long timeout;
67
68 /*
69 * set synchronisation state between this boot processor
70 * and the secondary one
71 */
72 spin_lock(&boot_lock);
73
74 /*
75 * The secondary processor is waiting to be released from
76 * the holding pen - release it, then wait for it to flag
77 * that it has been released by resetting pen_release.
78 *
79 * Note that "pen_release" is the hardware CPU ID, whereas
80 * "cpu" is Linux's internal ID.
81 */
82 pen_release = cpu;
83 flush_cache_all();
84
85 /*
86 * XXX
87 *
88 * This is a later addition to the booting protocol: the
89 * bootMonitor now puts secondary cores into WFI, so
90 * poke_milo() no longer gets the cores moving; we need
91 * to send a soft interrupt to wake the secondary core.
92 * Use smp_cross_call() for this, since there's little
93 * point duplicating the code here
94 */
95 smp_cross_call(cpumask_of_cpu(cpu));
96
97 timeout = jiffies + (1 * HZ);
98 while (time_before(jiffies, timeout)) {
99 if (pen_release == -1)
100 break;
101
102 udelay(10);
103 }
104
105 /*
106 * now the secondary core is starting up let it run its
107 * calibrations, then wait for it to finish
108 */
109 spin_unlock(&boot_lock);
110
111 return pen_release != -1 ? -ENOSYS : 0;
112}
113
114static void __init poke_milo(void)
115{
116 extern void secondary_startup(void);
117
118 /* nobody is to be released from the pen yet */
119 pen_release = -1;
120
121 phys_pen_release = virt_to_phys(&pen_release);
122
123 /*
124 * write the address of secondary startup into the system-wide
125 * flags register, then clear the bottom two bits, which is what
126 * BootMonitor is waiting for
127 */
128#if 1
129#define CINTEGRATOR_HDR_FLAGSS_OFFSET 0x30
130 __raw_writel(virt_to_phys(integrator_secondary_startup),
131 (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
132 CINTEGRATOR_HDR_FLAGSS_OFFSET));
133#define CINTEGRATOR_HDR_FLAGSC_OFFSET 0x34
134 __raw_writel(3,
135 (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
136 CINTEGRATOR_HDR_FLAGSC_OFFSET));
137#endif
138
139 mb();
140}
141
142/*
143 * Initialise the CPU possible map early - this describes the CPUs
144 * which may be present or become present in the system.
145 */
146void __init smp_init_cpus(void)
147{
148 unsigned int i, ncores = get_core_count();
149
150 for (i = 0; i < ncores; i++)
151 cpu_set(i, cpu_possible_map);
152}
153
154void __init smp_prepare_cpus(unsigned int max_cpus)
155{
156 unsigned int ncores = get_core_count();
157 unsigned int cpu = smp_processor_id();
158 int i;
159
160 /* sanity check */
161 if (ncores == 0) {
162 printk(KERN_ERR
163 "Integrator/CP: strange CM count of 0? Default to 1\n");
164
165 ncores = 1;
166 }
167
168 if (ncores > NR_CPUS) {
169 printk(KERN_WARNING
170 "Integrator/CP: no. of cores (%d) greater than configured "
171 "maximum of %d - clipping\n",
172 ncores, NR_CPUS);
173 ncores = NR_CPUS;
174 }
175
176 /*
177 * start with some more config for the Boot CPU, now that
178 * the world is a bit more alive (which was not the case
179 * when smp_prepare_boot_cpu() was called)
180 */
181 smp_store_cpu_info(cpu);
182
183 /*
184 * are we trying to boot more cores than exist?
185 */
186 if (max_cpus > ncores)
187 max_cpus = ncores;
188
189 /*
190 * Initialise the present map, which describes the set of CPUs
191 * actually populated at the present time.
192 */
193 for (i = 0; i < max_cpus; i++)
194 cpu_set(i, cpu_present_map);
195
196 /*
197 * Do we need any more CPUs? If so, then let them know where
198 * to start. Note that, on modern versions of MILO, the "poke"
199 * doesn't actually do anything until each individual core is
200 * sent a soft interrupt to get it out of WFI
201 */
202 if (max_cpus > 1)
203 poke_milo();
204}
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index 5791addd436b..69f07b25b3c9 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -30,77 +30,65 @@
30 30
31/* INTCTL0 CP6 R0 Page 4 31/* INTCTL0 CP6 R0 Page 4
32 */ 32 */
33static inline u32 read_intctl_0(void) 33static u32 read_intctl_0(void)
34{ 34{
35 u32 val; 35 u32 val;
36 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); 36 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
37 return val; 37 return val;
38} 38}
39static inline void write_intctl_0(u32 val) 39static void write_intctl_0(u32 val)
40{ 40{
41 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); 41 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
42} 42}
43 43
44/* INTCTL1 CP6 R1 Page 4 44/* INTCTL1 CP6 R1 Page 4
45 */ 45 */
46static inline u32 read_intctl_1(void) 46static u32 read_intctl_1(void)
47{ 47{
48 u32 val; 48 u32 val;
49 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); 49 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
50 return val; 50 return val;
51} 51}
52static inline void write_intctl_1(u32 val) 52static void write_intctl_1(u32 val)
53{ 53{
54 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); 54 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
55} 55}
56 56
57/* INTCTL2 CP6 R2 Page 4 57/* INTCTL2 CP6 R2 Page 4
58 */ 58 */
59static inline u32 read_intctl_2(void) 59static u32 read_intctl_2(void)
60{ 60{
61 u32 val; 61 u32 val;
62 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val)); 62 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
63 return val; 63 return val;
64} 64}
65static inline void write_intctl_2(u32 val) 65static void write_intctl_2(u32 val)
66{ 66{
67 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val)); 67 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
68} 68}
69 69
70/* INTCTL3 CP6 R3 Page 4 70/* INTCTL3 CP6 R3 Page 4
71 */ 71 */
72static inline u32 read_intctl_3(void) 72static u32 read_intctl_3(void)
73{ 73{
74 u32 val; 74 u32 val;
75 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val)); 75 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
76 return val; 76 return val;
77} 77}
78static inline void write_intctl_3(u32 val) 78static void write_intctl_3(u32 val)
79{ 79{
80 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val)); 80 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
81} 81}
82 82
83/* INTSTR0 CP6 R0 Page 5 83/* INTSTR0 CP6 R0 Page 5
84 */ 84 */
85static inline u32 read_intstr_0(void) 85static void write_intstr_0(u32 val)
86{
87 u32 val;
88 asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
89 return val;
90}
91static inline void write_intstr_0(u32 val)
92{ 86{
93 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val)); 87 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
94} 88}
95 89
96/* INTSTR1 CP6 R1 Page 5 90/* INTSTR1 CP6 R1 Page 5
97 */ 91 */
98static inline u32 read_intstr_1(void)
99{
100 u32 val;
101 asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
102 return val;
103}
104static void write_intstr_1(u32 val) 92static void write_intstr_1(u32 val)
105{ 93{
106 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val)); 94 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
@@ -108,12 +96,6 @@ static void write_intstr_1(u32 val)
108 96
109/* INTSTR2 CP6 R2 Page 5 97/* INTSTR2 CP6 R2 Page 5
110 */ 98 */
111static inline u32 read_intstr_2(void)
112{
113 u32 val;
114 asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
115 return val;
116}
117static void write_intstr_2(u32 val) 99static void write_intstr_2(u32 val)
118{ 100{
119 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val)); 101 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
@@ -121,12 +103,6 @@ static void write_intstr_2(u32 val)
121 103
122/* INTSTR3 CP6 R3 Page 5 104/* INTSTR3 CP6 R3 Page 5
123 */ 105 */
124static inline u32 read_intstr_3(void)
125{
126 u32 val;
127 asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
128 return val;
129}
130static void write_intstr_3(u32 val) 106static void write_intstr_3(u32 val)
131{ 107{
132 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val)); 108 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
@@ -134,12 +110,6 @@ static void write_intstr_3(u32 val)
134 110
135/* INTBASE CP6 R0 Page 2 111/* INTBASE CP6 R0 Page 2
136 */ 112 */
137static inline u32 read_intbase(void)
138{
139 u32 val;
140 asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
141 return val;
142}
143static void write_intbase(u32 val) 113static void write_intbase(u32 val)
144{ 114{
145 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val)); 115 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
@@ -147,12 +117,6 @@ static void write_intbase(u32 val)
147 117
148/* INTSIZE CP6 R2 Page 2 118/* INTSIZE CP6 R2 Page 2
149 */ 119 */
150static inline u32 read_intsize(void)
151{
152 u32 val;
153 asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
154 return val;
155}
156static void write_intsize(u32 val) 120static void write_intsize(u32 val)
157{ 121{
158 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val)); 122 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index 2d2369302220..63ef1124ca5c 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -30,52 +30,52 @@ static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
30 30
31/* IMIPR0 CP6 R8 Page 1 31/* IMIPR0 CP6 R8 Page 1
32 */ 32 */
33static inline u32 read_imipr_0(void) 33static u32 read_imipr_0(void)
34{ 34{
35 u32 val; 35 u32 val;
36 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); 36 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
37 return val; 37 return val;
38} 38}
39static inline void write_imipr_0(u32 val) 39static void write_imipr_0(u32 val)
40{ 40{
41 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); 41 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
42} 42}
43 43
44/* IMIPR1 CP6 R9 Page 1 44/* IMIPR1 CP6 R9 Page 1
45 */ 45 */
46static inline u32 read_imipr_1(void) 46static u32 read_imipr_1(void)
47{ 47{
48 u32 val; 48 u32 val;
49 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); 49 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
50 return val; 50 return val;
51} 51}
52static inline void write_imipr_1(u32 val) 52static void write_imipr_1(u32 val)
53{ 53{
54 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); 54 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
55} 55}
56 56
57/* IMIPR2 CP6 R10 Page 1 57/* IMIPR2 CP6 R10 Page 1
58 */ 58 */
59static inline u32 read_imipr_2(void) 59static u32 read_imipr_2(void)
60{ 60{
61 u32 val; 61 u32 val;
62 asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); 62 asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
63 return val; 63 return val;
64} 64}
65static inline void write_imipr_2(u32 val) 65static void write_imipr_2(u32 val)
66{ 66{
67 asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); 67 asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
68} 68}
69 69
70/* IMIPR3 CP6 R11 Page 1 70/* IMIPR3 CP6 R11 Page 1
71 */ 71 */
72static inline u32 read_imipr_3(void) 72static u32 read_imipr_3(void)
73{ 73{
74 u32 val; 74 u32 val;
75 asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); 75 asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
76 return val; 76 return val;
77} 77}
78static inline void write_imipr_3(u32 val) 78static void write_imipr_3(u32 val)
79{ 79{
80 asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); 80 asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
81} 81}
@@ -190,5 +190,5 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
190 write_msi_msg(irq, &msg); 190 write_msi_msg(irq, &msg);
191 set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); 191 set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
192 192
193 return irq; 193 return 0;
194} 194}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 6baeb26c3aa3..9d63d7f260ca 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -145,7 +145,7 @@ void iop13xx_map_pci_memory(void)
145 } 145 }
146} 146}
147 147
148static inline int iop13xx_atu_function(int atu) 148static int iop13xx_atu_function(int atu)
149{ 149{
150 int func = 0; 150 int func = 0;
151 /* the function number depends on the value of the 151 /* the function number depends on the value of the
@@ -260,7 +260,7 @@ static int iop13xx_atux_pci_status(int clear)
260 * data. Note that the data dependency on %0 encourages an abort 260 * data. Note that the data dependency on %0 encourages an abort
261 * to be detected before we return. 261 * to be detected before we return.
262 */ 262 */
263static inline u32 iop13xx_atux_read(unsigned long addr) 263static u32 iop13xx_atux_read(unsigned long addr)
264{ 264{
265 u32 val; 265 u32 val;
266 266
@@ -388,7 +388,7 @@ static int iop13xx_atue_pci_status(int clear)
388 return err; 388 return err;
389} 389}
390 390
391static inline int __init 391static int
392iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) 392iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
393{ 393{
394 WARN_ON(idsel != 0); 394 WARN_ON(idsel != 0);
@@ -402,7 +402,7 @@ iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
402 } 402 }
403} 403}
404 404
405static inline u32 iop13xx_atue_read(unsigned long addr) 405static u32 iop13xx_atue_read(unsigned long addr)
406{ 406{
407 u32 val; 407 u32 val;
408 408
@@ -990,7 +990,7 @@ void __init iop13xx_pci_init(void)
990 "imprecise external abort"); 990 "imprecise external abort");
991} 991}
992 992
993/* intialize the pci memory space. handle any combination of 993/* initialize the pci memory space. handle any combination of
994 * atue and atux enabled/disabled 994 * atue and atux enabled/disabled
995 */ 995 */
996int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) 996int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 45f4f13ae11b..5776fd884115 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -75,7 +75,7 @@ void __init glantank_map_io(void)
75#define INTC IRQ_IOP32X_XINT2 75#define INTC IRQ_IOP32X_XINT2
76#define INTD IRQ_IOP32X_XINT3 76#define INTD IRQ_IOP32X_XINT3
77 77
78static inline int __init 78static int __init
79glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 79glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
80{ 80{
81 static int pci_irq_table[][4] = { 81 static int pci_irq_table[][4] = {
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 7b21c6e13e59..d4eefbea1fe6 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -104,7 +104,7 @@ void __init iq31244_map_io(void)
104/* 104/*
105 * EP80219/IQ31244 PCI. 105 * EP80219/IQ31244 PCI.
106 */ 106 */
107static inline int __init 107static int __init
108ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 108ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
109{ 109{
110 int irq; 110 int irq;
@@ -140,7 +140,7 @@ static struct hw_pci ep80219_pci __initdata = {
140 .map_irq = ep80219_pci_map_irq, 140 .map_irq = ep80219_pci_map_irq,
141}; 141};
142 142
143static inline int __init 143static int __init
144iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 144iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
145{ 145{
146 int irq; 146 int irq;
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index bc25fb91e7b9..8d9f49164a84 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -72,7 +72,7 @@ void __init iq80321_map_io(void)
72/* 72/*
73 * IQ80321 PCI. 73 * IQ80321 PCI.
74 */ 74 */
75static inline int __init 75static int __init
76iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 76iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
77{ 77{
78 int irq; 78 int irq;
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index 82598dc18d80..c971171c2905 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -21,12 +21,12 @@
21 21
22static u32 iop32x_mask; 22static u32 iop32x_mask;
23 23
24static inline void intctl_write(u32 val) 24static void intctl_write(u32 val)
25{ 25{
26 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); 26 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
27} 27}
28 28
29static inline void intstr_write(u32 val) 29static void intstr_write(u32 val)
30{ 30{
31 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); 31 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
32} 32}
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index 5f07344d96f3..d55005d64781 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -76,7 +76,7 @@ void __init n2100_map_io(void)
76/* 76/*
77 * N2100 PCI. 77 * N2100 PCI.
78 */ 78 */
79static inline int __init 79static int __init
80n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 80n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
81{ 81{
82 int irq; 82 int irq;
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 376c932830be..2b063180687a 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -55,7 +55,7 @@ static struct sys_timer iq80331_timer = {
55/* 55/*
56 * IQ80331 PCI. 56 * IQ80331 PCI.
57 */ 57 */
58static inline int __init 58static int __init
59iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 59iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
60{ 60{
61 int irq; 61 int irq;
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 58c81496c6f6..7889ce3cb08e 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -55,7 +55,7 @@ static struct sys_timer iq80332_timer = {
55/* 55/*
56 * IQ80332 PCI. 56 * IQ80332 PCI.
57 */ 57 */
58static inline int __init 58static int __init
59iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 59iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
60{ 60{
61 int irq; 61 int irq;
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index c65ea78a2427..f09dd054b9c0 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -22,32 +22,32 @@
22static u32 iop33x_mask0; 22static u32 iop33x_mask0;
23static u32 iop33x_mask1; 23static u32 iop33x_mask1;
24 24
25static inline void intctl0_write(u32 val) 25static void intctl0_write(u32 val)
26{ 26{
27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); 27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
28} 28}
29 29
30static inline void intctl1_write(u32 val) 30static void intctl1_write(u32 val)
31{ 31{
32 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); 32 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
33} 33}
34 34
35static inline void intstr0_write(u32 val) 35static void intstr0_write(u32 val)
36{ 36{
37 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); 37 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
38} 38}
39 39
40static inline void intstr1_write(u32 val) 40static void intstr1_write(u32 val)
41{ 41{
42 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); 42 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
43} 43}
44 44
45static inline void intbase_write(u32 val) 45static void intbase_write(u32 val)
46{ 46{
47 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); 47 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
48} 48}
49 49
50static inline void intsize_write(u32 val) 50static void intsize_write(u32 val)
51{ 51{
52 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); 52 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
53} 53}
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index 500e997ba7a4..9c49435d42c3 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -198,7 +198,7 @@ subsys_initcall(enp2611_pci_init);
198 198
199 199
200/************************************************************************* 200/*************************************************************************
201 * ENP-2611 Machine Intialization 201 * ENP-2611 Machine Initialization
202 *************************************************************************/ 202 *************************************************************************/
203static struct flash_platform_data enp2611_flash_platform_data = { 203static struct flash_platform_data enp2611_flash_platform_data = {
204 .map_name = "cfi_probe", 204 .map_name = "cfi_probe",
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 52b368b34346..011065b967b4 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -195,7 +195,7 @@ void __init ixdp2x00_map_io(void)
195 * instances of the kernel. So far so good. Peers on the PCI bus running 195 * instances of the kernel. So far so good. Peers on the PCI bus running
196 * Linux is a common design in telecom systems. The problem is that instead 196 * Linux is a common design in telecom systems. The problem is that instead
197 * of all the devices being controlled by a single host, different 197 * of all the devices being controlled by a single host, different
198 * devices are controlles by different NPUs on the same bus, leading to 198 * devices are controlled by different NPUs on the same bus, leading to
199 * multiple hosts on the bus. The exact bus layout looks like: 199 * multiple hosts on the bus. The exact bus layout looks like:
200 * 200 *
201 * Bus 0 201 * Bus 0
@@ -211,7 +211,7 @@ void __init ixdp2x00_map_io(void)
211 * | | | | | 211 * | | | | |
212 * ... Dev PMC Media Eth0 Eth1 ... 212 * ... Dev PMC Media Eth0 Eth1 ...
213 * 213 *
214 * The master controlls all but Eth1, which is controlled by the 214 * The master controls all but Eth1, which is controlled by the
215 * slave. What this means is that the both the master and the slave 215 * slave. What this means is that the both the master and the slave
216 * have to scan the bus, but only one of them can enumerate the bus. 216 * have to scan the bus, but only one of them can enumerate the bus.
217 * In addition, after the bus is scanned, each kernel must remove 217 * In addition, after the bus is scanned, each kernel must remove
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 3084a5fa751c..d3d730d2fc2b 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -276,7 +276,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
276 /* Device is located after first MB bridge */ 276 /* Device is located after first MB bridge */
277 case 0x0008: 277 case 0x0008:
278 if (tmp_bus == dev->bus) { 278 if (tmp_bus == dev->bus) {
279 /* Device is located directy after first MB bridge */ 279 /* Device is located directly after first MB bridge */
280 switch (devpin) { 280 switch (devpin) {
281 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */ 281 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
282 if (machine_is_ixdp2401()) 282 if (machine_is_ixdp2401())
@@ -299,7 +299,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
299 break; 299 break;
300 case 0x0010: 300 case 0x0010:
301 if (tmp_bus == dev->bus) { 301 if (tmp_bus == dev->bus) {
302 /* Device is located directy after second MB bridge */ 302 /* Device is located directly after second MB bridge */
303 /* Secondary bus of second bridge */ 303 /* Secondary bus of second bridge */
304 switch (devpin) { 304 switch (devpin) {
305 case DEVPIN(0, 1): /* DB#0 */ 305 case DEVPIN(0, 1): /* DB#0 */
@@ -348,7 +348,7 @@ int __init ixdp2x01_pci_init(void)
348subsys_initcall(ixdp2x01_pci_init); 348subsys_initcall(ixdp2x01_pci_init);
349 349
350/************************************************************************* 350/*************************************************************************
351 * IXDP2x01 Machine Intialization 351 * IXDP2x01 Machine Initialization
352 *************************************************************************/ 352 *************************************************************************/
353static struct flash_platform_data ixdp2x01_flash_platform_data = { 353static struct flash_platform_data ixdp2x01_flash_platform_data = {
354 .map_name = "cfi_probe", 354 .map_name = "cfi_probe",
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 5a09a90c08fb..03f4cf7f9dec 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -102,7 +102,7 @@ int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where,
102} 102}
103 103
104/* 104/*
105 * We don't do error checks by callling clear_master_aborts() b/c the 105 * We don't do error checks by calling clear_master_aborts() b/c the
106 * assumption is that the caller did a read first to make sure a device 106 * assumption is that the caller did a read first to make sure a device
107 * exists. 107 * exists.
108 */ 108 */
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index b644bbab7d0a..16356ffc86ae 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -389,7 +389,7 @@ struct sys_timer ixp23xx_timer = {
389 389
390 390
391/************************************************************************* 391/*************************************************************************
392 * IXP23xx Platform Initializaion 392 * IXP23xx Platform Initialization
393 *************************************************************************/ 393 *************************************************************************/
394static struct resource ixp23xx_uart_resources[] = { 394static struct resource ixp23xx_uart_resources[] = {
395 { 395 {
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 30f1300e0e21..dc6725bda3c4 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-ixp4xx/gtwx5715-setup.c 2 * arch/arm/mach-ixp4xx/gtwx5715-setup.c
3 * 3 *
4 * Gemtek GTWX5715 (Linksys WRV54G) board settup 4 * Gemtek GTWX5715 (Linksys WRV54G) board setup
5 * 5 *
6 * Copyright (C) 2004 George T. Joseph 6 * Copyright (C) 2004 George T. Joseph
7 * Derived from Coyote 7 * Derived from Coyote
diff --git a/arch/arm/mach-lh7a40x/lcd-panel.h b/arch/arm/mach-lh7a40x/lcd-panel.h
index 4fb2efc4950f..df6e38ed425b 100644
--- a/arch/arm/mach-lh7a40x/lcd-panel.h
+++ b/arch/arm/mach-lh7a40x/lcd-panel.h
@@ -126,7 +126,7 @@ static struct clcd_panel_extra lcd_panel_extra = {
126 126
127 */ 127 */
128 128
129/* The full horozontal cycle (Th) is clock/360/400/450. */ 129/* The full horizontal cycle (Th) is clock/360/400/450. */
130/* The full vertical cycle (Tv) is line/251/262/280. */ 130/* The full vertical cycle (Tv) is line/251/262/280. */
131 131
132#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */ 132#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */
@@ -162,7 +162,7 @@ static struct clcd_panel lcd_panel = {
162 /* Logic Product Development LCD 6.4" VGA -10 */ 162 /* Logic Product Development LCD 6.4" VGA -10 */
163 /* Sharp PN LQ64D343 */ 163 /* Sharp PN LQ64D343 */
164 164
165/* The full horozontal cycle (Th) is clock/750/800/900. */ 165/* The full horizontal cycle (Th) is clock/750/800/900. */
166/* The full vertical cycle (Tv) is line/515/525/560. */ 166/* The full vertical cycle (Tv) is line/515/525/560. */
167 167
168#define PIX_CLOCK_TARGET (28330000) 168#define PIX_CLOCK_TARGET (28330000)
@@ -243,7 +243,7 @@ static struct clcd_panel lcd_panel = {
243 * (fdisk, e2fsck). And, at that speed the display may have a visible 243 * (fdisk, e2fsck). And, at that speed the display may have a visible
244 * flicker. */ 244 * flicker. */
245 245
246/* The full horozontal cycle (Th) is clock/832/1056/1395. */ 246/* The full horizontal cycle (Th) is clock/832/1056/1395. */
247 247
248#define PIX_CLOCK_TARGET (20000000) 248#define PIX_CLOCK_TARGET (20000000)
249#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) 249#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time.c
index dd257084441c..b97d0c54a388 100644
--- a/arch/arm/mach-ns9xxx/time.c
+++ b/arch/arm/mach-ns9xxx/time.c
@@ -35,7 +35,7 @@ static unsigned long ns9xxx_timer_gettimeoffset(void)
35{ 35{
36 /* return the microseconds which have passed since the last interrupt 36 /* return the microseconds which have passed since the last interrupt
37 * was _serviced_. That is, if an interrupt is pending or the counter 37 * was _serviced_. That is, if an interrupt is pending or the counter
38 * reloads, return one periode more. */ 38 * reloads, return one period more. */
39 39
40 u32 counter1 = SYS_TR(0); 40 u32 counter1 = SYS_TR(0);
41 int pending = SYS_ISR & (1 << IRQ_TIMER0); 41 int pending = SYS_ISR & (1 << IRQ_TIMER0);
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 856c681ebbbc..f6ecdd3a2478 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -38,7 +38,7 @@ config MACH_OMAP_H2
38config MACH_OMAP_H3 38config MACH_OMAP_H3
39 bool "TI H3 Support" 39 bool "TI H3 Support"
40 depends on ARCH_OMAP1 && ARCH_OMAP16XX 40 depends on ARCH_OMAP1 && ARCH_OMAP16XX
41 select GPIOEXPANDER_OMAP 41# select GPIOEXPANDER_OMAP
42 help 42 help
43 TI OMAP 1710 H3 board support. Say Y here if you have such 43 TI OMAP 1710 H3 board support. Say Y here if you have such
44 a board. 44 a board.
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 7d0cf7af88ce..e7130293a03f 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -385,7 +385,7 @@ static void __init osk_init(void)
385 /* Workaround for wrong CS3 (NOR flash) timing 385 /* Workaround for wrong CS3 (NOR flash) timing
386 * There are some U-Boot versions out there which configure 386 * There are some U-Boot versions out there which configure
387 * wrong CS3 memory timings. This mainly leads to CRC 387 * wrong CS3 memory timings. This mainly leads to CRC
388 * or similiar errors if you use NOR flash (e.g. with JFFS2) 388 * or similar errors if you use NOR flash (e.g. with JFFS2)
389 */ 389 */
390 if (EMIFS_CCS(3) != EMIFS_CS3_VAL) 390 if (EMIFS_CCS(3) != EMIFS_CS3_VAL)
391 EMIFS_CCS(3) = EMIFS_CS3_VAL; 391 EMIFS_CCS(3) = EMIFS_CS3_VAL;
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 4bc8a62909b9..015824185629 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -7,7 +7,7 @@
7 * 7 *
8 * Original version : Laurent Gonzalez 8 * Original version : Laurent Gonzalez
9 * 9 *
10 * Maintainters : http://palmtelinux.sf.net 10 * Maintainers : http://palmtelinux.sf.net
11 * palmtelinux-developpers@lists.sf.net 11 * palmtelinux-developpers@lists.sf.net
12 * 12 *
13 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 8caee68aa090..5bb348e2e315 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -438,7 +438,7 @@ void omap_pm_suspend(void)
438 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); 438 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
439 439
440 /* 440 /*
441 * Reenable interrupts 441 * Re-enable interrupts
442 */ 442 */
443 443
444 local_irq_enable(); 444 local_irq_enable();
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 5170481afeab..588adb5ab47f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -443,7 +443,7 @@ static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
443 443
444/* 444/*
445 * Check the DLL lock state, and return tue if running in unlock mode. 445 * Check the DLL lock state, and return tue if running in unlock mode.
446 * This is needed to compenste for the shifted DLL value in unlock mode. 446 * This is needed to compensate for the shifted DLL value in unlock mode.
447 */ 447 */
448static u32 omap2_dll_force_needed(void) 448static u32 omap2_dll_force_needed(void)
449{ 449{
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 162978fd5359..4f791866b910 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -338,7 +338,7 @@ struct prcm_config {
338/* 338/*
339 * These represent optimal values for common parts, it won't work for all. 339 * These represent optimal values for common parts, it won't work for all.
340 * As long as you scale down, most parameters are still work, they just 340 * As long as you scale down, most parameters are still work, they just
341 * become sub-optimal. The RFR value goes in the oppisite direction. If you 341 * become sub-optimal. The RFR value goes in the opposite direction. If you
342 * don't adjust it down as your clock period increases the refresh interval 342 * don't adjust it down as your clock period increases the refresh interval
343 * will not be met. Setting all parameters for complete worst case may work, 343 * will not be met. Setting all parameters for complete worst case may work,
344 * but may cut memory performance by 2x. Due to errata the DLLs need to be 344 * but may cut memory performance by 2x. Due to errata the DLLs need to be
@@ -384,7 +384,7 @@ struct prcm_config {
384 * Filling in table based on H4 boards and 2430-SDPs variants available. 384 * Filling in table based on H4 boards and 2430-SDPs variants available.
385 * There are quite a few more rates combinations which could be defined. 385 * There are quite a few more rates combinations which could be defined.
386 * 386 *
387 * When multiple values are defiend the start up will try and choose the 387 * When multiple values are defined the start up will try and choose the
388 * fastest one. If a 'fast' value is defined, then automatically, the /2 388 * fastest one. If a 'fast' value is defined, then automatically, the /2
389 * one should be included as it can be used. Generally having more that 389 * one should be included as it can be used. Generally having more that
390 * one fast set does not make sense, as static timings need to be changed 390 * one fast set does not make sense, as static timings need to be changed
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c
index a72476c24621..365b9435f748 100644
--- a/arch/arm/mach-pxa/corgi_lcd.c
+++ b/arch/arm/mach-pxa/corgi_lcd.c
@@ -40,7 +40,7 @@
40#define PICTRL_ADRS 0x06 40#define PICTRL_ADRS 0x06
41#define POLCTRL_ADRS 0x07 41#define POLCTRL_ADRS 0x07
42 42
43/* Resgister Bit Definitions */ 43/* Register Bit Definitions */
44#define RESCTL_QVGA 0x01 44#define RESCTL_QVGA 0x01
45#define RESCTL_VGA 0x00 45#define RESCTL_VGA 0x00
46 46
@@ -55,11 +55,11 @@
55#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */ 55#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
56#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */ 56#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
57#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */ 57#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
58#define POWER0_COM_ON 0x08 /* COM Powewr Supply ON */ 58#define POWER0_COM_ON 0x08 /* COM Power Supply ON */
59#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */ 59#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
60 60
61#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */ 61#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
62#define POWER0_COM_OFF 0x00 /* COM Powewr Supply OFF */ 62#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */
63#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */ 63#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
64 64
65#define PICTRL_INIT_STATE 0x01 65#define PICTRL_INIT_STATE 0x01
@@ -145,7 +145,7 @@ static void lcdtg_set_common_voltage(u8 base_data, u8 data)
145 lcdtg_i2c_send_stop(base_data); 145 lcdtg_i2c_send_stop(base_data);
146} 146}
147 147
148/* Set Phase Adjuct */ 148/* Set Phase Adjust */
149static void lcdtg_set_phadadj(int mode) 149static void lcdtg_set_phadadj(int mode)
150{ 150{
151 int adj; 151 int adj;
@@ -226,7 +226,7 @@ static void lcdtg_hw_init(int mode)
226 /* Signals output enable */ 226 /* Signals output enable */
227 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0); 227 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
228 228
229 /* Set Phase Adjuct */ 229 /* Set Phase Adjust */
230 lcdtg_set_phadadj(mode); 230 lcdtg_set_phadadj(mode);
231 231
232 /* Initialize for Input Signals from ATI */ 232 /* Initialize for Input Signals from ATI */
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c
index ff6b4ee037f5..40dea3d5142b 100644
--- a/arch/arm/mach-pxa/corgi_ssp.c
+++ b/arch/arm/mach-pxa/corgi_ssp.c
@@ -32,7 +32,7 @@ static struct corgissp_machinfo *ssp_machinfo;
32 * There are three devices connected to the SSP interface: 32 * There are three devices connected to the SSP interface:
33 * 1. A touchscreen controller (TI ADS7846 compatible) 33 * 1. A touchscreen controller (TI ADS7846 compatible)
34 * 2. An LCD contoller (with some Backlight functionality) 34 * 2. An LCD contoller (with some Backlight functionality)
35 * 3. A battery moinitoring IC (Maxim MAX1111) 35 * 3. A battery monitoring IC (Maxim MAX1111)
36 * 36 *
37 * Each device uses a different speed/mode of communication. 37 * Each device uses a different speed/mode of communication.
38 * 38 *
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
index caf6b8bb6c95..c7bdf04ab094 100644
--- a/arch/arm/mach-realview/localtimer.c
+++ b/arch/arm/mach-realview/localtimer.c
@@ -30,7 +30,7 @@ static unsigned long mpcore_timer_rate;
30/* 30/*
31 * local_timer_ack: checks for a local timer interrupt. 31 * local_timer_ack: checks for a local timer interrupt.
32 * 32 *
33 * If a local timer interrupt has occured, acknowledge and return 1. 33 * If a local timer interrupt has occurred, acknowledge and return 1.
34 * Otherwise, return 0. 34 * Otherwise, return 0.
35 */ 35 */
36int local_timer_ack(void) 36int local_timer_ack(void)
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 5ccd0be23a33..5c9bcea74767 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -17,6 +17,7 @@
17#include <linux/list.h> 17#include <linux/list.h>
18#include <linux/timer.h> 18#include <linux/timer.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/sysdev.h>
20#include <linux/serial_core.h> 21#include <linux/serial_core.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
22 23
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 9cc4253d7bbc..d86e6f18bac9 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -27,6 +27,7 @@
27#include <linux/list.h> 27#include <linux/list.h>
28#include <linux/timer.h> 28#include <linux/timer.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/sysdev.h>
30#include <linux/platform_device.h> 31#include <linux/platform_device.h>
31#include <linux/serial_core.h> 32#include <linux/serial_core.h>
32#include <linux/spi/spi.h> 33#include <linux/spi/spi.h>
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index d0f4695c09d9..668cccefe7b0 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -59,8 +59,8 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
59 [DMACH_SPI1] = { 59 [DMACH_SPI1] = {
60 .name = "spi1", 60 .name = "spi1",
61 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), 61 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
62 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, 62 .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
63 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, 63 .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT,
64 }, 64 },
65 [DMACH_UART0] = { 65 [DMACH_UART0] = {
66 .name = "uart0", 66 .name = "uart0",
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index aafe0bc593f1..c602aa39f9c4 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -37,6 +37,7 @@
37#include <asm/arch/regs-gpio.h> 37#include <asm/arch/regs-gpio.h>
38#include <asm/arch/regs-gpioj.h> 38#include <asm/arch/regs-gpioj.h>
39#include <asm/arch/regs-dsc.h> 39#include <asm/arch/regs-dsc.h>
40#include <asm/arch/regs-spi.h>
40 41
41#include <asm/plat-s3c24xx/s3c2412.h> 42#include <asm/plat-s3c24xx/s3c2412.h>
42#include <asm/plat-s3c24xx/cpu.h> 43#include <asm/plat-s3c24xx/cpu.h>
@@ -74,6 +75,14 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
74 s3c_device_sdi.name = "s3c2412-sdi"; 75 s3c_device_sdi.name = "s3c2412-sdi";
75 s3c_device_lcd.name = "s3c2412-lcd"; 76 s3c_device_lcd.name = "s3c2412-lcd";
76 s3c_device_nand.name = "s3c2412-nand"; 77 s3c_device_nand.name = "s3c2412-nand";
78
79 /* spi channel related changes, s3c2412/13 specific */
80 s3c_device_spi0.name = "s3c2412-spi";
81 s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
82 s3c_device_spi1.name = "s3c2412-spi";
83 s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
84 s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
85
77} 86}
78 87
79/* s3c2412_idle 88/* s3c2412_idle
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 324f5a237921..4d6c7a574c1a 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -45,7 +45,7 @@
45#include <asm/plat-s3c24xx/devs.h> 45#include <asm/plat-s3c24xx/devs.h>
46#include <asm/plat-s3c24xx/cpu.h> 46#include <asm/plat-s3c24xx/cpu.h>
47 47
48/* onboard perihpheral map */ 48/* onboard perihperal map */
49 49
50static struct map_desc osiris_iodesc[] __initdata = { 50static struct map_desc osiris_iodesc[] __initdata = {
51 /* ISA IO areas (may be over-written later) */ 51 /* ISA IO areas (may be over-written later) */
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index c3cc4bf158f6..866ff71c01dd 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -19,6 +19,7 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/tty.h> 20#include <linux/tty.h>
21#include <linux/console.h> 21#include <linux/console.h>
22#include <linux/sysdev.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23#include <linux/serial_core.h> 24#include <linux/serial_core.h>
24#include <linux/serial.h> 25#include <linux/serial.h>
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 0b6e360aeae7..5955efb5de8d 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -747,6 +747,25 @@ static struct clk init_clocks[] = {
747 .enable = s3c2443_clkcon_enable_h, 747 .enable = s3c2443_clkcon_enable_h,
748 .ctrlbit = S3C2443_HCLKCON_USBD, 748 .ctrlbit = S3C2443_HCLKCON_USBD,
749 }, { 749 }, {
750 .name = "hsmmc",
751 .id = -1,
752 .parent = &clk_h,
753 .enable = s3c2443_clkcon_enable_h,
754 .ctrlbit = S3C2443_HCLKCON_HSMMC,
755 }, {
756 .name = "cfc",
757 .id = -1,
758 .parent = &clk_h,
759 .enable = s3c2443_clkcon_enable_h,
760 .ctrlbit = S3C2443_HCLKCON_CFC,
761 .ctrlbit = S3C2443_HCLKCON_HSMMC,
762 }, {
763 .name = "ssmc",
764 .id = -1,
765 .parent = &clk_h,
766 .enable = s3c2443_clkcon_enable_h,
767 .ctrlbit = S3C2443_HCLKCON_SSMC,
768 }, {
750 .name = "timers", 769 .name = "timers",
751 .id = -1, 770 .id = -1,
752 .parent = &clk_p, 771 .parent = &clk_p,
@@ -791,7 +810,8 @@ static struct clk init_clocks[] = {
791 .name = "usb-bus-host", 810 .name = "usb-bus-host",
792 .id = -1, 811 .id = -1,
793 .parent = &clk_usb_bus_host, 812 .parent = &clk_usb_bus_host,
794 }, { .name = "ac97", 813 }, {
814 .name = "ac97",
795 .id = -1, 815 .id = -1,
796 .parent = &clk_p, 816 .parent = &clk_p,
797 .ctrlbit = S3C2443_PCLKCON_AC97, 817 .ctrlbit = S3C2443_PCLKCON_AC97,
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index b71ee53c2865..b1eb709ee65a 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -104,6 +104,7 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
104static struct platform_device *smdk2443_devices[] __initdata = { 104static struct platform_device *smdk2443_devices[] __initdata = {
105 &s3c_device_wdt, 105 &s3c_device_wdt,
106 &s3c_device_i2c, 106 &s3c_device_i2c,
107 &s3c_device_hsmmc,
107}; 108};
108 109
109static void __init smdk2443_map_io(void) 110static void __init smdk2443_map_io(void)
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index 11b1d0b310c3..8d8117158d23 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -63,6 +63,10 @@ int __init s3c2443_init(void)
63 63
64 s3c_device_nand.name = "s3c2412-nand"; 64 s3c_device_nand.name = "s3c2412-nand";
65 65
66 /* change WDT IRQ number */
67 s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
68 s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
69
66 return sysdev_register(&s3c2443_sysdev); 70 return sysdev_register(&s3c2443_sysdev);
67} 71}
68 72
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 416e277054c2..29cb0c1604ab 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -25,7 +25,7 @@ static unsigned long __init sa1100_get_rtc_time(void)
25{ 25{
26 /* 26 /*
27 * According to the manual we should be able to let RTTR be zero 27 * According to the manual we should be able to let RTTR be zero
28 * and then a default diviser for a 32.768KHz clock is used. 28 * and then a default divisor for a 32.768KHz clock is used.
29 * Apparently this doesn't work, at least for my SA1110 rev 5. 29 * Apparently this doesn't work, at least for my SA1110 rev 5.
30 * If the clock divider is uninitialized then reset it to the 30 * If the clock divider is uninitialized then reset it to the
31 * default value to get the 1Hz clock. 31 * default value to get the 1Hz clock.
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 15f0284010ca..5f472a8b406a 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -351,6 +351,7 @@ config CPU_V6
351 select CPU_CACHE_V6 351 select CPU_CACHE_V6
352 select CPU_CACHE_VIPT 352 select CPU_CACHE_VIPT
353 select CPU_CP15_MMU 353 select CPU_CP15_MMU
354 select CPU_HAS_ASID
354 select CPU_COPY_V6 if MMU 355 select CPU_COPY_V6 if MMU
355 select CPU_TLB_V6 if MMU 356 select CPU_TLB_V6 if MMU
356 357
@@ -376,6 +377,7 @@ config CPU_V7
376 select CPU_CACHE_V7 377 select CPU_CACHE_V7
377 select CPU_CACHE_VIPT 378 select CPU_CACHE_VIPT
378 select CPU_CP15_MMU 379 select CPU_CP15_MMU
380 select CPU_HAS_ASID
379 select CPU_COPY_V6 if MMU 381 select CPU_COPY_V6 if MMU
380 select CPU_TLB_V6 if MMU 382 select CPU_TLB_V6 if MMU
381 383
@@ -498,6 +500,12 @@ config CPU_TLB_V6
498 500
499endif 501endif
500 502
503config CPU_HAS_ASID
504 bool
505 help
506 This indicates whether the CPU has the ASID register; used to
507 tag TLB and possibly cache entries.
508
501config CPU_CP15 509config CPU_CP15
502 bool 510 bool
503 help 511 help
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 19ca333240ec..36440c899583 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 1995 Linus Torvalds 4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2001 Russell King 5 * Modifications for ARM processor (c) 1995-2001 Russell King
6 * Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc. 6 * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation. 7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
8 * Copyright (C) 1996, Cygnus Software Technologies Ltd. 8 * Copyright (C) 1996, Cygnus Software Technologies Ltd.
9 * 9 *
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index d6167ad4e011..f3ade18862aa 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -346,7 +346,7 @@ void __iounmap(volatile void __iomem *addr)
346#ifndef CONFIG_SMP 346#ifndef CONFIG_SMP
347 /* 347 /*
348 * If this is a section based mapping we need to handle it 348 * If this is a section based mapping we need to handle it
349 * specially as the VM subysystem does not know how to handle 349 * specially as the VM subsystem does not know how to handle
350 * such a beast. We need the lock here b/c we need to clear 350 * such a beast. We need the lock here b/c we need to clear
351 * all the mappings before the area can be reclaimed 351 * all the mappings before the area can be reclaimed
352 * by someone else. 352 * by someone else.
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 2ba1530d1ce1..02e050ae59f6 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -92,7 +92,7 @@ static struct cachepolicy cache_policies[] __initdata = {
92}; 92};
93 93
94/* 94/*
95 * These are useful for identifing cache coherency 95 * These are useful for identifying cache coherency
96 * problems by allowing the cache or the cache and 96 * problems by allowing the cache or the cache and
97 * writebuffer to be turned off. (Note: the write 97 * writebuffer to be turned off. (Note: the write
98 * buffer should not be on and the cache off). 98 * buffer should not be on and the cache off).
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index 7bf422978dd6..2b5aa1135b11 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -86,10 +86,10 @@ static int iop3xx_pci_status(void)
86 86
87/* 87/*
88 * Simply write the address register and read the configuration 88 * Simply write the address register and read the configuration
89 * data. Note that the 4 nop's ensure that we are able to handle 89 * data. Note that the 4 nops ensure that we are able to handle
90 * a delayed abort (in theory.) 90 * a delayed abort (in theory.)
91 */ 91 */
92static inline u32 iop3xx_read(unsigned long addr) 92static u32 iop3xx_read(unsigned long addr)
93{ 93{
94 u32 val; 94 u32 val;
95 95
@@ -322,7 +322,7 @@ void __init iop3xx_atu_disable(void)
322/* Flag to determine whether the ATU is initialized and the PCI bus scanned */ 322/* Flag to determine whether the ATU is initialized and the PCI bus scanned */
323int init_atu; 323int init_atu;
324 324
325void iop3xx_pci_preinit(void) 325void __init iop3xx_pci_preinit(void)
326{ 326{
327 if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { 327 if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
328 iop3xx_atu_disable(); 328 iop3xx_atu_disable();
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index dd8708ad0a71..7987aa6e95f8 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -73,7 +73,7 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
73 } 73 }
74 if (info != NULL) { 74 if (info != NULL) {
75 /* Check the length as a lame attempt to check for 75 /* Check the length as a lame attempt to check for
76 * binary inconsistancy. */ 76 * binary inconsistency. */
77 if (len != NO_LENGTH_CHECK) { 77 if (len != NO_LENGTH_CHECK) {
78 /* Word-align len */ 78 /* Word-align len */
79 if (len & 0x03) 79 if (len & 0x03)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 55a4d3be16b6..88d5b6d9f950 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1172,7 +1172,7 @@ static void set_b1_regs(void)
1172 break; 1172 break;
1173 default: 1173 default:
1174 BUG(); 1174 BUG();
1175 return; /* Supress warning about uninitialized vars */ 1175 return; /* Suppress warning about uninitialized vars */
1176 } 1176 }
1177 1177
1178 if (omap_dma_in_1510_mode()) { 1178 if (omap_dma_in_1510_mode()) {
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index bc46f33aede3..1f23f0459e5f 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -59,8 +59,8 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
59 59
60/* 60/*
61 * Depending on the target RAMFS firewall setup, the public usable amount of 61 * Depending on the target RAMFS firewall setup, the public usable amount of
62 * SRAM varies. The default accessable size for all device types is 2k. A GP 62 * SRAM varies. The default accessible size for all device types is 2k. A GP
63 * device allows ARM11 but not other initators for full size. This 63 * device allows ARM11 but not other initiators for full size. This
64 * functionality seems ok until some nice security API happens. 64 * functionality seems ok until some nice security API happens.
65 */ 65 */
66static int is_sram_locked(void) 66static int is_sram_locked(void)
@@ -71,7 +71,7 @@ static int is_sram_locked(void)
71 type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK; 71 type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK;
72 72
73 if (type == GP_DEVICE) { 73 if (type == GP_DEVICE) {
74 /* RAMFW: R/W access to all initators for all qualifier sets */ 74 /* RAMFW: R/W access to all initiators for all qualifier sets */
75 if (cpu_is_omap242x()) { 75 if (cpu_is_omap242x()) {
76 __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */ 76 __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */
77 __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */ 77 __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 25489aafb113..a5aedf964b88 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -177,7 +177,7 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
177 177
178 /* NOTE: SPEED and SUSP aren't configured here. OTG hosts 178 /* NOTE: SPEED and SUSP aren't configured here. OTG hosts
179 * may be able to use I2C requests to set those bits along 179 * may be able to use I2C requests to set those bits along
180 * with VBUS switching and overcurrent detction. 180 * with VBUS switching and overcurrent detection.
181 */ 181 */
182 182
183 if (cpu_class_is_omap1() && nwires != 6) 183 if (cpu_class_is_omap1() && nwires != 6)
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 908efa7d745f..7ed19b23ce56 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -18,6 +18,7 @@
18#include <linux/list.h> 18#include <linux/list.h>
19#include <linux/timer.h> 19#include <linux/timer.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/sysdev.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
22 23
23#include <linux/mtd/mtd.h> 24#include <linux/mtd/mtd.h>
@@ -29,6 +30,7 @@
29#include <asm/mach/map.h> 30#include <asm/mach/map.h>
30#include <asm/mach/irq.h> 31#include <asm/mach/irq.h>
31 32
33#include <asm/mach-types.h>
32#include <asm/hardware.h> 34#include <asm/hardware.h>
33#include <asm/io.h> 35#include <asm/io.h>
34#include <asm/irq.h> 36#include <asm/irq.h>
@@ -192,6 +194,9 @@ void __init smdk_machine_init(void)
192 s3c2410_gpio_setpin(S3C2410_GPF6, 1); 194 s3c2410_gpio_setpin(S3C2410_GPF6, 1);
193 s3c2410_gpio_setpin(S3C2410_GPF7, 1); 195 s3c2410_gpio_setpin(S3C2410_GPF7, 1);
194 196
197 if (machine_is_smdk2443())
198 smdk_nand_info.twrph0 = 50;
199
195 s3c_device_nand.dev.platform_data = &smdk_nand_info; 200 s3c_device_nand.dev.platform_data = &smdk_nand_info;
196 201
197 platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); 202 platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 0fe53b39cb2f..5875da0ae0eb 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -33,6 +33,7 @@
33 33
34#include <asm/plat-s3c24xx/devs.h> 34#include <asm/plat-s3c24xx/devs.h>
35#include <asm/plat-s3c24xx/cpu.h> 35#include <asm/plat-s3c24xx/cpu.h>
36#include <asm/arch/regs-spi.h>
36 37
37/* Serial port registrations */ 38/* Serial port registrations */
38 39
@@ -402,6 +403,36 @@ struct platform_device s3c_device_sdi = {
402 403
403EXPORT_SYMBOL(s3c_device_sdi); 404EXPORT_SYMBOL(s3c_device_sdi);
404 405
406/* High-speed MMC/SD */
407
408static struct resource s3c_hsmmc_resource[] = {
409 [0] = {
410 .start = S3C2443_PA_HSMMC,
411 .end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1,
412 .flags = IORESOURCE_MEM,
413 },
414 [1] = {
415 .start = IRQ_S3C2443_HSMMC,
416 .end = IRQ_S3C2443_HSMMC,
417 .flags = IORESOURCE_IRQ,
418 }
419};
420
421static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
422
423struct platform_device s3c_device_hsmmc = {
424 .name = "s3c-sdhci",
425 .id = -1,
426 .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
427 .resource = s3c_hsmmc_resource,
428 .dev = {
429 .dma_mask = &s3c_device_hsmmc_dmamask,
430 .coherent_dma_mask = 0xffffffffUL
431 }
432};
433
434
435
405/* SPI (0) */ 436/* SPI (0) */
406 437
407static struct resource s3c_spi0_resource[] = { 438static struct resource s3c_spi0_resource[] = {
@@ -437,8 +468,8 @@ EXPORT_SYMBOL(s3c_device_spi0);
437 468
438static struct resource s3c_spi1_resource[] = { 469static struct resource s3c_spi1_resource[] = {
439 [0] = { 470 [0] = {
440 .start = S3C24XX_PA_SPI + 0x20, 471 .start = S3C24XX_PA_SPI + S3C2410_SPI1,
441 .end = S3C24XX_PA_SPI + 0x20 + 0x1f, 472 .end = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f,
442 .flags = IORESOURCE_MEM, 473 .flags = IORESOURCE_MEM,
443 }, 474 },
444 [1] = { 475 [1] = {
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 6f03c9370979..08d80f2f51f2 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1153,7 +1153,7 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1153 * 1153 *
1154 * hwcfg: the value for xxxSTCn register, 1154 * hwcfg: the value for xxxSTCn register,
1155 * bit 0: 0=increment pointer, 1=leave pointer 1155 * bit 0: 0=increment pointer, 1=leave pointer
1156 * bit 1: 0=soucre is AHB, 1=soucre is APB 1156 * bit 1: 0=source is AHB, 1=source is APB
1157 * 1157 *
1158 * devaddr: physical address of the source 1158 * devaddr: physical address of the source
1159*/ 1159*/
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c
index bd965f2feeca..cb0b3a4ccf1b 100644
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/plat-s3c24xx/pm-simtec.c
@@ -18,6 +18,7 @@
18#include <linux/list.h> 18#include <linux/list.h>
19#include <linux/timer.h> 19#include <linux/timer.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/sysdev.h>
21#include <linux/device.h> 22#include <linux/device.h>
22 23
23#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index c6b03f8ab260..5692eccdf4d1 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -555,7 +555,7 @@ static int s3c2410_pm_enter(suspend_state_t state)
555 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); 555 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
556 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); 556 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
557 557
558 /* call cpu specific preperation */ 558 /* call cpu specific preparation */
559 559
560 pm_cpu_prep(); 560 pm_cpu_prep();
561 561
diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c
index c5346d677315..698763b28ddd 100644
--- a/drivers/serial/serial_ks8695.c
+++ b/drivers/serial/serial_ks8695.c
@@ -301,11 +301,11 @@ static int ks8695uart_startup(struct uart_port *port)
301 301
302 retval = request_irq(KS8695_IRQ_UART_LINE_STATUS, ks8695uart_rx_chars, IRQF_DISABLED, "UART LineStatus", port); 302 retval = request_irq(KS8695_IRQ_UART_LINE_STATUS, ks8695uart_rx_chars, IRQF_DISABLED, "UART LineStatus", port);
303 if (retval) 303 if (retval)
304 return err_ls; 304 goto err_ls;
305 305
306 retval = request_irq(KS8695_IRQ_UART_MODEM_STATUS, ks8695uart_modem_status, IRQF_DISABLED, "UART ModemStatus", port); 306 retval = request_irq(KS8695_IRQ_UART_MODEM_STATUS, ks8695uart_modem_status, IRQF_DISABLED, "UART ModemStatus", port);
307 if (retval) 307 if (retval)
308 return err_ms; 308 goto err_ms;
309 309
310 return 0; 310 return 0;
311 311
diff --git a/include/asm-arm/arch-at91/at91_adc.h b/include/asm-arm/arch-at91/at91_adc.h
index 1ed66eaaf83a..6d71ea2637b1 100644
--- a/include/asm-arm/arch-at91/at91_adc.h
+++ b/include/asm-arm/arch-at91/at91_adc.h
@@ -55,7 +55,7 @@
55#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ 55#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
56#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ 56#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
57 57
58#define AT91_ADC_CHR(n) (0x30 + ((n) * 4) /* Channel Data Register N */ 58#define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
59#define AT91_ADC_DATA (0x3ff) 59#define AT91_ADC_DATA (0x3ff)
60 60
61#endif 61#endif
diff --git a/include/asm-arm/arch-integrator/smp.h b/include/asm-arm/arch-integrator/smp.h
deleted file mode 100644
index ab2c79bb9505..000000000000
--- a/include/asm-arm/arch-integrator/smp.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#ifndef ASMARM_ARCH_SMP_H
2#define ASMARM_ARCH_SMP_H
3
4
5#include <asm/hardware.h>
6#include <asm/io.h>
7
8#define hard_smp_processor_id() \
9 ({ \
10 unsigned int cpunum; \
11 __asm__("mrc p15, 0, %0, c0, c0, 5" \
12 : "=r" (cpunum)); \
13 cpunum &= 0x0F; \
14 })
15
16extern void secondary_scan_irqs(void);
17
18#endif
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
index c79cb1819913..3b49cd1c345c 100644
--- a/include/asm-arm/arch-s3c2410/irqs.h
+++ b/include/asm-arm/arch-s3c2410/irqs.h
@@ -124,7 +124,7 @@
124#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ 124#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */
125#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ 125#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
126#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ 126#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
127#define IRQ_S3C2443_SDI1 S3C2410_IRQ(20) /* IRQ_SDI */ 127#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
128#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ 128#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
129 129
130#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) 130#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/arch-s3c2410/regs-spi.h
index 3552280d1e8f..4a499a138256 100644
--- a/include/asm-arm/arch-s3c2410/regs-spi.h
+++ b/include/asm-arm/arch-s3c2410/regs-spi.h
@@ -12,6 +12,8 @@
12#ifndef __ASM_ARCH_REGS_SPI_H 12#ifndef __ASM_ARCH_REGS_SPI_H
13#define __ASM_ARCH_REGS_SPI_H 13#define __ASM_ARCH_REGS_SPI_H
14 14
15#define S3C2410_SPI1 (0x20)
16#define S3C2412_SPI1 (0x100)
15 17
16#define S3C2410_SPCON (0x00) 18#define S3C2410_SPCON (0x00)
17 19
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 8261ff9e7955..1d3caa42a386 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -259,9 +259,11 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
259#define BIOVEC_MERGEABLE(vec1, vec2) \ 259#define BIOVEC_MERGEABLE(vec1, vec2) \
260 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) 260 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
261 261
262#ifdef CONFIG_MMU
262#define ARCH_HAS_VALID_PHYS_ADDR_RANGE 263#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
263extern int valid_phys_addr_range(unsigned long addr, size_t size); 264extern int valid_phys_addr_range(unsigned long addr, size_t size);
264extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 265extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
266#endif
265 267
266/* 268/*
267 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 269 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h
index fe2a23b5627b..53099d4ee421 100644
--- a/include/asm-arm/mmu.h
+++ b/include/asm-arm/mmu.h
@@ -4,13 +4,13 @@
4#ifdef CONFIG_MMU 4#ifdef CONFIG_MMU
5 5
6typedef struct { 6typedef struct {
7#if __LINUX_ARM_ARCH__ >= 6 7#ifdef CONFIG_CPU_HAS_ASID
8 unsigned int id; 8 unsigned int id;
9#endif 9#endif
10 unsigned int kvm_seq; 10 unsigned int kvm_seq;
11} mm_context_t; 11} mm_context_t;
12 12
13#if __LINUX_ARM_ARCH__ >= 6 13#ifdef CONFIG_CPU_HAS_ASID
14#define ASID(mm) ((mm)->context.id & 255) 14#define ASID(mm) ((mm)->context.id & 255)
15#else 15#else
16#define ASID(mm) (0) 16#define ASID(mm) (0)
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index 4981ad419198..6913d02ca5d6 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -20,7 +20,7 @@
20 20
21void __check_kvm_seq(struct mm_struct *mm); 21void __check_kvm_seq(struct mm_struct *mm);
22 22
23#if __LINUX_ARM_ARCH__ >= 6 23#ifdef CONFIG_CPU_HAS_ASID
24 24
25/* 25/*
26 * On ARMv6, we have the following structure in the Context ID: 26 * On ARMv6, we have the following structure in the Context ID:
diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
index dddf485fc067..f9d6f0317bc1 100644
--- a/include/asm-arm/plat-s3c24xx/devs.h
+++ b/include/asm-arm/plat-s3c24xx/devs.h
@@ -29,6 +29,7 @@ extern struct platform_device s3c_device_iis;
29extern struct platform_device s3c_device_rtc; 29extern struct platform_device s3c_device_rtc;
30extern struct platform_device s3c_device_adc; 30extern struct platform_device s3c_device_adc;
31extern struct platform_device s3c_device_sdi; 31extern struct platform_device s3c_device_sdi;
32extern struct platform_device s3c_device_hsmmc;
32 33
33extern struct platform_device s3c_device_spi0; 34extern struct platform_device s3c_device_spi0;
34extern struct platform_device s3c_device_spi1; 35extern struct platform_device s3c_device_spi1;
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index c025ab47e4b9..250d7f145aca 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -373,6 +373,10 @@
373#define __NR_getcpu (__NR_SYSCALL_BASE+345) 373#define __NR_getcpu (__NR_SYSCALL_BASE+345)
374 /* 346 for epoll_pwait */ 374 /* 346 for epoll_pwait */
375#define __NR_kexec_load (__NR_SYSCALL_BASE+347) 375#define __NR_kexec_load (__NR_SYSCALL_BASE+347)
376#define __NR_utimensat (__NR_SYSCALL_BASE+348)
377#define __NR_signalfd (__NR_SYSCALL_BASE+349)
378#define __NR_timerfd (__NR_SYSCALL_BASE+350)
379#define __NR_eventfd (__NR_SYSCALL_BASE+351)
376 380
377/* 381/*
378 * The following SWIs are ARM private. 382 * The following SWIs are ARM private.
@@ -433,5 +437,11 @@
433 */ 437 */
434#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") 438#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
435 439
440/*
441 * Unimplemented (or alternatively implemented) syscalls
442 */
443#define __IGNORE_sync_file_range 1
444#define __IGNORE_fadvise64_64 1
445
436#endif /* __KERNEL__ */ 446#endif /* __KERNEL__ */
437#endif /* __ASM_ARM_UNISTD_H */ 447#endif /* __ASM_ARM_UNISTD_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-23 02:24:28 -0400