diff options
| -rw-r--r-- | drivers/spi/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/spi/xilinx_spi.c | 118 | ||||
| -rw-r--r-- | drivers/spi/xilinx_spi_of.c | 1 | ||||
| -rw-r--r-- | include/linux/spi/xilinx_spi.h | 6 |
4 files changed, 95 insertions, 34 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index b528271c72ef..4dda097c239e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig | |||
| @@ -243,7 +243,7 @@ config SPI_TXX9 | |||
| 243 | SPI driver for Toshiba TXx9 MIPS SoCs | 243 | SPI driver for Toshiba TXx9 MIPS SoCs |
| 244 | 244 | ||
| 245 | config SPI_XILINX | 245 | config SPI_XILINX |
| 246 | tristate "Xilinx SPI controller" | 246 | tristate "Xilinx SPI controller common module" |
| 247 | depends on HAS_IOMEM && EXPERIMENTAL | 247 | depends on HAS_IOMEM && EXPERIMENTAL |
| 248 | select SPI_BITBANG | 248 | select SPI_BITBANG |
| 249 | select SPI_XILINX_OF if (XILINX_VIRTEX || MICROBLAZE) | 249 | select SPI_XILINX_OF if (XILINX_VIRTEX || MICROBLAZE) |
| @@ -253,6 +253,8 @@ config SPI_XILINX | |||
| 253 | See the "OPB Serial Peripheral Interface (SPI) (v1.00e)" | 253 | See the "OPB Serial Peripheral Interface (SPI) (v1.00e)" |
| 254 | Product Specification document (DS464) for hardware details. | 254 | Product Specification document (DS464) for hardware details. |
| 255 | 255 | ||
| 256 | Or for the DS570, see "XPS Serial Peripheral Interface (SPI) (v2.00b)" | ||
| 257 | |||
| 256 | config SPI_XILINX_OF | 258 | config SPI_XILINX_OF |
| 257 | tristate "Xilinx SPI controller OF device" | 259 | tristate "Xilinx SPI controller OF device" |
| 258 | depends on SPI_XILINX && (XILINX_VIRTEX || MICROBLAZE) | 260 | depends on SPI_XILINX && (XILINX_VIRTEX || MICROBLAZE) |
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 135a3a5931a4..b927812822c1 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c | |||
| @@ -27,7 +27,7 @@ | |||
| 27 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) | 27 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) |
| 28 | * Product Specification", DS464 | 28 | * Product Specification", DS464 |
| 29 | */ | 29 | */ |
| 30 | #define XSPI_CR_OFFSET 0x60 /* 16-bit Control Register */ | 30 | #define XSPI_CR_OFFSET 0x60 /* Control Register */ |
| 31 | 31 | ||
| 32 | #define XSPI_CR_ENABLE 0x02 | 32 | #define XSPI_CR_ENABLE 0x02 |
| 33 | #define XSPI_CR_MASTER_MODE 0x04 | 33 | #define XSPI_CR_MASTER_MODE 0x04 |
| @@ -38,8 +38,9 @@ | |||
| 38 | #define XSPI_CR_RXFIFO_RESET 0x40 | 38 | #define XSPI_CR_RXFIFO_RESET 0x40 |
| 39 | #define XSPI_CR_MANUAL_SSELECT 0x80 | 39 | #define XSPI_CR_MANUAL_SSELECT 0x80 |
| 40 | #define XSPI_CR_TRANS_INHIBIT 0x100 | 40 | #define XSPI_CR_TRANS_INHIBIT 0x100 |
| 41 | #define XSPI_CR_LSB_FIRST 0x200 | ||
| 41 | 42 | ||
| 42 | #define XSPI_SR_OFFSET 0x64 /* 8-bit Status Register */ | 43 | #define XSPI_SR_OFFSET 0x64 /* Status Register */ |
| 43 | 44 | ||
| 44 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ | 45 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ |
| 45 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ | 46 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ |
| @@ -47,8 +48,8 @@ | |||
| 47 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ | 48 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ |
| 48 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ | 49 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ |
| 49 | 50 | ||
| 50 | #define XSPI_TXD_OFFSET 0x68 /* 8-bit Data Transmit Register */ | 51 | #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ |
| 51 | #define XSPI_RXD_OFFSET 0x6c /* 8-bit Data Receive Register */ | 52 | #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ |
| 52 | 53 | ||
| 53 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ | 54 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ |
| 54 | 55 | ||
| @@ -68,6 +69,7 @@ | |||
| 68 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ | 69 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ |
| 69 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ | 70 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ |
| 70 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ | 71 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ |
| 72 | #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ | ||
| 71 | 73 | ||
| 72 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ | 74 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ |
| 73 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ | 75 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ |
| @@ -81,15 +83,61 @@ struct xilinx_spi { | |||
| 81 | 83 | ||
| 82 | u32 irq; | 84 | u32 irq; |
| 83 | 85 | ||
| 84 | u32 speed_hz; /* SCK has a fixed frequency of speed_hz Hz */ | ||
| 85 | |||
| 86 | u8 *rx_ptr; /* pointer in the Tx buffer */ | 86 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
| 87 | const u8 *tx_ptr; /* pointer in the Rx buffer */ | 87 | const u8 *tx_ptr; /* pointer in the Rx buffer */ |
| 88 | int remaining_bytes; /* the number of bytes left to transfer */ | 88 | int remaining_bytes; /* the number of bytes left to transfer */ |
| 89 | u8 bits_per_word; | ||
| 89 | unsigned int (*read_fn) (void __iomem *); | 90 | unsigned int (*read_fn) (void __iomem *); |
| 90 | void (*write_fn) (u32, void __iomem *); | 91 | void (*write_fn) (u32, void __iomem *); |
| 92 | void (*tx_fn) (struct xilinx_spi *); | ||
| 93 | void (*rx_fn) (struct xilinx_spi *); | ||
| 91 | }; | 94 | }; |
| 92 | 95 | ||
| 96 | static void xspi_tx8(struct xilinx_spi *xspi) | ||
| 97 | { | ||
| 98 | xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET); | ||
| 99 | xspi->tx_ptr++; | ||
| 100 | } | ||
| 101 | |||
| 102 | static void xspi_tx16(struct xilinx_spi *xspi) | ||
| 103 | { | ||
| 104 | xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | ||
| 105 | xspi->tx_ptr += 2; | ||
| 106 | } | ||
| 107 | |||
| 108 | static void xspi_tx32(struct xilinx_spi *xspi) | ||
| 109 | { | ||
| 110 | xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | ||
| 111 | xspi->tx_ptr += 4; | ||
| 112 | } | ||
| 113 | |||
| 114 | static void xspi_rx8(struct xilinx_spi *xspi) | ||
| 115 | { | ||
| 116 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | ||
| 117 | if (xspi->rx_ptr) { | ||
| 118 | *xspi->rx_ptr = data & 0xff; | ||
| 119 | xspi->rx_ptr++; | ||
| 120 | } | ||
| 121 | } | ||
| 122 | |||
| 123 | static void xspi_rx16(struct xilinx_spi *xspi) | ||
| 124 | { | ||
| 125 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | ||
| 126 | if (xspi->rx_ptr) { | ||
| 127 | *(u16 *)(xspi->rx_ptr) = data & 0xffff; | ||
| 128 | xspi->rx_ptr += 2; | ||
| 129 | } | ||
| 130 | } | ||
| 131 | |||
| 132 | static void xspi_rx32(struct xilinx_spi *xspi) | ||
| 133 | { | ||
| 134 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | ||
| 135 | if (xspi->rx_ptr) { | ||
| 136 | *(u32 *)(xspi->rx_ptr) = data; | ||
| 137 | xspi->rx_ptr += 4; | ||
| 138 | } | ||
| 139 | } | ||
| 140 | |||
| 93 | static void xspi_init_hw(struct xilinx_spi *xspi) | 141 | static void xspi_init_hw(struct xilinx_spi *xspi) |
| 94 | { | 142 | { |
| 95 | void __iomem *regs_base = xspi->regs; | 143 | void __iomem *regs_base = xspi->regs; |
| @@ -107,8 +155,8 @@ static void xspi_init_hw(struct xilinx_spi *xspi) | |||
| 107 | /* Disable the transmitter, enable Manual Slave Select Assertion, | 155 | /* Disable the transmitter, enable Manual Slave Select Assertion, |
| 108 | * put SPI controller into master mode, and enable it */ | 156 | * put SPI controller into master mode, and enable it */ |
| 109 | xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT | | 157 | xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT | |
| 110 | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE, | 158 | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | |
| 111 | regs_base + XSPI_CR_OFFSET); | 159 | XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET); |
| 112 | } | 160 | } |
| 113 | 161 | ||
| 114 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) | 162 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) |
| @@ -141,18 +189,20 @@ static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) | |||
| 141 | 189 | ||
| 142 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a | 190 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a |
| 143 | * custom txrx_bufs(). We have nothing to setup here as the SPI IP block | 191 | * custom txrx_bufs(). We have nothing to setup here as the SPI IP block |
| 144 | * supports just 8 bits per word, and SPI clock can't be changed in software. | 192 | * supports 8 or 16 bits per word which cannot be changed in software. |
| 145 | * Check for 8 bits per word. Chip select delay calculations could be | 193 | * SPI clock can't be changed in software either. |
| 194 | * Check for correct bits per word. Chip select delay calculations could be | ||
| 146 | * added here as soon as bitbang_work() can be made aware of the delay value. | 195 | * added here as soon as bitbang_work() can be made aware of the delay value. |
| 147 | */ | 196 | */ |
| 148 | static int xilinx_spi_setup_transfer(struct spi_device *spi, | 197 | static int xilinx_spi_setup_transfer(struct spi_device *spi, |
| 149 | struct spi_transfer *t) | 198 | struct spi_transfer *t) |
| 150 | { | 199 | { |
| 200 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | ||
| 151 | u8 bits_per_word; | 201 | u8 bits_per_word; |
| 152 | 202 | ||
| 153 | bits_per_word = (t && t->bits_per_word) | 203 | bits_per_word = (t && t->bits_per_word) |
| 154 | ? t->bits_per_word : spi->bits_per_word; | 204 | ? t->bits_per_word : spi->bits_per_word; |
| 155 | if (bits_per_word != 8) { | 205 | if (bits_per_word != xspi->bits_per_word) { |
| 156 | dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", | 206 | dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", |
| 157 | __func__, bits_per_word); | 207 | __func__, bits_per_word); |
| 158 | return -EINVAL; | 208 | return -EINVAL; |
| @@ -163,17 +213,16 @@ static int xilinx_spi_setup_transfer(struct spi_device *spi, | |||
| 163 | 213 | ||
| 164 | static int xilinx_spi_setup(struct spi_device *spi) | 214 | static int xilinx_spi_setup(struct spi_device *spi) |
| 165 | { | 215 | { |
| 166 | struct spi_bitbang *bitbang; | 216 | /* always return 0, we can not check the number of bits. |
| 167 | struct xilinx_spi *xspi; | 217 | * There are cases when SPI setup is called before any driver is |
| 168 | int retval; | 218 | * there, in that case the SPI core defaults to 8 bits, which we |
| 169 | 219 | * do not support in some cases. But if we return an error, the | |
| 170 | xspi = spi_master_get_devdata(spi->master); | 220 | * SPI device would not be registered and no driver can get hold of it |
| 171 | bitbang = &xspi->bitbang; | 221 | * When the driver is there, it will call SPI setup again with the |
| 172 | 222 | * correct number of bits per transfer. | |
| 173 | retval = xilinx_spi_setup_transfer(spi, NULL); | 223 | * If a driver setups with the wrong bit number, it will fail when |
| 174 | if (retval < 0) | 224 | * it tries to do a transfer |
| 175 | return retval; | 225 | */ |
| 176 | |||
| 177 | return 0; | 226 | return 0; |
| 178 | } | 227 | } |
| 179 | 228 | ||
| @@ -185,11 +234,10 @@ static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) | |||
| 185 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | 234 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
| 186 | while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { | 235 | while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { |
| 187 | if (xspi->tx_ptr) | 236 | if (xspi->tx_ptr) |
| 188 | xspi->write_fn(*xspi->tx_ptr++, | 237 | xspi->tx_fn(xspi); |
| 189 | xspi->regs + XSPI_TXD_OFFSET); | ||
| 190 | else | 238 | else |
| 191 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | 239 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); |
| 192 | xspi->remaining_bytes--; | 240 | xspi->remaining_bytes -= xspi->bits_per_word / 8; |
| 193 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | 241 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
| 194 | } | 242 | } |
| 195 | } | 243 | } |
| @@ -260,12 +308,7 @@ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) | |||
| 260 | /* Read out all the data from the Rx FIFO */ | 308 | /* Read out all the data from the Rx FIFO */ |
| 261 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | 309 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
| 262 | while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { | 310 | while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { |
| 263 | u8 data; | 311 | xspi->rx_fn(xspi); |
| 264 | |||
| 265 | data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | ||
| 266 | if (xspi->rx_ptr) { | ||
| 267 | *xspi->rx_ptr++ = data; | ||
| 268 | } | ||
| 269 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | 312 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
| 270 | } | 313 | } |
| 271 | 314 | ||
| @@ -337,6 +380,19 @@ struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem, | |||
| 337 | xspi->read_fn = ioread32be; | 380 | xspi->read_fn = ioread32be; |
| 338 | xspi->write_fn = iowrite32be; | 381 | xspi->write_fn = iowrite32be; |
| 339 | } | 382 | } |
| 383 | xspi->bits_per_word = pdata->bits_per_word; | ||
| 384 | if (xspi->bits_per_word == 8) { | ||
| 385 | xspi->tx_fn = xspi_tx8; | ||
| 386 | xspi->rx_fn = xspi_rx8; | ||
| 387 | } else if (xspi->bits_per_word == 16) { | ||
| 388 | xspi->tx_fn = xspi_tx16; | ||
| 389 | xspi->rx_fn = xspi_rx16; | ||
| 390 | } else if (xspi->bits_per_word == 32) { | ||
| 391 | xspi->tx_fn = xspi_tx32; | ||
| 392 | xspi->rx_fn = xspi_rx32; | ||
| 393 | } else | ||
| 394 | goto unmap_io; | ||
| 395 | |||
| 340 | 396 | ||
| 341 | /* SPI controller initializations */ | 397 | /* SPI controller initializations */ |
| 342 | xspi_init_hw(xspi); | 398 | xspi_init_hw(xspi); |
diff --git a/drivers/spi/xilinx_spi_of.c b/drivers/spi/xilinx_spi_of.c index 151aa13494bd..71dc3adc0495 100644 --- a/drivers/spi/xilinx_spi_of.c +++ b/drivers/spi/xilinx_spi_of.c | |||
| @@ -72,6 +72,7 @@ static int __devinit xilinx_spi_of_probe(struct of_device *ofdev, | |||
| 72 | return -EINVAL; | 72 | return -EINVAL; |
| 73 | } | 73 | } |
| 74 | pdata->num_chipselect = *prop; | 74 | pdata->num_chipselect = *prop; |
| 75 | pdata->bits_per_word = 8; | ||
| 75 | master = xilinx_spi_init(&ofdev->dev, &r_mem, r_irq.start, -1); | 76 | master = xilinx_spi_init(&ofdev->dev, &r_mem, r_irq.start, -1); |
| 76 | if (!master) | 77 | if (!master) |
| 77 | return -ENODEV; | 78 | return -ENODEV; |
diff --git a/include/linux/spi/xilinx_spi.h b/include/linux/spi/xilinx_spi.h index a705ad85eebe..6f17278810b0 100644 --- a/include/linux/spi/xilinx_spi.h +++ b/include/linux/spi/xilinx_spi.h | |||
| @@ -3,14 +3,16 @@ | |||
| 3 | 3 | ||
| 4 | /** | 4 | /** |
| 5 | * struct xspi_platform_data - Platform data of the Xilinx SPI driver | 5 | * struct xspi_platform_data - Platform data of the Xilinx SPI driver |
| 6 | * @num_chipselect: Number of chip select by the IP | 6 | * @num_chipselect: Number of chip select by the IP. |
| 7 | * @little_endian If registers should be accessed little endian or not | 7 | * @little_endian: If registers should be accessed little endian or not. |
| 8 | * @bits_per_word: Number of bits per word. | ||
| 8 | * @devices: Devices to add when the driver is probed. | 9 | * @devices: Devices to add when the driver is probed. |
| 9 | * @num_devices: Number of devices in the devices array. | 10 | * @num_devices: Number of devices in the devices array. |
| 10 | */ | 11 | */ |
| 11 | struct xspi_platform_data { | 12 | struct xspi_platform_data { |
| 12 | u16 num_chipselect; | 13 | u16 num_chipselect; |
| 13 | bool little_endian; | 14 | bool little_endian; |
| 15 | u8 bits_per_word; | ||
| 14 | struct spi_board_info *devices; | 16 | struct spi_board_info *devices; |
| 15 | u8 num_devices; | 17 | u8 num_devices; |
| 16 | }; | 18 | }; |
