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-rw-r--r--arch/arm/mach-omap2/clock24xx.h4
-rw-r--r--drivers/i2c/busses/i2c-omap.c420
-rw-r--r--drivers/i2c/busses/i2c-s3c2410.c185
3 files changed, 408 insertions, 201 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index ff6cd14d254d..ad6d98d177c5 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -2321,7 +2321,7 @@ static struct clk i2c2_fck = {
2321}; 2321};
2322 2322
2323static struct clk i2chs2_fck = { 2323static struct clk i2chs2_fck = {
2324 .name = "i2chs_fck", 2324 .name = "i2c_fck",
2325 .id = 2, 2325 .id = 2,
2326 .parent = &func_96m_ck, 2326 .parent = &func_96m_ck,
2327 .flags = CLOCK_IN_OMAP243X, 2327 .flags = CLOCK_IN_OMAP243X,
@@ -2354,7 +2354,7 @@ static struct clk i2c1_fck = {
2354}; 2354};
2355 2355
2356static struct clk i2chs1_fck = { 2356static struct clk i2chs1_fck = {
2357 .name = "i2chs_fck", 2357 .name = "i2c_fck",
2358 .id = 1, 2358 .id = 1,
2359 .parent = &func_96m_ck, 2359 .parent = &func_96m_ck,
2360 .flags = CLOCK_IN_OMAP243X, 2360 .flags = CLOCK_IN_OMAP243X,
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 608038d64f81..be8ee2cac8bb 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -2,13 +2,16 @@
2 * TI OMAP I2C master mode driver 2 * TI OMAP I2C master mode driver
3 * 3 *
4 * Copyright (C) 2003 MontaVista Software, Inc. 4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2004 Texas Instruments.
6 *
7 * Updated to work with multiple I2C interfaces on 24xx by
8 * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
9 * Copyright (C) 2005 Nokia Corporation 5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
10 * 7 *
11 * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com> 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
12 * 15 *
13 * This program is free software; you can redistribute it and/or modify 16 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by 17 * it under the terms of the GNU General Public License as published by
@@ -33,8 +36,14 @@
33#include <linux/completion.h> 36#include <linux/completion.h>
34#include <linux/platform_device.h> 37#include <linux/platform_device.h>
35#include <linux/clk.h> 38#include <linux/clk.h>
39#include <linux/io.h>
40
41/* I2C controller revisions */
42#define OMAP_I2C_REV_2 0x20
36 43
37#include <asm/io.h> 44/* I2C controller revisions present on specific hardware */
45#define OMAP_I2C_REV_ON_2430 0x36
46#define OMAP_I2C_REV_ON_3430 0x3C
38 47
39/* timeout waiting for the controller to respond */ 48/* timeout waiting for the controller to respond */
40#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 49#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
@@ -43,6 +52,8 @@
43#define OMAP_I2C_IE_REG 0x04 52#define OMAP_I2C_IE_REG 0x04
44#define OMAP_I2C_STAT_REG 0x08 53#define OMAP_I2C_STAT_REG 0x08
45#define OMAP_I2C_IV_REG 0x0c 54#define OMAP_I2C_IV_REG 0x0c
55/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56#define OMAP_I2C_WE_REG 0x0c
46#define OMAP_I2C_SYSS_REG 0x10 57#define OMAP_I2C_SYSS_REG 0x10
47#define OMAP_I2C_BUF_REG 0x14 58#define OMAP_I2C_BUF_REG 0x14
48#define OMAP_I2C_CNT_REG 0x18 59#define OMAP_I2C_CNT_REG 0x18
@@ -55,8 +66,11 @@
55#define OMAP_I2C_SCLL_REG 0x34 66#define OMAP_I2C_SCLL_REG 0x34
56#define OMAP_I2C_SCLH_REG 0x38 67#define OMAP_I2C_SCLH_REG 0x38
57#define OMAP_I2C_SYSTEST_REG 0x3c 68#define OMAP_I2C_SYSTEST_REG 0x3c
69#define OMAP_I2C_BUFSTAT_REG 0x40
58 70
59/* I2C Interrupt Enable Register (OMAP_I2C_IE): */ 71/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
72#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
73#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
60#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ 74#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
61#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ 75#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
62#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ 76#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
@@ -64,7 +78,8 @@
64#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ 78#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
65 79
66/* I2C Status Register (OMAP_I2C_STAT): */ 80/* I2C Status Register (OMAP_I2C_STAT): */
67#define OMAP_I2C_STAT_SBD (1 << 15) /* Single byte data */ 81#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
82#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
68#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ 83#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
69#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 84#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
70#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 85#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
@@ -76,13 +91,34 @@
76#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ 91#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
77#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ 92#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
78 93
94/* I2C WE wakeup enable register */
95#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
96#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
97#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
98#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
99#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
100#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
101#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
102#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
103#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
104#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
105
106#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
111
79/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ 112/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
80#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ 113#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
114#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
81#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ 115#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
116#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
82 117
83/* I2C Configuration Register (OMAP_I2C_CON): */ 118/* I2C Configuration Register (OMAP_I2C_CON): */
84#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ 119#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
85#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ 120#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
121#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
86#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ 122#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
87#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ 123#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
88#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ 124#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
@@ -91,6 +127,10 @@
91#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ 127#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
92#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ 128#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
93 129
130/* I2C SCL time value when Master */
131#define OMAP_I2C_SCLL_HSSCLL 8
132#define OMAP_I2C_SCLH_HSSCLH 8
133
94/* I2C System Test Register (OMAP_I2C_SYSTEST): */ 134/* I2C System Test Register (OMAP_I2C_SYSTEST): */
95#ifdef DEBUG 135#ifdef DEBUG
96#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ 136#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
@@ -103,17 +143,19 @@
103#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ 143#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
104#endif 144#endif
105 145
106/* I2C System Status register (OMAP_I2C_SYSS): */ 146/* OCP_SYSSTATUS bit definitions */
107#define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */ 147#define SYSS_RESETDONE_MASK (1 << 0)
148
149/* OCP_SYSCONFIG bit definitions */
150#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
151#define SYSC_SIDLEMODE_MASK (0x3 << 3)
152#define SYSC_ENAWAKEUP_MASK (1 << 2)
153#define SYSC_SOFTRESET_MASK (1 << 1)
154#define SYSC_AUTOIDLE_MASK (1 << 0)
108 155
109/* I2C System Configuration Register (OMAP_I2C_SYSC): */ 156#define SYSC_IDLEMODE_SMART 0x2
110#define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */ 157#define SYSC_CLOCKACTIVITY_FCLK 0x2
111 158
112/* REVISIT: Use platform_data instead of module parameters */
113/* Fast Mode = 400 kHz, Standard = 100 kHz */
114static int clock = 100; /* Default: 100 kHz */
115module_param(clock, int, 0);
116MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 400=fast mode (default == 100)");
117 159
118struct omap_i2c_dev { 160struct omap_i2c_dev {
119 struct device *dev; 161 struct device *dev;
@@ -123,11 +165,17 @@ struct omap_i2c_dev {
123 struct clk *fclk; /* Functional clock */ 165 struct clk *fclk; /* Functional clock */
124 struct completion cmd_complete; 166 struct completion cmd_complete;
125 struct resource *ioarea; 167 struct resource *ioarea;
168 u32 speed; /* Speed of bus in Khz */
126 u16 cmd_err; 169 u16 cmd_err;
127 u8 *buf; 170 u8 *buf;
128 size_t buf_len; 171 size_t buf_len;
129 struct i2c_adapter adapter; 172 struct i2c_adapter adapter;
130 unsigned rev1:1; 173 u8 fifo_size; /* use as flag and value
174 * fifo_size==0 implies no fifo
175 * if set, should be trsh+1
176 */
177 u8 rev;
178 unsigned b_hw:1; /* bad h/w fixes */
131 unsigned idle:1; 179 unsigned idle:1;
132 u16 iestate; /* Saved interrupt register */ 180 u16 iestate; /* Saved interrupt register */
133}; 181};
@@ -143,9 +191,9 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
143 return __raw_readw(i2c_dev->base + reg); 191 return __raw_readw(i2c_dev->base + reg);
144} 192}
145 193
146static int omap_i2c_get_clocks(struct omap_i2c_dev *dev) 194static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
147{ 195{
148 if (cpu_is_omap16xx() || cpu_is_omap24xx()) { 196 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
149 dev->iclk = clk_get(dev->dev, "i2c_ick"); 197 dev->iclk = clk_get(dev->dev, "i2c_ick");
150 if (IS_ERR(dev->iclk)) { 198 if (IS_ERR(dev->iclk)) {
151 dev->iclk = NULL; 199 dev->iclk = NULL;
@@ -178,25 +226,33 @@ static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
178 226
179static void omap_i2c_unidle(struct omap_i2c_dev *dev) 227static void omap_i2c_unidle(struct omap_i2c_dev *dev)
180{ 228{
229 WARN_ON(!dev->idle);
230
181 if (dev->iclk != NULL) 231 if (dev->iclk != NULL)
182 clk_enable(dev->iclk); 232 clk_enable(dev->iclk);
183 clk_enable(dev->fclk); 233 clk_enable(dev->fclk);
234 dev->idle = 0;
184 if (dev->iestate) 235 if (dev->iestate)
185 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); 236 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
186 dev->idle = 0;
187} 237}
188 238
189static void omap_i2c_idle(struct omap_i2c_dev *dev) 239static void omap_i2c_idle(struct omap_i2c_dev *dev)
190{ 240{
191 u16 iv; 241 u16 iv;
192 242
193 dev->idle = 1; 243 WARN_ON(dev->idle);
244
194 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 245 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
195 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); 246 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
196 if (dev->rev1) 247 if (dev->rev < OMAP_I2C_REV_2) {
197 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */ 248 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
198 else 249 } else {
199 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate); 250 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
251
252 /* Flush posted write before the dev->idle store occurs */
253 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
254 }
255 dev->idle = 1;
200 clk_disable(dev->fclk); 256 clk_disable(dev->fclk);
201 if (dev->iclk != NULL) 257 if (dev->iclk != NULL)
202 clk_disable(dev->iclk); 258 clk_disable(dev->iclk);
@@ -204,18 +260,20 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev)
204 260
205static int omap_i2c_init(struct omap_i2c_dev *dev) 261static int omap_i2c_init(struct omap_i2c_dev *dev)
206{ 262{
207 u16 psc = 0; 263 u16 psc = 0, scll = 0, sclh = 0;
264 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
208 unsigned long fclk_rate = 12000000; 265 unsigned long fclk_rate = 12000000;
209 unsigned long timeout; 266 unsigned long timeout;
267 unsigned long internal_clk = 0;
210 268
211 if (!dev->rev1) { 269 if (dev->rev >= OMAP_I2C_REV_2) {
212 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST); 270 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
213 /* For some reason we need to set the EN bit before the 271 /* For some reason we need to set the EN bit before the
214 * reset done bit gets set. */ 272 * reset done bit gets set. */
215 timeout = jiffies + OMAP_I2C_TIMEOUT; 273 timeout = jiffies + OMAP_I2C_TIMEOUT;
216 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 274 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
217 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & 275 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
218 OMAP_I2C_SYSS_RDONE)) { 276 SYSS_RESETDONE_MASK)) {
219 if (time_after(jiffies, timeout)) { 277 if (time_after(jiffies, timeout)) {
220 dev_warn(dev->dev, "timeout waiting " 278 dev_warn(dev->dev, "timeout waiting "
221 "for controller reset\n"); 279 "for controller reset\n");
@@ -223,6 +281,33 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
223 } 281 }
224 msleep(1); 282 msleep(1);
225 } 283 }
284
285 /* SYSC register is cleared by the reset; rewrite it */
286 if (dev->rev == OMAP_I2C_REV_ON_2430) {
287
288 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
289 SYSC_AUTOIDLE_MASK);
290
291 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
292 u32 v;
293
294 v = SYSC_AUTOIDLE_MASK;
295 v |= SYSC_ENAWAKEUP_MASK;
296 v |= (SYSC_IDLEMODE_SMART <<
297 __ffs(SYSC_SIDLEMODE_MASK));
298 v |= (SYSC_CLOCKACTIVITY_FCLK <<
299 __ffs(SYSC_CLOCKACTIVITY_MASK));
300
301 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v);
302 /*
303 * Enabling all wakup sources to stop I2C freezing on
304 * WFI instruction.
305 * REVISIT: Some wkup sources might not be needed.
306 */
307 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
308 OMAP_I2C_WE_ALL);
309
310 }
226 } 311 }
227 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 312 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
228 313
@@ -249,27 +334,65 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
249 psc = fclk_rate / 12000000; 334 psc = fclk_rate / 12000000;
250 } 335 }
251 336
337 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
338
339 /* HSI2C controller internal clk rate should be 19.2 Mhz */
340 internal_clk = 19200;
341 fclk_rate = clk_get_rate(dev->fclk) / 1000;
342
343 /* Compute prescaler divisor */
344 psc = fclk_rate / internal_clk;
345 psc = psc - 1;
346
347 /* If configured for High Speed */
348 if (dev->speed > 400) {
349 /* For first phase of HS mode */
350 fsscll = internal_clk / (400 * 2) - 6;
351 fssclh = internal_clk / (400 * 2) - 6;
352
353 /* For second phase of HS mode */
354 hsscll = fclk_rate / (dev->speed * 2) - 6;
355 hssclh = fclk_rate / (dev->speed * 2) - 6;
356 } else {
357 /* To handle F/S modes */
358 fsscll = internal_clk / (dev->speed * 2) - 6;
359 fssclh = internal_clk / (dev->speed * 2) - 6;
360 }
361 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
362 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
363 } else {
364 /* Program desired operating rate */
365 fclk_rate /= (psc + 1) * 1000;
366 if (psc > 2)
367 psc = 2;
368 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
369 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
370 }
371
252 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ 372 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
253 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); 373 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
254 374
255 /* Program desired operating rate */ 375 /* SCL low and high time values */
256 fclk_rate /= (psc + 1) * 1000; 376 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
257 if (psc > 2) 377 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
258 psc = 2;
259 378
260 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, 379 if (dev->fifo_size)
261 fclk_rate / (clock * 2) - 7 + psc); 380 /* Note: setup required fifo size - 1 */
262 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, 381 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
263 fclk_rate / (clock * 2) - 7 + psc); 382 (dev->fifo_size - 1) << 8 | /* RTRSH */
383 OMAP_I2C_BUF_RXFIF_CLR |
384 (dev->fifo_size - 1) | /* XTRSH */
385 OMAP_I2C_BUF_TXFIF_CLR);
264 386
265 /* Take the I2C module out of reset: */ 387 /* Take the I2C module out of reset: */
266 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 388 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
267 389
268 /* Enable interrupts */ 390 /* Enable interrupts */
269 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 391 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
270 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | 392 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
271 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | 393 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
272 OMAP_I2C_IE_AL)); 394 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
395 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
273 return 0; 396 return 0;
274} 397}
275 398
@@ -316,20 +439,59 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
316 439
317 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); 440 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
318 441
442 /* Clear the FIFO Buffers */
443 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
444 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
445 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
446
319 init_completion(&dev->cmd_complete); 447 init_completion(&dev->cmd_complete);
320 dev->cmd_err = 0; 448 dev->cmd_err = 0;
321 449
322 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; 450 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
451
452 /* High speed configuration */
453 if (dev->speed > 400)
454 w |= OMAP_I2C_CON_OPMODE_HS;
455
323 if (msg->flags & I2C_M_TEN) 456 if (msg->flags & I2C_M_TEN)
324 w |= OMAP_I2C_CON_XA; 457 w |= OMAP_I2C_CON_XA;
325 if (!(msg->flags & I2C_M_RD)) 458 if (!(msg->flags & I2C_M_RD))
326 w |= OMAP_I2C_CON_TRX; 459 w |= OMAP_I2C_CON_TRX;
327 if (stop) 460
461 if (!dev->b_hw && stop)
328 w |= OMAP_I2C_CON_STP; 462 w |= OMAP_I2C_CON_STP;
463
329 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 464 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
330 465
331 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete, 466 /*
332 OMAP_I2C_TIMEOUT); 467 * Don't write stt and stp together on some hardware.
468 */
469 if (dev->b_hw && stop) {
470 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
471 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
472 while (con & OMAP_I2C_CON_STT) {
473 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
474
475 /* Let the user know if i2c is in a bad state */
476 if (time_after(jiffies, delay)) {
477 dev_err(dev->dev, "controller timed out "
478 "waiting for start condition to finish\n");
479 return -ETIMEDOUT;
480 }
481 cpu_relax();
482 }
483
484 w |= OMAP_I2C_CON_STP;
485 w &= ~OMAP_I2C_CON_STT;
486 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
487 }
488
489 /*
490 * REVISIT: We should abort the transfer on signals, but the bus goes
491 * into arbitration and we're currently unable to recover from it.
492 */
493 r = wait_for_completion_timeout(&dev->cmd_complete,
494 OMAP_I2C_TIMEOUT);
333 dev->buf_len = 0; 495 dev->buf_len = 0;
334 if (r < 0) 496 if (r < 0)
335 return r; 497 return r;
@@ -376,7 +538,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
376 538
377 omap_i2c_unidle(dev); 539 omap_i2c_unidle(dev);
378 540
379 if ((r = omap_i2c_wait_for_bb(dev)) < 0) 541 r = omap_i2c_wait_for_bb(dev);
542 if (r < 0)
380 goto out; 543 goto out;
381 544
382 for (i = 0; i < num; i++) { 545 for (i = 0; i < num; i++) {
@@ -411,6 +574,9 @@ omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
411 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); 574 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
412} 575}
413 576
577/* rev1 devices are apparently only on some 15xx */
578#ifdef CONFIG_ARCH_OMAP15XX
579
414static irqreturn_t 580static irqreturn_t
415omap_i2c_rev1_isr(int this_irq, void *dev_id) 581omap_i2c_rev1_isr(int this_irq, void *dev_id)
416{ 582{
@@ -465,6 +631,9 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
465 631
466 return IRQ_HANDLED; 632 return IRQ_HANDLED;
467} 633}
634#else
635#define omap_i2c_rev1_isr NULL
636#endif
468 637
469static irqreturn_t 638static irqreturn_t
470omap_i2c_isr(int this_irq, void *dev_id) 639omap_i2c_isr(int this_irq, void *dev_id)
@@ -472,7 +641,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
472 struct omap_i2c_dev *dev = dev_id; 641 struct omap_i2c_dev *dev = dev_id;
473 u16 bits; 642 u16 bits;
474 u16 stat, w; 643 u16 stat, w;
475 int count = 0; 644 int err, count = 0;
476 645
477 if (dev->idle) 646 if (dev->idle)
478 return IRQ_NONE; 647 return IRQ_NONE;
@@ -487,39 +656,96 @@ omap_i2c_isr(int this_irq, void *dev_id)
487 656
488 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); 657 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
489 658
490 if (stat & OMAP_I2C_STAT_ARDY) { 659 err = 0;
491 omap_i2c_complete_cmd(dev, 0); 660 if (stat & OMAP_I2C_STAT_NACK) {
492 continue; 661 err |= OMAP_I2C_STAT_NACK;
662 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
663 OMAP_I2C_CON_STP);
493 } 664 }
494 if (stat & OMAP_I2C_STAT_RRDY) { 665 if (stat & OMAP_I2C_STAT_AL) {
495 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); 666 dev_err(dev->dev, "Arbitration lost\n");
496 if (dev->buf_len) { 667 err |= OMAP_I2C_STAT_AL;
497 *dev->buf++ = w; 668 }
498 dev->buf_len--; 669 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
670 OMAP_I2C_STAT_AL))
671 omap_i2c_complete_cmd(dev, err);
672 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
673 u8 num_bytes = 1;
674 if (dev->fifo_size) {
675 if (stat & OMAP_I2C_STAT_RRDY)
676 num_bytes = dev->fifo_size;
677 else
678 num_bytes = omap_i2c_read_reg(dev,
679 OMAP_I2C_BUFSTAT_REG);
680 }
681 while (num_bytes) {
682 num_bytes--;
683 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
499 if (dev->buf_len) { 684 if (dev->buf_len) {
500 *dev->buf++ = w >> 8; 685 *dev->buf++ = w;
501 dev->buf_len--; 686 dev->buf_len--;
687 /* Data reg from 2430 is 8 bit wide */
688 if (!cpu_is_omap2430() &&
689 !cpu_is_omap34xx()) {
690 if (dev->buf_len) {
691 *dev->buf++ = w >> 8;
692 dev->buf_len--;
693 }
694 }
695 } else {
696 if (stat & OMAP_I2C_STAT_RRDY)
697 dev_err(dev->dev,
698 "RRDY IRQ while no data"
699 " requested\n");
700 if (stat & OMAP_I2C_STAT_RDR)
701 dev_err(dev->dev,
702 "RDR IRQ while no data"
703 " requested\n");
704 break;
502 } 705 }
503 } else 706 }
504 dev_err(dev->dev, "RRDY IRQ while no data " 707 omap_i2c_ack_stat(dev,
505 "requested\n"); 708 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
506 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
507 continue; 709 continue;
508 } 710 }
509 if (stat & OMAP_I2C_STAT_XRDY) { 711 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
510 w = 0; 712 u8 num_bytes = 1;
511 if (dev->buf_len) { 713 if (dev->fifo_size) {
512 w = *dev->buf++; 714 if (stat & OMAP_I2C_STAT_XRDY)
513 dev->buf_len--; 715 num_bytes = dev->fifo_size;
716 else
717 num_bytes = omap_i2c_read_reg(dev,
718 OMAP_I2C_BUFSTAT_REG);
719 }
720 while (num_bytes) {
721 num_bytes--;
722 w = 0;
514 if (dev->buf_len) { 723 if (dev->buf_len) {
515 w |= *dev->buf++ << 8; 724 w = *dev->buf++;
516 dev->buf_len--; 725 dev->buf_len--;
726 /* Data reg from 2430 is 8 bit wide */
727 if (!cpu_is_omap2430() &&
728 !cpu_is_omap34xx()) {
729 if (dev->buf_len) {
730 w |= *dev->buf++ << 8;
731 dev->buf_len--;
732 }
733 }
734 } else {
735 if (stat & OMAP_I2C_STAT_XRDY)
736 dev_err(dev->dev,
737 "XRDY IRQ while no "
738 "data to send\n");
739 if (stat & OMAP_I2C_STAT_XDR)
740 dev_err(dev->dev,
741 "XDR IRQ while no "
742 "data to send\n");
743 break;
517 } 744 }
518 } else 745 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
519 dev_err(dev->dev, "XRDY IRQ while no " 746 }
520 "data to send\n"); 747 omap_i2c_ack_stat(dev,
521 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); 748 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
522 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
523 continue; 749 continue;
524 } 750 }
525 if (stat & OMAP_I2C_STAT_ROVR) { 751 if (stat & OMAP_I2C_STAT_ROVR) {
@@ -527,18 +753,9 @@ omap_i2c_isr(int this_irq, void *dev_id)
527 dev->cmd_err |= OMAP_I2C_STAT_ROVR; 753 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
528 } 754 }
529 if (stat & OMAP_I2C_STAT_XUDF) { 755 if (stat & OMAP_I2C_STAT_XUDF) {
530 dev_err(dev->dev, "Transmit overflow\n"); 756 dev_err(dev->dev, "Transmit underflow\n");
531 dev->cmd_err |= OMAP_I2C_STAT_XUDF; 757 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
532 } 758 }
533 if (stat & OMAP_I2C_STAT_NACK) {
534 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
535 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
536 OMAP_I2C_CON_STP);
537 }
538 if (stat & OMAP_I2C_STAT_AL) {
539 dev_err(dev->dev, "Arbitration lost\n");
540 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
541 }
542 } 759 }
543 760
544 return count ? IRQ_HANDLED : IRQ_NONE; 761 return count ? IRQ_HANDLED : IRQ_NONE;
@@ -549,13 +766,15 @@ static const struct i2c_algorithm omap_i2c_algo = {
549 .functionality = omap_i2c_func, 766 .functionality = omap_i2c_func,
550}; 767};
551 768
552static int 769static int __init
553omap_i2c_probe(struct platform_device *pdev) 770omap_i2c_probe(struct platform_device *pdev)
554{ 771{
555 struct omap_i2c_dev *dev; 772 struct omap_i2c_dev *dev;
556 struct i2c_adapter *adap; 773 struct i2c_adapter *adap;
557 struct resource *mem, *irq, *ioarea; 774 struct resource *mem, *irq, *ioarea;
775 irq_handler_t isr;
558 int r; 776 int r;
777 u32 speed = 0;
559 778
560 /* NOTE: driver uses the static register mapping */ 779 /* NOTE: driver uses the static register mapping */
561 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 780 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -576,17 +795,19 @@ omap_i2c_probe(struct platform_device *pdev)
576 return -EBUSY; 795 return -EBUSY;
577 } 796 }
578 797
579 if (clock > 200)
580 clock = 400; /* Fast mode */
581 else
582 clock = 100; /* Standard mode */
583
584 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL); 798 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
585 if (!dev) { 799 if (!dev) {
586 r = -ENOMEM; 800 r = -ENOMEM;
587 goto err_release_region; 801 goto err_release_region;
588 } 802 }
589 803
804 if (pdev->dev.platform_data != NULL)
805 speed = *(u32 *)pdev->dev.platform_data;
806 else
807 speed = 100; /* Defualt speed */
808
809 dev->speed = speed;
810 dev->idle = 1;
590 dev->dev = &pdev->dev; 811 dev->dev = &pdev->dev;
591 dev->irq = irq->start; 812 dev->irq = irq->start;
592 dev->base = ioremap(mem->start, mem->end - mem->start + 1); 813 dev->base = ioremap(mem->start, mem->end - mem->start + 1);
@@ -602,22 +823,39 @@ omap_i2c_probe(struct platform_device *pdev)
602 823
603 omap_i2c_unidle(dev); 824 omap_i2c_unidle(dev);
604 825
605 if (cpu_is_omap15xx()) 826 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
606 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20; 827
828 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
829 u16 s;
830
831 /* Set up the fifo size - Get total size */
832 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
833 dev->fifo_size = 0x8 << s;
834
835 /*
836 * Set up notification threshold as half the total available
837 * size. This is to ensure that we can handle the status on int
838 * call back latencies.
839 */
840 dev->fifo_size = (dev->fifo_size / 2);
841 dev->b_hw = 1; /* Enable hardware fixes */
842 }
607 843
608 /* reset ASAP, clearing any IRQs */ 844 /* reset ASAP, clearing any IRQs */
609 omap_i2c_init(dev); 845 omap_i2c_init(dev);
610 846
611 r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr, 847 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
612 0, pdev->name, dev); 848 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
613 849
614 if (r) { 850 if (r) {
615 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); 851 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
616 goto err_unuse_clocks; 852 goto err_unuse_clocks;
617 } 853 }
618 r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; 854
619 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", 855 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
620 pdev->id, r >> 4, r & 0xf, clock); 856 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
857
858 omap_i2c_idle(dev);
621 859
622 adap = &dev->adapter; 860 adap = &dev->adapter;
623 i2c_set_adapdata(adap, dev); 861 i2c_set_adapdata(adap, dev);
@@ -635,8 +873,6 @@ omap_i2c_probe(struct platform_device *pdev)
635 goto err_free_irq; 873 goto err_free_irq;
636 } 874 }
637 875
638 omap_i2c_idle(dev);
639
640 return 0; 876 return 0;
641 877
642err_free_irq: 878err_free_irq:
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index c39079f9c73f..f69f91ffb469 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -35,11 +35,9 @@
35#include <linux/clk.h> 35#include <linux/clk.h>
36#include <linux/cpufreq.h> 36#include <linux/cpufreq.h>
37 37
38#include <mach/hardware.h>
39#include <asm/irq.h> 38#include <asm/irq.h>
40#include <asm/io.h> 39#include <asm/io.h>
41 40
42#include <mach/regs-gpio.h>
43#include <plat/regs-iic.h> 41#include <plat/regs-iic.h>
44#include <plat/iic.h> 42#include <plat/iic.h>
45 43
@@ -64,6 +62,7 @@ struct s3c24xx_i2c {
64 unsigned int msg_ptr; 62 unsigned int msg_ptr;
65 63
66 unsigned int tx_setup; 64 unsigned int tx_setup;
65 unsigned int irq;
67 66
68 enum s3c24xx_i2c_state state; 67 enum s3c24xx_i2c_state state;
69 unsigned long clkrate; 68 unsigned long clkrate;
@@ -71,7 +70,6 @@ struct s3c24xx_i2c {
71 void __iomem *regs; 70 void __iomem *regs;
72 struct clk *clk; 71 struct clk *clk;
73 struct device *dev; 72 struct device *dev;
74 struct resource *irq;
75 struct resource *ioarea; 73 struct resource *ioarea;
76 struct i2c_adapter adap; 74 struct i2c_adapter adap;
77 75
@@ -80,16 +78,7 @@ struct s3c24xx_i2c {
80#endif 78#endif
81}; 79};
82 80
83/* default platform data to use if not supplied in the platform_device 81/* default platform data removed, dev should always carry data. */
84*/
85
86static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
87 .flags = 0,
88 .slave_addr = 0x10,
89 .bus_freq = 100*1000,
90 .max_freq = 400*1000,
91 .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
92};
93 82
94/* s3c24xx_i2c_is2440() 83/* s3c24xx_i2c_is2440()
95 * 84 *
@@ -103,21 +92,6 @@ static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
103 return !strcmp(pdev->name, "s3c2440-i2c"); 92 return !strcmp(pdev->name, "s3c2440-i2c");
104} 93}
105 94
106
107/* s3c24xx_i2c_get_platformdata
108 *
109 * get the platform data associated with the given device, or return
110 * the default if there is none
111*/
112
113static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev)
114{
115 if (dev->platform_data != NULL)
116 return (struct s3c2410_platform_i2c *)dev->platform_data;
117
118 return &s3c24xx_i2c_default_platform;
119}
120
121/* s3c24xx_i2c_master_complete 95/* s3c24xx_i2c_master_complete
122 * 96 *
123 * complete the message and wake up the caller, using the given return code, 97 * complete the message and wake up the caller, using the given return code,
@@ -130,7 +104,7 @@ static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
130 104
131 i2c->msg_ptr = 0; 105 i2c->msg_ptr = 0;
132 i2c->msg = NULL; 106 i2c->msg = NULL;
133 i2c->msg_idx ++; 107 i2c->msg_idx++;
134 i2c->msg_num = 0; 108 i2c->msg_num = 0;
135 if (ret) 109 if (ret)
136 i2c->msg_idx = ret; 110 i2c->msg_idx = ret;
@@ -141,19 +115,17 @@ static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
141static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) 115static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
142{ 116{
143 unsigned long tmp; 117 unsigned long tmp;
144 118
145 tmp = readl(i2c->regs + S3C2410_IICCON); 119 tmp = readl(i2c->regs + S3C2410_IICCON);
146 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 120 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
147
148} 121}
149 122
150static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) 123static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
151{ 124{
152 unsigned long tmp; 125 unsigned long tmp;
153 126
154 tmp = readl(i2c->regs + S3C2410_IICCON); 127 tmp = readl(i2c->regs + S3C2410_IICCON);
155 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 128 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
156
157} 129}
158 130
159/* irq enable/disable functions */ 131/* irq enable/disable functions */
@@ -161,7 +133,7 @@ static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
161static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) 133static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
162{ 134{
163 unsigned long tmp; 135 unsigned long tmp;
164 136
165 tmp = readl(i2c->regs + S3C2410_IICCON); 137 tmp = readl(i2c->regs + S3C2410_IICCON);
166 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 138 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
167} 139}
@@ -169,7 +141,7 @@ static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
169static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) 141static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
170{ 142{
171 unsigned long tmp; 143 unsigned long tmp;
172 144
173 tmp = readl(i2c->regs + S3C2410_IICCON); 145 tmp = readl(i2c->regs + S3C2410_IICCON);
174 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 146 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
175} 147}
@@ -177,10 +149,10 @@ static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
177 149
178/* s3c24xx_i2c_message_start 150/* s3c24xx_i2c_message_start
179 * 151 *
180 * put the start of a message onto the bus 152 * put the start of a message onto the bus
181*/ 153*/
182 154
183static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 155static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
184 struct i2c_msg *msg) 156 struct i2c_msg *msg)
185{ 157{
186 unsigned int addr = (msg->addr & 0x7f) << 1; 158 unsigned int addr = (msg->addr & 0x7f) << 1;
@@ -199,15 +171,15 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
199 if (msg->flags & I2C_M_REV_DIR_ADDR) 171 if (msg->flags & I2C_M_REV_DIR_ADDR)
200 addr ^= 1; 172 addr ^= 1;
201 173
202 // todo - check for wether ack wanted or not 174 /* todo - check for wether ack wanted or not */
203 s3c24xx_i2c_enable_ack(i2c); 175 s3c24xx_i2c_enable_ack(i2c);
204 176
205 iiccon = readl(i2c->regs + S3C2410_IICCON); 177 iiccon = readl(i2c->regs + S3C2410_IICCON);
206 writel(stat, i2c->regs + S3C2410_IICSTAT); 178 writel(stat, i2c->regs + S3C2410_IICSTAT);
207 179
208 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); 180 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
209 writeb(addr, i2c->regs + S3C2410_IICDS); 181 writeb(addr, i2c->regs + S3C2410_IICDS);
210 182
211 /* delay here to ensure the data byte has gotten onto the bus 183 /* delay here to ensure the data byte has gotten onto the bus
212 * before the transaction is started */ 184 * before the transaction is started */
213 185
@@ -215,8 +187,8 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
215 187
216 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); 188 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
217 writel(iiccon, i2c->regs + S3C2410_IICCON); 189 writel(iiccon, i2c->regs + S3C2410_IICCON);
218 190
219 stat |= S3C2410_IICSTAT_START; 191 stat |= S3C2410_IICSTAT_START;
220 writel(stat, i2c->regs + S3C2410_IICSTAT); 192 writel(stat, i2c->regs + S3C2410_IICSTAT);
221} 193}
222 194
@@ -227,11 +199,11 @@ static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
227 dev_dbg(i2c->dev, "STOP\n"); 199 dev_dbg(i2c->dev, "STOP\n");
228 200
229 /* stop the transfer */ 201 /* stop the transfer */
230 iicstat &= ~ S3C2410_IICSTAT_START; 202 iicstat &= ~S3C2410_IICSTAT_START;
231 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 203 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
232 204
233 i2c->state = STATE_STOP; 205 i2c->state = STATE_STOP;
234 206
235 s3c24xx_i2c_master_complete(i2c, ret); 207 s3c24xx_i2c_master_complete(i2c, ret);
236 s3c24xx_i2c_disable_irq(i2c); 208 s3c24xx_i2c_disable_irq(i2c);
237} 209}
@@ -241,7 +213,7 @@ static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
241 213
242/* is_lastmsg() 214/* is_lastmsg()
243 * 215 *
244 * returns TRUE if the current message is the last in the set 216 * returns TRUE if the current message is the last in the set
245*/ 217*/
246 218
247static inline int is_lastmsg(struct s3c24xx_i2c *i2c) 219static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
@@ -289,14 +261,14 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
289 261
290 case STATE_STOP: 262 case STATE_STOP:
291 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); 263 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
292 s3c24xx_i2c_disable_irq(i2c); 264 s3c24xx_i2c_disable_irq(i2c);
293 goto out_ack; 265 goto out_ack;
294 266
295 case STATE_START: 267 case STATE_START:
296 /* last thing we did was send a start condition on the 268 /* last thing we did was send a start condition on the
297 * bus, or started a new i2c message 269 * bus, or started a new i2c message
298 */ 270 */
299 271
300 if (iicstat & S3C2410_IICSTAT_LASTBIT && 272 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
301 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 273 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
302 /* ack was not received... */ 274 /* ack was not received... */
@@ -322,7 +294,7 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
322 if (i2c->state == STATE_READ) 294 if (i2c->state == STATE_READ)
323 goto prepare_read; 295 goto prepare_read;
324 296
325 /* fall through to the write state, as we will need to 297 /* fall through to the write state, as we will need to
326 * send a byte as well */ 298 * send a byte as well */
327 299
328 case STATE_WRITE: 300 case STATE_WRITE:
@@ -339,7 +311,7 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
339 } 311 }
340 } 312 }
341 313
342 retry_write: 314 retry_write:
343 315
344 if (!is_msgend(i2c)) { 316 if (!is_msgend(i2c)) {
345 byte = i2c->msg->buf[i2c->msg_ptr++]; 317 byte = i2c->msg->buf[i2c->msg_ptr++];
@@ -359,9 +331,9 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
359 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 331 dev_dbg(i2c->dev, "WRITE: Next Message\n");
360 332
361 i2c->msg_ptr = 0; 333 i2c->msg_ptr = 0;
362 i2c->msg_idx ++; 334 i2c->msg_idx++;
363 i2c->msg++; 335 i2c->msg++;
364 336
365 /* check to see if we need to do another message */ 337 /* check to see if we need to do another message */
366 if (i2c->msg->flags & I2C_M_NOSTART) { 338 if (i2c->msg->flags & I2C_M_NOSTART) {
367 339
@@ -375,7 +347,6 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
375 347
376 goto retry_write; 348 goto retry_write;
377 } else { 349 } else {
378
379 /* send the new start */ 350 /* send the new start */
380 s3c24xx_i2c_message_start(i2c, i2c->msg); 351 s3c24xx_i2c_message_start(i2c, i2c->msg);
381 i2c->state = STATE_START; 352 i2c->state = STATE_START;
@@ -389,7 +360,7 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
389 break; 360 break;
390 361
391 case STATE_READ: 362 case STATE_READ:
392 /* we have a byte of data in the data register, do 363 /* we have a byte of data in the data register, do
393 * something with it, and then work out wether we are 364 * something with it, and then work out wether we are
394 * going to do any more read/write 365 * going to do any more read/write
395 */ 366 */
@@ -397,13 +368,13 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
397 byte = readb(i2c->regs + S3C2410_IICDS); 368 byte = readb(i2c->regs + S3C2410_IICDS);
398 i2c->msg->buf[i2c->msg_ptr++] = byte; 369 i2c->msg->buf[i2c->msg_ptr++] = byte;
399 370
400 prepare_read: 371 prepare_read:
401 if (is_msglast(i2c)) { 372 if (is_msglast(i2c)) {
402 /* last byte of buffer */ 373 /* last byte of buffer */
403 374
404 if (is_lastmsg(i2c)) 375 if (is_lastmsg(i2c))
405 s3c24xx_i2c_disable_ack(i2c); 376 s3c24xx_i2c_disable_ack(i2c);
406 377
407 } else if (is_msgend(i2c)) { 378 } else if (is_msgend(i2c)) {
408 /* ok, we've read the entire buffer, see if there 379 /* ok, we've read the entire buffer, see if there
409 * is anything else we need to do */ 380 * is anything else we need to do */
@@ -429,7 +400,7 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
429 /* acknowlegde the IRQ and get back on with the work */ 400 /* acknowlegde the IRQ and get back on with the work */
430 401
431 out_ack: 402 out_ack:
432 tmp = readl(i2c->regs + S3C2410_IICCON); 403 tmp = readl(i2c->regs + S3C2410_IICCON);
433 tmp &= ~S3C2410_IICCON_IRQPEND; 404 tmp &= ~S3C2410_IICCON_IRQPEND;
434 writel(tmp, i2c->regs + S3C2410_IICCON); 405 writel(tmp, i2c->regs + S3C2410_IICCON);
435 out: 406 out:
@@ -450,19 +421,19 @@ static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
450 status = readl(i2c->regs + S3C2410_IICSTAT); 421 status = readl(i2c->regs + S3C2410_IICSTAT);
451 422
452 if (status & S3C2410_IICSTAT_ARBITR) { 423 if (status & S3C2410_IICSTAT_ARBITR) {
453 // deal with arbitration loss 424 /* deal with arbitration loss */
454 dev_err(i2c->dev, "deal with arbitration loss\n"); 425 dev_err(i2c->dev, "deal with arbitration loss\n");
455 } 426 }
456 427
457 if (i2c->state == STATE_IDLE) { 428 if (i2c->state == STATE_IDLE) {
458 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); 429 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
459 430
460 tmp = readl(i2c->regs + S3C2410_IICCON); 431 tmp = readl(i2c->regs + S3C2410_IICCON);
461 tmp &= ~S3C2410_IICCON_IRQPEND; 432 tmp &= ~S3C2410_IICCON_IRQPEND;
462 writel(tmp, i2c->regs + S3C2410_IICCON); 433 writel(tmp, i2c->regs + S3C2410_IICCON);
463 goto out; 434 goto out;
464 } 435 }
465 436
466 /* pretty much this leaves us with the fact that we've 437 /* pretty much this leaves us with the fact that we've
467 * transmitted or received whatever byte we last sent */ 438 * transmitted or received whatever byte we last sent */
468 439
@@ -485,16 +456,13 @@ static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
485 456
486 while (timeout-- > 0) { 457 while (timeout-- > 0) {
487 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 458 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
488 459
489 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) 460 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
490 return 0; 461 return 0;
491 462
492 msleep(1); 463 msleep(1);
493 } 464 }
494 465
495 dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
496 __raw_readl(S3C2410_GPEDAT));
497
498 return -ETIMEDOUT; 466 return -ETIMEDOUT;
499} 467}
500 468
@@ -503,7 +471,8 @@ static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
503 * this starts an i2c transfer 471 * this starts an i2c transfer
504*/ 472*/
505 473
506static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num) 474static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
475 struct i2c_msg *msgs, int num)
507{ 476{
508 unsigned long timeout; 477 unsigned long timeout;
509 int ret; 478 int ret;
@@ -529,12 +498,12 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int
529 s3c24xx_i2c_enable_irq(i2c); 498 s3c24xx_i2c_enable_irq(i2c);
530 s3c24xx_i2c_message_start(i2c, msgs); 499 s3c24xx_i2c_message_start(i2c, msgs);
531 spin_unlock_irq(&i2c->lock); 500 spin_unlock_irq(&i2c->lock);
532 501
533 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 502 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
534 503
535 ret = i2c->msg_idx; 504 ret = i2c->msg_idx;
536 505
537 /* having these next two as dev_err() makes life very 506 /* having these next two as dev_err() makes life very
538 * noisy when doing an i2cdetect */ 507 * noisy when doing an i2cdetect */
539 508
540 if (timeout == 0) 509 if (timeout == 0)
@@ -591,19 +560,6 @@ static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
591 .functionality = s3c24xx_i2c_func, 560 .functionality = s3c24xx_i2c_func,
592}; 561};
593 562
594static struct s3c24xx_i2c s3c24xx_i2c = {
595 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
596 .wait = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
597 .tx_setup = 50,
598 .adap = {
599 .name = "s3c2410-i2c",
600 .owner = THIS_MODULE,
601 .algo = &s3c24xx_i2c_algorithm,
602 .retries = 2,
603 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
604 },
605};
606
607/* s3c24xx_i2c_calcdivisor 563/* s3c24xx_i2c_calcdivisor
608 * 564 *
609 * return the divisor settings for a given frequency 565 * return the divisor settings for a given frequency
@@ -643,7 +599,7 @@ static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
643{ 599{
644 int diff = freq - wanted; 600 int diff = freq - wanted;
645 601
646 return (diff >= -2 && diff <= 2); 602 return diff >= -2 && diff <= 2;
647} 603}
648 604
649/* s3c24xx_i2c_clockrate 605/* s3c24xx_i2c_clockrate
@@ -655,7 +611,7 @@ static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
655 611
656static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) 612static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
657{ 613{
658 struct s3c2410_platform_i2c *pdata; 614 struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
659 unsigned long clkin = clk_get_rate(i2c->clk); 615 unsigned long clkin = clk_get_rate(i2c->clk);
660 unsigned int divs, div1; 616 unsigned int divs, div1;
661 u32 iiccon; 617 u32 iiccon;
@@ -663,10 +619,8 @@ static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
663 int start, end; 619 int start, end;
664 620
665 i2c->clkrate = clkin; 621 i2c->clkrate = clkin;
666
667 pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
668 clkin /= 1000; /* clkin now in KHz */ 622 clkin /= 1000; /* clkin now in KHz */
669 623
670 dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n", 624 dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
671 pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq); 625 pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
672 626
@@ -774,7 +728,7 @@ static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
774 728
775/* s3c24xx_i2c_init 729/* s3c24xx_i2c_init
776 * 730 *
777 * initialise the controller, set the IO lines and frequency 731 * initialise the controller, set the IO lines and frequency
778*/ 732*/
779 733
780static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) 734static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
@@ -785,15 +739,15 @@ static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
785 739
786 /* get the plafrom data */ 740 /* get the plafrom data */
787 741
788 pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent); 742 pdata = i2c->dev->platform_data;
789 743
790 /* inititalise the gpio */ 744 /* inititalise the gpio */
791 745
792 s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA); 746 if (pdata->cfg_gpio)
793 s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL); 747 pdata->cfg_gpio(to_platform_device(i2c->dev));
794 748
795 /* write slave address */ 749 /* write slave address */
796 750
797 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 751 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
798 752
799 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); 753 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
@@ -831,12 +785,32 @@ static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
831 785
832static int s3c24xx_i2c_probe(struct platform_device *pdev) 786static int s3c24xx_i2c_probe(struct platform_device *pdev)
833{ 787{
834 struct s3c24xx_i2c *i2c = &s3c24xx_i2c; 788 struct s3c24xx_i2c *i2c;
835 struct s3c2410_platform_i2c *pdata; 789 struct s3c2410_platform_i2c *pdata;
836 struct resource *res; 790 struct resource *res;
837 int ret; 791 int ret;
838 792
839 pdata = s3c24xx_i2c_get_platformdata(&pdev->dev); 793 pdata = pdev->dev.platform_data;
794 if (!pdata) {
795 dev_err(&pdev->dev, "no platform data\n");
796 return -EINVAL;
797 }
798
799 i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
800 if (!i2c) {
801 dev_err(&pdev->dev, "no memory for state\n");
802 return -ENOMEM;
803 }
804
805 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
806 i2c->adap.owner = THIS_MODULE;
807 i2c->adap.algo = &s3c24xx_i2c_algorithm;
808 i2c->adap.retries = 2;
809 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
810 i2c->tx_setup = 50;
811
812 spin_lock_init(&i2c->lock);
813 init_waitqueue_head(&i2c->wait);
840 814
841 /* find the clock and enable it */ 815 /* find the clock and enable it */
842 816
@@ -878,7 +852,8 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
878 goto err_ioarea; 852 goto err_ioarea;
879 } 853 }
880 854
881 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res); 855 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
856 i2c->regs, i2c->ioarea, res);
882 857
883 /* setup info block for the i2c core */ 858 /* setup info block for the i2c core */
884 859
@@ -892,29 +867,23 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
892 goto err_iomap; 867 goto err_iomap;
893 868
894 /* find the IRQ for this unit (note, this relies on the init call to 869 /* find the IRQ for this unit (note, this relies on the init call to
895 * ensure no current IRQs pending 870 * ensure no current IRQs pending
896 */ 871 */
897 872
898 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 873 i2c->irq = ret = platform_get_irq(pdev, 0);
899 if (res == NULL) { 874 if (ret <= 0) {
900 dev_err(&pdev->dev, "cannot find IRQ\n"); 875 dev_err(&pdev->dev, "cannot find IRQ\n");
901 ret = -ENOENT;
902 goto err_iomap; 876 goto err_iomap;
903 } 877 }
904 878
905 ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED, 879 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
906 pdev->name, i2c); 880 dev_name(&pdev->dev), i2c);
907 881
908 if (ret != 0) { 882 if (ret != 0) {
909 dev_err(&pdev->dev, "cannot claim IRQ\n"); 883 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
910 goto err_iomap; 884 goto err_iomap;
911 } 885 }
912 886
913 i2c->irq = res;
914
915 dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
916 (unsigned long)res->start);
917
918 ret = s3c24xx_i2c_register_cpufreq(i2c); 887 ret = s3c24xx_i2c_register_cpufreq(i2c);
919 if (ret < 0) { 888 if (ret < 0) {
920 dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); 889 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
@@ -944,7 +913,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
944 s3c24xx_i2c_deregister_cpufreq(i2c); 913 s3c24xx_i2c_deregister_cpufreq(i2c);
945 914
946 err_irq: 915 err_irq:
947 free_irq(i2c->irq->start, i2c); 916 free_irq(i2c->irq, i2c);
948 917
949 err_iomap: 918 err_iomap:
950 iounmap(i2c->regs); 919 iounmap(i2c->regs);
@@ -958,6 +927,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
958 clk_put(i2c->clk); 927 clk_put(i2c->clk);
959 928
960 err_noclk: 929 err_noclk:
930 kfree(i2c);
961 return ret; 931 return ret;
962} 932}
963 933
@@ -973,7 +943,7 @@ static int s3c24xx_i2c_remove(struct platform_device *pdev)
973 s3c24xx_i2c_deregister_cpufreq(i2c); 943 s3c24xx_i2c_deregister_cpufreq(i2c);
974 944
975 i2c_del_adapter(&i2c->adap); 945 i2c_del_adapter(&i2c->adap);
976 free_irq(i2c->irq->start, i2c); 946 free_irq(i2c->irq, i2c);
977 947
978 clk_disable(i2c->clk); 948 clk_disable(i2c->clk);
979 clk_put(i2c->clk); 949 clk_put(i2c->clk);
@@ -982,6 +952,7 @@ static int s3c24xx_i2c_remove(struct platform_device *pdev)
982 952
983 release_resource(i2c->ioarea); 953 release_resource(i2c->ioarea);
984 kfree(i2c->ioarea); 954 kfree(i2c->ioarea);
955 kfree(i2c);
985 956
986 return 0; 957 return 0;
987} 958}
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-13 06:08:21 -0500