aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/ABI/testing/sysfs-class-regulator55
-rw-r--r--Documentation/power/regulator/machine.txt140
-rw-r--r--Documentation/power/regulator/regulator.txt8
-rw-r--r--MAINTAINERS3
-rw-r--r--drivers/mfd/Kconfig38
-rw-r--r--drivers/mfd/Makefile5
-rw-r--r--drivers/mfd/wm8350-core.c1273
-rw-r--r--drivers/mfd/wm8350-gpio.c222
-rw-r--r--drivers/mfd/wm8350-i2c.c120
-rw-r--r--drivers/mfd/wm8350-regmap.c1347
-rw-r--r--drivers/mfd/wm8400-core.c455
-rw-r--r--drivers/regulator/Kconfig24
-rw-r--r--drivers/regulator/Makefile3
-rw-r--r--drivers/regulator/bq24022.c21
-rw-r--r--drivers/regulator/core.c508
-rw-r--r--drivers/regulator/da903x.c513
-rw-r--r--drivers/regulator/wm8350-regulator.c1431
-rw-r--r--drivers/regulator/wm8400-regulator.c368
-rw-r--r--include/linux/mfd/wm8350/audio.h598
-rw-r--r--include/linux/mfd/wm8350/comparator.h167
-rw-r--r--include/linux/mfd/wm8350/core.h631
-rw-r--r--include/linux/mfd/wm8350/gpio.h342
-rw-r--r--include/linux/mfd/wm8350/pmic.h741
-rw-r--r--include/linux/mfd/wm8350/rtc.h266
-rw-r--r--include/linux/mfd/wm8350/supply.h111
-rw-r--r--include/linux/mfd/wm8350/wdt.h28
-rw-r--r--include/linux/mfd/wm8400-audio.h1186
-rw-r--r--include/linux/mfd/wm8400-private.h936
-rw-r--r--include/linux/mfd/wm8400.h40
-rw-r--r--include/linux/regulator/driver.h10
-rw-r--r--include/linux/regulator/machine.h30
31 files changed, 11267 insertions, 353 deletions
diff --git a/Documentation/ABI/testing/sysfs-class-regulator b/Documentation/ABI/testing/sysfs-class-regulator
index 79a4a75b2d2c..3731f6f29bcb 100644
--- a/Documentation/ABI/testing/sysfs-class-regulator
+++ b/Documentation/ABI/testing/sysfs-class-regulator
@@ -1,7 +1,7 @@
1What: /sys/class/regulator/.../state 1What: /sys/class/regulator/.../state
2Date: April 2008 2Date: April 2008
3KernelVersion: 2.6.26 3KernelVersion: 2.6.26
4Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 4Contact: Liam Girdwood <lrg@slimlogic.co.uk>
5Description: 5Description:
6 Each regulator directory will contain a field called 6 Each regulator directory will contain a field called
7 state. This holds the regulator output state. 7 state. This holds the regulator output state.
@@ -27,7 +27,7 @@ Description:
27What: /sys/class/regulator/.../type 27What: /sys/class/regulator/.../type
28Date: April 2008 28Date: April 2008
29KernelVersion: 2.6.26 29KernelVersion: 2.6.26
30Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 30Contact: Liam Girdwood <lrg@slimlogic.co.uk>
31Description: 31Description:
32 Each regulator directory will contain a field called 32 Each regulator directory will contain a field called
33 type. This holds the regulator type. 33 type. This holds the regulator type.
@@ -51,7 +51,7 @@ Description:
51What: /sys/class/regulator/.../microvolts 51What: /sys/class/regulator/.../microvolts
52Date: April 2008 52Date: April 2008
53KernelVersion: 2.6.26 53KernelVersion: 2.6.26
54Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 54Contact: Liam Girdwood <lrg@slimlogic.co.uk>
55Description: 55Description:
56 Each regulator directory will contain a field called 56 Each regulator directory will contain a field called
57 microvolts. This holds the regulator output voltage setting 57 microvolts. This holds the regulator output voltage setting
@@ -65,7 +65,7 @@ Description:
65What: /sys/class/regulator/.../microamps 65What: /sys/class/regulator/.../microamps
66Date: April 2008 66Date: April 2008
67KernelVersion: 2.6.26 67KernelVersion: 2.6.26
68Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 68Contact: Liam Girdwood <lrg@slimlogic.co.uk>
69Description: 69Description:
70 Each regulator directory will contain a field called 70 Each regulator directory will contain a field called
71 microamps. This holds the regulator output current limit 71 microamps. This holds the regulator output current limit
@@ -79,7 +79,7 @@ Description:
79What: /sys/class/regulator/.../opmode 79What: /sys/class/regulator/.../opmode
80Date: April 2008 80Date: April 2008
81KernelVersion: 2.6.26 81KernelVersion: 2.6.26
82Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 82Contact: Liam Girdwood <lrg@slimlogic.co.uk>
83Description: 83Description:
84 Each regulator directory will contain a field called 84 Each regulator directory will contain a field called
85 opmode. This holds the regulator operating mode setting. 85 opmode. This holds the regulator operating mode setting.
@@ -102,7 +102,7 @@ Description:
102What: /sys/class/regulator/.../min_microvolts 102What: /sys/class/regulator/.../min_microvolts
103Date: April 2008 103Date: April 2008
104KernelVersion: 2.6.26 104KernelVersion: 2.6.26
105Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 105Contact: Liam Girdwood <lrg@slimlogic.co.uk>
106Description: 106Description:
107 Each regulator directory will contain a field called 107 Each regulator directory will contain a field called
108 min_microvolts. This holds the minimum safe working regulator 108 min_microvolts. This holds the minimum safe working regulator
@@ -116,7 +116,7 @@ Description:
116What: /sys/class/regulator/.../max_microvolts 116What: /sys/class/regulator/.../max_microvolts
117Date: April 2008 117Date: April 2008
118KernelVersion: 2.6.26 118KernelVersion: 2.6.26
119Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 119Contact: Liam Girdwood <lrg@slimlogic.co.uk>
120Description: 120Description:
121 Each regulator directory will contain a field called 121 Each regulator directory will contain a field called
122 max_microvolts. This holds the maximum safe working regulator 122 max_microvolts. This holds the maximum safe working regulator
@@ -130,7 +130,7 @@ Description:
130What: /sys/class/regulator/.../min_microamps 130What: /sys/class/regulator/.../min_microamps
131Date: April 2008 131Date: April 2008
132KernelVersion: 2.6.26 132KernelVersion: 2.6.26
133Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 133Contact: Liam Girdwood <lrg@slimlogic.co.uk>
134Description: 134Description:
135 Each regulator directory will contain a field called 135 Each regulator directory will contain a field called
136 min_microamps. This holds the minimum safe working regulator 136 min_microamps. This holds the minimum safe working regulator
@@ -145,7 +145,7 @@ Description:
145What: /sys/class/regulator/.../max_microamps 145What: /sys/class/regulator/.../max_microamps
146Date: April 2008 146Date: April 2008
147KernelVersion: 2.6.26 147KernelVersion: 2.6.26
148Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 148Contact: Liam Girdwood <lrg@slimlogic.co.uk>
149Description: 149Description:
150 Each regulator directory will contain a field called 150 Each regulator directory will contain a field called
151 max_microamps. This holds the maximum safe working regulator 151 max_microamps. This holds the maximum safe working regulator
@@ -157,10 +157,23 @@ Description:
157 platform code. 157 platform code.
158 158
159 159
160What: /sys/class/regulator/.../name
161Date: October 2008
162KernelVersion: 2.6.28
163Contact: Liam Girdwood <lrg@slimlogic.co.uk>
164Description:
165 Each regulator directory will contain a field called
166 name. This holds a string identifying the regulator for
167 display purposes.
168
169 NOTE: this will be empty if no suitable name is provided
170 by platform or regulator drivers.
171
172
160What: /sys/class/regulator/.../num_users 173What: /sys/class/regulator/.../num_users
161Date: April 2008 174Date: April 2008
162KernelVersion: 2.6.26 175KernelVersion: 2.6.26
163Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 176Contact: Liam Girdwood <lrg@slimlogic.co.uk>
164Description: 177Description:
165 Each regulator directory will contain a field called 178 Each regulator directory will contain a field called
166 num_users. This holds the number of consumer devices that 179 num_users. This holds the number of consumer devices that
@@ -170,7 +183,7 @@ Description:
170What: /sys/class/regulator/.../requested_microamps 183What: /sys/class/regulator/.../requested_microamps
171Date: April 2008 184Date: April 2008
172KernelVersion: 2.6.26 185KernelVersion: 2.6.26
173Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 186Contact: Liam Girdwood <lrg@slimlogic.co.uk>
174Description: 187Description:
175 Each regulator directory will contain a field called 188 Each regulator directory will contain a field called
176 requested_microamps. This holds the total requested load 189 requested_microamps. This holds the total requested load
@@ -181,7 +194,7 @@ Description:
181What: /sys/class/regulator/.../parent 194What: /sys/class/regulator/.../parent
182Date: April 2008 195Date: April 2008
183KernelVersion: 2.6.26 196KernelVersion: 2.6.26
184Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 197Contact: Liam Girdwood <lrg@slimlogic.co.uk>
185Description: 198Description:
186 Some regulator directories will contain a link called parent. 199 Some regulator directories will contain a link called parent.
187 This points to the parent or supply regulator if one exists. 200 This points to the parent or supply regulator if one exists.
@@ -189,7 +202,7 @@ Description:
189What: /sys/class/regulator/.../suspend_mem_microvolts 202What: /sys/class/regulator/.../suspend_mem_microvolts
190Date: May 2008 203Date: May 2008
191KernelVersion: 2.6.26 204KernelVersion: 2.6.26
192Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 205Contact: Liam Girdwood <lrg@slimlogic.co.uk>
193Description: 206Description:
194 Each regulator directory will contain a field called 207 Each regulator directory will contain a field called
195 suspend_mem_microvolts. This holds the regulator output 208 suspend_mem_microvolts. This holds the regulator output
@@ -203,7 +216,7 @@ Description:
203What: /sys/class/regulator/.../suspend_disk_microvolts 216What: /sys/class/regulator/.../suspend_disk_microvolts
204Date: May 2008 217Date: May 2008
205KernelVersion: 2.6.26 218KernelVersion: 2.6.26
206Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 219Contact: Liam Girdwood <lrg@slimlogic.co.uk>
207Description: 220Description:
208 Each regulator directory will contain a field called 221 Each regulator directory will contain a field called
209 suspend_disk_microvolts. This holds the regulator output 222 suspend_disk_microvolts. This holds the regulator output
@@ -217,7 +230,7 @@ Description:
217What: /sys/class/regulator/.../suspend_standby_microvolts 230What: /sys/class/regulator/.../suspend_standby_microvolts
218Date: May 2008 231Date: May 2008
219KernelVersion: 2.6.26 232KernelVersion: 2.6.26
220Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 233Contact: Liam Girdwood <lrg@slimlogic.co.uk>
221Description: 234Description:
222 Each regulator directory will contain a field called 235 Each regulator directory will contain a field called
223 suspend_standby_microvolts. This holds the regulator output 236 suspend_standby_microvolts. This holds the regulator output
@@ -231,7 +244,7 @@ Description:
231What: /sys/class/regulator/.../suspend_mem_mode 244What: /sys/class/regulator/.../suspend_mem_mode
232Date: May 2008 245Date: May 2008
233KernelVersion: 2.6.26 246KernelVersion: 2.6.26
234Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 247Contact: Liam Girdwood <lrg@slimlogic.co.uk>
235Description: 248Description:
236 Each regulator directory will contain a field called 249 Each regulator directory will contain a field called
237 suspend_mem_mode. This holds the regulator operating mode 250 suspend_mem_mode. This holds the regulator operating mode
@@ -245,7 +258,7 @@ Description:
245What: /sys/class/regulator/.../suspend_disk_mode 258What: /sys/class/regulator/.../suspend_disk_mode
246Date: May 2008 259Date: May 2008
247KernelVersion: 2.6.26 260KernelVersion: 2.6.26
248Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 261Contact: Liam Girdwood <lrg@slimlogic.co.uk>
249Description: 262Description:
250 Each regulator directory will contain a field called 263 Each regulator directory will contain a field called
251 suspend_disk_mode. This holds the regulator operating mode 264 suspend_disk_mode. This holds the regulator operating mode
@@ -258,7 +271,7 @@ Description:
258What: /sys/class/regulator/.../suspend_standby_mode 271What: /sys/class/regulator/.../suspend_standby_mode
259Date: May 2008 272Date: May 2008
260KernelVersion: 2.6.26 273KernelVersion: 2.6.26
261Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 274Contact: Liam Girdwood <lrg@slimlogic.co.uk>
262Description: 275Description:
263 Each regulator directory will contain a field called 276 Each regulator directory will contain a field called
264 suspend_standby_mode. This holds the regulator operating mode 277 suspend_standby_mode. This holds the regulator operating mode
@@ -272,7 +285,7 @@ Description:
272What: /sys/class/regulator/.../suspend_mem_state 285What: /sys/class/regulator/.../suspend_mem_state
273Date: May 2008 286Date: May 2008
274KernelVersion: 2.6.26 287KernelVersion: 2.6.26
275Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 288Contact: Liam Girdwood <lrg@slimlogic.co.uk>
276Description: 289Description:
277 Each regulator directory will contain a field called 290 Each regulator directory will contain a field called
278 suspend_mem_state. This holds the regulator operating state 291 suspend_mem_state. This holds the regulator operating state
@@ -287,7 +300,7 @@ Description:
287What: /sys/class/regulator/.../suspend_disk_state 300What: /sys/class/regulator/.../suspend_disk_state
288Date: May 2008 301Date: May 2008
289KernelVersion: 2.6.26 302KernelVersion: 2.6.26
290Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 303Contact: Liam Girdwood <lrg@slimlogic.co.uk>
291Description: 304Description:
292 Each regulator directory will contain a field called 305 Each regulator directory will contain a field called
293 suspend_disk_state. This holds the regulator operating state 306 suspend_disk_state. This holds the regulator operating state
@@ -302,7 +315,7 @@ Description:
302What: /sys/class/regulator/.../suspend_standby_state 315What: /sys/class/regulator/.../suspend_standby_state
303Date: May 2008 316Date: May 2008
304KernelVersion: 2.6.26 317KernelVersion: 2.6.26
305Contact: Liam Girdwood <lg@opensource.wolfsonmicro.com> 318Contact: Liam Girdwood <lrg@slimlogic.co.uk>
306Description: 319Description:
307 Each regulator directory will contain a field called 320 Each regulator directory will contain a field called
308 suspend_standby_state. This holds the regulator operating 321 suspend_standby_state. This holds the regulator operating
diff --git a/Documentation/power/regulator/machine.txt b/Documentation/power/regulator/machine.txt
index c9a35665cf70..ce3487d99abe 100644
--- a/Documentation/power/regulator/machine.txt
+++ b/Documentation/power/regulator/machine.txt
@@ -2,17 +2,8 @@ Regulator Machine Driver Interface
2=================================== 2===================================
3 3
4The regulator machine driver interface is intended for board/machine specific 4The regulator machine driver interface is intended for board/machine specific
5initialisation code to configure the regulator subsystem. Typical things that 5initialisation code to configure the regulator subsystem.
6machine drivers would do are :-
7 6
8 1. Regulator -> Device mapping.
9 2. Regulator supply configuration.
10 3. Power Domain constraint setting.
11
12
13
141. Regulator -> device mapping
15==============================
16Consider the following machine :- 7Consider the following machine :-
17 8
18 Regulator-1 -+-> Regulator-2 --> [Consumer A @ 1.8 - 2.0V] 9 Regulator-1 -+-> Regulator-2 --> [Consumer A @ 1.8 - 2.0V]
@@ -21,81 +12,82 @@ Consider the following machine :-
21 12
22The drivers for consumers A & B must be mapped to the correct regulator in 13The drivers for consumers A & B must be mapped to the correct regulator in
23order to control their power supply. This mapping can be achieved in machine 14order to control their power supply. This mapping can be achieved in machine
24initialisation code by calling :- 15initialisation code by creating a struct regulator_consumer_supply for
16each regulator.
17
18struct regulator_consumer_supply {
19 struct device *dev; /* consumer */
20 const char *supply; /* consumer supply - e.g. "vcc" */
21};
25 22
26int regulator_set_device_supply(const char *regulator, struct device *dev, 23e.g. for the machine above
27 const char *supply);
28 24
29and is shown with the following code :- 25static struct regulator_consumer_supply regulator1_consumers[] = {
26{
27 .dev = &platform_consumerB_device.dev,
28 .supply = "Vcc",
29},};
30 30
31regulator_set_device_supply("Regulator-1", devB, "Vcc"); 31static struct regulator_consumer_supply regulator2_consumers[] = {
32regulator_set_device_supply("Regulator-2", devA, "Vcc"); 32{
33 .dev = &platform_consumerA_device.dev,
34 .supply = "Vcc",
35},};
33 36
34This maps Regulator-1 to the 'Vcc' supply for Consumer B and maps Regulator-2 37This maps Regulator-1 to the 'Vcc' supply for Consumer B and maps Regulator-2
35to the 'Vcc' supply for Consumer A. 38to the 'Vcc' supply for Consumer A.
36 39
37 40Constraints can now be registered by defining a struct regulator_init_data
382. Regulator supply configuration. 41for each regulator power domain. This structure also maps the consumers
39================================== 42to their supply regulator :-
40Consider the following machine (again) :- 43
41 44static struct regulator_init_data regulator1_data = {
42 Regulator-1 -+-> Regulator-2 --> [Consumer A @ 1.8 - 2.0V] 45 .constraints = {
43 | 46 .min_uV = 3300000,
44 +-> [Consumer B @ 3.3V] 47 .max_uV = 3300000,
48 .valid_modes_mask = REGULATOR_MODE_NORMAL,
49 },
50 .num_consumer_supplies = ARRAY_SIZE(regulator1_consumers),
51 .consumer_supplies = regulator1_consumers,
52};
45 53
46Regulator-1 supplies power to Regulator-2. This relationship must be registered 54Regulator-1 supplies power to Regulator-2. This relationship must be registered
47with the core so that Regulator-1 is also enabled when Consumer A enables it's 55with the core so that Regulator-1 is also enabled when Consumer A enables it's
48supply (Regulator-2). 56supply (Regulator-2). The supply regulator is set by the supply_regulator_dev
49 57field below:-
50This relationship can be register with the core via :- 58
51 59static struct regulator_init_data regulator2_data = {
52int regulator_set_supply(const char *regulator, const char *regulator_supply); 60 .supply_regulator_dev = &platform_regulator1_device.dev,
53 61 .constraints = {
54In this example we would use the following code :- 62 .min_uV = 1800000,
55 63 .max_uV = 2000000,
56regulator_set_supply("Regulator-2", "Regulator-1"); 64 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
57 65 .valid_modes_mask = REGULATOR_MODE_NORMAL,
58Relationships can be queried by calling :- 66 },
59 67 .num_consumer_supplies = ARRAY_SIZE(regulator2_consumers),
60const char *regulator_get_supply(const char *regulator); 68 .consumer_supplies = regulator2_consumers,
61
62
633. Power Domain constraint setting.
64===================================
65Each power domain within a system has physical constraints on voltage and
66current. This must be defined in software so that the power domain is always
67operated within specifications.
68
69Consider the following machine (again) :-
70
71 Regulator-1 -+-> Regulator-2 --> [Consumer A @ 1.8 - 2.0V]
72 |
73 +-> [Consumer B @ 3.3V]
74
75This gives us two regulators and two power domains:
76
77 Domain 1: Regulator-2, Consumer B.
78 Domain 2: Consumer A.
79
80Constraints can be registered by calling :-
81
82int regulator_set_platform_constraints(const char *regulator,
83 struct regulation_constraints *constraints);
84
85The example is defined as follows :-
86
87struct regulation_constraints domain_1 = {
88 .min_uV = 3300000,
89 .max_uV = 3300000,
90 .valid_modes_mask = REGULATOR_MODE_NORMAL,
91}; 69};
92 70
93struct regulation_constraints domain_2 = { 71Finally the regulator devices must be registered in the usual manner.
94 .min_uV = 1800000, 72
95 .max_uV = 2000000, 73static struct platform_device regulator_devices[] = {
96 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 74{
97 .valid_modes_mask = REGULATOR_MODE_NORMAL, 75 .name = "regulator",
76 .id = DCDC_1,
77 .dev = {
78 .platform_data = &regulator1_data,
79 },
80},
81{
82 .name = "regulator",
83 .id = DCDC_2,
84 .dev = {
85 .platform_data = &regulator2_data,
86 },
87},
98}; 88};
89/* register regulator 1 device */
90platform_device_register(&wm8350_regulator_devices[0]);
99 91
100regulator_set_platform_constraints("Regulator-1", &domain_1); 92/* register regulator 2 device */
101regulator_set_platform_constraints("Regulator-2", &domain_2); 93platform_device_register(&wm8350_regulator_devices[1]);
diff --git a/Documentation/power/regulator/regulator.txt b/Documentation/power/regulator/regulator.txt
index a69050143592..4200accb9bba 100644
--- a/Documentation/power/regulator/regulator.txt
+++ b/Documentation/power/regulator/regulator.txt
@@ -10,11 +10,11 @@ Registration
10 10
11Drivers can register a regulator by calling :- 11Drivers can register a regulator by calling :-
12 12
13struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc, 13struct regulator_dev *regulator_register(struct device *dev,
14 void *reg_data); 14 struct regulator_desc *regulator_desc);
15 15
16This will register the regulators capabilities and operations the regulator 16This will register the regulators capabilities and operations to the regulator
17core. The core does not touch reg_data (private to regulator driver). 17core.
18 18
19Regulators can be unregistered by calling :- 19Regulators can be unregistered by calling :-
20 20
diff --git a/MAINTAINERS b/MAINTAINERS
index 988b0a852890..5d0b8a23d639 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4520,10 +4520,11 @@ S: Maintained
4520 4520
4521VOLTAGE AND CURRENT REGULATOR FRAMEWORK 4521VOLTAGE AND CURRENT REGULATOR FRAMEWORK
4522P: Liam Girdwood 4522P: Liam Girdwood
4523M: lg@opensource.wolfsonmicro.com 4523M: lrg@slimlogic.co.uk
4524P: Mark Brown 4524P: Mark Brown
4525M: broonie@opensource.wolfsonmicro.com 4525M: broonie@opensource.wolfsonmicro.com
4526W: http://opensource.wolfsonmicro.com/node/15 4526W: http://opensource.wolfsonmicro.com/node/15
4527W: http://www.slimlogic.co.uk/?page_id=5
4527T: git kernel.org/pub/scm/linux/kernel/git/lrg/voltage-2.6.git 4528T: git kernel.org/pub/scm/linux/kernel/git/lrg/voltage-2.6.git
4528S: Supported 4529S: Supported
4529 4530
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 0dae245c6259..5eff8ad834d6 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -87,6 +87,44 @@ config MFD_TC6393XB
87 help 87 help
88 Support for Toshiba Mobile IO Controller TC6393XB 88 Support for Toshiba Mobile IO Controller TC6393XB
89 89
90config MFD_WM8400
91 tristate "Support Wolfson Microelectronics WM8400"
92 help
93 Support for the Wolfson Microelecronics WM8400 PMIC and audio
94 CODEC. This driver adds provides common support for accessing
95 the device, additional drivers must be enabled in order to use
96 the functionality of the device.
97
98config MFD_WM8350
99 tristate
100
101config MFD_WM8350_CONFIG_MODE_0
102 bool
103 depends on MFD_WM8350
104
105config MFD_WM8350_CONFIG_MODE_1
106 bool
107 depends on MFD_WM8350
108
109config MFD_WM8350_CONFIG_MODE_2
110 bool
111 depends on MFD_WM8350
112
113config MFD_WM8350_CONFIG_MODE_3
114 bool
115 depends on MFD_WM8350
116
117config MFD_WM8350_I2C
118 tristate "Support Wolfson Microelectronics WM8350 with I2C"
119 select MFD_WM8350
120 depends on I2C
121 help
122 The WM8350 is an integrated audio and power management
123 subsystem with watchdog and RTC functionality for embedded
124 systems. This option enables core support for the WM8350 with
125 I2C as the control interface. Additional options must be
126 selected to enable support for the functionality of the chip.
127
90endmenu 128endmenu
91 129
92menu "Multimedia Capabilities Port drivers" 130menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 6abebe364419..759b1fe1c891 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -12,6 +12,11 @@ obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o
12obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o 12obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o
13obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o 13obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o
14 14
15obj-$(CONFIG_MFD_WM8400) += wm8400-core.o
16wm8350-objs := wm8350-core.o wm8350-regmap.o wm8350-gpio.o
17obj-$(CONFIG_MFD_WM8350) += wm8350.o
18obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o
19
15obj-$(CONFIG_MFD_CORE) += mfd-core.o 20obj-$(CONFIG_MFD_CORE) += mfd-core.o
16 21
17obj-$(CONFIG_MCP) += mcp-core.o 22obj-$(CONFIG_MCP) += mcp-core.o
diff --git a/drivers/mfd/wm8350-core.c b/drivers/mfd/wm8350-core.c
new file mode 100644
index 000000000000..25a7a5d08bce
--- /dev/null
+++ b/drivers/mfd/wm8350-core.c
@@ -0,0 +1,1273 @@
1/*
2 * wm8350-core.c -- Device access for Wolfson WM8350
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood, Mark Brown
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/bug.h>
19#include <linux/device.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/workqueue.h>
23
24#include <linux/mfd/wm8350/core.h>
25#include <linux/mfd/wm8350/audio.h>
26#include <linux/mfd/wm8350/comparator.h>
27#include <linux/mfd/wm8350/gpio.h>
28#include <linux/mfd/wm8350/pmic.h>
29#include <linux/mfd/wm8350/rtc.h>
30#include <linux/mfd/wm8350/supply.h>
31#include <linux/mfd/wm8350/wdt.h>
32
33#define WM8350_UNLOCK_KEY 0x0013
34#define WM8350_LOCK_KEY 0x0000
35
36#define WM8350_CLOCK_CONTROL_1 0x28
37#define WM8350_AIF_TEST 0x74
38
39/* debug */
40#define WM8350_BUS_DEBUG 0
41#if WM8350_BUS_DEBUG
42#define dump(regs, src) do { \
43 int i_; \
44 u16 *src_ = src; \
45 printk(KERN_DEBUG); \
46 for (i_ = 0; i_ < regs; i_++) \
47 printk(" 0x%4.4x", *src_++); \
48 printk("\n"); \
49} while (0);
50#else
51#define dump(bytes, src)
52#endif
53
54#define WM8350_LOCK_DEBUG 0
55#if WM8350_LOCK_DEBUG
56#define ldbg(format, arg...) printk(format, ## arg)
57#else
58#define ldbg(format, arg...)
59#endif
60
61/*
62 * WM8350 Device IO
63 */
64static DEFINE_MUTEX(io_mutex);
65static DEFINE_MUTEX(reg_lock_mutex);
66static DEFINE_MUTEX(auxadc_mutex);
67
68/* Perform a physical read from the device.
69 */
70static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
71 u16 *dest)
72{
73 int i, ret;
74 int bytes = num_regs * 2;
75
76 dev_dbg(wm8350->dev, "volatile read\n");
77 ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
78
79 for (i = reg; i < reg + num_regs; i++) {
80 /* Cache is CPU endian */
81 dest[i - reg] = be16_to_cpu(dest[i - reg]);
82
83 /* Satisfy non-volatile bits from cache */
84 dest[i - reg] &= wm8350_reg_io_map[i].vol;
85 dest[i - reg] |= wm8350->reg_cache[i];
86
87 /* Mask out non-readable bits */
88 dest[i - reg] &= wm8350_reg_io_map[i].readable;
89 }
90
91 dump(num_regs, dest);
92
93 return ret;
94}
95
96static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
97{
98 int i;
99 int end = reg + num_regs;
100 int ret = 0;
101 int bytes = num_regs * 2;
102
103 if (wm8350->read_dev == NULL)
104 return -ENODEV;
105
106 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
107 dev_err(wm8350->dev, "invalid reg %x\n",
108 reg + num_regs - 1);
109 return -EINVAL;
110 }
111
112 dev_dbg(wm8350->dev,
113 "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
114
115#if WM8350_BUS_DEBUG
116 /* we can _safely_ read any register, but warn if read not supported */
117 for (i = reg; i < end; i++) {
118 if (!wm8350_reg_io_map[i].readable)
119 dev_warn(wm8350->dev,
120 "reg R%d is not readable\n", i);
121 }
122#endif
123
124 /* if any volatile registers are required, then read back all */
125 for (i = reg; i < end; i++)
126 if (wm8350_reg_io_map[i].vol)
127 return wm8350_phys_read(wm8350, reg, num_regs, dest);
128
129 /* no volatiles, then cache is good */
130 dev_dbg(wm8350->dev, "cache read\n");
131 memcpy(dest, &wm8350->reg_cache[reg], bytes);
132 dump(num_regs, dest);
133 return ret;
134}
135
136static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
137{
138 if (reg == WM8350_SECURITY ||
139 wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
140 return 0;
141
142 if ((reg == WM8350_GPIO_CONFIGURATION_I_O) ||
143 (reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
144 reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
145 (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
146 reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
147 return 1;
148 return 0;
149}
150
151static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
152{
153 int i;
154 int end = reg + num_regs;
155 int bytes = num_regs * 2;
156
157 if (wm8350->write_dev == NULL)
158 return -ENODEV;
159
160 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
161 dev_err(wm8350->dev, "invalid reg %x\n",
162 reg + num_regs - 1);
163 return -EINVAL;
164 }
165
166 /* it's generally not a good idea to write to RO or locked registers */
167 for (i = reg; i < end; i++) {
168 if (!wm8350_reg_io_map[i].writable) {
169 dev_err(wm8350->dev,
170 "attempted write to read only reg R%d\n", i);
171 return -EINVAL;
172 }
173
174 if (is_reg_locked(wm8350, i)) {
175 dev_err(wm8350->dev,
176 "attempted write to locked reg R%d\n", i);
177 return -EINVAL;
178 }
179
180 src[i - reg] &= wm8350_reg_io_map[i].writable;
181
182 wm8350->reg_cache[i] =
183 (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
184 | src[i - reg];
185
186 src[i - reg] = cpu_to_be16(src[i - reg]);
187 }
188
189 /* Actually write it out */
190 return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
191}
192
193/*
194 * Safe read, modify, write methods
195 */
196int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
197{
198 u16 data;
199 int err;
200
201 mutex_lock(&io_mutex);
202 err = wm8350_read(wm8350, reg, 1, &data);
203 if (err) {
204 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
205 goto out;
206 }
207
208 data &= ~mask;
209 err = wm8350_write(wm8350, reg, 1, &data);
210 if (err)
211 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
212out:
213 mutex_unlock(&io_mutex);
214 return err;
215}
216EXPORT_SYMBOL_GPL(wm8350_clear_bits);
217
218int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
219{
220 u16 data;
221 int err;
222
223 mutex_lock(&io_mutex);
224 err = wm8350_read(wm8350, reg, 1, &data);
225 if (err) {
226 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
227 goto out;
228 }
229
230 data |= mask;
231 err = wm8350_write(wm8350, reg, 1, &data);
232 if (err)
233 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
234out:
235 mutex_unlock(&io_mutex);
236 return err;
237}
238EXPORT_SYMBOL_GPL(wm8350_set_bits);
239
240u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
241{
242 u16 data;
243 int err;
244
245 mutex_lock(&io_mutex);
246 err = wm8350_read(wm8350, reg, 1, &data);
247 if (err)
248 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
249
250 mutex_unlock(&io_mutex);
251 return data;
252}
253EXPORT_SYMBOL_GPL(wm8350_reg_read);
254
255int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
256{
257 int ret;
258 u16 data = val;
259
260 mutex_lock(&io_mutex);
261 ret = wm8350_write(wm8350, reg, 1, &data);
262 if (ret)
263 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
264 mutex_unlock(&io_mutex);
265 return ret;
266}
267EXPORT_SYMBOL_GPL(wm8350_reg_write);
268
269int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
270 u16 *dest)
271{
272 int err = 0;
273
274 mutex_lock(&io_mutex);
275 err = wm8350_read(wm8350, start_reg, regs, dest);
276 if (err)
277 dev_err(wm8350->dev, "block read starting from R%d failed\n",
278 start_reg);
279 mutex_unlock(&io_mutex);
280 return err;
281}
282EXPORT_SYMBOL_GPL(wm8350_block_read);
283
284int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
285 u16 *src)
286{
287 int ret = 0;
288
289 mutex_lock(&io_mutex);
290 ret = wm8350_write(wm8350, start_reg, regs, src);
291 if (ret)
292 dev_err(wm8350->dev, "block write starting at R%d failed\n",
293 start_reg);
294 mutex_unlock(&io_mutex);
295 return ret;
296}
297EXPORT_SYMBOL_GPL(wm8350_block_write);
298
299int wm8350_reg_lock(struct wm8350 *wm8350)
300{
301 u16 key = WM8350_LOCK_KEY;
302 int ret;
303
304 ldbg(__func__);
305 mutex_lock(&io_mutex);
306 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
307 if (ret)
308 dev_err(wm8350->dev, "lock failed\n");
309 mutex_unlock(&io_mutex);
310 return ret;
311}
312EXPORT_SYMBOL_GPL(wm8350_reg_lock);
313
314int wm8350_reg_unlock(struct wm8350 *wm8350)
315{
316 u16 key = WM8350_UNLOCK_KEY;
317 int ret;
318
319 ldbg(__func__);
320 mutex_lock(&io_mutex);
321 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
322 if (ret)
323 dev_err(wm8350->dev, "unlock failed\n");
324 mutex_unlock(&io_mutex);
325 return ret;
326}
327EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
328
329static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
330{
331 mutex_lock(&wm8350->irq_mutex);
332
333 if (wm8350->irq[irq].handler)
334 wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data);
335 else {
336 dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n",
337 irq);
338 wm8350_mask_irq(wm8350, irq);
339 }
340
341 mutex_unlock(&wm8350->irq_mutex);
342}
343
344/*
345 * wm8350_irq_worker actually handles the interrupts. Since all
346 * interrupts are clear on read the IRQ line will be reasserted and
347 * the physical IRQ will be handled again if another interrupt is
348 * asserted while we run - in the normal course of events this is a
349 * rare occurrence so we save I2C/SPI reads.
350 */
351static void wm8350_irq_worker(struct work_struct *work)
352{
353 struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work);
354 u16 level_one, status1, status2, comp;
355
356 /* TODO: Use block reads to improve performance? */
357 level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
358 & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
359 status1 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1)
360 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_1_MASK);
361 status2 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_2)
362 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_2_MASK);
363 comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS)
364 & ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK);
365
366 /* over current */
367 if (level_one & WM8350_OC_INT) {
368 u16 oc;
369
370 oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INT_STATUS);
371 oc &= ~wm8350_reg_read(wm8350,
372 WM8350_OVER_CURRENT_INT_STATUS_MASK);
373
374 if (oc & WM8350_OC_LS_EINT) /* limit switch */
375 wm8350_irq_call_handler(wm8350, WM8350_IRQ_OC_LS);
376 }
377
378 /* under voltage */
379 if (level_one & WM8350_UV_INT) {
380 u16 uv;
381
382 uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS);
383 uv &= ~wm8350_reg_read(wm8350,
384 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK);
385
386 if (uv & WM8350_UV_DC1_EINT)
387 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC1);
388 if (uv & WM8350_UV_DC2_EINT)
389 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC2);
390 if (uv & WM8350_UV_DC3_EINT)
391 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC3);
392 if (uv & WM8350_UV_DC4_EINT)
393 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC4);
394 if (uv & WM8350_UV_DC5_EINT)
395 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC5);
396 if (uv & WM8350_UV_DC6_EINT)
397 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC6);
398 if (uv & WM8350_UV_LDO1_EINT)
399 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO1);
400 if (uv & WM8350_UV_LDO2_EINT)
401 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO2);
402 if (uv & WM8350_UV_LDO3_EINT)
403 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO3);
404 if (uv & WM8350_UV_LDO4_EINT)
405 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO4);
406 }
407
408 /* charger, RTC */
409 if (status1) {
410 if (status1 & WM8350_CHG_BAT_HOT_EINT)
411 wm8350_irq_call_handler(wm8350,
412 WM8350_IRQ_CHG_BAT_HOT);
413 if (status1 & WM8350_CHG_BAT_COLD_EINT)
414 wm8350_irq_call_handler(wm8350,
415 WM8350_IRQ_CHG_BAT_COLD);
416 if (status1 & WM8350_CHG_BAT_FAIL_EINT)
417 wm8350_irq_call_handler(wm8350,
418 WM8350_IRQ_CHG_BAT_FAIL);
419 if (status1 & WM8350_CHG_TO_EINT)
420 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_TO);
421 if (status1 & WM8350_CHG_END_EINT)
422 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_END);
423 if (status1 & WM8350_CHG_START_EINT)
424 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_START);
425 if (status1 & WM8350_CHG_FAST_RDY_EINT)
426 wm8350_irq_call_handler(wm8350,
427 WM8350_IRQ_CHG_FAST_RDY);
428 if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT)
429 wm8350_irq_call_handler(wm8350,
430 WM8350_IRQ_CHG_VBATT_LT_3P9);
431 if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT)
432 wm8350_irq_call_handler(wm8350,
433 WM8350_IRQ_CHG_VBATT_LT_3P1);
434 if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT)
435 wm8350_irq_call_handler(wm8350,
436 WM8350_IRQ_CHG_VBATT_LT_2P85);
437 if (status1 & WM8350_RTC_ALM_EINT)
438 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_ALM);
439 if (status1 & WM8350_RTC_SEC_EINT)
440 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_SEC);
441 if (status1 & WM8350_RTC_PER_EINT)
442 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_PER);
443 }
444
445 /* current sink, system, aux adc */
446 if (status2) {
447 if (status2 & WM8350_CS1_EINT)
448 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS1);
449 if (status2 & WM8350_CS2_EINT)
450 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS2);
451
452 if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT)
453 wm8350_irq_call_handler(wm8350,
454 WM8350_IRQ_SYS_HYST_COMP_FAIL);
455 if (status2 & WM8350_SYS_CHIP_GT115_EINT)
456 wm8350_irq_call_handler(wm8350,
457 WM8350_IRQ_SYS_CHIP_GT115);
458 if (status2 & WM8350_SYS_CHIP_GT140_EINT)
459 wm8350_irq_call_handler(wm8350,
460 WM8350_IRQ_SYS_CHIP_GT140);
461 if (status2 & WM8350_SYS_WDOG_TO_EINT)
462 wm8350_irq_call_handler(wm8350,
463 WM8350_IRQ_SYS_WDOG_TO);
464
465 if (status2 & WM8350_AUXADC_DATARDY_EINT)
466 wm8350_irq_call_handler(wm8350,
467 WM8350_IRQ_AUXADC_DATARDY);
468 if (status2 & WM8350_AUXADC_DCOMP4_EINT)
469 wm8350_irq_call_handler(wm8350,
470 WM8350_IRQ_AUXADC_DCOMP4);
471 if (status2 & WM8350_AUXADC_DCOMP3_EINT)
472 wm8350_irq_call_handler(wm8350,
473 WM8350_IRQ_AUXADC_DCOMP3);
474 if (status2 & WM8350_AUXADC_DCOMP2_EINT)
475 wm8350_irq_call_handler(wm8350,
476 WM8350_IRQ_AUXADC_DCOMP2);
477 if (status2 & WM8350_AUXADC_DCOMP1_EINT)
478 wm8350_irq_call_handler(wm8350,
479 WM8350_IRQ_AUXADC_DCOMP1);
480
481 if (status2 & WM8350_USB_LIMIT_EINT)
482 wm8350_irq_call_handler(wm8350, WM8350_IRQ_USB_LIMIT);
483 }
484
485 /* wake, codec, ext */
486 if (comp) {
487 if (comp & WM8350_WKUP_OFF_STATE_EINT)
488 wm8350_irq_call_handler(wm8350,
489 WM8350_IRQ_WKUP_OFF_STATE);
490 if (comp & WM8350_WKUP_HIB_STATE_EINT)
491 wm8350_irq_call_handler(wm8350,
492 WM8350_IRQ_WKUP_HIB_STATE);
493 if (comp & WM8350_WKUP_CONV_FAULT_EINT)
494 wm8350_irq_call_handler(wm8350,
495 WM8350_IRQ_WKUP_CONV_FAULT);
496 if (comp & WM8350_WKUP_WDOG_RST_EINT)
497 wm8350_irq_call_handler(wm8350,
498 WM8350_IRQ_WKUP_WDOG_RST);
499 if (comp & WM8350_WKUP_GP_PWR_ON_EINT)
500 wm8350_irq_call_handler(wm8350,
501 WM8350_IRQ_WKUP_GP_PWR_ON);
502 if (comp & WM8350_WKUP_ONKEY_EINT)
503 wm8350_irq_call_handler(wm8350, WM8350_IRQ_WKUP_ONKEY);
504 if (comp & WM8350_WKUP_GP_WAKEUP_EINT)
505 wm8350_irq_call_handler(wm8350,
506 WM8350_IRQ_WKUP_GP_WAKEUP);
507
508 if (comp & WM8350_CODEC_JCK_DET_L_EINT)
509 wm8350_irq_call_handler(wm8350,
510 WM8350_IRQ_CODEC_JCK_DET_L);
511 if (comp & WM8350_CODEC_JCK_DET_R_EINT)
512 wm8350_irq_call_handler(wm8350,
513 WM8350_IRQ_CODEC_JCK_DET_R);
514 if (comp & WM8350_CODEC_MICSCD_EINT)
515 wm8350_irq_call_handler(wm8350,
516 WM8350_IRQ_CODEC_MICSCD);
517 if (comp & WM8350_CODEC_MICD_EINT)
518 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CODEC_MICD);
519
520 if (comp & WM8350_EXT_USB_FB_EINT)
521 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_USB_FB);
522 if (comp & WM8350_EXT_WALL_FB_EINT)
523 wm8350_irq_call_handler(wm8350,
524 WM8350_IRQ_EXT_WALL_FB);
525 if (comp & WM8350_EXT_BAT_FB_EINT)
526 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_BAT_FB);
527 }
528
529 if (level_one & WM8350_GP_INT) {
530 int i;
531 u16 gpio;
532
533 gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INT_STATUS);
534 gpio &= ~wm8350_reg_read(wm8350,
535 WM8350_GPIO_INT_STATUS_MASK);
536
537 for (i = 0; i < 12; i++) {
538 if (gpio & (1 << i))
539 wm8350_irq_call_handler(wm8350,
540 WM8350_IRQ_GPIO(i));
541 }
542 }
543
544 enable_irq(wm8350->chip_irq);
545}
546
547static irqreturn_t wm8350_irq(int irq, void *data)
548{
549 struct wm8350 *wm8350 = data;
550
551 disable_irq_nosync(irq);
552 schedule_work(&wm8350->irq_work);
553
554 return IRQ_HANDLED;
555}
556
557int wm8350_register_irq(struct wm8350 *wm8350, int irq,
558 void (*handler) (struct wm8350 *, int, void *),
559 void *data)
560{
561 if (irq < 0 || irq > WM8350_NUM_IRQ || !handler)
562 return -EINVAL;
563
564 if (wm8350->irq[irq].handler)
565 return -EBUSY;
566
567 mutex_lock(&wm8350->irq_mutex);
568 wm8350->irq[irq].handler = handler;
569 wm8350->irq[irq].data = data;
570 mutex_unlock(&wm8350->irq_mutex);
571
572 return 0;
573}
574EXPORT_SYMBOL_GPL(wm8350_register_irq);
575
576int wm8350_free_irq(struct wm8350 *wm8350, int irq)
577{
578 if (irq < 0 || irq > WM8350_NUM_IRQ)
579 return -EINVAL;
580
581 mutex_lock(&wm8350->irq_mutex);
582 wm8350->irq[irq].handler = NULL;
583 mutex_unlock(&wm8350->irq_mutex);
584 return 0;
585}
586EXPORT_SYMBOL_GPL(wm8350_free_irq);
587
588int wm8350_mask_irq(struct wm8350 *wm8350, int irq)
589{
590 switch (irq) {
591 case WM8350_IRQ_CHG_BAT_HOT:
592 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
593 WM8350_IM_CHG_BAT_HOT_EINT);
594 case WM8350_IRQ_CHG_BAT_COLD:
595 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
596 WM8350_IM_CHG_BAT_COLD_EINT);
597 case WM8350_IRQ_CHG_BAT_FAIL:
598 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
599 WM8350_IM_CHG_BAT_FAIL_EINT);
600 case WM8350_IRQ_CHG_TO:
601 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
602 WM8350_IM_CHG_TO_EINT);
603 case WM8350_IRQ_CHG_END:
604 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
605 WM8350_IM_CHG_END_EINT);
606 case WM8350_IRQ_CHG_START:
607 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
608 WM8350_IM_CHG_START_EINT);
609 case WM8350_IRQ_CHG_FAST_RDY:
610 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
611 WM8350_IM_CHG_FAST_RDY_EINT);
612 case WM8350_IRQ_RTC_PER:
613 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
614 WM8350_IM_RTC_PER_EINT);
615 case WM8350_IRQ_RTC_SEC:
616 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
617 WM8350_IM_RTC_SEC_EINT);
618 case WM8350_IRQ_RTC_ALM:
619 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
620 WM8350_IM_RTC_ALM_EINT);
621 case WM8350_IRQ_CHG_VBATT_LT_3P9:
622 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
623 WM8350_IM_CHG_VBATT_LT_3P9_EINT);
624 case WM8350_IRQ_CHG_VBATT_LT_3P1:
625 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
626 WM8350_IM_CHG_VBATT_LT_3P1_EINT);
627 case WM8350_IRQ_CHG_VBATT_LT_2P85:
628 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
629 WM8350_IM_CHG_VBATT_LT_2P85_EINT);
630 case WM8350_IRQ_CS1:
631 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
632 WM8350_IM_CS1_EINT);
633 case WM8350_IRQ_CS2:
634 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
635 WM8350_IM_CS2_EINT);
636 case WM8350_IRQ_USB_LIMIT:
637 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
638 WM8350_IM_USB_LIMIT_EINT);
639 case WM8350_IRQ_AUXADC_DATARDY:
640 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
641 WM8350_IM_AUXADC_DATARDY_EINT);
642 case WM8350_IRQ_AUXADC_DCOMP4:
643 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
644 WM8350_IM_AUXADC_DCOMP4_EINT);
645 case WM8350_IRQ_AUXADC_DCOMP3:
646 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
647 WM8350_IM_AUXADC_DCOMP3_EINT);
648 case WM8350_IRQ_AUXADC_DCOMP2:
649 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
650 WM8350_IM_AUXADC_DCOMP2_EINT);
651 case WM8350_IRQ_AUXADC_DCOMP1:
652 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
653 WM8350_IM_AUXADC_DCOMP1_EINT);
654 case WM8350_IRQ_SYS_HYST_COMP_FAIL:
655 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
656 WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
657 case WM8350_IRQ_SYS_CHIP_GT115:
658 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
659 WM8350_IM_SYS_CHIP_GT115_EINT);
660 case WM8350_IRQ_SYS_CHIP_GT140:
661 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
662 WM8350_IM_SYS_CHIP_GT140_EINT);
663 case WM8350_IRQ_SYS_WDOG_TO:
664 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
665 WM8350_IM_SYS_WDOG_TO_EINT);
666 case WM8350_IRQ_UV_LDO4:
667 return wm8350_set_bits(wm8350,
668 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
669 WM8350_IM_UV_LDO4_EINT);
670 case WM8350_IRQ_UV_LDO3:
671 return wm8350_set_bits(wm8350,
672 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
673 WM8350_IM_UV_LDO3_EINT);
674 case WM8350_IRQ_UV_LDO2:
675 return wm8350_set_bits(wm8350,
676 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
677 WM8350_IM_UV_LDO2_EINT);
678 case WM8350_IRQ_UV_LDO1:
679 return wm8350_set_bits(wm8350,
680 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
681 WM8350_IM_UV_LDO1_EINT);
682 case WM8350_IRQ_UV_DC6:
683 return wm8350_set_bits(wm8350,
684 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
685 WM8350_IM_UV_DC6_EINT);
686 case WM8350_IRQ_UV_DC5:
687 return wm8350_set_bits(wm8350,
688 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
689 WM8350_IM_UV_DC5_EINT);
690 case WM8350_IRQ_UV_DC4:
691 return wm8350_set_bits(wm8350,
692 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
693 WM8350_IM_UV_DC4_EINT);
694 case WM8350_IRQ_UV_DC3:
695 return wm8350_set_bits(wm8350,
696 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
697 WM8350_IM_UV_DC3_EINT);
698 case WM8350_IRQ_UV_DC2:
699 return wm8350_set_bits(wm8350,
700 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
701 WM8350_IM_UV_DC2_EINT);
702 case WM8350_IRQ_UV_DC1:
703 return wm8350_set_bits(wm8350,
704 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
705 WM8350_IM_UV_DC1_EINT);
706 case WM8350_IRQ_OC_LS:
707 return wm8350_set_bits(wm8350,
708 WM8350_OVER_CURRENT_INT_STATUS_MASK,
709 WM8350_IM_OC_LS_EINT);
710 case WM8350_IRQ_EXT_USB_FB:
711 return wm8350_set_bits(wm8350,
712 WM8350_COMPARATOR_INT_STATUS_MASK,
713 WM8350_IM_EXT_USB_FB_EINT);
714 case WM8350_IRQ_EXT_WALL_FB:
715 return wm8350_set_bits(wm8350,
716 WM8350_COMPARATOR_INT_STATUS_MASK,
717 WM8350_IM_EXT_WALL_FB_EINT);
718 case WM8350_IRQ_EXT_BAT_FB:
719 return wm8350_set_bits(wm8350,
720 WM8350_COMPARATOR_INT_STATUS_MASK,
721 WM8350_IM_EXT_BAT_FB_EINT);
722 case WM8350_IRQ_CODEC_JCK_DET_L:
723 return wm8350_set_bits(wm8350,
724 WM8350_COMPARATOR_INT_STATUS_MASK,
725 WM8350_IM_CODEC_JCK_DET_L_EINT);
726 case WM8350_IRQ_CODEC_JCK_DET_R:
727 return wm8350_set_bits(wm8350,
728 WM8350_COMPARATOR_INT_STATUS_MASK,
729 WM8350_IM_CODEC_JCK_DET_R_EINT);
730 case WM8350_IRQ_CODEC_MICSCD:
731 return wm8350_set_bits(wm8350,
732 WM8350_COMPARATOR_INT_STATUS_MASK,
733 WM8350_IM_CODEC_MICSCD_EINT);
734 case WM8350_IRQ_CODEC_MICD:
735 return wm8350_set_bits(wm8350,
736 WM8350_COMPARATOR_INT_STATUS_MASK,
737 WM8350_IM_CODEC_MICD_EINT);
738 case WM8350_IRQ_WKUP_OFF_STATE:
739 return wm8350_set_bits(wm8350,
740 WM8350_COMPARATOR_INT_STATUS_MASK,
741 WM8350_IM_WKUP_OFF_STATE_EINT);
742 case WM8350_IRQ_WKUP_HIB_STATE:
743 return wm8350_set_bits(wm8350,
744 WM8350_COMPARATOR_INT_STATUS_MASK,
745 WM8350_IM_WKUP_HIB_STATE_EINT);
746 case WM8350_IRQ_WKUP_CONV_FAULT:
747 return wm8350_set_bits(wm8350,
748 WM8350_COMPARATOR_INT_STATUS_MASK,
749 WM8350_IM_WKUP_CONV_FAULT_EINT);
750 case WM8350_IRQ_WKUP_WDOG_RST:
751 return wm8350_set_bits(wm8350,
752 WM8350_COMPARATOR_INT_STATUS_MASK,
753 WM8350_IM_WKUP_OFF_STATE_EINT);
754 case WM8350_IRQ_WKUP_GP_PWR_ON:
755 return wm8350_set_bits(wm8350,
756 WM8350_COMPARATOR_INT_STATUS_MASK,
757 WM8350_IM_WKUP_GP_PWR_ON_EINT);
758 case WM8350_IRQ_WKUP_ONKEY:
759 return wm8350_set_bits(wm8350,
760 WM8350_COMPARATOR_INT_STATUS_MASK,
761 WM8350_IM_WKUP_ONKEY_EINT);
762 case WM8350_IRQ_WKUP_GP_WAKEUP:
763 return wm8350_set_bits(wm8350,
764 WM8350_COMPARATOR_INT_STATUS_MASK,
765 WM8350_IM_WKUP_GP_WAKEUP_EINT);
766 case WM8350_IRQ_GPIO(0):
767 return wm8350_set_bits(wm8350,
768 WM8350_GPIO_INT_STATUS_MASK,
769 WM8350_IM_GP0_EINT);
770 case WM8350_IRQ_GPIO(1):
771 return wm8350_set_bits(wm8350,
772 WM8350_GPIO_INT_STATUS_MASK,
773 WM8350_IM_GP1_EINT);
774 case WM8350_IRQ_GPIO(2):
775 return wm8350_set_bits(wm8350,
776 WM8350_GPIO_INT_STATUS_MASK,
777 WM8350_IM_GP2_EINT);
778 case WM8350_IRQ_GPIO(3):
779 return wm8350_set_bits(wm8350,
780 WM8350_GPIO_INT_STATUS_MASK,
781 WM8350_IM_GP3_EINT);
782 case WM8350_IRQ_GPIO(4):
783 return wm8350_set_bits(wm8350,
784 WM8350_GPIO_INT_STATUS_MASK,
785 WM8350_IM_GP4_EINT);
786 case WM8350_IRQ_GPIO(5):
787 return wm8350_set_bits(wm8350,
788 WM8350_GPIO_INT_STATUS_MASK,
789 WM8350_IM_GP5_EINT);
790 case WM8350_IRQ_GPIO(6):
791 return wm8350_set_bits(wm8350,
792 WM8350_GPIO_INT_STATUS_MASK,
793 WM8350_IM_GP6_EINT);
794 case WM8350_IRQ_GPIO(7):
795 return wm8350_set_bits(wm8350,
796 WM8350_GPIO_INT_STATUS_MASK,
797 WM8350_IM_GP7_EINT);
798 case WM8350_IRQ_GPIO(8):
799 return wm8350_set_bits(wm8350,
800 WM8350_GPIO_INT_STATUS_MASK,
801 WM8350_IM_GP8_EINT);
802 case WM8350_IRQ_GPIO(9):
803 return wm8350_set_bits(wm8350,
804 WM8350_GPIO_INT_STATUS_MASK,
805 WM8350_IM_GP9_EINT);
806 case WM8350_IRQ_GPIO(10):
807 return wm8350_set_bits(wm8350,
808 WM8350_GPIO_INT_STATUS_MASK,
809 WM8350_IM_GP10_EINT);
810 case WM8350_IRQ_GPIO(11):
811 return wm8350_set_bits(wm8350,
812 WM8350_GPIO_INT_STATUS_MASK,
813 WM8350_IM_GP11_EINT);
814 case WM8350_IRQ_GPIO(12):
815 return wm8350_set_bits(wm8350,
816 WM8350_GPIO_INT_STATUS_MASK,
817 WM8350_IM_GP12_EINT);
818 default:
819 dev_warn(wm8350->dev, "Attempting to mask unknown IRQ %d\n",
820 irq);
821 return -EINVAL;
822 }
823 return 0;
824}
825EXPORT_SYMBOL_GPL(wm8350_mask_irq);
826
827int wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
828{
829 switch (irq) {
830 case WM8350_IRQ_CHG_BAT_HOT:
831 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
832 WM8350_IM_CHG_BAT_HOT_EINT);
833 case WM8350_IRQ_CHG_BAT_COLD:
834 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
835 WM8350_IM_CHG_BAT_COLD_EINT);
836 case WM8350_IRQ_CHG_BAT_FAIL:
837 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
838 WM8350_IM_CHG_BAT_FAIL_EINT);
839 case WM8350_IRQ_CHG_TO:
840 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
841 WM8350_IM_CHG_TO_EINT);
842 case WM8350_IRQ_CHG_END:
843 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
844 WM8350_IM_CHG_END_EINT);
845 case WM8350_IRQ_CHG_START:
846 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
847 WM8350_IM_CHG_START_EINT);
848 case WM8350_IRQ_CHG_FAST_RDY:
849 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
850 WM8350_IM_CHG_FAST_RDY_EINT);
851 case WM8350_IRQ_RTC_PER:
852 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
853 WM8350_IM_RTC_PER_EINT);
854 case WM8350_IRQ_RTC_SEC:
855 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
856 WM8350_IM_RTC_SEC_EINT);
857 case WM8350_IRQ_RTC_ALM:
858 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
859 WM8350_IM_RTC_ALM_EINT);
860 case WM8350_IRQ_CHG_VBATT_LT_3P9:
861 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
862 WM8350_IM_CHG_VBATT_LT_3P9_EINT);
863 case WM8350_IRQ_CHG_VBATT_LT_3P1:
864 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
865 WM8350_IM_CHG_VBATT_LT_3P1_EINT);
866 case WM8350_IRQ_CHG_VBATT_LT_2P85:
867 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
868 WM8350_IM_CHG_VBATT_LT_2P85_EINT);
869 case WM8350_IRQ_CS1:
870 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
871 WM8350_IM_CS1_EINT);
872 case WM8350_IRQ_CS2:
873 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
874 WM8350_IM_CS2_EINT);
875 case WM8350_IRQ_USB_LIMIT:
876 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
877 WM8350_IM_USB_LIMIT_EINT);
878 case WM8350_IRQ_AUXADC_DATARDY:
879 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
880 WM8350_IM_AUXADC_DATARDY_EINT);
881 case WM8350_IRQ_AUXADC_DCOMP4:
882 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
883 WM8350_IM_AUXADC_DCOMP4_EINT);
884 case WM8350_IRQ_AUXADC_DCOMP3:
885 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
886 WM8350_IM_AUXADC_DCOMP3_EINT);
887 case WM8350_IRQ_AUXADC_DCOMP2:
888 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
889 WM8350_IM_AUXADC_DCOMP2_EINT);
890 case WM8350_IRQ_AUXADC_DCOMP1:
891 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
892 WM8350_IM_AUXADC_DCOMP1_EINT);
893 case WM8350_IRQ_SYS_HYST_COMP_FAIL:
894 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
895 WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
896 case WM8350_IRQ_SYS_CHIP_GT115:
897 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
898 WM8350_IM_SYS_CHIP_GT115_EINT);
899 case WM8350_IRQ_SYS_CHIP_GT140:
900 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
901 WM8350_IM_SYS_CHIP_GT140_EINT);
902 case WM8350_IRQ_SYS_WDOG_TO:
903 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
904 WM8350_IM_SYS_WDOG_TO_EINT);
905 case WM8350_IRQ_UV_LDO4:
906 return wm8350_clear_bits(wm8350,
907 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
908 WM8350_IM_UV_LDO4_EINT);
909 case WM8350_IRQ_UV_LDO3:
910 return wm8350_clear_bits(wm8350,
911 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
912 WM8350_IM_UV_LDO3_EINT);
913 case WM8350_IRQ_UV_LDO2:
914 return wm8350_clear_bits(wm8350,
915 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
916 WM8350_IM_UV_LDO2_EINT);
917 case WM8350_IRQ_UV_LDO1:
918 return wm8350_clear_bits(wm8350,
919 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
920 WM8350_IM_UV_LDO1_EINT);
921 case WM8350_IRQ_UV_DC6:
922 return wm8350_clear_bits(wm8350,
923 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
924 WM8350_IM_UV_DC6_EINT);
925 case WM8350_IRQ_UV_DC5:
926 return wm8350_clear_bits(wm8350,
927 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
928 WM8350_IM_UV_DC5_EINT);
929 case WM8350_IRQ_UV_DC4:
930 return wm8350_clear_bits(wm8350,
931 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
932 WM8350_IM_UV_DC4_EINT);
933 case WM8350_IRQ_UV_DC3:
934 return wm8350_clear_bits(wm8350,
935 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
936 WM8350_IM_UV_DC3_EINT);
937 case WM8350_IRQ_UV_DC2:
938 return wm8350_clear_bits(wm8350,
939 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
940 WM8350_IM_UV_DC2_EINT);
941 case WM8350_IRQ_UV_DC1:
942 return wm8350_clear_bits(wm8350,
943 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
944 WM8350_IM_UV_DC1_EINT);
945 case WM8350_IRQ_OC_LS:
946 return wm8350_clear_bits(wm8350,
947 WM8350_OVER_CURRENT_INT_STATUS_MASK,
948 WM8350_IM_OC_LS_EINT);
949 case WM8350_IRQ_EXT_USB_FB:
950 return wm8350_clear_bits(wm8350,
951 WM8350_COMPARATOR_INT_STATUS_MASK,
952 WM8350_IM_EXT_USB_FB_EINT);
953 case WM8350_IRQ_EXT_WALL_FB:
954 return wm8350_clear_bits(wm8350,
955 WM8350_COMPARATOR_INT_STATUS_MASK,
956 WM8350_IM_EXT_WALL_FB_EINT);
957 case WM8350_IRQ_EXT_BAT_FB:
958 return wm8350_clear_bits(wm8350,
959 WM8350_COMPARATOR_INT_STATUS_MASK,
960 WM8350_IM_EXT_BAT_FB_EINT);
961 case WM8350_IRQ_CODEC_JCK_DET_L:
962 return wm8350_clear_bits(wm8350,
963 WM8350_COMPARATOR_INT_STATUS_MASK,
964 WM8350_IM_CODEC_JCK_DET_L_EINT);
965 case WM8350_IRQ_CODEC_JCK_DET_R:
966 return wm8350_clear_bits(wm8350,
967 WM8350_COMPARATOR_INT_STATUS_MASK,
968 WM8350_IM_CODEC_JCK_DET_R_EINT);
969 case WM8350_IRQ_CODEC_MICSCD:
970 return wm8350_clear_bits(wm8350,
971 WM8350_COMPARATOR_INT_STATUS_MASK,
972 WM8350_IM_CODEC_MICSCD_EINT);
973 case WM8350_IRQ_CODEC_MICD:
974 return wm8350_clear_bits(wm8350,
975 WM8350_COMPARATOR_INT_STATUS_MASK,
976 WM8350_IM_CODEC_MICD_EINT);
977 case WM8350_IRQ_WKUP_OFF_STATE:
978 return wm8350_clear_bits(wm8350,
979 WM8350_COMPARATOR_INT_STATUS_MASK,
980 WM8350_IM_WKUP_OFF_STATE_EINT);
981 case WM8350_IRQ_WKUP_HIB_STATE:
982 return wm8350_clear_bits(wm8350,
983 WM8350_COMPARATOR_INT_STATUS_MASK,
984 WM8350_IM_WKUP_HIB_STATE_EINT);
985 case WM8350_IRQ_WKUP_CONV_FAULT:
986 return wm8350_clear_bits(wm8350,
987 WM8350_COMPARATOR_INT_STATUS_MASK,
988 WM8350_IM_WKUP_CONV_FAULT_EINT);
989 case WM8350_IRQ_WKUP_WDOG_RST:
990 return wm8350_clear_bits(wm8350,
991 WM8350_COMPARATOR_INT_STATUS_MASK,
992 WM8350_IM_WKUP_OFF_STATE_EINT);
993 case WM8350_IRQ_WKUP_GP_PWR_ON:
994 return wm8350_clear_bits(wm8350,
995 WM8350_COMPARATOR_INT_STATUS_MASK,
996 WM8350_IM_WKUP_GP_PWR_ON_EINT);
997 case WM8350_IRQ_WKUP_ONKEY:
998 return wm8350_clear_bits(wm8350,
999 WM8350_COMPARATOR_INT_STATUS_MASK,
1000 WM8350_IM_WKUP_ONKEY_EINT);
1001 case WM8350_IRQ_WKUP_GP_WAKEUP:
1002 return wm8350_clear_bits(wm8350,
1003 WM8350_COMPARATOR_INT_STATUS_MASK,
1004 WM8350_IM_WKUP_GP_WAKEUP_EINT);
1005 case WM8350_IRQ_GPIO(0):
1006 return wm8350_clear_bits(wm8350,
1007 WM8350_GPIO_INT_STATUS_MASK,
1008 WM8350_IM_GP0_EINT);
1009 case WM8350_IRQ_GPIO(1):
1010 return wm8350_clear_bits(wm8350,
1011 WM8350_GPIO_INT_STATUS_MASK,
1012 WM8350_IM_GP1_EINT);
1013 case WM8350_IRQ_GPIO(2):
1014 return wm8350_clear_bits(wm8350,
1015 WM8350_GPIO_INT_STATUS_MASK,
1016 WM8350_IM_GP2_EINT);
1017 case WM8350_IRQ_GPIO(3):
1018 return wm8350_clear_bits(wm8350,
1019 WM8350_GPIO_INT_STATUS_MASK,
1020 WM8350_IM_GP3_EINT);
1021 case WM8350_IRQ_GPIO(4):
1022 return wm8350_clear_bits(wm8350,
1023 WM8350_GPIO_INT_STATUS_MASK,
1024 WM8350_IM_GP4_EINT);
1025 case WM8350_IRQ_GPIO(5):
1026 return wm8350_clear_bits(wm8350,
1027 WM8350_GPIO_INT_STATUS_MASK,
1028 WM8350_IM_GP5_EINT);
1029 case WM8350_IRQ_GPIO(6):
1030 return wm8350_clear_bits(wm8350,
1031 WM8350_GPIO_INT_STATUS_MASK,
1032 WM8350_IM_GP6_EINT);
1033 case WM8350_IRQ_GPIO(7):
1034 return wm8350_clear_bits(wm8350,
1035 WM8350_GPIO_INT_STATUS_MASK,
1036 WM8350_IM_GP7_EINT);
1037 case WM8350_IRQ_GPIO(8):
1038 return wm8350_clear_bits(wm8350,
1039 WM8350_GPIO_INT_STATUS_MASK,
1040 WM8350_IM_GP8_EINT);
1041 case WM8350_IRQ_GPIO(9):
1042 return wm8350_clear_bits(wm8350,
1043 WM8350_GPIO_INT_STATUS_MASK,
1044 WM8350_IM_GP9_EINT);
1045 case WM8350_IRQ_GPIO(10):
1046 return wm8350_clear_bits(wm8350,
1047 WM8350_GPIO_INT_STATUS_MASK,
1048 WM8350_IM_GP10_EINT);
1049 case WM8350_IRQ_GPIO(11):
1050 return wm8350_clear_bits(wm8350,
1051 WM8350_GPIO_INT_STATUS_MASK,
1052 WM8350_IM_GP11_EINT);
1053 case WM8350_IRQ_GPIO(12):
1054 return wm8350_clear_bits(wm8350,
1055 WM8350_GPIO_INT_STATUS_MASK,
1056 WM8350_IM_GP12_EINT);
1057 default:
1058 dev_warn(wm8350->dev, "Attempting to unmask unknown IRQ %d\n",
1059 irq);
1060 return -EINVAL;
1061 }
1062 return 0;
1063}
1064EXPORT_SYMBOL_GPL(wm8350_unmask_irq);
1065
1066/*
1067 * Cache is always host endian.
1068 */
1069static int wm8350_create_cache(struct wm8350 *wm8350, int mode)
1070{
1071 int i, ret = 0;
1072 u16 value;
1073 const u16 *reg_map;
1074
1075 switch (mode) {
1076#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
1077 case 0:
1078 reg_map = wm8350_mode0_defaults;
1079 break;
1080#endif
1081#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
1082 case 1:
1083 reg_map = wm8350_mode1_defaults;
1084 break;
1085#endif
1086#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
1087 case 2:
1088 reg_map = wm8350_mode2_defaults;
1089 break;
1090#endif
1091#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
1092 case 3:
1093 reg_map = wm8350_mode3_defaults;
1094 break;
1095#endif
1096 default:
1097 dev_err(wm8350->dev, "Configuration mode %d not supported\n",
1098 mode);
1099 return -EINVAL;
1100 }
1101
1102 wm8350->reg_cache =
1103 kzalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
1104 if (wm8350->reg_cache == NULL)
1105 return -ENOMEM;
1106
1107 /* Read the initial cache state back from the device - this is
1108 * a PMIC so the device many not be in a virgin state and we
1109 * can't rely on the silicon values.
1110 */
1111 for (i = 0; i < WM8350_MAX_REGISTER; i++) {
1112 /* audio register range */
1113 if (wm8350_reg_io_map[i].readable &&
1114 (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
1115 ret = wm8350->read_dev(wm8350, i, 2, (char *)&value);
1116 if (ret < 0) {
1117 dev_err(wm8350->dev,
1118 "failed to read initial cache value\n");
1119 goto out;
1120 }
1121 value = be16_to_cpu(value);
1122 value &= wm8350_reg_io_map[i].readable;
1123 wm8350->reg_cache[i] = value;
1124 } else
1125 wm8350->reg_cache[i] = reg_map[i];
1126 }
1127
1128out:
1129 return ret;
1130}
1131EXPORT_SYMBOL_GPL(wm8350_create_cache);
1132
1133/*
1134 * Register a client device. This is non-fatal since there is no need to
1135 * fail the entire device init due to a single platform device failing.
1136 */
1137static void wm8350_client_dev_register(struct wm8350 *wm8350,
1138 const char *name,
1139 struct platform_device **pdev)
1140{
1141 int ret;
1142
1143 *pdev = platform_device_alloc(name, -1);
1144 if (pdev == NULL) {
1145 dev_err(wm8350->dev, "Failed to allocate %s\n", name);
1146 return;
1147 }
1148
1149 (*pdev)->dev.parent = wm8350->dev;
1150 platform_set_drvdata(*pdev, wm8350);
1151 ret = platform_device_add(*pdev);
1152 if (ret != 0) {
1153 dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
1154 platform_device_put(*pdev);
1155 *pdev = NULL;
1156 }
1157}
1158
1159int wm8350_device_init(struct wm8350 *wm8350, int irq,
1160 struct wm8350_platform_data *pdata)
1161{
1162 int ret = -EINVAL;
1163 u16 id1, id2, mask, mode;
1164
1165 /* get WM8350 revision and config mode */
1166 wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
1167 wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
1168
1169 id1 = be16_to_cpu(id1);
1170 id2 = be16_to_cpu(id2);
1171
1172 if (id1 == 0x6143) {
1173 switch ((id2 & WM8350_CHIP_REV_MASK) >> 12) {
1174 case WM8350_REV_E:
1175 dev_info(wm8350->dev, "Found Rev E device\n");
1176 wm8350->rev = WM8350_REV_E;
1177 break;
1178 case WM8350_REV_F:
1179 dev_info(wm8350->dev, "Found Rev F device\n");
1180 wm8350->rev = WM8350_REV_F;
1181 break;
1182 case WM8350_REV_G:
1183 dev_info(wm8350->dev, "Found Rev G device\n");
1184 wm8350->rev = WM8350_REV_G;
1185 break;
1186 default:
1187 /* For safety we refuse to run on unknown hardware */
1188 dev_info(wm8350->dev, "Found unknown rev\n");
1189 ret = -ENODEV;
1190 goto err;
1191 }
1192 } else {
1193 dev_info(wm8350->dev, "Device with ID %x is not a WM8350\n",
1194 id1);
1195 ret = -ENODEV;
1196 goto err;
1197 }
1198
1199 mode = id2 & WM8350_CONF_STS_MASK >> 10;
1200 mask = id2 & WM8350_CUST_ID_MASK;
1201 dev_info(wm8350->dev, "Config mode %d, ROM mask %d\n", mode, mask);
1202
1203 ret = wm8350_create_cache(wm8350, mode);
1204 if (ret < 0) {
1205 printk(KERN_ERR "wm8350: failed to create register cache\n");
1206 return ret;
1207 }
1208
1209 if (pdata->init) {
1210 ret = pdata->init(wm8350);
1211 if (ret != 0) {
1212 dev_err(wm8350->dev, "Platform init() failed: %d\n",
1213 ret);
1214 goto err;
1215 }
1216 }
1217
1218 mutex_init(&wm8350->irq_mutex);
1219 INIT_WORK(&wm8350->irq_work, wm8350_irq_worker);
1220 if (irq != NO_IRQ) {
1221 ret = request_irq(irq, wm8350_irq, 0,
1222 "wm8350", wm8350);
1223 if (ret != 0) {
1224 dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
1225 ret);
1226 goto err;
1227 }
1228 } else {
1229 dev_err(wm8350->dev, "No IRQ configured\n");
1230 goto err;
1231 }
1232 wm8350->chip_irq = irq;
1233
1234 wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
1235
1236 wm8350_client_dev_register(wm8350, "wm8350-codec",
1237 &(wm8350->codec.pdev));
1238 wm8350_client_dev_register(wm8350, "wm8350-gpio",
1239 &(wm8350->gpio.pdev));
1240 wm8350_client_dev_register(wm8350, "wm8350-power",
1241 &(wm8350->power.pdev));
1242 wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
1243 wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
1244
1245 return 0;
1246
1247err:
1248 kfree(wm8350->reg_cache);
1249 return ret;
1250}
1251EXPORT_SYMBOL_GPL(wm8350_device_init);
1252
1253void wm8350_device_exit(struct wm8350 *wm8350)
1254{
1255 int i;
1256
1257 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
1258 platform_device_unregister(wm8350->pmic.pdev[i]);
1259
1260 platform_device_unregister(wm8350->wdt.pdev);
1261 platform_device_unregister(wm8350->rtc.pdev);
1262 platform_device_unregister(wm8350->power.pdev);
1263 platform_device_unregister(wm8350->gpio.pdev);
1264 platform_device_unregister(wm8350->codec.pdev);
1265
1266 free_irq(wm8350->chip_irq, wm8350);
1267 flush_work(&wm8350->irq_work);
1268 kfree(wm8350->reg_cache);
1269}
1270EXPORT_SYMBOL_GPL(wm8350_device_exit);
1271
1272MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
1273MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/wm8350-gpio.c b/drivers/mfd/wm8350-gpio.c
new file mode 100644
index 000000000000..ebf99bef392f
--- /dev/null
+++ b/drivers/mfd/wm8350-gpio.c
@@ -0,0 +1,222 @@
1/*
2 * wm8350-core.c -- Device access for Wolfson WM8350
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/errno.h>
18
19#include <linux/mfd/wm8350/core.h>
20#include <linux/mfd/wm8350/gpio.h>
21#include <linux/mfd/wm8350/pmic.h>
22
23static int gpio_set_dir(struct wm8350 *wm8350, int gpio, int dir)
24{
25 int ret;
26
27 wm8350_reg_unlock(wm8350);
28 if (dir == WM8350_GPIO_DIR_OUT)
29 ret = wm8350_clear_bits(wm8350,
30 WM8350_GPIO_CONFIGURATION_I_O,
31 1 << gpio);
32 else
33 ret = wm8350_set_bits(wm8350,
34 WM8350_GPIO_CONFIGURATION_I_O,
35 1 << gpio);
36 wm8350_reg_lock(wm8350);
37 return ret;
38}
39
40static int gpio_set_debounce(struct wm8350 *wm8350, int gpio, int db)
41{
42 if (db == WM8350_GPIO_DEBOUNCE_ON)
43 return wm8350_set_bits(wm8350, WM8350_GPIO_DEBOUNCE,
44 1 << gpio);
45 else
46 return wm8350_clear_bits(wm8350,
47 WM8350_GPIO_DEBOUNCE, 1 << gpio);
48}
49
50static int gpio_set_func(struct wm8350 *wm8350, int gpio, int func)
51{
52 u16 reg;
53
54 wm8350_reg_unlock(wm8350);
55 switch (gpio) {
56 case 0:
57 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
58 & ~WM8350_GP0_FN_MASK;
59 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1,
60 reg | ((func & 0xf) << 0));
61 break;
62 case 1:
63 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
64 & ~WM8350_GP1_FN_MASK;
65 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1,
66 reg | ((func & 0xf) << 4));
67 break;
68 case 2:
69 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
70 & ~WM8350_GP2_FN_MASK;
71 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1,
72 reg | ((func & 0xf) << 8));
73 break;
74 case 3:
75 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
76 & ~WM8350_GP3_FN_MASK;
77 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1,
78 reg | ((func & 0xf) << 12));
79 break;
80 case 4:
81 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2)
82 & ~WM8350_GP4_FN_MASK;
83 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2,
84 reg | ((func & 0xf) << 0));
85 break;
86 case 5:
87 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2)
88 & ~WM8350_GP5_FN_MASK;
89 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2,
90 reg | ((func & 0xf) << 4));
91 break;
92 case 6:
93 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2)
94 & ~WM8350_GP6_FN_MASK;
95 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2,
96 reg | ((func & 0xf) << 8));
97 break;
98 case 7:
99 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2)
100 & ~WM8350_GP7_FN_MASK;
101 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2,
102 reg | ((func & 0xf) << 12));
103 break;
104 case 8:
105 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3)
106 & ~WM8350_GP8_FN_MASK;
107 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3,
108 reg | ((func & 0xf) << 0));
109 break;
110 case 9:
111 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3)
112 & ~WM8350_GP9_FN_MASK;
113 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3,
114 reg | ((func & 0xf) << 4));
115 break;
116 case 10:
117 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3)
118 & ~WM8350_GP10_FN_MASK;
119 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3,
120 reg | ((func & 0xf) << 8));
121 break;
122 case 11:
123 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3)
124 & ~WM8350_GP11_FN_MASK;
125 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3,
126 reg | ((func & 0xf) << 12));
127 break;
128 case 12:
129 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_4)
130 & ~WM8350_GP12_FN_MASK;
131 wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_4,
132 reg | ((func & 0xf) << 0));
133 break;
134 default:
135 wm8350_reg_lock(wm8350);
136 return -EINVAL;
137 }
138
139 wm8350_reg_lock(wm8350);
140 return 0;
141}
142
143static int gpio_set_pull_up(struct wm8350 *wm8350, int gpio, int up)
144{
145 if (up)
146 return wm8350_set_bits(wm8350,
147 WM8350_GPIO_PIN_PULL_UP_CONTROL,
148 1 << gpio);
149 else
150 return wm8350_clear_bits(wm8350,
151 WM8350_GPIO_PIN_PULL_UP_CONTROL,
152 1 << gpio);
153}
154
155static int gpio_set_pull_down(struct wm8350 *wm8350, int gpio, int down)
156{
157 if (down)
158 return wm8350_set_bits(wm8350,
159 WM8350_GPIO_PULL_DOWN_CONTROL,
160 1 << gpio);
161 else
162 return wm8350_clear_bits(wm8350,
163 WM8350_GPIO_PULL_DOWN_CONTROL,
164 1 << gpio);
165}
166
167static int gpio_set_polarity(struct wm8350 *wm8350, int gpio, int pol)
168{
169 if (pol == WM8350_GPIO_ACTIVE_HIGH)
170 return wm8350_set_bits(wm8350,
171 WM8350_GPIO_PIN_POLARITY_TYPE,
172 1 << gpio);
173 else
174 return wm8350_clear_bits(wm8350,
175 WM8350_GPIO_PIN_POLARITY_TYPE,
176 1 << gpio);
177}
178
179static int gpio_set_invert(struct wm8350 *wm8350, int gpio, int invert)
180{
181 if (invert == WM8350_GPIO_INVERT_ON)
182 return wm8350_set_bits(wm8350, WM8350_GPIO_INT_MODE, 1 << gpio);
183 else
184 return wm8350_clear_bits(wm8350,
185 WM8350_GPIO_INT_MODE, 1 << gpio);
186}
187
188int wm8350_gpio_config(struct wm8350 *wm8350, int gpio, int dir, int func,
189 int pol, int pull, int invert, int debounce)
190{
191 /* make sure we never pull up and down at the same time */
192 if (pull == WM8350_GPIO_PULL_NONE) {
193 if (gpio_set_pull_up(wm8350, gpio, 0))
194 goto err;
195 if (gpio_set_pull_down(wm8350, gpio, 0))
196 goto err;
197 } else if (pull == WM8350_GPIO_PULL_UP) {
198 if (gpio_set_pull_down(wm8350, gpio, 0))
199 goto err;
200 if (gpio_set_pull_up(wm8350, gpio, 1))
201 goto err;
202 } else if (pull == WM8350_GPIO_PULL_DOWN) {
203 if (gpio_set_pull_up(wm8350, gpio, 0))
204 goto err;
205 if (gpio_set_pull_down(wm8350, gpio, 1))
206 goto err;
207 }
208
209 if (gpio_set_invert(wm8350, gpio, invert))
210 goto err;
211 if (gpio_set_polarity(wm8350, gpio, pol))
212 goto err;
213 if (gpio_set_debounce(wm8350, gpio, debounce))
214 goto err;
215 if (gpio_set_dir(wm8350, gpio, dir))
216 goto err;
217 return gpio_set_func(wm8350, gpio, func);
218
219err:
220 return -EIO;
221}
222EXPORT_SYMBOL_GPL(wm8350_gpio_config);
diff --git a/drivers/mfd/wm8350-i2c.c b/drivers/mfd/wm8350-i2c.c
new file mode 100644
index 000000000000..8dfe21bb3bd1
--- /dev/null
+++ b/drivers/mfd/wm8350-i2c.c
@@ -0,0 +1,120 @@
1/*
2 * wm8350-i2c.c -- Generic I2C driver for Wolfson WM8350 PMIC
3 *
4 * This driver defines and configures the WM8350 for the Freescale i.MX32ADS.
5 *
6 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
7 *
8 * Author: Liam Girdwood
9 * linux@wolfsonmicro.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
21#include <linux/i2c.h>
22#include <linux/platform_device.h>
23#include <linux/mfd/wm8350/core.h>
24
25static int wm8350_i2c_read_device(struct wm8350 *wm8350, char reg,
26 int bytes, void *dest)
27{
28 int ret;
29
30 ret = i2c_master_send(wm8350->i2c_client, &reg, 1);
31 if (ret < 0)
32 return ret;
33 return i2c_master_recv(wm8350->i2c_client, dest, bytes);
34}
35
36static int wm8350_i2c_write_device(struct wm8350 *wm8350, char reg,
37 int bytes, void *src)
38{
39 /* we add 1 byte for device register */
40 u8 msg[(WM8350_MAX_REGISTER << 1) + 1];
41
42 if (bytes > ((WM8350_MAX_REGISTER << 1) + 1))
43 return -EINVAL;
44
45 msg[0] = reg;
46 memcpy(&msg[1], src, bytes);
47 return i2c_master_send(wm8350->i2c_client, msg, bytes + 1);
48}
49
50static int wm8350_i2c_probe(struct i2c_client *i2c,
51 const struct i2c_device_id *id)
52{
53 struct wm8350 *wm8350;
54 int ret = 0;
55
56 wm8350 = kzalloc(sizeof(struct wm8350), GFP_KERNEL);
57 if (wm8350 == NULL) {
58 kfree(i2c);
59 return -ENOMEM;
60 }
61
62 i2c_set_clientdata(i2c, wm8350);
63 wm8350->dev = &i2c->dev;
64 wm8350->i2c_client = i2c;
65 wm8350->read_dev = wm8350_i2c_read_device;
66 wm8350->write_dev = wm8350_i2c_write_device;
67
68 ret = wm8350_device_init(wm8350, i2c->irq, i2c->dev.platform_data);
69 if (ret < 0)
70 goto err;
71
72 return ret;
73
74err:
75 kfree(wm8350);
76 return ret;
77}
78
79static int wm8350_i2c_remove(struct i2c_client *i2c)
80{
81 struct wm8350 *wm8350 = i2c_get_clientdata(i2c);
82
83 wm8350_device_exit(wm8350);
84 kfree(wm8350);
85
86 return 0;
87}
88
89static const struct i2c_device_id wm8350_i2c_id[] = {
90 { "wm8350", 0 },
91 { }
92};
93MODULE_DEVICE_TABLE(i2c, wm8350_i2c_id);
94
95
96static struct i2c_driver wm8350_i2c_driver = {
97 .driver = {
98 .name = "wm8350",
99 .owner = THIS_MODULE,
100 },
101 .probe = wm8350_i2c_probe,
102 .remove = wm8350_i2c_remove,
103 .id_table = wm8350_i2c_id,
104};
105
106static int __init wm8350_i2c_init(void)
107{
108 return i2c_add_driver(&wm8350_i2c_driver);
109}
110/* init early so consumer devices can complete system boot */
111subsys_initcall(wm8350_i2c_init);
112
113static void __exit wm8350_i2c_exit(void)
114{
115 i2c_del_driver(&wm8350_i2c_driver);
116}
117module_exit(wm8350_i2c_exit);
118
119MODULE_DESCRIPTION("I2C support for the WM8350 AudioPlus PMIC");
120MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/wm8350-regmap.c b/drivers/mfd/wm8350-regmap.c
new file mode 100644
index 000000000000..974678db22cd
--- /dev/null
+++ b/drivers/mfd/wm8350-regmap.c
@@ -0,0 +1,1347 @@
1/*
2 * wm8350-regmap.c -- Wolfson Microelectronics WM8350 register map
3 *
4 * This file splits out the tables describing the defaults and access
5 * status of the WM8350 registers since they are rather large.
6 *
7 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/mfd/wm8350/core.h>
16
17#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
18
19#undef WM8350_HAVE_CONFIG_MODE
20#define WM8350_HAVE_CONFIG_MODE
21
22const u16 wm8350_mode0_defaults[] = {
23 0x17FF, /* R0 - Reset/ID */
24 0x1000, /* R1 - ID */
25 0x0000, /* R2 */
26 0x1002, /* R3 - System Control 1 */
27 0x0004, /* R4 - System Control 2 */
28 0x0000, /* R5 - System Hibernate */
29 0x8A00, /* R6 - Interface Control */
30 0x0000, /* R7 */
31 0x8000, /* R8 - Power mgmt (1) */
32 0x0000, /* R9 - Power mgmt (2) */
33 0x0000, /* R10 - Power mgmt (3) */
34 0x2000, /* R11 - Power mgmt (4) */
35 0x0E00, /* R12 - Power mgmt (5) */
36 0x0000, /* R13 - Power mgmt (6) */
37 0x0000, /* R14 - Power mgmt (7) */
38 0x0000, /* R15 */
39 0x0000, /* R16 - RTC Seconds/Minutes */
40 0x0100, /* R17 - RTC Hours/Day */
41 0x0101, /* R18 - RTC Date/Month */
42 0x1400, /* R19 - RTC Year */
43 0x0000, /* R20 - Alarm Seconds/Minutes */
44 0x0000, /* R21 - Alarm Hours/Day */
45 0x0000, /* R22 - Alarm Date/Month */
46 0x0320, /* R23 - RTC Time Control */
47 0x0000, /* R24 - System Interrupts */
48 0x0000, /* R25 - Interrupt Status 1 */
49 0x0000, /* R26 - Interrupt Status 2 */
50 0x0000, /* R27 - Power Up Interrupt Status */
51 0x0000, /* R28 - Under Voltage Interrupt status */
52 0x0000, /* R29 - Over Current Interrupt status */
53 0x0000, /* R30 - GPIO Interrupt Status */
54 0x0000, /* R31 - Comparator Interrupt Status */
55 0x3FFF, /* R32 - System Interrupts Mask */
56 0x0000, /* R33 - Interrupt Status 1 Mask */
57 0x0000, /* R34 - Interrupt Status 2 Mask */
58 0x0000, /* R35 - Power Up Interrupt Status Mask */
59 0x0000, /* R36 - Under Voltage Interrupt status Mask */
60 0x0000, /* R37 - Over Current Interrupt status Mask */
61 0x0000, /* R38 - GPIO Interrupt Status Mask */
62 0x0000, /* R39 - Comparator Interrupt Status Mask */
63 0x0040, /* R40 - Clock Control 1 */
64 0x0000, /* R41 - Clock Control 2 */
65 0x3B00, /* R42 - FLL Control 1 */
66 0x7086, /* R43 - FLL Control 2 */
67 0xC226, /* R44 - FLL Control 3 */
68 0x0000, /* R45 - FLL Control 4 */
69 0x0000, /* R46 */
70 0x0000, /* R47 */
71 0x0000, /* R48 - DAC Control */
72 0x0000, /* R49 */
73 0x00C0, /* R50 - DAC Digital Volume L */
74 0x00C0, /* R51 - DAC Digital Volume R */
75 0x0000, /* R52 */
76 0x0040, /* R53 - DAC LR Rate */
77 0x0000, /* R54 - DAC Clock Control */
78 0x0000, /* R55 */
79 0x0000, /* R56 */
80 0x0000, /* R57 */
81 0x4000, /* R58 - DAC Mute */
82 0x0000, /* R59 - DAC Mute Volume */
83 0x0000, /* R60 - DAC Side */
84 0x0000, /* R61 */
85 0x0000, /* R62 */
86 0x0000, /* R63 */
87 0x8000, /* R64 - ADC Control */
88 0x0000, /* R65 */
89 0x00C0, /* R66 - ADC Digital Volume L */
90 0x00C0, /* R67 - ADC Digital Volume R */
91 0x0000, /* R68 - ADC Divider */
92 0x0000, /* R69 */
93 0x0040, /* R70 - ADC LR Rate */
94 0x0000, /* R71 */
95 0x0303, /* R72 - Input Control */
96 0x0000, /* R73 - IN3 Input Control */
97 0x0000, /* R74 - Mic Bias Control */
98 0x0000, /* R75 */
99 0x0000, /* R76 - Output Control */
100 0x0000, /* R77 - Jack Detect */
101 0x0000, /* R78 - Anti Pop Control */
102 0x0000, /* R79 */
103 0x0040, /* R80 - Left Input Volume */
104 0x0040, /* R81 - Right Input Volume */
105 0x0000, /* R82 */
106 0x0000, /* R83 */
107 0x0000, /* R84 */
108 0x0000, /* R85 */
109 0x0000, /* R86 */
110 0x0000, /* R87 */
111 0x0800, /* R88 - Left Mixer Control */
112 0x1000, /* R89 - Right Mixer Control */
113 0x0000, /* R90 */
114 0x0000, /* R91 */
115 0x0000, /* R92 - OUT3 Mixer Control */
116 0x0000, /* R93 - OUT4 Mixer Control */
117 0x0000, /* R94 */
118 0x0000, /* R95 */
119 0x0000, /* R96 - Output Left Mixer Volume */
120 0x0000, /* R97 - Output Right Mixer Volume */
121 0x0000, /* R98 - Input Mixer Volume L */
122 0x0000, /* R99 - Input Mixer Volume R */
123 0x0000, /* R100 - Input Mixer Volume */
124 0x0000, /* R101 */
125 0x0000, /* R102 */
126 0x0000, /* R103 */
127 0x00E4, /* R104 - LOUT1 Volume */
128 0x00E4, /* R105 - ROUT1 Volume */
129 0x00E4, /* R106 - LOUT2 Volume */
130 0x02E4, /* R107 - ROUT2 Volume */
131 0x0000, /* R108 */
132 0x0000, /* R109 */
133 0x0000, /* R110 */
134 0x0000, /* R111 - BEEP Volume */
135 0x0A00, /* R112 - AI Formating */
136 0x0000, /* R113 - ADC DAC COMP */
137 0x0020, /* R114 - AI ADC Control */
138 0x0020, /* R115 - AI DAC Control */
139 0x0000, /* R116 - AIF Test */
140 0x0000, /* R117 */
141 0x0000, /* R118 */
142 0x0000, /* R119 */
143 0x0000, /* R120 */
144 0x0000, /* R121 */
145 0x0000, /* R122 */
146 0x0000, /* R123 */
147 0x0000, /* R124 */
148 0x0000, /* R125 */
149 0x0000, /* R126 */
150 0x0000, /* R127 */
151 0x1FFF, /* R128 - GPIO Debounce */
152 0x0000, /* R129 - GPIO Pin pull up Control */
153 0x03FC, /* R130 - GPIO Pull down Control */
154 0x0000, /* R131 - GPIO Interrupt Mode */
155 0x0000, /* R132 */
156 0x0000, /* R133 - GPIO Control */
157 0x0FFC, /* R134 - GPIO Configuration (i/o) */
158 0x0FFC, /* R135 - GPIO Pin Polarity / Type */
159 0x0000, /* R136 */
160 0x0000, /* R137 */
161 0x0000, /* R138 */
162 0x0000, /* R139 */
163 0x0013, /* R140 - GPIO Function Select 1 */
164 0x0000, /* R141 - GPIO Function Select 2 */
165 0x0000, /* R142 - GPIO Function Select 3 */
166 0x0003, /* R143 - GPIO Function Select 4 */
167 0x0000, /* R144 - Digitiser Control (1) */
168 0x0002, /* R145 - Digitiser Control (2) */
169 0x0000, /* R146 */
170 0x0000, /* R147 */
171 0x0000, /* R148 */
172 0x0000, /* R149 */
173 0x0000, /* R150 */
174 0x0000, /* R151 */
175 0x7000, /* R152 - AUX1 Readback */
176 0x7000, /* R153 - AUX2 Readback */
177 0x7000, /* R154 - AUX3 Readback */
178 0x7000, /* R155 - AUX4 Readback */
179 0x0000, /* R156 - USB Voltage Readback */
180 0x0000, /* R157 - LINE Voltage Readback */
181 0x0000, /* R158 - BATT Voltage Readback */
182 0x0000, /* R159 - Chip Temp Readback */
183 0x0000, /* R160 */
184 0x0000, /* R161 */
185 0x0000, /* R162 */
186 0x0000, /* R163 - Generic Comparator Control */
187 0x0000, /* R164 - Generic comparator 1 */
188 0x0000, /* R165 - Generic comparator 2 */
189 0x0000, /* R166 - Generic comparator 3 */
190 0x0000, /* R167 - Generic comparator 4 */
191 0xA00F, /* R168 - Battery Charger Control 1 */
192 0x0B06, /* R169 - Battery Charger Control 2 */
193 0x0000, /* R170 - Battery Charger Control 3 */
194 0x0000, /* R171 */
195 0x0000, /* R172 - Current Sink Driver A */
196 0x0000, /* R173 - CSA Flash control */
197 0x0000, /* R174 - Current Sink Driver B */
198 0x0000, /* R175 - CSB Flash control */
199 0x0000, /* R176 - DCDC/LDO requested */
200 0x002D, /* R177 - DCDC Active options */
201 0x0000, /* R178 - DCDC Sleep options */
202 0x0025, /* R179 - Power-check comparator */
203 0x000E, /* R180 - DCDC1 Control */
204 0x0000, /* R181 - DCDC1 Timeouts */
205 0x1006, /* R182 - DCDC1 Low Power */
206 0x0018, /* R183 - DCDC2 Control */
207 0x0000, /* R184 - DCDC2 Timeouts */
208 0x0000, /* R185 */
209 0x0000, /* R186 - DCDC3 Control */
210 0x0000, /* R187 - DCDC3 Timeouts */
211 0x0006, /* R188 - DCDC3 Low Power */
212 0x0000, /* R189 - DCDC4 Control */
213 0x0000, /* R190 - DCDC4 Timeouts */
214 0x0006, /* R191 - DCDC4 Low Power */
215 0x0008, /* R192 - DCDC5 Control */
216 0x0000, /* R193 - DCDC5 Timeouts */
217 0x0000, /* R194 */
218 0x0000, /* R195 - DCDC6 Control */
219 0x0000, /* R196 - DCDC6 Timeouts */
220 0x0006, /* R197 - DCDC6 Low Power */
221 0x0000, /* R198 */
222 0x0003, /* R199 - Limit Switch Control */
223 0x001C, /* R200 - LDO1 Control */
224 0x0000, /* R201 - LDO1 Timeouts */
225 0x001C, /* R202 - LDO1 Low Power */
226 0x001B, /* R203 - LDO2 Control */
227 0x0000, /* R204 - LDO2 Timeouts */
228 0x001C, /* R205 - LDO2 Low Power */
229 0x001B, /* R206 - LDO3 Control */
230 0x0000, /* R207 - LDO3 Timeouts */
231 0x001C, /* R208 - LDO3 Low Power */
232 0x001B, /* R209 - LDO4 Control */
233 0x0000, /* R210 - LDO4 Timeouts */
234 0x001C, /* R211 - LDO4 Low Power */
235 0x0000, /* R212 */
236 0x0000, /* R213 */
237 0x0000, /* R214 */
238 0x0000, /* R215 - VCC_FAULT Masks */
239 0x001F, /* R216 - Main Bandgap Control */
240 0x0000, /* R217 - OSC Control */
241 0x9000, /* R218 - RTC Tick Control */
242 0x0000, /* R219 */
243 0x4000, /* R220 - RAM BIST 1 */
244 0x0000, /* R221 */
245 0x0000, /* R222 */
246 0x0000, /* R223 */
247 0x0000, /* R224 */
248 0x0000, /* R225 - DCDC/LDO status */
249 0x0000, /* R226 */
250 0x0000, /* R227 */
251 0x0000, /* R228 */
252 0x0000, /* R229 */
253 0xE000, /* R230 - GPIO Pin Status */
254 0x0000, /* R231 */
255 0x0000, /* R232 */
256 0x0000, /* R233 */
257 0x0000, /* R234 */
258 0x0000, /* R235 */
259 0x0000, /* R236 */
260 0x0000, /* R237 */
261 0x0000, /* R238 */
262 0x0000, /* R239 */
263 0x0000, /* R240 */
264 0x0000, /* R241 */
265 0x0000, /* R242 */
266 0x0000, /* R243 */
267 0x0000, /* R244 */
268 0x0000, /* R245 */
269 0x0000, /* R246 */
270 0x0000, /* R247 */
271 0x0000, /* R248 */
272 0x0000, /* R249 */
273 0x0000, /* R250 */
274 0x0000, /* R251 */
275 0x0000, /* R252 */
276 0x0000, /* R253 */
277 0x0000, /* R254 */
278 0x0000, /* R255 */
279};
280#endif
281
282#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
283
284#undef WM8350_HAVE_CONFIG_MODE
285#define WM8350_HAVE_CONFIG_MODE
286
287const u16 wm8350_mode1_defaults[] = {
288 0x17FF, /* R0 - Reset/ID */
289 0x1000, /* R1 - ID */
290 0x0000, /* R2 */
291 0x1002, /* R3 - System Control 1 */
292 0x0014, /* R4 - System Control 2 */
293 0x0000, /* R5 - System Hibernate */
294 0x8A00, /* R6 - Interface Control */
295 0x0000, /* R7 */
296 0x8000, /* R8 - Power mgmt (1) */
297 0x0000, /* R9 - Power mgmt (2) */
298 0x0000, /* R10 - Power mgmt (3) */
299 0x2000, /* R11 - Power mgmt (4) */
300 0x0E00, /* R12 - Power mgmt (5) */
301 0x0000, /* R13 - Power mgmt (6) */
302 0x0000, /* R14 - Power mgmt (7) */
303 0x0000, /* R15 */
304 0x0000, /* R16 - RTC Seconds/Minutes */
305 0x0100, /* R17 - RTC Hours/Day */
306 0x0101, /* R18 - RTC Date/Month */
307 0x1400, /* R19 - RTC Year */
308 0x0000, /* R20 - Alarm Seconds/Minutes */
309 0x0000, /* R21 - Alarm Hours/Day */
310 0x0000, /* R22 - Alarm Date/Month */
311 0x0320, /* R23 - RTC Time Control */
312 0x0000, /* R24 - System Interrupts */
313 0x0000, /* R25 - Interrupt Status 1 */
314 0x0000, /* R26 - Interrupt Status 2 */
315 0x0000, /* R27 - Power Up Interrupt Status */
316 0x0000, /* R28 - Under Voltage Interrupt status */
317 0x0000, /* R29 - Over Current Interrupt status */
318 0x0000, /* R30 - GPIO Interrupt Status */
319 0x0000, /* R31 - Comparator Interrupt Status */
320 0x3FFF, /* R32 - System Interrupts Mask */
321 0x0000, /* R33 - Interrupt Status 1 Mask */
322 0x0000, /* R34 - Interrupt Status 2 Mask */
323 0x0000, /* R35 - Power Up Interrupt Status Mask */
324 0x0000, /* R36 - Under Voltage Interrupt status Mask */
325 0x0000, /* R37 - Over Current Interrupt status Mask */
326 0x0000, /* R38 - GPIO Interrupt Status Mask */
327 0x0000, /* R39 - Comparator Interrupt Status Mask */
328 0x0040, /* R40 - Clock Control 1 */
329 0x0000, /* R41 - Clock Control 2 */
330 0x3B00, /* R42 - FLL Control 1 */
331 0x7086, /* R43 - FLL Control 2 */
332 0xC226, /* R44 - FLL Control 3 */
333 0x0000, /* R45 - FLL Control 4 */
334 0x0000, /* R46 */
335 0x0000, /* R47 */
336 0x0000, /* R48 - DAC Control */
337 0x0000, /* R49 */
338 0x00C0, /* R50 - DAC Digital Volume L */
339 0x00C0, /* R51 - DAC Digital Volume R */
340 0x0000, /* R52 */
341 0x0040, /* R53 - DAC LR Rate */
342 0x0000, /* R54 - DAC Clock Control */
343 0x0000, /* R55 */
344 0x0000, /* R56 */
345 0x0000, /* R57 */
346 0x4000, /* R58 - DAC Mute */
347 0x0000, /* R59 - DAC Mute Volume */
348 0x0000, /* R60 - DAC Side */
349 0x0000, /* R61 */
350 0x0000, /* R62 */
351 0x0000, /* R63 */
352 0x8000, /* R64 - ADC Control */
353 0x0000, /* R65 */
354 0x00C0, /* R66 - ADC Digital Volume L */
355 0x00C0, /* R67 - ADC Digital Volume R */
356 0x0000, /* R68 - ADC Divider */
357 0x0000, /* R69 */
358 0x0040, /* R70 - ADC LR Rate */
359 0x0000, /* R71 */
360 0x0303, /* R72 - Input Control */
361 0x0000, /* R73 - IN3 Input Control */
362 0x0000, /* R74 - Mic Bias Control */
363 0x0000, /* R75 */
364 0x0000, /* R76 - Output Control */
365 0x0000, /* R77 - Jack Detect */
366 0x0000, /* R78 - Anti Pop Control */
367 0x0000, /* R79 */
368 0x0040, /* R80 - Left Input Volume */
369 0x0040, /* R81 - Right Input Volume */
370 0x0000, /* R82 */
371 0x0000, /* R83 */
372 0x0000, /* R84 */
373 0x0000, /* R85 */
374 0x0000, /* R86 */
375 0x0000, /* R87 */
376 0x0800, /* R88 - Left Mixer Control */
377 0x1000, /* R89 - Right Mixer Control */
378 0x0000, /* R90 */
379 0x0000, /* R91 */
380 0x0000, /* R92 - OUT3 Mixer Control */
381 0x0000, /* R93 - OUT4 Mixer Control */
382 0x0000, /* R94 */
383 0x0000, /* R95 */
384 0x0000, /* R96 - Output Left Mixer Volume */
385 0x0000, /* R97 - Output Right Mixer Volume */
386 0x0000, /* R98 - Input Mixer Volume L */
387 0x0000, /* R99 - Input Mixer Volume R */
388 0x0000, /* R100 - Input Mixer Volume */
389 0x0000, /* R101 */
390 0x0000, /* R102 */
391 0x0000, /* R103 */
392 0x00E4, /* R104 - LOUT1 Volume */
393 0x00E4, /* R105 - ROUT1 Volume */
394 0x00E4, /* R106 - LOUT2 Volume */
395 0x02E4, /* R107 - ROUT2 Volume */
396 0x0000, /* R108 */
397 0x0000, /* R109 */
398 0x0000, /* R110 */
399 0x0000, /* R111 - BEEP Volume */
400 0x0A00, /* R112 - AI Formating */
401 0x0000, /* R113 - ADC DAC COMP */
402 0x0020, /* R114 - AI ADC Control */
403 0x0020, /* R115 - AI DAC Control */
404 0x0000, /* R116 - AIF Test */
405 0x0000, /* R117 */
406 0x0000, /* R118 */
407 0x0000, /* R119 */
408 0x0000, /* R120 */
409 0x0000, /* R121 */
410 0x0000, /* R122 */
411 0x0000, /* R123 */
412 0x0000, /* R124 */
413 0x0000, /* R125 */
414 0x0000, /* R126 */
415 0x0000, /* R127 */
416 0x1FFF, /* R128 - GPIO Debounce */
417 0x0000, /* R129 - GPIO Pin pull up Control */
418 0x03FC, /* R130 - GPIO Pull down Control */
419 0x0000, /* R131 - GPIO Interrupt Mode */
420 0x0000, /* R132 */
421 0x0000, /* R133 - GPIO Control */
422 0x00FB, /* R134 - GPIO Configuration (i/o) */
423 0x04FE, /* R135 - GPIO Pin Polarity / Type */
424 0x0000, /* R136 */
425 0x0000, /* R137 */
426 0x0000, /* R138 */
427 0x0000, /* R139 */
428 0x0312, /* R140 - GPIO Function Select 1 */
429 0x1003, /* R141 - GPIO Function Select 2 */
430 0x1331, /* R142 - GPIO Function Select 3 */
431 0x0003, /* R143 - GPIO Function Select 4 */
432 0x0000, /* R144 - Digitiser Control (1) */
433 0x0002, /* R145 - Digitiser Control (2) */
434 0x0000, /* R146 */
435 0x0000, /* R147 */
436 0x0000, /* R148 */
437 0x0000, /* R149 */
438 0x0000, /* R150 */
439 0x0000, /* R151 */
440 0x7000, /* R152 - AUX1 Readback */
441 0x7000, /* R153 - AUX2 Readback */
442 0x7000, /* R154 - AUX3 Readback */
443 0x7000, /* R155 - AUX4 Readback */
444 0x0000, /* R156 - USB Voltage Readback */
445 0x0000, /* R157 - LINE Voltage Readback */
446 0x0000, /* R158 - BATT Voltage Readback */
447 0x0000, /* R159 - Chip Temp Readback */
448 0x0000, /* R160 */
449 0x0000, /* R161 */
450 0x0000, /* R162 */
451 0x0000, /* R163 - Generic Comparator Control */
452 0x0000, /* R164 - Generic comparator 1 */
453 0x0000, /* R165 - Generic comparator 2 */
454 0x0000, /* R166 - Generic comparator 3 */
455 0x0000, /* R167 - Generic comparator 4 */
456 0xA00F, /* R168 - Battery Charger Control 1 */
457 0x0B06, /* R169 - Battery Charger Control 2 */
458 0x0000, /* R170 - Battery Charger Control 3 */
459 0x0000, /* R171 */
460 0x0000, /* R172 - Current Sink Driver A */
461 0x0000, /* R173 - CSA Flash control */
462 0x0000, /* R174 - Current Sink Driver B */
463 0x0000, /* R175 - CSB Flash control */
464 0x0000, /* R176 - DCDC/LDO requested */
465 0x002D, /* R177 - DCDC Active options */
466 0x0000, /* R178 - DCDC Sleep options */
467 0x0025, /* R179 - Power-check comparator */
468 0x0062, /* R180 - DCDC1 Control */
469 0x0400, /* R181 - DCDC1 Timeouts */
470 0x1006, /* R182 - DCDC1 Low Power */
471 0x0018, /* R183 - DCDC2 Control */
472 0x0000, /* R184 - DCDC2 Timeouts */
473 0x0000, /* R185 */
474 0x0026, /* R186 - DCDC3 Control */
475 0x0400, /* R187 - DCDC3 Timeouts */
476 0x0006, /* R188 - DCDC3 Low Power */
477 0x0062, /* R189 - DCDC4 Control */
478 0x0400, /* R190 - DCDC4 Timeouts */
479 0x0006, /* R191 - DCDC4 Low Power */
480 0x0008, /* R192 - DCDC5 Control */
481 0x0000, /* R193 - DCDC5 Timeouts */
482 0x0000, /* R194 */
483 0x0026, /* R195 - DCDC6 Control */
484 0x0800, /* R196 - DCDC6 Timeouts */
485 0x0006, /* R197 - DCDC6 Low Power */
486 0x0000, /* R198 */
487 0x0003, /* R199 - Limit Switch Control */
488 0x0006, /* R200 - LDO1 Control */
489 0x0400, /* R201 - LDO1 Timeouts */
490 0x001C, /* R202 - LDO1 Low Power */
491 0x0006, /* R203 - LDO2 Control */
492 0x0400, /* R204 - LDO2 Timeouts */
493 0x001C, /* R205 - LDO2 Low Power */
494 0x001B, /* R206 - LDO3 Control */
495 0x0000, /* R207 - LDO3 Timeouts */
496 0x001C, /* R208 - LDO3 Low Power */
497 0x001B, /* R209 - LDO4 Control */
498 0x0000, /* R210 - LDO4 Timeouts */
499 0x001C, /* R211 - LDO4 Low Power */
500 0x0000, /* R212 */
501 0x0000, /* R213 */
502 0x0000, /* R214 */
503 0x0000, /* R215 - VCC_FAULT Masks */
504 0x001F, /* R216 - Main Bandgap Control */
505 0x0000, /* R217 - OSC Control */
506 0x9000, /* R218 - RTC Tick Control */
507 0x0000, /* R219 */
508 0x4000, /* R220 - RAM BIST 1 */
509 0x0000, /* R221 */
510 0x0000, /* R222 */
511 0x0000, /* R223 */
512 0x0000, /* R224 */
513 0x0000, /* R225 - DCDC/LDO status */
514 0x0000, /* R226 */
515 0x0000, /* R227 */
516 0x0000, /* R228 */
517 0x0000, /* R229 */
518 0xE000, /* R230 - GPIO Pin Status */
519 0x0000, /* R231 */
520 0x0000, /* R232 */
521 0x0000, /* R233 */
522 0x0000, /* R234 */
523 0x0000, /* R235 */
524 0x0000, /* R236 */
525 0x0000, /* R237 */
526 0x0000, /* R238 */
527 0x0000, /* R239 */
528 0x0000, /* R240 */
529 0x0000, /* R241 */
530 0x0000, /* R242 */
531 0x0000, /* R243 */
532 0x0000, /* R244 */
533 0x0000, /* R245 */
534 0x0000, /* R246 */
535 0x0000, /* R247 */
536 0x0000, /* R248 */
537 0x0000, /* R249 */
538 0x0000, /* R250 */
539 0x0000, /* R251 */
540 0x0000, /* R252 */
541 0x0000, /* R253 */
542 0x0000, /* R254 */
543 0x0000, /* R255 */
544};
545#endif
546
547#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
548
549#undef WM8350_HAVE_CONFIG_MODE
550#define WM8350_HAVE_CONFIG_MODE
551
552const u16 wm8350_mode2_defaults[] = {
553 0x17FF, /* R0 - Reset/ID */
554 0x1000, /* R1 - ID */
555 0x0000, /* R2 */
556 0x1002, /* R3 - System Control 1 */
557 0x0014, /* R4 - System Control 2 */
558 0x0000, /* R5 - System Hibernate */
559 0x8A00, /* R6 - Interface Control */
560 0x0000, /* R7 */
561 0x8000, /* R8 - Power mgmt (1) */
562 0x0000, /* R9 - Power mgmt (2) */
563 0x0000, /* R10 - Power mgmt (3) */
564 0x2000, /* R11 - Power mgmt (4) */
565 0x0E00, /* R12 - Power mgmt (5) */
566 0x0000, /* R13 - Power mgmt (6) */
567 0x0000, /* R14 - Power mgmt (7) */
568 0x0000, /* R15 */
569 0x0000, /* R16 - RTC Seconds/Minutes */
570 0x0100, /* R17 - RTC Hours/Day */
571 0x0101, /* R18 - RTC Date/Month */
572 0x1400, /* R19 - RTC Year */
573 0x0000, /* R20 - Alarm Seconds/Minutes */
574 0x0000, /* R21 - Alarm Hours/Day */
575 0x0000, /* R22 - Alarm Date/Month */
576 0x0320, /* R23 - RTC Time Control */
577 0x0000, /* R24 - System Interrupts */
578 0x0000, /* R25 - Interrupt Status 1 */
579 0x0000, /* R26 - Interrupt Status 2 */
580 0x0000, /* R27 - Power Up Interrupt Status */
581 0x0000, /* R28 - Under Voltage Interrupt status */
582 0x0000, /* R29 - Over Current Interrupt status */
583 0x0000, /* R30 - GPIO Interrupt Status */
584 0x0000, /* R31 - Comparator Interrupt Status */
585 0x3FFF, /* R32 - System Interrupts Mask */
586 0x0000, /* R33 - Interrupt Status 1 Mask */
587 0x0000, /* R34 - Interrupt Status 2 Mask */
588 0x0000, /* R35 - Power Up Interrupt Status Mask */
589 0x0000, /* R36 - Under Voltage Interrupt status Mask */
590 0x0000, /* R37 - Over Current Interrupt status Mask */
591 0x0000, /* R38 - GPIO Interrupt Status Mask */
592 0x0000, /* R39 - Comparator Interrupt Status Mask */
593 0x0040, /* R40 - Clock Control 1 */
594 0x0000, /* R41 - Clock Control 2 */
595 0x3B00, /* R42 - FLL Control 1 */
596 0x7086, /* R43 - FLL Control 2 */
597 0xC226, /* R44 - FLL Control 3 */
598 0x0000, /* R45 - FLL Control 4 */
599 0x0000, /* R46 */
600 0x0000, /* R47 */
601 0x0000, /* R48 - DAC Control */
602 0x0000, /* R49 */
603 0x00C0, /* R50 - DAC Digital Volume L */
604 0x00C0, /* R51 - DAC Digital Volume R */
605 0x0000, /* R52 */
606 0x0040, /* R53 - DAC LR Rate */
607 0x0000, /* R54 - DAC Clock Control */
608 0x0000, /* R55 */
609 0x0000, /* R56 */
610 0x0000, /* R57 */
611 0x4000, /* R58 - DAC Mute */
612 0x0000, /* R59 - DAC Mute Volume */
613 0x0000, /* R60 - DAC Side */
614 0x0000, /* R61 */
615 0x0000, /* R62 */
616 0x0000, /* R63 */
617 0x8000, /* R64 - ADC Control */
618 0x0000, /* R65 */
619 0x00C0, /* R66 - ADC Digital Volume L */
620 0x00C0, /* R67 - ADC Digital Volume R */
621 0x0000, /* R68 - ADC Divider */
622 0x0000, /* R69 */
623 0x0040, /* R70 - ADC LR Rate */
624 0x0000, /* R71 */
625 0x0303, /* R72 - Input Control */
626 0x0000, /* R73 - IN3 Input Control */
627 0x0000, /* R74 - Mic Bias Control */
628 0x0000, /* R75 */
629 0x0000, /* R76 - Output Control */
630 0x0000, /* R77 - Jack Detect */
631 0x0000, /* R78 - Anti Pop Control */
632 0x0000, /* R79 */
633 0x0040, /* R80 - Left Input Volume */
634 0x0040, /* R81 - Right Input Volume */
635 0x0000, /* R82 */
636 0x0000, /* R83 */
637 0x0000, /* R84 */
638 0x0000, /* R85 */
639 0x0000, /* R86 */
640 0x0000, /* R87 */
641 0x0800, /* R88 - Left Mixer Control */
642 0x1000, /* R89 - Right Mixer Control */
643 0x0000, /* R90 */
644 0x0000, /* R91 */
645 0x0000, /* R92 - OUT3 Mixer Control */
646 0x0000, /* R93 - OUT4 Mixer Control */
647 0x0000, /* R94 */
648 0x0000, /* R95 */
649 0x0000, /* R96 - Output Left Mixer Volume */
650 0x0000, /* R97 - Output Right Mixer Volume */
651 0x0000, /* R98 - Input Mixer Volume L */
652 0x0000, /* R99 - Input Mixer Volume R */
653 0x0000, /* R100 - Input Mixer Volume */
654 0x0000, /* R101 */
655 0x0000, /* R102 */
656 0x0000, /* R103 */
657 0x00E4, /* R104 - LOUT1 Volume */
658 0x00E4, /* R105 - ROUT1 Volume */
659 0x00E4, /* R106 - LOUT2 Volume */
660 0x02E4, /* R107 - ROUT2 Volume */
661 0x0000, /* R108 */
662 0x0000, /* R109 */
663 0x0000, /* R110 */
664 0x0000, /* R111 - BEEP Volume */
665 0x0A00, /* R112 - AI Formating */
666 0x0000, /* R113 - ADC DAC COMP */
667 0x0020, /* R114 - AI ADC Control */
668 0x0020, /* R115 - AI DAC Control */
669 0x0000, /* R116 - AIF Test */
670 0x0000, /* R117 */
671 0x0000, /* R118 */
672 0x0000, /* R119 */
673 0x0000, /* R120 */
674 0x0000, /* R121 */
675 0x0000, /* R122 */
676 0x0000, /* R123 */
677 0x0000, /* R124 */
678 0x0000, /* R125 */
679 0x0000, /* R126 */
680 0x0000, /* R127 */
681 0x1FFF, /* R128 - GPIO Debounce */
682 0x0000, /* R129 - GPIO Pin pull up Control */
683 0x03FC, /* R130 - GPIO Pull down Control */
684 0x0000, /* R131 - GPIO Interrupt Mode */
685 0x0000, /* R132 */
686 0x0000, /* R133 - GPIO Control */
687 0x08FB, /* R134 - GPIO Configuration (i/o) */
688 0x0CFE, /* R135 - GPIO Pin Polarity / Type */
689 0x0000, /* R136 */
690 0x0000, /* R137 */
691 0x0000, /* R138 */
692 0x0000, /* R139 */
693 0x0312, /* R140 - GPIO Function Select 1 */
694 0x0003, /* R141 - GPIO Function Select 2 */
695 0x2331, /* R142 - GPIO Function Select 3 */
696 0x0003, /* R143 - GPIO Function Select 4 */
697 0x0000, /* R144 - Digitiser Control (1) */
698 0x0002, /* R145 - Digitiser Control (2) */
699 0x0000, /* R146 */
700 0x0000, /* R147 */
701 0x0000, /* R148 */
702 0x0000, /* R149 */
703 0x0000, /* R150 */
704 0x0000, /* R151 */
705 0x7000, /* R152 - AUX1 Readback */
706 0x7000, /* R153 - AUX2 Readback */
707 0x7000, /* R154 - AUX3 Readback */
708 0x7000, /* R155 - AUX4 Readback */
709 0x0000, /* R156 - USB Voltage Readback */
710 0x0000, /* R157 - LINE Voltage Readback */
711 0x0000, /* R158 - BATT Voltage Readback */
712 0x0000, /* R159 - Chip Temp Readback */
713 0x0000, /* R160 */
714 0x0000, /* R161 */
715 0x0000, /* R162 */
716 0x0000, /* R163 - Generic Comparator Control */
717 0x0000, /* R164 - Generic comparator 1 */
718 0x0000, /* R165 - Generic comparator 2 */
719 0x0000, /* R166 - Generic comparator 3 */
720 0x0000, /* R167 - Generic comparator 4 */
721 0xA00F, /* R168 - Battery Charger Control 1 */
722 0x0B06, /* R169 - Battery Charger Control 2 */
723 0x0000, /* R170 - Battery Charger Control 3 */
724 0x0000, /* R171 */
725 0x0000, /* R172 - Current Sink Driver A */
726 0x0000, /* R173 - CSA Flash control */
727 0x0000, /* R174 - Current Sink Driver B */
728 0x0000, /* R175 - CSB Flash control */
729 0x0000, /* R176 - DCDC/LDO requested */
730 0x002D, /* R177 - DCDC Active options */
731 0x0000, /* R178 - DCDC Sleep options */
732 0x0025, /* R179 - Power-check comparator */
733 0x000E, /* R180 - DCDC1 Control */
734 0x0400, /* R181 - DCDC1 Timeouts */
735 0x1006, /* R182 - DCDC1 Low Power */
736 0x0018, /* R183 - DCDC2 Control */
737 0x0000, /* R184 - DCDC2 Timeouts */
738 0x0000, /* R185 */
739 0x002E, /* R186 - DCDC3 Control */
740 0x0800, /* R187 - DCDC3 Timeouts */
741 0x0006, /* R188 - DCDC3 Low Power */
742 0x000E, /* R189 - DCDC4 Control */
743 0x0800, /* R190 - DCDC4 Timeouts */
744 0x0006, /* R191 - DCDC4 Low Power */
745 0x0008, /* R192 - DCDC5 Control */
746 0x0000, /* R193 - DCDC5 Timeouts */
747 0x0000, /* R194 */
748 0x0026, /* R195 - DCDC6 Control */
749 0x0C00, /* R196 - DCDC6 Timeouts */
750 0x0006, /* R197 - DCDC6 Low Power */
751 0x0000, /* R198 */
752 0x0003, /* R199 - Limit Switch Control */
753 0x001A, /* R200 - LDO1 Control */
754 0x0800, /* R201 - LDO1 Timeouts */
755 0x001C, /* R202 - LDO1 Low Power */
756 0x0010, /* R203 - LDO2 Control */
757 0x0800, /* R204 - LDO2 Timeouts */
758 0x001C, /* R205 - LDO2 Low Power */
759 0x000A, /* R206 - LDO3 Control */
760 0x0C00, /* R207 - LDO3 Timeouts */
761 0x001C, /* R208 - LDO3 Low Power */
762 0x001A, /* R209 - LDO4 Control */
763 0x0800, /* R210 - LDO4 Timeouts */
764 0x001C, /* R211 - LDO4 Low Power */
765 0x0000, /* R212 */
766 0x0000, /* R213 */
767 0x0000, /* R214 */
768 0x0000, /* R215 - VCC_FAULT Masks */
769 0x001F, /* R216 - Main Bandgap Control */
770 0x0000, /* R217 - OSC Control */
771 0x9000, /* R218 - RTC Tick Control */
772 0x0000, /* R219 */
773 0x4000, /* R220 - RAM BIST 1 */
774 0x0000, /* R221 */
775 0x0000, /* R222 */
776 0x0000, /* R223 */
777 0x0000, /* R224 */
778 0x0000, /* R225 - DCDC/LDO status */
779 0x0000, /* R226 */
780 0x0000, /* R227 */
781 0x0000, /* R228 */
782 0x0000, /* R229 */
783 0xE000, /* R230 - GPIO Pin Status */
784 0x0000, /* R231 */
785 0x0000, /* R232 */
786 0x0000, /* R233 */
787 0x0000, /* R234 */
788 0x0000, /* R235 */
789 0x0000, /* R236 */
790 0x0000, /* R237 */
791 0x0000, /* R238 */
792 0x0000, /* R239 */
793 0x0000, /* R240 */
794 0x0000, /* R241 */
795 0x0000, /* R242 */
796 0x0000, /* R243 */
797 0x0000, /* R244 */
798 0x0000, /* R245 */
799 0x0000, /* R246 */
800 0x0000, /* R247 */
801 0x0000, /* R248 */
802 0x0000, /* R249 */
803 0x0000, /* R250 */
804 0x0000, /* R251 */
805 0x0000, /* R252 */
806 0x0000, /* R253 */
807 0x0000, /* R254 */
808 0x0000, /* R255 */
809};
810#endif
811
812#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
813
814#undef WM8350_HAVE_CONFIG_MODE
815#define WM8350_HAVE_CONFIG_MODE
816
817const u16 wm8350_mode3_defaults[] = {
818 0x17FF, /* R0 - Reset/ID */
819 0x1000, /* R1 - ID */
820 0x0000, /* R2 */
821 0x1000, /* R3 - System Control 1 */
822 0x0004, /* R4 - System Control 2 */
823 0x0000, /* R5 - System Hibernate */
824 0x8A00, /* R6 - Interface Control */
825 0x0000, /* R7 */
826 0x8000, /* R8 - Power mgmt (1) */
827 0x0000, /* R9 - Power mgmt (2) */
828 0x0000, /* R10 - Power mgmt (3) */
829 0x2000, /* R11 - Power mgmt (4) */
830 0x0E00, /* R12 - Power mgmt (5) */
831 0x0000, /* R13 - Power mgmt (6) */
832 0x0000, /* R14 - Power mgmt (7) */
833 0x0000, /* R15 */
834 0x0000, /* R16 - RTC Seconds/Minutes */
835 0x0100, /* R17 - RTC Hours/Day */
836 0x0101, /* R18 - RTC Date/Month */
837 0x1400, /* R19 - RTC Year */
838 0x0000, /* R20 - Alarm Seconds/Minutes */
839 0x0000, /* R21 - Alarm Hours/Day */
840 0x0000, /* R22 - Alarm Date/Month */
841 0x0320, /* R23 - RTC Time Control */
842 0x0000, /* R24 - System Interrupts */
843 0x0000, /* R25 - Interrupt Status 1 */
844 0x0000, /* R26 - Interrupt Status 2 */
845 0x0000, /* R27 - Power Up Interrupt Status */
846 0x0000, /* R28 - Under Voltage Interrupt status */
847 0x0000, /* R29 - Over Current Interrupt status */
848 0x0000, /* R30 - GPIO Interrupt Status */
849 0x0000, /* R31 - Comparator Interrupt Status */
850 0x3FFF, /* R32 - System Interrupts Mask */
851 0x0000, /* R33 - Interrupt Status 1 Mask */
852 0x0000, /* R34 - Interrupt Status 2 Mask */
853 0x0000, /* R35 - Power Up Interrupt Status Mask */
854 0x0000, /* R36 - Under Voltage Interrupt status Mask */
855 0x0000, /* R37 - Over Current Interrupt status Mask */
856 0x0000, /* R38 - GPIO Interrupt Status Mask */
857 0x0000, /* R39 - Comparator Interrupt Status Mask */
858 0x0040, /* R40 - Clock Control 1 */
859 0x0000, /* R41 - Clock Control 2 */
860 0x3B00, /* R42 - FLL Control 1 */
861 0x7086, /* R43 - FLL Control 2 */
862 0xC226, /* R44 - FLL Control 3 */
863 0x0000, /* R45 - FLL Control 4 */
864 0x0000, /* R46 */
865 0x0000, /* R47 */
866 0x0000, /* R48 - DAC Control */
867 0x0000, /* R49 */
868 0x00C0, /* R50 - DAC Digital Volume L */
869 0x00C0, /* R51 - DAC Digital Volume R */
870 0x0000, /* R52 */
871 0x0040, /* R53 - DAC LR Rate */
872 0x0000, /* R54 - DAC Clock Control */
873 0x0000, /* R55 */
874 0x0000, /* R56 */
875 0x0000, /* R57 */
876 0x4000, /* R58 - DAC Mute */
877 0x0000, /* R59 - DAC Mute Volume */
878 0x0000, /* R60 - DAC Side */
879 0x0000, /* R61 */
880 0x0000, /* R62 */
881 0x0000, /* R63 */
882 0x8000, /* R64 - ADC Control */
883 0x0000, /* R65 */
884 0x00C0, /* R66 - ADC Digital Volume L */
885 0x00C0, /* R67 - ADC Digital Volume R */
886 0x0000, /* R68 - ADC Divider */
887 0x0000, /* R69 */
888 0x0040, /* R70 - ADC LR Rate */
889 0x0000, /* R71 */
890 0x0303, /* R72 - Input Control */
891 0x0000, /* R73 - IN3 Input Control */
892 0x0000, /* R74 - Mic Bias Control */
893 0x0000, /* R75 */
894 0x0000, /* R76 - Output Control */
895 0x0000, /* R77 - Jack Detect */
896 0x0000, /* R78 - Anti Pop Control */
897 0x0000, /* R79 */
898 0x0040, /* R80 - Left Input Volume */
899 0x0040, /* R81 - Right Input Volume */
900 0x0000, /* R82 */
901 0x0000, /* R83 */
902 0x0000, /* R84 */
903 0x0000, /* R85 */
904 0x0000, /* R86 */
905 0x0000, /* R87 */
906 0x0800, /* R88 - Left Mixer Control */
907 0x1000, /* R89 - Right Mixer Control */
908 0x0000, /* R90 */
909 0x0000, /* R91 */
910 0x0000, /* R92 - OUT3 Mixer Control */
911 0x0000, /* R93 - OUT4 Mixer Control */
912 0x0000, /* R94 */
913 0x0000, /* R95 */
914 0x0000, /* R96 - Output Left Mixer Volume */
915 0x0000, /* R97 - Output Right Mixer Volume */
916 0x0000, /* R98 - Input Mixer Volume L */
917 0x0000, /* R99 - Input Mixer Volume R */
918 0x0000, /* R100 - Input Mixer Volume */
919 0x0000, /* R101 */
920 0x0000, /* R102 */
921 0x0000, /* R103 */
922 0x00E4, /* R104 - LOUT1 Volume */
923 0x00E4, /* R105 - ROUT1 Volume */
924 0x00E4, /* R106 - LOUT2 Volume */
925 0x02E4, /* R107 - ROUT2 Volume */
926 0x0000, /* R108 */
927 0x0000, /* R109 */
928 0x0000, /* R110 */
929 0x0000, /* R111 - BEEP Volume */
930 0x0A00, /* R112 - AI Formating */
931 0x0000, /* R113 - ADC DAC COMP */
932 0x0020, /* R114 - AI ADC Control */
933 0x0020, /* R115 - AI DAC Control */
934 0x0000, /* R116 - AIF Test */
935 0x0000, /* R117 */
936 0x0000, /* R118 */
937 0x0000, /* R119 */
938 0x0000, /* R120 */
939 0x0000, /* R121 */
940 0x0000, /* R122 */
941 0x0000, /* R123 */
942 0x0000, /* R124 */
943 0x0000, /* R125 */
944 0x0000, /* R126 */
945 0x0000, /* R127 */
946 0x1FFF, /* R128 - GPIO Debounce */
947 0x0000, /* R129 - GPIO Pin pull up Control */
948 0x03FC, /* R130 - GPIO Pull down Control */
949 0x0000, /* R131 - GPIO Interrupt Mode */
950 0x0000, /* R132 */
951 0x0000, /* R133 - GPIO Control */
952 0x0A7B, /* R134 - GPIO Configuration (i/o) */
953 0x06FE, /* R135 - GPIO Pin Polarity / Type */
954 0x0000, /* R136 */
955 0x0000, /* R137 */
956 0x0000, /* R138 */
957 0x0000, /* R139 */
958 0x1312, /* R140 - GPIO Function Select 1 */
959 0x1030, /* R141 - GPIO Function Select 2 */
960 0x2231, /* R142 - GPIO Function Select 3 */
961 0x0003, /* R143 - GPIO Function Select 4 */
962 0x0000, /* R144 - Digitiser Control (1) */
963 0x0002, /* R145 - Digitiser Control (2) */
964 0x0000, /* R146 */
965 0x0000, /* R147 */
966 0x0000, /* R148 */
967 0x0000, /* R149 */
968 0x0000, /* R150 */
969 0x0000, /* R151 */
970 0x7000, /* R152 - AUX1 Readback */
971 0x7000, /* R153 - AUX2 Readback */
972 0x7000, /* R154 - AUX3 Readback */
973 0x7000, /* R155 - AUX4 Readback */
974 0x0000, /* R156 - USB Voltage Readback */
975 0x0000, /* R157 - LINE Voltage Readback */
976 0x0000, /* R158 - BATT Voltage Readback */
977 0x0000, /* R159 - Chip Temp Readback */
978 0x0000, /* R160 */
979 0x0000, /* R161 */
980 0x0000, /* R162 */
981 0x0000, /* R163 - Generic Comparator Control */
982 0x0000, /* R164 - Generic comparator 1 */
983 0x0000, /* R165 - Generic comparator 2 */
984 0x0000, /* R166 - Generic comparator 3 */
985 0x0000, /* R167 - Generic comparator 4 */
986 0xA00F, /* R168 - Battery Charger Control 1 */
987 0x0B06, /* R169 - Battery Charger Control 2 */
988 0x0000, /* R170 - Battery Charger Control 3 */
989 0x0000, /* R171 */
990 0x0000, /* R172 - Current Sink Driver A */
991 0x0000, /* R173 - CSA Flash control */
992 0x0000, /* R174 - Current Sink Driver B */
993 0x0000, /* R175 - CSB Flash control */
994 0x0000, /* R176 - DCDC/LDO requested */
995 0x002D, /* R177 - DCDC Active options */
996 0x0000, /* R178 - DCDC Sleep options */
997 0x0025, /* R179 - Power-check comparator */
998 0x000E, /* R180 - DCDC1 Control */
999 0x0400, /* R181 - DCDC1 Timeouts */
1000 0x1006, /* R182 - DCDC1 Low Power */
1001 0x0018, /* R183 - DCDC2 Control */
1002 0x0000, /* R184 - DCDC2 Timeouts */
1003 0x0000, /* R185 */
1004 0x000E, /* R186 - DCDC3 Control */
1005 0x0400, /* R187 - DCDC3 Timeouts */
1006 0x0006, /* R188 - DCDC3 Low Power */
1007 0x0026, /* R189 - DCDC4 Control */
1008 0x0400, /* R190 - DCDC4 Timeouts */
1009 0x0006, /* R191 - DCDC4 Low Power */
1010 0x0008, /* R192 - DCDC5 Control */
1011 0x0000, /* R193 - DCDC5 Timeouts */
1012 0x0000, /* R194 */
1013 0x0026, /* R195 - DCDC6 Control */
1014 0x0400, /* R196 - DCDC6 Timeouts */
1015 0x0006, /* R197 - DCDC6 Low Power */
1016 0x0000, /* R198 */
1017 0x0003, /* R199 - Limit Switch Control */
1018 0x001C, /* R200 - LDO1 Control */
1019 0x0000, /* R201 - LDO1 Timeouts */
1020 0x001C, /* R202 - LDO1 Low Power */
1021 0x001C, /* R203 - LDO2 Control */
1022 0x0400, /* R204 - LDO2 Timeouts */
1023 0x001C, /* R205 - LDO2 Low Power */
1024 0x001C, /* R206 - LDO3 Control */
1025 0x0400, /* R207 - LDO3 Timeouts */
1026 0x001C, /* R208 - LDO3 Low Power */
1027 0x001F, /* R209 - LDO4 Control */
1028 0x0400, /* R210 - LDO4 Timeouts */
1029 0x001C, /* R211 - LDO4 Low Power */
1030 0x0000, /* R212 */
1031 0x0000, /* R213 */
1032 0x0000, /* R214 */
1033 0x0000, /* R215 - VCC_FAULT Masks */
1034 0x001F, /* R216 - Main Bandgap Control */
1035 0x0000, /* R217 - OSC Control */
1036 0x9000, /* R218 - RTC Tick Control */
1037 0x0000, /* R219 */
1038 0x4000, /* R220 - RAM BIST 1 */
1039 0x0000, /* R221 */
1040 0x0000, /* R222 */
1041 0x0000, /* R223 */
1042 0x0000, /* R224 */
1043 0x0000, /* R225 - DCDC/LDO status */
1044 0x0000, /* R226 */
1045 0x0000, /* R227 */
1046 0x0000, /* R228 */
1047 0x0000, /* R229 */
1048 0xE000, /* R230 - GPIO Pin Status */
1049 0x0000, /* R231 */
1050 0x0000, /* R232 */
1051 0x0000, /* R233 */
1052 0x0000, /* R234 */
1053 0x0000, /* R235 */
1054 0x0000, /* R236 */
1055 0x0000, /* R237 */
1056 0x0000, /* R238 */
1057 0x0000, /* R239 */
1058 0x0000, /* R240 */
1059 0x0000, /* R241 */
1060 0x0000, /* R242 */
1061 0x0000, /* R243 */
1062 0x0000, /* R244 */
1063 0x0000, /* R245 */
1064 0x0000, /* R246 */
1065 0x0000, /* R247 */
1066 0x0000, /* R248 */
1067 0x0000, /* R249 */
1068 0x0000, /* R250 */
1069 0x0000, /* R251 */
1070 0x0000, /* R252 */
1071 0x0000, /* R253 */
1072 0x0000, /* R254 */
1073 0x0000, /* R255 */
1074};
1075#endif
1076
1077/* The register defaults for the config mode used must be compiled in but
1078 * due to the impact on kernel size it is possible to disable
1079 */
1080#ifndef WM8350_HAVE_CONFIG_MODE
1081#warning No WM8350 config modes supported - select at least one of the
1082#warning MFD_WM8350_CONFIG_MODE_n options from the board driver.
1083#endif
1084
1085/*
1086 * Access masks.
1087 */
1088
1089const struct wm8350_reg_access wm8350_reg_io_map[] = {
1090 /* read write volatile */
1091 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R0 - Reset/ID */
1092 { 0x7CFF, 0x0C00, 0x7FFF }, /* R1 - ID */
1093 { 0x0000, 0x0000, 0x0000 }, /* R2 */
1094 { 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
1095 { 0xFCF7, 0xFCF7, 0xF800 }, /* R4 - System Control 2 */
1096 { 0x80FF, 0x80FF, 0x8000 }, /* R5 - System Hibernate */
1097 { 0xFB0E, 0xFB0E, 0x0000 }, /* R6 - Interface Control */
1098 { 0x0000, 0x0000, 0x0000 }, /* R7 */
1099 { 0xE537, 0xE537, 0xFFFF }, /* R8 - Power mgmt (1) */
1100 { 0x0FF3, 0x0FF3, 0xFFFF }, /* R9 - Power mgmt (2) */
1101 { 0x008F, 0x008F, 0xFFFF }, /* R10 - Power mgmt (3) */
1102 { 0x6D3C, 0x6D3C, 0xFFFF }, /* R11 - Power mgmt (4) */
1103 { 0x1F8F, 0x1F8F, 0xFFFF }, /* R12 - Power mgmt (5) */
1104 { 0x8F3F, 0x8F3F, 0xFFFF }, /* R13 - Power mgmt (6) */
1105 { 0x0003, 0x0003, 0xFFFF }, /* R14 - Power mgmt (7) */
1106 { 0x0000, 0x0000, 0x0000 }, /* R15 */
1107 { 0x7F7F, 0x7F7F, 0xFFFF }, /* R16 - RTC Seconds/Minutes */
1108 { 0x073F, 0x073F, 0xFFFF }, /* R17 - RTC Hours/Day */
1109 { 0x1F3F, 0x1F3F, 0xFFFF }, /* R18 - RTC Date/Month */
1110 { 0x3FFF, 0x00FF, 0xFFFF }, /* R19 - RTC Year */
1111 { 0x7F7F, 0x7F7F, 0x0000 }, /* R20 - Alarm Seconds/Minutes */
1112 { 0x0F3F, 0x0F3F, 0x0000 }, /* R21 - Alarm Hours/Day */
1113 { 0x1F3F, 0x1F3F, 0x0000 }, /* R22 - Alarm Date/Month */
1114 { 0xEF7F, 0xEA7F, 0xFFFF }, /* R23 - RTC Time Control */
1115 { 0x3BFF, 0x0000, 0xFFFF }, /* R24 - System Interrupts */
1116 { 0xFEE7, 0x0000, 0xFFFF }, /* R25 - Interrupt Status 1 */
1117 { 0x35FF, 0x0000, 0xFFFF }, /* R26 - Interrupt Status 2 */
1118 { 0x0F3F, 0x0000, 0xFFFF }, /* R27 - Power Up Interrupt Status */
1119 { 0x0F3F, 0x0000, 0xFFFF }, /* R28 - Under Voltage Interrupt status */
1120 { 0x8000, 0x0000, 0xFFFF }, /* R29 - Over Current Interrupt status */
1121 { 0x1FFF, 0x0000, 0xFFFF }, /* R30 - GPIO Interrupt Status */
1122 { 0xEF7F, 0x0000, 0xFFFF }, /* R31 - Comparator Interrupt Status */
1123 { 0x3FFF, 0x3FFF, 0x0000 }, /* R32 - System Interrupts Mask */
1124 { 0xFEE7, 0xFEE7, 0x0000 }, /* R33 - Interrupt Status 1 Mask */
1125 { 0xF5FF, 0xF5FF, 0x0000 }, /* R34 - Interrupt Status 2 Mask */
1126 { 0x0F3F, 0x0F3F, 0x0000 }, /* R35 - Power Up Interrupt Status Mask */
1127 { 0x0F3F, 0x0F3F, 0x0000 }, /* R36 - Under Voltage Int status Mask */
1128 { 0x8000, 0x8000, 0x0000 }, /* R37 - Over Current Int status Mask */
1129 { 0x1FFF, 0x1FFF, 0x0000 }, /* R38 - GPIO Interrupt Status Mask */
1130 { 0xEF7F, 0xEF7F, 0x0000 }, /* R39 - Comparator IntStatus Mask */
1131 { 0xC9F7, 0xC9F7, 0xFFFF }, /* R40 - Clock Control 1 */
1132 { 0x8001, 0x8001, 0x0000 }, /* R41 - Clock Control 2 */
1133 { 0xFFF7, 0xFFF7, 0xFFFF }, /* R42 - FLL Control 1 */
1134 { 0xFBFF, 0xFBFF, 0x0000 }, /* R43 - FLL Control 2 */
1135 { 0xFFFF, 0xFFFF, 0x0000 }, /* R44 - FLL Control 3 */
1136 { 0x0033, 0x0033, 0x0000 }, /* R45 - FLL Control 4 */
1137 { 0x0000, 0x0000, 0x0000 }, /* R46 */
1138 { 0x0000, 0x0000, 0x0000 }, /* R47 */
1139 { 0x3033, 0x3033, 0x0000 }, /* R48 - DAC Control */
1140 { 0x0000, 0x0000, 0x0000 }, /* R49 */
1141 { 0x81FF, 0x81FF, 0xFFFF }, /* R50 - DAC Digital Volume L */
1142 { 0x81FF, 0x81FF, 0xFFFF }, /* R51 - DAC Digital Volume R */
1143 { 0x0000, 0x0000, 0x0000 }, /* R52 */
1144 { 0x0FFF, 0x0FFF, 0xFFFF }, /* R53 - DAC LR Rate */
1145 { 0x0017, 0x0017, 0x0000 }, /* R54 - DAC Clock Control */
1146 { 0x0000, 0x0000, 0x0000 }, /* R55 */
1147 { 0x0000, 0x0000, 0x0000 }, /* R56 */
1148 { 0x0000, 0x0000, 0x0000 }, /* R57 */
1149 { 0x4000, 0x4000, 0x0000 }, /* R58 - DAC Mute */
1150 { 0x7000, 0x7000, 0x0000 }, /* R59 - DAC Mute Volume */
1151 { 0x3C00, 0x3C00, 0x0000 }, /* R60 - DAC Side */
1152 { 0x0000, 0x0000, 0x0000 }, /* R61 */
1153 { 0x0000, 0x0000, 0x0000 }, /* R62 */
1154 { 0x0000, 0x0000, 0x0000 }, /* R63 */
1155 { 0x8303, 0x8303, 0xFFFF }, /* R64 - ADC Control */
1156 { 0x0000, 0x0000, 0x0000 }, /* R65 */
1157 { 0x81FF, 0x81FF, 0xFFFF }, /* R66 - ADC Digital Volume L */
1158 { 0x81FF, 0x81FF, 0xFFFF }, /* R67 - ADC Digital Volume R */
1159 { 0x0FFF, 0x0FFF, 0x0000 }, /* R68 - ADC Divider */
1160 { 0x0000, 0x0000, 0x0000 }, /* R69 */
1161 { 0x0FFF, 0x0FFF, 0xFFFF }, /* R70 - ADC LR Rate */
1162 { 0x0000, 0x0000, 0x0000 }, /* R71 */
1163 { 0x0707, 0x0707, 0xFFFF }, /* R72 - Input Control */
1164 { 0xC0C0, 0xC0C0, 0xFFFF }, /* R73 - IN3 Input Control */
1165 { 0xC09F, 0xC09F, 0xFFFF }, /* R74 - Mic Bias Control */
1166 { 0x0000, 0x0000, 0x0000 }, /* R75 */
1167 { 0x0F15, 0x0F15, 0xFFFF }, /* R76 - Output Control */
1168 { 0xC000, 0xC000, 0xFFFF }, /* R77 - Jack Detect */
1169 { 0x03FF, 0x03FF, 0x0000 }, /* R78 - Anti Pop Control */
1170 { 0x0000, 0x0000, 0x0000 }, /* R79 */
1171 { 0xE1FC, 0xE1FC, 0x8000 }, /* R80 - Left Input Volume */
1172 { 0xE1FC, 0xE1FC, 0x8000 }, /* R81 - Right Input Volume */
1173 { 0x0000, 0x0000, 0x0000 }, /* R82 */
1174 { 0x0000, 0x0000, 0x0000 }, /* R83 */
1175 { 0x0000, 0x0000, 0x0000 }, /* R84 */
1176 { 0x0000, 0x0000, 0x0000 }, /* R85 */
1177 { 0x0000, 0x0000, 0x0000 }, /* R86 */
1178 { 0x0000, 0x0000, 0x0000 }, /* R87 */
1179 { 0x9807, 0x9807, 0xFFFF }, /* R88 - Left Mixer Control */
1180 { 0x980B, 0x980B, 0xFFFF }, /* R89 - Right Mixer Control */
1181 { 0x0000, 0x0000, 0x0000 }, /* R90 */
1182 { 0x0000, 0x0000, 0x0000 }, /* R91 */
1183 { 0x8909, 0x8909, 0xFFFF }, /* R92 - OUT3 Mixer Control */
1184 { 0x9E07, 0x9E07, 0xFFFF }, /* R93 - OUT4 Mixer Control */
1185 { 0x0000, 0x0000, 0x0000 }, /* R94 */
1186 { 0x0000, 0x0000, 0x0000 }, /* R95 */
1187 { 0x0EEE, 0x0EEE, 0x0000 }, /* R96 - Output Left Mixer Volume */
1188 { 0xE0EE, 0xE0EE, 0x0000 }, /* R97 - Output Right Mixer Volume */
1189 { 0x0E0F, 0x0E0F, 0x0000 }, /* R98 - Input Mixer Volume L */
1190 { 0xE0E1, 0xE0E1, 0x0000 }, /* R99 - Input Mixer Volume R */
1191 { 0x800E, 0x800E, 0x0000 }, /* R100 - Input Mixer Volume */
1192 { 0x0000, 0x0000, 0x0000 }, /* R101 */
1193 { 0x0000, 0x0000, 0x0000 }, /* R102 */
1194 { 0x0000, 0x0000, 0x0000 }, /* R103 */
1195 { 0xE1FC, 0xE1FC, 0xFFFF }, /* R104 - LOUT1 Volume */
1196 { 0xE1FC, 0xE1FC, 0xFFFF }, /* R105 - ROUT1 Volume */
1197 { 0xE1FC, 0xE1FC, 0xFFFF }, /* R106 - LOUT2 Volume */
1198 { 0xE7FC, 0xE7FC, 0xFFFF }, /* R107 - ROUT2 Volume */
1199 { 0x0000, 0x0000, 0x0000 }, /* R108 */
1200 { 0x0000, 0x0000, 0x0000 }, /* R109 */
1201 { 0x0000, 0x0000, 0x0000 }, /* R110 */
1202 { 0x80E0, 0x80E0, 0xFFFF }, /* R111 - BEEP Volume */
1203 { 0xBF00, 0xBF00, 0x0000 }, /* R112 - AI Formating */
1204 { 0x00F1, 0x00F1, 0x0000 }, /* R113 - ADC DAC COMP */
1205 { 0x00F8, 0x00F8, 0x0000 }, /* R114 - AI ADC Control */
1206 { 0x40FB, 0x40FB, 0x0000 }, /* R115 - AI DAC Control */
1207 { 0x7C30, 0x7C30, 0x0000 }, /* R116 - AIF Test */
1208 { 0x0000, 0x0000, 0x0000 }, /* R117 */
1209 { 0x0000, 0x0000, 0x0000 }, /* R118 */
1210 { 0x0000, 0x0000, 0x0000 }, /* R119 */
1211 { 0x0000, 0x0000, 0x0000 }, /* R120 */
1212 { 0x0000, 0x0000, 0x0000 }, /* R121 */
1213 { 0x0000, 0x0000, 0x0000 }, /* R122 */
1214 { 0x0000, 0x0000, 0x0000 }, /* R123 */
1215 { 0x0000, 0x0000, 0x0000 }, /* R124 */
1216 { 0x0000, 0x0000, 0x0000 }, /* R125 */
1217 { 0x0000, 0x0000, 0x0000 }, /* R126 */
1218 { 0x0000, 0x0000, 0x0000 }, /* R127 */
1219 { 0x1FFF, 0x1FFF, 0x0000 }, /* R128 - GPIO Debounce */
1220 { 0x1FFF, 0x1FFF, 0x0000 }, /* R129 - GPIO Pin pull up Control */
1221 { 0x1FFF, 0x1FFF, 0x0000 }, /* R130 - GPIO Pull down Control */
1222 { 0x1FFF, 0x1FFF, 0x0000 }, /* R131 - GPIO Interrupt Mode */
1223 { 0x0000, 0x0000, 0x0000 }, /* R132 */
1224 { 0x00C0, 0x00C0, 0x0000 }, /* R133 - GPIO Control */
1225 { 0x1FFF, 0x1FFF, 0x0000 }, /* R134 - GPIO Configuration (i/o) */
1226 { 0x1FFF, 0x1FFF, 0x0000 }, /* R135 - GPIO Pin Polarity / Type */
1227 { 0x0000, 0x0000, 0x0000 }, /* R136 */
1228 { 0x0000, 0x0000, 0x0000 }, /* R137 */
1229 { 0x0000, 0x0000, 0x0000 }, /* R138 */
1230 { 0x0000, 0x0000, 0x0000 }, /* R139 */
1231 { 0xFFFF, 0xFFFF, 0x0000 }, /* R140 - GPIO Function Select 1 */
1232 { 0xFFFF, 0xFFFF, 0x0000 }, /* R141 - GPIO Function Select 2 */
1233 { 0xFFFF, 0xFFFF, 0x0000 }, /* R142 - GPIO Function Select 3 */
1234 { 0x000F, 0x000F, 0x0000 }, /* R143 - GPIO Function Select 4 */
1235 { 0xF0FF, 0xF0FF, 0xA000 }, /* R144 - Digitiser Control (1) */
1236 { 0x3707, 0x3707, 0x0000 }, /* R145 - Digitiser Control (2) */
1237 { 0x0000, 0x0000, 0x0000 }, /* R146 */
1238 { 0x0000, 0x0000, 0x0000 }, /* R147 */
1239 { 0x0000, 0x0000, 0x0000 }, /* R148 */
1240 { 0x0000, 0x0000, 0x0000 }, /* R149 */
1241 { 0x0000, 0x0000, 0x0000 }, /* R150 */
1242 { 0x0000, 0x0000, 0x0000 }, /* R151 */
1243 { 0x7FFF, 0x7000, 0xFFFF }, /* R152 - AUX1 Readback */
1244 { 0x7FFF, 0x7000, 0xFFFF }, /* R153 - AUX2 Readback */
1245 { 0x7FFF, 0x7000, 0xFFFF }, /* R154 - AUX3 Readback */
1246 { 0x7FFF, 0x7000, 0xFFFF }, /* R155 - AUX4 Readback */
1247 { 0x0FFF, 0x0000, 0xFFFF }, /* R156 - USB Voltage Readback */
1248 { 0x0FFF, 0x0000, 0xFFFF }, /* R157 - LINE Voltage Readback */
1249 { 0x0FFF, 0x0000, 0xFFFF }, /* R158 - BATT Voltage Readback */
1250 { 0x0FFF, 0x0000, 0xFFFF }, /* R159 - Chip Temp Readback */
1251 { 0x0000, 0x0000, 0x0000 }, /* R160 */
1252 { 0x0000, 0x0000, 0x0000 }, /* R161 */
1253 { 0x0000, 0x0000, 0x0000 }, /* R162 */
1254 { 0x000F, 0x000F, 0x0000 }, /* R163 - Generic Comparator Control */
1255 { 0xFFFF, 0xFFFF, 0x0000 }, /* R164 - Generic comparator 1 */
1256 { 0xFFFF, 0xFFFF, 0x0000 }, /* R165 - Generic comparator 2 */
1257 { 0xFFFF, 0xFFFF, 0x0000 }, /* R166 - Generic comparator 3 */
1258 { 0xFFFF, 0xFFFF, 0x0000 }, /* R167 - Generic comparator 4 */
1259 { 0xBFFF, 0xBFFF, 0x8000 }, /* R168 - Battery Charger Control 1 */
1260 { 0xFFFF, 0x4FFF, 0xB000 }, /* R169 - Battery Charger Control 2 */
1261 { 0x007F, 0x007F, 0x0000 }, /* R170 - Battery Charger Control 3 */
1262 { 0x0000, 0x0000, 0x0000 }, /* R171 */
1263 { 0x903F, 0x903F, 0xFFFF }, /* R172 - Current Sink Driver A */
1264 { 0xE333, 0xE333, 0xFFFF }, /* R173 - CSA Flash control */
1265 { 0x903F, 0x903F, 0xFFFF }, /* R174 - Current Sink Driver B */
1266 { 0xE333, 0xE333, 0xFFFF }, /* R175 - CSB Flash control */
1267 { 0x8F3F, 0x8F3F, 0xFFFF }, /* R176 - DCDC/LDO requested */
1268 { 0x332D, 0x332D, 0x0000 }, /* R177 - DCDC Active options */
1269 { 0x002D, 0x002D, 0x0000 }, /* R178 - DCDC Sleep options */
1270 { 0x5177, 0x5177, 0x8000 }, /* R179 - Power-check comparator */
1271 { 0x047F, 0x047F, 0x0000 }, /* R180 - DCDC1 Control */
1272 { 0xFFC0, 0xFFC0, 0x0000 }, /* R181 - DCDC1 Timeouts */
1273 { 0x737F, 0x737F, 0x0000 }, /* R182 - DCDC1 Low Power */
1274 { 0x535B, 0x535B, 0x0000 }, /* R183 - DCDC2 Control */
1275 { 0xFFC0, 0xFFC0, 0x0000 }, /* R184 - DCDC2 Timeouts */
1276 { 0x0000, 0x0000, 0x0000 }, /* R185 */
1277 { 0x047F, 0x047F, 0x0000 }, /* R186 - DCDC3 Control */
1278 { 0xFFC0, 0xFFC0, 0x0000 }, /* R187 - DCDC3 Timeouts */
1279 { 0x737F, 0x737F, 0x0000 }, /* R188 - DCDC3 Low Power */
1280 { 0x047F, 0x047F, 0x0000 }, /* R189 - DCDC4 Control */
1281 { 0xFFC0, 0xFFC0, 0x0000 }, /* R190 - DCDC4 Timeouts */
1282 { 0x737F, 0x737F, 0x0000 }, /* R191 - DCDC4 Low Power */
1283 { 0x535B, 0x535B, 0x0000 }, /* R192 - DCDC5 Control */
1284 { 0xFFC0, 0xFFC0, 0x0000 }, /* R193 - DCDC5 Timeouts */
1285 { 0x0000, 0x0000, 0x0000 }, /* R194 */
1286 { 0x047F, 0x047F, 0x0000 }, /* R195 - DCDC6 Control */
1287 { 0xFFC0, 0xFFC0, 0x0000 }, /* R196 - DCDC6 Timeouts */
1288 { 0x737F, 0x737F, 0x0000 }, /* R197 - DCDC6 Low Power */
1289 { 0x0000, 0x0000, 0x0000 }, /* R198 */
1290 { 0xFFD3, 0xFFD3, 0x0000 }, /* R199 - Limit Switch Control */
1291 { 0x441F, 0x441F, 0x0000 }, /* R200 - LDO1 Control */
1292 { 0xFFC0, 0xFFC0, 0x0000 }, /* R201 - LDO1 Timeouts */
1293 { 0x331F, 0x331F, 0x0000 }, /* R202 - LDO1 Low Power */
1294 { 0x441F, 0x441F, 0x0000 }, /* R203 - LDO2 Control */
1295 { 0xFFC0, 0xFFC0, 0x0000 }, /* R204 - LDO2 Timeouts */
1296 { 0x331F, 0x331F, 0x0000 }, /* R205 - LDO2 Low Power */
1297 { 0x441F, 0x441F, 0x0000 }, /* R206 - LDO3 Control */
1298 { 0xFFC0, 0xFFC0, 0x0000 }, /* R207 - LDO3 Timeouts */
1299 { 0x331F, 0x331F, 0x0000 }, /* R208 - LDO3 Low Power */
1300 { 0x441F, 0x441F, 0x0000 }, /* R209 - LDO4 Control */
1301 { 0xFFC0, 0xFFC0, 0x0000 }, /* R210 - LDO4 Timeouts */
1302 { 0x331F, 0x331F, 0x0000 }, /* R211 - LDO4 Low Power */
1303 { 0x0000, 0x0000, 0x0000 }, /* R212 */
1304 { 0x0000, 0x0000, 0x0000 }, /* R213 */
1305 { 0x0000, 0x0000, 0x0000 }, /* R214 */
1306 { 0x8F3F, 0x8F3F, 0x0000 }, /* R215 - VCC_FAULT Masks */
1307 { 0xFF3F, 0xE03F, 0x0000 }, /* R216 - Main Bandgap Control */
1308 { 0xEF2F, 0xE02F, 0x0000 }, /* R217 - OSC Control */
1309 { 0xF3FF, 0xB3FF, 0xc000 }, /* R218 - RTC Tick Control */
1310 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R219 */
1311 { 0x09FF, 0x01FF, 0x0000 }, /* R220 - RAM BIST 1 */
1312 { 0x0000, 0x0000, 0x0000 }, /* R221 */
1313 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R222 */
1314 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R223 */
1315 { 0x0000, 0x0000, 0x0000 }, /* R224 */
1316 { 0x8F3F, 0x0000, 0xFFFF }, /* R225 - DCDC/LDO status */
1317 { 0x0000, 0x0000, 0x0000 }, /* R226 */
1318 { 0x0000, 0x0000, 0xFFFF }, /* R227 */
1319 { 0x0000, 0x0000, 0x0000 }, /* R228 */
1320 { 0x0000, 0x0000, 0x0000 }, /* R229 */
1321 { 0xFFFF, 0x1FFF, 0xFFFF }, /* R230 - GPIO Pin Status */
1322 { 0xFFFF, 0x1FFF, 0xFFFF }, /* R231 */
1323 { 0xFFFF, 0x1FFF, 0xFFFF }, /* R232 */
1324 { 0xFFFF, 0x1FFF, 0xFFFF }, /* R233 */
1325 { 0x0000, 0x0000, 0x0000 }, /* R234 */
1326 { 0x0000, 0x0000, 0x0000 }, /* R235 */
1327 { 0x0000, 0x0000, 0x0000 }, /* R236 */
1328 { 0x0000, 0x0000, 0x0000 }, /* R237 */
1329 { 0x0000, 0x0000, 0x0000 }, /* R238 */
1330 { 0x0000, 0x0000, 0x0000 }, /* R239 */
1331 { 0x0000, 0x0000, 0x0000 }, /* R240 */
1332 { 0x0000, 0x0000, 0x0000 }, /* R241 */
1333 { 0x0000, 0x0000, 0x0000 }, /* R242 */
1334 { 0x0000, 0x0000, 0x0000 }, /* R243 */
1335 { 0x0000, 0x0000, 0x0000 }, /* R244 */
1336 { 0x0000, 0x0000, 0x0000 }, /* R245 */
1337 { 0x0000, 0x0000, 0x0000 }, /* R246 */
1338 { 0x0000, 0x0000, 0x0000 }, /* R247 */
1339 { 0xFFFF, 0x0010, 0xFFFF }, /* R248 */
1340 { 0x0000, 0x0000, 0x0000 }, /* R249 */
1341 { 0xFFFF, 0x0010, 0xFFFF }, /* R250 */
1342 { 0xFFFF, 0x0010, 0xFFFF }, /* R251 */
1343 { 0x0000, 0x0000, 0x0000 }, /* R252 */
1344 { 0xFFFF, 0x0010, 0xFFFF }, /* R253 */
1345 { 0x0000, 0x0000, 0x0000 }, /* R254 */
1346 { 0x0000, 0x0000, 0x0000 }, /* R255 */
1347};
diff --git a/drivers/mfd/wm8400-core.c b/drivers/mfd/wm8400-core.c
new file mode 100644
index 000000000000..6a0cedb5bb8a
--- /dev/null
+++ b/drivers/mfd/wm8400-core.c
@@ -0,0 +1,455 @@
1/*
2 * Core driver for WM8400.
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 */
14
15#include <linux/bug.h>
16#include <linux/i2c.h>
17#include <linux/kernel.h>
18#include <linux/mfd/wm8400-private.h>
19#include <linux/mfd/wm8400-audio.h>
20
21static struct {
22 u16 readable; /* Mask of readable bits */
23 u16 writable; /* Mask of writable bits */
24 u16 vol; /* Mask of volatile bits */
25 int is_codec; /* Register controlled by codec reset */
26 u16 default_val; /* Value on reset */
27} reg_data[] = {
28 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x6172 }, /* R0 */
29 { 0x7000, 0x0000, 0x8000, 0, 0x0000 }, /* R1 */
30 { 0xFF17, 0xFF17, 0x0000, 0, 0x0000 }, /* R2 */
31 { 0xEBF3, 0xEBF3, 0x0000, 1, 0x6000 }, /* R3 */
32 { 0x3CF3, 0x3CF3, 0x0000, 1, 0x0000 }, /* R4 */
33 { 0xF1F8, 0xF1F8, 0x0000, 1, 0x4050 }, /* R5 */
34 { 0xFC1F, 0xFC1F, 0x0000, 1, 0x4000 }, /* R6 */
35 { 0xDFDE, 0xDFDE, 0x0000, 1, 0x01C8 }, /* R7 */
36 { 0xFCFC, 0xFCFC, 0x0000, 1, 0x0000 }, /* R8 */
37 { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R9 */
38 { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R10 */
39 { 0x27F7, 0x27F7, 0x0000, 1, 0x0004 }, /* R11 */
40 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R12 */
41 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R13 */
42 { 0x1FEF, 0x1FEF, 0x0000, 1, 0x0000 }, /* R14 */
43 { 0x0163, 0x0163, 0x0000, 1, 0x0100 }, /* R15 */
44 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R16 */
45 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R17 */
46 { 0x1FFF, 0x0FFF, 0x0000, 1, 0x0000 }, /* R18 */
47 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1000 }, /* R19 */
48 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R20 */
49 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R21 */
50 { 0x0FDD, 0x0FDD, 0x0000, 1, 0x8000 }, /* R22 */
51 { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0800 }, /* R23 */
52 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R24 */
53 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R25 */
54 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R26 */
55 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R27 */
56 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R28 */
57 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R29 */
58 { 0x0000, 0x0077, 0x0000, 1, 0x0066 }, /* R30 */
59 { 0x0000, 0x0033, 0x0000, 1, 0x0022 }, /* R31 */
60 { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R32 */
61 { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R33 */
62 { 0x0000, 0x0003, 0x0000, 1, 0x0003 }, /* R34 */
63 { 0x0000, 0x01FF, 0x0000, 1, 0x0003 }, /* R35 */
64 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R36 */
65 { 0x0000, 0x003F, 0x0000, 1, 0x0100 }, /* R37 */
66 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R38 */
67 { 0x0000, 0x000F, 0x0000, 0, 0x0000 }, /* R39 */
68 { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R40 */
69 { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R41 */
70 { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R42 */
71 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R43 */
72 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R44 */
73 { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R45 */
74 { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R46 */
75 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R47 */
76 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R48 */
77 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R49 */
78 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R50 */
79 { 0x0000, 0x01B3, 0x0000, 1, 0x0180 }, /* R51 */
80 { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R52 */
81 { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R53 */
82 { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R54 */
83 { 0x0000, 0x0001, 0x0000, 1, 0x0000 }, /* R55 */
84 { 0x0000, 0x003F, 0x0000, 1, 0x0000 }, /* R56 */
85 { 0x0000, 0x004F, 0x0000, 1, 0x0000 }, /* R57 */
86 { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R58 */
87 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R59 */
88 { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0000 }, /* R60 */
89 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x0000 }, /* R61 */
90 { 0x03FF, 0x03FF, 0x0000, 1, 0x0000 }, /* R62 */
91 { 0x007F, 0x007F, 0x0000, 1, 0x0000 }, /* R63 */
92 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R64 */
93 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R65 */
94 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R66 */
95 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R67 */
96 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R68 */
97 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R69 */
98 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R70 */
99 { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R71 */
100 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R72 */
101 { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R73 */
102 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R74 */
103 { 0x000E, 0x000E, 0x0000, 0, 0x0008 }, /* R75 */
104 { 0xE00F, 0xE00F, 0x0000, 0, 0x0000 }, /* R76 */
105 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R77 */
106 { 0x03C0, 0x03C0, 0x0000, 0, 0x02C0 }, /* R78 */
107 { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R79 */
108 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x0000 }, /* R80 */
109 { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R81 */
110 { 0x2BFF, 0x0000, 0xffff, 0, 0x0000 }, /* R82 */
111 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R83 */
112 { 0x80FF, 0x80FF, 0x0000, 0, 0x00ff }, /* R84 */
113};
114
115static int wm8400_read(struct wm8400 *wm8400, u8 reg, int num_regs, u16 *dest)
116{
117 int i, ret = 0;
118
119 BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache));
120
121 /* If there are any volatile reads then read back the entire block */
122 for (i = reg; i < reg + num_regs; i++)
123 if (reg_data[i].vol) {
124 ret = wm8400->read_dev(wm8400->io_data, reg,
125 num_regs, dest);
126 if (ret != 0)
127 return ret;
128 for (i = 0; i < num_regs; i++)
129 dest[i] = be16_to_cpu(dest[i]);
130
131 return 0;
132 }
133
134 /* Otherwise use the cache */
135 memcpy(dest, &wm8400->reg_cache[reg], num_regs * sizeof(u16));
136
137 return 0;
138}
139
140static int wm8400_write(struct wm8400 *wm8400, u8 reg, int num_regs,
141 u16 *src)
142{
143 int ret, i;
144
145 BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache));
146
147 for (i = 0; i < num_regs; i++) {
148 BUG_ON(!reg_data[reg + i].writable);
149 wm8400->reg_cache[reg + i] = src[i];
150 src[i] = cpu_to_be16(src[i]);
151 }
152
153 /* Do the actual I/O */
154 ret = wm8400->write_dev(wm8400->io_data, reg, num_regs, src);
155 if (ret != 0)
156 return -EIO;
157
158 return 0;
159}
160
161/**
162 * wm8400_reg_read - Single register read
163 *
164 * @wm8400: Pointer to wm8400 control structure
165 * @reg: Register to read
166 *
167 * @return Read value
168 */
169u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg)
170{
171 u16 val;
172
173 mutex_lock(&wm8400->io_lock);
174
175 wm8400_read(wm8400, reg, 1, &val);
176
177 mutex_unlock(&wm8400->io_lock);
178
179 return val;
180}
181EXPORT_SYMBOL_GPL(wm8400_reg_read);
182
183int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data)
184{
185 int ret;
186
187 mutex_lock(&wm8400->io_lock);
188
189 ret = wm8400_read(wm8400, reg, count, data);
190
191 mutex_unlock(&wm8400->io_lock);
192
193 return ret;
194}
195EXPORT_SYMBOL_GPL(wm8400_block_read);
196
197/**
198 * wm8400_set_bits - Bitmask write
199 *
200 * @wm8400: Pointer to wm8400 control structure
201 * @reg: Register to access
202 * @mask: Mask of bits to change
203 * @val: Value to set for masked bits
204 */
205int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val)
206{
207 u16 tmp;
208 int ret;
209
210 mutex_lock(&wm8400->io_lock);
211
212 ret = wm8400_read(wm8400, reg, 1, &tmp);
213 tmp = (tmp & ~mask) | val;
214 if (ret == 0)
215 ret = wm8400_write(wm8400, reg, 1, &tmp);
216
217 mutex_unlock(&wm8400->io_lock);
218
219 return ret;
220}
221EXPORT_SYMBOL_GPL(wm8400_set_bits);
222
223/**
224 * wm8400_reset_codec_reg_cache - Reset cached codec registers to
225 * their default values.
226 */
227void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
228{
229 int i;
230
231 mutex_lock(&wm8400->io_lock);
232
233 /* Reset all codec registers to their initial value */
234 for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
235 if (reg_data[i].is_codec)
236 wm8400->reg_cache[i] = reg_data[i].default_val;
237
238 mutex_unlock(&wm8400->io_lock);
239}
240EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);
241
242/*
243 * wm8400_init - Generic initialisation
244 *
245 * The WM8400 can be configured as either an I2C or SPI device. Probe
246 * functions for each bus set up the accessors then call into this to
247 * set up the device itself.
248 */
249static int wm8400_init(struct wm8400 *wm8400,
250 struct wm8400_platform_data *pdata)
251{
252 u16 reg;
253 int ret, i;
254
255 mutex_init(&wm8400->io_lock);
256
257 wm8400->dev->driver_data = wm8400;
258
259 /* Check that this is actually a WM8400 */
260 ret = wm8400->read_dev(wm8400->io_data, WM8400_RESET_ID, 1, &reg);
261 if (ret != 0) {
262 dev_err(wm8400->dev, "Chip ID register read failed\n");
263 return -EIO;
264 }
265 if (be16_to_cpu(reg) != reg_data[WM8400_RESET_ID].default_val) {
266 dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n",
267 be16_to_cpu(reg));
268 return -ENODEV;
269 }
270
271 /* We don't know what state the hardware is in and since this
272 * is a PMIC we can't reset it safely so initialise the register
273 * cache from the hardware.
274 */
275 ret = wm8400->read_dev(wm8400->io_data, 0,
276 ARRAY_SIZE(wm8400->reg_cache),
277 wm8400->reg_cache);
278 if (ret != 0) {
279 dev_err(wm8400->dev, "Register cache read failed\n");
280 return -EIO;
281 }
282 for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
283 wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]);
284
285 /* If the codec is in reset use hard coded values */
286 if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA))
287 for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
288 if (reg_data[i].is_codec)
289 wm8400->reg_cache[i] = reg_data[i].default_val;
290
291 ret = wm8400_read(wm8400, WM8400_ID, 1, &reg);
292 if (ret != 0) {
293 dev_err(wm8400->dev, "ID register read failed: %d\n", ret);
294 return ret;
295 }
296 reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT;
297 dev_info(wm8400->dev, "WM8400 revision %x\n", reg);
298
299 if (pdata && pdata->platform_init) {
300 ret = pdata->platform_init(wm8400->dev);
301 if (ret != 0)
302 dev_err(wm8400->dev, "Platform init failed: %d\n",
303 ret);
304 } else
305 dev_warn(wm8400->dev, "No platform initialisation supplied\n");
306
307 return ret;
308}
309
310static void wm8400_release(struct wm8400 *wm8400)
311{
312 int i;
313
314 for (i = 0; i < ARRAY_SIZE(wm8400->regulators); i++)
315 if (wm8400->regulators[i].name)
316 platform_device_unregister(&wm8400->regulators[i]);
317}
318
319#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
320static int wm8400_i2c_read(void *io_data, char reg, int count, u16 *dest)
321{
322 struct i2c_client *i2c = io_data;
323 struct i2c_msg xfer[2];
324 int ret;
325
326 /* Write register */
327 xfer[0].addr = i2c->addr;
328 xfer[0].flags = 0;
329 xfer[0].len = 1;
330 xfer[0].buf = &reg;
331
332 /* Read data */
333 xfer[1].addr = i2c->addr;
334 xfer[1].flags = I2C_M_RD;
335 xfer[1].len = count * sizeof(u16);
336 xfer[1].buf = (u8 *)dest;
337
338 ret = i2c_transfer(i2c->adapter, xfer, 2);
339 if (ret == 2)
340 ret = 0;
341 else if (ret >= 0)
342 ret = -EIO;
343
344 return ret;
345}
346
347static int wm8400_i2c_write(void *io_data, char reg, int count, const u16 *src)
348{
349 struct i2c_client *i2c = io_data;
350 u8 *msg;
351 int ret;
352
353 /* We add 1 byte for device register - ideally I2C would gather. */
354 msg = kmalloc((count * sizeof(u16)) + 1, GFP_KERNEL);
355 if (msg == NULL)
356 return -ENOMEM;
357
358 msg[0] = reg;
359 memcpy(&msg[1], src, count * sizeof(u16));
360
361 ret = i2c_master_send(i2c, msg, (count * sizeof(u16)) + 1);
362
363 if (ret == (count * 2) + 1)
364 ret = 0;
365 else if (ret >= 0)
366 ret = -EIO;
367
368 kfree(msg);
369
370 return ret;
371}
372
373static int wm8400_i2c_probe(struct i2c_client *i2c,
374 const struct i2c_device_id *id)
375{
376 struct wm8400 *wm8400;
377 int ret;
378
379 wm8400 = kzalloc(sizeof(struct wm8400), GFP_KERNEL);
380 if (wm8400 == NULL) {
381 ret = -ENOMEM;
382 goto err;
383 }
384
385 wm8400->io_data = i2c;
386 wm8400->read_dev = wm8400_i2c_read;
387 wm8400->write_dev = wm8400_i2c_write;
388 wm8400->dev = &i2c->dev;
389 i2c_set_clientdata(i2c, wm8400);
390
391 ret = wm8400_init(wm8400, i2c->dev.platform_data);
392 if (ret != 0)
393 goto struct_err;
394
395 return 0;
396
397struct_err:
398 i2c_set_clientdata(i2c, NULL);
399 kfree(wm8400);
400err:
401 return ret;
402}
403
404static int wm8400_i2c_remove(struct i2c_client *i2c)
405{
406 struct wm8400 *wm8400 = i2c_get_clientdata(i2c);
407
408 wm8400_release(wm8400);
409 i2c_set_clientdata(i2c, NULL);
410 kfree(wm8400);
411
412 return 0;
413}
414
415static const struct i2c_device_id wm8400_i2c_id[] = {
416 { "wm8400", 0 },
417 { }
418};
419MODULE_DEVICE_TABLE(i2c, wm8400_i2c_id);
420
421static struct i2c_driver wm8400_i2c_driver = {
422 .driver = {
423 .name = "WM8400",
424 .owner = THIS_MODULE,
425 },
426 .probe = wm8400_i2c_probe,
427 .remove = wm8400_i2c_remove,
428 .id_table = wm8400_i2c_id,
429};
430#endif
431
432static int __init wm8400_module_init(void)
433{
434 int ret = -ENODEV;
435
436#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
437 ret = i2c_add_driver(&wm8400_i2c_driver);
438 if (ret != 0)
439 pr_err("Failed to register I2C driver: %d\n", ret);
440#endif
441
442 return ret;
443}
444module_init(wm8400_module_init);
445
446static void __exit wm8400_module_exit(void)
447{
448#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
449 i2c_del_driver(&wm8400_i2c_driver);
450#endif
451}
452module_exit(wm8400_module_exit);
453
454MODULE_LICENSE("GPL");
455MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index a656128f1fdd..4dada6ee1119 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -56,4 +56,28 @@ config REGULATOR_BQ24022
56 charging select between 100 mA and 500 mA charging current 56 charging select between 100 mA and 500 mA charging current
57 limit. 57 limit.
58 58
59config REGULATOR_WM8350
60 tristate "Wolfson Microelectroncis WM8350 AudioPlus PMIC"
61 depends on MFD_WM8350
62 select REGULATOR
63 help
64 This driver provides support for the voltage and current regulators
65 of the WM8350 AudioPlus PMIC.
66
67config REGULATOR_WM8400
68 tristate "Wolfson Microelectroncis WM8400 AudioPlus PMIC"
69 depends on MFD_WM8400
70 select REGULATOR
71 help
72 This driver provides support for the voltage regulators of the
73 WM8400 AudioPlus PMIC.
74
75config REGULATOR_DA903X
76 tristate "Support regulators on Dialog Semiconductor DA9030/DA9034 PMIC"
77 depends on PMIC_DA903X
78 select REGULATOR
79 help
80 Say y here to support the BUCKs and LDOs regulators found on
81 Dialog Semiconductor DA9030/DA9034 PMIC.
82
59endmenu 83endmenu
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index ac2c64efe65c..254d40c02ee8 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -8,5 +8,8 @@ obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o
8obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o 8obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o
9 9
10obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o 10obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o
11obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
12obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
13obj-$(CONFIG_REGULATOR_DA903X) += da903x.o
11 14
12ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG 15ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/bq24022.c b/drivers/regulator/bq24022.c
index 263699d6152d..366565aba865 100644
--- a/drivers/regulator/bq24022.c
+++ b/drivers/regulator/bq24022.c
@@ -18,13 +18,13 @@
18#include <linux/regulator/bq24022.h> 18#include <linux/regulator/bq24022.h>
19#include <linux/regulator/driver.h> 19#include <linux/regulator/driver.h>
20 20
21
21static int bq24022_set_current_limit(struct regulator_dev *rdev, 22static int bq24022_set_current_limit(struct regulator_dev *rdev,
22 int min_uA, int max_uA) 23 int min_uA, int max_uA)
23{ 24{
24 struct platform_device *pdev = rdev_get_drvdata(rdev); 25 struct bq24022_mach_info *pdata = rdev_get_drvdata(rdev);
25 struct bq24022_mach_info *pdata = pdev->dev.platform_data;
26 26
27 dev_dbg(&pdev->dev, "setting current limit to %s mA\n", 27 dev_dbg(rdev_get_dev(rdev), "setting current limit to %s mA\n",
28 max_uA >= 500000 ? "500" : "100"); 28 max_uA >= 500000 ? "500" : "100");
29 29
30 /* REVISIT: maybe return error if min_uA != 0 ? */ 30 /* REVISIT: maybe return error if min_uA != 0 ? */
@@ -34,18 +34,16 @@ static int bq24022_set_current_limit(struct regulator_dev *rdev,
34 34
35static int bq24022_get_current_limit(struct regulator_dev *rdev) 35static int bq24022_get_current_limit(struct regulator_dev *rdev)
36{ 36{
37 struct platform_device *pdev = rdev_get_drvdata(rdev); 37 struct bq24022_mach_info *pdata = rdev_get_drvdata(rdev);
38 struct bq24022_mach_info *pdata = pdev->dev.platform_data;
39 38
40 return gpio_get_value(pdata->gpio_iset2) ? 500000 : 100000; 39 return gpio_get_value(pdata->gpio_iset2) ? 500000 : 100000;
41} 40}
42 41
43static int bq24022_enable(struct regulator_dev *rdev) 42static int bq24022_enable(struct regulator_dev *rdev)
44{ 43{
45 struct platform_device *pdev = rdev_get_drvdata(rdev); 44 struct bq24022_mach_info *pdata = rdev_get_drvdata(rdev);
46 struct bq24022_mach_info *pdata = pdev->dev.platform_data;
47 45
48 dev_dbg(&pdev->dev, "enabling charger\n"); 46 dev_dbg(rdev_get_dev(rdev), "enabling charger\n");
49 47
50 gpio_set_value(pdata->gpio_nce, 0); 48 gpio_set_value(pdata->gpio_nce, 0);
51 return 0; 49 return 0;
@@ -53,10 +51,9 @@ static int bq24022_enable(struct regulator_dev *rdev)
53 51
54static int bq24022_disable(struct regulator_dev *rdev) 52static int bq24022_disable(struct regulator_dev *rdev)
55{ 53{
56 struct platform_device *pdev = rdev_get_drvdata(rdev); 54 struct bq24022_mach_info *pdata = rdev_get_drvdata(rdev);
57 struct bq24022_mach_info *pdata = pdev->dev.platform_data;
58 55
59 dev_dbg(&pdev->dev, "disabling charger\n"); 56 dev_dbg(rdev_get_dev(rdev), "disabling charger\n");
60 57
61 gpio_set_value(pdata->gpio_nce, 1); 58 gpio_set_value(pdata->gpio_nce, 1);
62 return 0; 59 return 0;
@@ -108,7 +105,7 @@ static int __init bq24022_probe(struct platform_device *pdev)
108 ret = gpio_direction_output(pdata->gpio_iset2, 0); 105 ret = gpio_direction_output(pdata->gpio_iset2, 0);
109 ret = gpio_direction_output(pdata->gpio_nce, 1); 106 ret = gpio_direction_output(pdata->gpio_nce, 1);
110 107
111 bq24022 = regulator_register(&bq24022_desc, pdev); 108 bq24022 = regulator_register(&bq24022_desc, &pdev->dev, pdata);
112 if (IS_ERR(bq24022)) { 109 if (IS_ERR(bq24022)) {
113 dev_dbg(&pdev->dev, "couldn't register regulator\n"); 110 dev_dbg(&pdev->dev, "couldn't register regulator\n");
114 ret = PTR_ERR(bq24022); 111 ret = PTR_ERR(bq24022);
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 9c7986261568..02a774424e8d 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -2,8 +2,9 @@
2 * core.c -- Voltage/Current Regulator framework. 2 * core.c -- Voltage/Current Regulator framework.
3 * 3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC. 4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 * Copyright 2008 SlimLogic Ltd.
5 * 6 *
6 * Author: Liam Girdwood <liam.girdwood@wolfsonmicro.com> 7 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
@@ -64,14 +65,9 @@ struct regulator_map {
64 struct list_head list; 65 struct list_head list;
65 struct device *dev; 66 struct device *dev;
66 const char *supply; 67 const char *supply;
67 const char *regulator; 68 struct regulator_dev *regulator;
68}; 69};
69 70
70static inline struct regulator_dev *to_rdev(struct device *d)
71{
72 return container_of(d, struct regulator_dev, dev);
73}
74
75/* 71/*
76 * struct regulator 72 * struct regulator
77 * 73 *
@@ -227,7 +223,7 @@ static ssize_t device_requested_uA_show(struct device *dev,
227static ssize_t regulator_uV_show(struct device *dev, 223static ssize_t regulator_uV_show(struct device *dev,
228 struct device_attribute *attr, char *buf) 224 struct device_attribute *attr, char *buf)
229{ 225{
230 struct regulator_dev *rdev = to_rdev(dev); 226 struct regulator_dev *rdev = dev_get_drvdata(dev);
231 ssize_t ret; 227 ssize_t ret;
232 228
233 mutex_lock(&rdev->mutex); 229 mutex_lock(&rdev->mutex);
@@ -240,15 +236,31 @@ static ssize_t regulator_uV_show(struct device *dev,
240static ssize_t regulator_uA_show(struct device *dev, 236static ssize_t regulator_uA_show(struct device *dev,
241 struct device_attribute *attr, char *buf) 237 struct device_attribute *attr, char *buf)
242{ 238{
243 struct regulator_dev *rdev = to_rdev(dev); 239 struct regulator_dev *rdev = dev_get_drvdata(dev);
244 240
245 return sprintf(buf, "%d\n", _regulator_get_current_limit(rdev)); 241 return sprintf(buf, "%d\n", _regulator_get_current_limit(rdev));
246} 242}
247 243
244static ssize_t regulator_name_show(struct device *dev,
245 struct device_attribute *attr, char *buf)
246{
247 struct regulator_dev *rdev = dev_get_drvdata(dev);
248 const char *name;
249
250 if (rdev->constraints->name)
251 name = rdev->constraints->name;
252 else if (rdev->desc->name)
253 name = rdev->desc->name;
254 else
255 name = "";
256
257 return sprintf(buf, "%s\n", name);
258}
259
248static ssize_t regulator_opmode_show(struct device *dev, 260static ssize_t regulator_opmode_show(struct device *dev,
249 struct device_attribute *attr, char *buf) 261 struct device_attribute *attr, char *buf)
250{ 262{
251 struct regulator_dev *rdev = to_rdev(dev); 263 struct regulator_dev *rdev = dev_get_drvdata(dev);
252 int mode = _regulator_get_mode(rdev); 264 int mode = _regulator_get_mode(rdev);
253 265
254 switch (mode) { 266 switch (mode) {
@@ -267,7 +279,7 @@ static ssize_t regulator_opmode_show(struct device *dev,
267static ssize_t regulator_state_show(struct device *dev, 279static ssize_t regulator_state_show(struct device *dev,
268 struct device_attribute *attr, char *buf) 280 struct device_attribute *attr, char *buf)
269{ 281{
270 struct regulator_dev *rdev = to_rdev(dev); 282 struct regulator_dev *rdev = dev_get_drvdata(dev);
271 int state = _regulator_is_enabled(rdev); 283 int state = _regulator_is_enabled(rdev);
272 284
273 if (state > 0) 285 if (state > 0)
@@ -281,7 +293,7 @@ static ssize_t regulator_state_show(struct device *dev,
281static ssize_t regulator_min_uA_show(struct device *dev, 293static ssize_t regulator_min_uA_show(struct device *dev,
282 struct device_attribute *attr, char *buf) 294 struct device_attribute *attr, char *buf)
283{ 295{
284 struct regulator_dev *rdev = to_rdev(dev); 296 struct regulator_dev *rdev = dev_get_drvdata(dev);
285 297
286 if (!rdev->constraints) 298 if (!rdev->constraints)
287 return sprintf(buf, "constraint not defined\n"); 299 return sprintf(buf, "constraint not defined\n");
@@ -292,7 +304,7 @@ static ssize_t regulator_min_uA_show(struct device *dev,
292static ssize_t regulator_max_uA_show(struct device *dev, 304static ssize_t regulator_max_uA_show(struct device *dev,
293 struct device_attribute *attr, char *buf) 305 struct device_attribute *attr, char *buf)
294{ 306{
295 struct regulator_dev *rdev = to_rdev(dev); 307 struct regulator_dev *rdev = dev_get_drvdata(dev);
296 308
297 if (!rdev->constraints) 309 if (!rdev->constraints)
298 return sprintf(buf, "constraint not defined\n"); 310 return sprintf(buf, "constraint not defined\n");
@@ -303,7 +315,7 @@ static ssize_t regulator_max_uA_show(struct device *dev,
303static ssize_t regulator_min_uV_show(struct device *dev, 315static ssize_t regulator_min_uV_show(struct device *dev,
304 struct device_attribute *attr, char *buf) 316 struct device_attribute *attr, char *buf)
305{ 317{
306 struct regulator_dev *rdev = to_rdev(dev); 318 struct regulator_dev *rdev = dev_get_drvdata(dev);
307 319
308 if (!rdev->constraints) 320 if (!rdev->constraints)
309 return sprintf(buf, "constraint not defined\n"); 321 return sprintf(buf, "constraint not defined\n");
@@ -314,7 +326,7 @@ static ssize_t regulator_min_uV_show(struct device *dev,
314static ssize_t regulator_max_uV_show(struct device *dev, 326static ssize_t regulator_max_uV_show(struct device *dev,
315 struct device_attribute *attr, char *buf) 327 struct device_attribute *attr, char *buf)
316{ 328{
317 struct regulator_dev *rdev = to_rdev(dev); 329 struct regulator_dev *rdev = dev_get_drvdata(dev);
318 330
319 if (!rdev->constraints) 331 if (!rdev->constraints)
320 return sprintf(buf, "constraint not defined\n"); 332 return sprintf(buf, "constraint not defined\n");
@@ -325,7 +337,7 @@ static ssize_t regulator_max_uV_show(struct device *dev,
325static ssize_t regulator_total_uA_show(struct device *dev, 337static ssize_t regulator_total_uA_show(struct device *dev,
326 struct device_attribute *attr, char *buf) 338 struct device_attribute *attr, char *buf)
327{ 339{
328 struct regulator_dev *rdev = to_rdev(dev); 340 struct regulator_dev *rdev = dev_get_drvdata(dev);
329 struct regulator *regulator; 341 struct regulator *regulator;
330 int uA = 0; 342 int uA = 0;
331 343
@@ -339,14 +351,14 @@ static ssize_t regulator_total_uA_show(struct device *dev,
339static ssize_t regulator_num_users_show(struct device *dev, 351static ssize_t regulator_num_users_show(struct device *dev,
340 struct device_attribute *attr, char *buf) 352 struct device_attribute *attr, char *buf)
341{ 353{
342 struct regulator_dev *rdev = to_rdev(dev); 354 struct regulator_dev *rdev = dev_get_drvdata(dev);
343 return sprintf(buf, "%d\n", rdev->use_count); 355 return sprintf(buf, "%d\n", rdev->use_count);
344} 356}
345 357
346static ssize_t regulator_type_show(struct device *dev, 358static ssize_t regulator_type_show(struct device *dev,
347 struct device_attribute *attr, char *buf) 359 struct device_attribute *attr, char *buf)
348{ 360{
349 struct regulator_dev *rdev = to_rdev(dev); 361 struct regulator_dev *rdev = dev_get_drvdata(dev);
350 362
351 switch (rdev->desc->type) { 363 switch (rdev->desc->type) {
352 case REGULATOR_VOLTAGE: 364 case REGULATOR_VOLTAGE:
@@ -360,7 +372,7 @@ static ssize_t regulator_type_show(struct device *dev,
360static ssize_t regulator_suspend_mem_uV_show(struct device *dev, 372static ssize_t regulator_suspend_mem_uV_show(struct device *dev,
361 struct device_attribute *attr, char *buf) 373 struct device_attribute *attr, char *buf)
362{ 374{
363 struct regulator_dev *rdev = to_rdev(dev); 375 struct regulator_dev *rdev = dev_get_drvdata(dev);
364 376
365 if (!rdev->constraints) 377 if (!rdev->constraints)
366 return sprintf(buf, "not defined\n"); 378 return sprintf(buf, "not defined\n");
@@ -370,7 +382,7 @@ static ssize_t regulator_suspend_mem_uV_show(struct device *dev,
370static ssize_t regulator_suspend_disk_uV_show(struct device *dev, 382static ssize_t regulator_suspend_disk_uV_show(struct device *dev,
371 struct device_attribute *attr, char *buf) 383 struct device_attribute *attr, char *buf)
372{ 384{
373 struct regulator_dev *rdev = to_rdev(dev); 385 struct regulator_dev *rdev = dev_get_drvdata(dev);
374 386
375 if (!rdev->constraints) 387 if (!rdev->constraints)
376 return sprintf(buf, "not defined\n"); 388 return sprintf(buf, "not defined\n");
@@ -380,7 +392,7 @@ static ssize_t regulator_suspend_disk_uV_show(struct device *dev,
380static ssize_t regulator_suspend_standby_uV_show(struct device *dev, 392static ssize_t regulator_suspend_standby_uV_show(struct device *dev,
381 struct device_attribute *attr, char *buf) 393 struct device_attribute *attr, char *buf)
382{ 394{
383 struct regulator_dev *rdev = to_rdev(dev); 395 struct regulator_dev *rdev = dev_get_drvdata(dev);
384 396
385 if (!rdev->constraints) 397 if (!rdev->constraints)
386 return sprintf(buf, "not defined\n"); 398 return sprintf(buf, "not defined\n");
@@ -406,7 +418,7 @@ static ssize_t suspend_opmode_show(struct regulator_dev *rdev,
406static ssize_t regulator_suspend_mem_mode_show(struct device *dev, 418static ssize_t regulator_suspend_mem_mode_show(struct device *dev,
407 struct device_attribute *attr, char *buf) 419 struct device_attribute *attr, char *buf)
408{ 420{
409 struct regulator_dev *rdev = to_rdev(dev); 421 struct regulator_dev *rdev = dev_get_drvdata(dev);
410 422
411 if (!rdev->constraints) 423 if (!rdev->constraints)
412 return sprintf(buf, "not defined\n"); 424 return sprintf(buf, "not defined\n");
@@ -417,7 +429,7 @@ static ssize_t regulator_suspend_mem_mode_show(struct device *dev,
417static ssize_t regulator_suspend_disk_mode_show(struct device *dev, 429static ssize_t regulator_suspend_disk_mode_show(struct device *dev,
418 struct device_attribute *attr, char *buf) 430 struct device_attribute *attr, char *buf)
419{ 431{
420 struct regulator_dev *rdev = to_rdev(dev); 432 struct regulator_dev *rdev = dev_get_drvdata(dev);
421 433
422 if (!rdev->constraints) 434 if (!rdev->constraints)
423 return sprintf(buf, "not defined\n"); 435 return sprintf(buf, "not defined\n");
@@ -428,7 +440,7 @@ static ssize_t regulator_suspend_disk_mode_show(struct device *dev,
428static ssize_t regulator_suspend_standby_mode_show(struct device *dev, 440static ssize_t regulator_suspend_standby_mode_show(struct device *dev,
429 struct device_attribute *attr, char *buf) 441 struct device_attribute *attr, char *buf)
430{ 442{
431 struct regulator_dev *rdev = to_rdev(dev); 443 struct regulator_dev *rdev = dev_get_drvdata(dev);
432 444
433 if (!rdev->constraints) 445 if (!rdev->constraints)
434 return sprintf(buf, "not defined\n"); 446 return sprintf(buf, "not defined\n");
@@ -439,7 +451,7 @@ static ssize_t regulator_suspend_standby_mode_show(struct device *dev,
439static ssize_t regulator_suspend_mem_state_show(struct device *dev, 451static ssize_t regulator_suspend_mem_state_show(struct device *dev,
440 struct device_attribute *attr, char *buf) 452 struct device_attribute *attr, char *buf)
441{ 453{
442 struct regulator_dev *rdev = to_rdev(dev); 454 struct regulator_dev *rdev = dev_get_drvdata(dev);
443 455
444 if (!rdev->constraints) 456 if (!rdev->constraints)
445 return sprintf(buf, "not defined\n"); 457 return sprintf(buf, "not defined\n");
@@ -453,7 +465,7 @@ static ssize_t regulator_suspend_mem_state_show(struct device *dev,
453static ssize_t regulator_suspend_disk_state_show(struct device *dev, 465static ssize_t regulator_suspend_disk_state_show(struct device *dev,
454 struct device_attribute *attr, char *buf) 466 struct device_attribute *attr, char *buf)
455{ 467{
456 struct regulator_dev *rdev = to_rdev(dev); 468 struct regulator_dev *rdev = dev_get_drvdata(dev);
457 469
458 if (!rdev->constraints) 470 if (!rdev->constraints)
459 return sprintf(buf, "not defined\n"); 471 return sprintf(buf, "not defined\n");
@@ -467,7 +479,7 @@ static ssize_t regulator_suspend_disk_state_show(struct device *dev,
467static ssize_t regulator_suspend_standby_state_show(struct device *dev, 479static ssize_t regulator_suspend_standby_state_show(struct device *dev,
468 struct device_attribute *attr, char *buf) 480 struct device_attribute *attr, char *buf)
469{ 481{
470 struct regulator_dev *rdev = to_rdev(dev); 482 struct regulator_dev *rdev = dev_get_drvdata(dev);
471 483
472 if (!rdev->constraints) 484 if (!rdev->constraints)
473 return sprintf(buf, "not defined\n"); 485 return sprintf(buf, "not defined\n");
@@ -477,7 +489,9 @@ static ssize_t regulator_suspend_standby_state_show(struct device *dev,
477 else 489 else
478 return sprintf(buf, "disabled\n"); 490 return sprintf(buf, "disabled\n");
479} 491}
492
480static struct device_attribute regulator_dev_attrs[] = { 493static struct device_attribute regulator_dev_attrs[] = {
494 __ATTR(name, 0444, regulator_name_show, NULL),
481 __ATTR(microvolts, 0444, regulator_uV_show, NULL), 495 __ATTR(microvolts, 0444, regulator_uV_show, NULL),
482 __ATTR(microamps, 0444, regulator_uA_show, NULL), 496 __ATTR(microamps, 0444, regulator_uA_show, NULL),
483 __ATTR(opmode, 0444, regulator_opmode_show, NULL), 497 __ATTR(opmode, 0444, regulator_opmode_show, NULL),
@@ -512,7 +526,7 @@ static struct device_attribute regulator_dev_attrs[] = {
512 526
513static void regulator_dev_release(struct device *dev) 527static void regulator_dev_release(struct device *dev)
514{ 528{
515 struct regulator_dev *rdev = to_rdev(dev); 529 struct regulator_dev *rdev = dev_get_drvdata(dev);
516 kfree(rdev); 530 kfree(rdev);
517} 531}
518 532
@@ -569,8 +583,11 @@ static int suspend_set_state(struct regulator_dev *rdev,
569 583
570 /* enable & disable are mandatory for suspend control */ 584 /* enable & disable are mandatory for suspend control */
571 if (!rdev->desc->ops->set_suspend_enable || 585 if (!rdev->desc->ops->set_suspend_enable ||
572 !rdev->desc->ops->set_suspend_disable) 586 !rdev->desc->ops->set_suspend_disable) {
587 printk(KERN_ERR "%s: no way to set suspend state\n",
588 __func__);
573 return -EINVAL; 589 return -EINVAL;
590 }
574 591
575 if (rstate->enabled) 592 if (rstate->enabled)
576 ret = rdev->desc->ops->set_suspend_enable(rdev); 593 ret = rdev->desc->ops->set_suspend_enable(rdev);
@@ -656,6 +673,155 @@ static void print_constraints(struct regulator_dev *rdev)
656 printk(KERN_INFO "regulator: %s: %s\n", rdev->desc->name, buf); 673 printk(KERN_INFO "regulator: %s: %s\n", rdev->desc->name, buf);
657} 674}
658 675
676/**
677 * set_machine_constraints - sets regulator constraints
678 * @regulator: regulator source
679 *
680 * Allows platform initialisation code to define and constrain
681 * regulator circuits e.g. valid voltage/current ranges, etc. NOTE:
682 * Constraints *must* be set by platform code in order for some
683 * regulator operations to proceed i.e. set_voltage, set_current_limit,
684 * set_mode.
685 */
686static int set_machine_constraints(struct regulator_dev *rdev,
687 struct regulation_constraints *constraints)
688{
689 int ret = 0;
690 const char *name;
691 struct regulator_ops *ops = rdev->desc->ops;
692
693 if (constraints->name)
694 name = constraints->name;
695 else if (rdev->desc->name)
696 name = rdev->desc->name;
697 else
698 name = "regulator";
699
700 rdev->constraints = constraints;
701
702 /* do we need to apply the constraint voltage */
703 if (rdev->constraints->apply_uV &&
704 rdev->constraints->min_uV == rdev->constraints->max_uV &&
705 ops->set_voltage) {
706 ret = ops->set_voltage(rdev,
707 rdev->constraints->min_uV, rdev->constraints->max_uV);
708 if (ret < 0) {
709 printk(KERN_ERR "%s: failed to apply %duV constraint to %s\n",
710 __func__,
711 rdev->constraints->min_uV, name);
712 rdev->constraints = NULL;
713 goto out;
714 }
715 }
716
717 /* are we enabled at boot time by firmware / bootloader */
718 if (rdev->constraints->boot_on)
719 rdev->use_count = 1;
720
721 /* do we need to setup our suspend state */
722 if (constraints->initial_state) {
723 ret = suspend_prepare(rdev, constraints->initial_state);
724 if (ret < 0) {
725 printk(KERN_ERR "%s: failed to set suspend state for %s\n",
726 __func__, name);
727 rdev->constraints = NULL;
728 goto out;
729 }
730 }
731
732 /* if always_on is set then turn the regulator on if it's not
733 * already on. */
734 if (constraints->always_on && ops->enable &&
735 ((ops->is_enabled && !ops->is_enabled(rdev)) ||
736 (!ops->is_enabled && !constraints->boot_on))) {
737 ret = ops->enable(rdev);
738 if (ret < 0) {
739 printk(KERN_ERR "%s: failed to enable %s\n",
740 __func__, name);
741 rdev->constraints = NULL;
742 goto out;
743 }
744 }
745
746 print_constraints(rdev);
747out:
748 return ret;
749}
750
751/**
752 * set_supply - set regulator supply regulator
753 * @regulator: regulator name
754 * @supply: supply regulator name
755 *
756 * Called by platform initialisation code to set the supply regulator for this
757 * regulator. This ensures that a regulators supply will also be enabled by the
758 * core if it's child is enabled.
759 */
760static int set_supply(struct regulator_dev *rdev,
761 struct regulator_dev *supply_rdev)
762{
763 int err;
764
765 err = sysfs_create_link(&rdev->dev.kobj, &supply_rdev->dev.kobj,
766 "supply");
767 if (err) {
768 printk(KERN_ERR
769 "%s: could not add device link %s err %d\n",
770 __func__, supply_rdev->dev.kobj.name, err);
771 goto out;
772 }
773 rdev->supply = supply_rdev;
774 list_add(&rdev->slist, &supply_rdev->supply_list);
775out:
776 return err;
777}
778
779/**
780 * set_consumer_device_supply: Bind a regulator to a symbolic supply
781 * @regulator: regulator source
782 * @dev: device the supply applies to
783 * @supply: symbolic name for supply
784 *
785 * Allows platform initialisation code to map physical regulator
786 * sources to symbolic names for supplies for use by devices. Devices
787 * should use these symbolic names to request regulators, avoiding the
788 * need to provide board-specific regulator names as platform data.
789 */
790static int set_consumer_device_supply(struct regulator_dev *rdev,
791 struct device *consumer_dev, const char *supply)
792{
793 struct regulator_map *node;
794
795 if (supply == NULL)
796 return -EINVAL;
797
798 node = kmalloc(sizeof(struct regulator_map), GFP_KERNEL);
799 if (node == NULL)
800 return -ENOMEM;
801
802 node->regulator = rdev;
803 node->dev = consumer_dev;
804 node->supply = supply;
805
806 list_add(&node->list, &regulator_map_list);
807 return 0;
808}
809
810static void unset_consumer_device_supply(struct regulator_dev *rdev,
811 struct device *consumer_dev)
812{
813 struct regulator_map *node, *n;
814
815 list_for_each_entry_safe(node, n, &regulator_map_list, list) {
816 if (rdev == node->regulator &&
817 consumer_dev == node->dev) {
818 list_del(&node->list);
819 kfree(node);
820 return;
821 }
822 }
823}
824
659#define REG_STR_SIZE 32 825#define REG_STR_SIZE 32
660 826
661static struct regulator *create_regulator(struct regulator_dev *rdev, 827static struct regulator *create_regulator(struct regulator_dev *rdev,
@@ -746,7 +912,6 @@ struct regulator *regulator_get(struct device *dev, const char *id)
746 struct regulator_dev *rdev; 912 struct regulator_dev *rdev;
747 struct regulator_map *map; 913 struct regulator_map *map;
748 struct regulator *regulator = ERR_PTR(-ENODEV); 914 struct regulator *regulator = ERR_PTR(-ENODEV);
749 const char *supply = id;
750 915
751 if (id == NULL) { 916 if (id == NULL) {
752 printk(KERN_ERR "regulator: get() with no identifier\n"); 917 printk(KERN_ERR "regulator: get() with no identifier\n");
@@ -758,15 +923,9 @@ struct regulator *regulator_get(struct device *dev, const char *id)
758 list_for_each_entry(map, &regulator_map_list, list) { 923 list_for_each_entry(map, &regulator_map_list, list) {
759 if (dev == map->dev && 924 if (dev == map->dev &&
760 strcmp(map->supply, id) == 0) { 925 strcmp(map->supply, id) == 0) {
761 supply = map->regulator; 926 rdev = map->regulator;
762 break;
763 }
764 }
765
766 list_for_each_entry(rdev, &regulator_list, list) {
767 if (strcmp(supply, rdev->desc->name) == 0 &&
768 try_module_get(rdev->owner))
769 goto found; 927 goto found;
928 }
770 } 929 }
771 printk(KERN_ERR "regulator: Unable to get requested regulator: %s\n", 930 printk(KERN_ERR "regulator: Unable to get requested regulator: %s\n",
772 id); 931 id);
@@ -774,12 +933,16 @@ struct regulator *regulator_get(struct device *dev, const char *id)
774 return regulator; 933 return regulator;
775 934
776found: 935found:
936 if (!try_module_get(rdev->owner))
937 goto out;
938
777 regulator = create_regulator(rdev, dev, id); 939 regulator = create_regulator(rdev, dev, id);
778 if (regulator == NULL) { 940 if (regulator == NULL) {
779 regulator = ERR_PTR(-ENOMEM); 941 regulator = ERR_PTR(-ENOMEM);
780 module_put(rdev->owner); 942 module_put(rdev->owner);
781 } 943 }
782 944
945out:
783 mutex_unlock(&regulator_list_mutex); 946 mutex_unlock(&regulator_list_mutex);
784 return regulator; 947 return regulator;
785} 948}
@@ -1559,11 +1722,12 @@ EXPORT_SYMBOL_GPL(regulator_notifier_call_chain);
1559 * Returns 0 on success. 1722 * Returns 0 on success.
1560 */ 1723 */
1561struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc, 1724struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc,
1562 void *reg_data) 1725 struct device *dev, void *driver_data)
1563{ 1726{
1564 static atomic_t regulator_no = ATOMIC_INIT(0); 1727 static atomic_t regulator_no = ATOMIC_INIT(0);
1565 struct regulator_dev *rdev; 1728 struct regulator_dev *rdev;
1566 int ret; 1729 struct regulator_init_data *init_data = dev->platform_data;
1730 int ret, i;
1567 1731
1568 if (regulator_desc == NULL) 1732 if (regulator_desc == NULL)
1569 return ERR_PTR(-EINVAL); 1733 return ERR_PTR(-EINVAL);
@@ -1575,6 +1739,9 @@ struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc,
1575 !regulator_desc->type == REGULATOR_CURRENT) 1739 !regulator_desc->type == REGULATOR_CURRENT)
1576 return ERR_PTR(-EINVAL); 1740 return ERR_PTR(-EINVAL);
1577 1741
1742 if (!init_data)
1743 return ERR_PTR(-EINVAL);
1744
1578 rdev = kzalloc(sizeof(struct regulator_dev), GFP_KERNEL); 1745 rdev = kzalloc(sizeof(struct regulator_dev), GFP_KERNEL);
1579 if (rdev == NULL) 1746 if (rdev == NULL)
1580 return ERR_PTR(-ENOMEM); 1747 return ERR_PTR(-ENOMEM);
@@ -1582,7 +1749,7 @@ struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc,
1582 mutex_lock(&regulator_list_mutex); 1749 mutex_lock(&regulator_list_mutex);
1583 1750
1584 mutex_init(&rdev->mutex); 1751 mutex_init(&rdev->mutex);
1585 rdev->reg_data = reg_data; 1752 rdev->reg_data = driver_data;
1586 rdev->owner = regulator_desc->owner; 1753 rdev->owner = regulator_desc->owner;
1587 rdev->desc = regulator_desc; 1754 rdev->desc = regulator_desc;
1588 INIT_LIST_HEAD(&rdev->consumer_list); 1755 INIT_LIST_HEAD(&rdev->consumer_list);
@@ -1591,20 +1758,68 @@ struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc,
1591 INIT_LIST_HEAD(&rdev->slist); 1758 INIT_LIST_HEAD(&rdev->slist);
1592 BLOCKING_INIT_NOTIFIER_HEAD(&rdev->notifier); 1759 BLOCKING_INIT_NOTIFIER_HEAD(&rdev->notifier);
1593 1760
1761 /* preform any regulator specific init */
1762 if (init_data->regulator_init) {
1763 ret = init_data->regulator_init(rdev->reg_data);
1764 if (ret < 0) {
1765 kfree(rdev);
1766 rdev = ERR_PTR(ret);
1767 goto out;
1768 }
1769 }
1770
1771 /* set regulator constraints */
1772 ret = set_machine_constraints(rdev, &init_data->constraints);
1773 if (ret < 0) {
1774 kfree(rdev);
1775 rdev = ERR_PTR(ret);
1776 goto out;
1777 }
1778
1779 /* register with sysfs */
1594 rdev->dev.class = &regulator_class; 1780 rdev->dev.class = &regulator_class;
1595 device_initialize(&rdev->dev); 1781 rdev->dev.parent = dev;
1596 snprintf(rdev->dev.bus_id, sizeof(rdev->dev.bus_id), 1782 snprintf(rdev->dev.bus_id, sizeof(rdev->dev.bus_id),
1597 "regulator_%ld_%s", 1783 "regulator.%d", atomic_inc_return(&regulator_no) - 1);
1598 (unsigned long)atomic_inc_return(&regulator_no) - 1, 1784 ret = device_register(&rdev->dev);
1599 regulator_desc->name); 1785 if (ret != 0) {
1600
1601 ret = device_add(&rdev->dev);
1602 if (ret == 0)
1603 list_add(&rdev->list, &regulator_list);
1604 else {
1605 kfree(rdev); 1786 kfree(rdev);
1606 rdev = ERR_PTR(ret); 1787 rdev = ERR_PTR(ret);
1788 goto out;
1789 }
1790
1791 dev_set_drvdata(&rdev->dev, rdev);
1792
1793 /* set supply regulator if it exists */
1794 if (init_data->supply_regulator_dev) {
1795 ret = set_supply(rdev,
1796 dev_get_drvdata(init_data->supply_regulator_dev));
1797 if (ret < 0) {
1798 device_unregister(&rdev->dev);
1799 kfree(rdev);
1800 rdev = ERR_PTR(ret);
1801 goto out;
1802 }
1607 } 1803 }
1804
1805 /* add consumers devices */
1806 for (i = 0; i < init_data->num_consumer_supplies; i++) {
1807 ret = set_consumer_device_supply(rdev,
1808 init_data->consumer_supplies[i].dev,
1809 init_data->consumer_supplies[i].supply);
1810 if (ret < 0) {
1811 for (--i; i >= 0; i--)
1812 unset_consumer_device_supply(rdev,
1813 init_data->consumer_supplies[i].dev);
1814 device_unregister(&rdev->dev);
1815 kfree(rdev);
1816 rdev = ERR_PTR(ret);
1817 goto out;
1818 }
1819 }
1820
1821 list_add(&rdev->list, &regulator_list);
1822out:
1608 mutex_unlock(&regulator_list_mutex); 1823 mutex_unlock(&regulator_list_mutex);
1609 return rdev; 1824 return rdev;
1610} 1825}
@@ -1631,187 +1846,6 @@ void regulator_unregister(struct regulator_dev *rdev)
1631EXPORT_SYMBOL_GPL(regulator_unregister); 1846EXPORT_SYMBOL_GPL(regulator_unregister);
1632 1847
1633/** 1848/**
1634 * regulator_set_supply - set regulator supply regulator
1635 * @regulator: regulator name
1636 * @supply: supply regulator name
1637 *
1638 * Called by platform initialisation code to set the supply regulator for this
1639 * regulator. This ensures that a regulators supply will also be enabled by the
1640 * core if it's child is enabled.
1641 */
1642int regulator_set_supply(const char *regulator, const char *supply)
1643{
1644 struct regulator_dev *rdev, *supply_rdev;
1645 int err;
1646
1647 if (regulator == NULL || supply == NULL)
1648 return -EINVAL;
1649
1650 mutex_lock(&regulator_list_mutex);
1651
1652 list_for_each_entry(rdev, &regulator_list, list) {
1653 if (!strcmp(rdev->desc->name, regulator))
1654 goto found_regulator;
1655 }
1656 mutex_unlock(&regulator_list_mutex);
1657 return -ENODEV;
1658
1659found_regulator:
1660 list_for_each_entry(supply_rdev, &regulator_list, list) {
1661 if (!strcmp(supply_rdev->desc->name, supply))
1662 goto found_supply;
1663 }
1664 mutex_unlock(&regulator_list_mutex);
1665 return -ENODEV;
1666
1667found_supply:
1668 err = sysfs_create_link(&rdev->dev.kobj, &supply_rdev->dev.kobj,
1669 "supply");
1670 if (err) {
1671 printk(KERN_ERR
1672 "%s: could not add device link %s err %d\n",
1673 __func__, supply_rdev->dev.kobj.name, err);
1674 goto out;
1675 }
1676 rdev->supply = supply_rdev;
1677 list_add(&rdev->slist, &supply_rdev->supply_list);
1678out:
1679 mutex_unlock(&regulator_list_mutex);
1680 return err;
1681}
1682EXPORT_SYMBOL_GPL(regulator_set_supply);
1683
1684/**
1685 * regulator_get_supply - get regulator supply regulator
1686 * @regulator: regulator name
1687 *
1688 * Returns the supply supply regulator name or NULL if no supply regulator
1689 * exists (i.e the regulator is supplied directly from USB, Line, Battery, etc)
1690 */
1691const char *regulator_get_supply(const char *regulator)
1692{
1693 struct regulator_dev *rdev;
1694
1695 if (regulator == NULL)
1696 return NULL;
1697
1698 mutex_lock(&regulator_list_mutex);
1699 list_for_each_entry(rdev, &regulator_list, list) {
1700 if (!strcmp(rdev->desc->name, regulator))
1701 goto found;
1702 }
1703 mutex_unlock(&regulator_list_mutex);
1704 return NULL;
1705
1706found:
1707 mutex_unlock(&regulator_list_mutex);
1708 if (rdev->supply)
1709 return rdev->supply->desc->name;
1710 else
1711 return NULL;
1712}
1713EXPORT_SYMBOL_GPL(regulator_get_supply);
1714
1715/**
1716 * regulator_set_machine_constraints - sets regulator constraints
1717 * @regulator: regulator source
1718 *
1719 * Allows platform initialisation code to define and constrain
1720 * regulator circuits e.g. valid voltage/current ranges, etc. NOTE:
1721 * Constraints *must* be set by platform code in order for some
1722 * regulator operations to proceed i.e. set_voltage, set_current_limit,
1723 * set_mode.
1724 */
1725int regulator_set_machine_constraints(const char *regulator_name,
1726 struct regulation_constraints *constraints)
1727{
1728 struct regulator_dev *rdev;
1729 int ret = 0;
1730
1731 if (regulator_name == NULL)
1732 return -EINVAL;
1733
1734 mutex_lock(&regulator_list_mutex);
1735
1736 list_for_each_entry(rdev, &regulator_list, list) {
1737 if (!strcmp(regulator_name, rdev->desc->name))
1738 goto found;
1739 }
1740 ret = -ENODEV;
1741 goto out;
1742
1743found:
1744 mutex_lock(&rdev->mutex);
1745 rdev->constraints = constraints;
1746
1747 /* do we need to apply the constraint voltage */
1748 if (rdev->constraints->apply_uV &&
1749 rdev->constraints->min_uV == rdev->constraints->max_uV &&
1750 rdev->desc->ops->set_voltage) {
1751 ret = rdev->desc->ops->set_voltage(rdev,
1752 rdev->constraints->min_uV, rdev->constraints->max_uV);
1753 if (ret < 0) {
1754 printk(KERN_ERR "%s: failed to apply %duV"
1755 " constraint\n", __func__,
1756 rdev->constraints->min_uV);
1757 rdev->constraints = NULL;
1758 goto out;
1759 }
1760 }
1761
1762 /* are we enabled at boot time by firmware / bootloader */
1763 if (rdev->constraints->boot_on)
1764 rdev->use_count = 1;
1765
1766 /* do we need to setup our suspend state */
1767 if (constraints->initial_state)
1768 ret = suspend_prepare(rdev, constraints->initial_state);
1769
1770 print_constraints(rdev);
1771 mutex_unlock(&rdev->mutex);
1772
1773out:
1774 mutex_unlock(&regulator_list_mutex);
1775 return ret;
1776}
1777EXPORT_SYMBOL_GPL(regulator_set_machine_constraints);
1778
1779
1780/**
1781 * regulator_set_device_supply: Bind a regulator to a symbolic supply
1782 * @regulator: regulator source
1783 * @dev: device the supply applies to
1784 * @supply: symbolic name for supply
1785 *
1786 * Allows platform initialisation code to map physical regulator
1787 * sources to symbolic names for supplies for use by devices. Devices
1788 * should use these symbolic names to request regulators, avoiding the
1789 * need to provide board-specific regulator names as platform data.
1790 */
1791int regulator_set_device_supply(const char *regulator, struct device *dev,
1792 const char *supply)
1793{
1794 struct regulator_map *node;
1795
1796 if (regulator == NULL || supply == NULL)
1797 return -EINVAL;
1798
1799 node = kmalloc(sizeof(struct regulator_map), GFP_KERNEL);
1800 if (node == NULL)
1801 return -ENOMEM;
1802
1803 node->regulator = regulator;
1804 node->dev = dev;
1805 node->supply = supply;
1806
1807 mutex_lock(&regulator_list_mutex);
1808 list_add(&node->list, &regulator_map_list);
1809 mutex_unlock(&regulator_list_mutex);
1810 return 0;
1811}
1812EXPORT_SYMBOL_GPL(regulator_set_device_supply);
1813
1814/**
1815 * regulator_suspend_prepare: prepare regulators for system wide suspend 1849 * regulator_suspend_prepare: prepare regulators for system wide suspend
1816 * @state: system suspend state 1850 * @state: system suspend state
1817 * 1851 *
@@ -1893,6 +1927,18 @@ int rdev_get_id(struct regulator_dev *rdev)
1893} 1927}
1894EXPORT_SYMBOL_GPL(rdev_get_id); 1928EXPORT_SYMBOL_GPL(rdev_get_id);
1895 1929
1930struct device *rdev_get_dev(struct regulator_dev *rdev)
1931{
1932 return &rdev->dev;
1933}
1934EXPORT_SYMBOL_GPL(rdev_get_dev);
1935
1936void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data)
1937{
1938 return reg_init_data->driver_data;
1939}
1940EXPORT_SYMBOL_GPL(regulator_get_init_drvdata);
1941
1896static int __init regulator_init(void) 1942static int __init regulator_init(void)
1897{ 1943{
1898 printk(KERN_INFO "regulator: core version %s\n", REGULATOR_VERSION); 1944 printk(KERN_INFO "regulator: core version %s\n", REGULATOR_VERSION);
diff --git a/drivers/regulator/da903x.c b/drivers/regulator/da903x.c
new file mode 100644
index 000000000000..3688e339db87
--- /dev/null
+++ b/drivers/regulator/da903x.c
@@ -0,0 +1,513 @@
1/*
2 * Regulators driver for Dialog Semiconductor DA903x
3 *
4 * Copyright (C) 2006-2008 Marvell International Ltd.
5 * Copyright (C) 2008 Compulab Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/err.h>
15#include <linux/platform_device.h>
16#include <linux/regulator/driver.h>
17#include <linux/regulator/machine.h>
18#include <linux/mfd/da903x.h>
19
20/* DA9030 Registers */
21#define DA9030_INVAL (-1)
22#define DA9030_LDO1011 (0x10)
23#define DA9030_LDO15 (0x11)
24#define DA9030_LDO1416 (0x12)
25#define DA9030_LDO1819 (0x13)
26#define DA9030_LDO17 (0x14)
27#define DA9030_BUCK2DVM1 (0x15)
28#define DA9030_BUCK2DVM2 (0x16)
29#define DA9030_RCTL11 (0x17)
30#define DA9030_RCTL21 (0x18)
31#define DA9030_LDO1 (0x90)
32#define DA9030_LDO23 (0x91)
33#define DA9030_LDO45 (0x92)
34#define DA9030_LDO6 (0x93)
35#define DA9030_LDO78 (0x94)
36#define DA9030_LDO912 (0x95)
37#define DA9030_BUCK (0x96)
38#define DA9030_RCTL12 (0x97)
39#define DA9030_RCTL22 (0x98)
40#define DA9030_LDO_UNLOCK (0xa0)
41#define DA9030_LDO_UNLOCK_MASK (0xe0)
42#define DA9034_OVER1 (0x10)
43
44/* DA9034 Registers */
45#define DA9034_INVAL (-1)
46#define DA9034_OVER2 (0x11)
47#define DA9034_OVER3 (0x12)
48#define DA9034_LDO643 (0x13)
49#define DA9034_LDO987 (0x14)
50#define DA9034_LDO1110 (0x15)
51#define DA9034_LDO1312 (0x16)
52#define DA9034_LDO1514 (0x17)
53#define DA9034_VCC1 (0x20)
54#define DA9034_ADTV1 (0x23)
55#define DA9034_ADTV2 (0x24)
56#define DA9034_AVRC (0x25)
57#define DA9034_CDTV1 (0x26)
58#define DA9034_CDTV2 (0x27)
59#define DA9034_CVRC (0x28)
60#define DA9034_SDTV1 (0x29)
61#define DA9034_SDTV2 (0x2a)
62#define DA9034_SVRC (0x2b)
63#define DA9034_MDTV1 (0x32)
64#define DA9034_MDTV2 (0x33)
65#define DA9034_MVRC (0x34)
66
67struct da903x_regulator_info {
68 struct regulator_desc desc;
69
70 int min_uV;
71 int max_uV;
72 int step_uV;
73 int vol_reg;
74 int vol_shift;
75 int vol_nbits;
76 int update_reg;
77 int update_bit;
78 int enable_reg;
79 int enable_bit;
80};
81
82static inline int check_range(struct da903x_regulator_info *info,
83 int min_uV, int max_uV)
84{
85 if (min_uV < info->min_uV || min_uV > info->max_uV)
86 return -EINVAL;
87
88 return 0;
89}
90
91/* DA9030/DA9034 common operations */
92static int da903x_set_ldo_voltage(struct regulator_dev *rdev,
93 int min_uV, int max_uV)
94{
95 struct da903x_regulator_info *info = rdev_get_drvdata(rdev);
96 struct device *da9034_dev = rdev_get_dev(rdev)->parent;
97 uint8_t val, mask;
98
99 if (check_range(info, min_uV, max_uV)) {
100 pr_err("invalid voltage range (%d, %d) uV", min_uV, max_uV);
101 return -EINVAL;
102 }
103
104 val = (min_uV - info->min_uV + info->step_uV - 1) / info->step_uV;
105 val <<= info->vol_shift;
106 mask = ((1 << info->vol_nbits) - 1) << info->vol_shift;
107
108 return da903x_update(da9034_dev, info->vol_reg, val, mask);
109}
110
111static int da903x_get_voltage(struct regulator_dev *rdev)
112{
113 struct da903x_regulator_info *info = rdev_get_drvdata(rdev);
114 struct device *da9034_dev = rdev_get_dev(rdev)->parent;
115 uint8_t val, mask;
116 int ret;
117
118 ret = da903x_read(da9034_dev, info->vol_reg, &val);
119 if (ret)
120 return ret;
121
122 mask = ((1 << info->vol_nbits) - 1) << info->vol_shift;
123 val = (val & mask) >> info->vol_shift;
124
125 return info->min_uV + info->step_uV * val;
126}
127
128static int da903x_enable(struct regulator_dev *rdev)
129{
130 struct da903x_regulator_info *info = rdev_get_drvdata(rdev);
131 struct device *da9034_dev = rdev_get_dev(rdev)->parent;
132
133 return da903x_set_bits(da9034_dev, info->enable_reg,
134 1 << info->enable_bit);
135}
136
137static int da903x_disable(struct regulator_dev *rdev)
138{
139 struct da903x_regulator_info *info = rdev_get_drvdata(rdev);
140 struct device *da9034_dev = rdev_get_dev(rdev)->parent;
141
142 return da903x_clr_bits(da9034_dev, info->enable_reg,
143 1 << info->enable_bit);
144}
145
146static int da903x_is_enabled(struct regulator_dev *rdev)
147{
148 struct da903x_regulator_info *info = rdev_get_drvdata(rdev);
149 struct device *da9034_dev = rdev_get_dev(rdev)->parent;
150 uint8_t reg_val;
151 int ret;
152
153 ret = da903x_read(da9034_dev, info->enable_reg, &reg_val);
154 if (ret)
155 return ret;
156
157 return reg_val & (1 << info->enable_bit);
158}
159
160/* DA9030 specific operations */
161static int da9030_set_ldo1_15_voltage(struct regulator_dev *rdev,
162 int min_uV, int max_uV)
163{
164 struct da903x_regulator_info *info = rdev_get_drvdata(rdev);
165 struct device *da903x_dev = rdev_get_dev(rdev)->parent;
166 uint8_t val, mask;
167 int ret;
168
169 if (check_range(info, min_uV, max_uV)) {
170 pr_err("invalid voltage range (%d, %d) uV", min_uV, max_uV);
171 return -EINVAL;
172 }
173
174 val = (min_uV - info->min_uV + info->step_uV - 1) / info->step_uV;
175 val <<= info->vol_shift;
176 mask = ((1 << info->vol_nbits) - 1) << info->vol_shift;
177 val |= DA9030_LDO_UNLOCK; /* have to set UNLOCK bits */
178 mask |= DA9030_LDO_UNLOCK_MASK;
179
180 /* write twice */
181 ret = da903x_update(da903x_dev, info->vol_reg, val, mask);
182 if (ret)
183 return ret;
184
185 return da903x_update(da903x_dev, info->vol_reg, val, mask);
186}
187
188static int da9030_set_ldo14_voltage(struct regulator_dev *rdev,
189 int min_uV, int max_uV)
190{
191 struct da903x_regulator_info *info = rdev_get_drvdata(rdev);
192 struct device *da903x_dev = rdev_get_dev(rdev)->parent;
193 uint8_t val, mask;
194 int thresh;
195
196 if (check_range(info, min_uV, max_uV)) {
197 pr_err("invalid voltage range (%d, %d) uV", min_uV, max_uV);
198 return -EINVAL;
199 }
200
201 thresh = (info->max_uV + info->min_uV) / 2;
202 if (min_uV < thresh) {
203 val = (thresh - min_uV + info->step_uV - 1) / info->step_uV;
204 val |= 0x4;
205 } else {
206 val = (min_uV - thresh + info->step_uV - 1) / info->step_uV;
207 }
208
209 val <<= info->vol_shift;
210 mask = ((1 << info->vol_nbits) - 1) << info->vol_shift;
211
212 return da903x_update(da903x_dev, info->vol_reg, val, mask);
213}
214
215static int da9030_get_ldo14_voltage(struct regulator_dev *rdev)
216{
217 struct da903x_regulator_info *info = rdev_get_drvdata(rdev);
218 struct device *da903x_dev = rdev_get_dev(rdev)->parent;
219 uint8_t val, mask;
220 int ret;
221
222 ret = da903x_read(da903x_dev, info->vol_reg, &val);
223 if (ret)
224 return ret;
225
226 mask = ((1 << info->vol_nbits) - 1) << info->vol_shift;
227 val = (val & mask) >> info->vol_shift;
228
229 if (val & 0x4)
230 return info->min_uV + info->step_uV * (3 - (val & ~0x4));
231 else
232 return (info->max_uV + info->min_uV) / 2 +
233 info->step_uV * (val & ~0x4);
234}
235
236/* DA9034 specific operations */
237static int da9034_set_dvc_voltage(struct regulator_dev *rdev,
238 int min_uV, int max_uV)
239{
240 struct da903x_regulator_info *info = rdev_get_drvdata(rdev);
241 struct device *da9034_dev = rdev_get_dev(rdev)->parent;
242 uint8_t val, mask;
243 int ret;
244
245 if (check_range(info, min_uV, max_uV)) {
246 pr_err("invalid voltage range (%d, %d) uV", min_uV, max_uV);
247 return -EINVAL;
248 }
249
250 val = (min_uV - info->min_uV + info->step_uV - 1) / info->step_uV;
251 val <<= info->vol_shift;
252 mask = ((1 << info->vol_nbits) - 1) << info->vol_shift;
253
254 ret = da903x_update(da9034_dev, info->vol_reg, val, mask);
255 if (ret)
256 return ret;
257
258 ret = da903x_set_bits(da9034_dev, info->update_reg,
259 1 << info->update_bit);
260 return ret;
261}
262
263static int da9034_set_ldo12_voltage(struct regulator_dev *rdev,
264 int min_uV, int max_uV)
265{
266 struct da903x_regulator_info *info = rdev_get_drvdata(rdev);
267 struct device *da9034_dev = rdev_get_dev(rdev)->parent;
268 uint8_t val, mask;
269
270 if (check_range(info, min_uV, max_uV)) {
271 pr_err("invalid voltage range (%d, %d) uV", min_uV, max_uV);
272 return -EINVAL;
273 }
274
275 val = (min_uV - info->min_uV + info->step_uV - 1) / info->step_uV;
276 val = (val > 7 || val < 20) ? 8 : val - 12;
277 val <<= info->vol_shift;
278 mask = ((1 << info->vol_nbits) - 1) << info->vol_shift;
279
280 return da903x_update(da9034_dev, info->vol_reg, val, mask);
281}
282
283static int da9034_get_ldo12_voltage(struct regulator_dev *rdev)
284{
285 struct da903x_regulator_info *info = rdev_get_drvdata(rdev);
286 struct device *da9034_dev = rdev_get_dev(rdev)->parent;
287 uint8_t val, mask;
288 int ret;
289
290 ret = da903x_read(da9034_dev, info->vol_reg, &val);
291 if (ret)
292 return ret;
293
294 mask = ((1 << info->vol_nbits) - 1) << info->vol_shift;
295 val = (val & mask) >> info->vol_shift;
296
297 if (val >= 8)
298 return 2700000 + info->step_uV * (val - 8);
299
300 return info->min_uV + info->step_uV * val;
301}
302
303static struct regulator_ops da903x_regulator_ldo_ops = {
304 .set_voltage = da903x_set_ldo_voltage,
305 .get_voltage = da903x_get_voltage,
306 .enable = da903x_enable,
307 .disable = da903x_disable,
308 .is_enabled = da903x_is_enabled,
309};
310
311/* NOTE: this is dedicated for the insane DA9030 LDO14 */
312static struct regulator_ops da9030_regulator_ldo14_ops = {
313 .set_voltage = da9030_set_ldo14_voltage,
314 .get_voltage = da9030_get_ldo14_voltage,
315 .enable = da903x_enable,
316 .disable = da903x_disable,
317 .is_enabled = da903x_is_enabled,
318};
319
320/* NOTE: this is dedicated for the DA9030 LDO1 and LDO15 that have locks */
321static struct regulator_ops da9030_regulator_ldo1_15_ops = {
322 .set_voltage = da9030_set_ldo1_15_voltage,
323 .get_voltage = da903x_get_voltage,
324 .enable = da903x_enable,
325 .disable = da903x_disable,
326 .is_enabled = da903x_is_enabled,
327};
328
329static struct regulator_ops da9034_regulator_dvc_ops = {
330 .set_voltage = da9034_set_dvc_voltage,
331 .get_voltage = da903x_get_voltage,
332 .enable = da903x_enable,
333 .disable = da903x_disable,
334 .is_enabled = da903x_is_enabled,
335};
336
337/* NOTE: this is dedicated for the insane LDO12 */
338static struct regulator_ops da9034_regulator_ldo12_ops = {
339 .set_voltage = da9034_set_ldo12_voltage,
340 .get_voltage = da9034_get_ldo12_voltage,
341 .enable = da903x_enable,
342 .disable = da903x_disable,
343 .is_enabled = da903x_is_enabled,
344};
345
346#define DA903x_LDO(_pmic, _id, min, max, step, vreg, shift, nbits, ereg, ebit) \
347{ \
348 .desc = { \
349 .name = "LDO" #_id, \
350 .ops = &da903x_regulator_ldo_ops, \
351 .type = REGULATOR_VOLTAGE, \
352 .id = _pmic##_ID_LDO##_id, \
353 .owner = THIS_MODULE, \
354 }, \
355 .min_uV = (min) * 1000, \
356 .max_uV = (max) * 1000, \
357 .step_uV = (step) * 1000, \
358 .vol_reg = _pmic##_##vreg, \
359 .vol_shift = (shift), \
360 .vol_nbits = (nbits), \
361 .enable_reg = _pmic##_##ereg, \
362 .enable_bit = (ebit), \
363}
364
365#define DA9034_DVC(_id, min, max, step, vreg, nbits, ureg, ubit, ereg, ebit) \
366{ \
367 .desc = { \
368 .name = #_id, \
369 .ops = &da9034_regulator_dvc_ops, \
370 .type = REGULATOR_VOLTAGE, \
371 .id = DA9034_ID_##_id, \
372 .owner = THIS_MODULE, \
373 }, \
374 .min_uV = (min) * 1000, \
375 .max_uV = (max) * 1000, \
376 .step_uV = (step) * 1000, \
377 .vol_reg = DA9034_##vreg, \
378 .vol_shift = (0), \
379 .vol_nbits = (nbits), \
380 .update_reg = DA9034_##ureg, \
381 .update_bit = (ubit), \
382 .enable_reg = DA9034_##ereg, \
383 .enable_bit = (ebit), \
384}
385
386#define DA9034_LDO(_id, min, max, step, vreg, shift, nbits, ereg, ebit) \
387 DA903x_LDO(DA9034, _id, min, max, step, vreg, shift, nbits, ereg, ebit)
388
389#define DA9030_LDO(_id, min, max, step, vreg, shift, nbits, ereg, ebit) \
390 DA903x_LDO(DA9030, _id, min, max, step, vreg, shift, nbits, ereg, ebit)
391
392static struct da903x_regulator_info da903x_regulator_info[] = {
393 /* DA9030 */
394 DA9030_LDO( 1, 1200, 3200, 100, LDO1, 0, 5, RCTL12, 1),
395 DA9030_LDO( 2, 1800, 3200, 100, LDO23, 0, 4, RCTL12, 2),
396 DA9030_LDO( 3, 1800, 3200, 100, LDO23, 4, 4, RCTL12, 3),
397 DA9030_LDO( 4, 1800, 3200, 100, LDO45, 0, 4, RCTL12, 4),
398 DA9030_LDO( 5, 1800, 3200, 100, LDO45, 4, 4, RCTL12, 5),
399 DA9030_LDO( 6, 1800, 3200, 100, LDO6, 0, 4, RCTL12, 6),
400 DA9030_LDO( 7, 1800, 3200, 100, LDO78, 0, 4, RCTL12, 7),
401 DA9030_LDO( 8, 1800, 3200, 100, LDO78, 4, 4, RCTL22, 0),
402 DA9030_LDO( 9, 1800, 3200, 100, LDO912, 0, 4, RCTL22, 1),
403 DA9030_LDO(10, 1800, 3200, 100, LDO1011, 0, 4, RCTL22, 2),
404 DA9030_LDO(11, 1800, 3200, 100, LDO1011, 4, 4, RCTL22, 3),
405 DA9030_LDO(12, 1800, 3200, 100, LDO912, 4, 4, RCTL22, 4),
406 DA9030_LDO(14, 2760, 2940, 30, LDO1416, 0, 3, RCTL11, 4),
407 DA9030_LDO(15, 1100, 2650, 50, LDO15, 0, 5, RCTL11, 5),
408 DA9030_LDO(16, 1100, 2650, 50, LDO1416, 3, 5, RCTL11, 6),
409 DA9030_LDO(17, 1800, 3200, 100, LDO17, 0, 4, RCTL11, 7),
410 DA9030_LDO(18, 1800, 3200, 100, LDO1819, 0, 4, RCTL21, 2),
411 DA9030_LDO(19, 1800, 3200, 100, LDO1819, 4, 4, RCTL21, 1),
412 DA9030_LDO(13, 2100, 2100, 0, INVAL, 0, 0, RCTL11, 3), /* fixed @2.1V */
413
414 /* DA9034 */
415 DA9034_DVC(BUCK1, 725, 1500, 25, ADTV1, 5, VCC1, 0, OVER1, 0),
416 DA9034_DVC(BUCK2, 725, 1500, 25, CDTV1, 5, VCC1, 2, OVER1, 1),
417 DA9034_DVC(LDO2, 725, 1500, 25, SDTV1, 5, VCC1, 4, OVER1, 2),
418 DA9034_DVC(LDO1, 1700, 2075, 25, MDTV1, 4, VCC1, 6, OVER3, 4),
419
420 DA9034_LDO( 3, 1800, 3300, 100, LDO643, 0, 4, OVER3, 5),
421 DA9034_LDO( 4, 1800, 2900,1100, LDO643, 4, 1, OVER3, 6),
422 DA9034_LDO( 6, 2500, 2850, 50, LDO643, 5, 3, OVER2, 0),
423 DA9034_LDO( 7, 2700, 3050, 50, LDO987, 0, 3, OVER2, 1),
424 DA9034_LDO( 8, 2700, 2850, 50, LDO987, 3, 2, OVER2, 2),
425 DA9034_LDO( 9, 2700, 3050, 50, LDO987, 5, 3, OVER2, 3),
426 DA9034_LDO(10, 2700, 3050, 50, LDO1110, 0, 3, OVER2, 4),
427 DA9034_LDO(11, 1800, 3300, 100, LDO1110, 4, 4, OVER2, 5),
428 DA9034_LDO(12, 1700, 3050, 50, LDO1312, 0, 4, OVER3, 6),
429 DA9034_LDO(13, 1800, 3300, 100, LDO1312, 4, 4, OVER2, 7),
430 DA9034_LDO(14, 1800, 3300, 100, LDO1514, 0, 4, OVER3, 0),
431 DA9034_LDO(15, 1800, 3300, 100, LDO1514, 4, 4, OVER3, 1),
432 DA9034_LDO(5, 3100, 3100, 0, INVAL, 0, 0, OVER3, 7), /* fixed @3.1V */
433};
434
435static inline struct da903x_regulator_info *find_regulator_info(int id)
436{
437 struct da903x_regulator_info *ri;
438 int i;
439
440 for (i = 0; i < ARRAY_SIZE(da903x_regulator_info); i++) {
441 ri = &da903x_regulator_info[i];
442 if (ri->desc.id == id)
443 return ri;
444 }
445 return NULL;
446}
447
448static int __devinit da903x_regulator_probe(struct platform_device *pdev)
449{
450 struct da903x_regulator_info *ri = NULL;
451 struct regulator_dev *rdev;
452
453 ri = find_regulator_info(pdev->id);
454 if (ri == NULL) {
455 dev_err(&pdev->dev, "invalid regulator ID specified\n");
456 return -EINVAL;
457 }
458
459 /* Workaround for the weird LDO12 voltage setting */
460 if (ri->desc.id == DA9034_ID_LDO12)
461 ri->desc.ops = &da9034_regulator_ldo12_ops;
462
463 if (ri->desc.id == DA9030_ID_LDO14)
464 ri->desc.ops = &da9030_regulator_ldo14_ops;
465
466 if (ri->desc.id == DA9030_ID_LDO1 || ri->desc.id == DA9030_ID_LDO15)
467 ri->desc.ops = &da9030_regulator_ldo1_15_ops;
468
469 rdev = regulator_register(&ri->desc, pdev->dev.parent, ri);
470 if (IS_ERR(rdev)) {
471 dev_err(&pdev->dev, "failed to register regulator %s\n",
472 ri->desc.name);
473 return PTR_ERR(rdev);
474 }
475
476 platform_set_drvdata(pdev, rdev);
477 return 0;
478}
479
480static int __devexit da903x_regulator_remove(struct platform_device *pdev)
481{
482 struct regulator_dev *rdev = platform_get_drvdata(pdev);
483
484 regulator_unregister(rdev);
485 return 0;
486}
487
488static struct platform_driver da903x_regulator_driver = {
489 .driver = {
490 .name = "da903x-regulator",
491 .owner = THIS_MODULE,
492 },
493 .probe = da903x_regulator_probe,
494 .remove = da903x_regulator_remove,
495};
496
497static int __init da903x_regulator_init(void)
498{
499 return platform_driver_register(&da903x_regulator_driver);
500}
501module_init(da903x_regulator_init);
502
503static void __exit da903x_regulator_exit(void)
504{
505 platform_driver_unregister(&da903x_regulator_driver);
506}
507module_exit(da903x_regulator_exit);
508
509MODULE_LICENSE("GPL");
510MODULE_AUTHOR("Eric Miao <eric.miao@marvell.com>"
511 "Mike Rapoport <mike@compulab.co.il>");
512MODULE_DESCRIPTION("Regulator Driver for Dialog Semiconductor DA903X PMIC");
513MODULE_ALIAS("platform:da903x-regulator");
diff --git a/drivers/regulator/wm8350-regulator.c b/drivers/regulator/wm8350-regulator.c
new file mode 100644
index 000000000000..1f44b17e23b1
--- /dev/null
+++ b/drivers/regulator/wm8350-regulator.c
@@ -0,0 +1,1431 @@
1/*
2 * wm8350.c -- Voltage and current regulation for the Wolfson WM8350 PMIC
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood
7 * linux@wolfsonmicro.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/bitops.h>
19#include <linux/err.h>
20#include <linux/i2c.h>
21#include <linux/mfd/wm8350/core.h>
22#include <linux/mfd/wm8350/pmic.h>
23#include <linux/platform_device.h>
24#include <linux/regulator/driver.h>
25#include <linux/regulator/machine.h>
26
27/* Microamps */
28static const int isink_cur[] = {
29 4,
30 5,
31 6,
32 7,
33 8,
34 10,
35 11,
36 14,
37 16,
38 19,
39 23,
40 27,
41 32,
42 39,
43 46,
44 54,
45 65,
46 77,
47 92,
48 109,
49 130,
50 154,
51 183,
52 218,
53 259,
54 308,
55 367,
56 436,
57 518,
58 616,
59 733,
60 872,
61 1037,
62 1233,
63 1466,
64 1744,
65 2073,
66 2466,
67 2933,
68 3487,
69 4147,
70 4932,
71 5865,
72 6975,
73 8294,
74 9864,
75 11730,
76 13949,
77 16589,
78 19728,
79 23460,
80 27899,
81 33178,
82 39455,
83 46920,
84 55798,
85 66355,
86 78910,
87 93840,
88 111596,
89 132710,
90 157820,
91 187681,
92 223191
93};
94
95static int get_isink_val(int min_uA, int max_uA, u16 *setting)
96{
97 int i;
98
99 for (i = ARRAY_SIZE(isink_cur) - 1; i >= 0; i--) {
100 if (min_uA <= isink_cur[i] && max_uA >= isink_cur[i]) {
101 *setting = i;
102 return 0;
103 }
104 }
105 return -EINVAL;
106}
107
108static inline int wm8350_ldo_val_to_mvolts(unsigned int val)
109{
110 if (val < 16)
111 return (val * 50) + 900;
112 else
113 return ((val - 16) * 100) + 1800;
114
115}
116
117static inline unsigned int wm8350_ldo_mvolts_to_val(int mV)
118{
119 if (mV < 1800)
120 return (mV - 900) / 50;
121 else
122 return ((mV - 1800) / 100) + 16;
123}
124
125static inline int wm8350_dcdc_val_to_mvolts(unsigned int val)
126{
127 return (val * 25) + 850;
128}
129
130static inline unsigned int wm8350_dcdc_mvolts_to_val(int mV)
131{
132 return (mV - 850) / 25;
133}
134
135static int wm8350_isink_set_current(struct regulator_dev *rdev, int min_uA,
136 int max_uA)
137{
138 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
139 int isink = rdev_get_id(rdev);
140 u16 val, setting;
141 int ret;
142
143 ret = get_isink_val(min_uA, max_uA, &setting);
144 if (ret != 0)
145 return ret;
146
147 switch (isink) {
148 case WM8350_ISINK_A:
149 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
150 ~WM8350_CS1_ISEL_MASK;
151 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_A,
152 val | setting);
153 break;
154 case WM8350_ISINK_B:
155 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
156 ~WM8350_CS1_ISEL_MASK;
157 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_B,
158 val | setting);
159 break;
160 default:
161 return -EINVAL;
162 }
163
164 return 0;
165}
166
167static int wm8350_isink_get_current(struct regulator_dev *rdev)
168{
169 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
170 int isink = rdev_get_id(rdev);
171 u16 val;
172
173 switch (isink) {
174 case WM8350_ISINK_A:
175 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
176 WM8350_CS1_ISEL_MASK;
177 break;
178 case WM8350_ISINK_B:
179 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
180 WM8350_CS1_ISEL_MASK;
181 break;
182 default:
183 return 0;
184 }
185
186 return (isink_cur[val] + 50) / 100;
187}
188
189/* turn on ISINK followed by DCDC */
190static int wm8350_isink_enable(struct regulator_dev *rdev)
191{
192 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
193 int isink = rdev_get_id(rdev);
194
195 switch (isink) {
196 case WM8350_ISINK_A:
197 switch (wm8350->pmic.isink_A_dcdc) {
198 case WM8350_DCDC_2:
199 case WM8350_DCDC_5:
200 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
201 WM8350_CS1_ENA);
202 wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL,
203 WM8350_CS1_DRIVE);
204 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
205 1 << (wm8350->pmic.isink_A_dcdc -
206 WM8350_DCDC_1));
207 break;
208 default:
209 return -EINVAL;
210 }
211 break;
212 case WM8350_ISINK_B:
213 switch (wm8350->pmic.isink_B_dcdc) {
214 case WM8350_DCDC_2:
215 case WM8350_DCDC_5:
216 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
217 WM8350_CS2_ENA);
218 wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL,
219 WM8350_CS2_DRIVE);
220 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
221 1 << (wm8350->pmic.isink_B_dcdc -
222 WM8350_DCDC_1));
223 break;
224 default:
225 return -EINVAL;
226 }
227 break;
228 default:
229 return -EINVAL;
230 }
231 return 0;
232}
233
234static int wm8350_isink_disable(struct regulator_dev *rdev)
235{
236 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
237 int isink = rdev_get_id(rdev);
238
239 switch (isink) {
240 case WM8350_ISINK_A:
241 switch (wm8350->pmic.isink_A_dcdc) {
242 case WM8350_DCDC_2:
243 case WM8350_DCDC_5:
244 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
245 1 << (wm8350->pmic.isink_A_dcdc -
246 WM8350_DCDC_1));
247 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
248 WM8350_CS1_ENA);
249 break;
250 default:
251 return -EINVAL;
252 }
253 break;
254 case WM8350_ISINK_B:
255 switch (wm8350->pmic.isink_B_dcdc) {
256 case WM8350_DCDC_2:
257 case WM8350_DCDC_5:
258 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
259 1 << (wm8350->pmic.isink_B_dcdc -
260 WM8350_DCDC_1));
261 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
262 WM8350_CS2_ENA);
263 break;
264 default:
265 return -EINVAL;
266 }
267 break;
268 default:
269 return -EINVAL;
270 }
271 return 0;
272}
273
274static int wm8350_isink_is_enabled(struct regulator_dev *rdev)
275{
276 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
277 int isink = rdev_get_id(rdev);
278
279 switch (isink) {
280 case WM8350_ISINK_A:
281 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
282 0x8000;
283 case WM8350_ISINK_B:
284 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
285 0x8000;
286 }
287 return -EINVAL;
288}
289
290int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
291 u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp,
292 u16 drive)
293{
294 switch (isink) {
295 case WM8350_ISINK_A:
296 wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL,
297 (mode ? WM8350_CS1_FLASH_MODE : 0) |
298 (trigger ? WM8350_CS1_TRIGSRC : 0) |
299 duration | on_ramp | off_ramp | drive);
300 break;
301 case WM8350_ISINK_B:
302 wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL,
303 (mode ? WM8350_CS2_FLASH_MODE : 0) |
304 (trigger ? WM8350_CS2_TRIGSRC : 0) |
305 duration | on_ramp | off_ramp | drive);
306 break;
307 default:
308 return -EINVAL;
309 }
310 return 0;
311}
312EXPORT_SYMBOL_GPL(wm8350_isink_set_flash);
313
314static int wm8350_dcdc_set_voltage(struct regulator_dev *rdev, int min_uV,
315 int max_uV)
316{
317 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
318 int volt_reg, dcdc = rdev_get_id(rdev), mV,
319 min_mV = min_uV / 1000, max_mV = max_uV / 1000;
320 u16 val;
321
322 if (min_mV < 850 || min_mV > 4025)
323 return -EINVAL;
324 if (max_mV < 850 || max_mV > 4025)
325 return -EINVAL;
326
327 /* step size is 25mV */
328 mV = (min_mV - 826) / 25;
329 if (wm8350_dcdc_val_to_mvolts(mV) > max_mV)
330 return -EINVAL;
331 BUG_ON(wm8350_dcdc_val_to_mvolts(mV) < min_mV);
332
333 switch (dcdc) {
334 case WM8350_DCDC_1:
335 volt_reg = WM8350_DCDC1_CONTROL;
336 break;
337 case WM8350_DCDC_3:
338 volt_reg = WM8350_DCDC3_CONTROL;
339 break;
340 case WM8350_DCDC_4:
341 volt_reg = WM8350_DCDC4_CONTROL;
342 break;
343 case WM8350_DCDC_6:
344 volt_reg = WM8350_DCDC6_CONTROL;
345 break;
346 case WM8350_DCDC_2:
347 case WM8350_DCDC_5:
348 default:
349 return -EINVAL;
350 }
351
352 /* all DCDCs have same mV bits */
353 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
354 wm8350_reg_write(wm8350, volt_reg, val | mV);
355 return 0;
356}
357
358static int wm8350_dcdc_get_voltage(struct regulator_dev *rdev)
359{
360 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
361 int volt_reg, dcdc = rdev_get_id(rdev);
362 u16 val;
363
364 switch (dcdc) {
365 case WM8350_DCDC_1:
366 volt_reg = WM8350_DCDC1_CONTROL;
367 break;
368 case WM8350_DCDC_3:
369 volt_reg = WM8350_DCDC3_CONTROL;
370 break;
371 case WM8350_DCDC_4:
372 volt_reg = WM8350_DCDC4_CONTROL;
373 break;
374 case WM8350_DCDC_6:
375 volt_reg = WM8350_DCDC6_CONTROL;
376 break;
377 case WM8350_DCDC_2:
378 case WM8350_DCDC_5:
379 default:
380 return -EINVAL;
381 }
382
383 /* all DCDCs have same mV bits */
384 val = wm8350_reg_read(wm8350, volt_reg) & WM8350_DC1_VSEL_MASK;
385 return wm8350_dcdc_val_to_mvolts(val) * 1000;
386}
387
388static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
389{
390 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
391 int volt_reg, mV = uV / 1000, dcdc = rdev_get_id(rdev);
392 u16 val;
393
394 dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, mV);
395
396 if (mV && (mV < 850 || mV > 4025)) {
397 dev_err(wm8350->dev,
398 "DCDC%d suspend voltage %d mV out of range\n",
399 dcdc, mV);
400 return -EINVAL;
401 }
402 if (mV == 0)
403 mV = 850;
404
405 switch (dcdc) {
406 case WM8350_DCDC_1:
407 volt_reg = WM8350_DCDC1_LOW_POWER;
408 break;
409 case WM8350_DCDC_3:
410 volt_reg = WM8350_DCDC3_LOW_POWER;
411 break;
412 case WM8350_DCDC_4:
413 volt_reg = WM8350_DCDC4_LOW_POWER;
414 break;
415 case WM8350_DCDC_6:
416 volt_reg = WM8350_DCDC6_LOW_POWER;
417 break;
418 case WM8350_DCDC_2:
419 case WM8350_DCDC_5:
420 default:
421 return -EINVAL;
422 }
423
424 /* all DCDCs have same mV bits */
425 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
426 wm8350_reg_write(wm8350, volt_reg,
427 val | wm8350_dcdc_mvolts_to_val(mV));
428 return 0;
429}
430
431static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
432{
433 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
434 int dcdc = rdev_get_id(rdev);
435 u16 val;
436
437 switch (dcdc) {
438 case WM8350_DCDC_1:
439 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
440 & ~WM8350_DCDC_HIB_MODE_MASK;
441 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
442 wm8350->pmic.dcdc1_hib_mode);
443 break;
444 case WM8350_DCDC_3:
445 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
446 & ~WM8350_DCDC_HIB_MODE_MASK;
447 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
448 wm8350->pmic.dcdc3_hib_mode);
449 break;
450 case WM8350_DCDC_4:
451 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
452 & ~WM8350_DCDC_HIB_MODE_MASK;
453 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
454 wm8350->pmic.dcdc4_hib_mode);
455 break;
456 case WM8350_DCDC_6:
457 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
458 & ~WM8350_DCDC_HIB_MODE_MASK;
459 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
460 wm8350->pmic.dcdc6_hib_mode);
461 break;
462 case WM8350_DCDC_2:
463 case WM8350_DCDC_5:
464 default:
465 return -EINVAL;
466 }
467
468 return 0;
469}
470
471static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev)
472{
473 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
474 int dcdc = rdev_get_id(rdev);
475 u16 val;
476
477 switch (dcdc) {
478 case WM8350_DCDC_1:
479 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
480 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
481 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
482 WM8350_DCDC_HIB_MODE_DIS);
483 break;
484 case WM8350_DCDC_3:
485 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
486 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
487 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
488 WM8350_DCDC_HIB_MODE_DIS);
489 break;
490 case WM8350_DCDC_4:
491 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
492 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
493 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
494 WM8350_DCDC_HIB_MODE_DIS);
495 break;
496 case WM8350_DCDC_6:
497 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
498 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
499 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
500 WM8350_DCDC_HIB_MODE_DIS);
501 break;
502 case WM8350_DCDC_2:
503 case WM8350_DCDC_5:
504 default:
505 return -EINVAL;
506 }
507
508 return 0;
509}
510
511static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev)
512{
513 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
514 int dcdc = rdev_get_id(rdev);
515 u16 val;
516
517 switch (dcdc) {
518 case WM8350_DCDC_2:
519 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
520 & ~WM8350_DC2_HIB_MODE_MASK;
521 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
522 WM8350_DC2_HIB_MODE_ACTIVE);
523 break;
524 case WM8350_DCDC_5:
525 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
526 & ~WM8350_DC2_HIB_MODE_MASK;
527 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
528 WM8350_DC5_HIB_MODE_ACTIVE);
529 break;
530 default:
531 return -EINVAL;
532 }
533 return 0;
534}
535
536static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
537{
538 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
539 int dcdc = rdev_get_id(rdev);
540 u16 val;
541
542 switch (dcdc) {
543 case WM8350_DCDC_2:
544 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
545 & ~WM8350_DC2_HIB_MODE_MASK;
546 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
547 WM8350_DC2_HIB_MODE_DISABLE);
548 break;
549 case WM8350_DCDC_5:
550 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
551 & ~WM8350_DC2_HIB_MODE_MASK;
552 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
553 WM8350_DC2_HIB_MODE_DISABLE);
554 break;
555 default:
556 return -EINVAL;
557 }
558 return 0;
559}
560
561static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev,
562 unsigned int mode)
563{
564 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
565 int dcdc = rdev_get_id(rdev);
566 u16 *hib_mode;
567
568 switch (dcdc) {
569 case WM8350_DCDC_1:
570 hib_mode = &wm8350->pmic.dcdc1_hib_mode;
571 break;
572 case WM8350_DCDC_3:
573 hib_mode = &wm8350->pmic.dcdc3_hib_mode;
574 break;
575 case WM8350_DCDC_4:
576 hib_mode = &wm8350->pmic.dcdc4_hib_mode;
577 break;
578 case WM8350_DCDC_6:
579 hib_mode = &wm8350->pmic.dcdc6_hib_mode;
580 break;
581 case WM8350_DCDC_2:
582 case WM8350_DCDC_5:
583 default:
584 return -EINVAL;
585 }
586
587 switch (mode) {
588 case REGULATOR_MODE_NORMAL:
589 *hib_mode = WM8350_DCDC_HIB_MODE_IMAGE;
590 break;
591 case REGULATOR_MODE_IDLE:
592 *hib_mode = WM8350_DCDC_HIB_MODE_STANDBY;
593 break;
594 case REGULATOR_MODE_STANDBY:
595 *hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM;
596 break;
597 default:
598 return -EINVAL;
599 }
600
601 return 0;
602}
603
604static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
605{
606 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
607 int volt_reg, mV = uV / 1000, ldo = rdev_get_id(rdev);
608 u16 val;
609
610 dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, mV);
611
612 if (mV < 900 || mV > 3300) {
613 dev_err(wm8350->dev, "LDO%d voltage %d mV out of range\n",
614 ldo, mV);
615 return -EINVAL;
616 }
617
618 switch (ldo) {
619 case WM8350_LDO_1:
620 volt_reg = WM8350_LDO1_LOW_POWER;
621 break;
622 case WM8350_LDO_2:
623 volt_reg = WM8350_LDO2_LOW_POWER;
624 break;
625 case WM8350_LDO_3:
626 volt_reg = WM8350_LDO3_LOW_POWER;
627 break;
628 case WM8350_LDO_4:
629 volt_reg = WM8350_LDO4_LOW_POWER;
630 break;
631 default:
632 return -EINVAL;
633 }
634
635 /* all LDOs have same mV bits */
636 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
637 wm8350_reg_write(wm8350, volt_reg,
638 val | wm8350_ldo_mvolts_to_val(mV));
639 return 0;
640}
641
642static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev)
643{
644 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
645 int volt_reg, ldo = rdev_get_id(rdev);
646 u16 val;
647
648 switch (ldo) {
649 case WM8350_LDO_1:
650 volt_reg = WM8350_LDO1_LOW_POWER;
651 break;
652 case WM8350_LDO_2:
653 volt_reg = WM8350_LDO2_LOW_POWER;
654 break;
655 case WM8350_LDO_3:
656 volt_reg = WM8350_LDO3_LOW_POWER;
657 break;
658 case WM8350_LDO_4:
659 volt_reg = WM8350_LDO4_LOW_POWER;
660 break;
661 default:
662 return -EINVAL;
663 }
664
665 /* all LDOs have same mV bits */
666 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
667 wm8350_reg_write(wm8350, volt_reg, val);
668 return 0;
669}
670
671static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev)
672{
673 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
674 int volt_reg, ldo = rdev_get_id(rdev);
675 u16 val;
676
677 switch (ldo) {
678 case WM8350_LDO_1:
679 volt_reg = WM8350_LDO1_LOW_POWER;
680 break;
681 case WM8350_LDO_2:
682 volt_reg = WM8350_LDO2_LOW_POWER;
683 break;
684 case WM8350_LDO_3:
685 volt_reg = WM8350_LDO3_LOW_POWER;
686 break;
687 case WM8350_LDO_4:
688 volt_reg = WM8350_LDO4_LOW_POWER;
689 break;
690 default:
691 return -EINVAL;
692 }
693
694 /* all LDOs have same mV bits */
695 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
696 wm8350_reg_write(wm8350, volt_reg, WM8350_LDO1_HIB_MODE_DIS);
697 return 0;
698}
699
700static int wm8350_ldo_set_voltage(struct regulator_dev *rdev, int min_uV,
701 int max_uV)
702{
703 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
704 int volt_reg, ldo = rdev_get_id(rdev), mV, min_mV = min_uV / 1000,
705 max_mV = max_uV / 1000;
706 u16 val;
707
708 if (min_mV < 900 || min_mV > 3300)
709 return -EINVAL;
710 if (max_mV < 900 || max_mV > 3300)
711 return -EINVAL;
712
713 if (min_mV < 1800) {
714 /* step size is 50mV < 1800mV */
715 mV = (min_mV - 851) / 50;
716 if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
717 return -EINVAL;
718 BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
719 } else {
720 /* step size is 100mV > 1800mV */
721 mV = ((min_mV - 1701) / 100) + 16;
722 if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
723 return -EINVAL;
724 BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
725 }
726
727 switch (ldo) {
728 case WM8350_LDO_1:
729 volt_reg = WM8350_LDO1_CONTROL;
730 break;
731 case WM8350_LDO_2:
732 volt_reg = WM8350_LDO2_CONTROL;
733 break;
734 case WM8350_LDO_3:
735 volt_reg = WM8350_LDO3_CONTROL;
736 break;
737 case WM8350_LDO_4:
738 volt_reg = WM8350_LDO4_CONTROL;
739 break;
740 default:
741 return -EINVAL;
742 }
743
744 /* all LDOs have same mV bits */
745 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
746 wm8350_reg_write(wm8350, volt_reg, val | mV);
747 return 0;
748}
749
750static int wm8350_ldo_get_voltage(struct regulator_dev *rdev)
751{
752 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
753 int volt_reg, ldo = rdev_get_id(rdev);
754 u16 val;
755
756 switch (ldo) {
757 case WM8350_LDO_1:
758 volt_reg = WM8350_LDO1_CONTROL;
759 break;
760 case WM8350_LDO_2:
761 volt_reg = WM8350_LDO2_CONTROL;
762 break;
763 case WM8350_LDO_3:
764 volt_reg = WM8350_LDO3_CONTROL;
765 break;
766 case WM8350_LDO_4:
767 volt_reg = WM8350_LDO4_CONTROL;
768 break;
769 default:
770 return -EINVAL;
771 }
772
773 /* all LDOs have same mV bits */
774 val = wm8350_reg_read(wm8350, volt_reg) & WM8350_LDO1_VSEL_MASK;
775 return wm8350_ldo_val_to_mvolts(val) * 1000;
776}
777
778int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
779 u16 stop, u16 fault)
780{
781 int slot_reg;
782 u16 val;
783
784 dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
785 __func__, dcdc, start, stop);
786
787 /* slot valid ? */
788 if (start > 15 || stop > 15)
789 return -EINVAL;
790
791 switch (dcdc) {
792 case WM8350_DCDC_1:
793 slot_reg = WM8350_DCDC1_TIMEOUTS;
794 break;
795 case WM8350_DCDC_2:
796 slot_reg = WM8350_DCDC2_TIMEOUTS;
797 break;
798 case WM8350_DCDC_3:
799 slot_reg = WM8350_DCDC3_TIMEOUTS;
800 break;
801 case WM8350_DCDC_4:
802 slot_reg = WM8350_DCDC4_TIMEOUTS;
803 break;
804 case WM8350_DCDC_5:
805 slot_reg = WM8350_DCDC5_TIMEOUTS;
806 break;
807 case WM8350_DCDC_6:
808 slot_reg = WM8350_DCDC6_TIMEOUTS;
809 break;
810 default:
811 return -EINVAL;
812 }
813
814 val = wm8350_reg_read(wm8350, slot_reg) &
815 ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
816 WM8350_DC1_ERRACT_MASK);
817 wm8350_reg_write(wm8350, slot_reg,
818 val | (start << WM8350_DC1_ENSLOT_SHIFT) |
819 (stop << WM8350_DC1_SDSLOT_SHIFT) |
820 (fault << WM8350_DC1_ERRACT_SHIFT));
821
822 return 0;
823}
824EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot);
825
826int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop)
827{
828 int slot_reg;
829 u16 val;
830
831 dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
832 __func__, ldo, start, stop);
833
834 /* slot valid ? */
835 if (start > 15 || stop > 15)
836 return -EINVAL;
837
838 switch (ldo) {
839 case WM8350_LDO_1:
840 slot_reg = WM8350_LDO1_TIMEOUTS;
841 break;
842 case WM8350_LDO_2:
843 slot_reg = WM8350_LDO2_TIMEOUTS;
844 break;
845 case WM8350_LDO_3:
846 slot_reg = WM8350_LDO3_TIMEOUTS;
847 break;
848 case WM8350_LDO_4:
849 slot_reg = WM8350_LDO4_TIMEOUTS;
850 break;
851 default:
852 return -EINVAL;
853 }
854
855 val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK;
856 wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6)));
857 return 0;
858}
859EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot);
860
861int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
862 u16 ilim, u16 ramp, u16 feedback)
863{
864 u16 val;
865
866 dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc,
867 mode ? "normal" : "boost", ilim ? "low" : "normal");
868
869 switch (dcdc) {
870 case WM8350_DCDC_2:
871 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
872 & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK |
873 WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK);
874 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
875 (mode << WM8350_DC2_MODE_SHIFT) |
876 (ilim << WM8350_DC2_ILIM_SHIFT) |
877 (ramp << WM8350_DC2_RMP_SHIFT) |
878 (feedback << WM8350_DC2_FBSRC_SHIFT));
879 break;
880 case WM8350_DCDC_5:
881 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
882 & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK |
883 WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK);
884 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
885 (mode << WM8350_DC5_MODE_SHIFT) |
886 (ilim << WM8350_DC5_ILIM_SHIFT) |
887 (ramp << WM8350_DC5_RMP_SHIFT) |
888 (feedback << WM8350_DC5_FBSRC_SHIFT));
889 break;
890 default:
891 return -EINVAL;
892 }
893
894 return 0;
895}
896EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode);
897
898static int wm8350_dcdc_enable(struct regulator_dev *rdev)
899{
900 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
901 int dcdc = rdev_get_id(rdev);
902 u16 shift;
903
904 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
905 return -EINVAL;
906
907 shift = dcdc - WM8350_DCDC_1;
908 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
909 return 0;
910}
911
912static int wm8350_dcdc_disable(struct regulator_dev *rdev)
913{
914 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
915 int dcdc = rdev_get_id(rdev);
916 u16 shift;
917
918 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
919 return -EINVAL;
920
921 shift = dcdc - WM8350_DCDC_1;
922 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
923
924 return 0;
925}
926
927static int wm8350_ldo_enable(struct regulator_dev *rdev)
928{
929 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
930 int ldo = rdev_get_id(rdev);
931 u16 shift;
932
933 if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
934 return -EINVAL;
935
936 shift = (ldo - WM8350_LDO_1) + 8;
937 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
938 return 0;
939}
940
941static int wm8350_ldo_disable(struct regulator_dev *rdev)
942{
943 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
944 int ldo = rdev_get_id(rdev);
945 u16 shift;
946
947 if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
948 return -EINVAL;
949
950 shift = (ldo - WM8350_LDO_1) + 8;
951 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
952 return 0;
953}
954
955static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable)
956{
957 int reg = 0, ret;
958
959 switch (dcdc) {
960 case WM8350_DCDC_1:
961 reg = WM8350_DCDC1_FORCE_PWM;
962 break;
963 case WM8350_DCDC_3:
964 reg = WM8350_DCDC3_FORCE_PWM;
965 break;
966 case WM8350_DCDC_4:
967 reg = WM8350_DCDC4_FORCE_PWM;
968 break;
969 case WM8350_DCDC_6:
970 reg = WM8350_DCDC6_FORCE_PWM;
971 break;
972 default:
973 return -EINVAL;
974 }
975
976 if (enable)
977 ret = wm8350_set_bits(wm8350, reg,
978 WM8350_DCDC1_FORCE_PWM_ENA);
979 else
980 ret = wm8350_clear_bits(wm8350, reg,
981 WM8350_DCDC1_FORCE_PWM_ENA);
982 return ret;
983}
984
985static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
986{
987 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
988 int dcdc = rdev_get_id(rdev);
989 u16 val;
990
991 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
992 return -EINVAL;
993
994 if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
995 return -EINVAL;
996
997 val = 1 << (dcdc - WM8350_DCDC_1);
998
999 switch (mode) {
1000 case REGULATOR_MODE_FAST:
1001 /* force continuous mode */
1002 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1003 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1004 force_continuous_enable(wm8350, dcdc, 1);
1005 break;
1006 case REGULATOR_MODE_NORMAL:
1007 /* active / pulse skipping */
1008 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1009 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1010 force_continuous_enable(wm8350, dcdc, 0);
1011 break;
1012 case REGULATOR_MODE_IDLE:
1013 /* standby mode */
1014 force_continuous_enable(wm8350, dcdc, 0);
1015 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1016 wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1017 break;
1018 case REGULATOR_MODE_STANDBY:
1019 /* LDO mode */
1020 force_continuous_enable(wm8350, dcdc, 0);
1021 wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1022 break;
1023 }
1024
1025 return 0;
1026}
1027
1028static unsigned int wm8350_dcdc_get_mode(struct regulator_dev *rdev)
1029{
1030 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1031 int dcdc = rdev_get_id(rdev);
1032 u16 mask, sleep, active, force;
1033 int mode = REGULATOR_MODE_NORMAL;
1034
1035 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
1036 return -EINVAL;
1037
1038 if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
1039 return -EINVAL;
1040
1041 mask = 1 << (dcdc - WM8350_DCDC_1);
1042 active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask;
1043 sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask;
1044 force = wm8350_reg_read(wm8350, WM8350_DCDC1_FORCE_PWM)
1045 & WM8350_DCDC1_FORCE_PWM_ENA;
1046 dev_dbg(wm8350->dev, "mask %x active %x sleep %x force %x",
1047 mask, active, sleep, force);
1048
1049 if (active && !sleep) {
1050 if (force)
1051 mode = REGULATOR_MODE_FAST;
1052 else
1053 mode = REGULATOR_MODE_NORMAL;
1054 } else if (!active && !sleep)
1055 mode = REGULATOR_MODE_IDLE;
1056 else if (!sleep)
1057 mode = REGULATOR_MODE_STANDBY;
1058
1059 return mode;
1060}
1061
1062static unsigned int wm8350_ldo_get_mode(struct regulator_dev *rdev)
1063{
1064 return REGULATOR_MODE_NORMAL;
1065}
1066
1067struct wm8350_dcdc_efficiency {
1068 int uA_load_min;
1069 int uA_load_max;
1070 unsigned int mode;
1071};
1072
1073static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = {
1074 {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */
1075 {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */
1076 {100000, 1000000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
1077 {-1, -1, REGULATOR_MODE_NORMAL},
1078};
1079
1080static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = {
1081 {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */
1082 {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */
1083 {100000, 800000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
1084 {-1, -1, REGULATOR_MODE_NORMAL},
1085};
1086
1087static unsigned int get_mode(int uA, const struct wm8350_dcdc_efficiency *eff)
1088{
1089 int i = 0;
1090
1091 while (eff[i].uA_load_min != -1) {
1092 if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max)
1093 return eff[i].mode;
1094 }
1095 return REGULATOR_MODE_NORMAL;
1096}
1097
1098/* Query the regulator for it's most efficient mode @ uV,uA
1099 * WM8350 regulator efficiency is pretty similar over
1100 * different input and output uV.
1101 */
1102static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator_dev *rdev,
1103 int input_uV, int output_uV,
1104 int output_uA)
1105{
1106 int dcdc = rdev_get_id(rdev), mode;
1107
1108 switch (dcdc) {
1109 case WM8350_DCDC_1:
1110 case WM8350_DCDC_6:
1111 mode = get_mode(output_uA, dcdc1_6_efficiency);
1112 break;
1113 case WM8350_DCDC_3:
1114 case WM8350_DCDC_4:
1115 mode = get_mode(output_uA, dcdc3_4_efficiency);
1116 break;
1117 default:
1118 mode = REGULATOR_MODE_NORMAL;
1119 break;
1120 }
1121 return mode;
1122}
1123
1124static int wm8350_dcdc_is_enabled(struct regulator_dev *rdev)
1125{
1126 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1127 int dcdc = rdev_get_id(rdev), shift;
1128
1129 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
1130 return -EINVAL;
1131
1132 shift = dcdc - WM8350_DCDC_1;
1133 return wm8350_reg_read(wm8350, WM8350_DCDC_LDO_REQUESTED)
1134 & (1 << shift);
1135}
1136
1137static int wm8350_ldo_is_enabled(struct regulator_dev *rdev)
1138{
1139 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1140 int ldo = rdev_get_id(rdev), shift;
1141
1142 if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
1143 return -EINVAL;
1144
1145 shift = (ldo - WM8350_LDO_1) + 8;
1146 return wm8350_reg_read(wm8350, WM8350_DCDC_LDO_REQUESTED)
1147 & (1 << shift);
1148}
1149
1150static struct regulator_ops wm8350_dcdc_ops = {
1151 .set_voltage = wm8350_dcdc_set_voltage,
1152 .get_voltage = wm8350_dcdc_get_voltage,
1153 .enable = wm8350_dcdc_enable,
1154 .disable = wm8350_dcdc_disable,
1155 .get_mode = wm8350_dcdc_get_mode,
1156 .set_mode = wm8350_dcdc_set_mode,
1157 .get_optimum_mode = wm8350_dcdc_get_optimum_mode,
1158 .is_enabled = wm8350_dcdc_is_enabled,
1159 .set_suspend_voltage = wm8350_dcdc_set_suspend_voltage,
1160 .set_suspend_enable = wm8350_dcdc_set_suspend_enable,
1161 .set_suspend_disable = wm8350_dcdc_set_suspend_disable,
1162 .set_suspend_mode = wm8350_dcdc_set_suspend_mode,
1163};
1164
1165static struct regulator_ops wm8350_dcdc2_5_ops = {
1166 .enable = wm8350_dcdc_enable,
1167 .disable = wm8350_dcdc_disable,
1168 .is_enabled = wm8350_dcdc_is_enabled,
1169 .set_suspend_enable = wm8350_dcdc25_set_suspend_enable,
1170 .set_suspend_disable = wm8350_dcdc25_set_suspend_disable,
1171};
1172
1173static struct regulator_ops wm8350_ldo_ops = {
1174 .set_voltage = wm8350_ldo_set_voltage,
1175 .get_voltage = wm8350_ldo_get_voltage,
1176 .enable = wm8350_ldo_enable,
1177 .disable = wm8350_ldo_disable,
1178 .is_enabled = wm8350_ldo_is_enabled,
1179 .get_mode = wm8350_ldo_get_mode,
1180 .set_suspend_voltage = wm8350_ldo_set_suspend_voltage,
1181 .set_suspend_enable = wm8350_ldo_set_suspend_enable,
1182 .set_suspend_disable = wm8350_ldo_set_suspend_disable,
1183};
1184
1185static struct regulator_ops wm8350_isink_ops = {
1186 .set_current_limit = wm8350_isink_set_current,
1187 .get_current_limit = wm8350_isink_get_current,
1188 .enable = wm8350_isink_enable,
1189 .disable = wm8350_isink_disable,
1190 .is_enabled = wm8350_isink_is_enabled,
1191};
1192
1193static struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = {
1194 {
1195 .name = "DCDC1",
1196 .id = WM8350_DCDC_1,
1197 .ops = &wm8350_dcdc_ops,
1198 .irq = WM8350_IRQ_UV_DC1,
1199 .type = REGULATOR_VOLTAGE,
1200 .owner = THIS_MODULE,
1201 },
1202 {
1203 .name = "DCDC2",
1204 .id = WM8350_DCDC_2,
1205 .ops = &wm8350_dcdc2_5_ops,
1206 .irq = WM8350_IRQ_UV_DC2,
1207 .type = REGULATOR_VOLTAGE,
1208 .owner = THIS_MODULE,
1209 },
1210 {
1211 .name = "DCDC3",
1212 .id = WM8350_DCDC_3,
1213 .ops = &wm8350_dcdc_ops,
1214 .irq = WM8350_IRQ_UV_DC3,
1215 .type = REGULATOR_VOLTAGE,
1216 .owner = THIS_MODULE,
1217 },
1218 {
1219 .name = "DCDC4",
1220 .id = WM8350_DCDC_4,
1221 .ops = &wm8350_dcdc_ops,
1222 .irq = WM8350_IRQ_UV_DC4,
1223 .type = REGULATOR_VOLTAGE,
1224 .owner = THIS_MODULE,
1225 },
1226 {
1227 .name = "DCDC5",
1228 .id = WM8350_DCDC_5,
1229 .ops = &wm8350_dcdc2_5_ops,
1230 .irq = WM8350_IRQ_UV_DC5,
1231 .type = REGULATOR_VOLTAGE,
1232 .owner = THIS_MODULE,
1233 },
1234 {
1235 .name = "DCDC6",
1236 .id = WM8350_DCDC_6,
1237 .ops = &wm8350_dcdc_ops,
1238 .irq = WM8350_IRQ_UV_DC6,
1239 .type = REGULATOR_VOLTAGE,
1240 .owner = THIS_MODULE,
1241 },
1242 {
1243 .name = "LDO1",
1244 .id = WM8350_LDO_1,
1245 .ops = &wm8350_ldo_ops,
1246 .irq = WM8350_IRQ_UV_LDO1,
1247 .type = REGULATOR_VOLTAGE,
1248 .owner = THIS_MODULE,
1249 },
1250 {
1251 .name = "LDO2",
1252 .id = WM8350_LDO_2,
1253 .ops = &wm8350_ldo_ops,
1254 .irq = WM8350_IRQ_UV_LDO2,
1255 .type = REGULATOR_VOLTAGE,
1256 .owner = THIS_MODULE,
1257 },
1258 {
1259 .name = "LDO3",
1260 .id = WM8350_LDO_3,
1261 .ops = &wm8350_ldo_ops,
1262 .irq = WM8350_IRQ_UV_LDO3,
1263 .type = REGULATOR_VOLTAGE,
1264 .owner = THIS_MODULE,
1265 },
1266 {
1267 .name = "LDO4",
1268 .id = WM8350_LDO_4,
1269 .ops = &wm8350_ldo_ops,
1270 .irq = WM8350_IRQ_UV_LDO4,
1271 .type = REGULATOR_VOLTAGE,
1272 .owner = THIS_MODULE,
1273 },
1274 {
1275 .name = "ISINKA",
1276 .id = WM8350_ISINK_A,
1277 .ops = &wm8350_isink_ops,
1278 .irq = WM8350_IRQ_CS1,
1279 .type = REGULATOR_CURRENT,
1280 .owner = THIS_MODULE,
1281 },
1282 {
1283 .name = "ISINKB",
1284 .id = WM8350_ISINK_B,
1285 .ops = &wm8350_isink_ops,
1286 .irq = WM8350_IRQ_CS2,
1287 .type = REGULATOR_CURRENT,
1288 .owner = THIS_MODULE,
1289 },
1290};
1291
1292static void pmic_uv_handler(struct wm8350 *wm8350, int irq, void *data)
1293{
1294 struct regulator_dev *rdev = (struct regulator_dev *)data;
1295
1296 if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2)
1297 regulator_notifier_call_chain(rdev,
1298 REGULATOR_EVENT_REGULATION_OUT,
1299 wm8350);
1300 else
1301 regulator_notifier_call_chain(rdev,
1302 REGULATOR_EVENT_UNDER_VOLTAGE,
1303 wm8350);
1304}
1305
1306static int wm8350_regulator_probe(struct platform_device *pdev)
1307{
1308 struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev);
1309 struct regulator_dev *rdev;
1310 int ret;
1311 u16 val;
1312
1313 if (pdev->id < WM8350_DCDC_1 || pdev->id > WM8350_ISINK_B)
1314 return -ENODEV;
1315
1316 /* do any regulatior specific init */
1317 switch (pdev->id) {
1318 case WM8350_DCDC_1:
1319 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
1320 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1321 break;
1322 case WM8350_DCDC_3:
1323 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
1324 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1325 break;
1326 case WM8350_DCDC_4:
1327 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
1328 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1329 break;
1330 case WM8350_DCDC_6:
1331 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
1332 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1333 break;
1334 }
1335
1336
1337 /* register regulator */
1338 rdev = regulator_register(&wm8350_reg[pdev->id], &pdev->dev,
1339 dev_get_drvdata(&pdev->dev));
1340 if (IS_ERR(rdev)) {
1341 dev_err(&pdev->dev, "failed to register %s\n",
1342 wm8350_reg[pdev->id].name);
1343 return PTR_ERR(rdev);
1344 }
1345
1346 /* register regulator IRQ */
1347 ret = wm8350_register_irq(wm8350, wm8350_reg[pdev->id].irq,
1348 pmic_uv_handler, rdev);
1349 if (ret < 0) {
1350 regulator_unregister(rdev);
1351 dev_err(&pdev->dev, "failed to register regulator %s IRQ\n",
1352 wm8350_reg[pdev->id].name);
1353 return ret;
1354 }
1355
1356 wm8350_unmask_irq(wm8350, wm8350_reg[pdev->id].irq);
1357
1358 return 0;
1359}
1360
1361static int wm8350_regulator_remove(struct platform_device *pdev)
1362{
1363 struct regulator_dev *rdev = platform_get_drvdata(pdev);
1364 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1365
1366 wm8350_mask_irq(wm8350, wm8350_reg[pdev->id].irq);
1367 wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq);
1368
1369 regulator_unregister(rdev);
1370
1371 return 0;
1372}
1373
1374int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
1375 struct regulator_init_data *initdata)
1376{
1377 struct platform_device *pdev;
1378 int ret;
1379
1380 if (wm8350->pmic.pdev[reg])
1381 return -EBUSY;
1382
1383 pdev = platform_device_alloc("wm8350-regulator", reg);
1384 if (!pdev)
1385 return -ENOMEM;
1386
1387 wm8350->pmic.pdev[reg] = pdev;
1388
1389 initdata->driver_data = wm8350;
1390
1391 pdev->dev.platform_data = initdata;
1392 pdev->dev.parent = wm8350->dev;
1393 platform_set_drvdata(pdev, wm8350);
1394
1395 ret = platform_device_add(pdev);
1396
1397 if (ret != 0) {
1398 dev_err(wm8350->dev, "Failed to register regulator %d: %d\n",
1399 reg, ret);
1400 platform_device_del(pdev);
1401 wm8350->pmic.pdev[reg] = NULL;
1402 }
1403
1404 return ret;
1405}
1406EXPORT_SYMBOL_GPL(wm8350_register_regulator);
1407
1408static struct platform_driver wm8350_regulator_driver = {
1409 .probe = wm8350_regulator_probe,
1410 .remove = wm8350_regulator_remove,
1411 .driver = {
1412 .name = "wm8350-regulator",
1413 },
1414};
1415
1416static int __init wm8350_regulator_init(void)
1417{
1418 return platform_driver_register(&wm8350_regulator_driver);
1419}
1420subsys_initcall(wm8350_regulator_init);
1421
1422static void __exit wm8350_regulator_exit(void)
1423{
1424 platform_driver_unregister(&wm8350_regulator_driver);
1425}
1426module_exit(wm8350_regulator_exit);
1427
1428/* Module information */
1429MODULE_AUTHOR("Liam Girdwood");
1430MODULE_DESCRIPTION("WM8350 voltage and current regulator driver");
1431MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/wm8400-regulator.c b/drivers/regulator/wm8400-regulator.c
new file mode 100644
index 000000000000..48b372e038a8
--- /dev/null
+++ b/drivers/regulator/wm8400-regulator.c
@@ -0,0 +1,368 @@
1/*
2 * Regulator support for WM8400
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 */
14
15#include <linux/bug.h>
16#include <linux/err.h>
17#include <linux/kernel.h>
18#include <linux/regulator/driver.h>
19#include <linux/mfd/wm8400-private.h>
20
21static int wm8400_ldo_is_enabled(struct regulator_dev *dev)
22{
23 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
24 u16 val;
25
26 val = wm8400_reg_read(wm8400, WM8400_LDO1_CONTROL + rdev_get_id(dev));
27 return (val & WM8400_LDO1_ENA) != 0;
28}
29
30static int wm8400_ldo_enable(struct regulator_dev *dev)
31{
32 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
33
34 return wm8400_set_bits(wm8400, WM8400_LDO1_CONTROL + rdev_get_id(dev),
35 WM8400_LDO1_ENA, WM8400_LDO1_ENA);
36}
37
38static int wm8400_ldo_disable(struct regulator_dev *dev)
39{
40 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
41
42 return wm8400_set_bits(wm8400, WM8400_LDO1_CONTROL + rdev_get_id(dev),
43 WM8400_LDO1_ENA, 0);
44}
45
46static int wm8400_ldo_get_voltage(struct regulator_dev *dev)
47{
48 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
49 u16 val;
50
51 val = wm8400_reg_read(wm8400, WM8400_LDO1_CONTROL + rdev_get_id(dev));
52 val &= WM8400_LDO1_VSEL_MASK;
53
54 if (val < 15)
55 return 900000 + (val * 50000);
56 else
57 return 1600000 + ((val - 14) * 100000);
58}
59
60static int wm8400_ldo_set_voltage(struct regulator_dev *dev,
61 int min_uV, int max_uV)
62{
63 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
64 u16 val;
65
66 if (min_uV < 900000 || min_uV > 3300000)
67 return -EINVAL;
68
69 if (min_uV < 1700000) {
70 /* Steps of 50mV from 900mV; */
71 val = (min_uV - 850001) / 50000;
72
73 if ((val * 50000) + 900000 > max_uV)
74 return -EINVAL;
75 BUG_ON((val * 50000) + 900000 < min_uV);
76 } else {
77 /* Steps of 100mV from 1700mV */
78 val = ((min_uV - 1600001) / 100000);
79
80 if ((val * 100000) + 1700000 > max_uV)
81 return -EINVAL;
82 BUG_ON((val * 100000) + 1700000 < min_uV);
83
84 val += 0xf;
85 }
86
87 return wm8400_set_bits(wm8400, WM8400_LDO1_CONTROL + rdev_get_id(dev),
88 WM8400_LDO1_VSEL_MASK, val);
89}
90
91static struct regulator_ops wm8400_ldo_ops = {
92 .is_enabled = wm8400_ldo_is_enabled,
93 .enable = wm8400_ldo_enable,
94 .disable = wm8400_ldo_disable,
95 .get_voltage = wm8400_ldo_get_voltage,
96 .set_voltage = wm8400_ldo_set_voltage,
97};
98
99static int wm8400_dcdc_is_enabled(struct regulator_dev *dev)
100{
101 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
102 int offset = (rdev_get_id(dev) - WM8400_DCDC1) * 2;
103 u16 val;
104
105 val = wm8400_reg_read(wm8400, WM8400_DCDC1_CONTROL_1 + offset);
106 return (val & WM8400_DC1_ENA) != 0;
107}
108
109static int wm8400_dcdc_enable(struct regulator_dev *dev)
110{
111 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
112 int offset = (rdev_get_id(dev) - WM8400_DCDC1) * 2;
113
114 return wm8400_set_bits(wm8400, WM8400_DCDC1_CONTROL_1 + offset,
115 WM8400_DC1_ENA, WM8400_DC1_ENA);
116}
117
118static int wm8400_dcdc_disable(struct regulator_dev *dev)
119{
120 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
121 int offset = (rdev_get_id(dev) - WM8400_DCDC1) * 2;
122
123 return wm8400_set_bits(wm8400, WM8400_DCDC1_CONTROL_1 + offset,
124 WM8400_DC1_ENA, 0);
125}
126
127static int wm8400_dcdc_get_voltage(struct regulator_dev *dev)
128{
129 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
130 u16 val;
131 int offset = (rdev_get_id(dev) - WM8400_DCDC1) * 2;
132
133 val = wm8400_reg_read(wm8400, WM8400_DCDC1_CONTROL_1 + offset);
134 val &= WM8400_DC1_VSEL_MASK;
135
136 return 850000 + (25000 * val);
137}
138
139static int wm8400_dcdc_set_voltage(struct regulator_dev *dev,
140 int min_uV, int max_uV)
141{
142 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
143 u16 val;
144 int offset = (rdev_get_id(dev) - WM8400_DCDC1) * 2;
145
146 if (min_uV < 850000)
147 return -EINVAL;
148
149 val = (min_uV - 825001) / 25000;
150
151 if (850000 + (25000 * val) > max_uV)
152 return -EINVAL;
153 BUG_ON(850000 + (25000 * val) < min_uV);
154
155 return wm8400_set_bits(wm8400, WM8400_DCDC1_CONTROL_1 + offset,
156 WM8400_DC1_VSEL_MASK, val);
157}
158
159static unsigned int wm8400_dcdc_get_mode(struct regulator_dev *dev)
160{
161 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
162 int offset = (rdev_get_id(dev) - WM8400_DCDC1) * 2;
163 u16 data[2];
164 int ret;
165
166 ret = wm8400_block_read(wm8400, WM8400_DCDC1_CONTROL_1 + offset, 2,
167 data);
168 if (ret != 0)
169 return 0;
170
171 /* Datasheet: hibernate */
172 if (data[0] & WM8400_DC1_SLEEP)
173 return REGULATOR_MODE_STANDBY;
174
175 /* Datasheet: standby */
176 if (!(data[0] & WM8400_DC1_ACTIVE))
177 return REGULATOR_MODE_IDLE;
178
179 /* Datasheet: active with or without force PWM */
180 if (data[1] & WM8400_DC1_FRC_PWM)
181 return REGULATOR_MODE_FAST;
182 else
183 return REGULATOR_MODE_NORMAL;
184}
185
186static int wm8400_dcdc_set_mode(struct regulator_dev *dev, unsigned int mode)
187{
188 struct wm8400 *wm8400 = rdev_get_drvdata(dev);
189 int offset = (rdev_get_id(dev) - WM8400_DCDC1) * 2;
190 int ret;
191
192 switch (mode) {
193 case REGULATOR_MODE_FAST:
194 /* Datasheet: active with force PWM */
195 ret = wm8400_set_bits(wm8400, WM8400_DCDC1_CONTROL_2 + offset,
196 WM8400_DC1_FRC_PWM, WM8400_DC1_FRC_PWM);
197 if (ret != 0)
198 return ret;
199
200 return wm8400_set_bits(wm8400, WM8400_DCDC1_CONTROL_1 + offset,
201 WM8400_DC1_ACTIVE | WM8400_DC1_SLEEP,
202 WM8400_DC1_ACTIVE);
203
204 case REGULATOR_MODE_NORMAL:
205 /* Datasheet: active */
206 ret = wm8400_set_bits(wm8400, WM8400_DCDC1_CONTROL_2 + offset,
207 WM8400_DC1_FRC_PWM, 0);
208 if (ret != 0)
209 return ret;
210
211 return wm8400_set_bits(wm8400, WM8400_DCDC1_CONTROL_1 + offset,
212 WM8400_DC1_ACTIVE | WM8400_DC1_SLEEP,
213 WM8400_DC1_ACTIVE);
214
215 case REGULATOR_MODE_IDLE:
216 /* Datasheet: standby */
217 ret = wm8400_set_bits(wm8400, WM8400_DCDC1_CONTROL_1 + offset,
218 WM8400_DC1_ACTIVE, 0);
219 if (ret != 0)
220 return ret;
221 return wm8400_set_bits(wm8400, WM8400_DCDC1_CONTROL_1 + offset,
222 WM8400_DC1_SLEEP, 0);
223
224 default:
225 return -EINVAL;
226 }
227}
228
229static unsigned int wm8400_dcdc_get_optimum_mode(struct regulator_dev *dev,
230 int input_uV, int output_uV,
231 int load_uA)
232{
233 return REGULATOR_MODE_NORMAL;
234}
235
236static struct regulator_ops wm8400_dcdc_ops = {
237 .is_enabled = wm8400_dcdc_is_enabled,
238 .enable = wm8400_dcdc_enable,
239 .disable = wm8400_dcdc_disable,
240 .get_voltage = wm8400_dcdc_get_voltage,
241 .set_voltage = wm8400_dcdc_set_voltage,
242 .get_mode = wm8400_dcdc_get_mode,
243 .set_mode = wm8400_dcdc_set_mode,
244 .get_optimum_mode = wm8400_dcdc_get_optimum_mode,
245};
246
247static struct regulator_desc regulators[] = {
248 {
249 .name = "LDO1",
250 .id = WM8400_LDO1,
251 .ops = &wm8400_ldo_ops,
252 .type = REGULATOR_VOLTAGE,
253 .owner = THIS_MODULE,
254 },
255 {
256 .name = "LDO2",
257 .id = WM8400_LDO2,
258 .ops = &wm8400_ldo_ops,
259 .type = REGULATOR_VOLTAGE,
260 .owner = THIS_MODULE,
261 },
262 {
263 .name = "LDO3",
264 .id = WM8400_LDO3,
265 .ops = &wm8400_ldo_ops,
266 .type = REGULATOR_VOLTAGE,
267 .owner = THIS_MODULE,
268 },
269 {
270 .name = "LDO4",
271 .id = WM8400_LDO4,
272 .ops = &wm8400_ldo_ops,
273 .type = REGULATOR_VOLTAGE,
274 .owner = THIS_MODULE,
275 },
276 {
277 .name = "DCDC1",
278 .id = WM8400_DCDC1,
279 .ops = &wm8400_dcdc_ops,
280 .type = REGULATOR_VOLTAGE,
281 .owner = THIS_MODULE,
282 },
283 {
284 .name = "DCDC2",
285 .id = WM8400_DCDC2,
286 .ops = &wm8400_dcdc_ops,
287 .type = REGULATOR_VOLTAGE,
288 .owner = THIS_MODULE,
289 },
290};
291
292static int __init wm8400_regulator_probe(struct platform_device *pdev)
293{
294 struct regulator_dev *rdev;
295
296 rdev = regulator_register(&regulators[pdev->id], &pdev->dev,
297 pdev->dev.driver_data);
298
299 if (IS_ERR(rdev))
300 return PTR_ERR(rdev);
301
302 return 0;
303}
304
305static int __devexit wm8400_regulator_remove(struct platform_device *pdev)
306{
307 struct regulator_dev *rdev = platform_get_drvdata(pdev);
308
309 regulator_unregister(rdev);
310
311 return 0;
312}
313
314static struct platform_driver wm8400_regulator_driver = {
315 .driver = {
316 .name = "wm8400-regulator",
317 },
318 .probe = wm8400_regulator_probe,
319 .remove = __devexit_p(wm8400_regulator_remove),
320};
321
322/**
323 * wm8400_register_regulator - enable software control of a WM8400 regulator
324 *
325 * This function enables software control of a WM8400 regulator via
326 * the regulator API. It is intended to be called from the
327 * platform_init() callback of the WM8400 MFD driver.
328 *
329 * @param dev The WM8400 device to operate on.
330 * @param reg The regulator to control.
331 * @param initdata Regulator initdata for the regulator.
332 */
333int wm8400_register_regulator(struct device *dev, int reg,
334 struct regulator_init_data *initdata)
335{
336 struct wm8400 *wm8400 = dev->driver_data;
337
338 if (wm8400->regulators[reg].name)
339 return -EBUSY;
340
341 initdata->driver_data = wm8400;
342
343 wm8400->regulators[reg].name = "wm8400-regulator";
344 wm8400->regulators[reg].id = reg;
345 wm8400->regulators[reg].dev.parent = dev;
346 wm8400->regulators[reg].dev.driver_data = wm8400;
347 wm8400->regulators[reg].dev.platform_data = initdata;
348
349 return platform_device_register(&wm8400->regulators[reg]);
350}
351EXPORT_SYMBOL_GPL(wm8400_register_regulator);
352
353static int __init wm8400_regulator_init(void)
354{
355 return platform_driver_register(&wm8400_regulator_driver);
356}
357module_init(wm8400_regulator_init);
358
359static void __exit wm8400_regulator_exit(void)
360{
361 platform_driver_unregister(&wm8400_regulator_driver);
362}
363module_exit(wm8400_regulator_exit);
364
365MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
366MODULE_DESCRIPTION("WM8400 regulator driver");
367MODULE_LICENSE("GPL");
368MODULE_ALIAS("platform:wm8400-regulator");
diff --git a/include/linux/mfd/wm8350/audio.h b/include/linux/mfd/wm8350/audio.h
new file mode 100644
index 000000000000..217bb22ebb8e
--- /dev/null
+++ b/include/linux/mfd/wm8350/audio.h
@@ -0,0 +1,598 @@
1/*
2 * audio.h -- Audio Driver for Wolfson WM8350 PMIC
3 *
4 * Copyright 2007 Wolfson Microelectronics PLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifndef __LINUX_MFD_WM8350_AUDIO_H_
14#define __LINUX_MFD_WM8350_AUDIO_H_
15
16#include <linux/platform_device.h>
17
18#define WM8350_CLOCK_CONTROL_1 0x28
19#define WM8350_CLOCK_CONTROL_2 0x29
20#define WM8350_FLL_CONTROL_1 0x2A
21#define WM8350_FLL_CONTROL_2 0x2B
22#define WM8350_FLL_CONTROL_3 0x2C
23#define WM8350_FLL_CONTROL_4 0x2D
24#define WM8350_DAC_CONTROL 0x30
25#define WM8350_DAC_DIGITAL_VOLUME_L 0x32
26#define WM8350_DAC_DIGITAL_VOLUME_R 0x33
27#define WM8350_DAC_LR_RATE 0x35
28#define WM8350_DAC_CLOCK_CONTROL 0x36
29#define WM8350_DAC_MUTE 0x3A
30#define WM8350_DAC_MUTE_VOLUME 0x3B
31#define WM8350_DAC_SIDE 0x3C
32#define WM8350_ADC_CONTROL 0x40
33#define WM8350_ADC_DIGITAL_VOLUME_L 0x42
34#define WM8350_ADC_DIGITAL_VOLUME_R 0x43
35#define WM8350_ADC_DIVIDER 0x44
36#define WM8350_ADC_LR_RATE 0x46
37#define WM8350_INPUT_CONTROL 0x48
38#define WM8350_IN3_INPUT_CONTROL 0x49
39#define WM8350_MIC_BIAS_CONTROL 0x4A
40#define WM8350_OUTPUT_CONTROL 0x4C
41#define WM8350_JACK_DETECT 0x4D
42#define WM8350_ANTI_POP_CONTROL 0x4E
43#define WM8350_LEFT_INPUT_VOLUME 0x50
44#define WM8350_RIGHT_INPUT_VOLUME 0x51
45#define WM8350_LEFT_MIXER_CONTROL 0x58
46#define WM8350_RIGHT_MIXER_CONTROL 0x59
47#define WM8350_OUT3_MIXER_CONTROL 0x5C
48#define WM8350_OUT4_MIXER_CONTROL 0x5D
49#define WM8350_OUTPUT_LEFT_MIXER_VOLUME 0x60
50#define WM8350_OUTPUT_RIGHT_MIXER_VOLUME 0x61
51#define WM8350_INPUT_MIXER_VOLUME_L 0x62
52#define WM8350_INPUT_MIXER_VOLUME_R 0x63
53#define WM8350_INPUT_MIXER_VOLUME 0x64
54#define WM8350_LOUT1_VOLUME 0x68
55#define WM8350_ROUT1_VOLUME 0x69
56#define WM8350_LOUT2_VOLUME 0x6A
57#define WM8350_ROUT2_VOLUME 0x6B
58#define WM8350_BEEP_VOLUME 0x6F
59#define WM8350_AI_FORMATING 0x70
60#define WM8350_ADC_DAC_COMP 0x71
61#define WM8350_AI_ADC_CONTROL 0x72
62#define WM8350_AI_DAC_CONTROL 0x73
63#define WM8350_AIF_TEST 0x74
64#define WM8350_JACK_PIN_STATUS 0xE7
65
66/* Bit values for R08 (0x08) */
67#define WM8350_CODEC_ISEL_1_5 0 /* x1.5 */
68#define WM8350_CODEC_ISEL_1_0 1 /* x1.0 */
69#define WM8350_CODEC_ISEL_0_75 2 /* x0.75 */
70#define WM8350_CODEC_ISEL_0_5 3 /* x0.5 */
71
72#define WM8350_VMID_OFF 0
73#define WM8350_VMID_500K 1
74#define WM8350_VMID_100K 2
75#define WM8350_VMID_10K 3
76
77/*
78 * R40 (0x28) - Clock Control 1
79 */
80#define WM8350_TOCLK_RATE 0x4000
81#define WM8350_MCLK_SEL 0x0800
82#define WM8350_MCLK_DIV_MASK 0x0100
83#define WM8350_BCLK_DIV_MASK 0x00F0
84#define WM8350_OPCLK_DIV_MASK 0x0007
85
86/*
87 * R41 (0x29) - Clock Control 2
88 */
89#define WM8350_LRC_ADC_SEL 0x8000
90#define WM8350_MCLK_DIR 0x0001
91
92/*
93 * R42 (0x2A) - FLL Control 1
94 */
95#define WM8350_FLL_DITHER_WIDTH_MASK 0x3000
96#define WM8350_FLL_DITHER_HP 0x0800
97#define WM8350_FLL_OUTDIV_MASK 0x0700
98#define WM8350_FLL_RSP_RATE_MASK 0x00F0
99#define WM8350_FLL_RATE_MASK 0x0007
100
101/*
102 * R43 (0x2B) - FLL Control 2
103 */
104#define WM8350_FLL_RATIO_MASK 0xF800
105#define WM8350_FLL_N_MASK 0x03FF
106
107/*
108 * R44 (0x2C) - FLL Control 3
109 */
110#define WM8350_FLL_K_MASK 0xFFFF
111
112/*
113 * R45 (0x2D) - FLL Control 4
114 */
115#define WM8350_FLL_FRAC 0x0020
116#define WM8350_FLL_SLOW_LOCK_REF 0x0010
117#define WM8350_FLL_CLK_SRC_MASK 0x0003
118
119/*
120 * R48 (0x30) - DAC Control
121 */
122#define WM8350_DAC_MONO 0x2000
123#define WM8350_AIF_LRCLKRATE 0x1000
124#define WM8350_DEEMP_MASK 0x0030
125#define WM8350_DACL_DATINV 0x0002
126#define WM8350_DACR_DATINV 0x0001
127
128/*
129 * R50 (0x32) - DAC Digital Volume L
130 */
131#define WM8350_DAC_VU 0x0100
132#define WM8350_DACL_VOL_MASK 0x00FF
133
134/*
135 * R51 (0x33) - DAC Digital Volume R
136 */
137#define WM8350_DAC_VU 0x0100
138#define WM8350_DACR_VOL_MASK 0x00FF
139
140/*
141 * R53 (0x35) - DAC LR Rate
142 */
143#define WM8350_DACLRC_ENA 0x0800
144#define WM8350_DACLRC_RATE_MASK 0x07FF
145
146/*
147 * R54 (0x36) - DAC Clock Control
148 */
149#define WM8350_DACCLK_POL 0x0010
150#define WM8350_DAC_CLKDIV_MASK 0x0007
151
152/*
153 * R58 (0x3A) - DAC Mute
154 */
155#define WM8350_DAC_MUTE_ENA 0x4000
156
157/*
158 * R59 (0x3B) - DAC Mute Volume
159 */
160#define WM8350_DAC_MUTEMODE 0x4000
161#define WM8350_DAC_MUTERATE 0x2000
162#define WM8350_DAC_SB_FILT 0x1000
163
164/*
165 * R60 (0x3C) - DAC Side
166 */
167#define WM8350_ADC_TO_DACL_MASK 0x3000
168#define WM8350_ADC_TO_DACR_MASK 0x0C00
169
170/*
171 * R64 (0x40) - ADC Control
172 */
173#define WM8350_ADC_HPF_CUT_MASK 0x0300
174#define WM8350_ADCL_DATINV 0x0002
175#define WM8350_ADCR_DATINV 0x0001
176
177/*
178 * R66 (0x42) - ADC Digital Volume L
179 */
180#define WM8350_ADC_VU 0x0100
181#define WM8350_ADCL_VOL_MASK 0x00FF
182
183/*
184 * R67 (0x43) - ADC Digital Volume R
185 */
186#define WM8350_ADC_VU 0x0100
187#define WM8350_ADCR_VOL_MASK 0x00FF
188
189/*
190 * R68 (0x44) - ADC Divider
191 */
192#define WM8350_ADCL_DAC_SVOL_MASK 0x0F00
193#define WM8350_ADCR_DAC_SVOL_MASK 0x00F0
194#define WM8350_ADCCLK_POL 0x0008
195#define WM8350_ADC_CLKDIV_MASK 0x0007
196
197/*
198 * R70 (0x46) - ADC LR Rate
199 */
200#define WM8350_ADCLRC_ENA 0x0800
201#define WM8350_ADCLRC_RATE_MASK 0x07FF
202
203/*
204 * R72 (0x48) - Input Control
205 */
206#define WM8350_IN2R_ENA 0x0400
207#define WM8350_IN1RN_ENA 0x0200
208#define WM8350_IN1RP_ENA 0x0100
209#define WM8350_IN2L_ENA 0x0004
210#define WM8350_IN1LN_ENA 0x0002
211#define WM8350_IN1LP_ENA 0x0001
212
213/*
214 * R73 (0x49) - IN3 Input Control
215 */
216#define WM8350_IN3R_SHORT 0x4000
217#define WM8350_IN3L_SHORT 0x0040
218
219/*
220 * R74 (0x4A) - Mic Bias Control
221 */
222#define WM8350_MICBSEL 0x4000
223#define WM8350_MCDTHR_MASK 0x001C
224#define WM8350_MCDSCTHR_MASK 0x0003
225
226/*
227 * R76 (0x4C) - Output Control
228 */
229#define WM8350_OUT4_VROI 0x0800
230#define WM8350_OUT3_VROI 0x0400
231#define WM8350_OUT2_VROI 0x0200
232#define WM8350_OUT1_VROI 0x0100
233#define WM8350_OUT2_FB 0x0004
234#define WM8350_OUT1_FB 0x0001
235
236/*
237 * R77 (0x4D) - Jack Detect
238 */
239#define WM8350_JDL_ENA 0x8000
240#define WM8350_JDR_ENA 0x4000
241
242/*
243 * R78 (0x4E) - Anti Pop Control
244 */
245#define WM8350_ANTI_POP_MASK 0x0300
246#define WM8350_DIS_OP_LN4_MASK 0x00C0
247#define WM8350_DIS_OP_LN3_MASK 0x0030
248#define WM8350_DIS_OP_OUT2_MASK 0x000C
249#define WM8350_DIS_OP_OUT1_MASK 0x0003
250
251/*
252 * R80 (0x50) - Left Input Volume
253 */
254#define WM8350_INL_MUTE 0x4000
255#define WM8350_INL_ZC 0x2000
256#define WM8350_IN_VU 0x0100
257#define WM8350_INL_VOL_MASK 0x00FC
258
259/*
260 * R81 (0x51) - Right Input Volume
261 */
262#define WM8350_INR_MUTE 0x4000
263#define WM8350_INR_ZC 0x2000
264#define WM8350_IN_VU 0x0100
265#define WM8350_INR_VOL_MASK 0x00FC
266
267/*
268 * R88 (0x58) - Left Mixer Control
269 */
270#define WM8350_DACR_TO_MIXOUTL 0x1000
271#define WM8350_DACL_TO_MIXOUTL 0x0800
272#define WM8350_IN3L_TO_MIXOUTL 0x0004
273#define WM8350_INR_TO_MIXOUTL 0x0002
274#define WM8350_INL_TO_MIXOUTL 0x0001
275
276/*
277 * R89 (0x59) - Right Mixer Control
278 */
279#define WM8350_DACR_TO_MIXOUTR 0x1000
280#define WM8350_DACL_TO_MIXOUTR 0x0800
281#define WM8350_IN3R_TO_MIXOUTR 0x0008
282#define WM8350_INR_TO_MIXOUTR 0x0002
283#define WM8350_INL_TO_MIXOUTR 0x0001
284
285/*
286 * R92 (0x5C) - OUT3 Mixer Control
287 */
288#define WM8350_DACL_TO_OUT3 0x0800
289#define WM8350_MIXINL_TO_OUT3 0x0100
290#define WM8350_OUT4_TO_OUT3 0x0008
291#define WM8350_MIXOUTL_TO_OUT3 0x0001
292
293/*
294 * R93 (0x5D) - OUT4 Mixer Control
295 */
296#define WM8350_DACR_TO_OUT4 0x1000
297#define WM8350_DACL_TO_OUT4 0x0800
298#define WM8350_OUT4_ATTN 0x0400
299#define WM8350_MIXINR_TO_OUT4 0x0200
300#define WM8350_OUT3_TO_OUT4 0x0004
301#define WM8350_MIXOUTR_TO_OUT4 0x0002
302#define WM8350_MIXOUTL_TO_OUT4 0x0001
303
304/*
305 * R96 (0x60) - Output Left Mixer Volume
306 */
307#define WM8350_IN3L_MIXOUTL_VOL_MASK 0x0E00
308#define WM8350_IN3L_MIXOUTL_VOL_SHIFT 9
309#define WM8350_INR_MIXOUTL_VOL_MASK 0x00E0
310#define WM8350_INR_MIXOUTL_VOL_SHIFT 5
311#define WM8350_INL_MIXOUTL_VOL_MASK 0x000E
312#define WM8350_INL_MIXOUTL_VOL_SHIFT 1
313
314/* Bit values for R96 (0x60) */
315#define WM8350_IN3L_MIXOUTL_VOL_OFF 0
316#define WM8350_IN3L_MIXOUTL_VOL_M12DB 1
317#define WM8350_IN3L_MIXOUTL_VOL_M9DB 2
318#define WM8350_IN3L_MIXOUTL_VOL_M6DB 3
319#define WM8350_IN3L_MIXOUTL_VOL_M3DB 4
320#define WM8350_IN3L_MIXOUTL_VOL_0DB 5
321#define WM8350_IN3L_MIXOUTL_VOL_3DB 6
322#define WM8350_IN3L_MIXOUTL_VOL_6DB 7
323
324#define WM8350_INR_MIXOUTL_VOL_OFF 0
325#define WM8350_INR_MIXOUTL_VOL_M12DB 1
326#define WM8350_INR_MIXOUTL_VOL_M9DB 2
327#define WM8350_INR_MIXOUTL_VOL_M6DB 3
328#define WM8350_INR_MIXOUTL_VOL_M3DB 4
329#define WM8350_INR_MIXOUTL_VOL_0DB 5
330#define WM8350_INR_MIXOUTL_VOL_3DB 6
331#define WM8350_INR_MIXOUTL_VOL_6DB 7
332
333#define WM8350_INL_MIXOUTL_VOL_OFF 0
334#define WM8350_INL_MIXOUTL_VOL_M12DB 1
335#define WM8350_INL_MIXOUTL_VOL_M9DB 2
336#define WM8350_INL_MIXOUTL_VOL_M6DB 3
337#define WM8350_INL_MIXOUTL_VOL_M3DB 4
338#define WM8350_INL_MIXOUTL_VOL_0DB 5
339#define WM8350_INL_MIXOUTL_VOL_3DB 6
340#define WM8350_INL_MIXOUTL_VOL_6DB 7
341
342/*
343 * R97 (0x61) - Output Right Mixer Volume
344 */
345#define WM8350_IN3R_MIXOUTR_VOL_MASK 0xE000
346#define WM8350_IN3R_MIXOUTR_VOL_SHIFT 13
347#define WM8350_INR_MIXOUTR_VOL_MASK 0x00E0
348#define WM8350_INR_MIXOUTR_VOL_SHIFT 5
349#define WM8350_INL_MIXOUTR_VOL_MASK 0x000E
350#define WM8350_INL_MIXOUTR_VOL_SHIFT 1
351
352/* Bit values for R96 (0x60) */
353#define WM8350_IN3R_MIXOUTR_VOL_OFF 0
354#define WM8350_IN3R_MIXOUTR_VOL_M12DB 1
355#define WM8350_IN3R_MIXOUTR_VOL_M9DB 2
356#define WM8350_IN3R_MIXOUTR_VOL_M6DB 3
357#define WM8350_IN3R_MIXOUTR_VOL_M3DB 4
358#define WM8350_IN3R_MIXOUTR_VOL_0DB 5
359#define WM8350_IN3R_MIXOUTR_VOL_3DB 6
360#define WM8350_IN3R_MIXOUTR_VOL_6DB 7
361
362#define WM8350_INR_MIXOUTR_VOL_OFF 0
363#define WM8350_INR_MIXOUTR_VOL_M12DB 1
364#define WM8350_INR_MIXOUTR_VOL_M9DB 2
365#define WM8350_INR_MIXOUTR_VOL_M6DB 3
366#define WM8350_INR_MIXOUTR_VOL_M3DB 4
367#define WM8350_INR_MIXOUTR_VOL_0DB 5
368#define WM8350_INR_MIXOUTR_VOL_3DB 6
369#define WM8350_INR_MIXOUTR_VOL_6DB 7
370
371#define WM8350_INL_MIXOUTR_VOL_OFF 0
372#define WM8350_INL_MIXOUTR_VOL_M12DB 1
373#define WM8350_INL_MIXOUTR_VOL_M9DB 2
374#define WM8350_INL_MIXOUTR_VOL_M6DB 3
375#define WM8350_INL_MIXOUTR_VOL_M3DB 4
376#define WM8350_INL_MIXOUTR_VOL_0DB 5
377#define WM8350_INL_MIXOUTR_VOL_3DB 6
378#define WM8350_INL_MIXOUTR_VOL_6DB 7
379
380/*
381 * R98 (0x62) - Input Mixer Volume L
382 */
383#define WM8350_IN3L_MIXINL_VOL_MASK 0x0E00
384#define WM8350_IN2L_MIXINL_VOL_MASK 0x000E
385#define WM8350_INL_MIXINL_VOL 0x0001
386
387/*
388 * R99 (0x63) - Input Mixer Volume R
389 */
390#define WM8350_IN3R_MIXINR_VOL_MASK 0xE000
391#define WM8350_IN2R_MIXINR_VOL_MASK 0x00E0
392#define WM8350_INR_MIXINR_VOL 0x0001
393
394/*
395 * R100 (0x64) - Input Mixer Volume
396 */
397#define WM8350_OUT4_MIXIN_DST 0x8000
398#define WM8350_OUT4_MIXIN_VOL_MASK 0x000E
399
400/*
401 * R104 (0x68) - LOUT1 Volume
402 */
403#define WM8350_OUT1L_MUTE 0x4000
404#define WM8350_OUT1L_ZC 0x2000
405#define WM8350_OUT1_VU 0x0100
406#define WM8350_OUT1L_VOL_MASK 0x00FC
407#define WM8350_OUT1L_VOL_SHIFT 2
408
409/*
410 * R105 (0x69) - ROUT1 Volume
411 */
412#define WM8350_OUT1R_MUTE 0x4000
413#define WM8350_OUT1R_ZC 0x2000
414#define WM8350_OUT1_VU 0x0100
415#define WM8350_OUT1R_VOL_MASK 0x00FC
416#define WM8350_OUT1R_VOL_SHIFT 2
417
418/*
419 * R106 (0x6A) - LOUT2 Volume
420 */
421#define WM8350_OUT2L_MUTE 0x4000
422#define WM8350_OUT2L_ZC 0x2000
423#define WM8350_OUT2_VU 0x0100
424#define WM8350_OUT2L_VOL_MASK 0x00FC
425
426/*
427 * R107 (0x6B) - ROUT2 Volume
428 */
429#define WM8350_OUT2R_MUTE 0x4000
430#define WM8350_OUT2R_ZC 0x2000
431#define WM8350_OUT2R_INV 0x0400
432#define WM8350_OUT2R_INV_MUTE 0x0200
433#define WM8350_OUT2_VU 0x0100
434#define WM8350_OUT2R_VOL_MASK 0x00FC
435
436/*
437 * R111 (0x6F) - BEEP Volume
438 */
439#define WM8350_IN3R_OUT2R_VOL_MASK 0x00E0
440
441/*
442 * R112 (0x70) - AI Formating
443 */
444#define WM8350_AIF_BCLK_INV 0x8000
445#define WM8350_AIF_TRI 0x2000
446#define WM8350_AIF_LRCLK_INV 0x1000
447#define WM8350_AIF_WL_MASK 0x0C00
448#define WM8350_AIF_FMT_MASK 0x0300
449
450/*
451 * R113 (0x71) - ADC DAC COMP
452 */
453#define WM8350_DAC_COMP 0x0080
454#define WM8350_DAC_COMPMODE 0x0040
455#define WM8350_ADC_COMP 0x0020
456#define WM8350_ADC_COMPMODE 0x0010
457#define WM8350_LOOPBACK 0x0001
458
459/*
460 * R114 (0x72) - AI ADC Control
461 */
462#define WM8350_AIFADC_PD 0x0080
463#define WM8350_AIFADCL_SRC 0x0040
464#define WM8350_AIFADCR_SRC 0x0020
465#define WM8350_AIFADC_TDM_CHAN 0x0010
466#define WM8350_AIFADC_TDM 0x0008
467
468/*
469 * R115 (0x73) - AI DAC Control
470 */
471#define WM8350_BCLK_MSTR 0x4000
472#define WM8350_AIFDAC_PD 0x0080
473#define WM8350_DACL_SRC 0x0040
474#define WM8350_DACR_SRC 0x0020
475#define WM8350_AIFDAC_TDM_CHAN 0x0010
476#define WM8350_AIFDAC_TDM 0x0008
477#define WM8350_DAC_BOOST_MASK 0x0003
478
479/*
480 * R116 (0x74) - AIF Test
481 */
482#define WM8350_CODEC_BYP 0x4000
483#define WM8350_AIFADC_WR_TST 0x2000
484#define WM8350_AIFADC_RD_TST 0x1000
485#define WM8350_AIFDAC_WR_TST 0x0800
486#define WM8350_AIFDAC_RD_TST 0x0400
487#define WM8350_AIFADC_ASYN 0x0020
488#define WM8350_AIFDAC_ASYN 0x0010
489
490/*
491 * R231 (0xE7) - Jack Status
492 */
493#define WM8350_JACK_R_LVL 0x0400
494
495/*
496 * WM8350 Platform setup
497 */
498#define WM8350_S_CURVE_NONE 0x0
499#define WM8350_S_CURVE_FAST 0x1
500#define WM8350_S_CURVE_MEDIUM 0x2
501#define WM8350_S_CURVE_SLOW 0x3
502
503#define WM8350_DISCHARGE_OFF 0x0
504#define WM8350_DISCHARGE_FAST 0x1
505#define WM8350_DISCHARGE_MEDIUM 0x2
506#define WM8350_DISCHARGE_SLOW 0x3
507
508#define WM8350_TIE_OFF_500R 0x0
509#define WM8350_TIE_OFF_30K 0x1
510
511/*
512 * Clock sources & directions
513 */
514#define WM8350_SYSCLK 0
515
516#define WM8350_MCLK_SEL_PLL_MCLK 0
517#define WM8350_MCLK_SEL_PLL_DAC 1
518#define WM8350_MCLK_SEL_PLL_ADC 2
519#define WM8350_MCLK_SEL_PLL_32K 3
520#define WM8350_MCLK_SEL_MCLK 5
521
522#define WM8350_MCLK_DIR_OUT 0
523#define WM8350_MCLK_DIR_IN 1
524
525/* clock divider id's */
526#define WM8350_ADC_CLKDIV 0
527#define WM8350_DAC_CLKDIV 1
528#define WM8350_BCLK_CLKDIV 2
529#define WM8350_OPCLK_CLKDIV 3
530#define WM8350_TO_CLKDIV 4
531#define WM8350_SYS_CLKDIV 5
532#define WM8350_DACLR_CLKDIV 6
533#define WM8350_ADCLR_CLKDIV 7
534
535/* ADC clock dividers */
536#define WM8350_ADCDIV_1 0x0
537#define WM8350_ADCDIV_1_5 0x1
538#define WM8350_ADCDIV_2 0x2
539#define WM8350_ADCDIV_3 0x3
540#define WM8350_ADCDIV_4 0x4
541#define WM8350_ADCDIV_5_5 0x5
542#define WM8350_ADCDIV_6 0x6
543
544/* ADC clock dividers */
545#define WM8350_DACDIV_1 0x0
546#define WM8350_DACDIV_1_5 0x1
547#define WM8350_DACDIV_2 0x2
548#define WM8350_DACDIV_3 0x3
549#define WM8350_DACDIV_4 0x4
550#define WM8350_DACDIV_5_5 0x5
551#define WM8350_DACDIV_6 0x6
552
553/* BCLK clock dividers */
554#define WM8350_BCLK_DIV_1 (0x0 << 4)
555#define WM8350_BCLK_DIV_1_5 (0x1 << 4)
556#define WM8350_BCLK_DIV_2 (0x2 << 4)
557#define WM8350_BCLK_DIV_3 (0x3 << 4)
558#define WM8350_BCLK_DIV_4 (0x4 << 4)
559#define WM8350_BCLK_DIV_5_5 (0x5 << 4)
560#define WM8350_BCLK_DIV_6 (0x6 << 4)
561#define WM8350_BCLK_DIV_8 (0x7 << 4)
562#define WM8350_BCLK_DIV_11 (0x8 << 4)
563#define WM8350_BCLK_DIV_12 (0x9 << 4)
564#define WM8350_BCLK_DIV_16 (0xa << 4)
565#define WM8350_BCLK_DIV_22 (0xb << 4)
566#define WM8350_BCLK_DIV_24 (0xc << 4)
567#define WM8350_BCLK_DIV_32 (0xd << 4)
568#define WM8350_BCLK_DIV_44 (0xe << 4)
569#define WM8350_BCLK_DIV_48 (0xf << 4)
570
571/* Sys (MCLK) clock dividers */
572#define WM8350_MCLK_DIV_1 (0x0 << 8)
573#define WM8350_MCLK_DIV_2 (0x1 << 8)
574
575/* OP clock dividers */
576#define WM8350_OPCLK_DIV_1 0x0
577#define WM8350_OPCLK_DIV_2 0x1
578#define WM8350_OPCLK_DIV_3 0x2
579#define WM8350_OPCLK_DIV_4 0x3
580#define WM8350_OPCLK_DIV_5_5 0x4
581#define WM8350_OPCLK_DIV_6 0x5
582
583/* DAI ID */
584#define WM8350_HIFI_DAI 0
585
586/*
587 * Audio interrupts.
588 */
589#define WM8350_IRQ_CODEC_JCK_DET_L 39
590#define WM8350_IRQ_CODEC_JCK_DET_R 40
591#define WM8350_IRQ_CODEC_MICSCD 41
592#define WM8350_IRQ_CODEC_MICD 42
593
594struct wm8350_codec {
595 struct platform_device *pdev;
596};
597
598#endif
diff --git a/include/linux/mfd/wm8350/comparator.h b/include/linux/mfd/wm8350/comparator.h
new file mode 100644
index 000000000000..053788649452
--- /dev/null
+++ b/include/linux/mfd/wm8350/comparator.h
@@ -0,0 +1,167 @@
1/*
2 * comparator.h -- Comparator Aux ADC for Wolfson WM8350 PMIC
3 *
4 * Copyright 2007 Wolfson Microelectronics PLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __LINUX_MFD_WM8350_COMPARATOR_H_
13#define __LINUX_MFD_WM8350_COMPARATOR_H_
14
15/*
16 * Registers
17 */
18
19#define WM8350_DIGITISER_CONTROL_1 0x90
20#define WM8350_DIGITISER_CONTROL_2 0x91
21#define WM8350_AUX1_READBACK 0x98
22#define WM8350_AUX2_READBACK 0x99
23#define WM8350_AUX3_READBACK 0x9A
24#define WM8350_AUX4_READBACK 0x9B
25#define WM8350_CHIP_TEMP_READBACK 0x9F
26#define WM8350_GENERIC_COMPARATOR_CONTROL 0xA3
27#define WM8350_GENERIC_COMPARATOR_1 0xA4
28#define WM8350_GENERIC_COMPARATOR_2 0xA5
29#define WM8350_GENERIC_COMPARATOR_3 0xA6
30#define WM8350_GENERIC_COMPARATOR_4 0xA7
31
32/*
33 * R144 (0x90) - Digitiser Control (1)
34 */
35#define WM8350_AUXADC_CTC 0x4000
36#define WM8350_AUXADC_POLL 0x2000
37#define WM8350_AUXADC_HIB_MODE 0x1000
38#define WM8350_AUXADC_SEL8 0x0080
39#define WM8350_AUXADC_SEL7 0x0040
40#define WM8350_AUXADC_SEL6 0x0020
41#define WM8350_AUXADC_SEL5 0x0010
42#define WM8350_AUXADC_SEL4 0x0008
43#define WM8350_AUXADC_SEL3 0x0004
44#define WM8350_AUXADC_SEL2 0x0002
45#define WM8350_AUXADC_SEL1 0x0001
46
47/*
48 * R145 (0x91) - Digitiser Control (2)
49 */
50#define WM8350_AUXADC_MASKMODE_MASK 0x3000
51#define WM8350_AUXADC_CRATE_MASK 0x0700
52#define WM8350_AUXADC_CAL 0x0004
53#define WM8350_AUX_RBMODE 0x0002
54#define WM8350_AUXADC_WAIT 0x0001
55
56/*
57 * R152 (0x98) - AUX1 Readback
58 */
59#define WM8350_AUXADC_SCALE1_MASK 0x6000
60#define WM8350_AUXADC_REF1 0x1000
61#define WM8350_AUXADC_DATA1_MASK 0x0FFF
62
63/*
64 * R153 (0x99) - AUX2 Readback
65 */
66#define WM8350_AUXADC_SCALE2_MASK 0x6000
67#define WM8350_AUXADC_REF2 0x1000
68#define WM8350_AUXADC_DATA2_MASK 0x0FFF
69
70/*
71 * R154 (0x9A) - AUX3 Readback
72 */
73#define WM8350_AUXADC_SCALE3_MASK 0x6000
74#define WM8350_AUXADC_REF3 0x1000
75#define WM8350_AUXADC_DATA3_MASK 0x0FFF
76
77/*
78 * R155 (0x9B) - AUX4 Readback
79 */
80#define WM8350_AUXADC_SCALE4_MASK 0x6000
81#define WM8350_AUXADC_REF4 0x1000
82#define WM8350_AUXADC_DATA4_MASK 0x0FFF
83
84/*
85 * R156 (0x9C) - USB Voltage Readback
86 */
87#define WM8350_AUXADC_DATA_USB_MASK 0x0FFF
88
89/*
90 * R157 (0x9D) - LINE Voltage Readback
91 */
92#define WM8350_AUXADC_DATA_LINE_MASK 0x0FFF
93
94/*
95 * R158 (0x9E) - BATT Voltage Readback
96 */
97#define WM8350_AUXADC_DATA_BATT_MASK 0x0FFF
98
99/*
100 * R159 (0x9F) - Chip Temp Readback
101 */
102#define WM8350_AUXADC_DATA_CHIPTEMP_MASK 0x0FFF
103
104/*
105 * R163 (0xA3) - Generic Comparator Control
106 */
107#define WM8350_DCMP4_ENA 0x0008
108#define WM8350_DCMP3_ENA 0x0004
109#define WM8350_DCMP2_ENA 0x0002
110#define WM8350_DCMP1_ENA 0x0001
111
112/*
113 * R164 (0xA4) - Generic comparator 1
114 */
115#define WM8350_DCMP1_SRCSEL_MASK 0xE000
116#define WM8350_DCMP1_GT 0x1000
117#define WM8350_DCMP1_THR_MASK 0x0FFF
118
119/*
120 * R165 (0xA5) - Generic comparator 2
121 */
122#define WM8350_DCMP2_SRCSEL_MASK 0xE000
123#define WM8350_DCMP2_GT 0x1000
124#define WM8350_DCMP2_THR_MASK 0x0FFF
125
126/*
127 * R166 (0xA6) - Generic comparator 3
128 */
129#define WM8350_DCMP3_SRCSEL_MASK 0xE000
130#define WM8350_DCMP3_GT 0x1000
131#define WM8350_DCMP3_THR_MASK 0x0FFF
132
133/*
134 * R167 (0xA7) - Generic comparator 4
135 */
136#define WM8350_DCMP4_SRCSEL_MASK 0xE000
137#define WM8350_DCMP4_GT 0x1000
138#define WM8350_DCMP4_THR_MASK 0x0FFF
139
140/*
141 * Interrupts.
142 */
143#define WM8350_IRQ_AUXADC_DATARDY 16
144#define WM8350_IRQ_AUXADC_DCOMP4 17
145#define WM8350_IRQ_AUXADC_DCOMP3 18
146#define WM8350_IRQ_AUXADC_DCOMP2 19
147#define WM8350_IRQ_AUXADC_DCOMP1 20
148#define WM8350_IRQ_SYS_HYST_COMP_FAIL 21
149#define WM8350_IRQ_SYS_CHIP_GT115 22
150#define WM8350_IRQ_SYS_CHIP_GT140 23
151
152/*
153 * USB/2, LINE & BATT = ((VRTC * 2) / 4095)) * 10e6 uV
154 * Where VRTC = 2.7 V
155 */
156#define WM8350_AUX_COEFF 1319
157
158#define WM8350_AUXADC_AUX1 0
159#define WM8350_AUXADC_AUX2 1
160#define WM8350_AUXADC_AUX3 2
161#define WM8350_AUXADC_AUX4 3
162#define WM8350_AUXADC_USB 4
163#define WM8350_AUXADC_LINE 5
164#define WM8350_AUXADC_BATT 6
165#define WM8350_AUXADC_TEMP 7
166
167#endif
diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h
new file mode 100644
index 000000000000..6ebf97f2a475
--- /dev/null
+++ b/include/linux/mfd/wm8350/core.h
@@ -0,0 +1,631 @@
1/*
2 * core.h -- Core Driver for Wolfson WM8350 PMIC
3 *
4 * Copyright 2007 Wolfson Microelectronics PLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifndef __LINUX_MFD_WM8350_CORE_H_
14#define __LINUX_MFD_WM8350_CORE_H_
15
16#include <linux/kernel.h>
17#include <linux/mutex.h>
18#include <linux/workqueue.h>
19
20#include <linux/mfd/wm8350/audio.h>
21#include <linux/mfd/wm8350/gpio.h>
22#include <linux/mfd/wm8350/pmic.h>
23#include <linux/mfd/wm8350/rtc.h>
24#include <linux/mfd/wm8350/supply.h>
25#include <linux/mfd/wm8350/wdt.h>
26
27/*
28 * Register values.
29 */
30#define WM8350_RESET_ID 0x00
31#define WM8350_ID 0x01
32#define WM8350_SYSTEM_CONTROL_1 0x03
33#define WM8350_SYSTEM_CONTROL_2 0x04
34#define WM8350_SYSTEM_HIBERNATE 0x05
35#define WM8350_INTERFACE_CONTROL 0x06
36#define WM8350_POWER_MGMT_1 0x08
37#define WM8350_POWER_MGMT_2 0x09
38#define WM8350_POWER_MGMT_3 0x0A
39#define WM8350_POWER_MGMT_4 0x0B
40#define WM8350_POWER_MGMT_5 0x0C
41#define WM8350_POWER_MGMT_6 0x0D
42#define WM8350_POWER_MGMT_7 0x0E
43
44#define WM8350_SYSTEM_INTERRUPTS 0x18
45#define WM8350_INT_STATUS_1 0x19
46#define WM8350_INT_STATUS_2 0x1A
47#define WM8350_POWER_UP_INT_STATUS 0x1B
48#define WM8350_UNDER_VOLTAGE_INT_STATUS 0x1C
49#define WM8350_OVER_CURRENT_INT_STATUS 0x1D
50#define WM8350_GPIO_INT_STATUS 0x1E
51#define WM8350_COMPARATOR_INT_STATUS 0x1F
52#define WM8350_SYSTEM_INTERRUPTS_MASK 0x20
53#define WM8350_INT_STATUS_1_MASK 0x21
54#define WM8350_INT_STATUS_2_MASK 0x22
55#define WM8350_POWER_UP_INT_STATUS_MASK 0x23
56#define WM8350_UNDER_VOLTAGE_INT_STATUS_MASK 0x24
57#define WM8350_OVER_CURRENT_INT_STATUS_MASK 0x25
58#define WM8350_GPIO_INT_STATUS_MASK 0x26
59#define WM8350_COMPARATOR_INT_STATUS_MASK 0x27
60
61#define WM8350_MAX_REGISTER 0xFF
62
63/*
64 * Field Definitions.
65 */
66
67/*
68 * R0 (0x00) - Reset/ID
69 */
70#define WM8350_SW_RESET_CHIP_ID_MASK 0xFFFF
71
72/*
73 * R1 (0x01) - ID
74 */
75#define WM8350_CHIP_REV_MASK 0x7000
76#define WM8350_CONF_STS_MASK 0x0C00
77#define WM8350_CUST_ID_MASK 0x00FF
78
79/*
80 * R3 (0x03) - System Control 1
81 */
82#define WM8350_CHIP_ON 0x8000
83#define WM8350_POWERCYCLE 0x2000
84#define WM8350_VCC_FAULT_OV 0x1000
85#define WM8350_REG_RSTB_TIME_MASK 0x0C00
86#define WM8350_BG_SLEEP 0x0200
87#define WM8350_MEM_VALID 0x0020
88#define WM8350_CHIP_SET_UP 0x0010
89#define WM8350_ON_DEB_T 0x0008
90#define WM8350_ON_POL 0x0002
91#define WM8350_IRQ_POL 0x0001
92
93/*
94 * R4 (0x04) - System Control 2
95 */
96#define WM8350_USB_SUSPEND_8MA 0x8000
97#define WM8350_USB_SUSPEND 0x4000
98#define WM8350_USB_MSTR 0x2000
99#define WM8350_USB_MSTR_SRC 0x1000
100#define WM8350_USB_500MA 0x0800
101#define WM8350_USB_NOLIM 0x0400
102
103/*
104 * R5 (0x05) - System Hibernate
105 */
106#define WM8350_HIBERNATE 0x8000
107#define WM8350_WDOG_HIB_MODE 0x0080
108#define WM8350_REG_HIB_STARTUP_SEQ 0x0040
109#define WM8350_REG_RESET_HIB_MODE 0x0020
110#define WM8350_RST_HIB_MODE 0x0010
111#define WM8350_IRQ_HIB_MODE 0x0008
112#define WM8350_MEMRST_HIB_MODE 0x0004
113#define WM8350_PCCOMP_HIB_MODE 0x0002
114#define WM8350_TEMPMON_HIB_MODE 0x0001
115
116/*
117 * R6 (0x06) - Interface Control
118 */
119#define WM8350_USE_DEV_PINS 0x8000
120#define WM8350_USE_DEV_PINS_MASK 0x8000
121#define WM8350_USE_DEV_PINS_SHIFT 15
122#define WM8350_DEV_ADDR_MASK 0x6000
123#define WM8350_DEV_ADDR_SHIFT 13
124#define WM8350_CONFIG_DONE 0x1000
125#define WM8350_CONFIG_DONE_MASK 0x1000
126#define WM8350_CONFIG_DONE_SHIFT 12
127#define WM8350_RECONFIG_AT_ON 0x0800
128#define WM8350_RECONFIG_AT_ON_MASK 0x0800
129#define WM8350_RECONFIG_AT_ON_SHIFT 11
130#define WM8350_AUTOINC 0x0200
131#define WM8350_AUTOINC_MASK 0x0200
132#define WM8350_AUTOINC_SHIFT 9
133#define WM8350_ARA 0x0100
134#define WM8350_ARA_MASK 0x0100
135#define WM8350_ARA_SHIFT 8
136#define WM8350_SPI_CFG 0x0008
137#define WM8350_SPI_CFG_MASK 0x0008
138#define WM8350_SPI_CFG_SHIFT 3
139#define WM8350_SPI_4WIRE 0x0004
140#define WM8350_SPI_4WIRE_MASK 0x0004
141#define WM8350_SPI_4WIRE_SHIFT 2
142#define WM8350_SPI_3WIRE 0x0002
143#define WM8350_SPI_3WIRE_MASK 0x0002
144#define WM8350_SPI_3WIRE_SHIFT 1
145
146/* Bit values for R06 (0x06) */
147#define WM8350_USE_DEV_PINS_PRIMARY 0
148#define WM8350_USE_DEV_PINS_DEV 1
149
150#define WM8350_DEV_ADDR_34 0
151#define WM8350_DEV_ADDR_36 1
152#define WM8350_DEV_ADDR_3C 2
153#define WM8350_DEV_ADDR_3E 3
154
155#define WM8350_CONFIG_DONE_OFF 0
156#define WM8350_CONFIG_DONE_DONE 1
157
158#define WM8350_RECONFIG_AT_ON_OFF 0
159#define WM8350_RECONFIG_AT_ON_ON 1
160
161#define WM8350_AUTOINC_OFF 0
162#define WM8350_AUTOINC_ON 1
163
164#define WM8350_ARA_OFF 0
165#define WM8350_ARA_ON 1
166
167#define WM8350_SPI_CFG_CMOS 0
168#define WM8350_SPI_CFG_OD 1
169
170#define WM8350_SPI_4WIRE_3WIRE 0
171#define WM8350_SPI_4WIRE_4WIRE 1
172
173#define WM8350_SPI_3WIRE_I2C 0
174#define WM8350_SPI_3WIRE_SPI 1
175
176/*
177 * R8 (0x08) - Power mgmt (1)
178 */
179#define WM8350_CODEC_ISEL_MASK 0xC000
180#define WM8350_VBUFEN 0x2000
181#define WM8350_OUTPUT_DRAIN_EN 0x0400
182#define WM8350_MIC_DET_ENA 0x0100
183#define WM8350_BIASEN 0x0020
184#define WM8350_MICBEN 0x0010
185#define WM8350_VMIDEN 0x0004
186#define WM8350_VMID_MASK 0x0003
187#define WM8350_VMID_SHIFT 0
188
189/*
190 * R9 (0x09) - Power mgmt (2)
191 */
192#define WM8350_IN3R_ENA 0x0800
193#define WM8350_IN3L_ENA 0x0400
194#define WM8350_INR_ENA 0x0200
195#define WM8350_INL_ENA 0x0100
196#define WM8350_MIXINR_ENA 0x0080
197#define WM8350_MIXINL_ENA 0x0040
198#define WM8350_OUT4_ENA 0x0020
199#define WM8350_OUT3_ENA 0x0010
200#define WM8350_MIXOUTR_ENA 0x0002
201#define WM8350_MIXOUTL_ENA 0x0001
202
203/*
204 * R10 (0x0A) - Power mgmt (3)
205 */
206#define WM8350_IN3R_TO_OUT2R 0x0080
207#define WM8350_OUT2R_ENA 0x0008
208#define WM8350_OUT2L_ENA 0x0004
209#define WM8350_OUT1R_ENA 0x0002
210#define WM8350_OUT1L_ENA 0x0001
211
212/*
213 * R11 (0x0B) - Power mgmt (4)
214 */
215#define WM8350_SYSCLK_ENA 0x4000
216#define WM8350_ADC_HPF_ENA 0x2000
217#define WM8350_FLL_ENA 0x0800
218#define WM8350_FLL_OSC_ENA 0x0400
219#define WM8350_TOCLK_ENA 0x0100
220#define WM8350_DACR_ENA 0x0020
221#define WM8350_DACL_ENA 0x0010
222#define WM8350_ADCR_ENA 0x0008
223#define WM8350_ADCL_ENA 0x0004
224
225/*
226 * R12 (0x0C) - Power mgmt (5)
227 */
228#define WM8350_CODEC_ENA 0x1000
229#define WM8350_RTC_TICK_ENA 0x0800
230#define WM8350_OSC32K_ENA 0x0400
231#define WM8350_CHG_ENA 0x0200
232#define WM8350_ACC_DET_ENA 0x0100
233#define WM8350_AUXADC_ENA 0x0080
234#define WM8350_DCMP4_ENA 0x0008
235#define WM8350_DCMP3_ENA 0x0004
236#define WM8350_DCMP2_ENA 0x0002
237#define WM8350_DCMP1_ENA 0x0001
238
239/*
240 * R13 (0x0D) - Power mgmt (6)
241 */
242#define WM8350_LS_ENA 0x8000
243#define WM8350_LDO4_ENA 0x0800
244#define WM8350_LDO3_ENA 0x0400
245#define WM8350_LDO2_ENA 0x0200
246#define WM8350_LDO1_ENA 0x0100
247#define WM8350_DC6_ENA 0x0020
248#define WM8350_DC5_ENA 0x0010
249#define WM8350_DC4_ENA 0x0008
250#define WM8350_DC3_ENA 0x0004
251#define WM8350_DC2_ENA 0x0002
252#define WM8350_DC1_ENA 0x0001
253
254/*
255 * R14 (0x0E) - Power mgmt (7)
256 */
257#define WM8350_CS2_ENA 0x0002
258#define WM8350_CS1_ENA 0x0001
259
260/*
261 * R24 (0x18) - System Interrupts
262 */
263#define WM8350_OC_INT 0x2000
264#define WM8350_UV_INT 0x1000
265#define WM8350_PUTO_INT 0x0800
266#define WM8350_CS_INT 0x0200
267#define WM8350_EXT_INT 0x0100
268#define WM8350_CODEC_INT 0x0080
269#define WM8350_GP_INT 0x0040
270#define WM8350_AUXADC_INT 0x0020
271#define WM8350_RTC_INT 0x0010
272#define WM8350_SYS_INT 0x0008
273#define WM8350_CHG_INT 0x0004
274#define WM8350_USB_INT 0x0002
275#define WM8350_WKUP_INT 0x0001
276
277/*
278 * R25 (0x19) - Interrupt Status 1
279 */
280#define WM8350_CHG_BAT_HOT_EINT 0x8000
281#define WM8350_CHG_BAT_COLD_EINT 0x4000
282#define WM8350_CHG_BAT_FAIL_EINT 0x2000
283#define WM8350_CHG_TO_EINT 0x1000
284#define WM8350_CHG_END_EINT 0x0800
285#define WM8350_CHG_START_EINT 0x0400
286#define WM8350_CHG_FAST_RDY_EINT 0x0200
287#define WM8350_RTC_PER_EINT 0x0080
288#define WM8350_RTC_SEC_EINT 0x0040
289#define WM8350_RTC_ALM_EINT 0x0020
290#define WM8350_CHG_VBATT_LT_3P9_EINT 0x0004
291#define WM8350_CHG_VBATT_LT_3P1_EINT 0x0002
292#define WM8350_CHG_VBATT_LT_2P85_EINT 0x0001
293
294/*
295 * R26 (0x1A) - Interrupt Status 2
296 */
297#define WM8350_CS1_EINT 0x2000
298#define WM8350_CS2_EINT 0x1000
299#define WM8350_USB_LIMIT_EINT 0x0400
300#define WM8350_AUXADC_DATARDY_EINT 0x0100
301#define WM8350_AUXADC_DCOMP4_EINT 0x0080
302#define WM8350_AUXADC_DCOMP3_EINT 0x0040
303#define WM8350_AUXADC_DCOMP2_EINT 0x0020
304#define WM8350_AUXADC_DCOMP1_EINT 0x0010
305#define WM8350_SYS_HYST_COMP_FAIL_EINT 0x0008
306#define WM8350_SYS_CHIP_GT115_EINT 0x0004
307#define WM8350_SYS_CHIP_GT140_EINT 0x0002
308#define WM8350_SYS_WDOG_TO_EINT 0x0001
309
310/*
311 * R27 (0x1B) - Power Up Interrupt Status
312 */
313#define WM8350_PUTO_LDO4_EINT 0x0800
314#define WM8350_PUTO_LDO3_EINT 0x0400
315#define WM8350_PUTO_LDO2_EINT 0x0200
316#define WM8350_PUTO_LDO1_EINT 0x0100
317#define WM8350_PUTO_DC6_EINT 0x0020
318#define WM8350_PUTO_DC5_EINT 0x0010
319#define WM8350_PUTO_DC4_EINT 0x0008
320#define WM8350_PUTO_DC3_EINT 0x0004
321#define WM8350_PUTO_DC2_EINT 0x0002
322#define WM8350_PUTO_DC1_EINT 0x0001
323
324/*
325 * R28 (0x1C) - Under Voltage Interrupt status
326 */
327#define WM8350_UV_LDO4_EINT 0x0800
328#define WM8350_UV_LDO3_EINT 0x0400
329#define WM8350_UV_LDO2_EINT 0x0200
330#define WM8350_UV_LDO1_EINT 0x0100
331#define WM8350_UV_DC6_EINT 0x0020
332#define WM8350_UV_DC5_EINT 0x0010
333#define WM8350_UV_DC4_EINT 0x0008
334#define WM8350_UV_DC3_EINT 0x0004
335#define WM8350_UV_DC2_EINT 0x0002
336#define WM8350_UV_DC1_EINT 0x0001
337
338/*
339 * R29 (0x1D) - Over Current Interrupt status
340 */
341#define WM8350_OC_LS_EINT 0x8000
342
343/*
344 * R30 (0x1E) - GPIO Interrupt Status
345 */
346#define WM8350_GP12_EINT 0x1000
347#define WM8350_GP11_EINT 0x0800
348#define WM8350_GP10_EINT 0x0400
349#define WM8350_GP9_EINT 0x0200
350#define WM8350_GP8_EINT 0x0100
351#define WM8350_GP7_EINT 0x0080
352#define WM8350_GP6_EINT 0x0040
353#define WM8350_GP5_EINT 0x0020
354#define WM8350_GP4_EINT 0x0010
355#define WM8350_GP3_EINT 0x0008
356#define WM8350_GP2_EINT 0x0004
357#define WM8350_GP1_EINT 0x0002
358#define WM8350_GP0_EINT 0x0001
359
360/*
361 * R31 (0x1F) - Comparator Interrupt Status
362 */
363#define WM8350_EXT_USB_FB_EINT 0x8000
364#define WM8350_EXT_WALL_FB_EINT 0x4000
365#define WM8350_EXT_BAT_FB_EINT 0x2000
366#define WM8350_CODEC_JCK_DET_L_EINT 0x0800
367#define WM8350_CODEC_JCK_DET_R_EINT 0x0400
368#define WM8350_CODEC_MICSCD_EINT 0x0200
369#define WM8350_CODEC_MICD_EINT 0x0100
370#define WM8350_WKUP_OFF_STATE_EINT 0x0040
371#define WM8350_WKUP_HIB_STATE_EINT 0x0020
372#define WM8350_WKUP_CONV_FAULT_EINT 0x0010
373#define WM8350_WKUP_WDOG_RST_EINT 0x0008
374#define WM8350_WKUP_GP_PWR_ON_EINT 0x0004
375#define WM8350_WKUP_ONKEY_EINT 0x0002
376#define WM8350_WKUP_GP_WAKEUP_EINT 0x0001
377
378/*
379 * R32 (0x20) - System Interrupts Mask
380 */
381#define WM8350_IM_OC_INT 0x2000
382#define WM8350_IM_UV_INT 0x1000
383#define WM8350_IM_PUTO_INT 0x0800
384#define WM8350_IM_SPARE_INT 0x0400
385#define WM8350_IM_CS_INT 0x0200
386#define WM8350_IM_EXT_INT 0x0100
387#define WM8350_IM_CODEC_INT 0x0080
388#define WM8350_IM_GP_INT 0x0040
389#define WM8350_IM_AUXADC_INT 0x0020
390#define WM8350_IM_RTC_INT 0x0010
391#define WM8350_IM_SYS_INT 0x0008
392#define WM8350_IM_CHG_INT 0x0004
393#define WM8350_IM_USB_INT 0x0002
394#define WM8350_IM_WKUP_INT 0x0001
395
396/*
397 * R33 (0x21) - Interrupt Status 1 Mask
398 */
399#define WM8350_IM_CHG_BAT_HOT_EINT 0x8000
400#define WM8350_IM_CHG_BAT_COLD_EINT 0x4000
401#define WM8350_IM_CHG_BAT_FAIL_EINT 0x2000
402#define WM8350_IM_CHG_TO_EINT 0x1000
403#define WM8350_IM_CHG_END_EINT 0x0800
404#define WM8350_IM_CHG_START_EINT 0x0400
405#define WM8350_IM_CHG_FAST_RDY_EINT 0x0200
406#define WM8350_IM_RTC_PER_EINT 0x0080
407#define WM8350_IM_RTC_SEC_EINT 0x0040
408#define WM8350_IM_RTC_ALM_EINT 0x0020
409#define WM8350_IM_CHG_VBATT_LT_3P9_EINT 0x0004
410#define WM8350_IM_CHG_VBATT_LT_3P1_EINT 0x0002
411#define WM8350_IM_CHG_VBATT_LT_2P85_EINT 0x0001
412
413/*
414 * R34 (0x22) - Interrupt Status 2 Mask
415 */
416#define WM8350_IM_SPARE2_EINT 0x8000
417#define WM8350_IM_SPARE1_EINT 0x4000
418#define WM8350_IM_CS1_EINT 0x2000
419#define WM8350_IM_CS2_EINT 0x1000
420#define WM8350_IM_USB_LIMIT_EINT 0x0400
421#define WM8350_IM_AUXADC_DATARDY_EINT 0x0100
422#define WM8350_IM_AUXADC_DCOMP4_EINT 0x0080
423#define WM8350_IM_AUXADC_DCOMP3_EINT 0x0040
424#define WM8350_IM_AUXADC_DCOMP2_EINT 0x0020
425#define WM8350_IM_AUXADC_DCOMP1_EINT 0x0010
426#define WM8350_IM_SYS_HYST_COMP_FAIL_EINT 0x0008
427#define WM8350_IM_SYS_CHIP_GT115_EINT 0x0004
428#define WM8350_IM_SYS_CHIP_GT140_EINT 0x0002
429#define WM8350_IM_SYS_WDOG_TO_EINT 0x0001
430
431/*
432 * R35 (0x23) - Power Up Interrupt Status Mask
433 */
434#define WM8350_IM_PUTO_LDO4_EINT 0x0800
435#define WM8350_IM_PUTO_LDO3_EINT 0x0400
436#define WM8350_IM_PUTO_LDO2_EINT 0x0200
437#define WM8350_IM_PUTO_LDO1_EINT 0x0100
438#define WM8350_IM_PUTO_DC6_EINT 0x0020
439#define WM8350_IM_PUTO_DC5_EINT 0x0010
440#define WM8350_IM_PUTO_DC4_EINT 0x0008
441#define WM8350_IM_PUTO_DC3_EINT 0x0004
442#define WM8350_IM_PUTO_DC2_EINT 0x0002
443#define WM8350_IM_PUTO_DC1_EINT 0x0001
444
445/*
446 * R36 (0x24) - Under Voltage Interrupt status Mask
447 */
448#define WM8350_IM_UV_LDO4_EINT 0x0800
449#define WM8350_IM_UV_LDO3_EINT 0x0400
450#define WM8350_IM_UV_LDO2_EINT 0x0200
451#define WM8350_IM_UV_LDO1_EINT 0x0100
452#define WM8350_IM_UV_DC6_EINT 0x0020
453#define WM8350_IM_UV_DC5_EINT 0x0010
454#define WM8350_IM_UV_DC4_EINT 0x0008
455#define WM8350_IM_UV_DC3_EINT 0x0004
456#define WM8350_IM_UV_DC2_EINT 0x0002
457#define WM8350_IM_UV_DC1_EINT 0x0001
458
459/*
460 * R37 (0x25) - Over Current Interrupt status Mask
461 */
462#define WM8350_IM_OC_LS_EINT 0x8000
463
464/*
465 * R38 (0x26) - GPIO Interrupt Status Mask
466 */
467#define WM8350_IM_GP12_EINT 0x1000
468#define WM8350_IM_GP11_EINT 0x0800
469#define WM8350_IM_GP10_EINT 0x0400
470#define WM8350_IM_GP9_EINT 0x0200
471#define WM8350_IM_GP8_EINT 0x0100
472#define WM8350_IM_GP7_EINT 0x0080
473#define WM8350_IM_GP6_EINT 0x0040
474#define WM8350_IM_GP5_EINT 0x0020
475#define WM8350_IM_GP4_EINT 0x0010
476#define WM8350_IM_GP3_EINT 0x0008
477#define WM8350_IM_GP2_EINT 0x0004
478#define WM8350_IM_GP1_EINT 0x0002
479#define WM8350_IM_GP0_EINT 0x0001
480
481/*
482 * R39 (0x27) - Comparator Interrupt Status Mask
483 */
484#define WM8350_IM_EXT_USB_FB_EINT 0x8000
485#define WM8350_IM_EXT_WALL_FB_EINT 0x4000
486#define WM8350_IM_EXT_BAT_FB_EINT 0x2000
487#define WM8350_IM_CODEC_JCK_DET_L_EINT 0x0800
488#define WM8350_IM_CODEC_JCK_DET_R_EINT 0x0400
489#define WM8350_IM_CODEC_MICSCD_EINT 0x0200
490#define WM8350_IM_CODEC_MICD_EINT 0x0100
491#define WM8350_IM_WKUP_OFF_STATE_EINT 0x0040
492#define WM8350_IM_WKUP_HIB_STATE_EINT 0x0020
493#define WM8350_IM_WKUP_CONV_FAULT_EINT 0x0010
494#define WM8350_IM_WKUP_WDOG_RST_EINT 0x0008
495#define WM8350_IM_WKUP_GP_PWR_ON_EINT 0x0004
496#define WM8350_IM_WKUP_ONKEY_EINT 0x0002
497#define WM8350_IM_WKUP_GP_WAKEUP_EINT 0x0001
498
499/*
500 * R220 (0xDC) - RAM BIST 1
501 */
502#define WM8350_READ_STATUS 0x0800
503#define WM8350_TSTRAM_CLK 0x0100
504#define WM8350_TSTRAM_CLK_ENA 0x0080
505#define WM8350_STARTSEQ 0x0040
506#define WM8350_READ_SRC 0x0020
507#define WM8350_COUNT_DIR 0x0010
508#define WM8350_TSTRAM_MODE_MASK 0x000E
509#define WM8350_TSTRAM_ENA 0x0001
510
511/*
512 * R225 (0xE1) - DCDC/LDO status
513 */
514#define WM8350_LS_STS 0x8000
515#define WM8350_LDO4_STS 0x0800
516#define WM8350_LDO3_STS 0x0400
517#define WM8350_LDO2_STS 0x0200
518#define WM8350_LDO1_STS 0x0100
519#define WM8350_DC6_STS 0x0020
520#define WM8350_DC5_STS 0x0010
521#define WM8350_DC4_STS 0x0008
522#define WM8350_DC3_STS 0x0004
523#define WM8350_DC2_STS 0x0002
524#define WM8350_DC1_STS 0x0001
525
526/* WM8350 wake up conditions */
527#define WM8350_IRQ_WKUP_OFF_STATE 43
528#define WM8350_IRQ_WKUP_HIB_STATE 44
529#define WM8350_IRQ_WKUP_CONV_FAULT 45
530#define WM8350_IRQ_WKUP_WDOG_RST 46
531#define WM8350_IRQ_WKUP_GP_PWR_ON 47
532#define WM8350_IRQ_WKUP_ONKEY 48
533#define WM8350_IRQ_WKUP_GP_WAKEUP 49
534
535/* wm8350 chip revisions */
536#define WM8350_REV_E 0x4
537#define WM8350_REV_F 0x5
538#define WM8350_REV_G 0x6
539
540#define WM8350_NUM_IRQ 63
541
542struct wm8350_reg_access {
543 u16 readable; /* Mask of readable bits */
544 u16 writable; /* Mask of writable bits */
545 u16 vol; /* Mask of volatile bits */
546};
547extern const struct wm8350_reg_access wm8350_reg_io_map[];
548extern const u16 wm8350_mode0_defaults[];
549extern const u16 wm8350_mode1_defaults[];
550extern const u16 wm8350_mode2_defaults[];
551extern const u16 wm8350_mode3_defaults[];
552
553struct wm8350;
554
555struct wm8350_irq {
556 void (*handler) (struct wm8350 *, int, void *);
557 void *data;
558};
559
560struct wm8350 {
561 int rev; /* chip revision */
562
563 struct device *dev;
564
565 /* device IO */
566 union {
567 struct i2c_client *i2c_client;
568 struct spi_device *spi_device;
569 };
570 int (*read_dev)(struct wm8350 *wm8350, char reg, int size, void *dest);
571 int (*write_dev)(struct wm8350 *wm8350, char reg, int size,
572 void *src);
573 u16 *reg_cache;
574
575 /* Interrupt handling */
576 struct work_struct irq_work;
577 struct mutex irq_mutex; /* IRQ table mutex */
578 struct wm8350_irq irq[WM8350_NUM_IRQ];
579 int chip_irq;
580
581 /* Client devices */
582 struct wm8350_codec codec;
583 struct wm8350_gpio gpio;
584 struct wm8350_pmic pmic;
585 struct wm8350_power power;
586 struct wm8350_rtc rtc;
587 struct wm8350_wdt wdt;
588};
589
590/**
591 * Data to be supplied by the platform to initialise the WM8350.
592 *
593 * @init: Function called during driver initialisation. Should be
594 * used by the platform to configure GPIO functions and similar.
595 */
596struct wm8350_platform_data {
597 int (*init)(struct wm8350 *wm8350);
598};
599
600
601/*
602 * WM8350 device initialisation and exit.
603 */
604int wm8350_device_init(struct wm8350 *wm8350, int irq,
605 struct wm8350_platform_data *pdata);
606void wm8350_device_exit(struct wm8350 *wm8350);
607
608/*
609 * WM8350 device IO
610 */
611int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
612int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
613u16 wm8350_reg_read(struct wm8350 *wm8350, int reg);
614int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val);
615int wm8350_reg_lock(struct wm8350 *wm8350);
616int wm8350_reg_unlock(struct wm8350 *wm8350);
617int wm8350_block_read(struct wm8350 *wm8350, int reg, int size, u16 *dest);
618int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src);
619
620/*
621 * WM8350 internal interrupts
622 */
623int wm8350_register_irq(struct wm8350 *wm8350, int irq,
624 void (*handler) (struct wm8350 *, int, void *),
625 void *data);
626int wm8350_free_irq(struct wm8350 *wm8350, int irq);
627int wm8350_mask_irq(struct wm8350 *wm8350, int irq);
628int wm8350_unmask_irq(struct wm8350 *wm8350, int irq);
629
630
631#endif
diff --git a/include/linux/mfd/wm8350/gpio.h b/include/linux/mfd/wm8350/gpio.h
new file mode 100644
index 000000000000..ed91e8f5d298
--- /dev/null
+++ b/include/linux/mfd/wm8350/gpio.h
@@ -0,0 +1,342 @@
1/*
2 * gpio.h -- GPIO Driver for Wolfson WM8350 PMIC
3 *
4 * Copyright 2007 Wolfson Microelectronics PLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifndef __LINUX_MFD_WM8350_GPIO_H_
14#define __LINUX_MFD_WM8350_GPIO_H_
15
16#include <linux/platform_device.h>
17
18/*
19 * GPIO Registers.
20 */
21#define WM8350_GPIO_DEBOUNCE 0x80
22#define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
23#define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
24#define WM8350_GPIO_INT_MODE 0x83
25#define WM8350_GPIO_CONTROL 0x85
26#define WM8350_GPIO_CONFIGURATION_I_O 0x86
27#define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
28#define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
29#define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
30#define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
31#define WM8350_GPIO_FUNCTION_SELECT_4 0x8F
32
33/*
34 * GPIO Functions
35 */
36#define WM8350_GPIO0_GPIO_IN 0x0
37#define WM8350_GPIO0_GPIO_OUT 0x0
38#define WM8350_GPIO0_PWR_ON_IN 0x1
39#define WM8350_GPIO0_PWR_ON_OUT 0x1
40#define WM8350_GPIO0_LDO_EN_IN 0x2
41#define WM8350_GPIO0_VRTC_OUT 0x2
42#define WM8350_GPIO0_LPWR1_IN 0x3
43#define WM8350_GPIO0_POR_B_OUT 0x3
44
45#define WM8350_GPIO1_GPIO_IN 0x0
46#define WM8350_GPIO1_GPIO_OUT 0x0
47#define WM8350_GPIO1_PWR_ON_IN 0x1
48#define WM8350_GPIO1_DO_CONF_OUT 0x1
49#define WM8350_GPIO1_LDO_EN_IN 0x2
50#define WM8350_GPIO1_RESET_OUT 0x2
51#define WM8350_GPIO1_LPWR2_IN 0x3
52#define WM8350_GPIO1_MEMRST_OUT 0x3
53
54#define WM8350_GPIO2_GPIO_IN 0x0
55#define WM8350_GPIO2_GPIO_OUT 0x0
56#define WM8350_GPIO2_PWR_ON_IN 0x1
57#define WM8350_GPIO2_PWR_ON_OUT 0x1
58#define WM8350_GPIO2_WAKE_UP_IN 0x2
59#define WM8350_GPIO2_VRTC_OUT 0x2
60#define WM8350_GPIO2_32KHZ_IN 0x3
61#define WM8350_GPIO2_32KHZ_OUT 0x3
62
63#define WM8350_GPIO3_GPIO_IN 0x0
64#define WM8350_GPIO3_GPIO_OUT 0x0
65#define WM8350_GPIO3_PWR_ON_IN 0x1
66#define WM8350_GPIO3_P_CLK_OUT 0x1
67#define WM8350_GPIO3_LDO_EN_IN 0x2
68#define WM8350_GPIO3_VRTC_OUT 0x2
69#define WM8350_GPIO3_PWR_OFF_IN 0x3
70#define WM8350_GPIO3_32KHZ_OUT 0x3
71
72#define WM8350_GPIO4_GPIO_IN 0x0
73#define WM8350_GPIO4_GPIO_OUT 0x0
74#define WM8350_GPIO4_MR_IN 0x1
75#define WM8350_GPIO4_MEM_RST_OUT 0x1
76#define WM8350_GPIO4_FLASH_IN 0x2
77#define WM8350_GPIO4_ADA_OUT 0x2
78#define WM8350_GPIO4_HIBERNATE_IN 0x3
79#define WM8350_GPIO4_FLASH_OUT 0x3
80#define WM8350_GPIO4_MICDET_OUT 0x4
81#define WM8350_GPIO4_MICSHT_OUT 0x5
82
83#define WM8350_GPIO5_GPIO_IN 0x0
84#define WM8350_GPIO5_GPIO_OUT 0x0
85#define WM8350_GPIO5_LPWR1_IN 0x1
86#define WM8350_GPIO5_P_CLK_OUT 0x1
87#define WM8350_GPIO5_ADCLRCLK_IN 0x2
88#define WM8350_GPIO5_ADCLRCLK_OUT 0x2
89#define WM8350_GPIO5_HIBERNATE_IN 0x3
90#define WM8350_GPIO5_32KHZ_OUT 0x3
91#define WM8350_GPIO5_MICDET_OUT 0x4
92#define WM8350_GPIO5_MICSHT_OUT 0x5
93#define WM8350_GPIO5_ADA_OUT 0x6
94#define WM8350_GPIO5_OPCLK_OUT 0x7
95
96#define WM8350_GPIO6_GPIO_IN 0x0
97#define WM8350_GPIO6_GPIO_OUT 0x0
98#define WM8350_GPIO6_LPWR2_IN 0x1
99#define WM8350_GPIO6_MEMRST_OUT 0x1
100#define WM8350_GPIO6_FLASH_IN 0x2
101#define WM8350_GPIO6_ADA_OUT 0x2
102#define WM8350_GPIO6_HIBERNATE_IN 0x3
103#define WM8350_GPIO6_RTC_OUT 0x3
104#define WM8350_GPIO6_MICDET_OUT 0x4
105#define WM8350_GPIO6_MICSHT_OUT 0x5
106#define WM8350_GPIO6_ADCLRCLKB_OUT 0x6
107#define WM8350_GPIO6_SDOUT_OUT 0x7
108
109#define WM8350_GPIO7_GPIO_IN 0x0
110#define WM8350_GPIO7_GPIO_OUT 0x0
111#define WM8350_GPIO7_LPWR3_IN 0x1
112#define WM8350_GPIO7_P_CLK_OUT 0x1
113#define WM8350_GPIO7_MASK_IN 0x2
114#define WM8350_GPIO7_VCC_FAULT_OUT 0x2
115#define WM8350_GPIO7_HIBERNATE_IN 0x3
116#define WM8350_GPIO7_BATT_FAULT_OUT 0x3
117#define WM8350_GPIO7_MICDET_OUT 0x4
118#define WM8350_GPIO7_MICSHT_OUT 0x5
119#define WM8350_GPIO7_ADA_OUT 0x6
120#define WM8350_GPIO7_CSB_IN 0x7
121
122#define WM8350_GPIO8_GPIO_IN 0x0
123#define WM8350_GPIO8_GPIO_OUT 0x0
124#define WM8350_GPIO8_MR_IN 0x1
125#define WM8350_GPIO8_VCC_FAULT_OUT 0x1
126#define WM8350_GPIO8_ADCBCLK_IN 0x2
127#define WM8350_GPIO8_ADCBCLK_OUT 0x2
128#define WM8350_GPIO8_PWR_OFF_IN 0x3
129#define WM8350_GPIO8_BATT_FAULT_OUT 0x3
130#define WM8350_GPIO8_ALTSCL_IN 0xf
131
132#define WM8350_GPIO9_GPIO_IN 0x0
133#define WM8350_GPIO9_GPIO_OUT 0x0
134#define WM8350_GPIO9_HEARTBEAT_IN 0x1
135#define WM8350_GPIO9_VCC_FAULT_OUT 0x1
136#define WM8350_GPIO9_MASK_IN 0x2
137#define WM8350_GPIO9_LINE_GT_BATT_OUT 0x2
138#define WM8350_GPIO9_PWR_OFF_IN 0x3
139#define WM8350_GPIO9_BATT_FAULT_OUT 0x3
140#define WM8350_GPIO9_ALTSDA_OUT 0xf
141
142#define WM8350_GPIO10_GPIO_IN 0x0
143#define WM8350_GPIO10_GPIO_OUT 0x0
144#define WM8350_GPIO10_ISINKC_OUT 0x1
145#define WM8350_GPIO10_PWR_OFF_IN 0x2
146#define WM8350_GPIO10_LINE_GT_BATT_OUT 0x2
147#define WM8350_GPIO10_CHD_IND_IN 0x3
148
149#define WM8350_GPIO11_GPIO_IN 0x0
150#define WM8350_GPIO11_GPIO_OUT 0x0
151#define WM8350_GPIO11_ISINKD_OUT 0x1
152#define WM8350_GPIO11_WAKEUP_IN 0x2
153#define WM8350_GPIO11_LINE_GT_BATT_OUT 0x2
154#define WM8350_GPIO11_CHD_IND_IN 0x3
155
156#define WM8350_GPIO12_GPIO_IN 0x0
157#define WM8350_GPIO12_GPIO_OUT 0x0
158#define WM8350_GPIO12_ISINKE_OUT 0x1
159#define WM8350_GPIO12_LINE_GT_BATT_OUT 0x2
160#define WM8350_GPIO12_LINE_EN_OUT 0x3
161#define WM8350_GPIO12_32KHZ_OUT 0x4
162
163#define WM8350_GPIO_DIR_IN 0
164#define WM8350_GPIO_DIR_OUT 1
165#define WM8350_GPIO_ACTIVE_LOW 0
166#define WM8350_GPIO_ACTIVE_HIGH 1
167#define WM8350_GPIO_PULL_NONE 0
168#define WM8350_GPIO_PULL_UP 1
169#define WM8350_GPIO_PULL_DOWN 2
170#define WM8350_GPIO_INVERT_OFF 0
171#define WM8350_GPIO_INVERT_ON 1
172#define WM8350_GPIO_DEBOUNCE_OFF 0
173#define WM8350_GPIO_DEBOUNCE_ON 1
174
175/*
176 * R128 (0x80) - GPIO Debounce
177 */
178#define WM8350_GP12_DB 0x1000
179#define WM8350_GP11_DB 0x0800
180#define WM8350_GP10_DB 0x0400
181#define WM8350_GP9_DB 0x0200
182#define WM8350_GP8_DB 0x0100
183#define WM8350_GP7_DB 0x0080
184#define WM8350_GP6_DB 0x0040
185#define WM8350_GP5_DB 0x0020
186#define WM8350_GP4_DB 0x0010
187#define WM8350_GP3_DB 0x0008
188#define WM8350_GP2_DB 0x0004
189#define WM8350_GP1_DB 0x0002
190#define WM8350_GP0_DB 0x0001
191
192/*
193 * R129 (0x81) - GPIO Pin pull up Control
194 */
195#define WM8350_GP12_PU 0x1000
196#define WM8350_GP11_PU 0x0800
197#define WM8350_GP10_PU 0x0400
198#define WM8350_GP9_PU 0x0200
199#define WM8350_GP8_PU 0x0100
200#define WM8350_GP7_PU 0x0080
201#define WM8350_GP6_PU 0x0040
202#define WM8350_GP5_PU 0x0020
203#define WM8350_GP4_PU 0x0010
204#define WM8350_GP3_PU 0x0008
205#define WM8350_GP2_PU 0x0004
206#define WM8350_GP1_PU 0x0002
207#define WM8350_GP0_PU 0x0001
208
209/*
210 * R130 (0x82) - GPIO Pull down Control
211 */
212#define WM8350_GP12_PD 0x1000
213#define WM8350_GP11_PD 0x0800
214#define WM8350_GP10_PD 0x0400
215#define WM8350_GP9_PD 0x0200
216#define WM8350_GP8_PD 0x0100
217#define WM8350_GP7_PD 0x0080
218#define WM8350_GP6_PD 0x0040
219#define WM8350_GP5_PD 0x0020
220#define WM8350_GP4_PD 0x0010
221#define WM8350_GP3_PD 0x0008
222#define WM8350_GP2_PD 0x0004
223#define WM8350_GP1_PD 0x0002
224#define WM8350_GP0_PD 0x0001
225
226/*
227 * R131 (0x83) - GPIO Interrupt Mode
228 */
229#define WM8350_GP12_INTMODE 0x1000
230#define WM8350_GP11_INTMODE 0x0800
231#define WM8350_GP10_INTMODE 0x0400
232#define WM8350_GP9_INTMODE 0x0200
233#define WM8350_GP8_INTMODE 0x0100
234#define WM8350_GP7_INTMODE 0x0080
235#define WM8350_GP6_INTMODE 0x0040
236#define WM8350_GP5_INTMODE 0x0020
237#define WM8350_GP4_INTMODE 0x0010
238#define WM8350_GP3_INTMODE 0x0008
239#define WM8350_GP2_INTMODE 0x0004
240#define WM8350_GP1_INTMODE 0x0002
241#define WM8350_GP0_INTMODE 0x0001
242
243/*
244 * R133 (0x85) - GPIO Control
245 */
246#define WM8350_GP_DBTIME_MASK 0x00C0
247
248/*
249 * R134 (0x86) - GPIO Configuration (i/o)
250 */
251#define WM8350_GP12_DIR 0x1000
252#define WM8350_GP11_DIR 0x0800
253#define WM8350_GP10_DIR 0x0400
254#define WM8350_GP9_DIR 0x0200
255#define WM8350_GP8_DIR 0x0100
256#define WM8350_GP7_DIR 0x0080
257#define WM8350_GP6_DIR 0x0040
258#define WM8350_GP5_DIR 0x0020
259#define WM8350_GP4_DIR 0x0010
260#define WM8350_GP3_DIR 0x0008
261#define WM8350_GP2_DIR 0x0004
262#define WM8350_GP1_DIR 0x0002
263#define WM8350_GP0_DIR 0x0001
264
265/*
266 * R135 (0x87) - GPIO Pin Polarity / Type
267 */
268#define WM8350_GP12_CFG 0x1000
269#define WM8350_GP11_CFG 0x0800
270#define WM8350_GP10_CFG 0x0400
271#define WM8350_GP9_CFG 0x0200
272#define WM8350_GP8_CFG 0x0100
273#define WM8350_GP7_CFG 0x0080
274#define WM8350_GP6_CFG 0x0040
275#define WM8350_GP5_CFG 0x0020
276#define WM8350_GP4_CFG 0x0010
277#define WM8350_GP3_CFG 0x0008
278#define WM8350_GP2_CFG 0x0004
279#define WM8350_GP1_CFG 0x0002
280#define WM8350_GP0_CFG 0x0001
281
282/*
283 * R140 (0x8C) - GPIO Function Select 1
284 */
285#define WM8350_GP3_FN_MASK 0xF000
286#define WM8350_GP2_FN_MASK 0x0F00
287#define WM8350_GP1_FN_MASK 0x00F0
288#define WM8350_GP0_FN_MASK 0x000F
289
290/*
291 * R141 (0x8D) - GPIO Function Select 2
292 */
293#define WM8350_GP7_FN_MASK 0xF000
294#define WM8350_GP6_FN_MASK 0x0F00
295#define WM8350_GP5_FN_MASK 0x00F0
296#define WM8350_GP4_FN_MASK 0x000F
297
298/*
299 * R142 (0x8E) - GPIO Function Select 3
300 */
301#define WM8350_GP11_FN_MASK 0xF000
302#define WM8350_GP10_FN_MASK 0x0F00
303#define WM8350_GP9_FN_MASK 0x00F0
304#define WM8350_GP8_FN_MASK 0x000F
305
306/*
307 * R143 (0x8F) - GPIO Function Select 4
308 */
309#define WM8350_GP12_FN_MASK 0x000F
310
311/*
312 * R230 (0xE6) - GPIO Pin Status
313 */
314#define WM8350_GP12_LVL 0x1000
315#define WM8350_GP11_LVL 0x0800
316#define WM8350_GP10_LVL 0x0400
317#define WM8350_GP9_LVL 0x0200
318#define WM8350_GP8_LVL 0x0100
319#define WM8350_GP7_LVL 0x0080
320#define WM8350_GP6_LVL 0x0040
321#define WM8350_GP5_LVL 0x0020
322#define WM8350_GP4_LVL 0x0010
323#define WM8350_GP3_LVL 0x0008
324#define WM8350_GP2_LVL 0x0004
325#define WM8350_GP1_LVL 0x0002
326#define WM8350_GP0_LVL 0x0001
327
328struct wm8350;
329
330int wm8350_gpio_config(struct wm8350 *wm8350, int gpio, int dir, int func,
331 int pol, int pull, int invert, int debounce);
332
333struct wm8350_gpio {
334 struct platform_device *pdev;
335};
336
337/*
338 * GPIO Interrupts
339 */
340#define WM8350_IRQ_GPIO(x) (50 + x)
341
342#endif
diff --git a/include/linux/mfd/wm8350/pmic.h b/include/linux/mfd/wm8350/pmic.h
new file mode 100644
index 000000000000..69b69e07f62f
--- /dev/null
+++ b/include/linux/mfd/wm8350/pmic.h
@@ -0,0 +1,741 @@
1/*
2 * pmic.h -- Power Managment Driver for Wolfson WM8350 PMIC
3 *
4 * Copyright 2007 Wolfson Microelectronics PLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifndef __LINUX_MFD_WM8350_PMIC_H
14#define __LINUX_MFD_WM8350_PMIC_H
15
16/*
17 * Register values.
18 */
19
20#define WM8350_CURRENT_SINK_DRIVER_A 0xAC
21#define WM8350_CSA_FLASH_CONTROL 0xAD
22#define WM8350_CURRENT_SINK_DRIVER_B 0xAE
23#define WM8350_CSB_FLASH_CONTROL 0xAF
24#define WM8350_DCDC_LDO_REQUESTED 0xB0
25#define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
26#define WM8350_DCDC_SLEEP_OPTIONS 0xB2
27#define WM8350_POWER_CHECK_COMPARATOR 0xB3
28#define WM8350_DCDC1_CONTROL 0xB4
29#define WM8350_DCDC1_TIMEOUTS 0xB5
30#define WM8350_DCDC1_LOW_POWER 0xB6
31#define WM8350_DCDC2_CONTROL 0xB7
32#define WM8350_DCDC2_TIMEOUTS 0xB8
33#define WM8350_DCDC3_CONTROL 0xBA
34#define WM8350_DCDC3_TIMEOUTS 0xBB
35#define WM8350_DCDC3_LOW_POWER 0xBC
36#define WM8350_DCDC4_CONTROL 0xBD
37#define WM8350_DCDC4_TIMEOUTS 0xBE
38#define WM8350_DCDC4_LOW_POWER 0xBF
39#define WM8350_DCDC5_CONTROL 0xC0
40#define WM8350_DCDC5_TIMEOUTS 0xC1
41#define WM8350_DCDC6_CONTROL 0xC3
42#define WM8350_DCDC6_TIMEOUTS 0xC4
43#define WM8350_DCDC6_LOW_POWER 0xC5
44#define WM8350_LIMIT_SWITCH_CONTROL 0xC7
45#define WM8350_LDO1_CONTROL 0xC8
46#define WM8350_LDO1_TIMEOUTS 0xC9
47#define WM8350_LDO1_LOW_POWER 0xCA
48#define WM8350_LDO2_CONTROL 0xCB
49#define WM8350_LDO2_TIMEOUTS 0xCC
50#define WM8350_LDO2_LOW_POWER 0xCD
51#define WM8350_LDO3_CONTROL 0xCE
52#define WM8350_LDO3_TIMEOUTS 0xCF
53#define WM8350_LDO3_LOW_POWER 0xD0
54#define WM8350_LDO4_CONTROL 0xD1
55#define WM8350_LDO4_TIMEOUTS 0xD2
56#define WM8350_LDO4_LOW_POWER 0xD3
57#define WM8350_VCC_FAULT_MASKS 0xD7
58#define WM8350_MAIN_BANDGAP_CONTROL 0xD8
59#define WM8350_OSC_CONTROL 0xD9
60#define WM8350_RTC_TICK_CONTROL 0xDA
61#define WM8350_SECURITY 0xDB
62#define WM8350_RAM_BIST_1 0xDC
63#define WM8350_DCDC_LDO_STATUS 0xE1
64#define WM8350_GPIO_PIN_STATUS 0xE6
65
66#define WM8350_DCDC1_FORCE_PWM 0xF8
67#define WM8350_DCDC3_FORCE_PWM 0xFA
68#define WM8350_DCDC4_FORCE_PWM 0xFB
69#define WM8350_DCDC6_FORCE_PWM 0xFD
70
71/*
72 * R172 (0xAC) - Current Sink Driver A
73 */
74#define WM8350_CS1_HIB_MODE 0x1000
75#define WM8350_CS1_HIB_MODE_MASK 0x1000
76#define WM8350_CS1_HIB_MODE_SHIFT 12
77#define WM8350_CS1_ISEL_MASK 0x003F
78#define WM8350_CS1_ISEL_SHIFT 0
79
80/* Bit values for R172 (0xAC) */
81#define WM8350_CS1_HIB_MODE_DISABLE 0
82#define WM8350_CS1_HIB_MODE_LEAVE 1
83
84#define WM8350_CS1_ISEL_220M 0x3F
85
86/*
87 * R173 (0xAD) - CSA Flash control
88 */
89#define WM8350_CS1_FLASH_MODE 0x8000
90#define WM8350_CS1_TRIGSRC 0x4000
91#define WM8350_CS1_DRIVE 0x2000
92#define WM8350_CS1_FLASH_DUR_MASK 0x0300
93#define WM8350_CS1_OFF_RAMP_MASK 0x0030
94#define WM8350_CS1_ON_RAMP_MASK 0x0003
95
96/*
97 * R174 (0xAE) - Current Sink Driver B
98 */
99#define WM8350_CS2_HIB_MODE 0x1000
100#define WM8350_CS2_ISEL_MASK 0x003F
101
102/*
103 * R175 (0xAF) - CSB Flash control
104 */
105#define WM8350_CS2_FLASH_MODE 0x8000
106#define WM8350_CS2_TRIGSRC 0x4000
107#define WM8350_CS2_DRIVE 0x2000
108#define WM8350_CS2_FLASH_DUR_MASK 0x0300
109#define WM8350_CS2_OFF_RAMP_MASK 0x0030
110#define WM8350_CS2_ON_RAMP_MASK 0x0003
111
112/*
113 * R176 (0xB0) - DCDC/LDO requested
114 */
115#define WM8350_LS_ENA 0x8000
116#define WM8350_LDO4_ENA 0x0800
117#define WM8350_LDO3_ENA 0x0400
118#define WM8350_LDO2_ENA 0x0200
119#define WM8350_LDO1_ENA 0x0100
120#define WM8350_DC6_ENA 0x0020
121#define WM8350_DC5_ENA 0x0010
122#define WM8350_DC4_ENA 0x0008
123#define WM8350_DC3_ENA 0x0004
124#define WM8350_DC2_ENA 0x0002
125#define WM8350_DC1_ENA 0x0001
126
127/*
128 * R177 (0xB1) - DCDC Active options
129 */
130#define WM8350_PUTO_MASK 0x3000
131#define WM8350_PWRUP_DELAY_MASK 0x0300
132#define WM8350_DC6_ACTIVE 0x0020
133#define WM8350_DC4_ACTIVE 0x0008
134#define WM8350_DC3_ACTIVE 0x0004
135#define WM8350_DC1_ACTIVE 0x0001
136
137/*
138 * R178 (0xB2) - DCDC Sleep options
139 */
140#define WM8350_DC6_SLEEP 0x0020
141#define WM8350_DC4_SLEEP 0x0008
142#define WM8350_DC3_SLEEP 0x0004
143#define WM8350_DC1_SLEEP 0x0001
144
145/*
146 * R179 (0xB3) - Power-check comparator
147 */
148#define WM8350_PCCMP_ERRACT 0x4000
149#define WM8350_PCCMP_RAIL 0x0100
150#define WM8350_PCCMP_OFF_THR_MASK 0x0070
151#define WM8350_PCCMP_ON_THR_MASK 0x0007
152
153/*
154 * R180 (0xB4) - DCDC1 Control
155 */
156#define WM8350_DC1_OPFLT 0x0400
157#define WM8350_DC1_VSEL_MASK 0x007F
158#define WM8350_DC1_VSEL_SHIFT 0
159
160/*
161 * R181 (0xB5) - DCDC1 Timeouts
162 */
163#define WM8350_DC1_ERRACT_MASK 0xC000
164#define WM8350_DC1_ERRACT_SHIFT 14
165#define WM8350_DC1_ENSLOT_MASK 0x3C00
166#define WM8350_DC1_ENSLOT_SHIFT 10
167#define WM8350_DC1_SDSLOT_MASK 0x03C0
168#define WM8350_DC1_UVTO_MASK 0x0030
169#define WM8350_DC1_SDSLOT_SHIFT 6
170
171/* Bit values for R181 (0xB5) */
172#define WM8350_DC1_ERRACT_NONE 0
173#define WM8350_DC1_ERRACT_SHUTDOWN_CONV 1
174#define WM8350_DC1_ERRACT_SHUTDOWN_SYS 2
175
176/*
177 * R182 (0xB6) - DCDC1 Low Power
178 */
179#define WM8350_DC1_HIB_MODE_MASK 0x7000
180#define WM8350_DC1_HIB_TRIG_MASK 0x0300
181#define WM8350_DC1_VIMG_MASK 0x007F
182
183/*
184 * R183 (0xB7) - DCDC2 Control
185 */
186#define WM8350_DC2_MODE 0x4000
187#define WM8350_DC2_MODE_MASK 0x4000
188#define WM8350_DC2_MODE_SHIFT 14
189#define WM8350_DC2_HIB_MODE 0x1000
190#define WM8350_DC2_HIB_MODE_MASK 0x1000
191#define WM8350_DC2_HIB_MODE_SHIFT 12
192#define WM8350_DC2_HIB_TRIG_MASK 0x0300
193#define WM8350_DC2_HIB_TRIG_SHIFT 8
194#define WM8350_DC2_ILIM 0x0040
195#define WM8350_DC2_ILIM_MASK 0x0040
196#define WM8350_DC2_ILIM_SHIFT 6
197#define WM8350_DC2_RMP_MASK 0x0018
198#define WM8350_DC2_RMP_SHIFT 3
199#define WM8350_DC2_FBSRC_MASK 0x0003
200#define WM8350_DC2_FBSRC_SHIFT 0
201
202/* Bit values for R183 (0xB7) */
203#define WM8350_DC2_MODE_BOOST 0
204#define WM8350_DC2_MODE_SWITCH 1
205
206#define WM8350_DC2_HIB_MODE_ACTIVE 1
207#define WM8350_DC2_HIB_MODE_DISABLE 0
208
209#define WM8350_DC2_HIB_TRIG_NONE 0
210#define WM8350_DC2_HIB_TRIG_LPWR1 1
211#define WM8350_DC2_HIB_TRIG_LPWR2 2
212#define WM8350_DC2_HIB_TRIG_LPWR3 3
213
214#define WM8350_DC2_ILIM_HIGH 0
215#define WM8350_DC2_ILIM_LOW 1
216
217#define WM8350_DC2_RMP_30V 0
218#define WM8350_DC2_RMP_20V 1
219#define WM8350_DC2_RMP_10V 2
220#define WM8350_DC2_RMP_5V 3
221
222#define WM8350_DC2_FBSRC_FB2 0
223#define WM8350_DC2_FBSRC_ISINKA 1
224#define WM8350_DC2_FBSRC_ISINKB 2
225#define WM8350_DC2_FBSRC_USB 3
226
227/*
228 * R184 (0xB8) - DCDC2 Timeouts
229 */
230#define WM8350_DC2_ERRACT_MASK 0xC000
231#define WM8350_DC2_ERRACT_SHIFT 14
232#define WM8350_DC2_ENSLOT_MASK 0x3C00
233#define WM8350_DC2_ENSLOT_SHIFT 10
234#define WM8350_DC2_SDSLOT_MASK 0x03C0
235#define WM8350_DC2_UVTO_MASK 0x0030
236
237/* Bit values for R184 (0xB8) */
238#define WM8350_DC2_ERRACT_NONE 0
239#define WM8350_DC2_ERRACT_SHUTDOWN_CONV 1
240#define WM8350_DC2_ERRACT_SHUTDOWN_SYS 2
241
242/*
243 * R186 (0xBA) - DCDC3 Control
244 */
245#define WM8350_DC3_OPFLT 0x0400
246#define WM8350_DC3_VSEL_MASK 0x007F
247#define WM8350_DC3_VSEL_SHIFT 0
248
249/*
250 * R187 (0xBB) - DCDC3 Timeouts
251 */
252#define WM8350_DC3_ERRACT_MASK 0xC000
253#define WM8350_DC3_ERRACT_SHIFT 14
254#define WM8350_DC3_ENSLOT_MASK 0x3C00
255#define WM8350_DC3_ENSLOT_SHIFT 10
256#define WM8350_DC3_SDSLOT_MASK 0x03C0
257#define WM8350_DC3_UVTO_MASK 0x0030
258#define WM8350_DC3_SDSLOT_SHIFT 6
259
260/* Bit values for R187 (0xBB) */
261#define WM8350_DC3_ERRACT_NONE 0
262#define WM8350_DC3_ERRACT_SHUTDOWN_CONV 1
263#define WM8350_DC3_ERRACT_SHUTDOWN_SYS 2
264/*
265 * R188 (0xBC) - DCDC3 Low Power
266 */
267#define WM8350_DC3_HIB_MODE_MASK 0x7000
268#define WM8350_DC3_HIB_TRIG_MASK 0x0300
269#define WM8350_DC3_VIMG_MASK 0x007F
270
271/*
272 * R189 (0xBD) - DCDC4 Control
273 */
274#define WM8350_DC4_OPFLT 0x0400
275#define WM8350_DC4_VSEL_MASK 0x007F
276#define WM8350_DC4_VSEL_SHIFT 0
277
278/*
279 * R190 (0xBE) - DCDC4 Timeouts
280 */
281#define WM8350_DC4_ERRACT_MASK 0xC000
282#define WM8350_DC4_ERRACT_SHIFT 14
283#define WM8350_DC4_ENSLOT_MASK 0x3C00
284#define WM8350_DC4_ENSLOT_SHIFT 10
285#define WM8350_DC4_SDSLOT_MASK 0x03C0
286#define WM8350_DC4_UVTO_MASK 0x0030
287#define WM8350_DC4_SDSLOT_SHIFT 6
288
289/* Bit values for R190 (0xBE) */
290#define WM8350_DC4_ERRACT_NONE 0
291#define WM8350_DC4_ERRACT_SHUTDOWN_CONV 1
292#define WM8350_DC4_ERRACT_SHUTDOWN_SYS 2
293
294/*
295 * R191 (0xBF) - DCDC4 Low Power
296 */
297#define WM8350_DC4_HIB_MODE_MASK 0x7000
298#define WM8350_DC4_HIB_TRIG_MASK 0x0300
299#define WM8350_DC4_VIMG_MASK 0x007F
300
301/*
302 * R192 (0xC0) - DCDC5 Control
303 */
304#define WM8350_DC5_MODE 0x4000
305#define WM8350_DC5_MODE_MASK 0x4000
306#define WM8350_DC5_MODE_SHIFT 14
307#define WM8350_DC5_HIB_MODE 0x1000
308#define WM8350_DC5_HIB_MODE_MASK 0x1000
309#define WM8350_DC5_HIB_MODE_SHIFT 12
310#define WM8350_DC5_HIB_TRIG_MASK 0x0300
311#define WM8350_DC5_HIB_TRIG_SHIFT 8
312#define WM8350_DC5_ILIM 0x0040
313#define WM8350_DC5_ILIM_MASK 0x0040
314#define WM8350_DC5_ILIM_SHIFT 6
315#define WM8350_DC5_RMP_MASK 0x0018
316#define WM8350_DC5_RMP_SHIFT 3
317#define WM8350_DC5_FBSRC_MASK 0x0003
318#define WM8350_DC5_FBSRC_SHIFT 0
319
320/* Bit values for R192 (0xC0) */
321#define WM8350_DC5_MODE_BOOST 0
322#define WM8350_DC5_MODE_SWITCH 1
323
324#define WM8350_DC5_HIB_MODE_ACTIVE 1
325#define WM8350_DC5_HIB_MODE_DISABLE 0
326
327#define WM8350_DC5_HIB_TRIG_NONE 0
328#define WM8350_DC5_HIB_TRIG_LPWR1 1
329#define WM8350_DC5_HIB_TRIG_LPWR2 2
330#define WM8350_DC5_HIB_TRIG_LPWR3 3
331
332#define WM8350_DC5_ILIM_HIGH 0
333#define WM8350_DC5_ILIM_LOW 1
334
335#define WM8350_DC5_RMP_30V 0
336#define WM8350_DC5_RMP_20V 1
337#define WM8350_DC5_RMP_10V 2
338#define WM8350_DC5_RMP_5V 3
339
340#define WM8350_DC5_FBSRC_FB2 0
341#define WM8350_DC5_FBSRC_ISINKA 1
342#define WM8350_DC5_FBSRC_ISINKB 2
343#define WM8350_DC5_FBSRC_USB 3
344
345/*
346 * R193 (0xC1) - DCDC5 Timeouts
347 */
348#define WM8350_DC5_ERRACT_MASK 0xC000
349#define WM8350_DC5_ERRACT_SHIFT 14
350#define WM8350_DC5_ENSLOT_MASK 0x3C00
351#define WM8350_DC5_ENSLOT_SHIFT 10
352#define WM8350_DC5_SDSLOT_MASK 0x03C0
353#define WM8350_DC5_UVTO_MASK 0x0030
354#define WM8350_DC5_SDSLOT_SHIFT 6
355
356/* Bit values for R193 (0xC1) */
357#define WM8350_DC5_ERRACT_NONE 0
358#define WM8350_DC5_ERRACT_SHUTDOWN_CONV 1
359#define WM8350_DC5_ERRACT_SHUTDOWN_SYS 2
360
361/*
362 * R195 (0xC3) - DCDC6 Control
363 */
364#define WM8350_DC6_OPFLT 0x0400
365#define WM8350_DC6_VSEL_MASK 0x007F
366#define WM8350_DC6_VSEL_SHIFT 0
367
368/*
369 * R196 (0xC4) - DCDC6 Timeouts
370 */
371#define WM8350_DC6_ERRACT_MASK 0xC000
372#define WM8350_DC6_ERRACT_SHIFT 14
373#define WM8350_DC6_ENSLOT_MASK 0x3C00
374#define WM8350_DC6_ENSLOT_SHIFT 10
375#define WM8350_DC6_SDSLOT_MASK 0x03C0
376#define WM8350_DC6_UVTO_MASK 0x0030
377#define WM8350_DC6_SDSLOT_SHIFT 6
378
379/* Bit values for R196 (0xC4) */
380#define WM8350_DC6_ERRACT_NONE 0
381#define WM8350_DC6_ERRACT_SHUTDOWN_CONV 1
382#define WM8350_DC6_ERRACT_SHUTDOWN_SYS 2
383
384/*
385 * R197 (0xC5) - DCDC6 Low Power
386 */
387#define WM8350_DC6_HIB_MODE_MASK 0x7000
388#define WM8350_DC6_HIB_TRIG_MASK 0x0300
389#define WM8350_DC6_VIMG_MASK 0x007F
390
391/*
392 * R199 (0xC7) - Limit Switch Control
393 */
394#define WM8350_LS_ERRACT_MASK 0xC000
395#define WM8350_LS_ERRACT_SHIFT 14
396#define WM8350_LS_ENSLOT_MASK 0x3C00
397#define WM8350_LS_ENSLOT_SHIFT 10
398#define WM8350_LS_SDSLOT_MASK 0x03C0
399#define WM8350_LS_SDSLOT_SHIFT 6
400#define WM8350_LS_HIB_MODE 0x0010
401#define WM8350_LS_HIB_MODE_MASK 0x0010
402#define WM8350_LS_HIB_MODE_SHIFT 4
403#define WM8350_LS_HIB_PROT 0x0002
404#define WM8350_LS_HIB_PROT_MASK 0x0002
405#define WM8350_LS_HIB_PROT_SHIFT 1
406#define WM8350_LS_PROT 0x0001
407#define WM8350_LS_PROT_MASK 0x0001
408#define WM8350_LS_PROT_SHIFT 0
409
410/* Bit values for R199 (0xC7) */
411#define WM8350_LS_ERRACT_NONE 0
412#define WM8350_LS_ERRACT_SHUTDOWN_CONV 1
413#define WM8350_LS_ERRACT_SHUTDOWN_SYS 2
414
415/*
416 * R200 (0xC8) - LDO1 Control
417 */
418#define WM8350_LDO1_SWI 0x4000
419#define WM8350_LDO1_OPFLT 0x0400
420#define WM8350_LDO1_VSEL_MASK 0x001F
421#define WM8350_LDO1_VSEL_SHIFT 0
422
423/*
424 * R201 (0xC9) - LDO1 Timeouts
425 */
426#define WM8350_LDO1_ERRACT_MASK 0xC000
427#define WM8350_LDO1_ERRACT_SHIFT 14
428#define WM8350_LDO1_ENSLOT_MASK 0x3C00
429#define WM8350_LDO1_ENSLOT_SHIFT 10
430#define WM8350_LDO1_SDSLOT_MASK 0x03C0
431#define WM8350_LDO1_UVTO_MASK 0x0030
432#define WM8350_LDO1_SDSLOT_SHIFT 6
433
434/* Bit values for R201 (0xC9) */
435#define WM8350_LDO1_ERRACT_NONE 0
436#define WM8350_LDO1_ERRACT_SHUTDOWN_CONV 1
437#define WM8350_LDO1_ERRACT_SHUTDOWN_SYS 2
438
439/*
440 * R202 (0xCA) - LDO1 Low Power
441 */
442#define WM8350_LDO1_HIB_MODE_MASK 0x3000
443#define WM8350_LDO1_HIB_TRIG_MASK 0x0300
444#define WM8350_LDO1_VIMG_MASK 0x001F
445#define WM8350_LDO1_HIB_MODE_DIS (0x1 << 12)
446
447
448/*
449 * R203 (0xCB) - LDO2 Control
450 */
451#define WM8350_LDO2_SWI 0x4000
452#define WM8350_LDO2_OPFLT 0x0400
453#define WM8350_LDO2_VSEL_MASK 0x001F
454#define WM8350_LDO2_VSEL_SHIFT 0
455
456/*
457 * R204 (0xCC) - LDO2 Timeouts
458 */
459#define WM8350_LDO2_ERRACT_MASK 0xC000
460#define WM8350_LDO2_ERRACT_SHIFT 14
461#define WM8350_LDO2_ENSLOT_MASK 0x3C00
462#define WM8350_LDO2_ENSLOT_SHIFT 10
463#define WM8350_LDO2_SDSLOT_MASK 0x03C0
464#define WM8350_LDO2_SDSLOT_SHIFT 6
465
466/* Bit values for R204 (0xCC) */
467#define WM8350_LDO2_ERRACT_NONE 0
468#define WM8350_LDO2_ERRACT_SHUTDOWN_CONV 1
469#define WM8350_LDO2_ERRACT_SHUTDOWN_SYS 2
470
471/*
472 * R205 (0xCD) - LDO2 Low Power
473 */
474#define WM8350_LDO2_HIB_MODE_MASK 0x3000
475#define WM8350_LDO2_HIB_TRIG_MASK 0x0300
476#define WM8350_LDO2_VIMG_MASK 0x001F
477
478/*
479 * R206 (0xCE) - LDO3 Control
480 */
481#define WM8350_LDO3_SWI 0x4000
482#define WM8350_LDO3_OPFLT 0x0400
483#define WM8350_LDO3_VSEL_MASK 0x001F
484#define WM8350_LDO3_VSEL_SHIFT 0
485
486/*
487 * R207 (0xCF) - LDO3 Timeouts
488 */
489#define WM8350_LDO3_ERRACT_MASK 0xC000
490#define WM8350_LDO3_ERRACT_SHIFT 14
491#define WM8350_LDO3_ENSLOT_MASK 0x3C00
492#define WM8350_LDO3_ENSLOT_SHIFT 10
493#define WM8350_LDO3_SDSLOT_MASK 0x03C0
494#define WM8350_LDO3_UVTO_MASK 0x0030
495#define WM8350_LDO3_SDSLOT_SHIFT 6
496
497/* Bit values for R207 (0xCF) */
498#define WM8350_LDO3_ERRACT_NONE 0
499#define WM8350_LDO3_ERRACT_SHUTDOWN_CONV 1
500#define WM8350_LDO3_ERRACT_SHUTDOWN_SYS 2
501
502/*
503 * R208 (0xD0) - LDO3 Low Power
504 */
505#define WM8350_LDO3_HIB_MODE_MASK 0x3000
506#define WM8350_LDO3_HIB_TRIG_MASK 0x0300
507#define WM8350_LDO3_VIMG_MASK 0x001F
508
509/*
510 * R209 (0xD1) - LDO4 Control
511 */
512#define WM8350_LDO4_SWI 0x4000
513#define WM8350_LDO4_OPFLT 0x0400
514#define WM8350_LDO4_VSEL_MASK 0x001F
515#define WM8350_LDO4_VSEL_SHIFT 0
516
517/*
518 * R210 (0xD2) - LDO4 Timeouts
519 */
520#define WM8350_LDO4_ERRACT_MASK 0xC000
521#define WM8350_LDO4_ERRACT_SHIFT 14
522#define WM8350_LDO4_ENSLOT_MASK 0x3C00
523#define WM8350_LDO4_ENSLOT_SHIFT 10
524#define WM8350_LDO4_SDSLOT_MASK 0x03C0
525#define WM8350_LDO4_UVTO_MASK 0x0030
526#define WM8350_LDO4_SDSLOT_SHIFT 6
527
528/* Bit values for R210 (0xD2) */
529#define WM8350_LDO4_ERRACT_NONE 0
530#define WM8350_LDO4_ERRACT_SHUTDOWN_CONV 1
531#define WM8350_LDO4_ERRACT_SHUTDOWN_SYS 2
532
533/*
534 * R211 (0xD3) - LDO4 Low Power
535 */
536#define WM8350_LDO4_HIB_MODE_MASK 0x3000
537#define WM8350_LDO4_HIB_TRIG_MASK 0x0300
538#define WM8350_LDO4_VIMG_MASK 0x001F
539
540/*
541 * R215 (0xD7) - VCC_FAULT Masks
542 */
543#define WM8350_LS_FAULT 0x8000
544#define WM8350_LDO4_FAULT 0x0800
545#define WM8350_LDO3_FAULT 0x0400
546#define WM8350_LDO2_FAULT 0x0200
547#define WM8350_LDO1_FAULT 0x0100
548#define WM8350_DC6_FAULT 0x0020
549#define WM8350_DC5_FAULT 0x0010
550#define WM8350_DC4_FAULT 0x0008
551#define WM8350_DC3_FAULT 0x0004
552#define WM8350_DC2_FAULT 0x0002
553#define WM8350_DC1_FAULT 0x0001
554
555/*
556 * R216 (0xD8) - Main Bandgap Control
557 */
558#define WM8350_MBG_LOAD_FUSES 0x8000
559#define WM8350_MBG_FUSE_WPREP 0x4000
560#define WM8350_MBG_FUSE_WRITE 0x2000
561#define WM8350_MBG_FUSE_TRIM_MASK 0x1F00
562#define WM8350_MBG_TRIM_SRC 0x0020
563#define WM8350_MBG_USER_TRIM_MASK 0x001F
564
565/*
566 * R217 (0xD9) - OSC Control
567 */
568#define WM8350_OSC_LOAD_FUSES 0x8000
569#define WM8350_OSC_FUSE_WPREP 0x4000
570#define WM8350_OSC_FUSE_WRITE 0x2000
571#define WM8350_OSC_FUSE_TRIM_MASK 0x0F00
572#define WM8350_OSC_TRIM_SRC 0x0020
573#define WM8350_OSC_USER_TRIM_MASK 0x000F
574
575/*
576 * R248 (0xF8) - DCDC1 Force PWM
577 */
578#define WM8350_DCDC1_FORCE_PWM_ENA 0x0010
579
580/*
581 * R250 (0xFA) - DCDC3 Force PWM
582 */
583#define WM8350_DCDC3_FORCE_PWM_ENA 0x0010
584
585/*
586 * R251 (0xFB) - DCDC4 Force PWM
587 */
588#define WM8350_DCDC4_FORCE_PWM_ENA 0x0010
589
590/*
591 * R253 (0xFD) - DCDC1 Force PWM
592 */
593#define WM8350_DCDC6_FORCE_PWM_ENA 0x0010
594
595/*
596 * DCDC's
597 */
598#define WM8350_DCDC_1 0
599#define WM8350_DCDC_2 1
600#define WM8350_DCDC_3 2
601#define WM8350_DCDC_4 3
602#define WM8350_DCDC_5 4
603#define WM8350_DCDC_6 5
604
605/* DCDC modes */
606#define WM8350_DCDC_ACTIVE_STANDBY 0
607#define WM8350_DCDC_ACTIVE_PULSE 1
608#define WM8350_DCDC_SLEEP_NORMAL 0
609#define WM8350_DCDC_SLEEP_LOW 1
610
611/* DCDC Low power (Hibernate) mode */
612#define WM8350_DCDC_HIB_MODE_CUR (0 << 12)
613#define WM8350_DCDC_HIB_MODE_IMAGE (1 << 12)
614#define WM8350_DCDC_HIB_MODE_STANDBY (2 << 12)
615#define WM8350_DCDC_HIB_MODE_LDO (4 << 12)
616#define WM8350_DCDC_HIB_MODE_LDO_IM (5 << 12)
617#define WM8350_DCDC_HIB_MODE_DIS (7 << 12)
618#define WM8350_DCDC_HIB_MODE_MASK (7 << 12)
619
620/* DCDC Low Power (Hibernate) signal */
621#define WM8350_DCDC_HIB_SIG_REG (0 << 8)
622#define WM8350_DCDC_HIB_SIG_LPWR1 (1 << 8)
623#define WM8350_DCDC_HIB_SIG_LPWR2 (2 << 8)
624#define WM8350_DCDC_HIB_SIG_LPWR3 (3 << 8)
625
626/* LDO Low power (Hibernate) mode */
627#define WM8350_LDO_HIB_MODE_IMAGE (0 << 0)
628#define WM8350_LDO_HIB_MODE_DIS (1 << 0)
629
630/* LDO Low Power (Hibernate) signal */
631#define WM8350_LDO_HIB_SIG_REG (0 << 8)
632#define WM8350_LDO_HIB_SIG_LPWR1 (1 << 8)
633#define WM8350_LDO_HIB_SIG_LPWR2 (2 << 8)
634#define WM8350_LDO_HIB_SIG_LPWR3 (3 << 8)
635
636/*
637 * LDOs
638 */
639#define WM8350_LDO_1 6
640#define WM8350_LDO_2 7
641#define WM8350_LDO_3 8
642#define WM8350_LDO_4 9
643
644/*
645 * ISINKs
646 */
647#define WM8350_ISINK_A 10
648#define WM8350_ISINK_B 11
649
650#define WM8350_ISINK_MODE_BOOST 0
651#define WM8350_ISINK_MODE_SWITCH 1
652#define WM8350_ISINK_ILIM_NORMAL 0
653#define WM8350_ISINK_ILIM_LOW 1
654
655#define WM8350_ISINK_FLASH_DISABLE 0
656#define WM8350_ISINK_FLASH_ENABLE 1
657#define WM8350_ISINK_FLASH_TRIG_BIT 0
658#define WM8350_ISINK_FLASH_TRIG_GPIO 1
659#define WM8350_ISINK_FLASH_MODE_EN (1 << 13)
660#define WM8350_ISINK_FLASH_MODE_DIS (0 << 13)
661#define WM8350_ISINK_FLASH_DUR_32MS (0 << 8)
662#define WM8350_ISINK_FLASH_DUR_64MS (1 << 8)
663#define WM8350_ISINK_FLASH_DUR_96MS (2 << 8)
664#define WM8350_ISINK_FLASH_DUR_1024MS (3 << 8)
665#define WM8350_ISINK_FLASH_ON_INSTANT (0 << 4)
666#define WM8350_ISINK_FLASH_ON_0_25S (1 << 4)
667#define WM8350_ISINK_FLASH_ON_0_50S (2 << 4)
668#define WM8350_ISINK_FLASH_ON_1_00S (3 << 4)
669#define WM8350_ISINK_FLASH_ON_1_95S (1 << 4)
670#define WM8350_ISINK_FLASH_ON_3_91S (2 << 4)
671#define WM8350_ISINK_FLASH_ON_7_80S (3 << 4)
672#define WM8350_ISINK_FLASH_OFF_INSTANT (0 << 0)
673#define WM8350_ISINK_FLASH_OFF_0_25S (1 << 0)
674#define WM8350_ISINK_FLASH_OFF_0_50S (2 << 0)
675#define WM8350_ISINK_FLASH_OFF_1_00S (3 << 0)
676#define WM8350_ISINK_FLASH_OFF_1_95S (1 << 0)
677#define WM8350_ISINK_FLASH_OFF_3_91S (2 << 0)
678#define WM8350_ISINK_FLASH_OFF_7_80S (3 << 0)
679
680/*
681 * Regulator Interrupts.
682 */
683#define WM8350_IRQ_CS1 13
684#define WM8350_IRQ_CS2 14
685#define WM8350_IRQ_UV_LDO4 25
686#define WM8350_IRQ_UV_LDO3 26
687#define WM8350_IRQ_UV_LDO2 27
688#define WM8350_IRQ_UV_LDO1 28
689#define WM8350_IRQ_UV_DC6 29
690#define WM8350_IRQ_UV_DC5 30
691#define WM8350_IRQ_UV_DC4 31
692#define WM8350_IRQ_UV_DC3 32
693#define WM8350_IRQ_UV_DC2 33
694#define WM8350_IRQ_UV_DC1 34
695#define WM8350_IRQ_OC_LS 35
696
697#define NUM_WM8350_REGULATORS 12
698
699struct wm8350;
700struct platform_device;
701struct regulator_init_data;
702
703struct wm8350_pmic {
704 /* ISINK to DCDC mapping */
705 int isink_A_dcdc;
706 int isink_B_dcdc;
707
708 /* hibernate configs */
709 u16 dcdc1_hib_mode;
710 u16 dcdc3_hib_mode;
711 u16 dcdc4_hib_mode;
712 u16 dcdc6_hib_mode;
713
714 /* regulator devices */
715 struct platform_device *pdev[NUM_WM8350_REGULATORS];
716};
717
718int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
719 struct regulator_init_data *initdata);
720
721/*
722 * Additional DCDC control not supported via regulator API
723 */
724int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
725 u16 stop, u16 fault);
726int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
727 u16 ilim, u16 ramp, u16 feedback);
728
729/*
730 * Additional LDO control not supported via regulator API
731 */
732int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop);
733
734/*
735 * Additional ISINK control not supported via regulator API
736 */
737int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
738 u16 trigger, u16 duration, u16 on_ramp,
739 u16 off_ramp, u16 drive);
740
741#endif
diff --git a/include/linux/mfd/wm8350/rtc.h b/include/linux/mfd/wm8350/rtc.h
new file mode 100644
index 000000000000..dfda69e9f440
--- /dev/null
+++ b/include/linux/mfd/wm8350/rtc.h
@@ -0,0 +1,266 @@
1/*
2 * rtc.h -- RTC driver for Wolfson WM8350 PMIC
3 *
4 * Copyright 2007 Wolfson Microelectronics PLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __LINUX_MFD_WM8350_RTC_H
13#define __LINUX_MFD_WM8350_RTC_H
14
15#include <linux/platform_device.h>
16
17/*
18 * Register values.
19 */
20#define WM8350_RTC_SECONDS_MINUTES 0x10
21#define WM8350_RTC_HOURS_DAY 0x11
22#define WM8350_RTC_DATE_MONTH 0x12
23#define WM8350_RTC_YEAR 0x13
24#define WM8350_ALARM_SECONDS_MINUTES 0x14
25#define WM8350_ALARM_HOURS_DAY 0x15
26#define WM8350_ALARM_DATE_MONTH 0x16
27#define WM8350_RTC_TIME_CONTROL 0x17
28
29/*
30 * R16 (0x10) - RTC Seconds/Minutes
31 */
32#define WM8350_RTC_MINS_MASK 0x7F00
33#define WM8350_RTC_MINS_SHIFT 8
34#define WM8350_RTC_SECS_MASK 0x007F
35#define WM8350_RTC_SECS_SHIFT 0
36
37/*
38 * R17 (0x11) - RTC Hours/Day
39 */
40#define WM8350_RTC_DAY_MASK 0x0700
41#define WM8350_RTC_DAY_SHIFT 8
42#define WM8350_RTC_HPM_MASK 0x0020
43#define WM8350_RTC_HPM_SHIFT 5
44#define WM8350_RTC_HRS_MASK 0x001F
45#define WM8350_RTC_HRS_SHIFT 0
46
47/* Bit values for R21 (0x15) */
48#define WM8350_RTC_DAY_SUN 1
49#define WM8350_RTC_DAY_MON 2
50#define WM8350_RTC_DAY_TUE 3
51#define WM8350_RTC_DAY_WED 4
52#define WM8350_RTC_DAY_THU 5
53#define WM8350_RTC_DAY_FRI 6
54#define WM8350_RTC_DAY_SAT 7
55
56#define WM8350_RTC_HPM_AM 0
57#define WM8350_RTC_HPM_PM 1
58
59/*
60 * R18 (0x12) - RTC Date/Month
61 */
62#define WM8350_RTC_MTH_MASK 0x1F00
63#define WM8350_RTC_MTH_SHIFT 8
64#define WM8350_RTC_DATE_MASK 0x003F
65#define WM8350_RTC_DATE_SHIFT 0
66
67/* Bit values for R22 (0x16) */
68#define WM8350_RTC_MTH_JAN 1
69#define WM8350_RTC_MTH_FEB 2
70#define WM8350_RTC_MTH_MAR 3
71#define WM8350_RTC_MTH_APR 4
72#define WM8350_RTC_MTH_MAY 5
73#define WM8350_RTC_MTH_JUN 6
74#define WM8350_RTC_MTH_JUL 7
75#define WM8350_RTC_MTH_AUG 8
76#define WM8350_RTC_MTH_SEP 9
77#define WM8350_RTC_MTH_OCT 10
78#define WM8350_RTC_MTH_NOV 11
79#define WM8350_RTC_MTH_DEC 12
80#define WM8350_RTC_MTH_JAN_BCD 0x01
81#define WM8350_RTC_MTH_FEB_BCD 0x02
82#define WM8350_RTC_MTH_MAR_BCD 0x03
83#define WM8350_RTC_MTH_APR_BCD 0x04
84#define WM8350_RTC_MTH_MAY_BCD 0x05
85#define WM8350_RTC_MTH_JUN_BCD 0x06
86#define WM8350_RTC_MTH_JUL_BCD 0x07
87#define WM8350_RTC_MTH_AUG_BCD 0x08
88#define WM8350_RTC_MTH_SEP_BCD 0x09
89#define WM8350_RTC_MTH_OCT_BCD 0x10
90#define WM8350_RTC_MTH_NOV_BCD 0x11
91#define WM8350_RTC_MTH_DEC_BCD 0x12
92
93/*
94 * R19 (0x13) - RTC Year
95 */
96#define WM8350_RTC_YHUNDREDS_MASK 0x3F00
97#define WM8350_RTC_YHUNDREDS_SHIFT 8
98#define WM8350_RTC_YUNITS_MASK 0x00FF
99#define WM8350_RTC_YUNITS_SHIFT 0
100
101/*
102 * R20 (0x14) - Alarm Seconds/Minutes
103 */
104#define WM8350_RTC_ALMMINS_MASK 0x7F00
105#define WM8350_RTC_ALMMINS_SHIFT 8
106#define WM8350_RTC_ALMSECS_MASK 0x007F
107#define WM8350_RTC_ALMSECS_SHIFT 0
108
109/* Bit values for R20 (0x14) */
110#define WM8350_RTC_ALMMINS_DONT_CARE -1
111#define WM8350_RTC_ALMSECS_DONT_CARE -1
112
113/*
114 * R21 (0x15) - Alarm Hours/Day
115 */
116#define WM8350_RTC_ALMDAY_MASK 0x0F00
117#define WM8350_RTC_ALMDAY_SHIFT 8
118#define WM8350_RTC_ALMHPM_MASK 0x0020
119#define WM8350_RTC_ALMHPM_SHIFT 5
120#define WM8350_RTC_ALMHRS_MASK 0x001F
121#define WM8350_RTC_ALMHRS_SHIFT 0
122
123/* Bit values for R21 (0x15) */
124#define WM8350_RTC_ALMDAY_DONT_CARE -1
125#define WM8350_RTC_ALMDAY_SUN 1
126#define WM8350_RTC_ALMDAY_MON 2
127#define WM8350_RTC_ALMDAY_TUE 3
128#define WM8350_RTC_ALMDAY_WED 4
129#define WM8350_RTC_ALMDAY_THU 5
130#define WM8350_RTC_ALMDAY_FRI 6
131#define WM8350_RTC_ALMDAY_SAT 7
132
133#define WM8350_RTC_ALMHPM_AM 0
134#define WM8350_RTC_ALMHPM_PM 1
135
136#define WM8350_RTC_ALMHRS_DONT_CARE -1
137
138/*
139 * R22 (0x16) - Alarm Date/Month
140 */
141#define WM8350_RTC_ALMMTH_MASK 0x1F00
142#define WM8350_RTC_ALMMTH_SHIFT 8
143#define WM8350_RTC_ALMDATE_MASK 0x003F
144#define WM8350_RTC_ALMDATE_SHIFT 0
145
146/* Bit values for R22 (0x16) */
147#define WM8350_RTC_ALMDATE_DONT_CARE -1
148
149#define WM8350_RTC_ALMMTH_DONT_CARE -1
150#define WM8350_RTC_ALMMTH_JAN 1
151#define WM8350_RTC_ALMMTH_FEB 2
152#define WM8350_RTC_ALMMTH_MAR 3
153#define WM8350_RTC_ALMMTH_APR 4
154#define WM8350_RTC_ALMMTH_MAY 5
155#define WM8350_RTC_ALMMTH_JUN 6
156#define WM8350_RTC_ALMMTH_JUL 7
157#define WM8350_RTC_ALMMTH_AUG 8
158#define WM8350_RTC_ALMMTH_SEP 9
159#define WM8350_RTC_ALMMTH_OCT 10
160#define WM8350_RTC_ALMMTH_NOV 11
161#define WM8350_RTC_ALMMTH_DEC 12
162#define WM8350_RTC_ALMMTH_JAN_BCD 0x01
163#define WM8350_RTC_ALMMTH_FEB_BCD 0x02
164#define WM8350_RTC_ALMMTH_MAR_BCD 0x03
165#define WM8350_RTC_ALMMTH_APR_BCD 0x04
166#define WM8350_RTC_ALMMTH_MAY_BCD 0x05
167#define WM8350_RTC_ALMMTH_JUN_BCD 0x06
168#define WM8350_RTC_ALMMTH_JUL_BCD 0x07
169#define WM8350_RTC_ALMMTH_AUG_BCD 0x08
170#define WM8350_RTC_ALMMTH_SEP_BCD 0x09
171#define WM8350_RTC_ALMMTH_OCT_BCD 0x10
172#define WM8350_RTC_ALMMTH_NOV_BCD 0x11
173#define WM8350_RTC_ALMMTH_DEC_BCD 0x12
174
175/*
176 * R23 (0x17) - RTC Time Control
177 */
178#define WM8350_RTC_BCD 0x8000
179#define WM8350_RTC_BCD_MASK 0x8000
180#define WM8350_RTC_BCD_SHIFT 15
181#define WM8350_RTC_12HR 0x4000
182#define WM8350_RTC_12HR_MASK 0x4000
183#define WM8350_RTC_12HR_SHIFT 14
184#define WM8350_RTC_DST 0x2000
185#define WM8350_RTC_DST_MASK 0x2000
186#define WM8350_RTC_DST_SHIFT 13
187#define WM8350_RTC_SET 0x0800
188#define WM8350_RTC_SET_MASK 0x0800
189#define WM8350_RTC_SET_SHIFT 11
190#define WM8350_RTC_STS 0x0400
191#define WM8350_RTC_STS_MASK 0x0400
192#define WM8350_RTC_STS_SHIFT 10
193#define WM8350_RTC_ALMSET 0x0200
194#define WM8350_RTC_ALMSET_MASK 0x0200
195#define WM8350_RTC_ALMSET_SHIFT 9
196#define WM8350_RTC_ALMSTS 0x0100
197#define WM8350_RTC_ALMSTS_MASK 0x0100
198#define WM8350_RTC_ALMSTS_SHIFT 8
199#define WM8350_RTC_PINT 0x0070
200#define WM8350_RTC_PINT_MASK 0x0070
201#define WM8350_RTC_PINT_SHIFT 4
202#define WM8350_RTC_DSW 0x000F
203#define WM8350_RTC_DSW_MASK 0x000F
204#define WM8350_RTC_DSW_SHIFT 0
205
206/* Bit values for R23 (0x17) */
207#define WM8350_RTC_BCD_BINARY 0
208#define WM8350_RTC_BCD_BCD 1
209
210#define WM8350_RTC_12HR_24HR 0
211#define WM8350_RTC_12HR_12HR 1
212
213#define WM8350_RTC_DST_DISABLED 0
214#define WM8350_RTC_DST_ENABLED 1
215
216#define WM8350_RTC_SET_RUN 0
217#define WM8350_RTC_SET_SET 1
218
219#define WM8350_RTC_STS_RUNNING 0
220#define WM8350_RTC_STS_STOPPED 1
221
222#define WM8350_RTC_ALMSET_RUN 0
223#define WM8350_RTC_ALMSET_SET 1
224
225#define WM8350_RTC_ALMSTS_RUNNING 0
226#define WM8350_RTC_ALMSTS_STOPPED 1
227
228#define WM8350_RTC_PINT_DISABLED 0
229#define WM8350_RTC_PINT_SECS 1
230#define WM8350_RTC_PINT_MINS 2
231#define WM8350_RTC_PINT_HRS 3
232#define WM8350_RTC_PINT_DAYS 4
233#define WM8350_RTC_PINT_MTHS 5
234
235#define WM8350_RTC_DSW_DISABLED 0
236#define WM8350_RTC_DSW_1HZ 1
237#define WM8350_RTC_DSW_2HZ 2
238#define WM8350_RTC_DSW_4HZ 3
239#define WM8350_RTC_DSW_8HZ 4
240#define WM8350_RTC_DSW_16HZ 5
241#define WM8350_RTC_DSW_32HZ 6
242#define WM8350_RTC_DSW_64HZ 7
243#define WM8350_RTC_DSW_128HZ 8
244#define WM8350_RTC_DSW_256HZ 9
245#define WM8350_RTC_DSW_512HZ 10
246#define WM8350_RTC_DSW_1024HZ 11
247
248/*
249 * R218 (0xDA) - RTC Tick Control
250 */
251#define WM8350_RTC_TICKSTS 0x4000
252#define WM8350_RTC_CLKSRC 0x2000
253#define WM8350_RTC_TRIM_MASK 0x03FF
254
255/*
256 * RTC Interrupts.
257 */
258#define WM8350_IRQ_RTC_PER 7
259#define WM8350_IRQ_RTC_SEC 8
260#define WM8350_IRQ_RTC_ALM 9
261
262struct wm8350_rtc {
263 struct platform_device *pdev;
264};
265
266#endif
diff --git a/include/linux/mfd/wm8350/supply.h b/include/linux/mfd/wm8350/supply.h
new file mode 100644
index 000000000000..1c8f3cde79b0
--- /dev/null
+++ b/include/linux/mfd/wm8350/supply.h
@@ -0,0 +1,111 @@
1/*
2 * supply.h -- Power Supply Driver for Wolfson WM8350 PMIC
3 *
4 * Copyright 2007 Wolfson Microelectronics PLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifndef __LINUX_MFD_WM8350_SUPPLY_H_
14#define __LINUX_MFD_WM8350_SUPPLY_H_
15
16#include <linux/platform_device.h>
17
18/*
19 * Charger registers
20 */
21#define WM8350_BATTERY_CHARGER_CONTROL_1 0xA8
22#define WM8350_BATTERY_CHARGER_CONTROL_2 0xA9
23#define WM8350_BATTERY_CHARGER_CONTROL_3 0xAA
24
25/*
26 * R168 (0xA8) - Battery Charger Control 1
27 */
28#define WM8350_CHG_ENA_R168 0x8000
29#define WM8350_CHG_THR 0x2000
30#define WM8350_CHG_EOC_SEL_MASK 0x1C00
31#define WM8350_CHG_TRICKLE_TEMP_CHOKE 0x0200
32#define WM8350_CHG_TRICKLE_USB_CHOKE 0x0100
33#define WM8350_CHG_RECOVER_T 0x0080
34#define WM8350_CHG_END_ACT 0x0040
35#define WM8350_CHG_FAST 0x0020
36#define WM8350_CHG_FAST_USB_THROTTLE 0x0010
37#define WM8350_CHG_NTC_MON 0x0008
38#define WM8350_CHG_BATT_HOT_MON 0x0004
39#define WM8350_CHG_BATT_COLD_MON 0x0002
40#define WM8350_CHG_CHIP_TEMP_MON 0x0001
41
42/*
43 * R169 (0xA9) - Battery Charger Control 2
44 */
45#define WM8350_CHG_ACTIVE 0x8000
46#define WM8350_CHG_PAUSE 0x4000
47#define WM8350_CHG_STS_MASK 0x3000
48#define WM8350_CHG_TIME_MASK 0x0F00
49#define WM8350_CHG_MASK_WALL_FB 0x0080
50#define WM8350_CHG_TRICKLE_SEL 0x0040
51#define WM8350_CHG_VSEL_MASK 0x0030
52#define WM8350_CHG_ISEL_MASK 0x000F
53#define WM8350_CHG_STS_OFF 0x0000
54#define WM8350_CHG_STS_TRICKLE 0x1000
55#define WM8350_CHG_STS_FAST 0x2000
56
57/*
58 * R170 (0xAA) - Battery Charger Control 3
59 */
60#define WM8350_CHG_THROTTLE_T_MASK 0x0060
61#define WM8350_CHG_SMART 0x0010
62#define WM8350_CHG_TIMER_ADJT_MASK 0x000F
63
64/*
65 * Charger Interrupts
66 */
67#define WM8350_IRQ_CHG_BAT_HOT 0
68#define WM8350_IRQ_CHG_BAT_COLD 1
69#define WM8350_IRQ_CHG_BAT_FAIL 2
70#define WM8350_IRQ_CHG_TO 3
71#define WM8350_IRQ_CHG_END 4
72#define WM8350_IRQ_CHG_START 5
73#define WM8350_IRQ_CHG_FAST_RDY 6
74#define WM8350_IRQ_CHG_VBATT_LT_3P9 10
75#define WM8350_IRQ_CHG_VBATT_LT_3P1 11
76#define WM8350_IRQ_CHG_VBATT_LT_2P85 12
77
78/*
79 * Charger Policy
80 */
81#define WM8350_CHG_TRICKLE_50mA (0 << 6)
82#define WM8350_CHG_TRICKLE_100mA (1 << 6)
83#define WM8350_CHG_4_05V (0 << 4)
84#define WM8350_CHG_4_10V (1 << 4)
85#define WM8350_CHG_4_15V (2 << 4)
86#define WM8350_CHG_4_20V (3 << 4)
87#define WM8350_CHG_FAST_LIMIT_mA(x) ((x / 50) & 0xf)
88#define WM8350_CHG_EOC_mA(x) (((x - 10) & 0x7) << 10)
89#define WM8350_CHG_TRICKLE_3_1V (0 << 13)
90#define WM8350_CHG_TRICKLE_3_9V (1 << 13)
91
92/*
93 * Supply Registers.
94 */
95#define WM8350_USB_VOLTAGE_READBACK 0x9C
96#define WM8350_LINE_VOLTAGE_READBACK 0x9D
97#define WM8350_BATT_VOLTAGE_READBACK 0x9E
98
99/*
100 * Supply Interrupts.
101 */
102#define WM8350_IRQ_USB_LIMIT 15
103#define WM8350_IRQ_EXT_USB_FB 36
104#define WM8350_IRQ_EXT_WALL_FB 37
105#define WM8350_IRQ_EXT_BAT_FB 38
106
107struct wm8350_power {
108 struct platform_device *pdev;
109};
110
111#endif
diff --git a/include/linux/mfd/wm8350/wdt.h b/include/linux/mfd/wm8350/wdt.h
new file mode 100644
index 000000000000..f6135b5e5ef4
--- /dev/null
+++ b/include/linux/mfd/wm8350/wdt.h
@@ -0,0 +1,28 @@
1/*
2 * wdt.h -- Watchdog Driver for Wolfson WM8350 PMIC
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __LINUX_MFD_WM8350_WDT_H_
13#define __LINUX_MFD_WM8350_WDT_H_
14
15#include <linux/platform_device.h>
16
17#define WM8350_WDOG_HIB_MODE 0x0080
18#define WM8350_WDOG_DEBUG 0x0040
19#define WM8350_WDOG_MODE_MASK 0x0030
20#define WM8350_WDOG_TO_MASK 0x0007
21
22#define WM8350_IRQ_SYS_WDOG_TO 24
23
24struct wm8350_wdt {
25 struct platform_device *pdev;
26};
27
28#endif
diff --git a/include/linux/mfd/wm8400-audio.h b/include/linux/mfd/wm8400-audio.h
new file mode 100644
index 000000000000..b6640e018046
--- /dev/null
+++ b/include/linux/mfd/wm8400-audio.h
@@ -0,0 +1,1186 @@
1/*
2 * wm8400 private definitions for audio
3 *
4 * Copyright 2008 Wolfson Microelectronics plc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef __LINUX_MFD_WM8400_AUDIO_H
22#define __LINUX_MFD_WM8400_AUDIO_H
23
24#include <linux/mfd/wm8400-audio.h>
25
26/*
27 * R2 (0x02) - Power Management (1)
28 */
29#define WM8400_CODEC_ENA 0x8000 /* CODEC_ENA */
30#define WM8400_CODEC_ENA_MASK 0x8000 /* CODEC_ENA */
31#define WM8400_CODEC_ENA_SHIFT 15 /* CODEC_ENA */
32#define WM8400_CODEC_ENA_WIDTH 1 /* CODEC_ENA */
33#define WM8400_SYSCLK_ENA 0x4000 /* SYSCLK_ENA */
34#define WM8400_SYSCLK_ENA_MASK 0x4000 /* SYSCLK_ENA */
35#define WM8400_SYSCLK_ENA_SHIFT 14 /* SYSCLK_ENA */
36#define WM8400_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
37#define WM8400_SPK_MIX_ENA 0x2000 /* SPK_MIX_ENA */
38#define WM8400_SPK_MIX_ENA_MASK 0x2000 /* SPK_MIX_ENA */
39#define WM8400_SPK_MIX_ENA_SHIFT 13 /* SPK_MIX_ENA */
40#define WM8400_SPK_MIX_ENA_WIDTH 1 /* SPK_MIX_ENA */
41#define WM8400_SPK_ENA 0x1000 /* SPK_ENA */
42#define WM8400_SPK_ENA_MASK 0x1000 /* SPK_ENA */
43#define WM8400_SPK_ENA_SHIFT 12 /* SPK_ENA */
44#define WM8400_SPK_ENA_WIDTH 1 /* SPK_ENA */
45#define WM8400_OUT3_ENA 0x0800 /* OUT3_ENA */
46#define WM8400_OUT3_ENA_MASK 0x0800 /* OUT3_ENA */
47#define WM8400_OUT3_ENA_SHIFT 11 /* OUT3_ENA */
48#define WM8400_OUT3_ENA_WIDTH 1 /* OUT3_ENA */
49#define WM8400_OUT4_ENA 0x0400 /* OUT4_ENA */
50#define WM8400_OUT4_ENA_MASK 0x0400 /* OUT4_ENA */
51#define WM8400_OUT4_ENA_SHIFT 10 /* OUT4_ENA */
52#define WM8400_OUT4_ENA_WIDTH 1 /* OUT4_ENA */
53#define WM8400_LOUT_ENA 0x0200 /* LOUT_ENA */
54#define WM8400_LOUT_ENA_MASK 0x0200 /* LOUT_ENA */
55#define WM8400_LOUT_ENA_SHIFT 9 /* LOUT_ENA */
56#define WM8400_LOUT_ENA_WIDTH 1 /* LOUT_ENA */
57#define WM8400_ROUT_ENA 0x0100 /* ROUT_ENA */
58#define WM8400_ROUT_ENA_MASK 0x0100 /* ROUT_ENA */
59#define WM8400_ROUT_ENA_SHIFT 8 /* ROUT_ENA */
60#define WM8400_ROUT_ENA_WIDTH 1 /* ROUT_ENA */
61#define WM8400_MIC1BIAS_ENA 0x0010 /* MIC1BIAS_ENA */
62#define WM8400_MIC1BIAS_ENA_MASK 0x0010 /* MIC1BIAS_ENA */
63#define WM8400_MIC1BIAS_ENA_SHIFT 4 /* MIC1BIAS_ENA */
64#define WM8400_MIC1BIAS_ENA_WIDTH 1 /* MIC1BIAS_ENA */
65#define WM8400_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */
66#define WM8400_VMID_MODE_SHIFT 1 /* VMID_MODE - [2:1] */
67#define WM8400_VMID_MODE_WIDTH 2 /* VMID_MODE - [2:1] */
68#define WM8400_VREF_ENA 0x0001 /* VREF_ENA */
69#define WM8400_VREF_ENA_MASK 0x0001 /* VREF_ENA */
70#define WM8400_VREF_ENA_SHIFT 0 /* VREF_ENA */
71#define WM8400_VREF_ENA_WIDTH 1 /* VREF_ENA */
72
73/*
74 * R3 (0x03) - Power Management (2)
75 */
76#define WM8400_FLL_ENA 0x8000 /* FLL_ENA */
77#define WM8400_FLL_ENA_MASK 0x8000 /* FLL_ENA */
78#define WM8400_FLL_ENA_SHIFT 15 /* FLL_ENA */
79#define WM8400_FLL_ENA_WIDTH 1 /* FLL_ENA */
80#define WM8400_TSHUT_ENA 0x4000 /* TSHUT_ENA */
81#define WM8400_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */
82#define WM8400_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */
83#define WM8400_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
84#define WM8400_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
85#define WM8400_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */
86#define WM8400_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */
87#define WM8400_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */
88#define WM8400_OPCLK_ENA 0x0800 /* OPCLK_ENA */
89#define WM8400_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
90#define WM8400_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
91#define WM8400_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
92#define WM8400_AINL_ENA 0x0200 /* AINL_ENA */
93#define WM8400_AINL_ENA_MASK 0x0200 /* AINL_ENA */
94#define WM8400_AINL_ENA_SHIFT 9 /* AINL_ENA */
95#define WM8400_AINL_ENA_WIDTH 1 /* AINL_ENA */
96#define WM8400_AINR_ENA 0x0100 /* AINR_ENA */
97#define WM8400_AINR_ENA_MASK 0x0100 /* AINR_ENA */
98#define WM8400_AINR_ENA_SHIFT 8 /* AINR_ENA */
99#define WM8400_AINR_ENA_WIDTH 1 /* AINR_ENA */
100#define WM8400_LIN34_ENA 0x0080 /* LIN34_ENA */
101#define WM8400_LIN34_ENA_MASK 0x0080 /* LIN34_ENA */
102#define WM8400_LIN34_ENA_SHIFT 7 /* LIN34_ENA */
103#define WM8400_LIN34_ENA_WIDTH 1 /* LIN34_ENA */
104#define WM8400_LIN12_ENA 0x0040 /* LIN12_ENA */
105#define WM8400_LIN12_ENA_MASK 0x0040 /* LIN12_ENA */
106#define WM8400_LIN12_ENA_SHIFT 6 /* LIN12_ENA */
107#define WM8400_LIN12_ENA_WIDTH 1 /* LIN12_ENA */
108#define WM8400_RIN34_ENA 0x0020 /* RIN34_ENA */
109#define WM8400_RIN34_ENA_MASK 0x0020 /* RIN34_ENA */
110#define WM8400_RIN34_ENA_SHIFT 5 /* RIN34_ENA */
111#define WM8400_RIN34_ENA_WIDTH 1 /* RIN34_ENA */
112#define WM8400_RIN12_ENA 0x0010 /* RIN12_ENA */
113#define WM8400_RIN12_ENA_MASK 0x0010 /* RIN12_ENA */
114#define WM8400_RIN12_ENA_SHIFT 4 /* RIN12_ENA */
115#define WM8400_RIN12_ENA_WIDTH 1 /* RIN12_ENA */
116#define WM8400_ADCL_ENA 0x0002 /* ADCL_ENA */
117#define WM8400_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
118#define WM8400_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
119#define WM8400_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
120#define WM8400_ADCR_ENA 0x0001 /* ADCR_ENA */
121#define WM8400_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
122#define WM8400_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
123#define WM8400_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
124
125/*
126 * R4 (0x04) - Power Management (3)
127 */
128#define WM8400_LON_ENA 0x2000 /* LON_ENA */
129#define WM8400_LON_ENA_MASK 0x2000 /* LON_ENA */
130#define WM8400_LON_ENA_SHIFT 13 /* LON_ENA */
131#define WM8400_LON_ENA_WIDTH 1 /* LON_ENA */
132#define WM8400_LOP_ENA 0x1000 /* LOP_ENA */
133#define WM8400_LOP_ENA_MASK 0x1000 /* LOP_ENA */
134#define WM8400_LOP_ENA_SHIFT 12 /* LOP_ENA */
135#define WM8400_LOP_ENA_WIDTH 1 /* LOP_ENA */
136#define WM8400_RON_ENA 0x0800 /* RON_ENA */
137#define WM8400_RON_ENA_MASK 0x0800 /* RON_ENA */
138#define WM8400_RON_ENA_SHIFT 11 /* RON_ENA */
139#define WM8400_RON_ENA_WIDTH 1 /* RON_ENA */
140#define WM8400_ROP_ENA 0x0400 /* ROP_ENA */
141#define WM8400_ROP_ENA_MASK 0x0400 /* ROP_ENA */
142#define WM8400_ROP_ENA_SHIFT 10 /* ROP_ENA */
143#define WM8400_ROP_ENA_WIDTH 1 /* ROP_ENA */
144#define WM8400_LOPGA_ENA 0x0080 /* LOPGA_ENA */
145#define WM8400_LOPGA_ENA_MASK 0x0080 /* LOPGA_ENA */
146#define WM8400_LOPGA_ENA_SHIFT 7 /* LOPGA_ENA */
147#define WM8400_LOPGA_ENA_WIDTH 1 /* LOPGA_ENA */
148#define WM8400_ROPGA_ENA 0x0040 /* ROPGA_ENA */
149#define WM8400_ROPGA_ENA_MASK 0x0040 /* ROPGA_ENA */
150#define WM8400_ROPGA_ENA_SHIFT 6 /* ROPGA_ENA */
151#define WM8400_ROPGA_ENA_WIDTH 1 /* ROPGA_ENA */
152#define WM8400_LOMIX_ENA 0x0020 /* LOMIX_ENA */
153#define WM8400_LOMIX_ENA_MASK 0x0020 /* LOMIX_ENA */
154#define WM8400_LOMIX_ENA_SHIFT 5 /* LOMIX_ENA */
155#define WM8400_LOMIX_ENA_WIDTH 1 /* LOMIX_ENA */
156#define WM8400_ROMIX_ENA 0x0010 /* ROMIX_ENA */
157#define WM8400_ROMIX_ENA_MASK 0x0010 /* ROMIX_ENA */
158#define WM8400_ROMIX_ENA_SHIFT 4 /* ROMIX_ENA */
159#define WM8400_ROMIX_ENA_WIDTH 1 /* ROMIX_ENA */
160#define WM8400_DACL_ENA 0x0002 /* DACL_ENA */
161#define WM8400_DACL_ENA_MASK 0x0002 /* DACL_ENA */
162#define WM8400_DACL_ENA_SHIFT 1 /* DACL_ENA */
163#define WM8400_DACL_ENA_WIDTH 1 /* DACL_ENA */
164#define WM8400_DACR_ENA 0x0001 /* DACR_ENA */
165#define WM8400_DACR_ENA_MASK 0x0001 /* DACR_ENA */
166#define WM8400_DACR_ENA_SHIFT 0 /* DACR_ENA */
167#define WM8400_DACR_ENA_WIDTH 1 /* DACR_ENA */
168
169/*
170 * R5 (0x05) - Audio Interface (1)
171 */
172#define WM8400_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */
173#define WM8400_AIFADCL_SRC_MASK 0x8000 /* AIFADCL_SRC */
174#define WM8400_AIFADCL_SRC_SHIFT 15 /* AIFADCL_SRC */
175#define WM8400_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */
176#define WM8400_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */
177#define WM8400_AIFADCR_SRC_MASK 0x4000 /* AIFADCR_SRC */
178#define WM8400_AIFADCR_SRC_SHIFT 14 /* AIFADCR_SRC */
179#define WM8400_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */
180#define WM8400_AIFADC_TDM 0x2000 /* AIFADC_TDM */
181#define WM8400_AIFADC_TDM_MASK 0x2000 /* AIFADC_TDM */
182#define WM8400_AIFADC_TDM_SHIFT 13 /* AIFADC_TDM */
183#define WM8400_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */
184#define WM8400_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */
185#define WM8400_AIFADC_TDM_CHAN_MASK 0x1000 /* AIFADC_TDM_CHAN */
186#define WM8400_AIFADC_TDM_CHAN_SHIFT 12 /* AIFADC_TDM_CHAN */
187#define WM8400_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */
188#define WM8400_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */
189#define WM8400_AIF_BCLK_INV_MASK 0x0100 /* AIF_BCLK_INV */
190#define WM8400_AIF_BCLK_INV_SHIFT 8 /* AIF_BCLK_INV */
191#define WM8400_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
192#define WM8400_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */
193#define WM8400_AIF_LRCLK_INV_MASK 0x0080 /* AIF_LRCLK_INV */
194#define WM8400_AIF_LRCLK_INV_SHIFT 7 /* AIF_LRCLK_INV */
195#define WM8400_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
196#define WM8400_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */
197#define WM8400_AIF_WL_SHIFT 5 /* AIF_WL - [6:5] */
198#define WM8400_AIF_WL_WIDTH 2 /* AIF_WL - [6:5] */
199#define WM8400_AIF_WL_16BITS (0 << 5)
200#define WM8400_AIF_WL_20BITS (1 << 5)
201#define WM8400_AIF_WL_24BITS (2 << 5)
202#define WM8400_AIF_WL_32BITS (3 << 5)
203#define WM8400_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */
204#define WM8400_AIF_FMT_SHIFT 3 /* AIF_FMT - [4:3] */
205#define WM8400_AIF_FMT_WIDTH 2 /* AIF_FMT - [4:3] */
206#define WM8400_AIF_FMT_RIGHTJ (0 << 3)
207#define WM8400_AIF_FMT_LEFTJ (1 << 3)
208#define WM8400_AIF_FMT_I2S (2 << 3)
209#define WM8400_AIF_FMT_DSP (3 << 3)
210
211/*
212 * R6 (0x06) - Audio Interface (2)
213 */
214#define WM8400_DACL_SRC 0x8000 /* DACL_SRC */
215#define WM8400_DACL_SRC_MASK 0x8000 /* DACL_SRC */
216#define WM8400_DACL_SRC_SHIFT 15 /* DACL_SRC */
217#define WM8400_DACL_SRC_WIDTH 1 /* DACL_SRC */
218#define WM8400_DACR_SRC 0x4000 /* DACR_SRC */
219#define WM8400_DACR_SRC_MASK 0x4000 /* DACR_SRC */
220#define WM8400_DACR_SRC_SHIFT 14 /* DACR_SRC */
221#define WM8400_DACR_SRC_WIDTH 1 /* DACR_SRC */
222#define WM8400_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */
223#define WM8400_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */
224#define WM8400_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */
225#define WM8400_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */
226#define WM8400_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */
227#define WM8400_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */
228#define WM8400_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */
229#define WM8400_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */
230#define WM8400_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST - [11:10] */
231#define WM8400_DAC_BOOST_SHIFT 10 /* DAC_BOOST - [11:10] */
232#define WM8400_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [11:10] */
233#define WM8400_DAC_COMP 0x0010 /* DAC_COMP */
234#define WM8400_DAC_COMP_MASK 0x0010 /* DAC_COMP */
235#define WM8400_DAC_COMP_SHIFT 4 /* DAC_COMP */
236#define WM8400_DAC_COMP_WIDTH 1 /* DAC_COMP */
237#define WM8400_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */
238#define WM8400_DAC_COMPMODE_MASK 0x0008 /* DAC_COMPMODE */
239#define WM8400_DAC_COMPMODE_SHIFT 3 /* DAC_COMPMODE */
240#define WM8400_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
241#define WM8400_ADC_COMP 0x0004 /* ADC_COMP */
242#define WM8400_ADC_COMP_MASK 0x0004 /* ADC_COMP */
243#define WM8400_ADC_COMP_SHIFT 2 /* ADC_COMP */
244#define WM8400_ADC_COMP_WIDTH 1 /* ADC_COMP */
245#define WM8400_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */
246#define WM8400_ADC_COMPMODE_MASK 0x0002 /* ADC_COMPMODE */
247#define WM8400_ADC_COMPMODE_SHIFT 1 /* ADC_COMPMODE */
248#define WM8400_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */
249#define WM8400_LOOPBACK 0x0001 /* LOOPBACK */
250#define WM8400_LOOPBACK_MASK 0x0001 /* LOOPBACK */
251#define WM8400_LOOPBACK_SHIFT 0 /* LOOPBACK */
252#define WM8400_LOOPBACK_WIDTH 1 /* LOOPBACK */
253
254/*
255 * R7 (0x07) - Clocking (1)
256 */
257#define WM8400_TOCLK_RATE 0x8000 /* TOCLK_RATE */
258#define WM8400_TOCLK_RATE_MASK 0x8000 /* TOCLK_RATE */
259#define WM8400_TOCLK_RATE_SHIFT 15 /* TOCLK_RATE */
260#define WM8400_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */
261#define WM8400_TOCLK_ENA 0x4000 /* TOCLK_ENA */
262#define WM8400_TOCLK_ENA_MASK 0x4000 /* TOCLK_ENA */
263#define WM8400_TOCLK_ENA_SHIFT 14 /* TOCLK_ENA */
264#define WM8400_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
265#define WM8400_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */
266#define WM8400_OPCLKDIV_SHIFT 9 /* OPCLKDIV - [12:9] */
267#define WM8400_OPCLKDIV_WIDTH 4 /* OPCLKDIV - [12:9] */
268#define WM8400_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */
269#define WM8400_DCLKDIV_SHIFT 6 /* DCLKDIV - [8:6] */
270#define WM8400_DCLKDIV_WIDTH 3 /* DCLKDIV - [8:6] */
271#define WM8400_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */
272#define WM8400_BCLK_DIV_SHIFT 1 /* BCLK_DIV - [4:1] */
273#define WM8400_BCLK_DIV_WIDTH 4 /* BCLK_DIV - [4:1] */
274
275/*
276 * R8 (0x08) - Clocking (2)
277 */
278#define WM8400_MCLK_SRC 0x8000 /* MCLK_SRC */
279#define WM8400_MCLK_SRC_MASK 0x8000 /* MCLK_SRC */
280#define WM8400_MCLK_SRC_SHIFT 15 /* MCLK_SRC */
281#define WM8400_MCLK_SRC_WIDTH 1 /* MCLK_SRC */
282#define WM8400_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */
283#define WM8400_SYSCLK_SRC_MASK 0x4000 /* SYSCLK_SRC */
284#define WM8400_SYSCLK_SRC_SHIFT 14 /* SYSCLK_SRC */
285#define WM8400_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
286#define WM8400_CLK_FORCE 0x2000 /* CLK_FORCE */
287#define WM8400_CLK_FORCE_MASK 0x2000 /* CLK_FORCE */
288#define WM8400_CLK_FORCE_SHIFT 13 /* CLK_FORCE */
289#define WM8400_CLK_FORCE_WIDTH 1 /* CLK_FORCE */
290#define WM8400_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */
291#define WM8400_MCLK_DIV_SHIFT 11 /* MCLK_DIV - [12:11] */
292#define WM8400_MCLK_DIV_WIDTH 2 /* MCLK_DIV - [12:11] */
293#define WM8400_MCLK_INV 0x0400 /* MCLK_INV */
294#define WM8400_MCLK_INV_MASK 0x0400 /* MCLK_INV */
295#define WM8400_MCLK_INV_SHIFT 10 /* MCLK_INV */
296#define WM8400_MCLK_INV_WIDTH 1 /* MCLK_INV */
297#define WM8400_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV - [7:5] */
298#define WM8400_ADC_CLKDIV_SHIFT 5 /* ADC_CLKDIV - [7:5] */
299#define WM8400_ADC_CLKDIV_WIDTH 3 /* ADC_CLKDIV - [7:5] */
300#define WM8400_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */
301#define WM8400_DAC_CLKDIV_SHIFT 2 /* DAC_CLKDIV - [4:2] */
302#define WM8400_DAC_CLKDIV_WIDTH 3 /* DAC_CLKDIV - [4:2] */
303
304/*
305 * R9 (0x09) - Audio Interface (3)
306 */
307#define WM8400_AIF_MSTR1 0x8000 /* AIF_MSTR1 */
308#define WM8400_AIF_MSTR1_MASK 0x8000 /* AIF_MSTR1 */
309#define WM8400_AIF_MSTR1_SHIFT 15 /* AIF_MSTR1 */
310#define WM8400_AIF_MSTR1_WIDTH 1 /* AIF_MSTR1 */
311#define WM8400_AIF_MSTR2 0x4000 /* AIF_MSTR2 */
312#define WM8400_AIF_MSTR2_MASK 0x4000 /* AIF_MSTR2 */
313#define WM8400_AIF_MSTR2_SHIFT 14 /* AIF_MSTR2 */
314#define WM8400_AIF_MSTR2_WIDTH 1 /* AIF_MSTR2 */
315#define WM8400_AIF_SEL 0x2000 /* AIF_SEL */
316#define WM8400_AIF_SEL_MASK 0x2000 /* AIF_SEL */
317#define WM8400_AIF_SEL_SHIFT 13 /* AIF_SEL */
318#define WM8400_AIF_SEL_WIDTH 1 /* AIF_SEL */
319#define WM8400_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */
320#define WM8400_ADCLRC_DIR_MASK 0x0800 /* ADCLRC_DIR */
321#define WM8400_ADCLRC_DIR_SHIFT 11 /* ADCLRC_DIR */
322#define WM8400_ADCLRC_DIR_WIDTH 1 /* ADCLRC_DIR */
323#define WM8400_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE - [10:0] */
324#define WM8400_ADCLRC_RATE_SHIFT 0 /* ADCLRC_RATE - [10:0] */
325#define WM8400_ADCLRC_RATE_WIDTH 11 /* ADCLRC_RATE - [10:0] */
326
327/*
328 * R10 (0x0A) - Audio Interface (4)
329 */
330#define WM8400_ALRCGPIO1 0x8000 /* ALRCGPIO1 */
331#define WM8400_ALRCGPIO1_MASK 0x8000 /* ALRCGPIO1 */
332#define WM8400_ALRCGPIO1_SHIFT 15 /* ALRCGPIO1 */
333#define WM8400_ALRCGPIO1_WIDTH 1 /* ALRCGPIO1 */
334#define WM8400_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */
335#define WM8400_ALRCBGPIO6_MASK 0x4000 /* ALRCBGPIO6 */
336#define WM8400_ALRCBGPIO6_SHIFT 14 /* ALRCBGPIO6 */
337#define WM8400_ALRCBGPIO6_WIDTH 1 /* ALRCBGPIO6 */
338#define WM8400_AIF_TRIS 0x2000 /* AIF_TRIS */
339#define WM8400_AIF_TRIS_MASK 0x2000 /* AIF_TRIS */
340#define WM8400_AIF_TRIS_SHIFT 13 /* AIF_TRIS */
341#define WM8400_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
342#define WM8400_DACLRC_DIR 0x0800 /* DACLRC_DIR */
343#define WM8400_DACLRC_DIR_MASK 0x0800 /* DACLRC_DIR */
344#define WM8400_DACLRC_DIR_SHIFT 11 /* DACLRC_DIR */
345#define WM8400_DACLRC_DIR_WIDTH 1 /* DACLRC_DIR */
346#define WM8400_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE - [10:0] */
347#define WM8400_DACLRC_RATE_SHIFT 0 /* DACLRC_RATE - [10:0] */
348#define WM8400_DACLRC_RATE_WIDTH 11 /* DACLRC_RATE - [10:0] */
349
350/*
351 * R11 (0x0B) - DAC CTRL
352 */
353#define WM8400_DAC_SDMCLK_RATE 0x2000 /* DAC_SDMCLK_RATE */
354#define WM8400_DAC_SDMCLK_RATE_MASK 0x2000 /* DAC_SDMCLK_RATE */
355#define WM8400_DAC_SDMCLK_RATE_SHIFT 13 /* DAC_SDMCLK_RATE */
356#define WM8400_DAC_SDMCLK_RATE_WIDTH 1 /* DAC_SDMCLK_RATE */
357#define WM8400_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */
358#define WM8400_AIF_LRCLKRATE_MASK 0x0400 /* AIF_LRCLKRATE */
359#define WM8400_AIF_LRCLKRATE_SHIFT 10 /* AIF_LRCLKRATE */
360#define WM8400_AIF_LRCLKRATE_WIDTH 1 /* AIF_LRCLKRATE */
361#define WM8400_DAC_MONO 0x0200 /* DAC_MONO */
362#define WM8400_DAC_MONO_MASK 0x0200 /* DAC_MONO */
363#define WM8400_DAC_MONO_SHIFT 9 /* DAC_MONO */
364#define WM8400_DAC_MONO_WIDTH 1 /* DAC_MONO */
365#define WM8400_DAC_SB_FILT 0x0100 /* DAC_SB_FILT */
366#define WM8400_DAC_SB_FILT_MASK 0x0100 /* DAC_SB_FILT */
367#define WM8400_DAC_SB_FILT_SHIFT 8 /* DAC_SB_FILT */
368#define WM8400_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */
369#define WM8400_DAC_MUTERATE 0x0080 /* DAC_MUTERATE */
370#define WM8400_DAC_MUTERATE_MASK 0x0080 /* DAC_MUTERATE */
371#define WM8400_DAC_MUTERATE_SHIFT 7 /* DAC_MUTERATE */
372#define WM8400_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
373#define WM8400_DAC_MUTEMODE 0x0040 /* DAC_MUTEMODE */
374#define WM8400_DAC_MUTEMODE_MASK 0x0040 /* DAC_MUTEMODE */
375#define WM8400_DAC_MUTEMODE_SHIFT 6 /* DAC_MUTEMODE */
376#define WM8400_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */
377#define WM8400_DEEMP_MASK 0x0030 /* DEEMP - [5:4] */
378#define WM8400_DEEMP_SHIFT 4 /* DEEMP - [5:4] */
379#define WM8400_DEEMP_WIDTH 2 /* DEEMP - [5:4] */
380#define WM8400_DAC_MUTE 0x0004 /* DAC_MUTE */
381#define WM8400_DAC_MUTE_MASK 0x0004 /* DAC_MUTE */
382#define WM8400_DAC_MUTE_SHIFT 2 /* DAC_MUTE */
383#define WM8400_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
384#define WM8400_DACL_DATINV 0x0002 /* DACL_DATINV */
385#define WM8400_DACL_DATINV_MASK 0x0002 /* DACL_DATINV */
386#define WM8400_DACL_DATINV_SHIFT 1 /* DACL_DATINV */
387#define WM8400_DACL_DATINV_WIDTH 1 /* DACL_DATINV */
388#define WM8400_DACR_DATINV 0x0001 /* DACR_DATINV */
389#define WM8400_DACR_DATINV_MASK 0x0001 /* DACR_DATINV */
390#define WM8400_DACR_DATINV_SHIFT 0 /* DACR_DATINV */
391#define WM8400_DACR_DATINV_WIDTH 1 /* DACR_DATINV */
392
393/*
394 * R12 (0x0C) - Left DAC Digital Volume
395 */
396#define WM8400_DAC_VU 0x0100 /* DAC_VU */
397#define WM8400_DAC_VU_MASK 0x0100 /* DAC_VU */
398#define WM8400_DAC_VU_SHIFT 8 /* DAC_VU */
399#define WM8400_DAC_VU_WIDTH 1 /* DAC_VU */
400#define WM8400_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
401#define WM8400_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */
402#define WM8400_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */
403
404/*
405 * R13 (0x0D) - Right DAC Digital Volume
406 */
407#define WM8400_DAC_VU 0x0100 /* DAC_VU */
408#define WM8400_DAC_VU_MASK 0x0100 /* DAC_VU */
409#define WM8400_DAC_VU_SHIFT 8 /* DAC_VU */
410#define WM8400_DAC_VU_WIDTH 1 /* DAC_VU */
411#define WM8400_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
412#define WM8400_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */
413#define WM8400_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */
414
415/*
416 * R14 (0x0E) - Digital Side Tone
417 */
418#define WM8400_ADCL_DAC_SVOL_MASK 0x1E00 /* ADCL_DAC_SVOL - [12:9] */
419#define WM8400_ADCL_DAC_SVOL_SHIFT 9 /* ADCL_DAC_SVOL - [12:9] */
420#define WM8400_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [12:9] */
421#define WM8400_ADCR_DAC_SVOL_MASK 0x01E0 /* ADCR_DAC_SVOL - [8:5] */
422#define WM8400_ADCR_DAC_SVOL_SHIFT 5 /* ADCR_DAC_SVOL - [8:5] */
423#define WM8400_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [8:5] */
424#define WM8400_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */
425#define WM8400_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */
426#define WM8400_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */
427#define WM8400_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */
428#define WM8400_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */
429#define WM8400_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */
430
431/*
432 * R15 (0x0F) - ADC CTRL
433 */
434#define WM8400_ADC_HPF_ENA 0x0100 /* ADC_HPF_ENA */
435#define WM8400_ADC_HPF_ENA_MASK 0x0100 /* ADC_HPF_ENA */
436#define WM8400_ADC_HPF_ENA_SHIFT 8 /* ADC_HPF_ENA */
437#define WM8400_ADC_HPF_ENA_WIDTH 1 /* ADC_HPF_ENA */
438#define WM8400_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */
439#define WM8400_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */
440#define WM8400_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */
441#define WM8400_ADCL_DATINV 0x0002 /* ADCL_DATINV */
442#define WM8400_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */
443#define WM8400_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */
444#define WM8400_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */
445#define WM8400_ADCR_DATINV 0x0001 /* ADCR_DATINV */
446#define WM8400_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */
447#define WM8400_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */
448#define WM8400_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */
449
450/*
451 * R16 (0x10) - Left ADC Digital Volume
452 */
453#define WM8400_ADC_VU 0x0100 /* ADC_VU */
454#define WM8400_ADC_VU_MASK 0x0100 /* ADC_VU */
455#define WM8400_ADC_VU_SHIFT 8 /* ADC_VU */
456#define WM8400_ADC_VU_WIDTH 1 /* ADC_VU */
457#define WM8400_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
458#define WM8400_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */
459#define WM8400_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */
460
461/*
462 * R17 (0x11) - Right ADC Digital Volume
463 */
464#define WM8400_ADC_VU 0x0100 /* ADC_VU */
465#define WM8400_ADC_VU_MASK 0x0100 /* ADC_VU */
466#define WM8400_ADC_VU_SHIFT 8 /* ADC_VU */
467#define WM8400_ADC_VU_WIDTH 1 /* ADC_VU */
468#define WM8400_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
469#define WM8400_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */
470#define WM8400_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */
471
472/*
473 * R24 (0x18) - Left Line Input 1&2 Volume
474 */
475#define WM8400_IPVU 0x0100 /* IPVU */
476#define WM8400_IPVU_MASK 0x0100 /* IPVU */
477#define WM8400_IPVU_SHIFT 8 /* IPVU */
478#define WM8400_IPVU_WIDTH 1 /* IPVU */
479#define WM8400_LI12MUTE 0x0080 /* LI12MUTE */
480#define WM8400_LI12MUTE_MASK 0x0080 /* LI12MUTE */
481#define WM8400_LI12MUTE_SHIFT 7 /* LI12MUTE */
482#define WM8400_LI12MUTE_WIDTH 1 /* LI12MUTE */
483#define WM8400_LI12ZC 0x0040 /* LI12ZC */
484#define WM8400_LI12ZC_MASK 0x0040 /* LI12ZC */
485#define WM8400_LI12ZC_SHIFT 6 /* LI12ZC */
486#define WM8400_LI12ZC_WIDTH 1 /* LI12ZC */
487#define WM8400_LIN12VOL_MASK 0x001F /* LIN12VOL - [4:0] */
488#define WM8400_LIN12VOL_SHIFT 0 /* LIN12VOL - [4:0] */
489#define WM8400_LIN12VOL_WIDTH 5 /* LIN12VOL - [4:0] */
490
491/*
492 * R25 (0x19) - Left Line Input 3&4 Volume
493 */
494#define WM8400_IPVU 0x0100 /* IPVU */
495#define WM8400_IPVU_MASK 0x0100 /* IPVU */
496#define WM8400_IPVU_SHIFT 8 /* IPVU */
497#define WM8400_IPVU_WIDTH 1 /* IPVU */
498#define WM8400_LI34MUTE 0x0080 /* LI34MUTE */
499#define WM8400_LI34MUTE_MASK 0x0080 /* LI34MUTE */
500#define WM8400_LI34MUTE_SHIFT 7 /* LI34MUTE */
501#define WM8400_LI34MUTE_WIDTH 1 /* LI34MUTE */
502#define WM8400_LI34ZC 0x0040 /* LI34ZC */
503#define WM8400_LI34ZC_MASK 0x0040 /* LI34ZC */
504#define WM8400_LI34ZC_SHIFT 6 /* LI34ZC */
505#define WM8400_LI34ZC_WIDTH 1 /* LI34ZC */
506#define WM8400_LIN34VOL_MASK 0x001F /* LIN34VOL - [4:0] */
507#define WM8400_LIN34VOL_SHIFT 0 /* LIN34VOL - [4:0] */
508#define WM8400_LIN34VOL_WIDTH 5 /* LIN34VOL - [4:0] */
509
510/*
511 * R26 (0x1A) - Right Line Input 1&2 Volume
512 */
513#define WM8400_IPVU 0x0100 /* IPVU */
514#define WM8400_IPVU_MASK 0x0100 /* IPVU */
515#define WM8400_IPVU_SHIFT 8 /* IPVU */
516#define WM8400_IPVU_WIDTH 1 /* IPVU */
517#define WM8400_RI12MUTE 0x0080 /* RI12MUTE */
518#define WM8400_RI12MUTE_MASK 0x0080 /* RI12MUTE */
519#define WM8400_RI12MUTE_SHIFT 7 /* RI12MUTE */
520#define WM8400_RI12MUTE_WIDTH 1 /* RI12MUTE */
521#define WM8400_RI12ZC 0x0040 /* RI12ZC */
522#define WM8400_RI12ZC_MASK 0x0040 /* RI12ZC */
523#define WM8400_RI12ZC_SHIFT 6 /* RI12ZC */
524#define WM8400_RI12ZC_WIDTH 1 /* RI12ZC */
525#define WM8400_RIN12VOL_MASK 0x001F /* RIN12VOL - [4:0] */
526#define WM8400_RIN12VOL_SHIFT 0 /* RIN12VOL - [4:0] */
527#define WM8400_RIN12VOL_WIDTH 5 /* RIN12VOL - [4:0] */
528
529/*
530 * R27 (0x1B) - Right Line Input 3&4 Volume
531 */
532#define WM8400_IPVU 0x0100 /* IPVU */
533#define WM8400_IPVU_MASK 0x0100 /* IPVU */
534#define WM8400_IPVU_SHIFT 8 /* IPVU */
535#define WM8400_IPVU_WIDTH 1 /* IPVU */
536#define WM8400_RI34MUTE 0x0080 /* RI34MUTE */
537#define WM8400_RI34MUTE_MASK 0x0080 /* RI34MUTE */
538#define WM8400_RI34MUTE_SHIFT 7 /* RI34MUTE */
539#define WM8400_RI34MUTE_WIDTH 1 /* RI34MUTE */
540#define WM8400_RI34ZC 0x0040 /* RI34ZC */
541#define WM8400_RI34ZC_MASK 0x0040 /* RI34ZC */
542#define WM8400_RI34ZC_SHIFT 6 /* RI34ZC */
543#define WM8400_RI34ZC_WIDTH 1 /* RI34ZC */
544#define WM8400_RIN34VOL_MASK 0x001F /* RIN34VOL - [4:0] */
545#define WM8400_RIN34VOL_SHIFT 0 /* RIN34VOL - [4:0] */
546#define WM8400_RIN34VOL_WIDTH 5 /* RIN34VOL - [4:0] */
547
548/*
549 * R28 (0x1C) - Left Output Volume
550 */
551#define WM8400_OPVU 0x0100 /* OPVU */
552#define WM8400_OPVU_MASK 0x0100 /* OPVU */
553#define WM8400_OPVU_SHIFT 8 /* OPVU */
554#define WM8400_OPVU_WIDTH 1 /* OPVU */
555#define WM8400_LOZC 0x0080 /* LOZC */
556#define WM8400_LOZC_MASK 0x0080 /* LOZC */
557#define WM8400_LOZC_SHIFT 7 /* LOZC */
558#define WM8400_LOZC_WIDTH 1 /* LOZC */
559#define WM8400_LOUTVOL_MASK 0x007F /* LOUTVOL - [6:0] */
560#define WM8400_LOUTVOL_SHIFT 0 /* LOUTVOL - [6:0] */
561#define WM8400_LOUTVOL_WIDTH 7 /* LOUTVOL - [6:0] */
562
563/*
564 * R29 (0x1D) - Right Output Volume
565 */
566#define WM8400_OPVU 0x0100 /* OPVU */
567#define WM8400_OPVU_MASK 0x0100 /* OPVU */
568#define WM8400_OPVU_SHIFT 8 /* OPVU */
569#define WM8400_OPVU_WIDTH 1 /* OPVU */
570#define WM8400_ROZC 0x0080 /* ROZC */
571#define WM8400_ROZC_MASK 0x0080 /* ROZC */
572#define WM8400_ROZC_SHIFT 7 /* ROZC */
573#define WM8400_ROZC_WIDTH 1 /* ROZC */
574#define WM8400_ROUTVOL_MASK 0x007F /* ROUTVOL - [6:0] */
575#define WM8400_ROUTVOL_SHIFT 0 /* ROUTVOL - [6:0] */
576#define WM8400_ROUTVOL_WIDTH 7 /* ROUTVOL - [6:0] */
577
578/*
579 * R30 (0x1E) - Line Outputs Volume
580 */
581#define WM8400_LONMUTE 0x0040 /* LONMUTE */
582#define WM8400_LONMUTE_MASK 0x0040 /* LONMUTE */
583#define WM8400_LONMUTE_SHIFT 6 /* LONMUTE */
584#define WM8400_LONMUTE_WIDTH 1 /* LONMUTE */
585#define WM8400_LOPMUTE 0x0020 /* LOPMUTE */
586#define WM8400_LOPMUTE_MASK 0x0020 /* LOPMUTE */
587#define WM8400_LOPMUTE_SHIFT 5 /* LOPMUTE */
588#define WM8400_LOPMUTE_WIDTH 1 /* LOPMUTE */
589#define WM8400_LOATTN 0x0010 /* LOATTN */
590#define WM8400_LOATTN_MASK 0x0010 /* LOATTN */
591#define WM8400_LOATTN_SHIFT 4 /* LOATTN */
592#define WM8400_LOATTN_WIDTH 1 /* LOATTN */
593#define WM8400_RONMUTE 0x0004 /* RONMUTE */
594#define WM8400_RONMUTE_MASK 0x0004 /* RONMUTE */
595#define WM8400_RONMUTE_SHIFT 2 /* RONMUTE */
596#define WM8400_RONMUTE_WIDTH 1 /* RONMUTE */
597#define WM8400_ROPMUTE 0x0002 /* ROPMUTE */
598#define WM8400_ROPMUTE_MASK 0x0002 /* ROPMUTE */
599#define WM8400_ROPMUTE_SHIFT 1 /* ROPMUTE */
600#define WM8400_ROPMUTE_WIDTH 1 /* ROPMUTE */
601#define WM8400_ROATTN 0x0001 /* ROATTN */
602#define WM8400_ROATTN_MASK 0x0001 /* ROATTN */
603#define WM8400_ROATTN_SHIFT 0 /* ROATTN */
604#define WM8400_ROATTN_WIDTH 1 /* ROATTN */
605
606/*
607 * R31 (0x1F) - Out3/4 Volume
608 */
609#define WM8400_OUT3MUTE 0x0020 /* OUT3MUTE */
610#define WM8400_OUT3MUTE_MASK 0x0020 /* OUT3MUTE */
611#define WM8400_OUT3MUTE_SHIFT 5 /* OUT3MUTE */
612#define WM8400_OUT3MUTE_WIDTH 1 /* OUT3MUTE */
613#define WM8400_OUT3ATTN 0x0010 /* OUT3ATTN */
614#define WM8400_OUT3ATTN_MASK 0x0010 /* OUT3ATTN */
615#define WM8400_OUT3ATTN_SHIFT 4 /* OUT3ATTN */
616#define WM8400_OUT3ATTN_WIDTH 1 /* OUT3ATTN */
617#define WM8400_OUT4MUTE 0x0002 /* OUT4MUTE */
618#define WM8400_OUT4MUTE_MASK 0x0002 /* OUT4MUTE */
619#define WM8400_OUT4MUTE_SHIFT 1 /* OUT4MUTE */
620#define WM8400_OUT4MUTE_WIDTH 1 /* OUT4MUTE */
621#define WM8400_OUT4ATTN 0x0001 /* OUT4ATTN */
622#define WM8400_OUT4ATTN_MASK 0x0001 /* OUT4ATTN */
623#define WM8400_OUT4ATTN_SHIFT 0 /* OUT4ATTN */
624#define WM8400_OUT4ATTN_WIDTH 1 /* OUT4ATTN */
625
626/*
627 * R32 (0x20) - Left OPGA Volume
628 */
629#define WM8400_OPVU 0x0100 /* OPVU */
630#define WM8400_OPVU_MASK 0x0100 /* OPVU */
631#define WM8400_OPVU_SHIFT 8 /* OPVU */
632#define WM8400_OPVU_WIDTH 1 /* OPVU */
633#define WM8400_LOPGAZC 0x0080 /* LOPGAZC */
634#define WM8400_LOPGAZC_MASK 0x0080 /* LOPGAZC */
635#define WM8400_LOPGAZC_SHIFT 7 /* LOPGAZC */
636#define WM8400_LOPGAZC_WIDTH 1 /* LOPGAZC */
637#define WM8400_LOPGAVOL_MASK 0x007F /* LOPGAVOL - [6:0] */
638#define WM8400_LOPGAVOL_SHIFT 0 /* LOPGAVOL - [6:0] */
639#define WM8400_LOPGAVOL_WIDTH 7 /* LOPGAVOL - [6:0] */
640
641/*
642 * R33 (0x21) - Right OPGA Volume
643 */
644#define WM8400_OPVU 0x0100 /* OPVU */
645#define WM8400_OPVU_MASK 0x0100 /* OPVU */
646#define WM8400_OPVU_SHIFT 8 /* OPVU */
647#define WM8400_OPVU_WIDTH 1 /* OPVU */
648#define WM8400_ROPGAZC 0x0080 /* ROPGAZC */
649#define WM8400_ROPGAZC_MASK 0x0080 /* ROPGAZC */
650#define WM8400_ROPGAZC_SHIFT 7 /* ROPGAZC */
651#define WM8400_ROPGAZC_WIDTH 1 /* ROPGAZC */
652#define WM8400_ROPGAVOL_MASK 0x007F /* ROPGAVOL - [6:0] */
653#define WM8400_ROPGAVOL_SHIFT 0 /* ROPGAVOL - [6:0] */
654#define WM8400_ROPGAVOL_WIDTH 7 /* ROPGAVOL - [6:0] */
655
656/*
657 * R34 (0x22) - Speaker Volume
658 */
659#define WM8400_SPKATTN_MASK 0x0003 /* SPKATTN - [1:0] */
660#define WM8400_SPKATTN_SHIFT 0 /* SPKATTN - [1:0] */
661#define WM8400_SPKATTN_WIDTH 2 /* SPKATTN - [1:0] */
662
663/*
664 * R35 (0x23) - ClassD1
665 */
666#define WM8400_CDMODE 0x0100 /* CDMODE */
667#define WM8400_CDMODE_MASK 0x0100 /* CDMODE */
668#define WM8400_CDMODE_SHIFT 8 /* CDMODE */
669#define WM8400_CDMODE_WIDTH 1 /* CDMODE */
670#define WM8400_CLASSD_CLK_SEL 0x0080 /* CLASSD_CLK_SEL */
671#define WM8400_CLASSD_CLK_SEL_MASK 0x0080 /* CLASSD_CLK_SEL */
672#define WM8400_CLASSD_CLK_SEL_SHIFT 7 /* CLASSD_CLK_SEL */
673#define WM8400_CLASSD_CLK_SEL_WIDTH 1 /* CLASSD_CLK_SEL */
674#define WM8400_CD_SRCTRL 0x0040 /* CD_SRCTRL */
675#define WM8400_CD_SRCTRL_MASK 0x0040 /* CD_SRCTRL */
676#define WM8400_CD_SRCTRL_SHIFT 6 /* CD_SRCTRL */
677#define WM8400_CD_SRCTRL_WIDTH 1 /* CD_SRCTRL */
678#define WM8400_SPKNOPOP 0x0020 /* SPKNOPOP */
679#define WM8400_SPKNOPOP_MASK 0x0020 /* SPKNOPOP */
680#define WM8400_SPKNOPOP_SHIFT 5 /* SPKNOPOP */
681#define WM8400_SPKNOPOP_WIDTH 1 /* SPKNOPOP */
682#define WM8400_DBLERATE 0x0010 /* DBLERATE */
683#define WM8400_DBLERATE_MASK 0x0010 /* DBLERATE */
684#define WM8400_DBLERATE_SHIFT 4 /* DBLERATE */
685#define WM8400_DBLERATE_WIDTH 1 /* DBLERATE */
686#define WM8400_LOOPTEST 0x0008 /* LOOPTEST */
687#define WM8400_LOOPTEST_MASK 0x0008 /* LOOPTEST */
688#define WM8400_LOOPTEST_SHIFT 3 /* LOOPTEST */
689#define WM8400_LOOPTEST_WIDTH 1 /* LOOPTEST */
690#define WM8400_HALFABBIAS 0x0004 /* HALFABBIAS */
691#define WM8400_HALFABBIAS_MASK 0x0004 /* HALFABBIAS */
692#define WM8400_HALFABBIAS_SHIFT 2 /* HALFABBIAS */
693#define WM8400_HALFABBIAS_WIDTH 1 /* HALFABBIAS */
694#define WM8400_TRIDEL_MASK 0x0003 /* TRIDEL - [1:0] */
695#define WM8400_TRIDEL_SHIFT 0 /* TRIDEL - [1:0] */
696#define WM8400_TRIDEL_WIDTH 2 /* TRIDEL - [1:0] */
697
698/*
699 * R37 (0x25) - ClassD3
700 */
701#define WM8400_DCGAIN_MASK 0x0038 /* DCGAIN - [5:3] */
702#define WM8400_DCGAIN_SHIFT 3 /* DCGAIN - [5:3] */
703#define WM8400_DCGAIN_WIDTH 3 /* DCGAIN - [5:3] */
704#define WM8400_ACGAIN_MASK 0x0007 /* ACGAIN - [2:0] */
705#define WM8400_ACGAIN_SHIFT 0 /* ACGAIN - [2:0] */
706#define WM8400_ACGAIN_WIDTH 3 /* ACGAIN - [2:0] */
707
708/*
709 * R39 (0x27) - Input Mixer1
710 */
711#define WM8400_AINLMODE_MASK 0x000C /* AINLMODE - [3:2] */
712#define WM8400_AINLMODE_SHIFT 2 /* AINLMODE - [3:2] */
713#define WM8400_AINLMODE_WIDTH 2 /* AINLMODE - [3:2] */
714#define WM8400_AINRMODE_MASK 0x0003 /* AINRMODE - [1:0] */
715#define WM8400_AINRMODE_SHIFT 0 /* AINRMODE - [1:0] */
716#define WM8400_AINRMODE_WIDTH 2 /* AINRMODE - [1:0] */
717
718/*
719 * R40 (0x28) - Input Mixer2
720 */
721#define WM8400_LMP4 0x0080 /* LMP4 */
722#define WM8400_LMP4_MASK 0x0080 /* LMP4 */
723#define WM8400_LMP4_SHIFT 7 /* LMP4 */
724#define WM8400_LMP4_WIDTH 1 /* LMP4 */
725#define WM8400_LMN3 0x0040 /* LMN3 */
726#define WM8400_LMN3_MASK 0x0040 /* LMN3 */
727#define WM8400_LMN3_SHIFT 6 /* LMN3 */
728#define WM8400_LMN3_WIDTH 1 /* LMN3 */
729#define WM8400_LMP2 0x0020 /* LMP2 */
730#define WM8400_LMP2_MASK 0x0020 /* LMP2 */
731#define WM8400_LMP2_SHIFT 5 /* LMP2 */
732#define WM8400_LMP2_WIDTH 1 /* LMP2 */
733#define WM8400_LMN1 0x0010 /* LMN1 */
734#define WM8400_LMN1_MASK 0x0010 /* LMN1 */
735#define WM8400_LMN1_SHIFT 4 /* LMN1 */
736#define WM8400_LMN1_WIDTH 1 /* LMN1 */
737#define WM8400_RMP4 0x0008 /* RMP4 */
738#define WM8400_RMP4_MASK 0x0008 /* RMP4 */
739#define WM8400_RMP4_SHIFT 3 /* RMP4 */
740#define WM8400_RMP4_WIDTH 1 /* RMP4 */
741#define WM8400_RMN3 0x0004 /* RMN3 */
742#define WM8400_RMN3_MASK 0x0004 /* RMN3 */
743#define WM8400_RMN3_SHIFT 2 /* RMN3 */
744#define WM8400_RMN3_WIDTH 1 /* RMN3 */
745#define WM8400_RMP2 0x0002 /* RMP2 */
746#define WM8400_RMP2_MASK 0x0002 /* RMP2 */
747#define WM8400_RMP2_SHIFT 1 /* RMP2 */
748#define WM8400_RMP2_WIDTH 1 /* RMP2 */
749#define WM8400_RMN1 0x0001 /* RMN1 */
750#define WM8400_RMN1_MASK 0x0001 /* RMN1 */
751#define WM8400_RMN1_SHIFT 0 /* RMN1 */
752#define WM8400_RMN1_WIDTH 1 /* RMN1 */
753
754/*
755 * R41 (0x29) - Input Mixer3
756 */
757#define WM8400_L34MNB 0x0100 /* L34MNB */
758#define WM8400_L34MNB_MASK 0x0100 /* L34MNB */
759#define WM8400_L34MNB_SHIFT 8 /* L34MNB */
760#define WM8400_L34MNB_WIDTH 1 /* L34MNB */
761#define WM8400_L34MNBST 0x0080 /* L34MNBST */
762#define WM8400_L34MNBST_MASK 0x0080 /* L34MNBST */
763#define WM8400_L34MNBST_SHIFT 7 /* L34MNBST */
764#define WM8400_L34MNBST_WIDTH 1 /* L34MNBST */
765#define WM8400_L12MNB 0x0020 /* L12MNB */
766#define WM8400_L12MNB_MASK 0x0020 /* L12MNB */
767#define WM8400_L12MNB_SHIFT 5 /* L12MNB */
768#define WM8400_L12MNB_WIDTH 1 /* L12MNB */
769#define WM8400_L12MNBST 0x0010 /* L12MNBST */
770#define WM8400_L12MNBST_MASK 0x0010 /* L12MNBST */
771#define WM8400_L12MNBST_SHIFT 4 /* L12MNBST */
772#define WM8400_L12MNBST_WIDTH 1 /* L12MNBST */
773#define WM8400_LDBVOL_MASK 0x0007 /* LDBVOL - [2:0] */
774#define WM8400_LDBVOL_SHIFT 0 /* LDBVOL - [2:0] */
775#define WM8400_LDBVOL_WIDTH 3 /* LDBVOL - [2:0] */
776
777/*
778 * R42 (0x2A) - Input Mixer4
779 */
780#define WM8400_R34MNB 0x0100 /* R34MNB */
781#define WM8400_R34MNB_MASK 0x0100 /* R34MNB */
782#define WM8400_R34MNB_SHIFT 8 /* R34MNB */
783#define WM8400_R34MNB_WIDTH 1 /* R34MNB */
784#define WM8400_R34MNBST 0x0080 /* R34MNBST */
785#define WM8400_R34MNBST_MASK 0x0080 /* R34MNBST */
786#define WM8400_R34MNBST_SHIFT 7 /* R34MNBST */
787#define WM8400_R34MNBST_WIDTH 1 /* R34MNBST */
788#define WM8400_R12MNB 0x0020 /* R12MNB */
789#define WM8400_R12MNB_MASK 0x0020 /* R12MNB */
790#define WM8400_R12MNB_SHIFT 5 /* R12MNB */
791#define WM8400_R12MNB_WIDTH 1 /* R12MNB */
792#define WM8400_R12MNBST 0x0010 /* R12MNBST */
793#define WM8400_R12MNBST_MASK 0x0010 /* R12MNBST */
794#define WM8400_R12MNBST_SHIFT 4 /* R12MNBST */
795#define WM8400_R12MNBST_WIDTH 1 /* R12MNBST */
796#define WM8400_RDBVOL_MASK 0x0007 /* RDBVOL - [2:0] */
797#define WM8400_RDBVOL_SHIFT 0 /* RDBVOL - [2:0] */
798#define WM8400_RDBVOL_WIDTH 3 /* RDBVOL - [2:0] */
799
800/*
801 * R43 (0x2B) - Input Mixer5
802 */
803#define WM8400_LI2BVOL_MASK 0x01C0 /* LI2BVOL - [8:6] */
804#define WM8400_LI2BVOL_SHIFT 6 /* LI2BVOL - [8:6] */
805#define WM8400_LI2BVOL_WIDTH 3 /* LI2BVOL - [8:6] */
806#define WM8400_LR4BVOL_MASK 0x0038 /* LR4BVOL - [5:3] */
807#define WM8400_LR4BVOL_SHIFT 3 /* LR4BVOL - [5:3] */
808#define WM8400_LR4BVOL_WIDTH 3 /* LR4BVOL - [5:3] */
809#define WM8400_LL4BVOL_MASK 0x0007 /* LL4BVOL - [2:0] */
810#define WM8400_LL4BVOL_SHIFT 0 /* LL4BVOL - [2:0] */
811#define WM8400_LL4BVOL_WIDTH 3 /* LL4BVOL - [2:0] */
812
813/*
814 * R44 (0x2C) - Input Mixer6
815 */
816#define WM8400_RI2BVOL_MASK 0x01C0 /* RI2BVOL - [8:6] */
817#define WM8400_RI2BVOL_SHIFT 6 /* RI2BVOL - [8:6] */
818#define WM8400_RI2BVOL_WIDTH 3 /* RI2BVOL - [8:6] */
819#define WM8400_RL4BVOL_MASK 0x0038 /* RL4BVOL - [5:3] */
820#define WM8400_RL4BVOL_SHIFT 3 /* RL4BVOL - [5:3] */
821#define WM8400_RL4BVOL_WIDTH 3 /* RL4BVOL - [5:3] */
822#define WM8400_RR4BVOL_MASK 0x0007 /* RR4BVOL - [2:0] */
823#define WM8400_RR4BVOL_SHIFT 0 /* RR4BVOL - [2:0] */
824#define WM8400_RR4BVOL_WIDTH 3 /* RR4BVOL - [2:0] */
825
826/*
827 * R45 (0x2D) - Output Mixer1
828 */
829#define WM8400_LRBLO 0x0080 /* LRBLO */
830#define WM8400_LRBLO_MASK 0x0080 /* LRBLO */
831#define WM8400_LRBLO_SHIFT 7 /* LRBLO */
832#define WM8400_LRBLO_WIDTH 1 /* LRBLO */
833#define WM8400_LLBLO 0x0040 /* LLBLO */
834#define WM8400_LLBLO_MASK 0x0040 /* LLBLO */
835#define WM8400_LLBLO_SHIFT 6 /* LLBLO */
836#define WM8400_LLBLO_WIDTH 1 /* LLBLO */
837#define WM8400_LRI3LO 0x0020 /* LRI3LO */
838#define WM8400_LRI3LO_MASK 0x0020 /* LRI3LO */
839#define WM8400_LRI3LO_SHIFT 5 /* LRI3LO */
840#define WM8400_LRI3LO_WIDTH 1 /* LRI3LO */
841#define WM8400_LLI3LO 0x0010 /* LLI3LO */
842#define WM8400_LLI3LO_MASK 0x0010 /* LLI3LO */
843#define WM8400_LLI3LO_SHIFT 4 /* LLI3LO */
844#define WM8400_LLI3LO_WIDTH 1 /* LLI3LO */
845#define WM8400_LR12LO 0x0008 /* LR12LO */
846#define WM8400_LR12LO_MASK 0x0008 /* LR12LO */
847#define WM8400_LR12LO_SHIFT 3 /* LR12LO */
848#define WM8400_LR12LO_WIDTH 1 /* LR12LO */
849#define WM8400_LL12LO 0x0004 /* LL12LO */
850#define WM8400_LL12LO_MASK 0x0004 /* LL12LO */
851#define WM8400_LL12LO_SHIFT 2 /* LL12LO */
852#define WM8400_LL12LO_WIDTH 1 /* LL12LO */
853#define WM8400_LDLO 0x0001 /* LDLO */
854#define WM8400_LDLO_MASK 0x0001 /* LDLO */
855#define WM8400_LDLO_SHIFT 0 /* LDLO */
856#define WM8400_LDLO_WIDTH 1 /* LDLO */
857
858/*
859 * R46 (0x2E) - Output Mixer2
860 */
861#define WM8400_RLBRO 0x0080 /* RLBRO */
862#define WM8400_RLBRO_MASK 0x0080 /* RLBRO */
863#define WM8400_RLBRO_SHIFT 7 /* RLBRO */
864#define WM8400_RLBRO_WIDTH 1 /* RLBRO */
865#define WM8400_RRBRO 0x0040 /* RRBRO */
866#define WM8400_RRBRO_MASK 0x0040 /* RRBRO */
867#define WM8400_RRBRO_SHIFT 6 /* RRBRO */
868#define WM8400_RRBRO_WIDTH 1 /* RRBRO */
869#define WM8400_RLI3RO 0x0020 /* RLI3RO */
870#define WM8400_RLI3RO_MASK 0x0020 /* RLI3RO */
871#define WM8400_RLI3RO_SHIFT 5 /* RLI3RO */
872#define WM8400_RLI3RO_WIDTH 1 /* RLI3RO */
873#define WM8400_RRI3RO 0x0010 /* RRI3RO */
874#define WM8400_RRI3RO_MASK 0x0010 /* RRI3RO */
875#define WM8400_RRI3RO_SHIFT 4 /* RRI3RO */
876#define WM8400_RRI3RO_WIDTH 1 /* RRI3RO */
877#define WM8400_RL12RO 0x0008 /* RL12RO */
878#define WM8400_RL12RO_MASK 0x0008 /* RL12RO */
879#define WM8400_RL12RO_SHIFT 3 /* RL12RO */
880#define WM8400_RL12RO_WIDTH 1 /* RL12RO */
881#define WM8400_RR12RO 0x0004 /* RR12RO */
882#define WM8400_RR12RO_MASK 0x0004 /* RR12RO */
883#define WM8400_RR12RO_SHIFT 2 /* RR12RO */
884#define WM8400_RR12RO_WIDTH 1 /* RR12RO */
885#define WM8400_RDRO 0x0001 /* RDRO */
886#define WM8400_RDRO_MASK 0x0001 /* RDRO */
887#define WM8400_RDRO_SHIFT 0 /* RDRO */
888#define WM8400_RDRO_WIDTH 1 /* RDRO */
889
890/*
891 * R47 (0x2F) - Output Mixer3
892 */
893#define WM8400_LLI3LOVOL_MASK 0x01C0 /* LLI3LOVOL - [8:6] */
894#define WM8400_LLI3LOVOL_SHIFT 6 /* LLI3LOVOL - [8:6] */
895#define WM8400_LLI3LOVOL_WIDTH 3 /* LLI3LOVOL - [8:6] */
896#define WM8400_LR12LOVOL_MASK 0x0038 /* LR12LOVOL - [5:3] */
897#define WM8400_LR12LOVOL_SHIFT 3 /* LR12LOVOL - [5:3] */
898#define WM8400_LR12LOVOL_WIDTH 3 /* LR12LOVOL - [5:3] */
899#define WM8400_LL12LOVOL_MASK 0x0007 /* LL12LOVOL - [2:0] */
900#define WM8400_LL12LOVOL_SHIFT 0 /* LL12LOVOL - [2:0] */
901#define WM8400_LL12LOVOL_WIDTH 3 /* LL12LOVOL - [2:0] */
902
903/*
904 * R48 (0x30) - Output Mixer4
905 */
906#define WM8400_RRI3ROVOL_MASK 0x01C0 /* RRI3ROVOL - [8:6] */
907#define WM8400_RRI3ROVOL_SHIFT 6 /* RRI3ROVOL - [8:6] */
908#define WM8400_RRI3ROVOL_WIDTH 3 /* RRI3ROVOL - [8:6] */
909#define WM8400_RL12ROVOL_MASK 0x0038 /* RL12ROVOL - [5:3] */
910#define WM8400_RL12ROVOL_SHIFT 3 /* RL12ROVOL - [5:3] */
911#define WM8400_RL12ROVOL_WIDTH 3 /* RL12ROVOL - [5:3] */
912#define WM8400_RR12ROVOL_MASK 0x0007 /* RR12ROVOL - [2:0] */
913#define WM8400_RR12ROVOL_SHIFT 0 /* RR12ROVOL - [2:0] */
914#define WM8400_RR12ROVOL_WIDTH 3 /* RR12ROVOL - [2:0] */
915
916/*
917 * R49 (0x31) - Output Mixer5
918 */
919#define WM8400_LRI3LOVOL_MASK 0x01C0 /* LRI3LOVOL - [8:6] */
920#define WM8400_LRI3LOVOL_SHIFT 6 /* LRI3LOVOL - [8:6] */
921#define WM8400_LRI3LOVOL_WIDTH 3 /* LRI3LOVOL - [8:6] */
922#define WM8400_LRBLOVOL_MASK 0x0038 /* LRBLOVOL - [5:3] */
923#define WM8400_LRBLOVOL_SHIFT 3 /* LRBLOVOL - [5:3] */
924#define WM8400_LRBLOVOL_WIDTH 3 /* LRBLOVOL - [5:3] */
925#define WM8400_LLBLOVOL_MASK 0x0007 /* LLBLOVOL - [2:0] */
926#define WM8400_LLBLOVOL_SHIFT 0 /* LLBLOVOL - [2:0] */
927#define WM8400_LLBLOVOL_WIDTH 3 /* LLBLOVOL - [2:0] */
928
929/*
930 * R50 (0x32) - Output Mixer6
931 */
932#define WM8400_RLI3ROVOL_MASK 0x01C0 /* RLI3ROVOL - [8:6] */
933#define WM8400_RLI3ROVOL_SHIFT 6 /* RLI3ROVOL - [8:6] */
934#define WM8400_RLI3ROVOL_WIDTH 3 /* RLI3ROVOL - [8:6] */
935#define WM8400_RLBROVOL_MASK 0x0038 /* RLBROVOL - [5:3] */
936#define WM8400_RLBROVOL_SHIFT 3 /* RLBROVOL - [5:3] */
937#define WM8400_RLBROVOL_WIDTH 3 /* RLBROVOL - [5:3] */
938#define WM8400_RRBROVOL_MASK 0x0007 /* RRBROVOL - [2:0] */
939#define WM8400_RRBROVOL_SHIFT 0 /* RRBROVOL - [2:0] */
940#define WM8400_RRBROVOL_WIDTH 3 /* RRBROVOL - [2:0] */
941
942/*
943 * R51 (0x33) - Out3/4 Mixer
944 */
945#define WM8400_VSEL_MASK 0x0180 /* VSEL - [8:7] */
946#define WM8400_VSEL_SHIFT 7 /* VSEL - [8:7] */
947#define WM8400_VSEL_WIDTH 2 /* VSEL - [8:7] */
948#define WM8400_LI4O3 0x0020 /* LI4O3 */
949#define WM8400_LI4O3_MASK 0x0020 /* LI4O3 */
950#define WM8400_LI4O3_SHIFT 5 /* LI4O3 */
951#define WM8400_LI4O3_WIDTH 1 /* LI4O3 */
952#define WM8400_LPGAO3 0x0010 /* LPGAO3 */
953#define WM8400_LPGAO3_MASK 0x0010 /* LPGAO3 */
954#define WM8400_LPGAO3_SHIFT 4 /* LPGAO3 */
955#define WM8400_LPGAO3_WIDTH 1 /* LPGAO3 */
956#define WM8400_RI4O4 0x0002 /* RI4O4 */
957#define WM8400_RI4O4_MASK 0x0002 /* RI4O4 */
958#define WM8400_RI4O4_SHIFT 1 /* RI4O4 */
959#define WM8400_RI4O4_WIDTH 1 /* RI4O4 */
960#define WM8400_RPGAO4 0x0001 /* RPGAO4 */
961#define WM8400_RPGAO4_MASK 0x0001 /* RPGAO4 */
962#define WM8400_RPGAO4_SHIFT 0 /* RPGAO4 */
963#define WM8400_RPGAO4_WIDTH 1 /* RPGAO4 */
964
965/*
966 * R52 (0x34) - Line Mixer1
967 */
968#define WM8400_LLOPGALON 0x0040 /* LLOPGALON */
969#define WM8400_LLOPGALON_MASK 0x0040 /* LLOPGALON */
970#define WM8400_LLOPGALON_SHIFT 6 /* LLOPGALON */
971#define WM8400_LLOPGALON_WIDTH 1 /* LLOPGALON */
972#define WM8400_LROPGALON 0x0020 /* LROPGALON */
973#define WM8400_LROPGALON_MASK 0x0020 /* LROPGALON */
974#define WM8400_LROPGALON_SHIFT 5 /* LROPGALON */
975#define WM8400_LROPGALON_WIDTH 1 /* LROPGALON */
976#define WM8400_LOPLON 0x0010 /* LOPLON */
977#define WM8400_LOPLON_MASK 0x0010 /* LOPLON */
978#define WM8400_LOPLON_SHIFT 4 /* LOPLON */
979#define WM8400_LOPLON_WIDTH 1 /* LOPLON */
980#define WM8400_LR12LOP 0x0004 /* LR12LOP */
981#define WM8400_LR12LOP_MASK 0x0004 /* LR12LOP */
982#define WM8400_LR12LOP_SHIFT 2 /* LR12LOP */
983#define WM8400_LR12LOP_WIDTH 1 /* LR12LOP */
984#define WM8400_LL12LOP 0x0002 /* LL12LOP */
985#define WM8400_LL12LOP_MASK 0x0002 /* LL12LOP */
986#define WM8400_LL12LOP_SHIFT 1 /* LL12LOP */
987#define WM8400_LL12LOP_WIDTH 1 /* LL12LOP */
988#define WM8400_LLOPGALOP 0x0001 /* LLOPGALOP */
989#define WM8400_LLOPGALOP_MASK 0x0001 /* LLOPGALOP */
990#define WM8400_LLOPGALOP_SHIFT 0 /* LLOPGALOP */
991#define WM8400_LLOPGALOP_WIDTH 1 /* LLOPGALOP */
992
993/*
994 * R53 (0x35) - Line Mixer2
995 */
996#define WM8400_RROPGARON 0x0040 /* RROPGARON */
997#define WM8400_RROPGARON_MASK 0x0040 /* RROPGARON */
998#define WM8400_RROPGARON_SHIFT 6 /* RROPGARON */
999#define WM8400_RROPGARON_WIDTH 1 /* RROPGARON */
1000#define WM8400_RLOPGARON 0x0020 /* RLOPGARON */
1001#define WM8400_RLOPGARON_MASK 0x0020 /* RLOPGARON */
1002#define WM8400_RLOPGARON_SHIFT 5 /* RLOPGARON */
1003#define WM8400_RLOPGARON_WIDTH 1 /* RLOPGARON */
1004#define WM8400_ROPRON 0x0010 /* ROPRON */
1005#define WM8400_ROPRON_MASK 0x0010 /* ROPRON */
1006#define WM8400_ROPRON_SHIFT 4 /* ROPRON */
1007#define WM8400_ROPRON_WIDTH 1 /* ROPRON */
1008#define WM8400_RL12ROP 0x0004 /* RL12ROP */
1009#define WM8400_RL12ROP_MASK 0x0004 /* RL12ROP */
1010#define WM8400_RL12ROP_SHIFT 2 /* RL12ROP */
1011#define WM8400_RL12ROP_WIDTH 1 /* RL12ROP */
1012#define WM8400_RR12ROP 0x0002 /* RR12ROP */
1013#define WM8400_RR12ROP_MASK 0x0002 /* RR12ROP */
1014#define WM8400_RR12ROP_SHIFT 1 /* RR12ROP */
1015#define WM8400_RR12ROP_WIDTH 1 /* RR12ROP */
1016#define WM8400_RROPGAROP 0x0001 /* RROPGAROP */
1017#define WM8400_RROPGAROP_MASK 0x0001 /* RROPGAROP */
1018#define WM8400_RROPGAROP_SHIFT 0 /* RROPGAROP */
1019#define WM8400_RROPGAROP_WIDTH 1 /* RROPGAROP */
1020
1021/*
1022 * R54 (0x36) - Speaker Mixer
1023 */
1024#define WM8400_LB2SPK 0x0080 /* LB2SPK */
1025#define WM8400_LB2SPK_MASK 0x0080 /* LB2SPK */
1026#define WM8400_LB2SPK_SHIFT 7 /* LB2SPK */
1027#define WM8400_LB2SPK_WIDTH 1 /* LB2SPK */
1028#define WM8400_RB2SPK 0x0040 /* RB2SPK */
1029#define WM8400_RB2SPK_MASK 0x0040 /* RB2SPK */
1030#define WM8400_RB2SPK_SHIFT 6 /* RB2SPK */
1031#define WM8400_RB2SPK_WIDTH 1 /* RB2SPK */
1032#define WM8400_LI2SPK 0x0020 /* LI2SPK */
1033#define WM8400_LI2SPK_MASK 0x0020 /* LI2SPK */
1034#define WM8400_LI2SPK_SHIFT 5 /* LI2SPK */
1035#define WM8400_LI2SPK_WIDTH 1 /* LI2SPK */
1036#define WM8400_RI2SPK 0x0010 /* RI2SPK */
1037#define WM8400_RI2SPK_MASK 0x0010 /* RI2SPK */
1038#define WM8400_RI2SPK_SHIFT 4 /* RI2SPK */
1039#define WM8400_RI2SPK_WIDTH 1 /* RI2SPK */
1040#define WM8400_LOPGASPK 0x0008 /* LOPGASPK */
1041#define WM8400_LOPGASPK_MASK 0x0008 /* LOPGASPK */
1042#define WM8400_LOPGASPK_SHIFT 3 /* LOPGASPK */
1043#define WM8400_LOPGASPK_WIDTH 1 /* LOPGASPK */
1044#define WM8400_ROPGASPK 0x0004 /* ROPGASPK */
1045#define WM8400_ROPGASPK_MASK 0x0004 /* ROPGASPK */
1046#define WM8400_ROPGASPK_SHIFT 2 /* ROPGASPK */
1047#define WM8400_ROPGASPK_WIDTH 1 /* ROPGASPK */
1048#define WM8400_LDSPK 0x0002 /* LDSPK */
1049#define WM8400_LDSPK_MASK 0x0002 /* LDSPK */
1050#define WM8400_LDSPK_SHIFT 1 /* LDSPK */
1051#define WM8400_LDSPK_WIDTH 1 /* LDSPK */
1052#define WM8400_RDSPK 0x0001 /* RDSPK */
1053#define WM8400_RDSPK_MASK 0x0001 /* RDSPK */
1054#define WM8400_RDSPK_SHIFT 0 /* RDSPK */
1055#define WM8400_RDSPK_WIDTH 1 /* RDSPK */
1056
1057/*
1058 * R55 (0x37) - Additional Control
1059 */
1060#define WM8400_VROI 0x0001 /* VROI */
1061#define WM8400_VROI_MASK 0x0001 /* VROI */
1062#define WM8400_VROI_SHIFT 0 /* VROI */
1063#define WM8400_VROI_WIDTH 1 /* VROI */
1064
1065/*
1066 * R56 (0x38) - AntiPOP1
1067 */
1068#define WM8400_DIS_LLINE 0x0020 /* DIS_LLINE */
1069#define WM8400_DIS_LLINE_MASK 0x0020 /* DIS_LLINE */
1070#define WM8400_DIS_LLINE_SHIFT 5 /* DIS_LLINE */
1071#define WM8400_DIS_LLINE_WIDTH 1 /* DIS_LLINE */
1072#define WM8400_DIS_RLINE 0x0010 /* DIS_RLINE */
1073#define WM8400_DIS_RLINE_MASK 0x0010 /* DIS_RLINE */
1074#define WM8400_DIS_RLINE_SHIFT 4 /* DIS_RLINE */
1075#define WM8400_DIS_RLINE_WIDTH 1 /* DIS_RLINE */
1076#define WM8400_DIS_OUT3 0x0008 /* DIS_OUT3 */
1077#define WM8400_DIS_OUT3_MASK 0x0008 /* DIS_OUT3 */
1078#define WM8400_DIS_OUT3_SHIFT 3 /* DIS_OUT3 */
1079#define WM8400_DIS_OUT3_WIDTH 1 /* DIS_OUT3 */
1080#define WM8400_DIS_OUT4 0x0004 /* DIS_OUT4 */
1081#define WM8400_DIS_OUT4_MASK 0x0004 /* DIS_OUT4 */
1082#define WM8400_DIS_OUT4_SHIFT 2 /* DIS_OUT4 */
1083#define WM8400_DIS_OUT4_WIDTH 1 /* DIS_OUT4 */
1084#define WM8400_DIS_LOUT 0x0002 /* DIS_LOUT */
1085#define WM8400_DIS_LOUT_MASK 0x0002 /* DIS_LOUT */
1086#define WM8400_DIS_LOUT_SHIFT 1 /* DIS_LOUT */
1087#define WM8400_DIS_LOUT_WIDTH 1 /* DIS_LOUT */
1088#define WM8400_DIS_ROUT 0x0001 /* DIS_ROUT */
1089#define WM8400_DIS_ROUT_MASK 0x0001 /* DIS_ROUT */
1090#define WM8400_DIS_ROUT_SHIFT 0 /* DIS_ROUT */
1091#define WM8400_DIS_ROUT_WIDTH 1 /* DIS_ROUT */
1092
1093/*
1094 * R57 (0x39) - AntiPOP2
1095 */
1096#define WM8400_SOFTST 0x0040 /* SOFTST */
1097#define WM8400_SOFTST_MASK 0x0040 /* SOFTST */
1098#define WM8400_SOFTST_SHIFT 6 /* SOFTST */
1099#define WM8400_SOFTST_WIDTH 1 /* SOFTST */
1100#define WM8400_BUFIOEN 0x0008 /* BUFIOEN */
1101#define WM8400_BUFIOEN_MASK 0x0008 /* BUFIOEN */
1102#define WM8400_BUFIOEN_SHIFT 3 /* BUFIOEN */
1103#define WM8400_BUFIOEN_WIDTH 1 /* BUFIOEN */
1104#define WM8400_BUFDCOPEN 0x0004 /* BUFDCOPEN */
1105#define WM8400_BUFDCOPEN_MASK 0x0004 /* BUFDCOPEN */
1106#define WM8400_BUFDCOPEN_SHIFT 2 /* BUFDCOPEN */
1107#define WM8400_BUFDCOPEN_WIDTH 1 /* BUFDCOPEN */
1108#define WM8400_POBCTRL 0x0002 /* POBCTRL */
1109#define WM8400_POBCTRL_MASK 0x0002 /* POBCTRL */
1110#define WM8400_POBCTRL_SHIFT 1 /* POBCTRL */
1111#define WM8400_POBCTRL_WIDTH 1 /* POBCTRL */
1112#define WM8400_VMIDTOG 0x0001 /* VMIDTOG */
1113#define WM8400_VMIDTOG_MASK 0x0001 /* VMIDTOG */
1114#define WM8400_VMIDTOG_SHIFT 0 /* VMIDTOG */
1115#define WM8400_VMIDTOG_WIDTH 1 /* VMIDTOG */
1116
1117/*
1118 * R58 (0x3A) - MICBIAS
1119 */
1120#define WM8400_MCDSCTH_MASK 0x00C0 /* MCDSCTH - [7:6] */
1121#define WM8400_MCDSCTH_SHIFT 6 /* MCDSCTH - [7:6] */
1122#define WM8400_MCDSCTH_WIDTH 2 /* MCDSCTH - [7:6] */
1123#define WM8400_MCDTHR_MASK 0x0038 /* MCDTHR - [5:3] */
1124#define WM8400_MCDTHR_SHIFT 3 /* MCDTHR - [5:3] */
1125#define WM8400_MCDTHR_WIDTH 3 /* MCDTHR - [5:3] */
1126#define WM8400_MCD 0x0004 /* MCD */
1127#define WM8400_MCD_MASK 0x0004 /* MCD */
1128#define WM8400_MCD_SHIFT 2 /* MCD */
1129#define WM8400_MCD_WIDTH 1 /* MCD */
1130#define WM8400_MBSEL 0x0001 /* MBSEL */
1131#define WM8400_MBSEL_MASK 0x0001 /* MBSEL */
1132#define WM8400_MBSEL_SHIFT 0 /* MBSEL */
1133#define WM8400_MBSEL_WIDTH 1 /* MBSEL */
1134
1135/*
1136 * R60 (0x3C) - FLL Control 1
1137 */
1138#define WM8400_FLL_REF_FREQ 0x1000 /* FLL_REF_FREQ */
1139#define WM8400_FLL_REF_FREQ_MASK 0x1000 /* FLL_REF_FREQ */
1140#define WM8400_FLL_REF_FREQ_SHIFT 12 /* FLL_REF_FREQ */
1141#define WM8400_FLL_REF_FREQ_WIDTH 1 /* FLL_REF_FREQ */
1142#define WM8400_FLL_CLK_SRC_MASK 0x0C00 /* FLL_CLK_SRC - [11:10] */
1143#define WM8400_FLL_CLK_SRC_SHIFT 10 /* FLL_CLK_SRC - [11:10] */
1144#define WM8400_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [11:10] */
1145#define WM8400_FLL_FRAC 0x0200 /* FLL_FRAC */
1146#define WM8400_FLL_FRAC_MASK 0x0200 /* FLL_FRAC */
1147#define WM8400_FLL_FRAC_SHIFT 9 /* FLL_FRAC */
1148#define WM8400_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
1149#define WM8400_FLL_OSC_ENA 0x0100 /* FLL_OSC_ENA */
1150#define WM8400_FLL_OSC_ENA_MASK 0x0100 /* FLL_OSC_ENA */
1151#define WM8400_FLL_OSC_ENA_SHIFT 8 /* FLL_OSC_ENA */
1152#define WM8400_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
1153#define WM8400_FLL_CTRL_RATE_MASK 0x00E0 /* FLL_CTRL_RATE - [7:5] */
1154#define WM8400_FLL_CTRL_RATE_SHIFT 5 /* FLL_CTRL_RATE - [7:5] */
1155#define WM8400_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [7:5] */
1156#define WM8400_FLL_FRATIO_MASK 0x001F /* FLL_FRATIO - [4:0] */
1157#define WM8400_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [4:0] */
1158#define WM8400_FLL_FRATIO_WIDTH 5 /* FLL_FRATIO - [4:0] */
1159
1160/*
1161 * R61 (0x3D) - FLL Control 2
1162 */
1163#define WM8400_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
1164#define WM8400_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
1165#define WM8400_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
1166
1167/*
1168 * R62 (0x3E) - FLL Control 3
1169 */
1170#define WM8400_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */
1171#define WM8400_FLL_N_SHIFT 0 /* FLL_N - [9:0] */
1172#define WM8400_FLL_N_WIDTH 10 /* FLL_N - [9:0] */
1173
1174/*
1175 * R63 (0x3F) - FLL Control 4
1176 */
1177#define WM8400_FLL_TRK_GAIN_MASK 0x0078 /* FLL_TRK_GAIN - [6:3] */
1178#define WM8400_FLL_TRK_GAIN_SHIFT 3 /* FLL_TRK_GAIN - [6:3] */
1179#define WM8400_FLL_TRK_GAIN_WIDTH 4 /* FLL_TRK_GAIN - [6:3] */
1180#define WM8400_FLL_OUTDIV_MASK 0x0007 /* FLL_OUTDIV - [2:0] */
1181#define WM8400_FLL_OUTDIV_SHIFT 0 /* FLL_OUTDIV - [2:0] */
1182#define WM8400_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [2:0] */
1183
1184void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400);
1185
1186#endif
diff --git a/include/linux/mfd/wm8400-private.h b/include/linux/mfd/wm8400-private.h
new file mode 100644
index 000000000000..2aab4e93a5c9
--- /dev/null
+++ b/include/linux/mfd/wm8400-private.h
@@ -0,0 +1,936 @@
1/*
2 * wm8400 private definitions.
3 *
4 * Copyright 2008 Wolfson Microelectronics plc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef __LINUX_MFD_WM8400_PRIV_H
22#define __LINUX_MFD_WM8400_PRIV_H
23
24#include <linux/mfd/wm8400.h>
25#include <linux/mutex.h>
26#include <linux/platform_device.h>
27
28#define WM8400_REGISTER_COUNT 0x55
29
30struct wm8400 {
31 struct device *dev;
32
33 int (*read_dev)(void *data, char reg, int count, u16 *dst);
34 int (*write_dev)(void *data, char reg, int count, const u16 *src);
35
36 struct mutex io_lock;
37 void *io_data;
38
39 u16 reg_cache[WM8400_REGISTER_COUNT];
40
41 struct platform_device regulators[6];
42};
43
44/*
45 * Register values.
46 */
47#define WM8400_RESET_ID 0x00
48#define WM8400_ID 0x01
49#define WM8400_POWER_MANAGEMENT_1 0x02
50#define WM8400_POWER_MANAGEMENT_2 0x03
51#define WM8400_POWER_MANAGEMENT_3 0x04
52#define WM8400_AUDIO_INTERFACE_1 0x05
53#define WM8400_AUDIO_INTERFACE_2 0x06
54#define WM8400_CLOCKING_1 0x07
55#define WM8400_CLOCKING_2 0x08
56#define WM8400_AUDIO_INTERFACE_3 0x09
57#define WM8400_AUDIO_INTERFACE_4 0x0A
58#define WM8400_DAC_CTRL 0x0B
59#define WM8400_LEFT_DAC_DIGITAL_VOLUME 0x0C
60#define WM8400_RIGHT_DAC_DIGITAL_VOLUME 0x0D
61#define WM8400_DIGITAL_SIDE_TONE 0x0E
62#define WM8400_ADC_CTRL 0x0F
63#define WM8400_LEFT_ADC_DIGITAL_VOLUME 0x10
64#define WM8400_RIGHT_ADC_DIGITAL_VOLUME 0x11
65#define WM8400_GPIO_CTRL_1 0x12
66#define WM8400_GPIO1_GPIO2 0x13
67#define WM8400_GPIO3_GPIO4 0x14
68#define WM8400_GPIO5_GPIO6 0x15
69#define WM8400_GPIOCTRL_2 0x16
70#define WM8400_GPIO_POL 0x17
71#define WM8400_LEFT_LINE_INPUT_1_2_VOLUME 0x18
72#define WM8400_LEFT_LINE_INPUT_3_4_VOLUME 0x19
73#define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
74#define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
75#define WM8400_LEFT_OUTPUT_VOLUME 0x1C
76#define WM8400_RIGHT_OUTPUT_VOLUME 0x1D
77#define WM8400_LINE_OUTPUTS_VOLUME 0x1E
78#define WM8400_OUT3_4_VOLUME 0x1F
79#define WM8400_LEFT_OPGA_VOLUME 0x20
80#define WM8400_RIGHT_OPGA_VOLUME 0x21
81#define WM8400_SPEAKER_VOLUME 0x22
82#define WM8400_CLASSD1 0x23
83#define WM8400_CLASSD3 0x25
84#define WM8400_INPUT_MIXER1 0x27
85#define WM8400_INPUT_MIXER2 0x28
86#define WM8400_INPUT_MIXER3 0x29
87#define WM8400_INPUT_MIXER4 0x2A
88#define WM8400_INPUT_MIXER5 0x2B
89#define WM8400_INPUT_MIXER6 0x2C
90#define WM8400_OUTPUT_MIXER1 0x2D
91#define WM8400_OUTPUT_MIXER2 0x2E
92#define WM8400_OUTPUT_MIXER3 0x2F
93#define WM8400_OUTPUT_MIXER4 0x30
94#define WM8400_OUTPUT_MIXER5 0x31
95#define WM8400_OUTPUT_MIXER6 0x32
96#define WM8400_OUT3_4_MIXER 0x33
97#define WM8400_LINE_MIXER1 0x34
98#define WM8400_LINE_MIXER2 0x35
99#define WM8400_SPEAKER_MIXER 0x36
100#define WM8400_ADDITIONAL_CONTROL 0x37
101#define WM8400_ANTIPOP1 0x38
102#define WM8400_ANTIPOP2 0x39
103#define WM8400_MICBIAS 0x3A
104#define WM8400_FLL_CONTROL_1 0x3C
105#define WM8400_FLL_CONTROL_2 0x3D
106#define WM8400_FLL_CONTROL_3 0x3E
107#define WM8400_FLL_CONTROL_4 0x3F
108#define WM8400_LDO1_CONTROL 0x41
109#define WM8400_LDO2_CONTROL 0x42
110#define WM8400_LDO3_CONTROL 0x43
111#define WM8400_LDO4_CONTROL 0x44
112#define WM8400_DCDC1_CONTROL_1 0x46
113#define WM8400_DCDC1_CONTROL_2 0x47
114#define WM8400_DCDC2_CONTROL_1 0x48
115#define WM8400_DCDC2_CONTROL_2 0x49
116#define WM8400_INTERFACE 0x4B
117#define WM8400_PM_GENERAL 0x4C
118#define WM8400_PM_SHUTDOWN_CONTROL 0x4E
119#define WM8400_INTERRUPT_STATUS_1 0x4F
120#define WM8400_INTERRUPT_STATUS_1_MASK 0x50
121#define WM8400_INTERRUPT_LEVELS 0x51
122#define WM8400_SHUTDOWN_REASON 0x52
123#define WM8400_LINE_CIRCUITS 0x54
124
125/*
126 * Field Definitions.
127 */
128
129/*
130 * R0 (0x00) - Reset/ID
131 */
132#define WM8400_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET/CHIP_ID - [15:0] */
133#define WM8400_SW_RESET_CHIP_ID_SHIFT 0 /* SW_RESET/CHIP_ID - [15:0] */
134#define WM8400_SW_RESET_CHIP_ID_WIDTH 16 /* SW_RESET/CHIP_ID - [15:0] */
135
136/*
137 * R1 (0x01) - ID
138 */
139#define WM8400_CHIP_REV_MASK 0x7000 /* CHIP_REV - [14:12] */
140#define WM8400_CHIP_REV_SHIFT 12 /* CHIP_REV - [14:12] */
141#define WM8400_CHIP_REV_WIDTH 3 /* CHIP_REV - [14:12] */
142
143/*
144 * R18 (0x12) - GPIO CTRL 1
145 */
146#define WM8400_IRQ 0x1000 /* IRQ */
147#define WM8400_IRQ_MASK 0x1000 /* IRQ */
148#define WM8400_IRQ_SHIFT 12 /* IRQ */
149#define WM8400_IRQ_WIDTH 1 /* IRQ */
150#define WM8400_TEMPOK 0x0800 /* TEMPOK */
151#define WM8400_TEMPOK_MASK 0x0800 /* TEMPOK */
152#define WM8400_TEMPOK_SHIFT 11 /* TEMPOK */
153#define WM8400_TEMPOK_WIDTH 1 /* TEMPOK */
154#define WM8400_MIC1SHRT 0x0400 /* MIC1SHRT */
155#define WM8400_MIC1SHRT_MASK 0x0400 /* MIC1SHRT */
156#define WM8400_MIC1SHRT_SHIFT 10 /* MIC1SHRT */
157#define WM8400_MIC1SHRT_WIDTH 1 /* MIC1SHRT */
158#define WM8400_MIC1DET 0x0200 /* MIC1DET */
159#define WM8400_MIC1DET_MASK 0x0200 /* MIC1DET */
160#define WM8400_MIC1DET_SHIFT 9 /* MIC1DET */
161#define WM8400_MIC1DET_WIDTH 1 /* MIC1DET */
162#define WM8400_FLL_LCK 0x0100 /* FLL_LCK */
163#define WM8400_FLL_LCK_MASK 0x0100 /* FLL_LCK */
164#define WM8400_FLL_LCK_SHIFT 8 /* FLL_LCK */
165#define WM8400_FLL_LCK_WIDTH 1 /* FLL_LCK */
166#define WM8400_GPIO_STATUS_MASK 0x00FF /* GPIO_STATUS - [7:0] */
167#define WM8400_GPIO_STATUS_SHIFT 0 /* GPIO_STATUS - [7:0] */
168#define WM8400_GPIO_STATUS_WIDTH 8 /* GPIO_STATUS - [7:0] */
169
170/*
171 * R19 (0x13) - GPIO1 & GPIO2
172 */
173#define WM8400_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */
174#define WM8400_GPIO2_DEB_ENA_MASK 0x8000 /* GPIO2_DEB_ENA */
175#define WM8400_GPIO2_DEB_ENA_SHIFT 15 /* GPIO2_DEB_ENA */
176#define WM8400_GPIO2_DEB_ENA_WIDTH 1 /* GPIO2_DEB_ENA */
177#define WM8400_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */
178#define WM8400_GPIO2_IRQ_ENA_MASK 0x4000 /* GPIO2_IRQ_ENA */
179#define WM8400_GPIO2_IRQ_ENA_SHIFT 14 /* GPIO2_IRQ_ENA */
180#define WM8400_GPIO2_IRQ_ENA_WIDTH 1 /* GPIO2_IRQ_ENA */
181#define WM8400_GPIO2_PU 0x2000 /* GPIO2_PU */
182#define WM8400_GPIO2_PU_MASK 0x2000 /* GPIO2_PU */
183#define WM8400_GPIO2_PU_SHIFT 13 /* GPIO2_PU */
184#define WM8400_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
185#define WM8400_GPIO2_PD 0x1000 /* GPIO2_PD */
186#define WM8400_GPIO2_PD_MASK 0x1000 /* GPIO2_PD */
187#define WM8400_GPIO2_PD_SHIFT 12 /* GPIO2_PD */
188#define WM8400_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
189#define WM8400_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */
190#define WM8400_GPIO2_SEL_SHIFT 8 /* GPIO2_SEL - [11:8] */
191#define WM8400_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [11:8] */
192#define WM8400_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */
193#define WM8400_GPIO1_DEB_ENA_MASK 0x0080 /* GPIO1_DEB_ENA */
194#define WM8400_GPIO1_DEB_ENA_SHIFT 7 /* GPIO1_DEB_ENA */
195#define WM8400_GPIO1_DEB_ENA_WIDTH 1 /* GPIO1_DEB_ENA */
196#define WM8400_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */
197#define WM8400_GPIO1_IRQ_ENA_MASK 0x0040 /* GPIO1_IRQ_ENA */
198#define WM8400_GPIO1_IRQ_ENA_SHIFT 6 /* GPIO1_IRQ_ENA */
199#define WM8400_GPIO1_IRQ_ENA_WIDTH 1 /* GPIO1_IRQ_ENA */
200#define WM8400_GPIO1_PU 0x0020 /* GPIO1_PU */
201#define WM8400_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
202#define WM8400_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
203#define WM8400_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
204#define WM8400_GPIO1_PD 0x0010 /* GPIO1_PD */
205#define WM8400_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
206#define WM8400_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
207#define WM8400_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
208#define WM8400_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
209#define WM8400_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
210#define WM8400_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
211
212/*
213 * R20 (0x14) - GPIO3 & GPIO4
214 */
215#define WM8400_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */
216#define WM8400_GPIO4_DEB_ENA_MASK 0x8000 /* GPIO4_DEB_ENA */
217#define WM8400_GPIO4_DEB_ENA_SHIFT 15 /* GPIO4_DEB_ENA */
218#define WM8400_GPIO4_DEB_ENA_WIDTH 1 /* GPIO4_DEB_ENA */
219#define WM8400_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */
220#define WM8400_GPIO4_IRQ_ENA_MASK 0x4000 /* GPIO4_IRQ_ENA */
221#define WM8400_GPIO4_IRQ_ENA_SHIFT 14 /* GPIO4_IRQ_ENA */
222#define WM8400_GPIO4_IRQ_ENA_WIDTH 1 /* GPIO4_IRQ_ENA */
223#define WM8400_GPIO4_PU 0x2000 /* GPIO4_PU */
224#define WM8400_GPIO4_PU_MASK 0x2000 /* GPIO4_PU */
225#define WM8400_GPIO4_PU_SHIFT 13 /* GPIO4_PU */
226#define WM8400_GPIO4_PU_WIDTH 1 /* GPIO4_PU */
227#define WM8400_GPIO4_PD 0x1000 /* GPIO4_PD */
228#define WM8400_GPIO4_PD_MASK 0x1000 /* GPIO4_PD */
229#define WM8400_GPIO4_PD_SHIFT 12 /* GPIO4_PD */
230#define WM8400_GPIO4_PD_WIDTH 1 /* GPIO4_PD */
231#define WM8400_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */
232#define WM8400_GPIO4_SEL_SHIFT 8 /* GPIO4_SEL - [11:8] */
233#define WM8400_GPIO4_SEL_WIDTH 4 /* GPIO4_SEL - [11:8] */
234#define WM8400_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */
235#define WM8400_GPIO3_DEB_ENA_MASK 0x0080 /* GPIO3_DEB_ENA */
236#define WM8400_GPIO3_DEB_ENA_SHIFT 7 /* GPIO3_DEB_ENA */
237#define WM8400_GPIO3_DEB_ENA_WIDTH 1 /* GPIO3_DEB_ENA */
238#define WM8400_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */
239#define WM8400_GPIO3_IRQ_ENA_MASK 0x0040 /* GPIO3_IRQ_ENA */
240#define WM8400_GPIO3_IRQ_ENA_SHIFT 6 /* GPIO3_IRQ_ENA */
241#define WM8400_GPIO3_IRQ_ENA_WIDTH 1 /* GPIO3_IRQ_ENA */
242#define WM8400_GPIO3_PU 0x0020 /* GPIO3_PU */
243#define WM8400_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
244#define WM8400_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
245#define WM8400_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
246#define WM8400_GPIO3_PD 0x0010 /* GPIO3_PD */
247#define WM8400_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
248#define WM8400_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
249#define WM8400_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
250#define WM8400_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
251#define WM8400_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
252#define WM8400_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
253
254/*
255 * R21 (0x15) - GPIO5 & GPIO6
256 */
257#define WM8400_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */
258#define WM8400_GPIO6_DEB_ENA_MASK 0x8000 /* GPIO6_DEB_ENA */
259#define WM8400_GPIO6_DEB_ENA_SHIFT 15 /* GPIO6_DEB_ENA */
260#define WM8400_GPIO6_DEB_ENA_WIDTH 1 /* GPIO6_DEB_ENA */
261#define WM8400_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */
262#define WM8400_GPIO6_IRQ_ENA_MASK 0x4000 /* GPIO6_IRQ_ENA */
263#define WM8400_GPIO6_IRQ_ENA_SHIFT 14 /* GPIO6_IRQ_ENA */
264#define WM8400_GPIO6_IRQ_ENA_WIDTH 1 /* GPIO6_IRQ_ENA */
265#define WM8400_GPIO6_PU 0x2000 /* GPIO6_PU */
266#define WM8400_GPIO6_PU_MASK 0x2000 /* GPIO6_PU */
267#define WM8400_GPIO6_PU_SHIFT 13 /* GPIO6_PU */
268#define WM8400_GPIO6_PU_WIDTH 1 /* GPIO6_PU */
269#define WM8400_GPIO6_PD 0x1000 /* GPIO6_PD */
270#define WM8400_GPIO6_PD_MASK 0x1000 /* GPIO6_PD */
271#define WM8400_GPIO6_PD_SHIFT 12 /* GPIO6_PD */
272#define WM8400_GPIO6_PD_WIDTH 1 /* GPIO6_PD */
273#define WM8400_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */
274#define WM8400_GPIO6_SEL_SHIFT 8 /* GPIO6_SEL - [11:8] */
275#define WM8400_GPIO6_SEL_WIDTH 4 /* GPIO6_SEL - [11:8] */
276#define WM8400_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */
277#define WM8400_GPIO5_DEB_ENA_MASK 0x0080 /* GPIO5_DEB_ENA */
278#define WM8400_GPIO5_DEB_ENA_SHIFT 7 /* GPIO5_DEB_ENA */
279#define WM8400_GPIO5_DEB_ENA_WIDTH 1 /* GPIO5_DEB_ENA */
280#define WM8400_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */
281#define WM8400_GPIO5_IRQ_ENA_MASK 0x0040 /* GPIO5_IRQ_ENA */
282#define WM8400_GPIO5_IRQ_ENA_SHIFT 6 /* GPIO5_IRQ_ENA */
283#define WM8400_GPIO5_IRQ_ENA_WIDTH 1 /* GPIO5_IRQ_ENA */
284#define WM8400_GPIO5_PU 0x0020 /* GPIO5_PU */
285#define WM8400_GPIO5_PU_MASK 0x0020 /* GPIO5_PU */
286#define WM8400_GPIO5_PU_SHIFT 5 /* GPIO5_PU */
287#define WM8400_GPIO5_PU_WIDTH 1 /* GPIO5_PU */
288#define WM8400_GPIO5_PD 0x0010 /* GPIO5_PD */
289#define WM8400_GPIO5_PD_MASK 0x0010 /* GPIO5_PD */
290#define WM8400_GPIO5_PD_SHIFT 4 /* GPIO5_PD */
291#define WM8400_GPIO5_PD_WIDTH 1 /* GPIO5_PD */
292#define WM8400_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */
293#define WM8400_GPIO5_SEL_SHIFT 0 /* GPIO5_SEL - [3:0] */
294#define WM8400_GPIO5_SEL_WIDTH 4 /* GPIO5_SEL - [3:0] */
295
296/*
297 * R22 (0x16) - GPIOCTRL 2
298 */
299#define WM8400_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */
300#define WM8400_TEMPOK_IRQ_ENA_MASK 0x0800 /* TEMPOK_IRQ_ENA */
301#define WM8400_TEMPOK_IRQ_ENA_SHIFT 11 /* TEMPOK_IRQ_ENA */
302#define WM8400_TEMPOK_IRQ_ENA_WIDTH 1 /* TEMPOK_IRQ_ENA */
303#define WM8400_MIC1SHRT_IRQ_ENA 0x0400 /* MIC1SHRT_IRQ_ENA */
304#define WM8400_MIC1SHRT_IRQ_ENA_MASK 0x0400 /* MIC1SHRT_IRQ_ENA */
305#define WM8400_MIC1SHRT_IRQ_ENA_SHIFT 10 /* MIC1SHRT_IRQ_ENA */
306#define WM8400_MIC1SHRT_IRQ_ENA_WIDTH 1 /* MIC1SHRT_IRQ_ENA */
307#define WM8400_MIC1DET_IRQ_ENA 0x0200 /* MIC1DET_IRQ_ENA */
308#define WM8400_MIC1DET_IRQ_ENA_MASK 0x0200 /* MIC1DET_IRQ_ENA */
309#define WM8400_MIC1DET_IRQ_ENA_SHIFT 9 /* MIC1DET_IRQ_ENA */
310#define WM8400_MIC1DET_IRQ_ENA_WIDTH 1 /* MIC1DET_IRQ_ENA */
311#define WM8400_FLL_LCK_IRQ_ENA 0x0100 /* FLL_LCK_IRQ_ENA */
312#define WM8400_FLL_LCK_IRQ_ENA_MASK 0x0100 /* FLL_LCK_IRQ_ENA */
313#define WM8400_FLL_LCK_IRQ_ENA_SHIFT 8 /* FLL_LCK_IRQ_ENA */
314#define WM8400_FLL_LCK_IRQ_ENA_WIDTH 1 /* FLL_LCK_IRQ_ENA */
315#define WM8400_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */
316#define WM8400_GPI8_DEB_ENA_MASK 0x0080 /* GPI8_DEB_ENA */
317#define WM8400_GPI8_DEB_ENA_SHIFT 7 /* GPI8_DEB_ENA */
318#define WM8400_GPI8_DEB_ENA_WIDTH 1 /* GPI8_DEB_ENA */
319#define WM8400_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */
320#define WM8400_GPI8_IRQ_ENA_MASK 0x0040 /* GPI8_IRQ_ENA */
321#define WM8400_GPI8_IRQ_ENA_SHIFT 6 /* GPI8_IRQ_ENA */
322#define WM8400_GPI8_IRQ_ENA_WIDTH 1 /* GPI8_IRQ_ENA */
323#define WM8400_GPI8_ENA 0x0010 /* GPI8_ENA */
324#define WM8400_GPI8_ENA_MASK 0x0010 /* GPI8_ENA */
325#define WM8400_GPI8_ENA_SHIFT 4 /* GPI8_ENA */
326#define WM8400_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
327#define WM8400_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */
328#define WM8400_GPI7_DEB_ENA_MASK 0x0008 /* GPI7_DEB_ENA */
329#define WM8400_GPI7_DEB_ENA_SHIFT 3 /* GPI7_DEB_ENA */
330#define WM8400_GPI7_DEB_ENA_WIDTH 1 /* GPI7_DEB_ENA */
331#define WM8400_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */
332#define WM8400_GPI7_IRQ_ENA_MASK 0x0004 /* GPI7_IRQ_ENA */
333#define WM8400_GPI7_IRQ_ENA_SHIFT 2 /* GPI7_IRQ_ENA */
334#define WM8400_GPI7_IRQ_ENA_WIDTH 1 /* GPI7_IRQ_ENA */
335#define WM8400_GPI7_ENA 0x0001 /* GPI7_ENA */
336#define WM8400_GPI7_ENA_MASK 0x0001 /* GPI7_ENA */
337#define WM8400_GPI7_ENA_SHIFT 0 /* GPI7_ENA */
338#define WM8400_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
339
340/*
341 * R23 (0x17) - GPIO_POL
342 */
343#define WM8400_IRQ_INV 0x1000 /* IRQ_INV */
344#define WM8400_IRQ_INV_MASK 0x1000 /* IRQ_INV */
345#define WM8400_IRQ_INV_SHIFT 12 /* IRQ_INV */
346#define WM8400_IRQ_INV_WIDTH 1 /* IRQ_INV */
347#define WM8400_TEMPOK_POL 0x0800 /* TEMPOK_POL */
348#define WM8400_TEMPOK_POL_MASK 0x0800 /* TEMPOK_POL */
349#define WM8400_TEMPOK_POL_SHIFT 11 /* TEMPOK_POL */
350#define WM8400_TEMPOK_POL_WIDTH 1 /* TEMPOK_POL */
351#define WM8400_MIC1SHRT_POL 0x0400 /* MIC1SHRT_POL */
352#define WM8400_MIC1SHRT_POL_MASK 0x0400 /* MIC1SHRT_POL */
353#define WM8400_MIC1SHRT_POL_SHIFT 10 /* MIC1SHRT_POL */
354#define WM8400_MIC1SHRT_POL_WIDTH 1 /* MIC1SHRT_POL */
355#define WM8400_MIC1DET_POL 0x0200 /* MIC1DET_POL */
356#define WM8400_MIC1DET_POL_MASK 0x0200 /* MIC1DET_POL */
357#define WM8400_MIC1DET_POL_SHIFT 9 /* MIC1DET_POL */
358#define WM8400_MIC1DET_POL_WIDTH 1 /* MIC1DET_POL */
359#define WM8400_FLL_LCK_POL 0x0100 /* FLL_LCK_POL */
360#define WM8400_FLL_LCK_POL_MASK 0x0100 /* FLL_LCK_POL */
361#define WM8400_FLL_LCK_POL_SHIFT 8 /* FLL_LCK_POL */
362#define WM8400_FLL_LCK_POL_WIDTH 1 /* FLL_LCK_POL */
363#define WM8400_GPIO_POL_MASK 0x00FF /* GPIO_POL - [7:0] */
364#define WM8400_GPIO_POL_SHIFT 0 /* GPIO_POL - [7:0] */
365#define WM8400_GPIO_POL_WIDTH 8 /* GPIO_POL - [7:0] */
366
367/*
368 * R65 (0x41) - LDO 1 Control
369 */
370#define WM8400_LDO1_ENA 0x8000 /* LDO1_ENA */
371#define WM8400_LDO1_ENA_MASK 0x8000 /* LDO1_ENA */
372#define WM8400_LDO1_ENA_SHIFT 15 /* LDO1_ENA */
373#define WM8400_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
374#define WM8400_LDO1_SWI 0x4000 /* LDO1_SWI */
375#define WM8400_LDO1_SWI_MASK 0x4000 /* LDO1_SWI */
376#define WM8400_LDO1_SWI_SHIFT 14 /* LDO1_SWI */
377#define WM8400_LDO1_SWI_WIDTH 1 /* LDO1_SWI */
378#define WM8400_LDO1_OPFLT 0x1000 /* LDO1_OPFLT */
379#define WM8400_LDO1_OPFLT_MASK 0x1000 /* LDO1_OPFLT */
380#define WM8400_LDO1_OPFLT_SHIFT 12 /* LDO1_OPFLT */
381#define WM8400_LDO1_OPFLT_WIDTH 1 /* LDO1_OPFLT */
382#define WM8400_LDO1_ERRACT 0x0800 /* LDO1_ERRACT */
383#define WM8400_LDO1_ERRACT_MASK 0x0800 /* LDO1_ERRACT */
384#define WM8400_LDO1_ERRACT_SHIFT 11 /* LDO1_ERRACT */
385#define WM8400_LDO1_ERRACT_WIDTH 1 /* LDO1_ERRACT */
386#define WM8400_LDO1_HIB_MODE 0x0400 /* LDO1_HIB_MODE */
387#define WM8400_LDO1_HIB_MODE_MASK 0x0400 /* LDO1_HIB_MODE */
388#define WM8400_LDO1_HIB_MODE_SHIFT 10 /* LDO1_HIB_MODE */
389#define WM8400_LDO1_HIB_MODE_WIDTH 1 /* LDO1_HIB_MODE */
390#define WM8400_LDO1_VIMG_MASK 0x03E0 /* LDO1_VIMG - [9:5] */
391#define WM8400_LDO1_VIMG_SHIFT 5 /* LDO1_VIMG - [9:5] */
392#define WM8400_LDO1_VIMG_WIDTH 5 /* LDO1_VIMG - [9:5] */
393#define WM8400_LDO1_VSEL_MASK 0x001F /* LDO1_VSEL - [4:0] */
394#define WM8400_LDO1_VSEL_SHIFT 0 /* LDO1_VSEL - [4:0] */
395#define WM8400_LDO1_VSEL_WIDTH 5 /* LDO1_VSEL - [4:0] */
396
397/*
398 * R66 (0x42) - LDO 2 Control
399 */
400#define WM8400_LDO2_ENA 0x8000 /* LDO2_ENA */
401#define WM8400_LDO2_ENA_MASK 0x8000 /* LDO2_ENA */
402#define WM8400_LDO2_ENA_SHIFT 15 /* LDO2_ENA */
403#define WM8400_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
404#define WM8400_LDO2_SWI 0x4000 /* LDO2_SWI */
405#define WM8400_LDO2_SWI_MASK 0x4000 /* LDO2_SWI */
406#define WM8400_LDO2_SWI_SHIFT 14 /* LDO2_SWI */
407#define WM8400_LDO2_SWI_WIDTH 1 /* LDO2_SWI */
408#define WM8400_LDO2_OPFLT 0x1000 /* LDO2_OPFLT */
409#define WM8400_LDO2_OPFLT_MASK 0x1000 /* LDO2_OPFLT */
410#define WM8400_LDO2_OPFLT_SHIFT 12 /* LDO2_OPFLT */
411#define WM8400_LDO2_OPFLT_WIDTH 1 /* LDO2_OPFLT */
412#define WM8400_LDO2_ERRACT 0x0800 /* LDO2_ERRACT */
413#define WM8400_LDO2_ERRACT_MASK 0x0800 /* LDO2_ERRACT */
414#define WM8400_LDO2_ERRACT_SHIFT 11 /* LDO2_ERRACT */
415#define WM8400_LDO2_ERRACT_WIDTH 1 /* LDO2_ERRACT */
416#define WM8400_LDO2_HIB_MODE 0x0400 /* LDO2_HIB_MODE */
417#define WM8400_LDO2_HIB_MODE_MASK 0x0400 /* LDO2_HIB_MODE */
418#define WM8400_LDO2_HIB_MODE_SHIFT 10 /* LDO2_HIB_MODE */
419#define WM8400_LDO2_HIB_MODE_WIDTH 1 /* LDO2_HIB_MODE */
420#define WM8400_LDO2_VIMG_MASK 0x03E0 /* LDO2_VIMG - [9:5] */
421#define WM8400_LDO2_VIMG_SHIFT 5 /* LDO2_VIMG - [9:5] */
422#define WM8400_LDO2_VIMG_WIDTH 5 /* LDO2_VIMG - [9:5] */
423#define WM8400_LDO2_VSEL_MASK 0x001F /* LDO2_VSEL - [4:0] */
424#define WM8400_LDO2_VSEL_SHIFT 0 /* LDO2_VSEL - [4:0] */
425#define WM8400_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [4:0] */
426
427/*
428 * R67 (0x43) - LDO 3 Control
429 */
430#define WM8400_LDO3_ENA 0x8000 /* LDO3_ENA */
431#define WM8400_LDO3_ENA_MASK 0x8000 /* LDO3_ENA */
432#define WM8400_LDO3_ENA_SHIFT 15 /* LDO3_ENA */
433#define WM8400_LDO3_ENA_WIDTH 1 /* LDO3_ENA */
434#define WM8400_LDO3_SWI 0x4000 /* LDO3_SWI */
435#define WM8400_LDO3_SWI_MASK 0x4000 /* LDO3_SWI */
436#define WM8400_LDO3_SWI_SHIFT 14 /* LDO3_SWI */
437#define WM8400_LDO3_SWI_WIDTH 1 /* LDO3_SWI */
438#define WM8400_LDO3_OPFLT 0x1000 /* LDO3_OPFLT */
439#define WM8400_LDO3_OPFLT_MASK 0x1000 /* LDO3_OPFLT */
440#define WM8400_LDO3_OPFLT_SHIFT 12 /* LDO3_OPFLT */
441#define WM8400_LDO3_OPFLT_WIDTH 1 /* LDO3_OPFLT */
442#define WM8400_LDO3_ERRACT 0x0800 /* LDO3_ERRACT */
443#define WM8400_LDO3_ERRACT_MASK 0x0800 /* LDO3_ERRACT */
444#define WM8400_LDO3_ERRACT_SHIFT 11 /* LDO3_ERRACT */
445#define WM8400_LDO3_ERRACT_WIDTH 1 /* LDO3_ERRACT */
446#define WM8400_LDO3_HIB_MODE 0x0400 /* LDO3_HIB_MODE */
447#define WM8400_LDO3_HIB_MODE_MASK 0x0400 /* LDO3_HIB_MODE */
448#define WM8400_LDO3_HIB_MODE_SHIFT 10 /* LDO3_HIB_MODE */
449#define WM8400_LDO3_HIB_MODE_WIDTH 1 /* LDO3_HIB_MODE */
450#define WM8400_LDO3_VIMG_MASK 0x03E0 /* LDO3_VIMG - [9:5] */
451#define WM8400_LDO3_VIMG_SHIFT 5 /* LDO3_VIMG - [9:5] */
452#define WM8400_LDO3_VIMG_WIDTH 5 /* LDO3_VIMG - [9:5] */
453#define WM8400_LDO3_VSEL_MASK 0x001F /* LDO3_VSEL - [4:0] */
454#define WM8400_LDO3_VSEL_SHIFT 0 /* LDO3_VSEL - [4:0] */
455#define WM8400_LDO3_VSEL_WIDTH 5 /* LDO3_VSEL - [4:0] */
456
457/*
458 * R68 (0x44) - LDO 4 Control
459 */
460#define WM8400_LDO4_ENA 0x8000 /* LDO4_ENA */
461#define WM8400_LDO4_ENA_MASK 0x8000 /* LDO4_ENA */
462#define WM8400_LDO4_ENA_SHIFT 15 /* LDO4_ENA */
463#define WM8400_LDO4_ENA_WIDTH 1 /* LDO4_ENA */
464#define WM8400_LDO4_SWI 0x4000 /* LDO4_SWI */
465#define WM8400_LDO4_SWI_MASK 0x4000 /* LDO4_SWI */
466#define WM8400_LDO4_SWI_SHIFT 14 /* LDO4_SWI */
467#define WM8400_LDO4_SWI_WIDTH 1 /* LDO4_SWI */
468#define WM8400_LDO4_OPFLT 0x1000 /* LDO4_OPFLT */
469#define WM8400_LDO4_OPFLT_MASK 0x1000 /* LDO4_OPFLT */
470#define WM8400_LDO4_OPFLT_SHIFT 12 /* LDO4_OPFLT */
471#define WM8400_LDO4_OPFLT_WIDTH 1 /* LDO4_OPFLT */
472#define WM8400_LDO4_ERRACT 0x0800 /* LDO4_ERRACT */
473#define WM8400_LDO4_ERRACT_MASK 0x0800 /* LDO4_ERRACT */
474#define WM8400_LDO4_ERRACT_SHIFT 11 /* LDO4_ERRACT */
475#define WM8400_LDO4_ERRACT_WIDTH 1 /* LDO4_ERRACT */
476#define WM8400_LDO4_HIB_MODE 0x0400 /* LDO4_HIB_MODE */
477#define WM8400_LDO4_HIB_MODE_MASK 0x0400 /* LDO4_HIB_MODE */
478#define WM8400_LDO4_HIB_MODE_SHIFT 10 /* LDO4_HIB_MODE */
479#define WM8400_LDO4_HIB_MODE_WIDTH 1 /* LDO4_HIB_MODE */
480#define WM8400_LDO4_VIMG_MASK 0x03E0 /* LDO4_VIMG - [9:5] */
481#define WM8400_LDO4_VIMG_SHIFT 5 /* LDO4_VIMG - [9:5] */
482#define WM8400_LDO4_VIMG_WIDTH 5 /* LDO4_VIMG - [9:5] */
483#define WM8400_LDO4_VSEL_MASK 0x001F /* LDO4_VSEL - [4:0] */
484#define WM8400_LDO4_VSEL_SHIFT 0 /* LDO4_VSEL - [4:0] */
485#define WM8400_LDO4_VSEL_WIDTH 5 /* LDO4_VSEL - [4:0] */
486
487/*
488 * R70 (0x46) - DCDC1 Control 1
489 */
490#define WM8400_DC1_ENA 0x8000 /* DC1_ENA */
491#define WM8400_DC1_ENA_MASK 0x8000 /* DC1_ENA */
492#define WM8400_DC1_ENA_SHIFT 15 /* DC1_ENA */
493#define WM8400_DC1_ENA_WIDTH 1 /* DC1_ENA */
494#define WM8400_DC1_ACTIVE 0x4000 /* DC1_ACTIVE */
495#define WM8400_DC1_ACTIVE_MASK 0x4000 /* DC1_ACTIVE */
496#define WM8400_DC1_ACTIVE_SHIFT 14 /* DC1_ACTIVE */
497#define WM8400_DC1_ACTIVE_WIDTH 1 /* DC1_ACTIVE */
498#define WM8400_DC1_SLEEP 0x2000 /* DC1_SLEEP */
499#define WM8400_DC1_SLEEP_MASK 0x2000 /* DC1_SLEEP */
500#define WM8400_DC1_SLEEP_SHIFT 13 /* DC1_SLEEP */
501#define WM8400_DC1_SLEEP_WIDTH 1 /* DC1_SLEEP */
502#define WM8400_DC1_OPFLT 0x1000 /* DC1_OPFLT */
503#define WM8400_DC1_OPFLT_MASK 0x1000 /* DC1_OPFLT */
504#define WM8400_DC1_OPFLT_SHIFT 12 /* DC1_OPFLT */
505#define WM8400_DC1_OPFLT_WIDTH 1 /* DC1_OPFLT */
506#define WM8400_DC1_ERRACT 0x0800 /* DC1_ERRACT */
507#define WM8400_DC1_ERRACT_MASK 0x0800 /* DC1_ERRACT */
508#define WM8400_DC1_ERRACT_SHIFT 11 /* DC1_ERRACT */
509#define WM8400_DC1_ERRACT_WIDTH 1 /* DC1_ERRACT */
510#define WM8400_DC1_HIB_MODE 0x0400 /* DC1_HIB_MODE */
511#define WM8400_DC1_HIB_MODE_MASK 0x0400 /* DC1_HIB_MODE */
512#define WM8400_DC1_HIB_MODE_SHIFT 10 /* DC1_HIB_MODE */
513#define WM8400_DC1_HIB_MODE_WIDTH 1 /* DC1_HIB_MODE */
514#define WM8400_DC1_SOFTST_MASK 0x0300 /* DC1_SOFTST - [9:8] */
515#define WM8400_DC1_SOFTST_SHIFT 8 /* DC1_SOFTST - [9:8] */
516#define WM8400_DC1_SOFTST_WIDTH 2 /* DC1_SOFTST - [9:8] */
517#define WM8400_DC1_OV_PROT 0x0080 /* DC1_OV_PROT */
518#define WM8400_DC1_OV_PROT_MASK 0x0080 /* DC1_OV_PROT */
519#define WM8400_DC1_OV_PROT_SHIFT 7 /* DC1_OV_PROT */
520#define WM8400_DC1_OV_PROT_WIDTH 1 /* DC1_OV_PROT */
521#define WM8400_DC1_VSEL_MASK 0x007F /* DC1_VSEL - [6:0] */
522#define WM8400_DC1_VSEL_SHIFT 0 /* DC1_VSEL - [6:0] */
523#define WM8400_DC1_VSEL_WIDTH 7 /* DC1_VSEL - [6:0] */
524
525/*
526 * R71 (0x47) - DCDC1 Control 2
527 */
528#define WM8400_DC1_FRC_PWM 0x2000 /* DC1_FRC_PWM */
529#define WM8400_DC1_FRC_PWM_MASK 0x2000 /* DC1_FRC_PWM */
530#define WM8400_DC1_FRC_PWM_SHIFT 13 /* DC1_FRC_PWM */
531#define WM8400_DC1_FRC_PWM_WIDTH 1 /* DC1_FRC_PWM */
532#define WM8400_DC1_STBY_LIM_MASK 0x0300 /* DC1_STBY_LIM - [9:8] */
533#define WM8400_DC1_STBY_LIM_SHIFT 8 /* DC1_STBY_LIM - [9:8] */
534#define WM8400_DC1_STBY_LIM_WIDTH 2 /* DC1_STBY_LIM - [9:8] */
535#define WM8400_DC1_ACT_LIM 0x0080 /* DC1_ACT_LIM */
536#define WM8400_DC1_ACT_LIM_MASK 0x0080 /* DC1_ACT_LIM */
537#define WM8400_DC1_ACT_LIM_SHIFT 7 /* DC1_ACT_LIM */
538#define WM8400_DC1_ACT_LIM_WIDTH 1 /* DC1_ACT_LIM */
539#define WM8400_DC1_VIMG_MASK 0x007F /* DC1_VIMG - [6:0] */
540#define WM8400_DC1_VIMG_SHIFT 0 /* DC1_VIMG - [6:0] */
541#define WM8400_DC1_VIMG_WIDTH 7 /* DC1_VIMG - [6:0] */
542
543/*
544 * R72 (0x48) - DCDC2 Control 1
545 */
546#define WM8400_DC2_ENA 0x8000 /* DC2_ENA */
547#define WM8400_DC2_ENA_MASK 0x8000 /* DC2_ENA */
548#define WM8400_DC2_ENA_SHIFT 15 /* DC2_ENA */
549#define WM8400_DC2_ENA_WIDTH 1 /* DC2_ENA */
550#define WM8400_DC2_ACTIVE 0x4000 /* DC2_ACTIVE */
551#define WM8400_DC2_ACTIVE_MASK 0x4000 /* DC2_ACTIVE */
552#define WM8400_DC2_ACTIVE_SHIFT 14 /* DC2_ACTIVE */
553#define WM8400_DC2_ACTIVE_WIDTH 1 /* DC2_ACTIVE */
554#define WM8400_DC2_SLEEP 0x2000 /* DC2_SLEEP */
555#define WM8400_DC2_SLEEP_MASK 0x2000 /* DC2_SLEEP */
556#define WM8400_DC2_SLEEP_SHIFT 13 /* DC2_SLEEP */
557#define WM8400_DC2_SLEEP_WIDTH 1 /* DC2_SLEEP */
558#define WM8400_DC2_OPFLT 0x1000 /* DC2_OPFLT */
559#define WM8400_DC2_OPFLT_MASK 0x1000 /* DC2_OPFLT */
560#define WM8400_DC2_OPFLT_SHIFT 12 /* DC2_OPFLT */
561#define WM8400_DC2_OPFLT_WIDTH 1 /* DC2_OPFLT */
562#define WM8400_DC2_ERRACT 0x0800 /* DC2_ERRACT */
563#define WM8400_DC2_ERRACT_MASK 0x0800 /* DC2_ERRACT */
564#define WM8400_DC2_ERRACT_SHIFT 11 /* DC2_ERRACT */
565#define WM8400_DC2_ERRACT_WIDTH 1 /* DC2_ERRACT */
566#define WM8400_DC2_HIB_MODE 0x0400 /* DC2_HIB_MODE */
567#define WM8400_DC2_HIB_MODE_MASK 0x0400 /* DC2_HIB_MODE */
568#define WM8400_DC2_HIB_MODE_SHIFT 10 /* DC2_HIB_MODE */
569#define WM8400_DC2_HIB_MODE_WIDTH 1 /* DC2_HIB_MODE */
570#define WM8400_DC2_SOFTST_MASK 0x0300 /* DC2_SOFTST - [9:8] */
571#define WM8400_DC2_SOFTST_SHIFT 8 /* DC2_SOFTST - [9:8] */
572#define WM8400_DC2_SOFTST_WIDTH 2 /* DC2_SOFTST - [9:8] */
573#define WM8400_DC2_OV_PROT 0x0080 /* DC2_OV_PROT */
574#define WM8400_DC2_OV_PROT_MASK 0x0080 /* DC2_OV_PROT */
575#define WM8400_DC2_OV_PROT_SHIFT 7 /* DC2_OV_PROT */
576#define WM8400_DC2_OV_PROT_WIDTH 1 /* DC2_OV_PROT */
577#define WM8400_DC2_VSEL_MASK 0x007F /* DC2_VSEL - [6:0] */
578#define WM8400_DC2_VSEL_SHIFT 0 /* DC2_VSEL - [6:0] */
579#define WM8400_DC2_VSEL_WIDTH 7 /* DC2_VSEL - [6:0] */
580
581/*
582 * R73 (0x49) - DCDC2 Control 2
583 */
584#define WM8400_DC2_FRC_PWM 0x2000 /* DC2_FRC_PWM */
585#define WM8400_DC2_FRC_PWM_MASK 0x2000 /* DC2_FRC_PWM */
586#define WM8400_DC2_FRC_PWM_SHIFT 13 /* DC2_FRC_PWM */
587#define WM8400_DC2_FRC_PWM_WIDTH 1 /* DC2_FRC_PWM */
588#define WM8400_DC2_STBY_LIM_MASK 0x0300 /* DC2_STBY_LIM - [9:8] */
589#define WM8400_DC2_STBY_LIM_SHIFT 8 /* DC2_STBY_LIM - [9:8] */
590#define WM8400_DC2_STBY_LIM_WIDTH 2 /* DC2_STBY_LIM - [9:8] */
591#define WM8400_DC2_ACT_LIM 0x0080 /* DC2_ACT_LIM */
592#define WM8400_DC2_ACT_LIM_MASK 0x0080 /* DC2_ACT_LIM */
593#define WM8400_DC2_ACT_LIM_SHIFT 7 /* DC2_ACT_LIM */
594#define WM8400_DC2_ACT_LIM_WIDTH 1 /* DC2_ACT_LIM */
595#define WM8400_DC2_VIMG_MASK 0x007F /* DC2_VIMG - [6:0] */
596#define WM8400_DC2_VIMG_SHIFT 0 /* DC2_VIMG - [6:0] */
597#define WM8400_DC2_VIMG_WIDTH 7 /* DC2_VIMG - [6:0] */
598
599/*
600 * R75 (0x4B) - Interface
601 */
602#define WM8400_AUTOINC 0x0008 /* AUTOINC */
603#define WM8400_AUTOINC_MASK 0x0008 /* AUTOINC */
604#define WM8400_AUTOINC_SHIFT 3 /* AUTOINC */
605#define WM8400_AUTOINC_WIDTH 1 /* AUTOINC */
606#define WM8400_ARA_ENA 0x0004 /* ARA_ENA */
607#define WM8400_ARA_ENA_MASK 0x0004 /* ARA_ENA */
608#define WM8400_ARA_ENA_SHIFT 2 /* ARA_ENA */
609#define WM8400_ARA_ENA_WIDTH 1 /* ARA_ENA */
610#define WM8400_SPI_CFG 0x0002 /* SPI_CFG */
611#define WM8400_SPI_CFG_MASK 0x0002 /* SPI_CFG */
612#define WM8400_SPI_CFG_SHIFT 1 /* SPI_CFG */
613#define WM8400_SPI_CFG_WIDTH 1 /* SPI_CFG */
614
615/*
616 * R76 (0x4C) - PM GENERAL
617 */
618#define WM8400_CODEC_SOFTST 0x8000 /* CODEC_SOFTST */
619#define WM8400_CODEC_SOFTST_MASK 0x8000 /* CODEC_SOFTST */
620#define WM8400_CODEC_SOFTST_SHIFT 15 /* CODEC_SOFTST */
621#define WM8400_CODEC_SOFTST_WIDTH 1 /* CODEC_SOFTST */
622#define WM8400_CODEC_SOFTSD 0x4000 /* CODEC_SOFTSD */
623#define WM8400_CODEC_SOFTSD_MASK 0x4000 /* CODEC_SOFTSD */
624#define WM8400_CODEC_SOFTSD_SHIFT 14 /* CODEC_SOFTSD */
625#define WM8400_CODEC_SOFTSD_WIDTH 1 /* CODEC_SOFTSD */
626#define WM8400_CHIP_SOFTSD 0x2000 /* CHIP_SOFTSD */
627#define WM8400_CHIP_SOFTSD_MASK 0x2000 /* CHIP_SOFTSD */
628#define WM8400_CHIP_SOFTSD_SHIFT 13 /* CHIP_SOFTSD */
629#define WM8400_CHIP_SOFTSD_WIDTH 1 /* CHIP_SOFTSD */
630#define WM8400_DSLEEP1_POL 0x0008 /* DSLEEP1_POL */
631#define WM8400_DSLEEP1_POL_MASK 0x0008 /* DSLEEP1_POL */
632#define WM8400_DSLEEP1_POL_SHIFT 3 /* DSLEEP1_POL */
633#define WM8400_DSLEEP1_POL_WIDTH 1 /* DSLEEP1_POL */
634#define WM8400_DSLEEP2_POL 0x0004 /* DSLEEP2_POL */
635#define WM8400_DSLEEP2_POL_MASK 0x0004 /* DSLEEP2_POL */
636#define WM8400_DSLEEP2_POL_SHIFT 2 /* DSLEEP2_POL */
637#define WM8400_DSLEEP2_POL_WIDTH 1 /* DSLEEP2_POL */
638#define WM8400_PWR_STATE_MASK 0x0003 /* PWR_STATE - [1:0] */
639#define WM8400_PWR_STATE_SHIFT 0 /* PWR_STATE - [1:0] */
640#define WM8400_PWR_STATE_WIDTH 2 /* PWR_STATE - [1:0] */
641
642/*
643 * R78 (0x4E) - PM Shutdown Control
644 */
645#define WM8400_CHIP_GT150_ERRACT 0x0200 /* CHIP_GT150_ERRACT */
646#define WM8400_CHIP_GT150_ERRACT_MASK 0x0200 /* CHIP_GT150_ERRACT */
647#define WM8400_CHIP_GT150_ERRACT_SHIFT 9 /* CHIP_GT150_ERRACT */
648#define WM8400_CHIP_GT150_ERRACT_WIDTH 1 /* CHIP_GT150_ERRACT */
649#define WM8400_CHIP_GT115_ERRACT 0x0100 /* CHIP_GT115_ERRACT */
650#define WM8400_CHIP_GT115_ERRACT_MASK 0x0100 /* CHIP_GT115_ERRACT */
651#define WM8400_CHIP_GT115_ERRACT_SHIFT 8 /* CHIP_GT115_ERRACT */
652#define WM8400_CHIP_GT115_ERRACT_WIDTH 1 /* CHIP_GT115_ERRACT */
653#define WM8400_LINE_CMP_ERRACT 0x0080 /* LINE_CMP_ERRACT */
654#define WM8400_LINE_CMP_ERRACT_MASK 0x0080 /* LINE_CMP_ERRACT */
655#define WM8400_LINE_CMP_ERRACT_SHIFT 7 /* LINE_CMP_ERRACT */
656#define WM8400_LINE_CMP_ERRACT_WIDTH 1 /* LINE_CMP_ERRACT */
657#define WM8400_UVLO_ERRACT 0x0040 /* UVLO_ERRACT */
658#define WM8400_UVLO_ERRACT_MASK 0x0040 /* UVLO_ERRACT */
659#define WM8400_UVLO_ERRACT_SHIFT 6 /* UVLO_ERRACT */
660#define WM8400_UVLO_ERRACT_WIDTH 1 /* UVLO_ERRACT */
661
662/*
663 * R79 (0x4F) - Interrupt Status 1
664 */
665#define WM8400_MICD_CINT 0x8000 /* MICD_CINT */
666#define WM8400_MICD_CINT_MASK 0x8000 /* MICD_CINT */
667#define WM8400_MICD_CINT_SHIFT 15 /* MICD_CINT */
668#define WM8400_MICD_CINT_WIDTH 1 /* MICD_CINT */
669#define WM8400_MICSCD_CINT 0x4000 /* MICSCD_CINT */
670#define WM8400_MICSCD_CINT_MASK 0x4000 /* MICSCD_CINT */
671#define WM8400_MICSCD_CINT_SHIFT 14 /* MICSCD_CINT */
672#define WM8400_MICSCD_CINT_WIDTH 1 /* MICSCD_CINT */
673#define WM8400_JDL_CINT 0x2000 /* JDL_CINT */
674#define WM8400_JDL_CINT_MASK 0x2000 /* JDL_CINT */
675#define WM8400_JDL_CINT_SHIFT 13 /* JDL_CINT */
676#define WM8400_JDL_CINT_WIDTH 1 /* JDL_CINT */
677#define WM8400_JDR_CINT 0x1000 /* JDR_CINT */
678#define WM8400_JDR_CINT_MASK 0x1000 /* JDR_CINT */
679#define WM8400_JDR_CINT_SHIFT 12 /* JDR_CINT */
680#define WM8400_JDR_CINT_WIDTH 1 /* JDR_CINT */
681#define WM8400_CODEC_SEQ_END_EINT 0x0800 /* CODEC_SEQ_END_EINT */
682#define WM8400_CODEC_SEQ_END_EINT_MASK 0x0800 /* CODEC_SEQ_END_EINT */
683#define WM8400_CODEC_SEQ_END_EINT_SHIFT 11 /* CODEC_SEQ_END_EINT */
684#define WM8400_CODEC_SEQ_END_EINT_WIDTH 1 /* CODEC_SEQ_END_EINT */
685#define WM8400_CDEL_TO_EINT 0x0400 /* CDEL_TO_EINT */
686#define WM8400_CDEL_TO_EINT_MASK 0x0400 /* CDEL_TO_EINT */
687#define WM8400_CDEL_TO_EINT_SHIFT 10 /* CDEL_TO_EINT */
688#define WM8400_CDEL_TO_EINT_WIDTH 1 /* CDEL_TO_EINT */
689#define WM8400_CHIP_GT150_EINT 0x0200 /* CHIP_GT150_EINT */
690#define WM8400_CHIP_GT150_EINT_MASK 0x0200 /* CHIP_GT150_EINT */
691#define WM8400_CHIP_GT150_EINT_SHIFT 9 /* CHIP_GT150_EINT */
692#define WM8400_CHIP_GT150_EINT_WIDTH 1 /* CHIP_GT150_EINT */
693#define WM8400_CHIP_GT115_EINT 0x0100 /* CHIP_GT115_EINT */
694#define WM8400_CHIP_GT115_EINT_MASK 0x0100 /* CHIP_GT115_EINT */
695#define WM8400_CHIP_GT115_EINT_SHIFT 8 /* CHIP_GT115_EINT */
696#define WM8400_CHIP_GT115_EINT_WIDTH 1 /* CHIP_GT115_EINT */
697#define WM8400_LINE_CMP_EINT 0x0080 /* LINE_CMP_EINT */
698#define WM8400_LINE_CMP_EINT_MASK 0x0080 /* LINE_CMP_EINT */
699#define WM8400_LINE_CMP_EINT_SHIFT 7 /* LINE_CMP_EINT */
700#define WM8400_LINE_CMP_EINT_WIDTH 1 /* LINE_CMP_EINT */
701#define WM8400_UVLO_EINT 0x0040 /* UVLO_EINT */
702#define WM8400_UVLO_EINT_MASK 0x0040 /* UVLO_EINT */
703#define WM8400_UVLO_EINT_SHIFT 6 /* UVLO_EINT */
704#define WM8400_UVLO_EINT_WIDTH 1 /* UVLO_EINT */
705#define WM8400_DC2_UV_EINT 0x0020 /* DC2_UV_EINT */
706#define WM8400_DC2_UV_EINT_MASK 0x0020 /* DC2_UV_EINT */
707#define WM8400_DC2_UV_EINT_SHIFT 5 /* DC2_UV_EINT */
708#define WM8400_DC2_UV_EINT_WIDTH 1 /* DC2_UV_EINT */
709#define WM8400_DC1_UV_EINT 0x0010 /* DC1_UV_EINT */
710#define WM8400_DC1_UV_EINT_MASK 0x0010 /* DC1_UV_EINT */
711#define WM8400_DC1_UV_EINT_SHIFT 4 /* DC1_UV_EINT */
712#define WM8400_DC1_UV_EINT_WIDTH 1 /* DC1_UV_EINT */
713#define WM8400_LDO4_UV_EINT 0x0008 /* LDO4_UV_EINT */
714#define WM8400_LDO4_UV_EINT_MASK 0x0008 /* LDO4_UV_EINT */
715#define WM8400_LDO4_UV_EINT_SHIFT 3 /* LDO4_UV_EINT */
716#define WM8400_LDO4_UV_EINT_WIDTH 1 /* LDO4_UV_EINT */
717#define WM8400_LDO3_UV_EINT 0x0004 /* LDO3_UV_EINT */
718#define WM8400_LDO3_UV_EINT_MASK 0x0004 /* LDO3_UV_EINT */
719#define WM8400_LDO3_UV_EINT_SHIFT 2 /* LDO3_UV_EINT */
720#define WM8400_LDO3_UV_EINT_WIDTH 1 /* LDO3_UV_EINT */
721#define WM8400_LDO2_UV_EINT 0x0002 /* LDO2_UV_EINT */
722#define WM8400_LDO2_UV_EINT_MASK 0x0002 /* LDO2_UV_EINT */
723#define WM8400_LDO2_UV_EINT_SHIFT 1 /* LDO2_UV_EINT */
724#define WM8400_LDO2_UV_EINT_WIDTH 1 /* LDO2_UV_EINT */
725#define WM8400_LDO1_UV_EINT 0x0001 /* LDO1_UV_EINT */
726#define WM8400_LDO1_UV_EINT_MASK 0x0001 /* LDO1_UV_EINT */
727#define WM8400_LDO1_UV_EINT_SHIFT 0 /* LDO1_UV_EINT */
728#define WM8400_LDO1_UV_EINT_WIDTH 1 /* LDO1_UV_EINT */
729
730/*
731 * R80 (0x50) - Interrupt Status 1 Mask
732 */
733#define WM8400_IM_MICD_CINT 0x8000 /* IM_MICD_CINT */
734#define WM8400_IM_MICD_CINT_MASK 0x8000 /* IM_MICD_CINT */
735#define WM8400_IM_MICD_CINT_SHIFT 15 /* IM_MICD_CINT */
736#define WM8400_IM_MICD_CINT_WIDTH 1 /* IM_MICD_CINT */
737#define WM8400_IM_MICSCD_CINT 0x4000 /* IM_MICSCD_CINT */
738#define WM8400_IM_MICSCD_CINT_MASK 0x4000 /* IM_MICSCD_CINT */
739#define WM8400_IM_MICSCD_CINT_SHIFT 14 /* IM_MICSCD_CINT */
740#define WM8400_IM_MICSCD_CINT_WIDTH 1 /* IM_MICSCD_CINT */
741#define WM8400_IM_JDL_CINT 0x2000 /* IM_JDL_CINT */
742#define WM8400_IM_JDL_CINT_MASK 0x2000 /* IM_JDL_CINT */
743#define WM8400_IM_JDL_CINT_SHIFT 13 /* IM_JDL_CINT */
744#define WM8400_IM_JDL_CINT_WIDTH 1 /* IM_JDL_CINT */
745#define WM8400_IM_JDR_CINT 0x1000 /* IM_JDR_CINT */
746#define WM8400_IM_JDR_CINT_MASK 0x1000 /* IM_JDR_CINT */
747#define WM8400_IM_JDR_CINT_SHIFT 12 /* IM_JDR_CINT */
748#define WM8400_IM_JDR_CINT_WIDTH 1 /* IM_JDR_CINT */
749#define WM8400_IM_CODEC_SEQ_END_EINT 0x0800 /* IM_CODEC_SEQ_END_EINT */
750#define WM8400_IM_CODEC_SEQ_END_EINT_MASK 0x0800 /* IM_CODEC_SEQ_END_EINT */
751#define WM8400_IM_CODEC_SEQ_END_EINT_SHIFT 11 /* IM_CODEC_SEQ_END_EINT */
752#define WM8400_IM_CODEC_SEQ_END_EINT_WIDTH 1 /* IM_CODEC_SEQ_END_EINT */
753#define WM8400_IM_CDEL_TO_EINT 0x0400 /* IM_CDEL_TO_EINT */
754#define WM8400_IM_CDEL_TO_EINT_MASK 0x0400 /* IM_CDEL_TO_EINT */
755#define WM8400_IM_CDEL_TO_EINT_SHIFT 10 /* IM_CDEL_TO_EINT */
756#define WM8400_IM_CDEL_TO_EINT_WIDTH 1 /* IM_CDEL_TO_EINT */
757#define WM8400_IM_CHIP_GT150_EINT 0x0200 /* IM_CHIP_GT150_EINT */
758#define WM8400_IM_CHIP_GT150_EINT_MASK 0x0200 /* IM_CHIP_GT150_EINT */
759#define WM8400_IM_CHIP_GT150_EINT_SHIFT 9 /* IM_CHIP_GT150_EINT */
760#define WM8400_IM_CHIP_GT150_EINT_WIDTH 1 /* IM_CHIP_GT150_EINT */
761#define WM8400_IM_CHIP_GT115_EINT 0x0100 /* IM_CHIP_GT115_EINT */
762#define WM8400_IM_CHIP_GT115_EINT_MASK 0x0100 /* IM_CHIP_GT115_EINT */
763#define WM8400_IM_CHIP_GT115_EINT_SHIFT 8 /* IM_CHIP_GT115_EINT */
764#define WM8400_IM_CHIP_GT115_EINT_WIDTH 1 /* IM_CHIP_GT115_EINT */
765#define WM8400_IM_LINE_CMP_EINT 0x0080 /* IM_LINE_CMP_EINT */
766#define WM8400_IM_LINE_CMP_EINT_MASK 0x0080 /* IM_LINE_CMP_EINT */
767#define WM8400_IM_LINE_CMP_EINT_SHIFT 7 /* IM_LINE_CMP_EINT */
768#define WM8400_IM_LINE_CMP_EINT_WIDTH 1 /* IM_LINE_CMP_EINT */
769#define WM8400_IM_UVLO_EINT 0x0040 /* IM_UVLO_EINT */
770#define WM8400_IM_UVLO_EINT_MASK 0x0040 /* IM_UVLO_EINT */
771#define WM8400_IM_UVLO_EINT_SHIFT 6 /* IM_UVLO_EINT */
772#define WM8400_IM_UVLO_EINT_WIDTH 1 /* IM_UVLO_EINT */
773#define WM8400_IM_DC2_UV_EINT 0x0020 /* IM_DC2_UV_EINT */
774#define WM8400_IM_DC2_UV_EINT_MASK 0x0020 /* IM_DC2_UV_EINT */
775#define WM8400_IM_DC2_UV_EINT_SHIFT 5 /* IM_DC2_UV_EINT */
776#define WM8400_IM_DC2_UV_EINT_WIDTH 1 /* IM_DC2_UV_EINT */
777#define WM8400_IM_DC1_UV_EINT 0x0010 /* IM_DC1_UV_EINT */
778#define WM8400_IM_DC1_UV_EINT_MASK 0x0010 /* IM_DC1_UV_EINT */
779#define WM8400_IM_DC1_UV_EINT_SHIFT 4 /* IM_DC1_UV_EINT */
780#define WM8400_IM_DC1_UV_EINT_WIDTH 1 /* IM_DC1_UV_EINT */
781#define WM8400_IM_LDO4_UV_EINT 0x0008 /* IM_LDO4_UV_EINT */
782#define WM8400_IM_LDO4_UV_EINT_MASK 0x0008 /* IM_LDO4_UV_EINT */
783#define WM8400_IM_LDO4_UV_EINT_SHIFT 3 /* IM_LDO4_UV_EINT */
784#define WM8400_IM_LDO4_UV_EINT_WIDTH 1 /* IM_LDO4_UV_EINT */
785#define WM8400_IM_LDO3_UV_EINT 0x0004 /* IM_LDO3_UV_EINT */
786#define WM8400_IM_LDO3_UV_EINT_MASK 0x0004 /* IM_LDO3_UV_EINT */
787#define WM8400_IM_LDO3_UV_EINT_SHIFT 2 /* IM_LDO3_UV_EINT */
788#define WM8400_IM_LDO3_UV_EINT_WIDTH 1 /* IM_LDO3_UV_EINT */
789#define WM8400_IM_LDO2_UV_EINT 0x0002 /* IM_LDO2_UV_EINT */
790#define WM8400_IM_LDO2_UV_EINT_MASK 0x0002 /* IM_LDO2_UV_EINT */
791#define WM8400_IM_LDO2_UV_EINT_SHIFT 1 /* IM_LDO2_UV_EINT */
792#define WM8400_IM_LDO2_UV_EINT_WIDTH 1 /* IM_LDO2_UV_EINT */
793#define WM8400_IM_LDO1_UV_EINT 0x0001 /* IM_LDO1_UV_EINT */
794#define WM8400_IM_LDO1_UV_EINT_MASK 0x0001 /* IM_LDO1_UV_EINT */
795#define WM8400_IM_LDO1_UV_EINT_SHIFT 0 /* IM_LDO1_UV_EINT */
796#define WM8400_IM_LDO1_UV_EINT_WIDTH 1 /* IM_LDO1_UV_EINT */
797
798/*
799 * R81 (0x51) - Interrupt Levels
800 */
801#define WM8400_MICD_LVL 0x8000 /* MICD_LVL */
802#define WM8400_MICD_LVL_MASK 0x8000 /* MICD_LVL */
803#define WM8400_MICD_LVL_SHIFT 15 /* MICD_LVL */
804#define WM8400_MICD_LVL_WIDTH 1 /* MICD_LVL */
805#define WM8400_MICSCD_LVL 0x4000 /* MICSCD_LVL */
806#define WM8400_MICSCD_LVL_MASK 0x4000 /* MICSCD_LVL */
807#define WM8400_MICSCD_LVL_SHIFT 14 /* MICSCD_LVL */
808#define WM8400_MICSCD_LVL_WIDTH 1 /* MICSCD_LVL */
809#define WM8400_JDL_LVL 0x2000 /* JDL_LVL */
810#define WM8400_JDL_LVL_MASK 0x2000 /* JDL_LVL */
811#define WM8400_JDL_LVL_SHIFT 13 /* JDL_LVL */
812#define WM8400_JDL_LVL_WIDTH 1 /* JDL_LVL */
813#define WM8400_JDR_LVL 0x1000 /* JDR_LVL */
814#define WM8400_JDR_LVL_MASK 0x1000 /* JDR_LVL */
815#define WM8400_JDR_LVL_SHIFT 12 /* JDR_LVL */
816#define WM8400_JDR_LVL_WIDTH 1 /* JDR_LVL */
817#define WM8400_CODEC_SEQ_END_LVL 0x0800 /* CODEC_SEQ_END_LVL */
818#define WM8400_CODEC_SEQ_END_LVL_MASK 0x0800 /* CODEC_SEQ_END_LVL */
819#define WM8400_CODEC_SEQ_END_LVL_SHIFT 11 /* CODEC_SEQ_END_LVL */
820#define WM8400_CODEC_SEQ_END_LVL_WIDTH 1 /* CODEC_SEQ_END_LVL */
821#define WM8400_CDEL_TO_LVL 0x0400 /* CDEL_TO_LVL */
822#define WM8400_CDEL_TO_LVL_MASK 0x0400 /* CDEL_TO_LVL */
823#define WM8400_CDEL_TO_LVL_SHIFT 10 /* CDEL_TO_LVL */
824#define WM8400_CDEL_TO_LVL_WIDTH 1 /* CDEL_TO_LVL */
825#define WM8400_CHIP_GT150_LVL 0x0200 /* CHIP_GT150_LVL */
826#define WM8400_CHIP_GT150_LVL_MASK 0x0200 /* CHIP_GT150_LVL */
827#define WM8400_CHIP_GT150_LVL_SHIFT 9 /* CHIP_GT150_LVL */
828#define WM8400_CHIP_GT150_LVL_WIDTH 1 /* CHIP_GT150_LVL */
829#define WM8400_CHIP_GT115_LVL 0x0100 /* CHIP_GT115_LVL */
830#define WM8400_CHIP_GT115_LVL_MASK 0x0100 /* CHIP_GT115_LVL */
831#define WM8400_CHIP_GT115_LVL_SHIFT 8 /* CHIP_GT115_LVL */
832#define WM8400_CHIP_GT115_LVL_WIDTH 1 /* CHIP_GT115_LVL */
833#define WM8400_LINE_CMP_LVL 0x0080 /* LINE_CMP_LVL */
834#define WM8400_LINE_CMP_LVL_MASK 0x0080 /* LINE_CMP_LVL */
835#define WM8400_LINE_CMP_LVL_SHIFT 7 /* LINE_CMP_LVL */
836#define WM8400_LINE_CMP_LVL_WIDTH 1 /* LINE_CMP_LVL */
837#define WM8400_UVLO_LVL 0x0040 /* UVLO_LVL */
838#define WM8400_UVLO_LVL_MASK 0x0040 /* UVLO_LVL */
839#define WM8400_UVLO_LVL_SHIFT 6 /* UVLO_LVL */
840#define WM8400_UVLO_LVL_WIDTH 1 /* UVLO_LVL */
841#define WM8400_DC2_UV_LVL 0x0020 /* DC2_UV_LVL */
842#define WM8400_DC2_UV_LVL_MASK 0x0020 /* DC2_UV_LVL */
843#define WM8400_DC2_UV_LVL_SHIFT 5 /* DC2_UV_LVL */
844#define WM8400_DC2_UV_LVL_WIDTH 1 /* DC2_UV_LVL */
845#define WM8400_DC1_UV_LVL 0x0010 /* DC1_UV_LVL */
846#define WM8400_DC1_UV_LVL_MASK 0x0010 /* DC1_UV_LVL */
847#define WM8400_DC1_UV_LVL_SHIFT 4 /* DC1_UV_LVL */
848#define WM8400_DC1_UV_LVL_WIDTH 1 /* DC1_UV_LVL */
849#define WM8400_LDO4_UV_LVL 0x0008 /* LDO4_UV_LVL */
850#define WM8400_LDO4_UV_LVL_MASK 0x0008 /* LDO4_UV_LVL */
851#define WM8400_LDO4_UV_LVL_SHIFT 3 /* LDO4_UV_LVL */
852#define WM8400_LDO4_UV_LVL_WIDTH 1 /* LDO4_UV_LVL */
853#define WM8400_LDO3_UV_LVL 0x0004 /* LDO3_UV_LVL */
854#define WM8400_LDO3_UV_LVL_MASK 0x0004 /* LDO3_UV_LVL */
855#define WM8400_LDO3_UV_LVL_SHIFT 2 /* LDO3_UV_LVL */
856#define WM8400_LDO3_UV_LVL_WIDTH 1 /* LDO3_UV_LVL */
857#define WM8400_LDO2_UV_LVL 0x0002 /* LDO2_UV_LVL */
858#define WM8400_LDO2_UV_LVL_MASK 0x0002 /* LDO2_UV_LVL */
859#define WM8400_LDO2_UV_LVL_SHIFT 1 /* LDO2_UV_LVL */
860#define WM8400_LDO2_UV_LVL_WIDTH 1 /* LDO2_UV_LVL */
861#define WM8400_LDO1_UV_LVL 0x0001 /* LDO1_UV_LVL */
862#define WM8400_LDO1_UV_LVL_MASK 0x0001 /* LDO1_UV_LVL */
863#define WM8400_LDO1_UV_LVL_SHIFT 0 /* LDO1_UV_LVL */
864#define WM8400_LDO1_UV_LVL_WIDTH 1 /* LDO1_UV_LVL */
865
866/*
867 * R82 (0x52) - Shutdown Reason
868 */
869#define WM8400_SDR_CHIP_SOFTSD 0x2000 /* SDR_CHIP_SOFTSD */
870#define WM8400_SDR_CHIP_SOFTSD_MASK 0x2000 /* SDR_CHIP_SOFTSD */
871#define WM8400_SDR_CHIP_SOFTSD_SHIFT 13 /* SDR_CHIP_SOFTSD */
872#define WM8400_SDR_CHIP_SOFTSD_WIDTH 1 /* SDR_CHIP_SOFTSD */
873#define WM8400_SDR_NPDN 0x0800 /* SDR_NPDN */
874#define WM8400_SDR_NPDN_MASK 0x0800 /* SDR_NPDN */
875#define WM8400_SDR_NPDN_SHIFT 11 /* SDR_NPDN */
876#define WM8400_SDR_NPDN_WIDTH 1 /* SDR_NPDN */
877#define WM8400_SDR_CHIP_GT150 0x0200 /* SDR_CHIP_GT150 */
878#define WM8400_SDR_CHIP_GT150_MASK 0x0200 /* SDR_CHIP_GT150 */
879#define WM8400_SDR_CHIP_GT150_SHIFT 9 /* SDR_CHIP_GT150 */
880#define WM8400_SDR_CHIP_GT150_WIDTH 1 /* SDR_CHIP_GT150 */
881#define WM8400_SDR_CHIP_GT115 0x0100 /* SDR_CHIP_GT115 */
882#define WM8400_SDR_CHIP_GT115_MASK 0x0100 /* SDR_CHIP_GT115 */
883#define WM8400_SDR_CHIP_GT115_SHIFT 8 /* SDR_CHIP_GT115 */
884#define WM8400_SDR_CHIP_GT115_WIDTH 1 /* SDR_CHIP_GT115 */
885#define WM8400_SDR_LINE_CMP 0x0080 /* SDR_LINE_CMP */
886#define WM8400_SDR_LINE_CMP_MASK 0x0080 /* SDR_LINE_CMP */
887#define WM8400_SDR_LINE_CMP_SHIFT 7 /* SDR_LINE_CMP */
888#define WM8400_SDR_LINE_CMP_WIDTH 1 /* SDR_LINE_CMP */
889#define WM8400_SDR_UVLO 0x0040 /* SDR_UVLO */
890#define WM8400_SDR_UVLO_MASK 0x0040 /* SDR_UVLO */
891#define WM8400_SDR_UVLO_SHIFT 6 /* SDR_UVLO */
892#define WM8400_SDR_UVLO_WIDTH 1 /* SDR_UVLO */
893#define WM8400_SDR_DC2_UV 0x0020 /* SDR_DC2_UV */
894#define WM8400_SDR_DC2_UV_MASK 0x0020 /* SDR_DC2_UV */
895#define WM8400_SDR_DC2_UV_SHIFT 5 /* SDR_DC2_UV */
896#define WM8400_SDR_DC2_UV_WIDTH 1 /* SDR_DC2_UV */
897#define WM8400_SDR_DC1_UV 0x0010 /* SDR_DC1_UV */
898#define WM8400_SDR_DC1_UV_MASK 0x0010 /* SDR_DC1_UV */
899#define WM8400_SDR_DC1_UV_SHIFT 4 /* SDR_DC1_UV */
900#define WM8400_SDR_DC1_UV_WIDTH 1 /* SDR_DC1_UV */
901#define WM8400_SDR_LDO4_UV 0x0008 /* SDR_LDO4_UV */
902#define WM8400_SDR_LDO4_UV_MASK 0x0008 /* SDR_LDO4_UV */
903#define WM8400_SDR_LDO4_UV_SHIFT 3 /* SDR_LDO4_UV */
904#define WM8400_SDR_LDO4_UV_WIDTH 1 /* SDR_LDO4_UV */
905#define WM8400_SDR_LDO3_UV 0x0004 /* SDR_LDO3_UV */
906#define WM8400_SDR_LDO3_UV_MASK 0x0004 /* SDR_LDO3_UV */
907#define WM8400_SDR_LDO3_UV_SHIFT 2 /* SDR_LDO3_UV */
908#define WM8400_SDR_LDO3_UV_WIDTH 1 /* SDR_LDO3_UV */
909#define WM8400_SDR_LDO2_UV 0x0002 /* SDR_LDO2_UV */
910#define WM8400_SDR_LDO2_UV_MASK 0x0002 /* SDR_LDO2_UV */
911#define WM8400_SDR_LDO2_UV_SHIFT 1 /* SDR_LDO2_UV */
912#define WM8400_SDR_LDO2_UV_WIDTH 1 /* SDR_LDO2_UV */
913#define WM8400_SDR_LDO1_UV 0x0001 /* SDR_LDO1_UV */
914#define WM8400_SDR_LDO1_UV_MASK 0x0001 /* SDR_LDO1_UV */
915#define WM8400_SDR_LDO1_UV_SHIFT 0 /* SDR_LDO1_UV */
916#define WM8400_SDR_LDO1_UV_WIDTH 1 /* SDR_LDO1_UV */
917
918/*
919 * R84 (0x54) - Line Circuits
920 */
921#define WM8400_BG_LINE_COMP 0x8000 /* BG_LINE_COMP */
922#define WM8400_BG_LINE_COMP_MASK 0x8000 /* BG_LINE_COMP */
923#define WM8400_BG_LINE_COMP_SHIFT 15 /* BG_LINE_COMP */
924#define WM8400_BG_LINE_COMP_WIDTH 1 /* BG_LINE_COMP */
925#define WM8400_LINE_CMP_VTHI_MASK 0x00F0 /* LINE_CMP_VTHI - [7:4] */
926#define WM8400_LINE_CMP_VTHI_SHIFT 4 /* LINE_CMP_VTHI - [7:4] */
927#define WM8400_LINE_CMP_VTHI_WIDTH 4 /* LINE_CMP_VTHI - [7:4] */
928#define WM8400_LINE_CMP_VTHD_MASK 0x000F /* LINE_CMP_VTHD - [3:0] */
929#define WM8400_LINE_CMP_VTHD_SHIFT 0 /* LINE_CMP_VTHD - [3:0] */
930#define WM8400_LINE_CMP_VTHD_WIDTH 4 /* LINE_CMP_VTHD - [3:0] */
931
932u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg);
933int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data);
934int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val);
935
936#endif
diff --git a/include/linux/mfd/wm8400.h b/include/linux/mfd/wm8400.h
new file mode 100644
index 000000000000..b46b566ac1ac
--- /dev/null
+++ b/include/linux/mfd/wm8400.h
@@ -0,0 +1,40 @@
1/*
2 * wm8400 client interface
3 *
4 * Copyright 2008 Wolfson Microelectronics plc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef __LINUX_MFD_WM8400_H
22#define __LINUX_MFD_WM8400_H
23
24#include <linux/regulator/machine.h>
25
26#define WM8400_LDO1 0
27#define WM8400_LDO2 1
28#define WM8400_LDO3 2
29#define WM8400_LDO4 3
30#define WM8400_DCDC1 4
31#define WM8400_DCDC2 5
32
33struct wm8400_platform_data {
34 int (*platform_init)(struct device *dev);
35};
36
37int wm8400_register_regulator(struct device *dev, int reg,
38 struct regulator_init_data *initdata);
39
40#endif
diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h
index 1d712c7172a2..e37d80561985 100644
--- a/include/linux/regulator/driver.h
+++ b/include/linux/regulator/driver.h
@@ -18,8 +18,8 @@
18#include <linux/device.h> 18#include <linux/device.h>
19#include <linux/regulator/consumer.h> 19#include <linux/regulator/consumer.h>
20 20
21struct regulator_constraints;
22struct regulator_dev; 21struct regulator_dev;
22struct regulator_init_data;
23 23
24/** 24/**
25 * struct regulator_ops - regulator operations. 25 * struct regulator_ops - regulator operations.
@@ -51,7 +51,7 @@ struct regulator_ops {
51 int output_uV, int load_uA); 51 int output_uV, int load_uA);
52 52
53 /* the operations below are for configuration of regulator state when 53 /* the operations below are for configuration of regulator state when
54 * it's parent PMIC enters a global STANBY/HIBERNATE state */ 54 * its parent PMIC enters a global STANDBY/HIBERNATE state */
55 55
56 /* set regulator suspend voltage */ 56 /* set regulator suspend voltage */
57 int (*set_suspend_voltage) (struct regulator_dev *, int uV); 57 int (*set_suspend_voltage) (struct regulator_dev *, int uV);
@@ -85,15 +85,17 @@ struct regulator_desc {
85 struct module *owner; 85 struct module *owner;
86}; 86};
87 87
88
89struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc, 88struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc,
90 void *reg_data); 89 struct device *dev, void *driver_data);
91void regulator_unregister(struct regulator_dev *rdev); 90void regulator_unregister(struct regulator_dev *rdev);
92 91
93int regulator_notifier_call_chain(struct regulator_dev *rdev, 92int regulator_notifier_call_chain(struct regulator_dev *rdev,
94 unsigned long event, void *data); 93 unsigned long event, void *data);
95 94
96void *rdev_get_drvdata(struct regulator_dev *rdev); 95void *rdev_get_drvdata(struct regulator_dev *rdev);
96struct device *rdev_get_dev(struct regulator_dev *rdev);
97int rdev_get_id(struct regulator_dev *rdev); 97int rdev_get_id(struct regulator_dev *rdev);
98 98
99void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data);
100
99#endif 101#endif
diff --git a/include/linux/regulator/machine.h b/include/linux/regulator/machine.h
index 11e737dbfcf2..c6d69331a81e 100644
--- a/include/linux/regulator/machine.h
+++ b/include/linux/regulator/machine.h
@@ -89,15 +89,33 @@ struct regulation_constraints {
89 unsigned apply_uV:1; /* apply uV constraint iff min == max */ 89 unsigned apply_uV:1; /* apply uV constraint iff min == max */
90}; 90};
91 91
92int regulator_set_supply(const char *regulator, const char *regulator_supply); 92/**
93 * struct regulator_consumer_supply - supply -> device mapping
94 *
95 * This maps a supply name to a device.
96 */
97struct regulator_consumer_supply {
98 struct device *dev; /* consumer */
99 const char *supply; /* consumer supply - e.g. "vcc" */
100};
93 101
94const char *regulator_get_supply(const char *regulator); 102/**
103 * struct regulator_init_data - regulator platform initialisation data.
104 *
105 * Initialisation constraints, our supply and consumers supplies.
106 */
107struct regulator_init_data {
108 struct device *supply_regulator_dev; /* or NULL for LINE */
95 109
96int regulator_set_machine_constraints(const char *regulator, 110 struct regulation_constraints constraints;
97 struct regulation_constraints *constraints);
98 111
99int regulator_set_device_supply(const char *regulator, struct device *dev, 112 int num_consumer_supplies;
100 const char *supply); 113 struct regulator_consumer_supply *consumer_supplies;
114
115 /* optional regulator machine specific init */
116 int (*regulator_init)(void *driver_data);
117 void *driver_data; /* core does not touch this */
118};
101 119
102int regulator_suspend_prepare(suspend_state_t state); 120int regulator_suspend_prepare(suspend_state_t state);
103 121
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-10 07:47:56 -0500