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-rw-r--r--arch/arm/mach-s3c2410/include/mach/dma.h117
-rw-r--r--arch/arm/plat-s3c/include/plat/dma.h127
2 files changed, 130 insertions, 114 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 6cefa56e6a1f..2fbabecf4f6e 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -13,6 +13,7 @@
13#ifndef __ASM_ARCH_DMA_H 13#ifndef __ASM_ARCH_DMA_H
14#define __ASM_ARCH_DMA_H __FILE__ 14#define __ASM_ARCH_DMA_H __FILE__
15 15
16#include <plat/dma.h>
16#include <linux/sysdev.h> 17#include <linux/sysdev.h>
17#include <mach/hardware.h> 18#include <mach/hardware.h>
18 19
@@ -103,32 +104,6 @@ enum s3c2410_dma_loadst {
103 S3C2410_DMALOAD_1LOADED_1RUNNING, 104 S3C2410_DMALOAD_1LOADED_1RUNNING,
104}; 105};
105 106
106enum s3c2410_dma_buffresult {
107 S3C2410_RES_OK,
108 S3C2410_RES_ERR,
109 S3C2410_RES_ABORT
110};
111
112enum s3c2410_dmasrc {
113 S3C2410_DMASRC_HW, /* source is memory */
114 S3C2410_DMASRC_MEM /* source is hardware */
115};
116
117/* enum s3c2410_chan_op
118 *
119 * operation codes passed to the DMA code by the user, and also used
120 * to inform the current channel owner of any changes to the system state
121*/
122
123enum s3c2410_chan_op {
124 S3C2410_DMAOP_START,
125 S3C2410_DMAOP_STOP,
126 S3C2410_DMAOP_PAUSE,
127 S3C2410_DMAOP_RESUME,
128 S3C2410_DMAOP_FLUSH,
129 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
130 S3C2410_DMAOP_STARTED, /* indicate channel started */
131};
132 107
133/* flags */ 108/* flags */
134 109
@@ -138,17 +113,14 @@ enum s3c2410_chan_op {
138 113
139/* dma buffer */ 114/* dma buffer */
140 115
141struct s3c2410_dma_client { 116struct s3c2410_dma_buf;
142 char *name;
143};
144 117
145/* s3c2410_dma_buf_s 118/* s3c2410_dma_buf
146 * 119 *
147 * internally used buffer structure to describe a queued or running 120 * internally used buffer structure to describe a queued or running
148 * buffer. 121 * buffer.
149*/ 122*/
150 123
151struct s3c2410_dma_buf;
152struct s3c2410_dma_buf { 124struct s3c2410_dma_buf {
153 struct s3c2410_dma_buf *next; 125 struct s3c2410_dma_buf *next;
154 int magic; /* magic */ 126 int magic; /* magic */
@@ -160,20 +132,6 @@ struct s3c2410_dma_buf {
160 132
161/* [1] is this updated for both recv/send modes? */ 133/* [1] is this updated for both recv/send modes? */
162 134
163struct s3c2410_dma_chan;
164
165/* s3c2410_dma_cbfn_t
166 *
167 * buffer callback routine type
168*/
169
170typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
171 void *buf, int size,
172 enum s3c2410_dma_buffresult result);
173
174typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
175 enum s3c2410_chan_op );
176
177struct s3c2410_dma_stats { 135struct s3c2410_dma_stats {
178 unsigned long loads; 136 unsigned long loads;
179 unsigned long timeout_longest; 137 unsigned long timeout_longest;
@@ -241,73 +199,4 @@ extern struct s3c2410_dma_chan s3c2410_chans[];
241/* note, we don't really use dma_device_t at the moment */ 199/* note, we don't really use dma_device_t at the moment */
242typedef unsigned long dma_device_t; 200typedef unsigned long dma_device_t;
243 201
244/* functions --------------------------------------------------------------- */
245
246/* s3c2410_dma_request
247 *
248 * request a dma channel exclusivley
249*/
250
251extern int s3c2410_dma_request(unsigned int channel,
252 struct s3c2410_dma_client *, void *dev);
253
254
255/* s3c2410_dma_ctrl
256 *
257 * change the state of the dma channel
258*/
259
260extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
261
262/* s3c2410_dma_setflags
263 *
264 * set the channel's flags to a given state
265*/
266
267extern int s3c2410_dma_setflags(unsigned int channel,
268 unsigned int flags);
269
270/* s3c2410_dma_free
271 *
272 * free the dma channel (will also abort any outstanding operations)
273*/
274
275extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
276
277/* s3c2410_dma_enqueue
278 *
279 * place the given buffer onto the queue of operations for the channel.
280 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
281 * drained before the buffer is given to the DMA system.
282*/
283
284extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
285 dma_addr_t data, int size);
286
287/* s3c2410_dma_config
288 *
289 * configure the dma channel
290*/
291
292extern int s3c2410_dma_config(unsigned int channel, int xferunit);
293
294/* s3c2410_dma_devconfig
295 *
296 * configure the device we're talking to
297*/
298
299extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
300 unsigned long devaddr);
301
302/* s3c2410_dma_getposition
303 *
304 * get the position that the dma transfer is currently at
305*/
306
307extern int s3c2410_dma_getposition(unsigned int channel,
308 dma_addr_t *src, dma_addr_t *dest);
309
310extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
311extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
312
313#endif /* __ASM_ARCH_DMA_H */ 202#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-s3c/include/plat/dma.h b/arch/arm/plat-s3c/include/plat/dma.h
new file mode 100644
index 000000000000..34dba98f08e1
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/dma.h
@@ -0,0 +1,127 @@
1/* arch/arm/plat-s3c/include/plat/dma.h
2 *
3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13enum s3c2410_dma_buffresult {
14 S3C2410_RES_OK,
15 S3C2410_RES_ERR,
16 S3C2410_RES_ABORT
17};
18
19enum s3c2410_dmasrc {
20 S3C2410_DMASRC_HW, /* source is memory */
21 S3C2410_DMASRC_MEM /* source is hardware */
22};
23
24/* enum s3c2410_chan_op
25 *
26 * operation codes passed to the DMA code by the user, and also used
27 * to inform the current channel owner of any changes to the system state
28*/
29
30enum s3c2410_chan_op {
31 S3C2410_DMAOP_START,
32 S3C2410_DMAOP_STOP,
33 S3C2410_DMAOP_PAUSE,
34 S3C2410_DMAOP_RESUME,
35 S3C2410_DMAOP_FLUSH,
36 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
37 S3C2410_DMAOP_STARTED, /* indicate channel started */
38};
39
40struct s3c2410_dma_client {
41 char *name;
42};
43
44struct s3c2410_dma_chan;
45
46/* s3c2410_dma_cbfn_t
47 *
48 * buffer callback routine type
49*/
50
51typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
52 void *buf, int size,
53 enum s3c2410_dma_buffresult result);
54
55typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
56 enum s3c2410_chan_op );
57
58
59
60/* s3c2410_dma_request
61 *
62 * request a dma channel exclusivley
63*/
64
65extern int s3c2410_dma_request(unsigned int channel,
66 struct s3c2410_dma_client *, void *dev);
67
68
69/* s3c2410_dma_ctrl
70 *
71 * change the state of the dma channel
72*/
73
74extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
75
76/* s3c2410_dma_setflags
77 *
78 * set the channel's flags to a given state
79*/
80
81extern int s3c2410_dma_setflags(unsigned int channel,
82 unsigned int flags);
83
84/* s3c2410_dma_free
85 *
86 * free the dma channel (will also abort any outstanding operations)
87*/
88
89extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
90
91/* s3c2410_dma_enqueue
92 *
93 * place the given buffer onto the queue of operations for the channel.
94 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
95 * drained before the buffer is given to the DMA system.
96*/
97
98extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
99 dma_addr_t data, int size);
100
101/* s3c2410_dma_config
102 *
103 * configure the dma channel
104*/
105
106extern int s3c2410_dma_config(unsigned int channel, int xferunit);
107
108/* s3c2410_dma_devconfig
109 *
110 * configure the device we're talking to
111*/
112
113extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
114 unsigned long devaddr);
115
116/* s3c2410_dma_getposition
117 *
118 * get the position that the dma transfer is currently at
119*/
120
121extern int s3c2410_dma_getposition(unsigned int channel,
122 dma_addr_t *src, dma_addr_t *dest);
123
124extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
125extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
126
127
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