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-rw-r--r--arch/sh/cchips/Kconfig5
-rw-r--r--arch/sh/include/asm/hd64461.h146
2 files changed, 74 insertions, 77 deletions
diff --git a/arch/sh/cchips/Kconfig b/arch/sh/cchips/Kconfig
index f43d18373f22..a5ab2eccdaa6 100644
--- a/arch/sh/cchips/Kconfig
+++ b/arch/sh/cchips/Kconfig
@@ -34,11 +34,6 @@ config HD64461_IRQ
34 34
35 Do not change this unless you know what you are doing. 35 Do not change this unless you know what you are doing.
36 36
37config HD64461_IOBASE
38 hex "HD64461 start address"
39 depends on HD64461
40 default "0xb0000000"
41
42config HD64461_ENABLER 37config HD64461_ENABLER
43 bool "HD64461 PCMCIA enabler" 38 bool "HD64461 PCMCIA enabler"
44 depends on HD64461 39 depends on HD64461
diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h
index 52b4b6238277..c16d54563c93 100644
--- a/arch/sh/include/asm/hd64461.h
+++ b/arch/sh/include/asm/hd64461.h
@@ -13,13 +13,15 @@
13#define HD64461_PCC_WINDOW 0x01000000 13#define HD64461_PCC_WINDOW 0x01000000
14 14
15/* Area 6 - Slot 0 - memory and/or IO card */ 15/* Area 6 - Slot 0 - memory and/or IO card */
16#define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000) 16#define HD64461_IOBASE 0xb0000000
17#define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x))
18#define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
17#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ 19#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
18#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ 20#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
19#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ 21#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
20 22
21/* Area 5 - Slot 1 - memory card only */ 23/* Area 5 - Slot 1 - memory card only */
22#define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000) 24#define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
23#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ 25#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
24#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ 26#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
25 27
@@ -41,19 +43,19 @@
41#define HD64461_STBCR_SURTST 0x0001 43#define HD64461_STBCR_SURTST 0x0001
42 44
43/* System Configuration Register */ 45/* System Configuration Register */
44#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02) 46#define HD64461_SYSCR HD64461_IO_OFFSET(0x02)
45 47
46/* CPU Data Bus Control Register */ 48/* CPU Data Bus Control Register */
47#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) 49#define HD64461_SCPUCR HD64461_IO_OFFSET(0x04)
48 50
49/* Base Address Register */ 51/* Base Address Register */
50#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) 52#define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000)
51 53
52/* Line increment address */ 54/* Line increment address */
53#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) 55#define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002)
54 56
55/* Controls LCD controller */ 57/* Controls LCD controller */
56#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004) 58#define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004)
57 59
58/* LCCDR control bits */ 60/* LCCDR control bits */
59#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ 61#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
@@ -64,30 +66,30 @@
64#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ 66#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
65 67
66/* Controls LCD (1) */ 68/* Controls LCD (1) */
67#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010) 69#define HD64461_LDR1 HD64461_IO_OFFSET(0x1010)
68#define HD64461_LDR1_DON 0x01 /* Display On */ 70#define HD64461_LDR1_DON 0x01 /* Display On */
69#define HD64461_LDR1_DINV 0x80 /* Display Invert */ 71#define HD64461_LDR1_DINV 0x80 /* Display Invert */
70 72
71/* Controls LCD (2) */ 73/* Controls LCD (2) */
72#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012) 74#define HD64461_LDR2 HD64461_IO_OFFSET(0x1012)
73#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */ 75#define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */
74#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */ 76#define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */
75#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */ 77#define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */
76#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */ 78#define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */
77#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */ 79#define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */
78 80
79/* Controls LCD (3) */ 81/* Controls LCD (3) */
80#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) 82#define HD64461_LDR3 HD64461_IO_OFFSET(0x101e)
81 83
82/* Palette Registers */ 84/* Palette Registers */
83#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */ 85#define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */
84#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */ 86#define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */
85#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */ 87#define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */
86#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */ 88#define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */
87 89
88#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */ 90#define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */
89#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */ 91#define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */
90#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */ 92#define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */
91 93
92#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ 94#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
93#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ 95#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
@@ -97,41 +99,41 @@
97#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ 99#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
98 100
99/* Line Drawing Registers */ 101/* Line Drawing Registers */
100#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */ 102#define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */
101#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */ 103#define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */
102#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */ 104#define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */
103#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */ 105#define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */
104#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */ 106#define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */
105#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */ 107#define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */
106#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */ 108#define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */
107 109
108/* BitBLT Registers */ 110/* BitBLT Registers */
109#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */ 111#define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */
110#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */ 112#define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */
111#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */ 113#define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */
112#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */ 114#define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */
113#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */ 115#define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */
114#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */ 116#define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */
115#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */ 117#define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */
116#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */ 118#define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */
117#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */ 119#define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */
118#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */ 120#define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */
119#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */ 121#define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */
120#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */ 122#define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */
121 123
122/* PC Card Controller Registers */ 124/* PC Card Controller Registers */
123/* Maps to Physical Area 6 */ 125/* Maps to Physical Area 6 */
124#define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */ 126#define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */
125#define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */ 127#define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */
126#define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */ 128#define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */
127#define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */ 129#define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */
128#define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */ 130#define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */
129/* Maps to Physical Area 5 */ 131/* Maps to Physical Area 5 */
130#define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */ 132#define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */
131#define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */ 133#define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */
132#define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */ 134#define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */
133#define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */ 135#define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */
134#define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */ 136#define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */
135 137
136/* PCC Interface Status Register */ 138/* PCC Interface Status Register */
137#define HD64461_PCCISR_READY 0x80 /* card ready */ 139#define HD64461_PCCISR_READY 0x80 /* card ready */
@@ -189,41 +191,41 @@
189#define HD64461_PCCSCR_SWP 0x01 /* write protect */ 191#define HD64461_PCCSCR_SWP 0x01 /* write protect */
190 192
191/* PCC0 Output Pins Control Register */ 193/* PCC0 Output Pins Control Register */
192#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a) 194#define HD64461_P0OCR HD64461_IO_OFFSET(0x202a)
193 195
194/* PCC1 Output Pins Control Register */ 196/* PCC1 Output Pins Control Register */
195#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c) 197#define HD64461_P1OCR HD64461_IO_OFFSET(0x202c)
196 198
197/* PC Card General Control Register */ 199/* PC Card General Control Register */
198#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e) 200#define HD64461_PGCR HD64461_IO_OFFSET(0x202e)
199 201
200/* Port Control Registers */ 202/* Port Control Registers */
201#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */ 203#define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */
202#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */ 204#define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */
203#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */ 205#define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */
204#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */ 206#define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */
205 207
206/* Port Control Data Registers */ 208/* Port Control Data Registers */
207#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */ 209#define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */
208#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */ 210#define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */
209#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */ 211#define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */
210#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */ 212#define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */
211 213
212/* Interrupt Control Registers */ 214/* Interrupt Control Registers */
213#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */ 215#define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */
214#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */ 216#define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */
215#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */ 217#define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */
216#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */ 218#define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */
217 219
218/* Interrupt Status Registers */ 220/* Interrupt Status Registers */
219#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */ 221#define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */
220#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */ 222#define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */
221#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */ 223#define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */
222#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */ 224#define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */
223 225
224/* Interrupt Request Register & Interrupt Mask Register */ 226/* Interrupt Request Register & Interrupt Mask Register */
225#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000) 227#define HD64461_NIRR HD64461_IO_OFFSET(0x5000)
226#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) 228#define HD64461_NIMR HD64461_IO_OFFSET(0x5002)
227 229
228#define HD64461_IRQBASE OFFCHIP_IRQ_BASE 230#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
229#define OFFCHIP_IRQ_BASE 64 231#define OFFCHIP_IRQ_BASE 64
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-03 06:10:09 -0500