1 files changed, 7 insertions, 3 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 68dcf36e2793..ab8162afb4a7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4695,7 +4695,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         struct drm_gem_object *obj;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_unpin_work *work;
-        unsigned long flags;
+        unsigned long flags, offset;
         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
         int ret, pipesrc;
         u32 flip_mask;
@@ -4762,19 +4762,23 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
                 while (I915_READ(ISR) & flip_mask)
                         ;
 
+        /* Offset into the new buffer for cases of shared fbs between CRTCs */
+        offset = obj_priv->gtt_offset;
+        offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
+
         BEGIN_LP_RING(4);
         if (IS_I965G(dev)) {
                 OUT_RING(MI_DISPLAY_FLIP |
                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
                 OUT_RING(fb->pitch);
-                OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
+                OUT_RING(offset | obj_priv->tiling_mode);
                 pipesrc = I915_READ(pipesrc_reg); 
                 OUT_RING(pipesrc & 0x0fff0fff);
         } else {
                 OUT_RING(MI_DISPLAY_FLIP_I915 |
                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
                 OUT_RING(fb->pitch);
-                OUT_RING(obj_priv->gtt_offset);
+                OUT_RING(offset);
                 OUT_RING(MI_NOOP);
         }
         ADVANCE_LP_RING();