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-rw-r--r--arch/arm/mach-u300/gpio.c701
-rw-r--r--arch/arm/mach-u300/include/mach/gpio.h290
-rw-r--r--arch/arm/mach-u300/padmux.c58
-rw-r--r--arch/arm/mach-u300/padmux.h19
4 files changed, 1068 insertions, 0 deletions
diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c
new file mode 100644
index 000000000000..2d5ae8ecb8c8
--- /dev/null
+++ b/arch/arm/mach-u300/gpio.c
@@ -0,0 +1,701 @@
1/*
2 *
3 * arch/arm/mach-u300/gpio.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * U300 GPIO module.
9 * This can driver either of the two basic GPIO cores
10 * available in the U300 platforms:
11 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
12 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
13 * Notice that you also have inline macros in <asm-arch/gpio.h>
14 * Author: Linus Walleij <linus.walleij@stericsson.com>
15 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
16 *
17 */
18#include <linux/module.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/errno.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/platform_device.h>
26#include <linux/gpio.h>
27
28/* Need access to SYSCON registers for PADmuxing */
29#include <mach/syscon.h>
30
31#include "padmux.h"
32
33/* Reference to GPIO block clock */
34static struct clk *clk;
35
36/* Memory resource */
37static struct resource *memres;
38static void __iomem *virtbase;
39
40struct u300_gpio_port {
41 const char *name;
42 int irq;
43 int number;
44};
45
46
47static struct u300_gpio_port gpio_ports[] = {
48 {
49 .name = "gpio0",
50 .number = 0,
51 },
52 {
53 .name = "gpio1",
54 .number = 1,
55 },
56 {
57 .name = "gpio2",
58 .number = 2,
59 },
60#ifdef U300_COH901571_3
61 {
62 .name = "gpio3",
63 .number = 3,
64 },
65 {
66 .name = "gpio4",
67 .number = 4,
68 },
69#ifdef CONFIG_MACH_U300_BS335
70 {
71 .name = "gpio5",
72 .number = 5,
73 },
74 {
75 .name = "gpio6",
76 .number = 6,
77 },
78#endif
79#endif
80
81};
82
83
84#ifdef U300_COH901571_3
85
86/* Default input value */
87#define DEFAULT_OUTPUT_LOW 0
88#define DEFAULT_OUTPUT_HIGH 1
89
90/* GPIO Pull-Up status */
91#define DISABLE_PULL_UP 0
92#define ENABLE_PULL_UP 1
93
94#define GPIO_NOT_USED 0
95#define GPIO_IN 1
96#define GPIO_OUT 2
97
98struct u300_gpio_configuration_data {
99 unsigned char pin_usage;
100 unsigned char default_output_value;
101 unsigned char pull_up;
102};
103
104/* Initial configuration */
105const struct u300_gpio_configuration_data
106u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
107#ifdef CONFIG_MACH_U300_BS335
108 /* Port 0, pins 0-7 */
109 {
110 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
111 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
112 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
113 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
114 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
115 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
116 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
117 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
118 },
119 /* Port 1, pins 0-7 */
120 {
121 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
122 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
123 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
124 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
125 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
126 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
127 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
128 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
129 },
130 /* Port 2, pins 0-7 */
131 {
132 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
133 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
134 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
135 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
136 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
137 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
138 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
139 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
140 },
141 /* Port 3, pins 0-7 */
142 {
143 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
144 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
145 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
146 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
147 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
148 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
149 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
150 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
151 },
152 /* Port 4, pins 0-7 */
153 {
154 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
155 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
156 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
157 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
158 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
159 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
160 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
161 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
162 },
163 /* Port 5, pins 0-7 */
164 {
165 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
166 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
167 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
168 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
169 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
170 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
171 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
172 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
173 },
174 /* Port 6, pind 0-7 */
175 {
176 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
177 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
178 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
179 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
180 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
181 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
182 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
183 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
184 }
185#endif
186
187#ifdef CONFIG_MACH_U300_BS365
188 /* Port 0, pins 0-7 */
189 {
190 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
191 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
192 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
193 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
194 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
195 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
196 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
197 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
198 },
199 /* Port 1, pins 0-7 */
200 {
201 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
202 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
203 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
204 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
205 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
206 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
207 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
208 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
209 },
210 /* Port 2, pins 0-7 */
211 {
212 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
213 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
214 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
215 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
216 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
217 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
218 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
219 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
220 },
221 /* Port 3, pins 0-7 */
222 {
223 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
224 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
225 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
226 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
227 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
228 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
229 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
230 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
231 },
232 /* Port 4, pins 0-7 */
233 {
234 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
235 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
236 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
237 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
238 /* These 4 pins doesn't exist on DB3210 */
239 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
240 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
241 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
242 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
243 }
244#endif
245};
246#endif
247
248
249/* No users == we can power down GPIO */
250static int gpio_users;
251
252struct gpio_struct {
253 int (*callback)(void *);
254 void *data;
255 int users;
256};
257
258static struct gpio_struct gpio_pin[U300_GPIO_MAX];
259
260/*
261 * Let drivers register callback in order to get notified when there is
262 * an interrupt on the gpio pin
263 */
264int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data)
265{
266 if (gpio_pin[gpio].callback)
267 printk(KERN_WARNING "GPIO: %s: WARNING: callback already " \
268 "registered for gpio pin#%d\n", __func__, gpio);
269 gpio_pin[gpio].callback = func;
270 gpio_pin[gpio].data = data;
271
272 return 0;
273}
274EXPORT_SYMBOL(gpio_register_callback);
275
276int gpio_unregister_callback(unsigned gpio)
277{
278 if (!gpio_pin[gpio].callback)
279 printk(KERN_WARNING "GPIO: %s: WARNING: callback already " \
280 "unregistered for gpio pin#%d\n", __func__, gpio);
281 gpio_pin[gpio].callback = NULL;
282 gpio_pin[gpio].data = NULL;
283
284 return 0;
285}
286EXPORT_SYMBOL(gpio_unregister_callback);
287
288int gpio_request(unsigned gpio, const char *label)
289{
290 if (gpio_pin[gpio].users)
291 return -EINVAL;
292 else
293 gpio_pin[gpio].users++;
294
295 gpio_users++;
296
297 return 0;
298}
299EXPORT_SYMBOL(gpio_request);
300
301void gpio_free(unsigned gpio)
302{
303 gpio_users--;
304 gpio_pin[gpio].users--;
305 if (unlikely(gpio_pin[gpio].users < 0)) {
306 printk(KERN_WARNING "GPIO: Warning: gpio#%d release mismatch\n",
307 gpio);
308 gpio_pin[gpio].users = 0;
309 }
310
311 return;
312}
313EXPORT_SYMBOL(gpio_free);
314
315/* This returns zero or nonzero */
316int gpio_get_value(unsigned gpio)
317{
318 return readl(virtbase + U300_GPIO_PXPDIR +
319 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07));
320}
321EXPORT_SYMBOL(gpio_get_value);
322
323/*
324 * We hope that the compiler will optimize away the unused branch
325 * in case "value" is a constant
326 */
327void gpio_set_value(unsigned gpio, int value)
328{
329 u32 val;
330 unsigned long flags;
331
332 local_irq_save(flags);
333 if (value) {
334 /* set */
335 val = readl(virtbase + U300_GPIO_PXPDOR +
336 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
337 & (1 << (gpio & 0x07));
338 writel(val | (1 << (gpio & 0x07)), virtbase +
339 U300_GPIO_PXPDOR +
340 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
341 } else {
342 /* clear */
343 val = readl(virtbase + U300_GPIO_PXPDOR +
344 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
345 & (1 << (gpio & 0x07));
346 writel(val & ~(1 << (gpio & 0x07)), virtbase +
347 U300_GPIO_PXPDOR +
348 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
349 }
350 local_irq_restore(flags);
351}
352EXPORT_SYMBOL(gpio_set_value);
353
354int gpio_direction_input(unsigned gpio)
355{
356 unsigned long flags;
357 u32 val;
358
359 if (gpio > U300_GPIO_MAX)
360 return -EINVAL;
361
362 local_irq_save(flags);
363 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
364 U300_GPIO_PORTX_SPACING);
365 /* Mask out this pin*/
366 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
367 /* This is not needed since it sets the bits to zero.*/
368 /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */
369 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
370 U300_GPIO_PORTX_SPACING);
371 local_irq_restore(flags);
372 return 0;
373}
374EXPORT_SYMBOL(gpio_direction_input);
375
376int gpio_direction_output(unsigned gpio, int value)
377{
378 unsigned long flags;
379 u32 val;
380
381 if (gpio > U300_GPIO_MAX)
382 return -EINVAL;
383
384 local_irq_save(flags);
385 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
386 U300_GPIO_PORTX_SPACING);
387 /* Mask out this pin */
388 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
389 /*
390 * FIXME: configure for push/pull, open drain or open source per pin
391 * in setup. The current driver will only support push/pull.
392 */
393 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
394 << ((gpio & 0x07) << 1));
395 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
396 U300_GPIO_PORTX_SPACING);
397 gpio_set_value(gpio, value);
398 local_irq_restore(flags);
399 return 0;
400}
401EXPORT_SYMBOL(gpio_direction_output);
402
403/*
404 * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0).
405 */
406void enable_irq_on_gpio_pin(unsigned gpio, int edge)
407{
408 u32 val;
409 unsigned long flags;
410 local_irq_save(flags);
411
412 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
413 U300_GPIO_PORTX_SPACING);
414 val |= (1 << (gpio & 0x07));
415 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
416 U300_GPIO_PORTX_SPACING);
417 val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
418 U300_GPIO_PORTX_SPACING);
419 if (edge)
420 val |= (1 << (gpio & 0x07));
421 else
422 val &= ~(1 << (gpio & 0x07));
423 writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
424 U300_GPIO_PORTX_SPACING);
425 local_irq_restore(flags);
426}
427EXPORT_SYMBOL(enable_irq_on_gpio_pin);
428
429void disable_irq_on_gpio_pin(unsigned gpio)
430{
431 u32 val;
432 unsigned long flags;
433
434 local_irq_save(flags);
435 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
436 U300_GPIO_PORTX_SPACING);
437 val &= ~(1 << (gpio & 0x07));
438 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
439 U300_GPIO_PORTX_SPACING);
440 local_irq_restore(flags);
441}
442EXPORT_SYMBOL(disable_irq_on_gpio_pin);
443
444/* Enable (value == 0) or disable (value == 1) internal pullup */
445void gpio_pullup(unsigned gpio, int value)
446{
447 u32 val;
448 unsigned long flags;
449
450 local_irq_save(flags);
451 if (value) {
452 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
453 U300_GPIO_PORTX_SPACING);
454 writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
455 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
456 } else {
457 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
458 U300_GPIO_PORTX_SPACING);
459 writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
460 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
461 }
462 local_irq_restore(flags);
463}
464EXPORT_SYMBOL(gpio_pullup);
465
466static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
467{
468 struct u300_gpio_port *port = dev_id;
469 u32 val;
470 int pin;
471
472 /* Read event register */
473 val = readl(virtbase + U300_GPIO_PXIEV + port->number *
474 U300_GPIO_PORTX_SPACING);
475 /* Mask with enable register */
476 val &= readl(virtbase + U300_GPIO_PXIEV + port->number *
477 U300_GPIO_PORTX_SPACING);
478 /* Mask relevant bits */
479 val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK;
480 /* ACK IRQ (clear event) */
481 writel(val, virtbase + U300_GPIO_PXIEV + port->number *
482 U300_GPIO_PORTX_SPACING);
483 /* Print message */
484 while (val != 0) {
485 unsigned gpio;
486
487 pin = __ffs(val);
488 /* mask off this pin */
489 val &= ~(1 << pin);
490 gpio = (port->number << 3) + pin;
491
492 if (gpio_pin[gpio].callback)
493 (void)gpio_pin[gpio].callback(gpio_pin[gpio].data);
494 else
495 printk(KERN_DEBUG "GPIO: Stray GPIO IRQ on line %d\n",
496 gpio);
497 }
498 return IRQ_HANDLED;
499}
500
501static void gpio_set_initial_values(void)
502{
503#ifdef U300_COH901571_3
504 int i, j;
505 unsigned long flags;
506 u32 val;
507
508 /* Write default values to all pins */
509 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
510 val = 0;
511 for (j = 0; j < 8; j++)
512 val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j;
513 local_irq_save(flags);
514 writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING);
515 local_irq_restore(flags);
516 }
517
518 /*
519 * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED'
520 * to output and 'GPIO_IN' to input for each port. And initalize
521 * default value on outputs.
522 */
523 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
524 for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) {
525 local_irq_save(flags);
526 val = readl(virtbase + U300_GPIO_PXPCR +
527 i * U300_GPIO_PORTX_SPACING);
528 /* Mask out this pin */
529 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1));
530
531 if (u300_gpio_config[i][j].pin_usage != GPIO_IN)
532 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1));
533 writel(val, virtbase + U300_GPIO_PXPCR +
534 i * U300_GPIO_PORTX_SPACING);
535 local_irq_restore(flags);
536 }
537 }
538
539 /* Enable or disable the internal pull-ups in the GPIO ASIC block */
540 for (i = 0; i < U300_GPIO_MAX; i++) {
541 val = 0;
542 for (j = 0; j < 8; j++)
543 val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP)) << j;
544 local_irq_save(flags);
545 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
546 local_irq_restore(flags);
547 }
548#endif
549}
550
551static int __devinit gpio_probe(struct platform_device *pdev)
552{
553 u32 val;
554 int err = 0;
555 int i;
556 int num_irqs;
557
558 memset(gpio_pin, 0, sizeof(gpio_pin));
559
560 /* Get GPIO clock */
561 clk = clk_get(&pdev->dev, NULL);
562 if (IS_ERR(clk)) {
563 err = PTR_ERR(clk);
564 printk(KERN_ERR "GPIO: could not get GPIO clock\n");
565 goto err_no_clk;
566 }
567 err = clk_enable(clk);
568 if (err) {
569 printk(KERN_ERR "GPIO: could not enable GPIO clock\n");
570 goto err_no_clk_enable;
571 }
572
573 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
574 if (!memres)
575 goto err_no_resource;
576
577 if (request_mem_region(memres->start, memres->end - memres->start, "GPIO Controller")
578 == NULL) {
579 err = -ENODEV;
580 goto err_no_ioregion;
581 }
582
583 virtbase = ioremap(memres->start, memres->end - memres->start + 1);
584 if (!virtbase) {
585 err = -ENOMEM;
586 goto err_no_ioremap;
587 }
588
589#ifdef U300_COH901335
590 printk(KERN_INFO "GPIO: Initializing GPIO Controller COH 901 335\n");
591 /* Turn on the GPIO block */
592 writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR);
593#endif
594
595#ifdef U300_COH901571_3
596 printk(KERN_INFO "GPIO: Initializing GPIO Controller COH 901 571/3\n");
597 val = readl(virtbase + U300_GPIO_CR);
598 printk(KERN_INFO "GPIO: COH901571/3 block version: %d, " \
599 "number of cores: %d\n",
600 ((val & 0x0000FE00) >> 9),
601 ((val & 0x000001FC) >> 2));
602 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR);
603#endif
604
605 /* Set up some padmuxing here */
606#ifdef CONFIG_MMC
607 pmx_set_mission_mode_mmc();
608#endif
609#ifdef CONFIG_SPI_PL022
610 pmx_set_mission_mode_spi();
611#endif
612
613 gpio_set_initial_values();
614
615 for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) {
616
617 gpio_ports[num_irqs].irq =
618 platform_get_irq_byname(pdev,
619 gpio_ports[num_irqs].name);
620
621 err = request_irq(gpio_ports[num_irqs].irq,
622 gpio_irq_handler, IRQF_DISABLED,
623 gpio_ports[num_irqs].name,
624 &gpio_ports[num_irqs]);
625 if (err) {
626 printk(KERN_CRIT "GPIO: Cannot allocate IRQ for %s!\n",
627 gpio_ports[num_irqs].name);
628 goto err_no_irq;
629 }
630 /* Turns off PortX_irq_force */
631 writel(0x0, virtbase + U300_GPIO_PXIFR +
632 num_irqs * U300_GPIO_PORTX_SPACING);
633 }
634 printk(KERN_INFO "GPIO: U300 gpio module loaded\n");
635
636 return 0;
637
638 err_no_irq:
639 for (i = 0; i < num_irqs; i++)
640 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
641 iounmap(virtbase);
642 err_no_ioremap:
643 release_mem_region(memres->start, memres->end - memres->start);
644 err_no_ioregion:
645 err_no_resource:
646 clk_disable(clk);
647 err_no_clk_enable:
648 clk_put(clk);
649 err_no_clk:
650 printk(KERN_INFO "GPIO: module ERROR:%d\n", err);
651 return err;
652}
653
654static int __devexit gpio_remove(struct platform_device *pdev)
655{
656 int i;
657
658 /* Turn off the GPIO block */
659 writel(0x00000000U, virtbase + U300_GPIO_CR);
660 for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++)
661 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
662 iounmap(virtbase);
663 release_mem_region(memres->start, memres->end - memres->start);
664 clk_disable(clk);
665 clk_put(clk);
666 return 0;
667}
668
669static struct platform_driver gpio_driver = {
670 .driver = {
671 .name = "u300-gpio",
672 },
673 .probe = gpio_probe,
674 .remove = __devexit_p(gpio_remove),
675};
676
677
678static int __init u300_gpio_init(void)
679{
680 return platform_driver_register(&gpio_driver);
681}
682
683static void __exit u300_gpio_exit(void)
684{
685 platform_driver_unregister(&gpio_driver);
686}
687
688arch_initcall(u300_gpio_init);
689module_exit(u300_gpio_exit);
690
691MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
692
693#ifdef U300_COH901571_3
694MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver");
695#endif
696
697#ifdef U300_COH901335
698MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver");
699#endif
700
701MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
new file mode 100644
index 000000000000..c8174128d7eb
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/gpio.h
@@ -0,0 +1,290 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/gpio.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * GPIO block resgister definitions and inline macros for
9 * U300 GPIO COH 901 335 or COH 901 571/3
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12
13#ifndef __MACH_U300_GPIO_H
14#define __MACH_U300_GPIO_H
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <mach/hardware.h>
19#include <asm/irq.h>
20
21/* Switch type depending on platform/chip variant */
22#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
23#define U300_COH901335
24#endif
25#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
26#define U300_COH901571_3
27#endif
28
29/* Get base address for regs here */
30#include "u300-regs.h"
31/* IRQ numbers */
32#include "irqs.h"
33
34/*
35 * This is the GPIO block definitions. GPIO (General Purpose I/O) can be
36 * used for anything, and often is. The event/enable etc figures are for
37 * the lowermost pin (pin 0 on each port), shift this left to match your
38 * pin if you're gonna use these values.
39 */
40#ifdef U300_COH901335
41#define U300_GPIO_PORTX_SPACING (0x1C)
42/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
43#define U300_GPIO_PXPDIR (0x00)
44#define U300_GPIO_PXPDOR (0x00)
45/* Port X Pin Config Register 32bit (R/W) */
46#define U300_GPIO_PXPCR (0x04)
47#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
48#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
49#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
50#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
51#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
52#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
53#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
54/* Port X Interrupt Event Register 32bit (R/W) */
55#define U300_GPIO_PXIEV (0x08)
56#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
57#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
58/* Port X Interrupt Enable Register 32bit (R/W) */
59#define U300_GPIO_PXIEN (0x0C)
60#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
61#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
62/* Port X Interrupt Force Register 32bit (R/W) */
63#define U300_GPIO_PXIFR (0x10)
64#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
65#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
66/* Port X Interrupt Config Register 32bit (R/W) */
67#define U300_GPIO_PXICR (0x14)
68#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
69#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
70#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
71#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
72/* Port X Pull-up Enable Register 32bit (R/W) */
73#define U300_GPIO_PXPER (0x18)
74#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
75#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
76/* Control Register 32bit (R/W) */
77#define U300_GPIO_CR (0x54)
78#define U300_GPIO_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
79/* three ports of 8 bits each = GPIO pins 0..23 */
80#define U300_GPIO_NUM_PORTS 3
81#define U300_GPIO_PINS_PER_PORT 8
82#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
83#endif
84
85#ifdef U300_COH901571_3
86/*
87 * Control Register 32bit (R/W)
88 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
89 * gives the number of GPIO pins.
90 * bit 8-2 (mask 0x000001FC) contains the core version ID.
91 */
92#define U300_GPIO_CR (0x00)
93#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
94#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
95#define U300_GPIO_PORTX_SPACING (0x30)
96/* Port X Pin Data INPUT Register 32bit (R/W) */
97#define U300_GPIO_PXPDIR (0x04)
98/* Port X Pin Data OUTPUT Register 32bit (R/W) */
99#define U300_GPIO_PXPDOR (0x08)
100/* Port X Pin Config Register 32bit (R/W) */
101#define U300_GPIO_PXPCR (0x0C)
102#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
103#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
104#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
105#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
106#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
107#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
108#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
109/* Port X Pull-up Enable Register 32bit (R/W) */
110#define U300_GPIO_PXPER (0x10)
111#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
112#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
113/* Port X Interrupt Event Register 32bit (R/W) */
114#define U300_GPIO_PXIEV (0x14)
115#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
116#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
117/* Port X Interrupt Enable Register 32bit (R/W) */
118#define U300_GPIO_PXIEN (0x18)
119#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
120#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
121/* Port X Interrupt Force Register 32bit (R/W) */
122#define U300_GPIO_PXIFR (0x1C)
123#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
124#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
125/* Port X Interrupt Config Register 32bit (R/W) */
126#define U300_GPIO_PXICR (0x20)
127#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
128#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
129#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
130#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
131#ifdef CONFIG_MACH_U300_BS335
132/* seven ports of 8 bits each = GPIO pins 0..55 */
133#define U300_GPIO_NUM_PORTS 7
134#else
135/* five ports of 8 bits each = GPIO pins 0..39 */
136#define U300_GPIO_NUM_PORTS 5
137#endif
138#define U300_GPIO_PINS_PER_PORT 8
139#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
140#endif
141
142/*
143 * Individual pin assignments for the B26/S26. Notice that the
144 * actual usage of these pins depends on the PAD MUX settings, that
145 * is why the same number can potentially appear several times.
146 * In the reference design each pin is only used for one purpose.
147 * These were determined by inspecting the B26/S26 schematic:
148 * 2/1911-ROA 128 1603
149 */
150#ifdef CONFIG_MACH_U300_BS2X
151#define U300_GPIO_PIN_UART_RX 0
152#define U300_GPIO_PIN_UART_TX 1
153#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */
154#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */
155#define U300_GPIO_PIN_CAM_SLEEP 4
156#define U300_GPIO_PIN_CAM_REG_EN 5
157#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */
158#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */
159
160#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */
161#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */
162#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */
163#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
164#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
165#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */
166#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */
167#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
168
169#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */
170#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */
171#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */
172#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */
173#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
174#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
175#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
176#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
177#endif
178
179/*
180 * Individual pin assignments for the B330/S330 and B365/S365.
181 * Notice that the actual usage of these pins depends on the
182 * PAD MUX settings, that is why the same number can potentially
183 * appear several times. In the reference design each pin is only
184 * used for one purpose. These were determined by inspecting the
185 * S365 schematic.
186 */
187#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
188 defined(CONFIG_MACH_U300_BS335)
189#define U300_GPIO_PIN_UART_RX 0
190#define U300_GPIO_PIN_UART_TX 1
191#define U300_GPIO_PIN_UART_CTS 2
192#define U300_GPIO_PIN_UART_RTS 3
193#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */
194#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */
195#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */
196#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */
197
198#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */
199#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */
200#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */
201#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
202#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
203#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */
204#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */
205#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
206
207#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */
208#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */
209#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */
210#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */
211#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
212#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
213#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
214#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
215
216#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */
217#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */
218#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */
219#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */
220#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */
221#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */
222#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */
223#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */
224
225#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */
226#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */
227#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */
228#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */
229#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */
230#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */
231#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */
232#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */
233
234#ifdef CONFIG_MACH_U300_BS335
235
236#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */
237#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */
238#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */
239#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */
240#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */
241#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */
242#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */
243#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */
244
245#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */
246#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */
247#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */
248#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */
249#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */
250#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */
251#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */
252#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */
253#endif
254
255#endif
256
257/* translates a pin number to a port number */
258#define PIN_TO_PORT(val) (val >> 3)
259
260/* These can be found in arch/arm/mach-u300/gpio.c */
261extern int gpio_request(unsigned gpio, const char *label);
262extern void gpio_free(unsigned gpio);
263extern int gpio_direction_input(unsigned gpio);
264extern int gpio_direction_output(unsigned gpio, int value);
265extern int gpio_register_callback(unsigned gpio,
266 int (*func)(void *arg),
267 void *);
268extern int gpio_unregister_callback(unsigned gpio);
269extern void enable_irq_on_gpio_pin(unsigned gpio, int edge);
270extern void disable_irq_on_gpio_pin(unsigned gpio);
271extern void gpio_pullup(unsigned gpio, int value);
272extern int gpio_get_value(unsigned gpio);
273extern void gpio_set_value(unsigned gpio, int value);
274
275/* wrappers to sleep-enable the previous two functions */
276static inline unsigned gpio_to_irq(unsigned gpio)
277{
278 return PIN_TO_PORT(gpio) + IRQ_U300_GPIO_PORT0;
279}
280
281static inline unsigned irq_to_gpio(unsigned irq)
282{
283 /*
284 * FIXME: This is no 1-1 mapping at all, it points to the
285 * whole block of 8 pins.
286 */
287 return (irq - IRQ_U300_GPIO_PORT0) << 3;
288}
289
290#endif
diff --git a/arch/arm/mach-u300/padmux.c b/arch/arm/mach-u300/padmux.c
new file mode 100644
index 000000000000..f3664564f086
--- /dev/null
+++ b/arch/arm/mach-u300/padmux.c
@@ -0,0 +1,58 @@
1/*
2 *
3 * arch/arm/mach-u300/padmux.c
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * U300 PADMUX functions
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 *
11 */
12#include <linux/io.h>
13#include <linux/err.h>
14#include <mach/u300-regs.h>
15#include <mach/syscon.h>
16
17#include "padmux.h"
18
19/* Set the PAD MUX to route the MMC reader correctly to GPIO0. */
20void pmx_set_mission_mode_mmc(void)
21{
22 u16 val;
23
24 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1LR);
25 val &= ~U300_SYSCON_PMC1LR_MMCSD_MASK;
26 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1LR);
27 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
28 val &= ~U300_SYSCON_PMC1HR_APP_GPIO_1_MASK;
29 val |= U300_SYSCON_PMC1HR_APP_GPIO_1_MMC;
30 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
31}
32
33void pmx_set_mission_mode_spi(void)
34{
35 u16 val;
36
37 /* Set up padmuxing so the SPI port and its chipselects are active */
38 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
39 /*
40 * Activate the SPI port (disable the use of these pins for generic
41 * GPIO, DSP, AAIF
42 */
43 val &= ~U300_SYSCON_PMC1HR_APP_SPI_2_MASK;
44 val |= U300_SYSCON_PMC1HR_APP_SPI_2_SPI;
45 /*
46 * Use GPIO pin SPI CS1 for CS1 actually (it can be used for other
47 * things also)
48 */
49 val &= ~U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK;
50 val |= U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI;
51 /*
52 * Use GPIO pin SPI CS2 for CS2 actually (it can be used for other
53 * things also)
54 */
55 val &= ~U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK;
56 val |= U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI;
57 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
58}
diff --git a/arch/arm/mach-u300/padmux.h b/arch/arm/mach-u300/padmux.h
new file mode 100644
index 000000000000..8c2099ac5046
--- /dev/null
+++ b/arch/arm/mach-u300/padmux.h
@@ -0,0 +1,19 @@
1/*
2 *
3 * arch/arm/mach-u300/padmux.h
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * U300 PADMUX API
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 *
11 */
12
13#ifndef __MACH_U300_PADMUX_H
14#define __MACH_U300_PADMUX_H
15
16void pmx_set_mission_mode_mmc(void);
17void pmx_set_mission_mode_spi(void);
18
19#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-05 19:13:02 -0500