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-rw-r--r--drivers/media/dvb/dvb-usb/Kconfig16
-rw-r--r--drivers/media/dvb/dvb-usb/Makefile6
-rw-r--r--drivers/media/dvb/dvb-usb/af9005-fe.c1503
-rw-r--r--drivers/media/dvb/dvb-usb/af9005-remote.c157
-rw-r--r--drivers/media/dvb/dvb-usb/af9005-script.h203
-rw-r--r--drivers/media/dvb/dvb-usb/af9005.c1141
-rw-r--r--drivers/media/dvb/dvb-usb/af9005.h3496
-rw-r--r--drivers/media/dvb/dvb-usb/dvb-usb-ids.h4
8 files changed, 6526 insertions, 0 deletions
diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig
index 54488737a08f..c56f38d90f31 100644
--- a/drivers/media/dvb/dvb-usb/Kconfig
+++ b/drivers/media/dvb/dvb-usb/Kconfig
@@ -218,3 +218,19 @@ config DVB_USB_OPERA1
218 select DVB_STV0299 if !DVB_FE_CUSTOMISE 218 select DVB_STV0299 if !DVB_FE_CUSTOMISE
219 help 219 help
220 Say Y here to support the Opera DVB-S USB2.0 receiver. 220 Say Y here to support the Opera DVB-S USB2.0 receiver.
221
222config DVB_USB_AF9005
223 tristate "Afatech AF9005 DVB-T USB1.1 support"
224 depends on DVB_USB
225 select DVB_TUNER_MT2060 if !DVB_FE_CUSTOMISE
226 help
227 Say Y here to support the Afatech AF9005 based DVB-T USB1.1 receiver
228 and the TerraTec Cinergy T USB XE (Rev.1)
229
230config DVB_USB_AF9005_REMOTE
231 tristate "Afatech AF9005 default remote control support"
232 depends on DVB_USB_AF9005
233 help
234 Say Y here to support the default remote control decoding for the
235 Afatech AF9005 based receiver.
236
diff --git a/drivers/media/dvb/dvb-usb/Makefile b/drivers/media/dvb/dvb-usb/Makefile
index 976f840cc904..6e0a9c0f3ec7 100644
--- a/drivers/media/dvb/dvb-usb/Makefile
+++ b/drivers/media/dvb/dvb-usb/Makefile
@@ -55,4 +55,10 @@ dvb-usb-opera-objs = opera1.o
55obj-$(CONFIG_DVB_USB_OPERA1) += dvb-usb-opera.o 55obj-$(CONFIG_DVB_USB_OPERA1) += dvb-usb-opera.o
56 56
57 57
58dvb-usb-af9005-objs = af9005.o af9005-fe.o
59obj-$(CONFIG_DVB_USB_AF9005) += dvb-usb-af9005.o
60
61dvb-usb-af9005-remote-objs = af9005-remote.o
62obj-$(CONFIG_DVB_USB_AF9005_REMOTE) += dvb-usb-af9005-remote.o
63
58EXTRA_CFLAGS = -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/ 64EXTRA_CFLAGS = -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/
diff --git a/drivers/media/dvb/dvb-usb/af9005-fe.c b/drivers/media/dvb/dvb-usb/af9005-fe.c
new file mode 100644
index 000000000000..7195c9461524
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/af9005-fe.c
@@ -0,0 +1,1503 @@
1/* Frontend part of the Linux driver for the Afatech 9005
2 * USB1.1 DVB-T receiver.
3 *
4 * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
5 *
6 * Thanks to Afatech who kindly provided information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * see Documentation/dvb/README.dvb-usb for more information
23 */
24#include "af9005.h"
25#include "af9005-script.h"
26#include "mt2060.h"
27#include "qt1010.h"
28#include <asm/div64.h>
29
30struct af9005_fe_state {
31 struct dvb_usb_device *d;
32 struct dvb_frontend *tuner;
33
34 fe_status_t stat;
35
36 /* retraining parameters */
37 u32 original_fcw;
38 u16 original_rf_top;
39 u16 original_if_top;
40 u16 original_if_min;
41 u16 original_aci0_if_top;
42 u16 original_aci1_if_top;
43 u16 original_aci0_if_min;
44 u8 original_if_unplug_th;
45 u8 original_rf_unplug_th;
46 u8 original_dtop_if_unplug_th;
47 u8 original_dtop_rf_unplug_th;
48
49 /* statistics */
50 u32 pre_vit_error_count;
51 u32 pre_vit_bit_count;
52 u32 ber;
53 u32 post_vit_error_count;
54 u32 post_vit_bit_count;
55 u32 unc;
56 u16 abort_count;
57
58 int opened;
59 int strong;
60 unsigned long next_status_check;
61 struct dvb_frontend frontend;
62};
63
64static int af9005_write_word_agc(struct dvb_usb_device *d, u16 reghi,
65 u16 reglo, u8 pos, u8 len, u16 value)
66{
67 int ret;
68 u8 temp;
69
70 if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff))))
71 return ret;
72 temp = (u8) ((value & 0x0300) >> 8);
73 return af9005_write_register_bits(d, reghi, pos, len,
74 (u8) ((value & 0x300) >> 8));
75}
76
77static int af9005_read_word_agc(struct dvb_usb_device *d, u16 reghi,
78 u16 reglo, u8 pos, u8 len, u16 * value)
79{
80 int ret;
81 u8 temp0, temp1;
82
83 if ((ret = af9005_read_ofdm_register(d, reglo, &temp0)))
84 return ret;
85 if ((ret = af9005_read_ofdm_register(d, reghi, &temp1)))
86 return ret;
87 switch (pos) {
88 case 0:
89 *value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0;
90 break;
91 case 2:
92 *value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0;
93 break;
94 case 4:
95 *value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0;
96 break;
97 case 6:
98 *value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0;
99 break;
100 default:
101 err("invalid pos in read word agc");
102 return -EINVAL;
103 }
104 return 0;
105
106}
107
108static int af9005_is_fecmon_available(struct dvb_frontend *fe, int *available)
109{
110 struct af9005_fe_state *state = fe->demodulator_priv;
111 int ret;
112 u8 temp;
113
114 *available = false;
115
116 ret = af9005_read_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
117 fec_vtb_rsd_mon_en_pos,
118 fec_vtb_rsd_mon_en_len, &temp);
119 if (ret)
120 return ret;
121 if (temp & 1) {
122 ret =
123 af9005_read_register_bits(state->d,
124 xd_p_reg_ofsm_read_rbc_en,
125 reg_ofsm_read_rbc_en_pos,
126 reg_ofsm_read_rbc_en_len, &temp);
127 if (ret)
128 return ret;
129 if ((temp & 1) == 0)
130 *available = true;
131
132 }
133 return 0;
134}
135
136static int af9005_get_post_vit_err_cw_count(struct dvb_frontend *fe,
137 u32 * post_err_count,
138 u32 * post_cw_count,
139 u16 * abort_count)
140{
141 struct af9005_fe_state *state = fe->demodulator_priv;
142 int ret;
143 u32 err_count;
144 u32 cw_count;
145 u8 temp, temp0, temp1, temp2;
146 u16 loc_abort_count;
147
148 *post_err_count = 0;
149 *post_cw_count = 0;
150
151 /* check if error bit count is ready */
152 ret =
153 af9005_read_register_bits(state->d, xd_r_fec_rsd_ber_rdy,
154 fec_rsd_ber_rdy_pos, fec_rsd_ber_rdy_len,
155 &temp);
156 if (ret)
157 return ret;
158 if (!temp) {
159 deb_info("rsd counter not ready\n");
160 return 100;
161 }
162 /* get abort count */
163 ret =
164 af9005_read_ofdm_register(state->d,
165 xd_r_fec_rsd_abort_packet_cnt_7_0,
166 &temp0);
167 if (ret)
168 return ret;
169 ret =
170 af9005_read_ofdm_register(state->d,
171 xd_r_fec_rsd_abort_packet_cnt_15_8,
172 &temp1);
173 if (ret)
174 return ret;
175 loc_abort_count = ((u16) temp1 << 8) + temp0;
176
177 /* get error count */
178 ret =
179 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_7_0,
180 &temp0);
181 if (ret)
182 return ret;
183 ret =
184 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_15_8,
185 &temp1);
186 if (ret)
187 return ret;
188 ret =
189 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_23_16,
190 &temp2);
191 if (ret)
192 return ret;
193 err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
194 *post_err_count = err_count - (u32) loc_abort_count *8 * 8;
195
196 /* get RSD packet number */
197 ret =
198 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
199 &temp0);
200 if (ret)
201 return ret;
202 ret =
203 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
204 &temp1);
205 if (ret)
206 return ret;
207 cw_count = ((u32) temp1 << 8) + temp0;
208 if (cw_count == 0) {
209 err("wrong RSD packet count");
210 return -EIO;
211 }
212 deb_info("POST abort count %d err count %d rsd packets %d\n",
213 loc_abort_count, err_count, cw_count);
214 *post_cw_count = cw_count - (u32) loc_abort_count;
215 *abort_count = loc_abort_count;
216 return 0;
217
218}
219
220static int af9005_get_post_vit_ber(struct dvb_frontend *fe,
221 u32 * post_err_count, u32 * post_cw_count,
222 u16 * abort_count)
223{
224 u32 loc_cw_count = 0, loc_err_count;
225 u16 loc_abort_count;
226 int ret;
227
228 ret =
229 af9005_get_post_vit_err_cw_count(fe, &loc_err_count, &loc_cw_count,
230 &loc_abort_count);
231 if (ret)
232 return ret;
233 *post_err_count = loc_err_count;
234 *post_cw_count = loc_cw_count * 204 * 8;
235 *abort_count = loc_abort_count;
236
237 return 0;
238}
239
240static int af9005_get_pre_vit_err_bit_count(struct dvb_frontend *fe,
241 u32 * pre_err_count,
242 u32 * pre_bit_count)
243{
244 struct af9005_fe_state *state = fe->demodulator_priv;
245 u8 temp, temp0, temp1, temp2;
246 u32 super_frame_count, x, bits;
247 int ret;
248
249 ret =
250 af9005_read_register_bits(state->d, xd_r_fec_vtb_ber_rdy,
251 fec_vtb_ber_rdy_pos, fec_vtb_ber_rdy_len,
252 &temp);
253 if (ret)
254 return ret;
255 if (!temp) {
256 deb_info("viterbi counter not ready\n");
257 return 101; /* ERR_APO_VTB_COUNTER_NOT_READY; */
258 }
259 ret =
260 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_7_0,
261 &temp0);
262 if (ret)
263 return ret;
264 ret =
265 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_15_8,
266 &temp1);
267 if (ret)
268 return ret;
269 ret =
270 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_23_16,
271 &temp2);
272 if (ret)
273 return ret;
274 *pre_err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
275
276 ret =
277 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
278 &temp0);
279 if (ret)
280 return ret;
281 ret =
282 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
283 &temp1);
284 if (ret)
285 return ret;
286 super_frame_count = ((u32) temp1 << 8) + temp0;
287 if (super_frame_count == 0) {
288 deb_info("super frame count 0\n");
289 return 102;
290 }
291
292 /* read fft mode */
293 ret =
294 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
295 reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
296 &temp);
297 if (ret)
298 return ret;
299 if (temp == 0) {
300 /* 2K */
301 x = 1512;
302 } else if (temp == 1) {
303 /* 8k */
304 x = 6048;
305 } else {
306 err("Invalid fft mode");
307 return -EINVAL;
308 }
309
310 /* read constellation mode */
311 ret =
312 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
313 reg_tpsd_const_pos, reg_tpsd_const_len,
314 &temp);
315 if (ret)
316 return ret;
317 switch (temp) {
318 case 0: /* QPSK */
319 bits = 2;
320 break;
321 case 1: /* QAM_16 */
322 bits = 4;
323 break;
324 case 2: /* QAM_64 */
325 bits = 6;
326 break;
327 default:
328 err("invalid constellation mode");
329 return -EINVAL;
330 }
331 *pre_bit_count = super_frame_count * 68 * 4 * x * bits;
332 deb_info("PRE err count %d frame count %d bit count %d\n",
333 *pre_err_count, super_frame_count, *pre_bit_count);
334 return 0;
335}
336
337static int af9005_reset_pre_viterbi(struct dvb_frontend *fe)
338{
339 struct af9005_fe_state *state = fe->demodulator_priv;
340 int ret;
341
342 /* set super frame count to 1 */
343 ret =
344 af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
345 1 & 0xff);
346 if (ret)
347 return ret;
348 af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
349 1 >> 8);
350 if (ret)
351 return ret;
352 /* reset pre viterbi error count */
353 ret =
354 af9005_write_register_bits(state->d, xd_p_fec_vtb_ber_rst,
355 fec_vtb_ber_rst_pos, fec_vtb_ber_rst_len,
356 1);
357
358 return ret;
359}
360
361static int af9005_reset_post_viterbi(struct dvb_frontend *fe)
362{
363 struct af9005_fe_state *state = fe->demodulator_priv;
364 int ret;
365
366 /* set packet unit */
367 ret =
368 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
369 10000 & 0xff);
370 if (ret)
371 return ret;
372 ret =
373 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
374 10000 >> 8);
375 if (ret)
376 return ret;
377 /* reset post viterbi error count */
378 ret =
379 af9005_write_register_bits(state->d, xd_p_fec_rsd_ber_rst,
380 fec_rsd_ber_rst_pos, fec_rsd_ber_rst_len,
381 1);
382
383 return ret;
384}
385
386static int af9005_get_statistic(struct dvb_frontend *fe)
387{
388 struct af9005_fe_state *state = fe->demodulator_priv;
389 int ret, fecavailable;
390 u64 numerator, denominator;
391
392 deb_info("GET STATISTIC\n");
393 ret = af9005_is_fecmon_available(fe, &fecavailable);
394 if (ret)
395 return ret;
396 if (!fecavailable) {
397 deb_info("fecmon not available\n");
398 return 0;
399 }
400
401 ret = af9005_get_pre_vit_err_bit_count(fe, &state->pre_vit_error_count,
402 &state->pre_vit_bit_count);
403 if (ret == 0) {
404 af9005_reset_pre_viterbi(fe);
405 if (state->pre_vit_bit_count > 0) {
406 /* according to v 0.0.4 of the dvb api ber should be a multiple
407 of 10E-9 so we have to multiply the error count by
408 10E9=1000000000 */
409 numerator =
410 (u64) state->pre_vit_error_count * (u64) 1000000000;
411 denominator = (u64) state->pre_vit_bit_count;
412 state->ber = do_div(numerator, denominator);
413 } else {
414 state->ber = 0xffffffff;
415 }
416 }
417
418 ret = af9005_get_post_vit_ber(fe, &state->post_vit_error_count,
419 &state->post_vit_bit_count,
420 &state->abort_count);
421 if (ret == 0) {
422 ret = af9005_reset_post_viterbi(fe);
423 state->unc += state->abort_count;
424 if (ret)
425 return ret;
426 }
427 return 0;
428}
429
430static int af9005_fe_refresh_state(struct dvb_frontend *fe)
431{
432 struct af9005_fe_state *state = fe->demodulator_priv;
433 if (time_after(jiffies, state->next_status_check)) {
434 deb_info("REFRESH STATE\n");
435
436 /* statistics */
437 if (af9005_get_statistic(fe))
438 err("get_statistic_failed");
439 state->next_status_check = jiffies + 250 * HZ / 1000;
440 }
441 return 0;
442}
443
444static int af9005_fe_read_status(struct dvb_frontend *fe, fe_status_t * stat)
445{
446 struct af9005_fe_state *state = fe->demodulator_priv;
447 u8 temp;
448 int ret;
449
450 if (state->tuner == NULL)
451 return -ENODEV;
452
453 *stat = 0;
454 ret = af9005_read_register_bits(state->d, xd_p_agc_lock,
455 agc_lock_pos, agc_lock_len, &temp);
456 if (ret)
457 return ret;
458 if (temp)
459 *stat |= FE_HAS_SIGNAL;
460
461 ret = af9005_read_register_bits(state->d, xd_p_fd_tpsd_lock,
462 fd_tpsd_lock_pos, fd_tpsd_lock_len,
463 &temp);
464 if (ret)
465 return ret;
466 if (temp)
467 *stat |= FE_HAS_CARRIER;
468
469 ret = af9005_read_register_bits(state->d,
470 xd_r_mp2if_sync_byte_locked,
471 mp2if_sync_byte_locked_pos,
472 mp2if_sync_byte_locked_pos, &temp);
473 if (ret)
474 return ret;
475 if (temp)
476 *stat |= FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_LOCK;
477 if (state->opened)
478 af9005_led_control(state->d, *stat & FE_HAS_LOCK);
479
480 ret =
481 af9005_read_register_bits(state->d, xd_p_reg_strong_sginal_detected,
482 reg_strong_sginal_detected_pos,
483 reg_strong_sginal_detected_len, &temp);
484 if (ret)
485 return ret;
486 if (temp != state->strong) {
487 deb_info("adjust for strong signal %d\n", temp);
488 state->strong = temp;
489 }
490 return 0;
491}
492
493static int af9005_fe_read_ber(struct dvb_frontend *fe, u32 * ber)
494{
495 struct af9005_fe_state *state = fe->demodulator_priv;
496 if (state->tuner == NULL)
497 return -ENODEV;
498 af9005_fe_refresh_state(fe);
499 *ber = state->ber;
500 return 0;
501}
502
503static int af9005_fe_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
504{
505 struct af9005_fe_state *state = fe->demodulator_priv;
506 if (state->tuner == NULL)
507 return -ENODEV;
508 af9005_fe_refresh_state(fe);
509 *unc = state->unc;
510 return 0;
511}
512
513static int af9005_fe_read_signal_strength(struct dvb_frontend *fe,
514 u16 * strength)
515{
516 struct af9005_fe_state *state = fe->demodulator_priv;
517 int ret;
518 u8 if_gain, rf_gain;
519
520 if (state->tuner == NULL)
521 return -ENODEV;
522 ret =
523 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_rf_gain,
524 &rf_gain);
525 if (ret)
526 return ret;
527 ret =
528 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain,
529 &if_gain);
530 if (ret)
531 return ret;
532 /* this value has no real meaning, but i don't have the tables that relate
533 the rf and if gain with the dbm, so I just scale the value */
534 *strength = (512 - rf_gain - if_gain) << 7;
535 return 0;
536}
537
538static int af9005_fe_read_snr(struct dvb_frontend *fe, u16 * snr)
539{
540 /* the snr can be derived from the ber and the constellation
541 but I don't think this kind of complex calculations belong
542 in the driver. I may be wrong.... */
543 return -ENOSYS;
544}
545
546static int af9005_fe_program_cfoe(struct dvb_usb_device *d, fe_bandwidth_t bw)
547{
548 u8 temp0, temp1, temp2, temp3, buf[4];
549 int ret;
550 u32 NS_coeff1_2048Nu;
551 u32 NS_coeff1_8191Nu;
552 u32 NS_coeff1_8192Nu;
553 u32 NS_coeff1_8193Nu;
554 u32 NS_coeff2_2k;
555 u32 NS_coeff2_8k;
556
557 switch (bw) {
558 case BANDWIDTH_6_MHZ:
559 NS_coeff1_2048Nu = 0x2ADB6DC;
560 NS_coeff1_8191Nu = 0xAB7313;
561 NS_coeff1_8192Nu = 0xAB6DB7;
562 NS_coeff1_8193Nu = 0xAB685C;
563 NS_coeff2_2k = 0x156DB6E;
564 NS_coeff2_8k = 0x55B6DC;
565 break;
566
567 case BANDWIDTH_7_MHZ:
568 NS_coeff1_2048Nu = 0x3200001;
569 NS_coeff1_8191Nu = 0xC80640;
570 NS_coeff1_8192Nu = 0xC80000;
571 NS_coeff1_8193Nu = 0xC7F9C0;
572 NS_coeff2_2k = 0x1900000;
573 NS_coeff2_8k = 0x640000;
574 break;
575
576 case BANDWIDTH_8_MHZ:
577 NS_coeff1_2048Nu = 0x3924926;
578 NS_coeff1_8191Nu = 0xE4996E;
579 NS_coeff1_8192Nu = 0xE49249;
580 NS_coeff1_8193Nu = 0xE48B25;
581 NS_coeff2_2k = 0x1C92493;
582 NS_coeff2_8k = 0x724925;
583 break;
584 default:
585 err("Invalid bandwith %d.", bw);
586 return -EINVAL;
587 }
588
589 /*
590 * write NS_coeff1_2048Nu
591 */
592
593 temp0 = (u8) (NS_coeff1_2048Nu & 0x000000FF);
594 temp1 = (u8) ((NS_coeff1_2048Nu & 0x0000FF00) >> 8);
595 temp2 = (u8) ((NS_coeff1_2048Nu & 0x00FF0000) >> 16);
596 temp3 = (u8) ((NS_coeff1_2048Nu & 0x03000000) >> 24);
597
598 /* big endian to make 8051 happy */
599 buf[0] = temp3;
600 buf[1] = temp2;
601 buf[2] = temp1;
602 buf[3] = temp0;
603
604 /* cfoe_NS_2k_coeff1_25_24 */
605 ret = af9005_write_ofdm_register(d, 0xAE00, buf[0]);
606 if (ret)
607 return ret;
608
609 /* cfoe_NS_2k_coeff1_23_16 */
610 ret = af9005_write_ofdm_register(d, 0xAE01, buf[1]);
611 if (ret)
612 return ret;
613
614 /* cfoe_NS_2k_coeff1_15_8 */
615 ret = af9005_write_ofdm_register(d, 0xAE02, buf[2]);
616 if (ret)
617 return ret;
618
619 /* cfoe_NS_2k_coeff1_7_0 */
620 ret = af9005_write_ofdm_register(d, 0xAE03, buf[3]);
621 if (ret)
622 return ret;
623
624 /*
625 * write NS_coeff2_2k
626 */
627
628 temp0 = (u8) ((NS_coeff2_2k & 0x0000003F));
629 temp1 = (u8) ((NS_coeff2_2k & 0x00003FC0) >> 6);
630 temp2 = (u8) ((NS_coeff2_2k & 0x003FC000) >> 14);
631 temp3 = (u8) ((NS_coeff2_2k & 0x01C00000) >> 22);
632
633 /* big endian to make 8051 happy */
634 buf[0] = temp3;
635 buf[1] = temp2;
636 buf[2] = temp1;
637 buf[3] = temp0;
638
639 ret = af9005_write_ofdm_register(d, 0xAE04, buf[0]);
640 if (ret)
641 return ret;
642
643 ret = af9005_write_ofdm_register(d, 0xAE05, buf[1]);
644 if (ret)
645 return ret;
646
647 ret = af9005_write_ofdm_register(d, 0xAE06, buf[2]);
648 if (ret)
649 return ret;
650
651 ret = af9005_write_ofdm_register(d, 0xAE07, buf[3]);
652 if (ret)
653 return ret;
654
655 /*
656 * write NS_coeff1_8191Nu
657 */
658
659 temp0 = (u8) ((NS_coeff1_8191Nu & 0x000000FF));
660 temp1 = (u8) ((NS_coeff1_8191Nu & 0x0000FF00) >> 8);
661 temp2 = (u8) ((NS_coeff1_8191Nu & 0x00FFC000) >> 16);
662 temp3 = (u8) ((NS_coeff1_8191Nu & 0x03000000) >> 24);
663
664 /* big endian to make 8051 happy */
665 buf[0] = temp3;
666 buf[1] = temp2;
667 buf[2] = temp1;
668 buf[3] = temp0;
669
670 ret = af9005_write_ofdm_register(d, 0xAE08, buf[0]);
671 if (ret)
672 return ret;
673
674 ret = af9005_write_ofdm_register(d, 0xAE09, buf[1]);
675 if (ret)
676 return ret;
677
678 ret = af9005_write_ofdm_register(d, 0xAE0A, buf[2]);
679 if (ret)
680 return ret;
681
682 ret = af9005_write_ofdm_register(d, 0xAE0B, buf[3]);
683 if (ret)
684 return ret;
685
686 /*
687 * write NS_coeff1_8192Nu
688 */
689
690 temp0 = (u8) (NS_coeff1_8192Nu & 0x000000FF);
691 temp1 = (u8) ((NS_coeff1_8192Nu & 0x0000FF00) >> 8);
692 temp2 = (u8) ((NS_coeff1_8192Nu & 0x00FFC000) >> 16);
693 temp3 = (u8) ((NS_coeff1_8192Nu & 0x03000000) >> 24);
694
695 /* big endian to make 8051 happy */
696 buf[0] = temp3;
697 buf[1] = temp2;
698 buf[2] = temp1;
699 buf[3] = temp0;
700
701 ret = af9005_write_ofdm_register(d, 0xAE0C, buf[0]);
702 if (ret)
703 return ret;
704
705 ret = af9005_write_ofdm_register(d, 0xAE0D, buf[1]);
706 if (ret)
707 return ret;
708
709 ret = af9005_write_ofdm_register(d, 0xAE0E, buf[2]);
710 if (ret)
711 return ret;
712
713 ret = af9005_write_ofdm_register(d, 0xAE0F, buf[3]);
714 if (ret)
715 return ret;
716
717 /*
718 * write NS_coeff1_8193Nu
719 */
720
721 temp0 = (u8) ((NS_coeff1_8193Nu & 0x000000FF));
722 temp1 = (u8) ((NS_coeff1_8193Nu & 0x0000FF00) >> 8);
723 temp2 = (u8) ((NS_coeff1_8193Nu & 0x00FFC000) >> 16);
724 temp3 = (u8) ((NS_coeff1_8193Nu & 0x03000000) >> 24);
725
726 /* big endian to make 8051 happy */
727 buf[0] = temp3;
728 buf[1] = temp2;
729 buf[2] = temp1;
730 buf[3] = temp0;
731
732 ret = af9005_write_ofdm_register(d, 0xAE10, buf[0]);
733 if (ret)
734 return ret;
735
736 ret = af9005_write_ofdm_register(d, 0xAE11, buf[1]);
737 if (ret)
738 return ret;
739
740 ret = af9005_write_ofdm_register(d, 0xAE12, buf[2]);
741 if (ret)
742 return ret;
743
744 ret = af9005_write_ofdm_register(d, 0xAE13, buf[3]);
745 if (ret)
746 return ret;
747
748 /*
749 * write NS_coeff2_8k
750 */
751
752 temp0 = (u8) ((NS_coeff2_8k & 0x0000003F));
753 temp1 = (u8) ((NS_coeff2_8k & 0x00003FC0) >> 6);
754 temp2 = (u8) ((NS_coeff2_8k & 0x003FC000) >> 14);
755 temp3 = (u8) ((NS_coeff2_8k & 0x01C00000) >> 22);
756
757 /* big endian to make 8051 happy */
758 buf[0] = temp3;
759 buf[1] = temp2;
760 buf[2] = temp1;
761 buf[3] = temp0;
762
763 ret = af9005_write_ofdm_register(d, 0xAE14, buf[0]);
764 if (ret)
765 return ret;
766
767 ret = af9005_write_ofdm_register(d, 0xAE15, buf[1]);
768 if (ret)
769 return ret;
770
771 ret = af9005_write_ofdm_register(d, 0xAE16, buf[2]);
772 if (ret)
773 return ret;
774
775 ret = af9005_write_ofdm_register(d, 0xAE17, buf[3]);
776 return ret;
777
778}
779
780static int af9005_fe_select_bw(struct dvb_usb_device *d, fe_bandwidth_t bw)
781{
782 u8 temp;
783 switch (bw) {
784 case BANDWIDTH_6_MHZ:
785 temp = 0;
786 break;
787 case BANDWIDTH_7_MHZ:
788 temp = 1;
789 break;
790 case BANDWIDTH_8_MHZ:
791 temp = 2;
792 break;
793 default:
794 err("Invalid bandwith %d.", bw);
795 return -EINVAL;
796 }
797 return af9005_write_register_bits(d, xd_g_reg_bw, reg_bw_pos,
798 reg_bw_len, temp);
799}
800
801static int af9005_fe_power(struct dvb_frontend *fe, int on)
802{
803 struct af9005_fe_state *state = fe->demodulator_priv;
804 u8 temp = on;
805 int ret;
806 deb_info("power %s tuner\n", on ? "on" : "off");
807 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
808 return ret;
809}
810
811static struct mt2060_config af9005_mt2060_config = {
812 0xC0
813};
814
815static struct qt1010_config af9005_qt1010_config = {
816 0xC4
817};
818
819static int af9005_fe_init(struct dvb_frontend *fe)
820{
821 struct af9005_fe_state *state = fe->demodulator_priv;
822 struct dvb_usb_adapter *adap = fe->dvb->priv;
823 int ret, i, scriptlen;
824 u8 temp, temp0 = 0, temp1 = 0, temp2 = 0;
825 u8 buf[2];
826 u16 if1;
827
828 deb_info("in af9005_fe_init\n");
829
830 /* reset */
831 deb_info("reset\n");
832 if ((ret =
833 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en,
834 4, 1, 0x01)))
835 return ret;
836 if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0)))
837 return ret;
838 /* clear ofdm reset */
839 deb_info("clear ofdm reset\n");
840 for (i = 0; i < 150; i++) {
841 if ((ret =
842 af9005_read_ofdm_register(state->d,
843 xd_I2C_reg_ofdm_rst, &temp)))
844 return ret;
845 if (temp & (regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos))
846 break;
847 msleep(10);
848 }
849 if (i == 150)
850 return -ETIMEDOUT;
851
852 /*FIXME in the dump
853 write B200 A9
854 write xd_g_reg_ofsm_clk 7
855 read eepr c6 (2)
856 read eepr c7 (2)
857 misc ctrl 3 -> 1
858 read eepr ca (6)
859 write xd_g_reg_ofsm_clk 0
860 write B200 a1
861 */
862 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9);
863 if (ret)
864 return ret;
865 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07);
866 if (ret)
867 return ret;
868 temp = 0x01;
869 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
870 if (ret)
871 return ret;
872 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00);
873 if (ret)
874 return ret;
875 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1);
876 if (ret)
877 return ret;
878
879 temp = regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos;
880 if ((ret =
881 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
882 reg_ofdm_rst_pos, reg_ofdm_rst_len, 1)))
883 return ret;
884 if ((ret =
885 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
886 reg_ofdm_rst_pos, reg_ofdm_rst_len, 0)))
887 return ret;
888
889 if (ret)
890 return ret;
891 /* don't know what register aefc is, but this is what the windows driver does */
892 ret = af9005_write_ofdm_register(state->d, 0xaefc, 0);
893 if (ret)
894 return ret;
895
896 /* set stand alone chip */
897 deb_info("set stand alone chip\n");
898 if ((ret =
899 af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone,
900 reg_dca_stand_alone_pos,
901 reg_dca_stand_alone_len, 1)))
902 return ret;
903
904 /* set dca upper & lower chip */
905 deb_info("set dca upper & lower chip\n");
906 if ((ret =
907 af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip,
908 reg_dca_upper_chip_pos,
909 reg_dca_upper_chip_len, 0)))
910 return ret;
911 if ((ret =
912 af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip,
913 reg_dca_lower_chip_pos,
914 reg_dca_lower_chip_len, 0)))
915 return ret;
916
917 /* set 2wire master clock to 0x14 (for 60KHz) */
918 deb_info("set 2wire master clock to 0x14 (for 60KHz)\n");
919 if ((ret =
920 af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14)))
921 return ret;
922
923 /* clear dca enable chip */
924 deb_info("clear dca enable chip\n");
925 if ((ret =
926 af9005_write_register_bits(state->d, xd_p_reg_dca_en,
927 reg_dca_en_pos, reg_dca_en_len, 0)))
928 return ret;
929 /* FIXME these are register bits, but I don't know which ones */
930 ret = af9005_write_ofdm_register(state->d, 0xa16c, 1);
931 if (ret)
932 return ret;
933 ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0);
934 if (ret)
935 return ret;
936
937 /* init other parameters: program cfoe and select bandwith */
938 deb_info("program cfoe\n");
939 if ((ret = af9005_fe_program_cfoe(state->d, BANDWIDTH_6_MHZ)))
940 return ret;
941 /* set read-update bit for constellation */
942 deb_info("set read-update bit for constellation\n");
943 if ((ret =
944 af9005_write_register_bits(state->d, xd_p_reg_feq_read_update,
945 reg_feq_read_update_pos,
946 reg_feq_read_update_len, 1)))
947 return ret;
948
949 /* sample code has a set MPEG TS code here
950 but sniffing reveals that it doesn't do it */
951
952 /* set read-update bit to 1 for DCA constellation */
953 deb_info("set read-update bit 1 for DCA constellation\n");
954 if ((ret =
955 af9005_write_register_bits(state->d, xd_p_reg_dca_read_update,
956 reg_dca_read_update_pos,
957 reg_dca_read_update_len, 1)))
958 return ret;
959
960 /* enable fec monitor */
961 deb_info("enable fec monitor\n");
962 if ((ret =
963 af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
964 fec_vtb_rsd_mon_en_pos,
965 fec_vtb_rsd_mon_en_len, 1)))
966 return ret;
967
968 /* FIXME should be register bits, I don't know which ones */
969 ret = af9005_write_ofdm_register(state->d, 0xa601, 0);
970
971 /* set api_retrain_never_freeze */
972 deb_info("set api_retrain_never_freeze\n");
973 if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01)))
974 return ret;
975
976 /* load init script */
977 deb_info("load init script\n");
978 scriptlen = sizeof(script) / sizeof(RegDesc);
979 for (i = 0; i < scriptlen; i++) {
980 if ((ret =
981 af9005_write_register_bits(state->d, script[i].reg,
982 script[i].pos,
983 script[i].len, script[i].val)))
984 return ret;
985 /* save 3 bytes of original fcw */
986 if (script[i].reg == 0xae18)
987 temp2 = script[i].val;
988 if (script[i].reg == 0xae19)
989 temp1 = script[i].val;
990 if (script[i].reg == 0xae1a)
991 temp0 = script[i].val;
992
993 /* save original unplug threshold */
994 if (script[i].reg == xd_p_reg_unplug_th)
995 state->original_if_unplug_th = script[i].val;
996 if (script[i].reg == xd_p_reg_unplug_rf_gain_th)
997 state->original_rf_unplug_th = script[i].val;
998 if (script[i].reg == xd_p_reg_unplug_dtop_if_gain_th)
999 state->original_dtop_if_unplug_th = script[i].val;
1000 if (script[i].reg == xd_p_reg_unplug_dtop_rf_gain_th)
1001 state->original_dtop_rf_unplug_th = script[i].val;
1002
1003 }
1004 state->original_fcw =
1005 ((u32) temp2 << 16) + ((u32) temp1 << 8) + (u32) temp0;
1006
1007
1008 /* save original TOPs */
1009 deb_info("save original TOPs\n");
1010
1011 /* RF TOP */
1012 ret =
1013 af9005_read_word_agc(state->d,
1014 xd_p_reg_aagc_rf_top_numerator_9_8,
1015 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
1016 &state->original_rf_top);
1017 if (ret)
1018 return ret;
1019
1020 /* IF TOP */
1021 ret =
1022 af9005_read_word_agc(state->d,
1023 xd_p_reg_aagc_if_top_numerator_9_8,
1024 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1025 &state->original_if_top);
1026 if (ret)
1027 return ret;
1028
1029 /* ACI 0 IF TOP */
1030 ret =
1031 af9005_read_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1032 &state->original_aci0_if_top);
1033 if (ret)
1034 return ret;
1035
1036 /* ACI 1 IF TOP */
1037 ret =
1038 af9005_read_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1039 &state->original_aci1_if_top);
1040 if (ret)
1041 return ret;
1042
1043 /* attach tuner and init */
1044 if (state->tuner == NULL) {
1045 /* read tuner and board id from eeprom */
1046 ret = af9005_read_eeprom(adap->dev, 0xc6, buf, 2);
1047 if (ret) {
1048 err("Impossible to read EEPROM\n");
1049 return ret;
1050 }
1051 deb_info("Tuner id %d, board id %d\n", buf[0], buf[1]);
1052 switch (buf[0]) {
1053 case 2: /* MT2060 */
1054 /* read if1 from eeprom */
1055 ret = af9005_read_eeprom(adap->dev, 0xc8, buf, 2);
1056 if (ret) {
1057 err("Impossible to read EEPROM\n");
1058 return ret;
1059 }
1060 if1 = (u16) (buf[0] << 8) + buf[1];
1061 state->tuner =
1062 dvb_attach(mt2060_attach, fe, &adap->dev->i2c_adap,
1063 &af9005_mt2060_config, if1);
1064 if (state->tuner == NULL) {
1065 deb_info("MT2060 attach failed\n");
1066 return -ENODEV;
1067 }
1068 break;
1069 case 3: /* QT1010 */
1070 case 9: /* QT1010B */
1071 state->tuner =
1072 dvb_attach(qt1010_attach, fe, &adap->dev->i2c_adap,
1073 &af9005_qt1010_config);
1074 if (state->tuner == NULL) {
1075 deb_info("QT1010 attach failed\n");
1076 return -ENODEV;
1077 }
1078 break;
1079 default:
1080 err("Unsupported tuner type %d", buf[0]);
1081 return -ENODEV;
1082 }
1083 ret = state->tuner->ops.tuner_ops.init(state->tuner);
1084 if (ret)
1085 return ret;
1086 }
1087
1088 deb_info("profit!\n");
1089 return 0;
1090}
1091
1092static int af9005_fe_sleep(struct dvb_frontend *fe)
1093{
1094 return af9005_fe_power(fe, 0);
1095}
1096
1097static int af9005_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
1098{
1099 struct af9005_fe_state *state = fe->demodulator_priv;
1100
1101 if (acquire) {
1102 state->opened++;
1103 } else {
1104
1105 state->opened--;
1106 if (!state->opened)
1107 af9005_led_control(state->d, 0);
1108 }
1109 return 0;
1110}
1111
1112static int af9005_fe_set_frontend(struct dvb_frontend *fe,
1113 struct dvb_frontend_parameters *fep)
1114{
1115 struct af9005_fe_state *state = fe->demodulator_priv;
1116 int ret;
1117 u8 temp, temp0, temp1, temp2;
1118
1119 deb_info("af9005_fe_set_frontend freq %d bw %d\n", fep->frequency,
1120 fep->u.ofdm.bandwidth);
1121 if (state->tuner == NULL) {
1122 err("Tuner not attached");
1123 return -ENODEV;
1124 }
1125
1126 deb_info("turn off led\n");
1127 /* not in the log */
1128 ret = af9005_led_control(state->d, 0);
1129 if (ret)
1130 return ret;
1131 /* not sure about the bits */
1132 ret = af9005_write_register_bits(state->d, XD_MP2IF_MISC, 2, 1, 0);
1133 if (ret)
1134 return ret;
1135
1136 /* set FCW to default value */
1137 deb_info("set FCW to default value\n");
1138 temp0 = (u8) (state->original_fcw & 0x000000ff);
1139 temp1 = (u8) ((state->original_fcw & 0x0000ff00) >> 8);
1140 temp2 = (u8) ((state->original_fcw & 0x00ff0000) >> 16);
1141 ret = af9005_write_ofdm_register(state->d, 0xae1a, temp0);
1142 if (ret)
1143 return ret;
1144 ret = af9005_write_ofdm_register(state->d, 0xae19, temp1);
1145 if (ret)
1146 return ret;
1147 ret = af9005_write_ofdm_register(state->d, 0xae18, temp2);
1148 if (ret)
1149 return ret;
1150
1151 /* restore original TOPs */
1152 deb_info("restore original TOPs\n");
1153 ret =
1154 af9005_write_word_agc(state->d,
1155 xd_p_reg_aagc_rf_top_numerator_9_8,
1156 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
1157 state->original_rf_top);
1158 if (ret)
1159 return ret;
1160 ret =
1161 af9005_write_word_agc(state->d,
1162 xd_p_reg_aagc_if_top_numerator_9_8,
1163 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1164 state->original_if_top);
1165 if (ret)
1166 return ret;
1167 ret =
1168 af9005_write_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1169 state->original_aci0_if_top);
1170 if (ret)
1171 return ret;
1172 ret =
1173 af9005_write_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1174 state->original_aci1_if_top);
1175 if (ret)
1176 return ret;
1177
1178 /* select bandwith */
1179 deb_info("select bandwidth");
1180 ret = af9005_fe_select_bw(state->d, fep->u.ofdm.bandwidth);
1181 if (ret)
1182 return ret;
1183 ret = af9005_fe_program_cfoe(state->d, fep->u.ofdm.bandwidth);
1184 if (ret)
1185 return ret;
1186
1187 /* clear easy mode flag */
1188 deb_info("clear easy mode flag\n");
1189 ret = af9005_write_ofdm_register(state->d, 0xaefd, 0);
1190 if (ret)
1191 return ret;
1192
1193 /* set unplug threshold to original value */
1194 deb_info("set unplug threshold to original value\n");
1195 ret =
1196 af9005_write_ofdm_register(state->d, xd_p_reg_unplug_th,
1197 state->original_if_unplug_th);
1198 if (ret)
1199 return ret;
1200 /* set tuner */
1201 deb_info("set tuner\n");
1202 ret = state->tuner->ops.tuner_ops.set_params(state->tuner, fep);
1203 if (ret)
1204 return ret;
1205
1206 /* trigger ofsm */
1207 deb_info("trigger ofsm\n");
1208 temp = 0;
1209 ret = af9005_write_tuner_registers(state->d, 0xffff, &temp, 1);
1210 if (ret)
1211 return ret;
1212
1213 /* clear retrain and freeze flag */
1214 deb_info("clear retrain and freeze flag\n");
1215 ret =
1216 af9005_write_register_bits(state->d,
1217 xd_p_reg_api_retrain_request,
1218 reg_api_retrain_request_pos, 2, 0);
1219 if (ret)
1220 return ret;
1221
1222 /* reset pre viterbi and post viterbi registers and statistics */
1223 af9005_reset_pre_viterbi(fe);
1224 af9005_reset_post_viterbi(fe);
1225 state->pre_vit_error_count = 0;
1226 state->pre_vit_bit_count = 0;
1227 state->ber = 0;
1228 state->post_vit_error_count = 0;
1229 /* state->unc = 0; commented out since it should be ever increasing */
1230 state->abort_count = 0;
1231
1232 state->next_status_check = jiffies;
1233 state->strong = -1;
1234
1235 return 0;
1236}
1237
1238static int af9005_fe_get_frontend(struct dvb_frontend *fe,
1239 struct dvb_frontend_parameters *fep)
1240{
1241 struct af9005_fe_state *state = fe->demodulator_priv;
1242 int ret;
1243 u8 temp;
1244
1245 /* mode */
1246 ret =
1247 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
1248 reg_tpsd_const_pos, reg_tpsd_const_len,
1249 &temp);
1250 if (ret)
1251 return ret;
1252 deb_info("===== fe_get_frontend ==============\n");
1253 deb_info("CONSTELLATION ");
1254 switch (temp) {
1255 case 0:
1256 fep->u.ofdm.constellation = QPSK;
1257 deb_info("QPSK\n");
1258 break;
1259 case 1:
1260 fep->u.ofdm.constellation = QAM_16;
1261 deb_info("QAM_16\n");
1262 break;
1263 case 2:
1264 fep->u.ofdm.constellation = QAM_64;
1265 deb_info("QAM_64\n");
1266 break;
1267 }
1268
1269 /* tps hierarchy and alpha value */
1270 ret =
1271 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hier,
1272 reg_tpsd_hier_pos, reg_tpsd_hier_len,
1273 &temp);
1274 if (ret)
1275 return ret;
1276 deb_info("HIERARCHY ");
1277 switch (temp) {
1278 case 0:
1279 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1280 deb_info("NONE\n");
1281 break;
1282 case 1:
1283 fep->u.ofdm.hierarchy_information = HIERARCHY_1;
1284 deb_info("1\n");
1285 break;
1286 case 2:
1287 fep->u.ofdm.hierarchy_information = HIERARCHY_2;
1288 deb_info("2\n");
1289 break;
1290 case 3:
1291 fep->u.ofdm.hierarchy_information = HIERARCHY_4;
1292 deb_info("4\n");
1293 break;
1294 }
1295
1296 /* high/low priority */
1297 ret =
1298 af9005_read_register_bits(state->d, xd_g_reg_dec_pri,
1299 reg_dec_pri_pos, reg_dec_pri_len, &temp);
1300 if (ret)
1301 return ret;
1302 /* if temp is set = high priority */
1303 deb_info("PRIORITY %s\n", temp ? "high" : "low");
1304
1305 /* high coderate */
1306 ret =
1307 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hpcr,
1308 reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len,
1309 &temp);
1310 if (ret)
1311 return ret;
1312 deb_info("CODERATE HP ");
1313 switch (temp) {
1314 case 0:
1315 fep->u.ofdm.code_rate_HP = FEC_1_2;
1316 deb_info("FEC_1_2\n");
1317 break;
1318 case 1:
1319 fep->u.ofdm.code_rate_HP = FEC_2_3;
1320 deb_info("FEC_2_3\n");
1321 break;
1322 case 2:
1323 fep->u.ofdm.code_rate_HP = FEC_3_4;
1324 deb_info("FEC_3_4\n");
1325 break;
1326 case 3:
1327 fep->u.ofdm.code_rate_HP = FEC_5_6;
1328 deb_info("FEC_5_6\n");
1329 break;
1330 case 4:
1331 fep->u.ofdm.code_rate_HP = FEC_7_8;
1332 deb_info("FEC_7_8\n");
1333 break;
1334 }
1335
1336 /* low coderate */
1337 ret =
1338 af9005_read_register_bits(state->d, xd_g_reg_tpsd_lpcr,
1339 reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len,
1340 &temp);
1341 if (ret)
1342 return ret;
1343 deb_info("CODERATE LP ");
1344 switch (temp) {
1345 case 0:
1346 fep->u.ofdm.code_rate_LP = FEC_1_2;
1347 deb_info("FEC_1_2\n");
1348 break;
1349 case 1:
1350 fep->u.ofdm.code_rate_LP = FEC_2_3;
1351 deb_info("FEC_2_3\n");
1352 break;
1353 case 2:
1354 fep->u.ofdm.code_rate_LP = FEC_3_4;
1355 deb_info("FEC_3_4\n");
1356 break;
1357 case 3:
1358 fep->u.ofdm.code_rate_LP = FEC_5_6;
1359 deb_info("FEC_5_6\n");
1360 break;
1361 case 4:
1362 fep->u.ofdm.code_rate_LP = FEC_7_8;
1363 deb_info("FEC_7_8\n");
1364 break;
1365 }
1366
1367 /* guard interval */
1368 ret =
1369 af9005_read_register_bits(state->d, xd_g_reg_tpsd_gi,
1370 reg_tpsd_gi_pos, reg_tpsd_gi_len, &temp);
1371 if (ret)
1372 return ret;
1373 deb_info("GUARD INTERVAL ");
1374 switch (temp) {
1375 case 0:
1376 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1377 deb_info("1_32\n");
1378 break;
1379 case 1:
1380 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1381 deb_info("1_16\n");
1382 break;
1383 case 2:
1384 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1385 deb_info("1_8\n");
1386 break;
1387 case 3:
1388 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1389 deb_info("1_4\n");
1390 break;
1391 }
1392
1393 /* fft */
1394 ret =
1395 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
1396 reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
1397 &temp);
1398 if (ret)
1399 return ret;
1400 deb_info("TRANSMISSION MODE ");
1401 switch (temp) {
1402 case 0:
1403 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1404 deb_info("2K\n");
1405 break;
1406 case 1:
1407 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1408 deb_info("8K\n");
1409 break;
1410 }
1411
1412 /* bandwidth */
1413 ret =
1414 af9005_read_register_bits(state->d, xd_g_reg_bw, reg_bw_pos,
1415 reg_bw_len, &temp);
1416 deb_info("BANDWIDTH ");
1417 switch (temp) {
1418 case 0:
1419 fep->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1420 deb_info("6\n");
1421 break;
1422 case 1:
1423 fep->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1424 deb_info("7\n");
1425 break;
1426 case 2:
1427 fep->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1428 deb_info("8\n");
1429 break;
1430 }
1431 return 0;
1432}
1433
1434static void af9005_fe_release(struct dvb_frontend *fe)
1435{
1436 struct af9005_fe_state *state =
1437 (struct af9005_fe_state *)fe->demodulator_priv;
1438 if (state->tuner != NULL && state->tuner->ops.tuner_ops.release != NULL) {
1439 state->tuner->ops.tuner_ops.release(state->tuner);
1440#ifdef CONFIG_DVB_CORE_ATTACH
1441 symbol_put_addr(state->tuner->ops.tuner_ops.release);
1442#endif
1443 }
1444 kfree(state);
1445}
1446
1447static struct dvb_frontend_ops af9005_fe_ops;
1448
1449struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d)
1450{
1451 struct af9005_fe_state *state = NULL;
1452
1453 /* allocate memory for the internal state */
1454 state = kzalloc(sizeof(struct af9005_fe_state), GFP_KERNEL);
1455 if (state == NULL)
1456 goto error;
1457
1458 deb_info("attaching frontend af9005\n");
1459
1460 state->d = d;
1461 state->tuner = NULL;
1462 state->opened = 0;
1463
1464 memcpy(&state->frontend.ops, &af9005_fe_ops,
1465 sizeof(struct dvb_frontend_ops));
1466 state->frontend.demodulator_priv = state;
1467
1468 return &state->frontend;
1469 error:
1470 return NULL;
1471}
1472
1473static struct dvb_frontend_ops af9005_fe_ops = {
1474 .info = {
1475 .name = "AF9005 USB DVB-T",
1476 .type = FE_OFDM,
1477 .frequency_min = 44250000,
1478 .frequency_max = 867250000,
1479 .frequency_stepsize = 250000,
1480 .caps = FE_CAN_INVERSION_AUTO |
1481 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1482 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1483 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1484 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
1485 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
1486 FE_CAN_HIERARCHY_AUTO,
1487 },
1488
1489 .release = af9005_fe_release,
1490
1491 .init = af9005_fe_init,
1492 .sleep = af9005_fe_sleep,
1493 .ts_bus_ctrl = af9005_ts_bus_ctrl,
1494
1495 .set_frontend = af9005_fe_set_frontend,
1496 .get_frontend = af9005_fe_get_frontend,
1497
1498 .read_status = af9005_fe_read_status,
1499 .read_ber = af9005_fe_read_ber,
1500 .read_signal_strength = af9005_fe_read_signal_strength,
1501 .read_snr = af9005_fe_read_snr,
1502 .read_ucblocks = af9005_fe_read_unc_blocks,
1503};
diff --git a/drivers/media/dvb/dvb-usb/af9005-remote.c b/drivers/media/dvb/dvb-usb/af9005-remote.c
new file mode 100644
index 000000000000..ff00c0e8f4a1
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/af9005-remote.c
@@ -0,0 +1,157 @@
1/* DVB USB compliant Linux driver for the Afatech 9005
2 * USB1.1 DVB-T receiver.
3 *
4 * Standard remote decode function
5 *
6 * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
7 *
8 * Thanks to Afatech who kindly provided information.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 * see Documentation/dvb/REDME.dvb-usb for more information
25 */
26#include "af9005.h"
27/* debug */
28int dvb_usb_af9005_remote_debug;
29module_param_named(debug, dvb_usb_af9005_remote_debug, int, 0644);
30MODULE_PARM_DESC(debug,
31 "enable (1) or disable (0) debug messages."
32 DVB_USB_DEBUG_STATUS);
33
34#define deb_decode(args...) dprintk(dvb_usb_af9005_remote_debug,0x01,args)
35
36struct dvb_usb_rc_key af9005_rc_keys[] = {
37
38 {0x01, 0xb7, KEY_POWER},
39 {0x01, 0xa7, KEY_VOLUMEUP},
40 {0x01, 0x87, KEY_CHANNELUP},
41 {0x01, 0x7f, KEY_MUTE},
42 {0x01, 0xbf, KEY_VOLUMEDOWN},
43 {0x01, 0x3f, KEY_CHANNELDOWN},
44 {0x01, 0xdf, KEY_1},
45 {0x01, 0x5f, KEY_2},
46 {0x01, 0x9f, KEY_3},
47 {0x01, 0x1f, KEY_4},
48 {0x01, 0xef, KEY_5},
49 {0x01, 0x6f, KEY_6},
50 {0x01, 0xaf, KEY_7},
51 {0x01, 0x27, KEY_8},
52 {0x01, 0x07, KEY_9},
53 {0x01, 0xcf, KEY_ZOOM},
54 {0x01, 0x4f, KEY_0},
55 {0x01, 0x8f, KEY_GOTO}, /* marked jump on the remote */
56
57 {0x00, 0xbd, KEY_POWER},
58 {0x00, 0x7d, KEY_VOLUMEUP},
59 {0x00, 0xfd, KEY_CHANNELUP},
60 {0x00, 0x9d, KEY_MUTE},
61 {0x00, 0x5d, KEY_VOLUMEDOWN},
62 {0x00, 0xdd, KEY_CHANNELDOWN},
63 {0x00, 0xad, KEY_1},
64 {0x00, 0x6d, KEY_2},
65 {0x00, 0xed, KEY_3},
66 {0x00, 0x8d, KEY_4},
67 {0x00, 0x4d, KEY_5},
68 {0x00, 0xcd, KEY_6},
69 {0x00, 0xb5, KEY_7},
70 {0x00, 0x75, KEY_8},
71 {0x00, 0xf5, KEY_9},
72 {0x00, 0x95, KEY_ZOOM},
73 {0x00, 0x55, KEY_0},
74 {0x00, 0xd5, KEY_GOTO}, /* marked jump on the remote */
75};
76
77int af9005_rc_keys_size = ARRAY_SIZE(af9005_rc_keys);
78
79static int repeatable_keys[] = {
80 KEY_VOLUMEUP,
81 KEY_VOLUMEDOWN,
82 KEY_CHANNELUP,
83 KEY_CHANNELDOWN
84};
85
86int af9005_rc_decode(struct dvb_usb_device *d, u8 * data, int len, u32 * event,
87 int *state)
88{
89 u16 mark, space;
90 u32 result;
91 u8 cust, dat, invdat;
92 int i;
93
94 if (len >= 6) {
95 mark = (u16) (data[0] << 8) + data[1];
96 space = (u16) (data[2] << 8) + data[3];
97 if (space * 3 < mark) {
98 for (i = 0; i < ARRAY_SIZE(repeatable_keys); i++) {
99 if (d->last_event == repeatable_keys[i]) {
100 *state = REMOTE_KEY_REPEAT;
101 *event = d->last_event;
102 deb_decode("repeat key, event %x\n",
103 *event);
104 return 0;
105 }
106 }
107 deb_decode("repeated key ignored (non repeatable)\n");
108 return 0;
109 } else if (len >= 33 * 4) { /*32 bits + start code */
110 result = 0;
111 for (i = 4; i < 4 + 32 * 4; i += 4) {
112 result <<= 1;
113 mark = (u16) (data[i] << 8) + data[i + 1];
114 mark >>= 1;
115 space = (u16) (data[i + 2] << 8) + data[i + 3];
116 space >>= 1;
117 if (mark * 2 > space)
118 result += 1;
119 }
120 deb_decode("key pressed, raw value %x\n", result);
121 if ((result & 0xff000000) != 0xfe000000) {
122 deb_decode
123 ("doesn't start with 0xfe, ignored\n");
124 return 0;
125 }
126 cust = (result >> 16) & 0xff;
127 dat = (result >> 8) & 0xff;
128 invdat = (~result) & 0xff;
129 if (dat != invdat) {
130 deb_decode("code != inverted code\n");
131 return 0;
132 }
133 for (i = 0; i < af9005_rc_keys_size; i++) {
134 if (af9005_rc_keys[i].custom == cust
135 && af9005_rc_keys[i].data == dat) {
136 *event = af9005_rc_keys[i].event;
137 *state = REMOTE_KEY_PRESSED;
138 deb_decode
139 ("key pressed, event %x\n", *event);
140 return 0;
141 }
142 }
143 deb_decode("not found in table\n");
144 }
145 }
146 return 0;
147}
148
149EXPORT_SYMBOL(af9005_rc_keys);
150EXPORT_SYMBOL(af9005_rc_keys_size);
151EXPORT_SYMBOL(af9005_rc_decode);
152
153MODULE_AUTHOR("Luca Olivetti <luca@ventoso.org>");
154MODULE_DESCRIPTION
155 ("Standard remote control decoder for Afatech 9005 DVB-T USB1.1 stick");
156MODULE_VERSION("1.0");
157MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/dvb-usb/af9005-script.h b/drivers/media/dvb/dvb-usb/af9005-script.h
new file mode 100644
index 000000000000..6eeaae51b1ca
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/af9005-script.h
@@ -0,0 +1,203 @@
1/*
2File automatically generated by createinit.py using data
3extracted from AF05BDA.sys (windows driver):
4
5dd if=AF05BDA.sys of=initsequence bs=1 skip=88316 count=1110
6python createinit.py > af9005-script.h
7
8*/
9
10typedef struct {
11 u16 reg;
12 u8 pos;
13 u8 len;
14 u8 val;
15} RegDesc;
16
17RegDesc script[] = {
18 {0xa180, 0x0, 0x8, 0xa},
19 {0xa181, 0x0, 0x8, 0xd7},
20 {0xa182, 0x0, 0x8, 0xa3},
21 {0xa0a0, 0x0, 0x8, 0x0},
22 {0xa0a1, 0x0, 0x5, 0x0},
23 {0xa0a1, 0x5, 0x1, 0x1},
24 {0xa0c0, 0x0, 0x4, 0x1},
25 {0xa20e, 0x4, 0x4, 0xa},
26 {0xa20f, 0x0, 0x8, 0x40},
27 {0xa210, 0x0, 0x8, 0x8},
28 {0xa32a, 0x0, 0x4, 0xa},
29 {0xa32c, 0x0, 0x8, 0x20},
30 {0xa32b, 0x0, 0x8, 0x15},
31 {0xa1a0, 0x1, 0x1, 0x1},
32 {0xa000, 0x0, 0x1, 0x1},
33 {0xa000, 0x1, 0x1, 0x0},
34 {0xa001, 0x1, 0x1, 0x1},
35 {0xa001, 0x0, 0x1, 0x0},
36 {0xa001, 0x5, 0x1, 0x0},
37 {0xa00e, 0x0, 0x5, 0x10},
38 {0xa00f, 0x0, 0x3, 0x4},
39 {0xa00f, 0x3, 0x3, 0x5},
40 {0xa010, 0x0, 0x3, 0x4},
41 {0xa010, 0x3, 0x3, 0x5},
42 {0xa016, 0x4, 0x4, 0x3},
43 {0xa01f, 0x0, 0x6, 0xa},
44 {0xa020, 0x0, 0x6, 0xa},
45 {0xa2bc, 0x0, 0x1, 0x1},
46 {0xa2bc, 0x5, 0x1, 0x1},
47 {0xa015, 0x0, 0x8, 0x50},
48 {0xa016, 0x0, 0x1, 0x0},
49 {0xa02a, 0x0, 0x8, 0x50},
50 {0xa029, 0x0, 0x8, 0x4b},
51 {0xa614, 0x0, 0x8, 0x46},
52 {0xa002, 0x0, 0x5, 0x19},
53 {0xa003, 0x0, 0x5, 0x1a},
54 {0xa004, 0x0, 0x5, 0x19},
55 {0xa005, 0x0, 0x5, 0x1a},
56 {0xa008, 0x0, 0x8, 0x69},
57 {0xa009, 0x0, 0x2, 0x2},
58 {0xae1b, 0x0, 0x8, 0x69},
59 {0xae1c, 0x0, 0x8, 0x2},
60 {0xae1d, 0x0, 0x8, 0x2a},
61 {0xa022, 0x0, 0x8, 0xaa},
62 {0xa006, 0x0, 0x8, 0xc8},
63 {0xa007, 0x0, 0x2, 0x0},
64 {0xa00c, 0x0, 0x8, 0xba},
65 {0xa00d, 0x0, 0x2, 0x2},
66 {0xa608, 0x0, 0x8, 0xba},
67 {0xa60e, 0x0, 0x2, 0x2},
68 {0xa609, 0x0, 0x8, 0x80},
69 {0xa60e, 0x2, 0x2, 0x3},
70 {0xa00a, 0x0, 0x8, 0xb6},
71 {0xa00b, 0x0, 0x2, 0x0},
72 {0xa011, 0x0, 0x8, 0xb9},
73 {0xa012, 0x0, 0x2, 0x0},
74 {0xa013, 0x0, 0x8, 0xbd},
75 {0xa014, 0x0, 0x2, 0x2},
76 {0xa366, 0x0, 0x1, 0x1},
77 {0xa2bc, 0x3, 0x1, 0x0},
78 {0xa2bd, 0x0, 0x8, 0xa},
79 {0xa2be, 0x0, 0x8, 0x14},
80 {0xa2bf, 0x0, 0x8, 0x8},
81 {0xa60a, 0x0, 0x8, 0xbd},
82 {0xa60e, 0x4, 0x2, 0x2},
83 {0xa60b, 0x0, 0x8, 0x86},
84 {0xa60e, 0x6, 0x2, 0x3},
85 {0xa001, 0x2, 0x2, 0x1},
86 {0xa1c7, 0x0, 0x8, 0xf5},
87 {0xa03d, 0x0, 0x8, 0xb1},
88 {0xa616, 0x0, 0x8, 0xff},
89 {0xa617, 0x0, 0x8, 0xad},
90 {0xa618, 0x0, 0x8, 0xad},
91 {0xa61e, 0x3, 0x1, 0x1},
92 {0xae1a, 0x0, 0x8, 0x0},
93 {0xae19, 0x0, 0x8, 0xc8},
94 {0xae18, 0x0, 0x8, 0x61},
95 {0xa140, 0x0, 0x8, 0x0},
96 {0xa141, 0x0, 0x8, 0xc8},
97 {0xa142, 0x0, 0x7, 0x61},
98 {0xa023, 0x0, 0x8, 0xff},
99 {0xa021, 0x0, 0x8, 0xad},
100 {0xa026, 0x0, 0x1, 0x0},
101 {0xa024, 0x0, 0x8, 0xff},
102 {0xa025, 0x0, 0x8, 0xff},
103 {0xa1c8, 0x0, 0x8, 0xf},
104 {0xa2bc, 0x1, 0x1, 0x0},
105 {0xa60c, 0x0, 0x4, 0x5},
106 {0xa60c, 0x4, 0x4, 0x6},
107 {0xa60d, 0x0, 0x8, 0xa},
108 {0xa371, 0x0, 0x1, 0x1},
109 {0xa366, 0x1, 0x3, 0x7},
110 {0xa338, 0x0, 0x8, 0x10},
111 {0xa339, 0x0, 0x6, 0x7},
112 {0xa33a, 0x0, 0x6, 0x1f},
113 {0xa33b, 0x0, 0x8, 0xf6},
114 {0xa33c, 0x3, 0x5, 0x4},
115 {0xa33d, 0x4, 0x4, 0x0},
116 {0xa33d, 0x1, 0x1, 0x1},
117 {0xa33d, 0x2, 0x1, 0x1},
118 {0xa33d, 0x3, 0x1, 0x1},
119 {0xa16d, 0x0, 0x4, 0xf},
120 {0xa161, 0x0, 0x5, 0x5},
121 {0xa162, 0x0, 0x4, 0x5},
122 {0xa165, 0x0, 0x8, 0xff},
123 {0xa166, 0x0, 0x8, 0x9c},
124 {0xa2c3, 0x0, 0x4, 0x5},
125 {0xa61a, 0x0, 0x6, 0xf},
126 {0xb200, 0x0, 0x8, 0xa1},
127 {0xb201, 0x0, 0x8, 0x7},
128 {0xa093, 0x0, 0x1, 0x0},
129 {0xa093, 0x1, 0x5, 0xf},
130 {0xa094, 0x0, 0x8, 0xff},
131 {0xa095, 0x0, 0x8, 0xf},
132 {0xa080, 0x2, 0x5, 0x3},
133 {0xa081, 0x0, 0x4, 0x0},
134 {0xa081, 0x4, 0x4, 0x9},
135 {0xa082, 0x0, 0x5, 0x1f},
136 {0xa08d, 0x0, 0x8, 0x1},
137 {0xa083, 0x0, 0x8, 0x32},
138 {0xa084, 0x0, 0x1, 0x0},
139 {0xa08e, 0x0, 0x8, 0x3},
140 {0xa085, 0x0, 0x8, 0x32},
141 {0xa086, 0x0, 0x3, 0x0},
142 {0xa087, 0x0, 0x8, 0x6e},
143 {0xa088, 0x0, 0x5, 0x15},
144 {0xa089, 0x0, 0x8, 0x0},
145 {0xa08a, 0x0, 0x5, 0x19},
146 {0xa08b, 0x0, 0x8, 0x92},
147 {0xa08c, 0x0, 0x5, 0x1c},
148 {0xa120, 0x0, 0x8, 0x0},
149 {0xa121, 0x0, 0x5, 0x10},
150 {0xa122, 0x0, 0x8, 0x0},
151 {0xa123, 0x0, 0x7, 0x40},
152 {0xa123, 0x7, 0x1, 0x0},
153 {0xa124, 0x0, 0x8, 0x13},
154 {0xa125, 0x0, 0x7, 0x10},
155 {0xa1c0, 0x0, 0x8, 0x0},
156 {0xa1c1, 0x0, 0x5, 0x4},
157 {0xa1c2, 0x0, 0x8, 0x0},
158 {0xa1c3, 0x0, 0x5, 0x10},
159 {0xa1c3, 0x5, 0x3, 0x0},
160 {0xa1c4, 0x0, 0x6, 0x0},
161 {0xa1c5, 0x0, 0x7, 0x10},
162 {0xa100, 0x0, 0x8, 0x0},
163 {0xa101, 0x0, 0x5, 0x10},
164 {0xa102, 0x0, 0x8, 0x0},
165 {0xa103, 0x0, 0x7, 0x40},
166 {0xa103, 0x7, 0x1, 0x0},
167 {0xa104, 0x0, 0x8, 0x18},
168 {0xa105, 0x0, 0x7, 0xa},
169 {0xa106, 0x0, 0x8, 0x20},
170 {0xa107, 0x0, 0x8, 0x40},
171 {0xa108, 0x0, 0x4, 0x0},
172 {0xa38c, 0x0, 0x8, 0xfc},
173 {0xa38d, 0x0, 0x8, 0x0},
174 {0xa38e, 0x0, 0x8, 0x7e},
175 {0xa38f, 0x0, 0x8, 0x0},
176 {0xa390, 0x0, 0x8, 0x2f},
177 {0xa60f, 0x5, 0x1, 0x1},
178 {0xa170, 0x0, 0x8, 0xdc},
179 {0xa171, 0x0, 0x2, 0x0},
180 {0xa2ae, 0x0, 0x1, 0x1},
181 {0xa2ae, 0x1, 0x1, 0x1},
182 {0xa392, 0x0, 0x1, 0x1},
183 {0xa391, 0x2, 0x1, 0x0},
184 {0xabc1, 0x0, 0x8, 0xff},
185 {0xabc2, 0x0, 0x8, 0x0},
186 {0xabc8, 0x0, 0x8, 0x8},
187 {0xabca, 0x0, 0x8, 0x10},
188 {0xabcb, 0x0, 0x1, 0x0},
189 {0xabc3, 0x5, 0x3, 0x7},
190 {0xabc0, 0x6, 0x1, 0x0},
191 {0xabc0, 0x4, 0x2, 0x0},
192 {0xa344, 0x4, 0x4, 0x1},
193 {0xabc0, 0x7, 0x1, 0x1},
194 {0xabc0, 0x2, 0x1, 0x1},
195 {0xa345, 0x0, 0x8, 0x66},
196 {0xa346, 0x0, 0x8, 0x66},
197 {0xa347, 0x0, 0x4, 0x0},
198 {0xa343, 0x0, 0x4, 0xa},
199 {0xa347, 0x4, 0x4, 0x2},
200 {0xa348, 0x0, 0x4, 0xc},
201 {0xa348, 0x4, 0x4, 0x7},
202 {0xa349, 0x0, 0x6, 0x2},
203};
diff --git a/drivers/media/dvb/dvb-usb/af9005.c b/drivers/media/dvb/dvb-usb/af9005.c
new file mode 100644
index 000000000000..7db6eee50e39
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/af9005.c
@@ -0,0 +1,1141 @@
1/* DVB USB compliant Linux driver for the Afatech 9005
2 * USB1.1 DVB-T receiver.
3 *
4 * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
5 *
6 * Thanks to Afatech who kindly provided information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * see Documentation/dvb/REDME.dvb-usb for more information
23 */
24#include "af9005.h"
25
26/* debug */
27int dvb_usb_af9005_debug;
28module_param_named(debug, dvb_usb_af9005_debug, int, 0644);
29MODULE_PARM_DESC(debug,
30 "set debugging level (1=info,xfer=2,rc=4,reg=8,i2c=16,fw=32 (or-able))."
31 DVB_USB_DEBUG_STATUS);
32/* enable obnoxious led */
33int dvb_usb_af9005_led = 1;
34module_param_named(led, dvb_usb_af9005_led, bool, 0644);
35MODULE_PARM_DESC(led, "enable led (default: 1).");
36
37/* eeprom dump */
38int dvb_usb_af9005_dump_eeprom = 0;
39module_param_named(dump_eeprom, dvb_usb_af9005_dump_eeprom, int, 0);
40MODULE_PARM_DESC(dump_eeprom, "dump contents of the eeprom.");
41
42/* remote control decoder */
43int (*rc_decode) (struct dvb_usb_device * d, u8 * data, int len, u32 * event,
44 int *state);
45void *rc_keys;
46int *rc_keys_size;
47
48u8 regmask[8] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff };
49
50struct af9005_device_state {
51 u8 sequence;
52 int led_state;
53};
54
55int af9005_usb_generic_rw(struct dvb_usb_device *d, u8 * wbuf, u16 wlen,
56 u8 * rbuf, u16 rlen, int delay_ms)
57{
58 int actlen, ret = -ENOMEM;
59
60 if (wbuf == NULL || wlen == 0)
61 return -EINVAL;
62
63 if ((ret = mutex_lock_interruptible(&d->usb_mutex)))
64 return ret;
65
66 deb_xfer(">>> ");
67 debug_dump(wbuf, wlen, deb_xfer);
68
69 ret = usb_bulk_msg(d->udev, usb_sndbulkpipe(d->udev,
70 2), wbuf, wlen,
71 &actlen, 2000);
72
73 if (ret)
74 err("bulk message failed: %d (%d/%d)", ret, wlen, actlen);
75 else
76 ret = actlen != wlen ? -1 : 0;
77
78 /* an answer is expected, and no error before */
79 if (!ret && rbuf && rlen) {
80 if (delay_ms)
81 msleep(delay_ms);
82
83 ret = usb_bulk_msg(d->udev, usb_rcvbulkpipe(d->udev,
84 0x01), rbuf,
85 rlen, &actlen, 2000);
86
87 if (ret)
88 err("recv bulk message failed: %d", ret);
89 else {
90 deb_xfer("<<< ");
91 debug_dump(rbuf, actlen, deb_xfer);
92 }
93 }
94
95 mutex_unlock(&d->usb_mutex);
96 return ret;
97}
98
99int af9005_usb_generic_write(struct dvb_usb_device *d, u8 * buf, u16 len)
100{
101 return af9005_usb_generic_rw(d, buf, len, NULL, 0, 0);
102}
103
104int af9005_generic_read_write(struct dvb_usb_device *d, u16 reg,
105 int readwrite, int type, u8 * values, int len)
106{
107 struct af9005_device_state *st = d->priv;
108 u8 obuf[16] = { 0 };
109 u8 ibuf[17] = { 0 };
110 u8 command;
111 int i;
112 int ret;
113
114 if (len < 1) {
115 err("generic read/write, less than 1 byte. Makes no sense.");
116 return -EINVAL;
117 }
118 if (len > 8) {
119 err("generic read/write, more than 8 bytes. Not supported.");
120 return -EINVAL;
121 }
122
123 obuf[0] = 14; /* rest of buffer length low */
124 obuf[1] = 0; /* rest of buffer length high */
125
126 obuf[2] = AF9005_REGISTER_RW; /* register operation */
127 obuf[3] = 12; /* rest of buffer length */
128
129 obuf[4] = st->sequence++; /* sequence number */
130
131 obuf[5] = (u8) (reg >> 8); /* register address */
132 obuf[6] = (u8) (reg & 0xff);
133
134 if (type == AF9005_OFDM_REG) {
135 command = AF9005_CMD_OFDM_REG;
136 } else {
137 command = AF9005_CMD_TUNER;
138 }
139
140 if (len > 1)
141 command |=
142 AF9005_CMD_BURST | AF9005_CMD_AUTOINC | (len - 1) << 3;
143 command |= readwrite;
144 if (readwrite == AF9005_CMD_WRITE)
145 for (i = 0; i < len; i++)
146 obuf[8 + i] = values[i];
147 else if (type == AF9005_TUNER_REG)
148 /* read command for tuner, the first byte contains the i2c address */
149 obuf[8] = values[0];
150 obuf[7] = command;
151
152 ret = af9005_usb_generic_rw(d, obuf, 16, ibuf, 17, 0);
153 if (ret)
154 return ret;
155
156 /* sanity check */
157 if (ibuf[2] != AF9005_REGISTER_RW_ACK) {
158 err("generic read/write, wrong reply code.");
159 return -EIO;
160 }
161 if (ibuf[3] != 0x0d) {
162 err("generic read/write, wrong length in reply.");
163 return -EIO;
164 }
165 if (ibuf[4] != obuf[4]) {
166 err("generic read/write, wrong sequence in reply.");
167 return -EIO;
168 }
169 /*
170 Windows driver doesn't check these fields, in fact sometimes
171 the register in the reply is different that what has been sent
172
173 if (ibuf[5] != obuf[5] || ibuf[6] != obuf[6]) {
174 err("generic read/write, wrong register in reply.");
175 return -EIO;
176 }
177 if (ibuf[7] != command) {
178 err("generic read/write wrong command in reply.");
179 return -EIO;
180 }
181 */
182 if (ibuf[16] != 0x01) {
183 err("generic read/write wrong status code in reply.");
184 return -EIO;
185 }
186 if (readwrite == AF9005_CMD_READ)
187 for (i = 0; i < len; i++)
188 values[i] = ibuf[8 + i];
189
190 return 0;
191
192}
193
194int af9005_read_ofdm_register(struct dvb_usb_device *d, u16 reg, u8 * value)
195{
196 int ret;
197 deb_reg("read register %x ", reg);
198 ret = af9005_generic_read_write(d, reg,
199 AF9005_CMD_READ, AF9005_OFDM_REG,
200 value, 1);
201 if (ret)
202 deb_reg("failed\n");
203 else
204 deb_reg("value %x\n", *value);
205 return ret;
206}
207
208int af9005_read_ofdm_registers(struct dvb_usb_device *d, u16 reg,
209 u8 * values, int len)
210{
211 int ret;
212 deb_reg("read %d registers %x ", len, reg);
213 ret = af9005_generic_read_write(d, reg,
214 AF9005_CMD_READ, AF9005_OFDM_REG,
215 values, len);
216 if (ret)
217 deb_reg("failed\n");
218 else
219 debug_dump(values, len, deb_reg);
220 return ret;
221}
222
223int af9005_write_ofdm_register(struct dvb_usb_device *d, u16 reg, u8 value)
224{
225 int ret;
226 u8 temp = value;
227 deb_reg("write register %x value %x ", reg, value);
228 ret = af9005_generic_read_write(d, reg,
229 AF9005_CMD_WRITE, AF9005_OFDM_REG,
230 &temp, 1);
231 if (ret)
232 deb_reg("failed\n");
233 else
234 deb_reg("ok\n");
235 return ret;
236}
237
238int af9005_write_ofdm_registers(struct dvb_usb_device *d, u16 reg,
239 u8 * values, int len)
240{
241 int ret;
242 deb_reg("write %d registers %x values ", len, reg);
243 debug_dump(values, len, deb_reg);
244
245 ret = af9005_generic_read_write(d, reg,
246 AF9005_CMD_WRITE, AF9005_OFDM_REG,
247 values, len);
248 if (ret)
249 deb_reg("failed\n");
250 else
251 deb_reg("ok\n");
252 return ret;
253}
254
255int af9005_read_register_bits(struct dvb_usb_device *d, u16 reg, u8 pos,
256 u8 len, u8 * value)
257{
258 u8 temp;
259 int ret;
260 deb_reg("read bits %x %x %x", reg, pos, len);
261 ret = af9005_read_ofdm_register(d, reg, &temp);
262 if (ret) {
263 deb_reg(" failed\n");
264 return ret;
265 }
266 *value = (temp >> pos) & regmask[len - 1];
267 deb_reg(" value %x\n", *value);
268 return 0;
269
270}
271
272int af9005_write_register_bits(struct dvb_usb_device *d, u16 reg, u8 pos,
273 u8 len, u8 value)
274{
275 u8 temp, mask;
276 int ret;
277 deb_reg("write bits %x %x %x value %x\n", reg, pos, len, value);
278 if (pos == 0 && len == 8)
279 return af9005_write_ofdm_register(d, reg, value);
280 ret = af9005_read_ofdm_register(d, reg, &temp);
281 if (ret)
282 return ret;
283 mask = regmask[len - 1] << pos;
284 temp = (temp & ~mask) | ((value << pos) & mask);
285 return af9005_write_ofdm_register(d, reg, temp);
286
287}
288
289static int af9005_usb_read_tuner_registers(struct dvb_usb_device *d,
290 u16 reg, u8 * values, int len)
291{
292 return af9005_generic_read_write(d, reg,
293 AF9005_CMD_READ, AF9005_TUNER_REG,
294 values, len);
295}
296
297static int af9005_usb_write_tuner_registers(struct dvb_usb_device *d,
298 u16 reg, u8 * values, int len)
299{
300 return af9005_generic_read_write(d, reg,
301 AF9005_CMD_WRITE,
302 AF9005_TUNER_REG, values, len);
303}
304
305int af9005_write_tuner_registers(struct dvb_usb_device *d, u16 reg,
306 u8 * values, int len)
307{
308 /* don't let the name of this function mislead you: it's just used
309 as an interface from the firmware to the i2c bus. The actual
310 i2c addresses are contained in the data */
311 int ret, i, done = 0, fail = 0;
312 u8 temp;
313 ret = af9005_usb_write_tuner_registers(d, reg, values, len);
314 if (ret)
315 return ret;
316 if (reg != 0xffff) {
317 /* check if write done (0xa40d bit 1) or fail (0xa40d bit 2) */
318 for (i = 0; i < 200; i++) {
319 ret =
320 af9005_read_ofdm_register(d,
321 xd_I2C_i2c_m_status_wdat_done,
322 &temp);
323 if (ret)
324 return ret;
325 done = temp & (regmask[i2c_m_status_wdat_done_len - 1]
326 << i2c_m_status_wdat_done_pos);
327 if (done)
328 break;
329 fail = temp & (regmask[i2c_m_status_wdat_fail_len - 1]
330 << i2c_m_status_wdat_fail_pos);
331 if (fail)
332 break;
333 msleep(50);
334 }
335 if (i == 200)
336 return -ETIMEDOUT;
337 if (fail) {
338 /* clear write fail bit */
339 af9005_write_register_bits(d,
340 xd_I2C_i2c_m_status_wdat_fail,
341 i2c_m_status_wdat_fail_pos,
342 i2c_m_status_wdat_fail_len,
343 1);
344 return -EIO;
345 }
346 /* clear write done bit */
347 ret =
348 af9005_write_register_bits(d,
349 xd_I2C_i2c_m_status_wdat_fail,
350 i2c_m_status_wdat_done_pos,
351 i2c_m_status_wdat_done_len, 1);
352 if (ret)
353 return ret;
354 }
355 return 0;
356}
357
358int af9005_read_tuner_registers(struct dvb_usb_device *d, u16 reg, u8 addr,
359 u8 * values, int len)
360{
361 /* don't let the name of this function mislead you: it's just used
362 as an interface from the firmware to the i2c bus. The actual
363 i2c addresses are contained in the data */
364 int ret, i;
365 u8 temp, buf[2];
366
367 buf[0] = addr; /* tuner i2c address */
368 buf[1] = values[0]; /* tuner register */
369
370 values[0] = addr + 0x01; /* i2c read address */
371
372 if (reg == APO_REG_I2C_RW_SILICON_TUNER) {
373 /* write tuner i2c address to tuner, 0c00c0 undocumented, found by sniffing */
374 ret = af9005_write_tuner_registers(d, 0x00c0, buf, 2);
375 if (ret)
376 return ret;
377 }
378
379 /* send read command to ofsm */
380 ret = af9005_usb_read_tuner_registers(d, reg, values, 1);
381 if (ret)
382 return ret;
383
384 /* check if read done */
385 for (i = 0; i < 200; i++) {
386 ret = af9005_read_ofdm_register(d, 0xa408, &temp);
387 if (ret)
388 return ret;
389 if (temp & 0x01)
390 break;
391 msleep(50);
392 }
393 if (i == 200)
394 return -ETIMEDOUT;
395
396 /* clear read done bit (by writing 1) */
397 ret = af9005_write_ofdm_register(d, xd_I2C_i2c_m_data8, 1);
398 if (ret)
399 return ret;
400
401 /* get read data (available from 0xa400) */
402 for (i = 0; i < len; i++) {
403 ret = af9005_read_ofdm_register(d, 0xa400 + i, &temp);
404 if (ret)
405 return ret;
406 values[i] = temp;
407 }
408 return 0;
409}
410
411static int af9005_i2c_write(struct dvb_usb_device *d, u8 i2caddr, u8 reg,
412 u8 * data, int len)
413{
414 int ret, i;
415 u8 buf[3];
416 deb_i2c("i2c_write i2caddr %x, reg %x, len %d data ", i2caddr,
417 reg, len);
418 debug_dump(data, len, deb_i2c);
419
420 for (i = 0; i < len; i++) {
421 buf[0] = i2caddr;
422 buf[1] = reg + (u8) i;
423 buf[2] = data[i];
424 ret =
425 af9005_write_tuner_registers(d,
426 APO_REG_I2C_RW_SILICON_TUNER,
427 buf, 3);
428 if (ret) {
429 deb_i2c("i2c_write failed\n");
430 return ret;
431 }
432 }
433 deb_i2c("i2c_write ok\n");
434 return 0;
435}
436
437static int af9005_i2c_read(struct dvb_usb_device *d, u8 i2caddr, u8 reg,
438 u8 * data, int len)
439{
440 int ret, i;
441 u8 temp;
442 deb_i2c("i2c_read i2caddr %x, reg %x, len %d\n ", i2caddr, reg, len);
443 for (i = 0; i < len; i++) {
444 temp = reg + i;
445 ret =
446 af9005_read_tuner_registers(d,
447 APO_REG_I2C_RW_SILICON_TUNER,
448 i2caddr, &temp, 1);
449 if (ret) {
450 deb_i2c("i2c_read failed\n");
451 return ret;
452 }
453 data[i] = temp;
454 }
455 deb_i2c("i2c data read: ");
456 debug_dump(data, len, deb_i2c);
457 return 0;
458}
459
460static int af9005_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[],
461 int num)
462{
463 /* only implements what the mt2060 module does, don't know how
464 to make it really generic */
465 struct dvb_usb_device *d = i2c_get_adapdata(adap);
466 int ret;
467 u8 reg, addr;
468 u8 *value;
469
470 if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
471 return -EAGAIN;
472
473 if (num > 2)
474 warn("more than 2 i2c messages at a time is not handled yet. TODO.");
475
476 if (num == 2) {
477 /* reads a single register */
478 reg = *msg[0].buf;
479 addr = msg[0].addr;
480 value = msg[1].buf;
481 ret = af9005_i2c_read(d, addr, reg, value, 1);
482 if (ret == 0)
483 ret = 2;
484 } else {
485 /* write one or more registers */
486 reg = msg[0].buf[0];
487 addr = msg[0].addr;
488 value = &msg[0].buf[1];
489 ret = af9005_i2c_write(d, addr, reg, value, msg[0].len - 1);
490 if (ret == 0)
491 ret = 1;
492 }
493
494 mutex_unlock(&d->i2c_mutex);
495 return ret;
496}
497
498static u32 af9005_i2c_func(struct i2c_adapter *adapter)
499{
500 return I2C_FUNC_I2C;
501}
502
503static struct i2c_algorithm af9005_i2c_algo = {
504 .master_xfer = af9005_i2c_xfer,
505 .functionality = af9005_i2c_func,
506};
507
508int af9005_send_command(struct dvb_usb_device *d, u8 command, u8 * wbuf,
509 int wlen, u8 * rbuf, int rlen)
510{
511 struct af9005_device_state *st = d->priv;
512
513 int ret, i, packet_len;
514 u8 buf[64];
515 u8 ibuf[64];
516
517 if (wlen < 0) {
518 err("send command, wlen less than 0 bytes. Makes no sense.");
519 return -EINVAL;
520 }
521 if (wlen > 54) {
522 err("send command, wlen more than 54 bytes. Not supported.");
523 return -EINVAL;
524 }
525 if (rlen > 54) {
526 err("send command, rlen more than 54 bytes. Not supported.");
527 return -EINVAL;
528 }
529 packet_len = wlen + 5;
530 buf[0] = (u8) (packet_len & 0xff);
531 buf[1] = (u8) ((packet_len & 0xff00) >> 8);
532
533 buf[2] = 0x26; /* packet type */
534 buf[3] = wlen + 3;
535 buf[4] = st->sequence++;
536 buf[5] = command;
537 buf[6] = wlen;
538 for (i = 0; i < wlen; i++)
539 buf[7 + i] = wbuf[i];
540 ret = af9005_usb_generic_rw(d, buf, wlen + 7, ibuf, rlen + 7, 0);
541 if (ret)
542 return ret;
543 if (ibuf[2] != 0x27) {
544 err("send command, wrong reply code.");
545 return -EIO;
546 }
547 if (ibuf[4] != buf[4]) {
548 err("send command, wrong sequence in reply.");
549 return -EIO;
550 }
551 if (ibuf[5] != 0x01) {
552 err("send command, wrong status code in reply.");
553 return -EIO;
554 }
555 if (ibuf[6] != rlen) {
556 err("send command, invalid data length in reply.");
557 return -EIO;
558 }
559 for (i = 0; i < rlen; i++)
560 rbuf[i] = ibuf[i + 7];
561 return 0;
562}
563
564int af9005_read_eeprom(struct dvb_usb_device *d, u8 address, u8 * values,
565 int len)
566{
567 struct af9005_device_state *st = d->priv;
568 u8 obuf[16], ibuf[14];
569 int ret, i;
570
571 memset(obuf, 0, sizeof(obuf));
572 memset(ibuf, 0, sizeof(ibuf));
573
574 obuf[0] = 14; /* length of rest of packet low */
575 obuf[1] = 0; /* length of rest of packer high */
576
577 obuf[2] = 0x2a; /* read/write eeprom */
578
579 obuf[3] = 12; /* size */
580
581 obuf[4] = st->sequence++;
582
583 obuf[5] = 0; /* read */
584
585 obuf[6] = len;
586 obuf[7] = address;
587 ret = af9005_usb_generic_rw(d, obuf, 16, ibuf, 14, 0);
588 if (ret)
589 return ret;
590 if (ibuf[2] != 0x2b) {
591 err("Read eeprom, invalid reply code");
592 return -EIO;
593 }
594 if (ibuf[3] != 10) {
595 err("Read eeprom, invalid reply length");
596 return -EIO;
597 }
598 if (ibuf[4] != obuf[4]) {
599 err("Read eeprom, wrong sequence in reply ");
600 return -EIO;
601 }
602 if (ibuf[5] != 1) {
603 err("Read eeprom, wrong status in reply ");
604 return -EIO;
605 }
606 for (i = 0; i < len; i++) {
607 values[i] = ibuf[6 + i];
608 }
609 return 0;
610}
611
612static int af9005_boot_packet(struct usb_device *udev, int type, u8 * reply)
613{
614 u8 buf[FW_BULKOUT_SIZE + 2];
615 u16 checksum;
616 int act_len, i, ret;
617 memset(buf, 0, sizeof(buf));
618 buf[0] = (u8) (FW_BULKOUT_SIZE & 0xff);
619 buf[1] = (u8) ((FW_BULKOUT_SIZE >> 8) & 0xff);
620 switch (type) {
621 case FW_CONFIG:
622 buf[2] = 0x11;
623 buf[3] = 0x04;
624 buf[4] = 0x00; /* sequence number, original driver doesn't increment it here */
625 buf[5] = 0x03;
626 checksum = buf[4] + buf[5];
627 buf[6] = (u8) ((checksum >> 8) & 0xff);
628 buf[7] = (u8) (checksum & 0xff);
629 break;
630 case FW_CONFIRM:
631 buf[2] = 0x11;
632 buf[3] = 0x04;
633 buf[4] = 0x00; /* sequence number, original driver doesn't increment it here */
634 buf[5] = 0x01;
635 checksum = buf[4] + buf[5];
636 buf[6] = (u8) ((checksum >> 8) & 0xff);
637 buf[7] = (u8) (checksum & 0xff);
638 break;
639 case FW_BOOT:
640 buf[2] = 0x10;
641 buf[3] = 0x08;
642 buf[4] = 0x00; /* sequence number, original driver doesn't increment it here */
643 buf[5] = 0x97;
644 buf[6] = 0xaa;
645 buf[7] = 0x55;
646 buf[8] = 0xa5;
647 buf[9] = 0x5a;
648 checksum = 0;
649 for (i = 4; i <= 9; i++)
650 checksum += buf[i];
651 buf[10] = (u8) ((checksum >> 8) & 0xff);
652 buf[11] = (u8) (checksum & 0xff);
653 break;
654 default:
655 err("boot packet invalid boot packet type");
656 return -EINVAL;
657 }
658 deb_fw(">>> ");
659 debug_dump(buf, FW_BULKOUT_SIZE + 2, deb_fw);
660
661 ret = usb_bulk_msg(udev,
662 usb_sndbulkpipe(udev, 0x02),
663 buf, FW_BULKOUT_SIZE + 2, &act_len, 2000);
664 if (ret)
665 err("boot packet bulk message failed: %d (%d/%d)", ret,
666 FW_BULKOUT_SIZE + 2, act_len);
667 else
668 ret = act_len != FW_BULKOUT_SIZE + 2 ? -1 : 0;
669 if (ret)
670 return ret;
671 memset(buf, 0, 9);
672 ret = usb_bulk_msg(udev,
673 usb_rcvbulkpipe(udev, 0x01), buf, 9, &act_len, 2000);
674 if (ret) {
675 err("boot packet recv bulk message failed: %d", ret);
676 return ret;
677 }
678 deb_fw("<<< ");
679 debug_dump(buf, act_len, deb_fw);
680 checksum = 0;
681 switch (type) {
682 case FW_CONFIG:
683 if (buf[2] != 0x11) {
684 err("boot bad config header.");
685 return -EIO;
686 }
687 if (buf[3] != 0x05) {
688 err("boot bad config size.");
689 return -EIO;
690 }
691 if (buf[4] != 0x00) {
692 err("boot bad config sequence.");
693 return -EIO;
694 }
695 if (buf[5] != 0x04) {
696 err("boot bad config subtype.");
697 return -EIO;
698 }
699 for (i = 4; i <= 6; i++)
700 checksum += buf[i];
701 if (buf[7] * 256 + buf[8] != checksum) {
702 err("boot bad config checksum.");
703 return -EIO;
704 }
705 *reply = buf[6];
706 break;
707 case FW_CONFIRM:
708 if (buf[2] != 0x11) {
709 err("boot bad confirm header.");
710 return -EIO;
711 }
712 if (buf[3] != 0x05) {
713 err("boot bad confirm size.");
714 return -EIO;
715 }
716 if (buf[4] != 0x00) {
717 err("boot bad confirm sequence.");
718 return -EIO;
719 }
720 if (buf[5] != 0x02) {
721 err("boot bad confirm subtype.");
722 return -EIO;
723 }
724 for (i = 4; i <= 6; i++)
725 checksum += buf[i];
726 if (buf[7] * 256 + buf[8] != checksum) {
727 err("boot bad confirm checksum.");
728 return -EIO;
729 }
730 *reply = buf[6];
731 break;
732 case FW_BOOT:
733 if (buf[2] != 0x10) {
734 err("boot bad boot header.");
735 return -EIO;
736 }
737 if (buf[3] != 0x05) {
738 err("boot bad boot size.");
739 return -EIO;
740 }
741 if (buf[4] != 0x00) {
742 err("boot bad boot sequence.");
743 return -EIO;
744 }
745 if (buf[5] != 0x01) {
746 err("boot bad boot pattern 01.");
747 return -EIO;
748 }
749 if (buf[6] != 0x10) {
750 err("boot bad boot pattern 10.");
751 return -EIO;
752 }
753 for (i = 4; i <= 6; i++)
754 checksum += buf[i];
755 if (buf[7] * 256 + buf[8] != checksum) {
756 err("boot bad boot checksum.");
757 return -EIO;
758 }
759 break;
760
761 }
762
763 return 0;
764}
765
766int af9005_download_firmware(struct usb_device *udev, const struct firmware *fw)
767{
768 int i, packets, ret, act_len;
769
770 u8 buf[FW_BULKOUT_SIZE + 2];
771 u8 reply;
772
773 ret = af9005_boot_packet(udev, FW_CONFIG, &reply);
774 if (ret)
775 return ret;
776 if (reply != 0x01) {
777 err("before downloading firmware, FW_CONFIG expected 0x01, received 0x%x", reply);
778 return -EIO;
779 }
780 packets = fw->size / FW_BULKOUT_SIZE;
781 buf[0] = (u8) (FW_BULKOUT_SIZE & 0xff);
782 buf[1] = (u8) ((FW_BULKOUT_SIZE >> 8) & 0xff);
783 for (i = 0; i < packets; i++) {
784 memcpy(&buf[2], fw->data + i * FW_BULKOUT_SIZE,
785 FW_BULKOUT_SIZE);
786 deb_fw(">>> ");
787 debug_dump(buf, FW_BULKOUT_SIZE + 2, deb_fw);
788 ret = usb_bulk_msg(udev,
789 usb_sndbulkpipe(udev, 0x02),
790 buf, FW_BULKOUT_SIZE + 2, &act_len, 1000);
791 if (ret) {
792 err("firmware download failed at packet %d with code %d", i, ret);
793 return ret;
794 }
795 }
796 ret = af9005_boot_packet(udev, FW_CONFIRM, &reply);
797 if (ret)
798 return ret;
799 if (reply != (u8) (packets & 0xff)) {
800 err("after downloading firmware, FW_CONFIRM expected 0x%x, received 0x%x", packets & 0xff, reply);
801 return -EIO;
802 }
803 ret = af9005_boot_packet(udev, FW_BOOT, &reply);
804 if (ret)
805 return ret;
806 ret = af9005_boot_packet(udev, FW_CONFIG, &reply);
807 if (ret)
808 return ret;
809 if (reply != 0x02) {
810 err("after downloading firmware, FW_CONFIG expected 0x02, received 0x%x", reply);
811 return -EIO;
812 }
813
814 return 0;
815
816}
817
818int af9005_led_control(struct dvb_usb_device *d, int onoff)
819{
820 struct af9005_device_state *st = d->priv;
821 int temp, ret;
822
823 if (onoff && dvb_usb_af9005_led)
824 temp = 1;
825 else
826 temp = 0;
827 if (st->led_state != temp) {
828 ret =
829 af9005_write_register_bits(d, xd_p_reg_top_locken1,
830 reg_top_locken1_pos,
831 reg_top_locken1_len, temp);
832 if (ret)
833 return ret;
834 ret =
835 af9005_write_register_bits(d, xd_p_reg_top_lock1,
836 reg_top_lock1_pos,
837 reg_top_lock1_len, temp);
838 if (ret)
839 return ret;
840 st->led_state = temp;
841 }
842 return 0;
843}
844
845static int af9005_frontend_attach(struct dvb_usb_adapter *adap)
846{
847 u8 buf[8];
848 int i;
849
850 /* without these calls the first commands after downloading
851 the firmware fail. I put these calls here to simulate
852 what it is done in dvb-usb-init.c.
853 */
854 struct usb_device *udev = adap->dev->udev;
855 usb_clear_halt(udev, usb_sndbulkpipe(udev, 2));
856 usb_clear_halt(udev, usb_rcvbulkpipe(udev, 1));
857 if (dvb_usb_af9005_dump_eeprom) {
858 printk("EEPROM DUMP\n");
859 for (i = 0; i < 255; i += 8) {
860 af9005_read_eeprom(adap->dev, i, buf, 8);
861 printk("ADDR %x ", i);
862 debug_dump(buf, 8, printk);
863 }
864 }
865 adap->fe = af9005_fe_attach(adap->dev);
866 return 0;
867}
868
869static int af9005_rc_query(struct dvb_usb_device *d, u32 * event, int *state)
870{
871 struct af9005_device_state *st = d->priv;
872 int ret, len;
873
874 u8 obuf[5];
875 u8 ibuf[256];
876
877 *state = REMOTE_NO_KEY_PRESSED;
878 if (rc_decode == NULL) {
879 /* it shouldn't never come here */
880 return 0;
881 }
882 /* deb_info("rc_query\n"); */
883 obuf[0] = 3; /* rest of packet length low */
884 obuf[1] = 0; /* rest of packet lentgh high */
885 obuf[2] = 0x40; /* read remote */
886 obuf[3] = 1; /* rest of packet length */
887 obuf[4] = st->sequence++; /* sequence number */
888 ret = af9005_usb_generic_rw(d, obuf, 5, ibuf, 256, 0);
889 if (ret) {
890 err("rc query failed");
891 return ret;
892 }
893 if (ibuf[2] != 0x41) {
894 err("rc query bad header.");
895 return -EIO;
896 }
897 if (ibuf[4] != obuf[4]) {
898 err("rc query bad sequence.");
899 return -EIO;
900 }
901 len = ibuf[5];
902 if (len > 246) {
903 err("rc query invalid length");
904 return -EIO;
905 }
906 if (len > 0) {
907 deb_rc("rc data (%d) ", len);
908 debug_dump((ibuf + 6), len, deb_rc);
909 ret = rc_decode(d, &ibuf[6], len, event, state);
910 if (ret) {
911 err("rc_decode failed");
912 return ret;
913 } else {
914 deb_rc("rc_decode state %x event %x\n", *state, *event);
915 if (*state == REMOTE_KEY_REPEAT)
916 *event = d->last_event;
917 }
918 }
919 return 0;
920}
921
922static int af9005_power_ctrl(struct dvb_usb_device *d, int onoff)
923{
924
925 return 0;
926}
927
928static int af9005_pid_filter_control(struct dvb_usb_adapter *adap, int onoff)
929{
930 int ret;
931 deb_info("pid filter control onoff %d\n", onoff);
932 if (onoff) {
933 ret =
934 af9005_write_ofdm_register(adap->dev, XD_MP2IF_DMX_CTRL, 1);
935 if (ret)
936 return ret;
937 ret =
938 af9005_write_register_bits(adap->dev,
939 XD_MP2IF_DMX_CTRL, 1, 1, 1);
940 if (ret)
941 return ret;
942 ret =
943 af9005_write_ofdm_register(adap->dev, XD_MP2IF_DMX_CTRL, 1);
944 } else
945 ret =
946 af9005_write_ofdm_register(adap->dev, XD_MP2IF_DMX_CTRL, 0);
947 if (ret)
948 return ret;
949 deb_info("pid filter control ok\n");
950 return 0;
951}
952
953static int af9005_pid_filter(struct dvb_usb_adapter *adap, int index,
954 u16 pid, int onoff)
955{
956 u8 cmd = index & 0x1f;
957 int ret;
958 deb_info("set pid filter, index %d, pid %x, onoff %d\n", index,
959 pid, onoff);
960 if (onoff) {
961 /* cannot use it as pid_filter_ctrl since it has to be done
962 before setting the first pid */
963 if (adap->feedcount == 1) {
964 deb_info("first pid set, enable pid table\n");
965 ret = af9005_pid_filter_control(adap, onoff);
966 if (ret)
967 return ret;
968 }
969 ret =
970 af9005_write_ofdm_register(adap->dev,
971 XD_MP2IF_PID_DATA_L,
972 (u8) (pid & 0xff));
973 if (ret)
974 return ret;
975 ret =
976 af9005_write_ofdm_register(adap->dev,
977 XD_MP2IF_PID_DATA_H,
978 (u8) (pid >> 8));
979 if (ret)
980 return ret;
981 cmd |= 0x20 | 0x40;
982 } else {
983 if (adap->feedcount == 0) {
984 deb_info("last pid unset, disable pid table\n");
985 ret = af9005_pid_filter_control(adap, onoff);
986 if (ret)
987 return ret;
988 }
989 }
990 ret = af9005_write_ofdm_register(adap->dev, XD_MP2IF_PID_IDX, cmd);
991 if (ret)
992 return ret;
993 deb_info("set pid ok\n");
994 return 0;
995}
996
997static int af9005_identify_state(struct usb_device *udev,
998 struct dvb_usb_device_properties *props,
999 struct dvb_usb_device_description **desc,
1000 int *cold)
1001{
1002 int ret;
1003 u8 reply;
1004 ret = af9005_boot_packet(udev, FW_CONFIG, &reply);
1005 if (ret)
1006 return ret;
1007 deb_info("result of FW_CONFIG in identify state %d\n", reply);
1008 if (reply == 0x01)
1009 *cold = 1;
1010 else if (reply == 0x02)
1011 *cold = 0;
1012 else
1013 return -EIO;
1014 deb_info("Identify state cold = %d\n", *cold);
1015 return 0;
1016}
1017
1018static struct dvb_usb_device_properties af9005_properties;
1019
1020static int af9005_usb_probe(struct usb_interface *intf,
1021 const struct usb_device_id *id)
1022{
1023 return dvb_usb_device_init(intf, &af9005_properties, THIS_MODULE, NULL);
1024}
1025
1026static struct usb_device_id af9005_usb_table[] = {
1027 {USB_DEVICE(USB_VID_AFATECH, USB_PID_AFATECH_AF9005)},
1028 {USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_T_USB_XE)},
1029 {0},
1030};
1031
1032MODULE_DEVICE_TABLE(usb, af9005_usb_table);
1033
1034static struct dvb_usb_device_properties af9005_properties = {
1035 .caps = DVB_USB_IS_AN_I2C_ADAPTER,
1036
1037 .usb_ctrl = DEVICE_SPECIFIC,
1038 .firmware = "af9005.fw",
1039 .download_firmware = af9005_download_firmware,
1040 .no_reconnect = 1,
1041
1042 .size_of_priv = sizeof(struct af9005_device_state),
1043
1044 .num_adapters = 1,
1045 .adapter = {
1046 {
1047 .caps =
1048 DVB_USB_ADAP_HAS_PID_FILTER |
1049 DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
1050 .pid_filter_count = 32,
1051 .pid_filter = af9005_pid_filter,
1052 /* .pid_filter_ctrl = af9005_pid_filter_control, */
1053 .frontend_attach = af9005_frontend_attach,
1054 /* .tuner_attach = af9005_tuner_attach, */
1055 /* parameter for the MPEG2-data transfer */
1056 .stream = {
1057 .type = USB_BULK,
1058 .count = 10,
1059 .endpoint = 0x04,
1060 .u = {
1061 .bulk = {
1062 .buffersize = 4096, /* actual size seen is 3948 */
1063 }
1064 }
1065 },
1066 }
1067 },
1068 .power_ctrl = af9005_power_ctrl,
1069 .identify_state = af9005_identify_state,
1070
1071 .i2c_algo = &af9005_i2c_algo,
1072
1073 .rc_interval = 200,
1074 .rc_key_map = NULL,
1075 .rc_key_map_size = 0,
1076 .rc_query = af9005_rc_query,
1077
1078 .num_device_descs = 2,
1079 .devices = {
1080 {.name = "Afatech DVB-T USB1.1 stick",
1081 .cold_ids = {&af9005_usb_table[0], NULL},
1082 .warm_ids = {NULL},
1083 },
1084 {.name = "TerraTec Cinergy T USB XE",
1085 .cold_ids = {&af9005_usb_table[1], NULL},
1086 .warm_ids = {NULL},
1087 },
1088 {NULL},
1089 }
1090};
1091
1092/* usb specific object needed to register this driver with the usb subsystem */
1093static struct usb_driver af9005_usb_driver = {
1094 .name = "dvb_usb_af9005",
1095 .probe = af9005_usb_probe,
1096 .disconnect = dvb_usb_device_exit,
1097 .id_table = af9005_usb_table,
1098};
1099
1100/* module stuff */
1101static int __init af9005_usb_module_init(void)
1102{
1103 int result;
1104 if ((result = usb_register(&af9005_usb_driver))) {
1105 err("usb_register failed. (%d)", result);
1106 return result;
1107 }
1108 rc_decode = symbol_request(af9005_rc_decode);
1109 rc_keys = symbol_request(af9005_rc_keys);
1110 rc_keys_size = symbol_request(af9005_rc_keys_size);
1111 if (rc_decode == NULL || rc_keys == NULL || rc_keys_size == NULL) {
1112 err("af9005_rc_decode function not found, disabling remote");
1113 af9005_properties.rc_query = NULL;
1114 } else {
1115 af9005_properties.rc_key_map = rc_keys;
1116 af9005_properties.rc_key_map_size = *rc_keys_size;
1117 }
1118
1119 return 0;
1120}
1121
1122static void __exit af9005_usb_module_exit(void)
1123{
1124 /* release rc decode symbols */
1125 if (rc_decode != NULL)
1126 symbol_put(af9005_rc_decode);
1127 if (rc_keys != NULL)
1128 symbol_put(af9005_rc_keys);
1129 if (rc_keys_size != NULL)
1130 symbol_put(af9005_rc_keys_size);
1131 /* deregister this driver from the USB subsystem */
1132 usb_deregister(&af9005_usb_driver);
1133}
1134
1135module_init(af9005_usb_module_init);
1136module_exit(af9005_usb_module_exit);
1137
1138MODULE_AUTHOR("Luca Olivetti <luca@ventoso.org>");
1139MODULE_DESCRIPTION("Driver for Afatech 9005 DVB-T USB1.1 stick");
1140MODULE_VERSION("1.0");
1141MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/dvb-usb/af9005.h b/drivers/media/dvb/dvb-usb/af9005.h
new file mode 100644
index 000000000000..0bc48a012187
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/af9005.h
@@ -0,0 +1,3496 @@
1/* Common header-file of the Linux driver for the Afatech 9005
2 * USB1.1 DVB-T receiver.
3 *
4 * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
5 *
6 * Thanks to Afatech who kindly provided information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * see Documentation/dvb/README.dvb-usb for more information
23 */
24#ifndef _DVB_USB_AF9005_H_
25#define _DVB_USB_AF9005_H_
26
27#define DVB_USB_LOG_PREFIX "af9005"
28#include "dvb-usb.h"
29
30extern int dvb_usb_af9005_debug;
31#define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args)
32#define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args)
33#define deb_rc(args...) dprintk(dvb_usb_af9005_debug,0x04,args)
34#define deb_reg(args...) dprintk(dvb_usb_af9005_debug,0x08,args)
35#define deb_i2c(args...) dprintk(dvb_usb_af9005_debug,0x10,args)
36#define deb_fw(args...) dprintk(dvb_usb_af9005_debug,0x20,args)
37
38extern int dvb_usb_af9005_led;
39
40/* firmware */
41#define FW_BULKOUT_SIZE 250
42enum {
43 FW_CONFIG,
44 FW_CONFIRM,
45 FW_BOOT
46};
47
48/* af9005 commands */
49#define AF9005_OFDM_REG 0
50#define AF9005_TUNER_REG 1
51
52#define AF9005_REGISTER_RW 0x20
53#define AF9005_REGISTER_RW_ACK 0x21
54
55#define AF9005_CMD_OFDM_REG 0x00
56#define AF9005_CMD_TUNER 0x80
57#define AF9005_CMD_BURST 0x02
58#define AF9005_CMD_AUTOINC 0x04
59#define AF9005_CMD_READ 0x00
60#define AF9005_CMD_WRITE 0x01
61
62/* af9005 registers */
63#define APO_REG_RESET 0xAEFF
64
65#define APO_REG_I2C_RW_CAN_TUNER 0xF000
66#define APO_REG_I2C_RW_SILICON_TUNER 0xF001
67#define APO_REG_GPIO_RW_SILICON_TUNER 0xFFFE /* also for OFSM */
68#define APO_REG_TRIGGER_OFSM 0xFFFF /* also for OFSM */
69
70/***********************************************************************
71 * Apollo Registers from VLSI *
72 ***********************************************************************/
73#define xd_p_reg_aagc_inverted_agc 0xA000
74#define reg_aagc_inverted_agc_pos 0
75#define reg_aagc_inverted_agc_len 1
76#define reg_aagc_inverted_agc_lsb 0
77#define xd_p_reg_aagc_sign_only 0xA000
78#define reg_aagc_sign_only_pos 1
79#define reg_aagc_sign_only_len 1
80#define reg_aagc_sign_only_lsb 0
81#define xd_p_reg_aagc_slow_adc_en 0xA000
82#define reg_aagc_slow_adc_en_pos 2
83#define reg_aagc_slow_adc_en_len 1
84#define reg_aagc_slow_adc_en_lsb 0
85#define xd_p_reg_aagc_slow_adc_scale 0xA000
86#define reg_aagc_slow_adc_scale_pos 3
87#define reg_aagc_slow_adc_scale_len 5
88#define reg_aagc_slow_adc_scale_lsb 0
89#define xd_p_reg_aagc_check_slow_adc_lock 0xA001
90#define reg_aagc_check_slow_adc_lock_pos 0
91#define reg_aagc_check_slow_adc_lock_len 1
92#define reg_aagc_check_slow_adc_lock_lsb 0
93#define xd_p_reg_aagc_init_control 0xA001
94#define reg_aagc_init_control_pos 1
95#define reg_aagc_init_control_len 1
96#define reg_aagc_init_control_lsb 0
97#define xd_p_reg_aagc_total_gain_sel 0xA001
98#define reg_aagc_total_gain_sel_pos 2
99#define reg_aagc_total_gain_sel_len 2
100#define reg_aagc_total_gain_sel_lsb 0
101#define xd_p_reg_aagc_out_inv 0xA001
102#define reg_aagc_out_inv_pos 5
103#define reg_aagc_out_inv_len 1
104#define reg_aagc_out_inv_lsb 0
105#define xd_p_reg_aagc_int_en 0xA001
106#define reg_aagc_int_en_pos 6
107#define reg_aagc_int_en_len 1
108#define reg_aagc_int_en_lsb 0
109#define xd_p_reg_aagc_lock_change_flag 0xA001
110#define reg_aagc_lock_change_flag_pos 7
111#define reg_aagc_lock_change_flag_len 1
112#define reg_aagc_lock_change_flag_lsb 0
113#define xd_p_reg_aagc_rf_loop_bw_scale_acquire 0xA002
114#define reg_aagc_rf_loop_bw_scale_acquire_pos 0
115#define reg_aagc_rf_loop_bw_scale_acquire_len 5
116#define reg_aagc_rf_loop_bw_scale_acquire_lsb 0
117#define xd_p_reg_aagc_rf_loop_bw_scale_track 0xA003
118#define reg_aagc_rf_loop_bw_scale_track_pos 0
119#define reg_aagc_rf_loop_bw_scale_track_len 5
120#define reg_aagc_rf_loop_bw_scale_track_lsb 0
121#define xd_p_reg_aagc_if_loop_bw_scale_acquire 0xA004
122#define reg_aagc_if_loop_bw_scale_acquire_pos 0
123#define reg_aagc_if_loop_bw_scale_acquire_len 5
124#define reg_aagc_if_loop_bw_scale_acquire_lsb 0
125#define xd_p_reg_aagc_if_loop_bw_scale_track 0xA005
126#define reg_aagc_if_loop_bw_scale_track_pos 0
127#define reg_aagc_if_loop_bw_scale_track_len 5
128#define reg_aagc_if_loop_bw_scale_track_lsb 0
129#define xd_p_reg_aagc_max_rf_agc_7_0 0xA006
130#define reg_aagc_max_rf_agc_7_0_pos 0
131#define reg_aagc_max_rf_agc_7_0_len 8
132#define reg_aagc_max_rf_agc_7_0_lsb 0
133#define xd_p_reg_aagc_max_rf_agc_9_8 0xA007
134#define reg_aagc_max_rf_agc_9_8_pos 0
135#define reg_aagc_max_rf_agc_9_8_len 2
136#define reg_aagc_max_rf_agc_9_8_lsb 8
137#define xd_p_reg_aagc_min_rf_agc_7_0 0xA008
138#define reg_aagc_min_rf_agc_7_0_pos 0
139#define reg_aagc_min_rf_agc_7_0_len 8
140#define reg_aagc_min_rf_agc_7_0_lsb 0
141#define xd_p_reg_aagc_min_rf_agc_9_8 0xA009
142#define reg_aagc_min_rf_agc_9_8_pos 0
143#define reg_aagc_min_rf_agc_9_8_len 2
144#define reg_aagc_min_rf_agc_9_8_lsb 8
145#define xd_p_reg_aagc_max_if_agc_7_0 0xA00A
146#define reg_aagc_max_if_agc_7_0_pos 0
147#define reg_aagc_max_if_agc_7_0_len 8
148#define reg_aagc_max_if_agc_7_0_lsb 0
149#define xd_p_reg_aagc_max_if_agc_9_8 0xA00B
150#define reg_aagc_max_if_agc_9_8_pos 0
151#define reg_aagc_max_if_agc_9_8_len 2
152#define reg_aagc_max_if_agc_9_8_lsb 8
153#define xd_p_reg_aagc_min_if_agc_7_0 0xA00C
154#define reg_aagc_min_if_agc_7_0_pos 0
155#define reg_aagc_min_if_agc_7_0_len 8
156#define reg_aagc_min_if_agc_7_0_lsb 0
157#define xd_p_reg_aagc_min_if_agc_9_8 0xA00D
158#define reg_aagc_min_if_agc_9_8_pos 0
159#define reg_aagc_min_if_agc_9_8_len 2
160#define reg_aagc_min_if_agc_9_8_lsb 8
161#define xd_p_reg_aagc_lock_sample_scale 0xA00E
162#define reg_aagc_lock_sample_scale_pos 0
163#define reg_aagc_lock_sample_scale_len 5
164#define reg_aagc_lock_sample_scale_lsb 0
165#define xd_p_reg_aagc_rf_agc_lock_scale_acquire 0xA00F
166#define reg_aagc_rf_agc_lock_scale_acquire_pos 0
167#define reg_aagc_rf_agc_lock_scale_acquire_len 3
168#define reg_aagc_rf_agc_lock_scale_acquire_lsb 0
169#define xd_p_reg_aagc_rf_agc_lock_scale_track 0xA00F
170#define reg_aagc_rf_agc_lock_scale_track_pos 3
171#define reg_aagc_rf_agc_lock_scale_track_len 3
172#define reg_aagc_rf_agc_lock_scale_track_lsb 0
173#define xd_p_reg_aagc_if_agc_lock_scale_acquire 0xA010
174#define reg_aagc_if_agc_lock_scale_acquire_pos 0
175#define reg_aagc_if_agc_lock_scale_acquire_len 3
176#define reg_aagc_if_agc_lock_scale_acquire_lsb 0
177#define xd_p_reg_aagc_if_agc_lock_scale_track 0xA010
178#define reg_aagc_if_agc_lock_scale_track_pos 3
179#define reg_aagc_if_agc_lock_scale_track_len 3
180#define reg_aagc_if_agc_lock_scale_track_lsb 0
181#define xd_p_reg_aagc_rf_top_numerator_7_0 0xA011
182#define reg_aagc_rf_top_numerator_7_0_pos 0
183#define reg_aagc_rf_top_numerator_7_0_len 8
184#define reg_aagc_rf_top_numerator_7_0_lsb 0
185#define xd_p_reg_aagc_rf_top_numerator_9_8 0xA012
186#define reg_aagc_rf_top_numerator_9_8_pos 0
187#define reg_aagc_rf_top_numerator_9_8_len 2
188#define reg_aagc_rf_top_numerator_9_8_lsb 8
189#define xd_p_reg_aagc_if_top_numerator_7_0 0xA013
190#define reg_aagc_if_top_numerator_7_0_pos 0
191#define reg_aagc_if_top_numerator_7_0_len 8
192#define reg_aagc_if_top_numerator_7_0_lsb 0
193#define xd_p_reg_aagc_if_top_numerator_9_8 0xA014
194#define reg_aagc_if_top_numerator_9_8_pos 0
195#define reg_aagc_if_top_numerator_9_8_len 2
196#define reg_aagc_if_top_numerator_9_8_lsb 8
197#define xd_p_reg_aagc_adc_out_desired_7_0 0xA015
198#define reg_aagc_adc_out_desired_7_0_pos 0
199#define reg_aagc_adc_out_desired_7_0_len 8
200#define reg_aagc_adc_out_desired_7_0_lsb 0
201#define xd_p_reg_aagc_adc_out_desired_8 0xA016
202#define reg_aagc_adc_out_desired_8_pos 0
203#define reg_aagc_adc_out_desired_8_len 1
204#define reg_aagc_adc_out_desired_8_lsb 0
205#define xd_p_reg_aagc_fixed_gain 0xA016
206#define reg_aagc_fixed_gain_pos 3
207#define reg_aagc_fixed_gain_len 1
208#define reg_aagc_fixed_gain_lsb 0
209#define xd_p_reg_aagc_lock_count_th 0xA016
210#define reg_aagc_lock_count_th_pos 4
211#define reg_aagc_lock_count_th_len 4
212#define reg_aagc_lock_count_th_lsb 0
213#define xd_p_reg_aagc_fixed_rf_agc_control_7_0 0xA017
214#define reg_aagc_fixed_rf_agc_control_7_0_pos 0
215#define reg_aagc_fixed_rf_agc_control_7_0_len 8
216#define reg_aagc_fixed_rf_agc_control_7_0_lsb 0
217#define xd_p_reg_aagc_fixed_rf_agc_control_15_8 0xA018
218#define reg_aagc_fixed_rf_agc_control_15_8_pos 0
219#define reg_aagc_fixed_rf_agc_control_15_8_len 8
220#define reg_aagc_fixed_rf_agc_control_15_8_lsb 8
221#define xd_p_reg_aagc_fixed_rf_agc_control_23_16 0xA019
222#define reg_aagc_fixed_rf_agc_control_23_16_pos 0
223#define reg_aagc_fixed_rf_agc_control_23_16_len 8
224#define reg_aagc_fixed_rf_agc_control_23_16_lsb 16
225#define xd_p_reg_aagc_fixed_rf_agc_control_30_24 0xA01A
226#define reg_aagc_fixed_rf_agc_control_30_24_pos 0
227#define reg_aagc_fixed_rf_agc_control_30_24_len 7
228#define reg_aagc_fixed_rf_agc_control_30_24_lsb 24
229#define xd_p_reg_aagc_fixed_if_agc_control_7_0 0xA01B
230#define reg_aagc_fixed_if_agc_control_7_0_pos 0
231#define reg_aagc_fixed_if_agc_control_7_0_len 8
232#define reg_aagc_fixed_if_agc_control_7_0_lsb 0
233#define xd_p_reg_aagc_fixed_if_agc_control_15_8 0xA01C
234#define reg_aagc_fixed_if_agc_control_15_8_pos 0
235#define reg_aagc_fixed_if_agc_control_15_8_len 8
236#define reg_aagc_fixed_if_agc_control_15_8_lsb 8
237#define xd_p_reg_aagc_fixed_if_agc_control_23_16 0xA01D
238#define reg_aagc_fixed_if_agc_control_23_16_pos 0
239#define reg_aagc_fixed_if_agc_control_23_16_len 8
240#define reg_aagc_fixed_if_agc_control_23_16_lsb 16
241#define xd_p_reg_aagc_fixed_if_agc_control_30_24 0xA01E
242#define reg_aagc_fixed_if_agc_control_30_24_pos 0
243#define reg_aagc_fixed_if_agc_control_30_24_len 7
244#define reg_aagc_fixed_if_agc_control_30_24_lsb 24
245#define xd_p_reg_aagc_rf_agc_unlock_numerator 0xA01F
246#define reg_aagc_rf_agc_unlock_numerator_pos 0
247#define reg_aagc_rf_agc_unlock_numerator_len 6
248#define reg_aagc_rf_agc_unlock_numerator_lsb 0
249#define xd_p_reg_aagc_if_agc_unlock_numerator 0xA020
250#define reg_aagc_if_agc_unlock_numerator_pos 0
251#define reg_aagc_if_agc_unlock_numerator_len 6
252#define reg_aagc_if_agc_unlock_numerator_lsb 0
253#define xd_p_reg_unplug_th 0xA021
254#define reg_unplug_th_pos 0
255#define reg_unplug_th_len 8
256#define reg_aagc_rf_x0_lsb 0
257#define xd_p_reg_weak_signal_rfagc_thr 0xA022
258#define reg_weak_signal_rfagc_thr_pos 0
259#define reg_weak_signal_rfagc_thr_len 8
260#define reg_weak_signal_rfagc_thr_lsb 0
261#define xd_p_reg_unplug_rf_gain_th 0xA023
262#define reg_unplug_rf_gain_th_pos 0
263#define reg_unplug_rf_gain_th_len 8
264#define reg_unplug_rf_gain_th_lsb 0
265#define xd_p_reg_unplug_dtop_rf_gain_th 0xA024
266#define reg_unplug_dtop_rf_gain_th_pos 0
267#define reg_unplug_dtop_rf_gain_th_len 8
268#define reg_unplug_dtop_rf_gain_th_lsb 0
269#define xd_p_reg_unplug_dtop_if_gain_th 0xA025
270#define reg_unplug_dtop_if_gain_th_pos 0
271#define reg_unplug_dtop_if_gain_th_len 8
272#define reg_unplug_dtop_if_gain_th_lsb 0
273#define xd_p_reg_top_recover_at_unplug_en 0xA026
274#define reg_top_recover_at_unplug_en_pos 0
275#define reg_top_recover_at_unplug_en_len 1
276#define reg_top_recover_at_unplug_en_lsb 0
277#define xd_p_reg_aagc_rf_x6 0xA027
278#define reg_aagc_rf_x6_pos 0
279#define reg_aagc_rf_x6_len 8
280#define reg_aagc_rf_x6_lsb 0
281#define xd_p_reg_aagc_rf_x7 0xA028
282#define reg_aagc_rf_x7_pos 0
283#define reg_aagc_rf_x7_len 8
284#define reg_aagc_rf_x7_lsb 0
285#define xd_p_reg_aagc_rf_x8 0xA029
286#define reg_aagc_rf_x8_pos 0
287#define reg_aagc_rf_x8_len 8
288#define reg_aagc_rf_x8_lsb 0
289#define xd_p_reg_aagc_rf_x9 0xA02A
290#define reg_aagc_rf_x9_pos 0
291#define reg_aagc_rf_x9_len 8
292#define reg_aagc_rf_x9_lsb 0
293#define xd_p_reg_aagc_rf_x10 0xA02B
294#define reg_aagc_rf_x10_pos 0
295#define reg_aagc_rf_x10_len 8
296#define reg_aagc_rf_x10_lsb 0
297#define xd_p_reg_aagc_rf_x11 0xA02C
298#define reg_aagc_rf_x11_pos 0
299#define reg_aagc_rf_x11_len 8
300#define reg_aagc_rf_x11_lsb 0
301#define xd_p_reg_aagc_rf_x12 0xA02D
302#define reg_aagc_rf_x12_pos 0
303#define reg_aagc_rf_x12_len 8
304#define reg_aagc_rf_x12_lsb 0
305#define xd_p_reg_aagc_rf_x13 0xA02E
306#define reg_aagc_rf_x13_pos 0
307#define reg_aagc_rf_x13_len 8
308#define reg_aagc_rf_x13_lsb 0
309#define xd_p_reg_aagc_if_x0 0xA02F
310#define reg_aagc_if_x0_pos 0
311#define reg_aagc_if_x0_len 8
312#define reg_aagc_if_x0_lsb 0
313#define xd_p_reg_aagc_if_x1 0xA030
314#define reg_aagc_if_x1_pos 0
315#define reg_aagc_if_x1_len 8
316#define reg_aagc_if_x1_lsb 0
317#define xd_p_reg_aagc_if_x2 0xA031
318#define reg_aagc_if_x2_pos 0
319#define reg_aagc_if_x2_len 8
320#define reg_aagc_if_x2_lsb 0
321#define xd_p_reg_aagc_if_x3 0xA032
322#define reg_aagc_if_x3_pos 0
323#define reg_aagc_if_x3_len 8
324#define reg_aagc_if_x3_lsb 0
325#define xd_p_reg_aagc_if_x4 0xA033
326#define reg_aagc_if_x4_pos 0
327#define reg_aagc_if_x4_len 8
328#define reg_aagc_if_x4_lsb 0
329#define xd_p_reg_aagc_if_x5 0xA034
330#define reg_aagc_if_x5_pos 0
331#define reg_aagc_if_x5_len 8
332#define reg_aagc_if_x5_lsb 0
333#define xd_p_reg_aagc_if_x6 0xA035
334#define reg_aagc_if_x6_pos 0
335#define reg_aagc_if_x6_len 8
336#define reg_aagc_if_x6_lsb 0
337#define xd_p_reg_aagc_if_x7 0xA036
338#define reg_aagc_if_x7_pos 0
339#define reg_aagc_if_x7_len 8
340#define reg_aagc_if_x7_lsb 0
341#define xd_p_reg_aagc_if_x8 0xA037
342#define reg_aagc_if_x8_pos 0
343#define reg_aagc_if_x8_len 8
344#define reg_aagc_if_x8_lsb 0
345#define xd_p_reg_aagc_if_x9 0xA038
346#define reg_aagc_if_x9_pos 0
347#define reg_aagc_if_x9_len 8
348#define reg_aagc_if_x9_lsb 0
349#define xd_p_reg_aagc_if_x10 0xA039
350#define reg_aagc_if_x10_pos 0
351#define reg_aagc_if_x10_len 8
352#define reg_aagc_if_x10_lsb 0
353#define xd_p_reg_aagc_if_x11 0xA03A
354#define reg_aagc_if_x11_pos 0
355#define reg_aagc_if_x11_len 8
356#define reg_aagc_if_x11_lsb 0
357#define xd_p_reg_aagc_if_x12 0xA03B
358#define reg_aagc_if_x12_pos 0
359#define reg_aagc_if_x12_len 8
360#define reg_aagc_if_x12_lsb 0
361#define xd_p_reg_aagc_if_x13 0xA03C
362#define reg_aagc_if_x13_pos 0
363#define reg_aagc_if_x13_len 8
364#define reg_aagc_if_x13_lsb 0
365#define xd_p_reg_aagc_min_rf_ctl_8bit_for_dca 0xA03D
366#define reg_aagc_min_rf_ctl_8bit_for_dca_pos 0
367#define reg_aagc_min_rf_ctl_8bit_for_dca_len 8
368#define reg_aagc_min_rf_ctl_8bit_for_dca_lsb 0
369#define xd_p_reg_aagc_min_if_ctl_8bit_for_dca 0xA03E
370#define reg_aagc_min_if_ctl_8bit_for_dca_pos 0
371#define reg_aagc_min_if_ctl_8bit_for_dca_len 8
372#define reg_aagc_min_if_ctl_8bit_for_dca_lsb 0
373#define xd_r_reg_aagc_total_gain_7_0 0xA070
374#define reg_aagc_total_gain_7_0_pos 0
375#define reg_aagc_total_gain_7_0_len 8
376#define reg_aagc_total_gain_7_0_lsb 0
377#define xd_r_reg_aagc_total_gain_15_8 0xA071
378#define reg_aagc_total_gain_15_8_pos 0
379#define reg_aagc_total_gain_15_8_len 8
380#define reg_aagc_total_gain_15_8_lsb 8
381#define xd_p_reg_aagc_in_sat_cnt_7_0 0xA074
382#define reg_aagc_in_sat_cnt_7_0_pos 0
383#define reg_aagc_in_sat_cnt_7_0_len 8
384#define reg_aagc_in_sat_cnt_7_0_lsb 0
385#define xd_p_reg_aagc_in_sat_cnt_15_8 0xA075
386#define reg_aagc_in_sat_cnt_15_8_pos 0
387#define reg_aagc_in_sat_cnt_15_8_len 8
388#define reg_aagc_in_sat_cnt_15_8_lsb 8
389#define xd_p_reg_aagc_in_sat_cnt_23_16 0xA076
390#define reg_aagc_in_sat_cnt_23_16_pos 0
391#define reg_aagc_in_sat_cnt_23_16_len 8
392#define reg_aagc_in_sat_cnt_23_16_lsb 16
393#define xd_p_reg_aagc_in_sat_cnt_31_24 0xA077
394#define reg_aagc_in_sat_cnt_31_24_pos 0
395#define reg_aagc_in_sat_cnt_31_24_len 8
396#define reg_aagc_in_sat_cnt_31_24_lsb 24
397#define xd_r_reg_aagc_digital_rf_volt_7_0 0xA078
398#define reg_aagc_digital_rf_volt_7_0_pos 0
399#define reg_aagc_digital_rf_volt_7_0_len 8
400#define reg_aagc_digital_rf_volt_7_0_lsb 0
401#define xd_r_reg_aagc_digital_rf_volt_9_8 0xA079
402#define reg_aagc_digital_rf_volt_9_8_pos 0
403#define reg_aagc_digital_rf_volt_9_8_len 2
404#define reg_aagc_digital_rf_volt_9_8_lsb 8
405#define xd_r_reg_aagc_digital_if_volt_7_0 0xA07A
406#define reg_aagc_digital_if_volt_7_0_pos 0
407#define reg_aagc_digital_if_volt_7_0_len 8
408#define reg_aagc_digital_if_volt_7_0_lsb 0
409#define xd_r_reg_aagc_digital_if_volt_9_8 0xA07B
410#define reg_aagc_digital_if_volt_9_8_pos 0
411#define reg_aagc_digital_if_volt_9_8_len 2
412#define reg_aagc_digital_if_volt_9_8_lsb 8
413#define xd_r_reg_aagc_rf_gain 0xA07C
414#define reg_aagc_rf_gain_pos 0
415#define reg_aagc_rf_gain_len 8
416#define reg_aagc_rf_gain_lsb 0
417#define xd_r_reg_aagc_if_gain 0xA07D
418#define reg_aagc_if_gain_pos 0
419#define reg_aagc_if_gain_len 8
420#define reg_aagc_if_gain_lsb 0
421#define xd_p_tinr_imp_indicator 0xA080
422#define tinr_imp_indicator_pos 0
423#define tinr_imp_indicator_len 2
424#define tinr_imp_indicator_lsb 0
425#define xd_p_reg_tinr_fifo_size 0xA080
426#define reg_tinr_fifo_size_pos 2
427#define reg_tinr_fifo_size_len 5
428#define reg_tinr_fifo_size_lsb 0
429#define xd_p_reg_tinr_saturation_cnt_th 0xA081
430#define reg_tinr_saturation_cnt_th_pos 0
431#define reg_tinr_saturation_cnt_th_len 4
432#define reg_tinr_saturation_cnt_th_lsb 0
433#define xd_p_reg_tinr_saturation_th_3_0 0xA081
434#define reg_tinr_saturation_th_3_0_pos 4
435#define reg_tinr_saturation_th_3_0_len 4
436#define reg_tinr_saturation_th_3_0_lsb 0
437#define xd_p_reg_tinr_saturation_th_8_4 0xA082
438#define reg_tinr_saturation_th_8_4_pos 0
439#define reg_tinr_saturation_th_8_4_len 5
440#define reg_tinr_saturation_th_8_4_lsb 4
441#define xd_p_reg_tinr_imp_duration_th_2k_7_0 0xA083
442#define reg_tinr_imp_duration_th_2k_7_0_pos 0
443#define reg_tinr_imp_duration_th_2k_7_0_len 8
444#define reg_tinr_imp_duration_th_2k_7_0_lsb 0
445#define xd_p_reg_tinr_imp_duration_th_2k_8 0xA084
446#define reg_tinr_imp_duration_th_2k_8_pos 0
447#define reg_tinr_imp_duration_th_2k_8_len 1
448#define reg_tinr_imp_duration_th_2k_8_lsb 0
449#define xd_p_reg_tinr_imp_duration_th_8k_7_0 0xA085
450#define reg_tinr_imp_duration_th_8k_7_0_pos 0
451#define reg_tinr_imp_duration_th_8k_7_0_len 8
452#define reg_tinr_imp_duration_th_8k_7_0_lsb 0
453#define xd_p_reg_tinr_imp_duration_th_8k_10_8 0xA086
454#define reg_tinr_imp_duration_th_8k_10_8_pos 0
455#define reg_tinr_imp_duration_th_8k_10_8_len 3
456#define reg_tinr_imp_duration_th_8k_10_8_lsb 8
457#define xd_p_reg_tinr_freq_ratio_6m_7_0 0xA087
458#define reg_tinr_freq_ratio_6m_7_0_pos 0
459#define reg_tinr_freq_ratio_6m_7_0_len 8
460#define reg_tinr_freq_ratio_6m_7_0_lsb 0
461#define xd_p_reg_tinr_freq_ratio_6m_12_8 0xA088
462#define reg_tinr_freq_ratio_6m_12_8_pos 0
463#define reg_tinr_freq_ratio_6m_12_8_len 5
464#define reg_tinr_freq_ratio_6m_12_8_lsb 8
465#define xd_p_reg_tinr_freq_ratio_7m_7_0 0xA089
466#define reg_tinr_freq_ratio_7m_7_0_pos 0
467#define reg_tinr_freq_ratio_7m_7_0_len 8
468#define reg_tinr_freq_ratio_7m_7_0_lsb 0
469#define xd_p_reg_tinr_freq_ratio_7m_12_8 0xA08A
470#define reg_tinr_freq_ratio_7m_12_8_pos 0
471#define reg_tinr_freq_ratio_7m_12_8_len 5
472#define reg_tinr_freq_ratio_7m_12_8_lsb 8
473#define xd_p_reg_tinr_freq_ratio_8m_7_0 0xA08B
474#define reg_tinr_freq_ratio_8m_7_0_pos 0
475#define reg_tinr_freq_ratio_8m_7_0_len 8
476#define reg_tinr_freq_ratio_8m_7_0_lsb 0
477#define xd_p_reg_tinr_freq_ratio_8m_12_8 0xA08C
478#define reg_tinr_freq_ratio_8m_12_8_pos 0
479#define reg_tinr_freq_ratio_8m_12_8_len 5
480#define reg_tinr_freq_ratio_8m_12_8_lsb 8
481#define xd_p_reg_tinr_imp_duration_th_low_2k 0xA08D
482#define reg_tinr_imp_duration_th_low_2k_pos 0
483#define reg_tinr_imp_duration_th_low_2k_len 8
484#define reg_tinr_imp_duration_th_low_2k_lsb 0
485#define xd_p_reg_tinr_imp_duration_th_low_8k 0xA08E
486#define reg_tinr_imp_duration_th_low_8k_pos 0
487#define reg_tinr_imp_duration_th_low_8k_len 8
488#define reg_tinr_imp_duration_th_low_8k_lsb 0
489#define xd_r_reg_tinr_counter_7_0 0xA090
490#define reg_tinr_counter_7_0_pos 0
491#define reg_tinr_counter_7_0_len 8
492#define reg_tinr_counter_7_0_lsb 0
493#define xd_r_reg_tinr_counter_15_8 0xA091
494#define reg_tinr_counter_15_8_pos 0
495#define reg_tinr_counter_15_8_len 8
496#define reg_tinr_counter_15_8_lsb 8
497#define xd_p_reg_tinr_adative_tinr_en 0xA093
498#define reg_tinr_adative_tinr_en_pos 0
499#define reg_tinr_adative_tinr_en_len 1
500#define reg_tinr_adative_tinr_en_lsb 0
501#define xd_p_reg_tinr_peak_fifo_size 0xA093
502#define reg_tinr_peak_fifo_size_pos 1
503#define reg_tinr_peak_fifo_size_len 5
504#define reg_tinr_peak_fifo_size_lsb 0
505#define xd_p_reg_tinr_counter_rst 0xA093
506#define reg_tinr_counter_rst_pos 6
507#define reg_tinr_counter_rst_len 1
508#define reg_tinr_counter_rst_lsb 0
509#define xd_p_reg_tinr_search_period_7_0 0xA094
510#define reg_tinr_search_period_7_0_pos 0
511#define reg_tinr_search_period_7_0_len 8
512#define reg_tinr_search_period_7_0_lsb 0
513#define xd_p_reg_tinr_search_period_15_8 0xA095
514#define reg_tinr_search_period_15_8_pos 0
515#define reg_tinr_search_period_15_8_len 8
516#define reg_tinr_search_period_15_8_lsb 8
517#define xd_p_reg_ccifs_fcw_7_0 0xA0A0
518#define reg_ccifs_fcw_7_0_pos 0
519#define reg_ccifs_fcw_7_0_len 8
520#define reg_ccifs_fcw_7_0_lsb 0
521#define xd_p_reg_ccifs_fcw_12_8 0xA0A1
522#define reg_ccifs_fcw_12_8_pos 0
523#define reg_ccifs_fcw_12_8_len 5
524#define reg_ccifs_fcw_12_8_lsb 8
525#define xd_p_reg_ccifs_spec_inv 0xA0A1
526#define reg_ccifs_spec_inv_pos 5
527#define reg_ccifs_spec_inv_len 1
528#define reg_ccifs_spec_inv_lsb 0
529#define xd_p_reg_gp_trigger 0xA0A2
530#define reg_gp_trigger_pos 0
531#define reg_gp_trigger_len 1
532#define reg_gp_trigger_lsb 0
533#define xd_p_reg_trigger_sel 0xA0A2
534#define reg_trigger_sel_pos 1
535#define reg_trigger_sel_len 2
536#define reg_trigger_sel_lsb 0
537#define xd_p_reg_debug_ofdm 0xA0A2
538#define reg_debug_ofdm_pos 3
539#define reg_debug_ofdm_len 2
540#define reg_debug_ofdm_lsb 0
541#define xd_p_reg_trigger_module_sel 0xA0A3
542#define reg_trigger_module_sel_pos 0
543#define reg_trigger_module_sel_len 6
544#define reg_trigger_module_sel_lsb 0
545#define xd_p_reg_trigger_set_sel 0xA0A4
546#define reg_trigger_set_sel_pos 0
547#define reg_trigger_set_sel_len 6
548#define reg_trigger_set_sel_lsb 0
549#define xd_p_reg_fw_int_mask_n 0xA0A4
550#define reg_fw_int_mask_n_pos 6
551#define reg_fw_int_mask_n_len 1
552#define reg_fw_int_mask_n_lsb 0
553#define xd_p_reg_debug_group 0xA0A5
554#define reg_debug_group_pos 0
555#define reg_debug_group_len 4
556#define reg_debug_group_lsb 0
557#define xd_p_reg_odbg_clk_sel 0xA0A5
558#define reg_odbg_clk_sel_pos 4
559#define reg_odbg_clk_sel_len 2
560#define reg_odbg_clk_sel_lsb 0
561#define xd_p_reg_ccif_sc 0xA0C0
562#define reg_ccif_sc_pos 0
563#define reg_ccif_sc_len 4
564#define reg_ccif_sc_lsb 0
565#define xd_r_reg_ccif_saturate 0xA0C1
566#define reg_ccif_saturate_pos 0
567#define reg_ccif_saturate_len 2
568#define reg_ccif_saturate_lsb 0
569#define xd_r_reg_antif_saturate 0xA0C1
570#define reg_antif_saturate_pos 2
571#define reg_antif_saturate_len 4
572#define reg_antif_saturate_lsb 0
573#define xd_r_reg_acif_saturate 0xA0C2
574#define reg_acif_saturate_pos 0
575#define reg_acif_saturate_len 8
576#define reg_acif_saturate_lsb 0
577#define xd_p_reg_tmr_timer0_threshold_7_0 0xA0C8
578#define reg_tmr_timer0_threshold_7_0_pos 0
579#define reg_tmr_timer0_threshold_7_0_len 8
580#define reg_tmr_timer0_threshold_7_0_lsb 0
581#define xd_p_reg_tmr_timer0_threshold_15_8 0xA0C9
582#define reg_tmr_timer0_threshold_15_8_pos 0
583#define reg_tmr_timer0_threshold_15_8_len 8
584#define reg_tmr_timer0_threshold_15_8_lsb 8
585#define xd_p_reg_tmr_timer0_enable 0xA0CA
586#define reg_tmr_timer0_enable_pos 0
587#define reg_tmr_timer0_enable_len 1
588#define reg_tmr_timer0_enable_lsb 0
589#define xd_p_reg_tmr_timer0_clk_sel 0xA0CA
590#define reg_tmr_timer0_clk_sel_pos 1
591#define reg_tmr_timer0_clk_sel_len 1
592#define reg_tmr_timer0_clk_sel_lsb 0
593#define xd_p_reg_tmr_timer0_int 0xA0CA
594#define reg_tmr_timer0_int_pos 2
595#define reg_tmr_timer0_int_len 1
596#define reg_tmr_timer0_int_lsb 0
597#define xd_p_reg_tmr_timer0_rst 0xA0CA
598#define reg_tmr_timer0_rst_pos 3
599#define reg_tmr_timer0_rst_len 1
600#define reg_tmr_timer0_rst_lsb 0
601#define xd_r_reg_tmr_timer0_count_7_0 0xA0CB
602#define reg_tmr_timer0_count_7_0_pos 0
603#define reg_tmr_timer0_count_7_0_len 8
604#define reg_tmr_timer0_count_7_0_lsb 0
605#define xd_r_reg_tmr_timer0_count_15_8 0xA0CC
606#define reg_tmr_timer0_count_15_8_pos 0
607#define reg_tmr_timer0_count_15_8_len 8
608#define reg_tmr_timer0_count_15_8_lsb 8
609#define xd_p_reg_suspend 0xA0CD
610#define reg_suspend_pos 0
611#define reg_suspend_len 1
612#define reg_suspend_lsb 0
613#define xd_p_reg_suspend_rdy 0xA0CD
614#define reg_suspend_rdy_pos 1
615#define reg_suspend_rdy_len 1
616#define reg_suspend_rdy_lsb 0
617#define xd_p_reg_resume 0xA0CD
618#define reg_resume_pos 2
619#define reg_resume_len 1
620#define reg_resume_lsb 0
621#define xd_p_reg_resume_rdy 0xA0CD
622#define reg_resume_rdy_pos 3
623#define reg_resume_rdy_len 1
624#define reg_resume_rdy_lsb 0
625#define xd_p_reg_fmf 0xA0CE
626#define reg_fmf_pos 0
627#define reg_fmf_len 8
628#define reg_fmf_lsb 0
629#define xd_p_ccid_accumulate_num_2k_7_0 0xA100
630#define ccid_accumulate_num_2k_7_0_pos 0
631#define ccid_accumulate_num_2k_7_0_len 8
632#define ccid_accumulate_num_2k_7_0_lsb 0
633#define xd_p_ccid_accumulate_num_2k_12_8 0xA101
634#define ccid_accumulate_num_2k_12_8_pos 0
635#define ccid_accumulate_num_2k_12_8_len 5
636#define ccid_accumulate_num_2k_12_8_lsb 8
637#define xd_p_ccid_accumulate_num_8k_7_0 0xA102
638#define ccid_accumulate_num_8k_7_0_pos 0
639#define ccid_accumulate_num_8k_7_0_len 8
640#define ccid_accumulate_num_8k_7_0_lsb 0
641#define xd_p_ccid_accumulate_num_8k_14_8 0xA103
642#define ccid_accumulate_num_8k_14_8_pos 0
643#define ccid_accumulate_num_8k_14_8_len 7
644#define ccid_accumulate_num_8k_14_8_lsb 8
645#define xd_p_ccid_desired_level_0 0xA103
646#define ccid_desired_level_0_pos 7
647#define ccid_desired_level_0_len 1
648#define ccid_desired_level_0_lsb 0
649#define xd_p_ccid_desired_level_8_1 0xA104
650#define ccid_desired_level_8_1_pos 0
651#define ccid_desired_level_8_1_len 8
652#define ccid_desired_level_8_1_lsb 1
653#define xd_p_ccid_apply_delay 0xA105
654#define ccid_apply_delay_pos 0
655#define ccid_apply_delay_len 7
656#define ccid_apply_delay_lsb 0
657#define xd_p_ccid_CCID_Threshold1 0xA106
658#define ccid_CCID_Threshold1_pos 0
659#define ccid_CCID_Threshold1_len 8
660#define ccid_CCID_Threshold1_lsb 0
661#define xd_p_ccid_CCID_Threshold2 0xA107
662#define ccid_CCID_Threshold2_pos 0
663#define ccid_CCID_Threshold2_len 8
664#define ccid_CCID_Threshold2_lsb 0
665#define xd_p_reg_ccid_gain_scale 0xA108
666#define reg_ccid_gain_scale_pos 0
667#define reg_ccid_gain_scale_len 4
668#define reg_ccid_gain_scale_lsb 0
669#define xd_p_reg_ccid2_passband_gain_set 0xA108
670#define reg_ccid2_passband_gain_set_pos 4
671#define reg_ccid2_passband_gain_set_len 4
672#define reg_ccid2_passband_gain_set_lsb 0
673#define xd_r_ccid_multiplier_7_0 0xA109
674#define ccid_multiplier_7_0_pos 0
675#define ccid_multiplier_7_0_len 8
676#define ccid_multiplier_7_0_lsb 0
677#define xd_r_ccid_multiplier_15_8 0xA10A
678#define ccid_multiplier_15_8_pos 0
679#define ccid_multiplier_15_8_len 8
680#define ccid_multiplier_15_8_lsb 8
681#define xd_r_ccid_right_shift_bits 0xA10B
682#define ccid_right_shift_bits_pos 0
683#define ccid_right_shift_bits_len 4
684#define ccid_right_shift_bits_lsb 0
685#define xd_r_reg_ccid_sx_7_0 0xA10C
686#define reg_ccid_sx_7_0_pos 0
687#define reg_ccid_sx_7_0_len 8
688#define reg_ccid_sx_7_0_lsb 0
689#define xd_r_reg_ccid_sx_15_8 0xA10D
690#define reg_ccid_sx_15_8_pos 0
691#define reg_ccid_sx_15_8_len 8
692#define reg_ccid_sx_15_8_lsb 8
693#define xd_r_reg_ccid_sx_21_16 0xA10E
694#define reg_ccid_sx_21_16_pos 0
695#define reg_ccid_sx_21_16_len 6
696#define reg_ccid_sx_21_16_lsb 16
697#define xd_r_reg_ccid_sy_7_0 0xA110
698#define reg_ccid_sy_7_0_pos 0
699#define reg_ccid_sy_7_0_len 8
700#define reg_ccid_sy_7_0_lsb 0
701#define xd_r_reg_ccid_sy_15_8 0xA111
702#define reg_ccid_sy_15_8_pos 0
703#define reg_ccid_sy_15_8_len 8
704#define reg_ccid_sy_15_8_lsb 8
705#define xd_r_reg_ccid_sy_23_16 0xA112
706#define reg_ccid_sy_23_16_pos 0
707#define reg_ccid_sy_23_16_len 8
708#define reg_ccid_sy_23_16_lsb 16
709#define xd_r_reg_ccid2_sz_7_0 0xA114
710#define reg_ccid2_sz_7_0_pos 0
711#define reg_ccid2_sz_7_0_len 8
712#define reg_ccid2_sz_7_0_lsb 0
713#define xd_r_reg_ccid2_sz_15_8 0xA115
714#define reg_ccid2_sz_15_8_pos 0
715#define reg_ccid2_sz_15_8_len 8
716#define reg_ccid2_sz_15_8_lsb 8
717#define xd_r_reg_ccid2_sz_23_16 0xA116
718#define reg_ccid2_sz_23_16_pos 0
719#define reg_ccid2_sz_23_16_len 8
720#define reg_ccid2_sz_23_16_lsb 16
721#define xd_r_reg_ccid2_sz_25_24 0xA117
722#define reg_ccid2_sz_25_24_pos 0
723#define reg_ccid2_sz_25_24_len 2
724#define reg_ccid2_sz_25_24_lsb 24
725#define xd_r_reg_ccid2_sy_7_0 0xA118
726#define reg_ccid2_sy_7_0_pos 0
727#define reg_ccid2_sy_7_0_len 8
728#define reg_ccid2_sy_7_0_lsb 0
729#define xd_r_reg_ccid2_sy_15_8 0xA119
730#define reg_ccid2_sy_15_8_pos 0
731#define reg_ccid2_sy_15_8_len 8
732#define reg_ccid2_sy_15_8_lsb 8
733#define xd_r_reg_ccid2_sy_23_16 0xA11A
734#define reg_ccid2_sy_23_16_pos 0
735#define reg_ccid2_sy_23_16_len 8
736#define reg_ccid2_sy_23_16_lsb 16
737#define xd_r_reg_ccid2_sy_25_24 0xA11B
738#define reg_ccid2_sy_25_24_pos 0
739#define reg_ccid2_sy_25_24_len 2
740#define reg_ccid2_sy_25_24_lsb 24
741#define xd_p_dagc1_accumulate_num_2k_7_0 0xA120
742#define dagc1_accumulate_num_2k_7_0_pos 0
743#define dagc1_accumulate_num_2k_7_0_len 8
744#define dagc1_accumulate_num_2k_7_0_lsb 0
745#define xd_p_dagc1_accumulate_num_2k_12_8 0xA121
746#define dagc1_accumulate_num_2k_12_8_pos 0
747#define dagc1_accumulate_num_2k_12_8_len 5
748#define dagc1_accumulate_num_2k_12_8_lsb 8
749#define xd_p_dagc1_accumulate_num_8k_7_0 0xA122
750#define dagc1_accumulate_num_8k_7_0_pos 0
751#define dagc1_accumulate_num_8k_7_0_len 8
752#define dagc1_accumulate_num_8k_7_0_lsb 0
753#define xd_p_dagc1_accumulate_num_8k_14_8 0xA123
754#define dagc1_accumulate_num_8k_14_8_pos 0
755#define dagc1_accumulate_num_8k_14_8_len 7
756#define dagc1_accumulate_num_8k_14_8_lsb 8
757#define xd_p_dagc1_desired_level_0 0xA123
758#define dagc1_desired_level_0_pos 7
759#define dagc1_desired_level_0_len 1
760#define dagc1_desired_level_0_lsb 0
761#define xd_p_dagc1_desired_level_8_1 0xA124
762#define dagc1_desired_level_8_1_pos 0
763#define dagc1_desired_level_8_1_len 8
764#define dagc1_desired_level_8_1_lsb 1
765#define xd_p_dagc1_apply_delay 0xA125
766#define dagc1_apply_delay_pos 0
767#define dagc1_apply_delay_len 7
768#define dagc1_apply_delay_lsb 0
769#define xd_p_dagc1_bypass_scale_ctl 0xA126
770#define dagc1_bypass_scale_ctl_pos 0
771#define dagc1_bypass_scale_ctl_len 2
772#define dagc1_bypass_scale_ctl_lsb 0
773#define xd_p_reg_dagc1_in_sat_cnt_7_0 0xA127
774#define reg_dagc1_in_sat_cnt_7_0_pos 0
775#define reg_dagc1_in_sat_cnt_7_0_len 8
776#define reg_dagc1_in_sat_cnt_7_0_lsb 0
777#define xd_p_reg_dagc1_in_sat_cnt_15_8 0xA128
778#define reg_dagc1_in_sat_cnt_15_8_pos 0
779#define reg_dagc1_in_sat_cnt_15_8_len 8
780#define reg_dagc1_in_sat_cnt_15_8_lsb 8
781#define xd_p_reg_dagc1_in_sat_cnt_23_16 0xA129
782#define reg_dagc1_in_sat_cnt_23_16_pos 0
783#define reg_dagc1_in_sat_cnt_23_16_len 8
784#define reg_dagc1_in_sat_cnt_23_16_lsb 16
785#define xd_p_reg_dagc1_in_sat_cnt_31_24 0xA12A
786#define reg_dagc1_in_sat_cnt_31_24_pos 0
787#define reg_dagc1_in_sat_cnt_31_24_len 8
788#define reg_dagc1_in_sat_cnt_31_24_lsb 24
789#define xd_p_reg_dagc1_out_sat_cnt_7_0 0xA12B
790#define reg_dagc1_out_sat_cnt_7_0_pos 0
791#define reg_dagc1_out_sat_cnt_7_0_len 8
792#define reg_dagc1_out_sat_cnt_7_0_lsb 0
793#define xd_p_reg_dagc1_out_sat_cnt_15_8 0xA12C
794#define reg_dagc1_out_sat_cnt_15_8_pos 0
795#define reg_dagc1_out_sat_cnt_15_8_len 8
796#define reg_dagc1_out_sat_cnt_15_8_lsb 8
797#define xd_p_reg_dagc1_out_sat_cnt_23_16 0xA12D
798#define reg_dagc1_out_sat_cnt_23_16_pos 0
799#define reg_dagc1_out_sat_cnt_23_16_len 8
800#define reg_dagc1_out_sat_cnt_23_16_lsb 16
801#define xd_p_reg_dagc1_out_sat_cnt_31_24 0xA12E
802#define reg_dagc1_out_sat_cnt_31_24_pos 0
803#define reg_dagc1_out_sat_cnt_31_24_len 8
804#define reg_dagc1_out_sat_cnt_31_24_lsb 24
805#define xd_r_dagc1_multiplier_7_0 0xA136
806#define dagc1_multiplier_7_0_pos 0
807#define dagc1_multiplier_7_0_len 8
808#define dagc1_multiplier_7_0_lsb 0
809#define xd_r_dagc1_multiplier_15_8 0xA137
810#define dagc1_multiplier_15_8_pos 0
811#define dagc1_multiplier_15_8_len 8
812#define dagc1_multiplier_15_8_lsb 8
813#define xd_r_dagc1_right_shift_bits 0xA138
814#define dagc1_right_shift_bits_pos 0
815#define dagc1_right_shift_bits_len 4
816#define dagc1_right_shift_bits_lsb 0
817#define xd_p_reg_bfs_fcw_7_0 0xA140
818#define reg_bfs_fcw_7_0_pos 0
819#define reg_bfs_fcw_7_0_len 8
820#define reg_bfs_fcw_7_0_lsb 0
821#define xd_p_reg_bfs_fcw_15_8 0xA141
822#define reg_bfs_fcw_15_8_pos 0
823#define reg_bfs_fcw_15_8_len 8
824#define reg_bfs_fcw_15_8_lsb 8
825#define xd_p_reg_bfs_fcw_22_16 0xA142
826#define reg_bfs_fcw_22_16_pos 0
827#define reg_bfs_fcw_22_16_len 7
828#define reg_bfs_fcw_22_16_lsb 16
829#define xd_p_reg_antif_sf_7_0 0xA144
830#define reg_antif_sf_7_0_pos 0
831#define reg_antif_sf_7_0_len 8
832#define reg_antif_sf_7_0_lsb 0
833#define xd_p_reg_antif_sf_11_8 0xA145
834#define reg_antif_sf_11_8_pos 0
835#define reg_antif_sf_11_8_len 4
836#define reg_antif_sf_11_8_lsb 8
837#define xd_r_bfs_fcw_q_7_0 0xA150
838#define bfs_fcw_q_7_0_pos 0
839#define bfs_fcw_q_7_0_len 8
840#define bfs_fcw_q_7_0_lsb 0
841#define xd_r_bfs_fcw_q_15_8 0xA151
842#define bfs_fcw_q_15_8_pos 0
843#define bfs_fcw_q_15_8_len 8
844#define bfs_fcw_q_15_8_lsb 8
845#define xd_r_bfs_fcw_q_22_16 0xA152
846#define bfs_fcw_q_22_16_pos 0
847#define bfs_fcw_q_22_16_len 7
848#define bfs_fcw_q_22_16_lsb 16
849#define xd_p_reg_dca_enu 0xA160
850#define reg_dca_enu_pos 0
851#define reg_dca_enu_len 1
852#define reg_dca_enu_lsb 0
853#define xd_p_reg_dca_enl 0xA160
854#define reg_dca_enl_pos 1
855#define reg_dca_enl_len 1
856#define reg_dca_enl_lsb 0
857#define xd_p_reg_dca_lower_chip 0xA160
858#define reg_dca_lower_chip_pos 2
859#define reg_dca_lower_chip_len 1
860#define reg_dca_lower_chip_lsb 0
861#define xd_p_reg_dca_upper_chip 0xA160
862#define reg_dca_upper_chip_pos 3
863#define reg_dca_upper_chip_len 1
864#define reg_dca_upper_chip_lsb 0
865#define xd_p_reg_dca_platch 0xA160
866#define reg_dca_platch_pos 4
867#define reg_dca_platch_len 1
868#define reg_dca_platch_lsb 0
869#define xd_p_reg_dca_th 0xA161
870#define reg_dca_th_pos 0
871#define reg_dca_th_len 5
872#define reg_dca_th_lsb 0
873#define xd_p_reg_dca_scale 0xA162
874#define reg_dca_scale_pos 0
875#define reg_dca_scale_len 4
876#define reg_dca_scale_lsb 0
877#define xd_p_reg_dca_tone_7_0 0xA163
878#define reg_dca_tone_7_0_pos 0
879#define reg_dca_tone_7_0_len 8
880#define reg_dca_tone_7_0_lsb 0
881#define xd_p_reg_dca_tone_12_8 0xA164
882#define reg_dca_tone_12_8_pos 0
883#define reg_dca_tone_12_8_len 5
884#define reg_dca_tone_12_8_lsb 8
885#define xd_p_reg_dca_time_7_0 0xA165
886#define reg_dca_time_7_0_pos 0
887#define reg_dca_time_7_0_len 8
888#define reg_dca_time_7_0_lsb 0
889#define xd_p_reg_dca_time_15_8 0xA166
890#define reg_dca_time_15_8_pos 0
891#define reg_dca_time_15_8_len 8
892#define reg_dca_time_15_8_lsb 8
893#define xd_r_dcasm 0xA167
894#define dcasm_pos 0
895#define dcasm_len 3
896#define dcasm_lsb 0
897#define xd_p_reg_qnt_valuew_7_0 0xA168
898#define reg_qnt_valuew_7_0_pos 0
899#define reg_qnt_valuew_7_0_len 8
900#define reg_qnt_valuew_7_0_lsb 0
901#define xd_p_reg_qnt_valuew_10_8 0xA169
902#define reg_qnt_valuew_10_8_pos 0
903#define reg_qnt_valuew_10_8_len 3
904#define reg_qnt_valuew_10_8_lsb 8
905#define xd_p_dca_sbx_gain_diff_7_0 0xA16A
906#define dca_sbx_gain_diff_7_0_pos 0
907#define dca_sbx_gain_diff_7_0_len 8
908#define dca_sbx_gain_diff_7_0_lsb 0
909#define xd_p_dca_sbx_gain_diff_9_8 0xA16B
910#define dca_sbx_gain_diff_9_8_pos 0
911#define dca_sbx_gain_diff_9_8_len 2
912#define dca_sbx_gain_diff_9_8_lsb 8
913#define xd_p_reg_dca_stand_alone 0xA16C
914#define reg_dca_stand_alone_pos 0
915#define reg_dca_stand_alone_len 1
916#define reg_dca_stand_alone_lsb 0
917#define xd_p_reg_dca_upper_out_en 0xA16C
918#define reg_dca_upper_out_en_pos 1
919#define reg_dca_upper_out_en_len 1
920#define reg_dca_upper_out_en_lsb 0
921#define xd_p_reg_dca_rc_en 0xA16C
922#define reg_dca_rc_en_pos 2
923#define reg_dca_rc_en_len 1
924#define reg_dca_rc_en_lsb 0
925#define xd_p_reg_dca_retrain_send 0xA16C
926#define reg_dca_retrain_send_pos 3
927#define reg_dca_retrain_send_len 1
928#define reg_dca_retrain_send_lsb 0
929#define xd_p_reg_dca_retrain_rec 0xA16C
930#define reg_dca_retrain_rec_pos 4
931#define reg_dca_retrain_rec_len 1
932#define reg_dca_retrain_rec_lsb 0
933#define xd_p_reg_dca_api_tpsrdy 0xA16C
934#define reg_dca_api_tpsrdy_pos 5
935#define reg_dca_api_tpsrdy_len 1
936#define reg_dca_api_tpsrdy_lsb 0
937#define xd_p_reg_dca_symbol_gap 0xA16D
938#define reg_dca_symbol_gap_pos 0
939#define reg_dca_symbol_gap_len 4
940#define reg_dca_symbol_gap_lsb 0
941#define xd_p_reg_qnt_nfvaluew_7_0 0xA16E
942#define reg_qnt_nfvaluew_7_0_pos 0
943#define reg_qnt_nfvaluew_7_0_len 8
944#define reg_qnt_nfvaluew_7_0_lsb 0
945#define xd_p_reg_qnt_nfvaluew_10_8 0xA16F
946#define reg_qnt_nfvaluew_10_8_pos 0
947#define reg_qnt_nfvaluew_10_8_len 3
948#define reg_qnt_nfvaluew_10_8_lsb 8
949#define xd_p_reg_qnt_flatness_thr_7_0 0xA170
950#define reg_qnt_flatness_thr_7_0_pos 0
951#define reg_qnt_flatness_thr_7_0_len 8
952#define reg_qnt_flatness_thr_7_0_lsb 0
953#define xd_p_reg_qnt_flatness_thr_9_8 0xA171
954#define reg_qnt_flatness_thr_9_8_pos 0
955#define reg_qnt_flatness_thr_9_8_len 2
956#define reg_qnt_flatness_thr_9_8_lsb 8
957#define xd_p_reg_dca_tone_idx_5_0 0xA171
958#define reg_dca_tone_idx_5_0_pos 2
959#define reg_dca_tone_idx_5_0_len 6
960#define reg_dca_tone_idx_5_0_lsb 0
961#define xd_p_reg_dca_tone_idx_12_6 0xA172
962#define reg_dca_tone_idx_12_6_pos 0
963#define reg_dca_tone_idx_12_6_len 7
964#define reg_dca_tone_idx_12_6_lsb 6
965#define xd_p_reg_dca_data_vld 0xA173
966#define reg_dca_data_vld_pos 0
967#define reg_dca_data_vld_len 1
968#define reg_dca_data_vld_lsb 0
969#define xd_p_reg_dca_read_update 0xA173
970#define reg_dca_read_update_pos 1
971#define reg_dca_read_update_len 1
972#define reg_dca_read_update_lsb 0
973#define xd_r_reg_dca_data_re_5_0 0xA173
974#define reg_dca_data_re_5_0_pos 2
975#define reg_dca_data_re_5_0_len 6
976#define reg_dca_data_re_5_0_lsb 0
977#define xd_r_reg_dca_data_re_10_6 0xA174
978#define reg_dca_data_re_10_6_pos 0
979#define reg_dca_data_re_10_6_len 5
980#define reg_dca_data_re_10_6_lsb 6
981#define xd_r_reg_dca_data_im_7_0 0xA175
982#define reg_dca_data_im_7_0_pos 0
983#define reg_dca_data_im_7_0_len 8
984#define reg_dca_data_im_7_0_lsb 0
985#define xd_r_reg_dca_data_im_10_8 0xA176
986#define reg_dca_data_im_10_8_pos 0
987#define reg_dca_data_im_10_8_len 3
988#define reg_dca_data_im_10_8_lsb 8
989#define xd_r_reg_dca_data_h2_7_0 0xA178
990#define reg_dca_data_h2_7_0_pos 0
991#define reg_dca_data_h2_7_0_len 8
992#define reg_dca_data_h2_7_0_lsb 0
993#define xd_r_reg_dca_data_h2_9_8 0xA179
994#define reg_dca_data_h2_9_8_pos 0
995#define reg_dca_data_h2_9_8_len 2
996#define reg_dca_data_h2_9_8_lsb 8
997#define xd_p_reg_f_adc_7_0 0xA180
998#define reg_f_adc_7_0_pos 0
999#define reg_f_adc_7_0_len 8
1000#define reg_f_adc_7_0_lsb 0
1001#define xd_p_reg_f_adc_15_8 0xA181
1002#define reg_f_adc_15_8_pos 0
1003#define reg_f_adc_15_8_len 8
1004#define reg_f_adc_15_8_lsb 8
1005#define xd_p_reg_f_adc_23_16 0xA182
1006#define reg_f_adc_23_16_pos 0
1007#define reg_f_adc_23_16_len 8
1008#define reg_f_adc_23_16_lsb 16
1009#define xd_r_intp_mu_7_0 0xA190
1010#define intp_mu_7_0_pos 0
1011#define intp_mu_7_0_len 8
1012#define intp_mu_7_0_lsb 0
1013#define xd_r_intp_mu_15_8 0xA191
1014#define intp_mu_15_8_pos 0
1015#define intp_mu_15_8_len 8
1016#define intp_mu_15_8_lsb 8
1017#define xd_r_intp_mu_19_16 0xA192
1018#define intp_mu_19_16_pos 0
1019#define intp_mu_19_16_len 4
1020#define intp_mu_19_16_lsb 16
1021#define xd_p_reg_agc_rst 0xA1A0
1022#define reg_agc_rst_pos 0
1023#define reg_agc_rst_len 1
1024#define reg_agc_rst_lsb 0
1025#define xd_p_rf_agc_en 0xA1A0
1026#define rf_agc_en_pos 1
1027#define rf_agc_en_len 1
1028#define rf_agc_en_lsb 0
1029#define xd_p_rf_agc_dis 0xA1A0
1030#define rf_agc_dis_pos 2
1031#define rf_agc_dis_len 1
1032#define rf_agc_dis_lsb 0
1033#define xd_p_if_agc_rst 0xA1A0
1034#define if_agc_rst_pos 3
1035#define if_agc_rst_len 1
1036#define if_agc_rst_lsb 0
1037#define xd_p_if_agc_en 0xA1A0
1038#define if_agc_en_pos 4
1039#define if_agc_en_len 1
1040#define if_agc_en_lsb 0
1041#define xd_p_if_agc_dis 0xA1A0
1042#define if_agc_dis_pos 5
1043#define if_agc_dis_len 1
1044#define if_agc_dis_lsb 0
1045#define xd_p_agc_lock 0xA1A0
1046#define agc_lock_pos 6
1047#define agc_lock_len 1
1048#define agc_lock_lsb 0
1049#define xd_p_reg_tinr_rst 0xA1A1
1050#define reg_tinr_rst_pos 0
1051#define reg_tinr_rst_len 1
1052#define reg_tinr_rst_lsb 0
1053#define xd_p_reg_tinr_en 0xA1A1
1054#define reg_tinr_en_pos 1
1055#define reg_tinr_en_len 1
1056#define reg_tinr_en_lsb 0
1057#define xd_p_reg_ccifs_en 0xA1A2
1058#define reg_ccifs_en_pos 0
1059#define reg_ccifs_en_len 1
1060#define reg_ccifs_en_lsb 0
1061#define xd_p_reg_ccifs_dis 0xA1A2
1062#define reg_ccifs_dis_pos 1
1063#define reg_ccifs_dis_len 1
1064#define reg_ccifs_dis_lsb 0
1065#define xd_p_reg_ccifs_rst 0xA1A2
1066#define reg_ccifs_rst_pos 2
1067#define reg_ccifs_rst_len 1
1068#define reg_ccifs_rst_lsb 0
1069#define xd_p_reg_ccifs_byp 0xA1A2
1070#define reg_ccifs_byp_pos 3
1071#define reg_ccifs_byp_len 1
1072#define reg_ccifs_byp_lsb 0
1073#define xd_p_reg_ccif_en 0xA1A3
1074#define reg_ccif_en_pos 0
1075#define reg_ccif_en_len 1
1076#define reg_ccif_en_lsb 0
1077#define xd_p_reg_ccif_dis 0xA1A3
1078#define reg_ccif_dis_pos 1
1079#define reg_ccif_dis_len 1
1080#define reg_ccif_dis_lsb 0
1081#define xd_p_reg_ccif_rst 0xA1A3
1082#define reg_ccif_rst_pos 2
1083#define reg_ccif_rst_len 1
1084#define reg_ccif_rst_lsb 0
1085#define xd_p_reg_ccif_byp 0xA1A3
1086#define reg_ccif_byp_pos 3
1087#define reg_ccif_byp_len 1
1088#define reg_ccif_byp_lsb 0
1089#define xd_p_dagc1_rst 0xA1A4
1090#define dagc1_rst_pos 0
1091#define dagc1_rst_len 1
1092#define dagc1_rst_lsb 0
1093#define xd_p_dagc1_en 0xA1A4
1094#define dagc1_en_pos 1
1095#define dagc1_en_len 1
1096#define dagc1_en_lsb 0
1097#define xd_p_dagc1_mode 0xA1A4
1098#define dagc1_mode_pos 2
1099#define dagc1_mode_len 2
1100#define dagc1_mode_lsb 0
1101#define xd_p_dagc1_done 0xA1A4
1102#define dagc1_done_pos 4
1103#define dagc1_done_len 1
1104#define dagc1_done_lsb 0
1105#define xd_p_ccid_rst 0xA1A5
1106#define ccid_rst_pos 0
1107#define ccid_rst_len 1
1108#define ccid_rst_lsb 0
1109#define xd_p_ccid_en 0xA1A5
1110#define ccid_en_pos 1
1111#define ccid_en_len 1
1112#define ccid_en_lsb 0
1113#define xd_p_ccid_mode 0xA1A5
1114#define ccid_mode_pos 2
1115#define ccid_mode_len 2
1116#define ccid_mode_lsb 0
1117#define xd_p_ccid_done 0xA1A5
1118#define ccid_done_pos 4
1119#define ccid_done_len 1
1120#define ccid_done_lsb 0
1121#define xd_r_ccid_deted 0xA1A5
1122#define ccid_deted_pos 5
1123#define ccid_deted_len 1
1124#define ccid_deted_lsb 0
1125#define xd_p_ccid2_en 0xA1A5
1126#define ccid2_en_pos 6
1127#define ccid2_en_len 1
1128#define ccid2_en_lsb 0
1129#define xd_p_ccid2_done 0xA1A5
1130#define ccid2_done_pos 7
1131#define ccid2_done_len 1
1132#define ccid2_done_lsb 0
1133#define xd_p_reg_bfs_en 0xA1A6
1134#define reg_bfs_en_pos 0
1135#define reg_bfs_en_len 1
1136#define reg_bfs_en_lsb 0
1137#define xd_p_reg_bfs_dis 0xA1A6
1138#define reg_bfs_dis_pos 1
1139#define reg_bfs_dis_len 1
1140#define reg_bfs_dis_lsb 0
1141#define xd_p_reg_bfs_rst 0xA1A6
1142#define reg_bfs_rst_pos 2
1143#define reg_bfs_rst_len 1
1144#define reg_bfs_rst_lsb 0
1145#define xd_p_reg_bfs_byp 0xA1A6
1146#define reg_bfs_byp_pos 3
1147#define reg_bfs_byp_len 1
1148#define reg_bfs_byp_lsb 0
1149#define xd_p_reg_antif_en 0xA1A7
1150#define reg_antif_en_pos 0
1151#define reg_antif_en_len 1
1152#define reg_antif_en_lsb 0
1153#define xd_p_reg_antif_dis 0xA1A7
1154#define reg_antif_dis_pos 1
1155#define reg_antif_dis_len 1
1156#define reg_antif_dis_lsb 0
1157#define xd_p_reg_antif_rst 0xA1A7
1158#define reg_antif_rst_pos 2
1159#define reg_antif_rst_len 1
1160#define reg_antif_rst_lsb 0
1161#define xd_p_reg_antif_byp 0xA1A7
1162#define reg_antif_byp_pos 3
1163#define reg_antif_byp_len 1
1164#define reg_antif_byp_lsb 0
1165#define xd_p_intp_en 0xA1A8
1166#define intp_en_pos 0
1167#define intp_en_len 1
1168#define intp_en_lsb 0
1169#define xd_p_intp_dis 0xA1A8
1170#define intp_dis_pos 1
1171#define intp_dis_len 1
1172#define intp_dis_lsb 0
1173#define xd_p_intp_rst 0xA1A8
1174#define intp_rst_pos 2
1175#define intp_rst_len 1
1176#define intp_rst_lsb 0
1177#define xd_p_intp_byp 0xA1A8
1178#define intp_byp_pos 3
1179#define intp_byp_len 1
1180#define intp_byp_lsb 0
1181#define xd_p_reg_acif_en 0xA1A9
1182#define reg_acif_en_pos 0
1183#define reg_acif_en_len 1
1184#define reg_acif_en_lsb 0
1185#define xd_p_reg_acif_dis 0xA1A9
1186#define reg_acif_dis_pos 1
1187#define reg_acif_dis_len 1
1188#define reg_acif_dis_lsb 0
1189#define xd_p_reg_acif_rst 0xA1A9
1190#define reg_acif_rst_pos 2
1191#define reg_acif_rst_len 1
1192#define reg_acif_rst_lsb 0
1193#define xd_p_reg_acif_byp 0xA1A9
1194#define reg_acif_byp_pos 3
1195#define reg_acif_byp_len 1
1196#define reg_acif_byp_lsb 0
1197#define xd_p_reg_acif_sync_mode 0xA1A9
1198#define reg_acif_sync_mode_pos 4
1199#define reg_acif_sync_mode_len 1
1200#define reg_acif_sync_mode_lsb 0
1201#define xd_p_dagc2_rst 0xA1AA
1202#define dagc2_rst_pos 0
1203#define dagc2_rst_len 1
1204#define dagc2_rst_lsb 0
1205#define xd_p_dagc2_en 0xA1AA
1206#define dagc2_en_pos 1
1207#define dagc2_en_len 1
1208#define dagc2_en_lsb 0
1209#define xd_p_dagc2_mode 0xA1AA
1210#define dagc2_mode_pos 2
1211#define dagc2_mode_len 2
1212#define dagc2_mode_lsb 0
1213#define xd_p_dagc2_done 0xA1AA
1214#define dagc2_done_pos 4
1215#define dagc2_done_len 1
1216#define dagc2_done_lsb 0
1217#define xd_p_reg_dca_en 0xA1AB
1218#define reg_dca_en_pos 0
1219#define reg_dca_en_len 1
1220#define reg_dca_en_lsb 0
1221#define xd_p_dagc2_accumulate_num_2k_7_0 0xA1C0
1222#define dagc2_accumulate_num_2k_7_0_pos 0
1223#define dagc2_accumulate_num_2k_7_0_len 8
1224#define dagc2_accumulate_num_2k_7_0_lsb 0
1225#define xd_p_dagc2_accumulate_num_2k_12_8 0xA1C1
1226#define dagc2_accumulate_num_2k_12_8_pos 0
1227#define dagc2_accumulate_num_2k_12_8_len 5
1228#define dagc2_accumulate_num_2k_12_8_lsb 8
1229#define xd_p_dagc2_accumulate_num_8k_7_0 0xA1C2
1230#define dagc2_accumulate_num_8k_7_0_pos 0
1231#define dagc2_accumulate_num_8k_7_0_len 8
1232#define dagc2_accumulate_num_8k_7_0_lsb 0
1233#define xd_p_dagc2_accumulate_num_8k_12_8 0xA1C3
1234#define dagc2_accumulate_num_8k_12_8_pos 0
1235#define dagc2_accumulate_num_8k_12_8_len 5
1236#define dagc2_accumulate_num_8k_12_8_lsb 8
1237#define xd_p_dagc2_desired_level_2_0 0xA1C3
1238#define dagc2_desired_level_2_0_pos 5
1239#define dagc2_desired_level_2_0_len 3
1240#define dagc2_desired_level_2_0_lsb 0
1241#define xd_p_dagc2_desired_level_8_3 0xA1C4
1242#define dagc2_desired_level_8_3_pos 0
1243#define dagc2_desired_level_8_3_len 6
1244#define dagc2_desired_level_8_3_lsb 3
1245#define xd_p_dagc2_apply_delay 0xA1C5
1246#define dagc2_apply_delay_pos 0
1247#define dagc2_apply_delay_len 7
1248#define dagc2_apply_delay_lsb 0
1249#define xd_p_dagc2_bypass_scale_ctl 0xA1C6
1250#define dagc2_bypass_scale_ctl_pos 0
1251#define dagc2_bypass_scale_ctl_len 3
1252#define dagc2_bypass_scale_ctl_lsb 0
1253#define xd_p_dagc2_programmable_shift1 0xA1C7
1254#define dagc2_programmable_shift1_pos 0
1255#define dagc2_programmable_shift1_len 8
1256#define dagc2_programmable_shift1_lsb 0
1257#define xd_p_dagc2_programmable_shift2 0xA1C8
1258#define dagc2_programmable_shift2_pos 0
1259#define dagc2_programmable_shift2_len 8
1260#define dagc2_programmable_shift2_lsb 0
1261#define xd_p_reg_dagc2_in_sat_cnt_7_0 0xA1C9
1262#define reg_dagc2_in_sat_cnt_7_0_pos 0
1263#define reg_dagc2_in_sat_cnt_7_0_len 8
1264#define reg_dagc2_in_sat_cnt_7_0_lsb 0
1265#define xd_p_reg_dagc2_in_sat_cnt_15_8 0xA1CA
1266#define reg_dagc2_in_sat_cnt_15_8_pos 0
1267#define reg_dagc2_in_sat_cnt_15_8_len 8
1268#define reg_dagc2_in_sat_cnt_15_8_lsb 8
1269#define xd_p_reg_dagc2_in_sat_cnt_23_16 0xA1CB
1270#define reg_dagc2_in_sat_cnt_23_16_pos 0
1271#define reg_dagc2_in_sat_cnt_23_16_len 8
1272#define reg_dagc2_in_sat_cnt_23_16_lsb 16
1273#define xd_p_reg_dagc2_in_sat_cnt_31_24 0xA1CC
1274#define reg_dagc2_in_sat_cnt_31_24_pos 0
1275#define reg_dagc2_in_sat_cnt_31_24_len 8
1276#define reg_dagc2_in_sat_cnt_31_24_lsb 24
1277#define xd_p_reg_dagc2_out_sat_cnt_7_0 0xA1CD
1278#define reg_dagc2_out_sat_cnt_7_0_pos 0
1279#define reg_dagc2_out_sat_cnt_7_0_len 8
1280#define reg_dagc2_out_sat_cnt_7_0_lsb 0
1281#define xd_p_reg_dagc2_out_sat_cnt_15_8 0xA1CE
1282#define reg_dagc2_out_sat_cnt_15_8_pos 0
1283#define reg_dagc2_out_sat_cnt_15_8_len 8
1284#define reg_dagc2_out_sat_cnt_15_8_lsb 8
1285#define xd_p_reg_dagc2_out_sat_cnt_23_16 0xA1CF
1286#define reg_dagc2_out_sat_cnt_23_16_pos 0
1287#define reg_dagc2_out_sat_cnt_23_16_len 8
1288#define reg_dagc2_out_sat_cnt_23_16_lsb 16
1289#define xd_p_reg_dagc2_out_sat_cnt_31_24 0xA1D0
1290#define reg_dagc2_out_sat_cnt_31_24_pos 0
1291#define reg_dagc2_out_sat_cnt_31_24_len 8
1292#define reg_dagc2_out_sat_cnt_31_24_lsb 24
1293#define xd_r_dagc2_multiplier_7_0 0xA1D6
1294#define dagc2_multiplier_7_0_pos 0
1295#define dagc2_multiplier_7_0_len 8
1296#define dagc2_multiplier_7_0_lsb 0
1297#define xd_r_dagc2_multiplier_15_8 0xA1D7
1298#define dagc2_multiplier_15_8_pos 0
1299#define dagc2_multiplier_15_8_len 8
1300#define dagc2_multiplier_15_8_lsb 8
1301#define xd_r_dagc2_right_shift_bits 0xA1D8
1302#define dagc2_right_shift_bits_pos 0
1303#define dagc2_right_shift_bits_len 4
1304#define dagc2_right_shift_bits_lsb 0
1305#define xd_p_cfoe_NS_coeff1_7_0 0xA200
1306#define cfoe_NS_coeff1_7_0_pos 0
1307#define cfoe_NS_coeff1_7_0_len 8
1308#define cfoe_NS_coeff1_7_0_lsb 0
1309#define xd_p_cfoe_NS_coeff1_15_8 0xA201
1310#define cfoe_NS_coeff1_15_8_pos 0
1311#define cfoe_NS_coeff1_15_8_len 8
1312#define cfoe_NS_coeff1_15_8_lsb 8
1313#define xd_p_cfoe_NS_coeff1_23_16 0xA202
1314#define cfoe_NS_coeff1_23_16_pos 0
1315#define cfoe_NS_coeff1_23_16_len 8
1316#define cfoe_NS_coeff1_23_16_lsb 16
1317#define xd_p_cfoe_NS_coeff1_25_24 0xA203
1318#define cfoe_NS_coeff1_25_24_pos 0
1319#define cfoe_NS_coeff1_25_24_len 2
1320#define cfoe_NS_coeff1_25_24_lsb 24
1321#define xd_p_cfoe_NS_coeff2_5_0 0xA203
1322#define cfoe_NS_coeff2_5_0_pos 2
1323#define cfoe_NS_coeff2_5_0_len 6
1324#define cfoe_NS_coeff2_5_0_lsb 0
1325#define xd_p_cfoe_NS_coeff2_13_6 0xA204
1326#define cfoe_NS_coeff2_13_6_pos 0
1327#define cfoe_NS_coeff2_13_6_len 8
1328#define cfoe_NS_coeff2_13_6_lsb 6
1329#define xd_p_cfoe_NS_coeff2_21_14 0xA205
1330#define cfoe_NS_coeff2_21_14_pos 0
1331#define cfoe_NS_coeff2_21_14_len 8
1332#define cfoe_NS_coeff2_21_14_lsb 14
1333#define xd_p_cfoe_NS_coeff2_24_22 0xA206
1334#define cfoe_NS_coeff2_24_22_pos 0
1335#define cfoe_NS_coeff2_24_22_len 3
1336#define cfoe_NS_coeff2_24_22_lsb 22
1337#define xd_p_cfoe_lf_c1_4_0 0xA206
1338#define cfoe_lf_c1_4_0_pos 3
1339#define cfoe_lf_c1_4_0_len 5
1340#define cfoe_lf_c1_4_0_lsb 0
1341#define xd_p_cfoe_lf_c1_12_5 0xA207
1342#define cfoe_lf_c1_12_5_pos 0
1343#define cfoe_lf_c1_12_5_len 8
1344#define cfoe_lf_c1_12_5_lsb 5
1345#define xd_p_cfoe_lf_c1_20_13 0xA208
1346#define cfoe_lf_c1_20_13_pos 0
1347#define cfoe_lf_c1_20_13_len 8
1348#define cfoe_lf_c1_20_13_lsb 13
1349#define xd_p_cfoe_lf_c1_25_21 0xA209
1350#define cfoe_lf_c1_25_21_pos 0
1351#define cfoe_lf_c1_25_21_len 5
1352#define cfoe_lf_c1_25_21_lsb 21
1353#define xd_p_cfoe_lf_c2_2_0 0xA209
1354#define cfoe_lf_c2_2_0_pos 5
1355#define cfoe_lf_c2_2_0_len 3
1356#define cfoe_lf_c2_2_0_lsb 0
1357#define xd_p_cfoe_lf_c2_10_3 0xA20A
1358#define cfoe_lf_c2_10_3_pos 0
1359#define cfoe_lf_c2_10_3_len 8
1360#define cfoe_lf_c2_10_3_lsb 3
1361#define xd_p_cfoe_lf_c2_18_11 0xA20B
1362#define cfoe_lf_c2_18_11_pos 0
1363#define cfoe_lf_c2_18_11_len 8
1364#define cfoe_lf_c2_18_11_lsb 11
1365#define xd_p_cfoe_lf_c2_25_19 0xA20C
1366#define cfoe_lf_c2_25_19_pos 0
1367#define cfoe_lf_c2_25_19_len 7
1368#define cfoe_lf_c2_25_19_lsb 19
1369#define xd_p_cfoe_ifod_7_0 0xA20D
1370#define cfoe_ifod_7_0_pos 0
1371#define cfoe_ifod_7_0_len 8
1372#define cfoe_ifod_7_0_lsb 0
1373#define xd_p_cfoe_ifod_10_8 0xA20E
1374#define cfoe_ifod_10_8_pos 0
1375#define cfoe_ifod_10_8_len 3
1376#define cfoe_ifod_10_8_lsb 8
1377#define xd_p_cfoe_Divg_ctr_th 0xA20E
1378#define cfoe_Divg_ctr_th_pos 4
1379#define cfoe_Divg_ctr_th_len 4
1380#define cfoe_Divg_ctr_th_lsb 0
1381#define xd_p_cfoe_FOT_divg_th 0xA20F
1382#define cfoe_FOT_divg_th_pos 0
1383#define cfoe_FOT_divg_th_len 8
1384#define cfoe_FOT_divg_th_lsb 0
1385#define xd_p_cfoe_FOT_cnvg_th 0xA210
1386#define cfoe_FOT_cnvg_th_pos 0
1387#define cfoe_FOT_cnvg_th_len 8
1388#define cfoe_FOT_cnvg_th_lsb 0
1389#define xd_p_reg_cfoe_offset_7_0 0xA211
1390#define reg_cfoe_offset_7_0_pos 0
1391#define reg_cfoe_offset_7_0_len 8
1392#define reg_cfoe_offset_7_0_lsb 0
1393#define xd_p_reg_cfoe_offset_9_8 0xA212
1394#define reg_cfoe_offset_9_8_pos 0
1395#define reg_cfoe_offset_9_8_len 2
1396#define reg_cfoe_offset_9_8_lsb 8
1397#define xd_p_reg_cfoe_ifoe_sign_corr 0xA212
1398#define reg_cfoe_ifoe_sign_corr_pos 2
1399#define reg_cfoe_ifoe_sign_corr_len 1
1400#define reg_cfoe_ifoe_sign_corr_lsb 0
1401#define xd_r_cfoe_fot_LF_output_7_0 0xA218
1402#define cfoe_fot_LF_output_7_0_pos 0
1403#define cfoe_fot_LF_output_7_0_len 8
1404#define cfoe_fot_LF_output_7_0_lsb 0
1405#define xd_r_cfoe_fot_LF_output_15_8 0xA219
1406#define cfoe_fot_LF_output_15_8_pos 0
1407#define cfoe_fot_LF_output_15_8_len 8
1408#define cfoe_fot_LF_output_15_8_lsb 8
1409#define xd_r_cfoe_ifo_metric_7_0 0xA21A
1410#define cfoe_ifo_metric_7_0_pos 0
1411#define cfoe_ifo_metric_7_0_len 8
1412#define cfoe_ifo_metric_7_0_lsb 0
1413#define xd_r_cfoe_ifo_metric_15_8 0xA21B
1414#define cfoe_ifo_metric_15_8_pos 0
1415#define cfoe_ifo_metric_15_8_len 8
1416#define cfoe_ifo_metric_15_8_lsb 8
1417#define xd_r_cfoe_ifo_metric_23_16 0xA21C
1418#define cfoe_ifo_metric_23_16_pos 0
1419#define cfoe_ifo_metric_23_16_len 8
1420#define cfoe_ifo_metric_23_16_lsb 16
1421#define xd_p_ste_Nu 0xA220
1422#define ste_Nu_pos 0
1423#define ste_Nu_len 2
1424#define ste_Nu_lsb 0
1425#define xd_p_ste_GI 0xA220
1426#define ste_GI_pos 2
1427#define ste_GI_len 3
1428#define ste_GI_lsb 0
1429#define xd_p_ste_symbol_num 0xA221
1430#define ste_symbol_num_pos 0
1431#define ste_symbol_num_len 2
1432#define ste_symbol_num_lsb 0
1433#define xd_p_ste_sample_num 0xA221
1434#define ste_sample_num_pos 2
1435#define ste_sample_num_len 2
1436#define ste_sample_num_lsb 0
1437#define xd_p_reg_ste_buf_en 0xA221
1438#define reg_ste_buf_en_pos 7
1439#define reg_ste_buf_en_len 1
1440#define reg_ste_buf_en_lsb 0
1441#define xd_p_ste_FFT_offset_7_0 0xA222
1442#define ste_FFT_offset_7_0_pos 0
1443#define ste_FFT_offset_7_0_len 8
1444#define ste_FFT_offset_7_0_lsb 0
1445#define xd_p_ste_FFT_offset_11_8 0xA223
1446#define ste_FFT_offset_11_8_pos 0
1447#define ste_FFT_offset_11_8_len 4
1448#define ste_FFT_offset_11_8_lsb 8
1449#define xd_p_reg_ste_tstmod 0xA223
1450#define reg_ste_tstmod_pos 5
1451#define reg_ste_tstmod_len 1
1452#define reg_ste_tstmod_lsb 0
1453#define xd_p_ste_adv_start_7_0 0xA224
1454#define ste_adv_start_7_0_pos 0
1455#define ste_adv_start_7_0_len 8
1456#define ste_adv_start_7_0_lsb 0
1457#define xd_p_ste_adv_start_10_8 0xA225
1458#define ste_adv_start_10_8_pos 0
1459#define ste_adv_start_10_8_len 3
1460#define ste_adv_start_10_8_lsb 8
1461#define xd_p_ste_adv_stop 0xA226
1462#define ste_adv_stop_pos 0
1463#define ste_adv_stop_len 8
1464#define ste_adv_stop_lsb 0
1465#define xd_r_ste_P_value_7_0 0xA228
1466#define ste_P_value_7_0_pos 0
1467#define ste_P_value_7_0_len 8
1468#define ste_P_value_7_0_lsb 0
1469#define xd_r_ste_P_value_10_8 0xA229
1470#define ste_P_value_10_8_pos 0
1471#define ste_P_value_10_8_len 3
1472#define ste_P_value_10_8_lsb 8
1473#define xd_r_ste_M_value_7_0 0xA22A
1474#define ste_M_value_7_0_pos 0
1475#define ste_M_value_7_0_len 8
1476#define ste_M_value_7_0_lsb 0
1477#define xd_r_ste_M_value_10_8 0xA22B
1478#define ste_M_value_10_8_pos 0
1479#define ste_M_value_10_8_len 3
1480#define ste_M_value_10_8_lsb 8
1481#define xd_r_ste_H1 0xA22C
1482#define ste_H1_pos 0
1483#define ste_H1_len 7
1484#define ste_H1_lsb 0
1485#define xd_r_ste_H2 0xA22D
1486#define ste_H2_pos 0
1487#define ste_H2_len 7
1488#define ste_H2_lsb 0
1489#define xd_r_ste_H3 0xA22E
1490#define ste_H3_pos 0
1491#define ste_H3_len 7
1492#define ste_H3_lsb 0
1493#define xd_r_ste_H4 0xA22F
1494#define ste_H4_pos 0
1495#define ste_H4_len 7
1496#define ste_H4_lsb 0
1497#define xd_r_ste_Corr_value_I_7_0 0xA230
1498#define ste_Corr_value_I_7_0_pos 0
1499#define ste_Corr_value_I_7_0_len 8
1500#define ste_Corr_value_I_7_0_lsb 0
1501#define xd_r_ste_Corr_value_I_15_8 0xA231
1502#define ste_Corr_value_I_15_8_pos 0
1503#define ste_Corr_value_I_15_8_len 8
1504#define ste_Corr_value_I_15_8_lsb 8
1505#define xd_r_ste_Corr_value_I_23_16 0xA232
1506#define ste_Corr_value_I_23_16_pos 0
1507#define ste_Corr_value_I_23_16_len 8
1508#define ste_Corr_value_I_23_16_lsb 16
1509#define xd_r_ste_Corr_value_I_27_24 0xA233
1510#define ste_Corr_value_I_27_24_pos 0
1511#define ste_Corr_value_I_27_24_len 4
1512#define ste_Corr_value_I_27_24_lsb 24
1513#define xd_r_ste_Corr_value_Q_7_0 0xA234
1514#define ste_Corr_value_Q_7_0_pos 0
1515#define ste_Corr_value_Q_7_0_len 8
1516#define ste_Corr_value_Q_7_0_lsb 0
1517#define xd_r_ste_Corr_value_Q_15_8 0xA235
1518#define ste_Corr_value_Q_15_8_pos 0
1519#define ste_Corr_value_Q_15_8_len 8
1520#define ste_Corr_value_Q_15_8_lsb 8
1521#define xd_r_ste_Corr_value_Q_23_16 0xA236
1522#define ste_Corr_value_Q_23_16_pos 0
1523#define ste_Corr_value_Q_23_16_len 8
1524#define ste_Corr_value_Q_23_16_lsb 16
1525#define xd_r_ste_Corr_value_Q_27_24 0xA237
1526#define ste_Corr_value_Q_27_24_pos 0
1527#define ste_Corr_value_Q_27_24_len 4
1528#define ste_Corr_value_Q_27_24_lsb 24
1529#define xd_r_ste_J_num_7_0 0xA238
1530#define ste_J_num_7_0_pos 0
1531#define ste_J_num_7_0_len 8
1532#define ste_J_num_7_0_lsb 0
1533#define xd_r_ste_J_num_15_8 0xA239
1534#define ste_J_num_15_8_pos 0
1535#define ste_J_num_15_8_len 8
1536#define ste_J_num_15_8_lsb 8
1537#define xd_r_ste_J_num_23_16 0xA23A
1538#define ste_J_num_23_16_pos 0
1539#define ste_J_num_23_16_len 8
1540#define ste_J_num_23_16_lsb 16
1541#define xd_r_ste_J_num_31_24 0xA23B
1542#define ste_J_num_31_24_pos 0
1543#define ste_J_num_31_24_len 8
1544#define ste_J_num_31_24_lsb 24
1545#define xd_r_ste_J_den_7_0 0xA23C
1546#define ste_J_den_7_0_pos 0
1547#define ste_J_den_7_0_len 8
1548#define ste_J_den_7_0_lsb 0
1549#define xd_r_ste_J_den_15_8 0xA23D
1550#define ste_J_den_15_8_pos 0
1551#define ste_J_den_15_8_len 8
1552#define ste_J_den_15_8_lsb 8
1553#define xd_r_ste_J_den_18_16 0xA23E
1554#define ste_J_den_18_16_pos 0
1555#define ste_J_den_18_16_len 3
1556#define ste_J_den_18_16_lsb 16
1557#define xd_r_ste_Beacon_Indicator 0xA23E
1558#define ste_Beacon_Indicator_pos 4
1559#define ste_Beacon_Indicator_len 1
1560#define ste_Beacon_Indicator_lsb 0
1561#define xd_r_tpsd_Frame_Num 0xA250
1562#define tpsd_Frame_Num_pos 0
1563#define tpsd_Frame_Num_len 2
1564#define tpsd_Frame_Num_lsb 0
1565#define xd_r_tpsd_Constel 0xA250
1566#define tpsd_Constel_pos 2
1567#define tpsd_Constel_len 2
1568#define tpsd_Constel_lsb 0
1569#define xd_r_tpsd_GI 0xA250
1570#define tpsd_GI_pos 4
1571#define tpsd_GI_len 2
1572#define tpsd_GI_lsb 0
1573#define xd_r_tpsd_Mode 0xA250
1574#define tpsd_Mode_pos 6
1575#define tpsd_Mode_len 2
1576#define tpsd_Mode_lsb 0
1577#define xd_r_tpsd_CR_HP 0xA251
1578#define tpsd_CR_HP_pos 0
1579#define tpsd_CR_HP_len 3
1580#define tpsd_CR_HP_lsb 0
1581#define xd_r_tpsd_CR_LP 0xA251
1582#define tpsd_CR_LP_pos 3
1583#define tpsd_CR_LP_len 3
1584#define tpsd_CR_LP_lsb 0
1585#define xd_r_tpsd_Hie 0xA252
1586#define tpsd_Hie_pos 0
1587#define tpsd_Hie_len 3
1588#define tpsd_Hie_lsb 0
1589#define xd_r_tpsd_Res_Bits 0xA252
1590#define tpsd_Res_Bits_pos 3
1591#define tpsd_Res_Bits_len 5
1592#define tpsd_Res_Bits_lsb 0
1593#define xd_r_tpsd_Res_Bits_0 0xA253
1594#define tpsd_Res_Bits_0_pos 0
1595#define tpsd_Res_Bits_0_len 1
1596#define tpsd_Res_Bits_0_lsb 0
1597#define xd_r_tpsd_LengthInd 0xA253
1598#define tpsd_LengthInd_pos 1
1599#define tpsd_LengthInd_len 6
1600#define tpsd_LengthInd_lsb 0
1601#define xd_r_tpsd_Cell_Id_7_0 0xA254
1602#define tpsd_Cell_Id_7_0_pos 0
1603#define tpsd_Cell_Id_7_0_len 8
1604#define tpsd_Cell_Id_7_0_lsb 0
1605#define xd_r_tpsd_Cell_Id_15_8 0xA255
1606#define tpsd_Cell_Id_15_8_pos 0
1607#define tpsd_Cell_Id_15_8_len 8
1608#define tpsd_Cell_Id_15_8_lsb 0
1609#define xd_p_reg_fft_mask_tone0_7_0 0xA260
1610#define reg_fft_mask_tone0_7_0_pos 0
1611#define reg_fft_mask_tone0_7_0_len 8
1612#define reg_fft_mask_tone0_7_0_lsb 0
1613#define xd_p_reg_fft_mask_tone0_12_8 0xA261
1614#define reg_fft_mask_tone0_12_8_pos 0
1615#define reg_fft_mask_tone0_12_8_len 5
1616#define reg_fft_mask_tone0_12_8_lsb 8
1617#define xd_p_reg_fft_mask_tone1_7_0 0xA262
1618#define reg_fft_mask_tone1_7_0_pos 0
1619#define reg_fft_mask_tone1_7_0_len 8
1620#define reg_fft_mask_tone1_7_0_lsb 0
1621#define xd_p_reg_fft_mask_tone1_12_8 0xA263
1622#define reg_fft_mask_tone1_12_8_pos 0
1623#define reg_fft_mask_tone1_12_8_len 5
1624#define reg_fft_mask_tone1_12_8_lsb 8
1625#define xd_p_reg_fft_mask_tone2_7_0 0xA264
1626#define reg_fft_mask_tone2_7_0_pos 0
1627#define reg_fft_mask_tone2_7_0_len 8
1628#define reg_fft_mask_tone2_7_0_lsb 0
1629#define xd_p_reg_fft_mask_tone2_12_8 0xA265
1630#define reg_fft_mask_tone2_12_8_pos 0
1631#define reg_fft_mask_tone2_12_8_len 5
1632#define reg_fft_mask_tone2_12_8_lsb 8
1633#define xd_p_reg_fft_mask_tone3_7_0 0xA266
1634#define reg_fft_mask_tone3_7_0_pos 0
1635#define reg_fft_mask_tone3_7_0_len 8
1636#define reg_fft_mask_tone3_7_0_lsb 0
1637#define xd_p_reg_fft_mask_tone3_12_8 0xA267
1638#define reg_fft_mask_tone3_12_8_pos 0
1639#define reg_fft_mask_tone3_12_8_len 5
1640#define reg_fft_mask_tone3_12_8_lsb 8
1641#define xd_p_reg_fft_mask_from0_7_0 0xA268
1642#define reg_fft_mask_from0_7_0_pos 0
1643#define reg_fft_mask_from0_7_0_len 8
1644#define reg_fft_mask_from0_7_0_lsb 0
1645#define xd_p_reg_fft_mask_from0_12_8 0xA269
1646#define reg_fft_mask_from0_12_8_pos 0
1647#define reg_fft_mask_from0_12_8_len 5
1648#define reg_fft_mask_from0_12_8_lsb 8
1649#define xd_p_reg_fft_mask_to0_7_0 0xA26A
1650#define reg_fft_mask_to0_7_0_pos 0
1651#define reg_fft_mask_to0_7_0_len 8
1652#define reg_fft_mask_to0_7_0_lsb 0
1653#define xd_p_reg_fft_mask_to0_12_8 0xA26B
1654#define reg_fft_mask_to0_12_8_pos 0
1655#define reg_fft_mask_to0_12_8_len 5
1656#define reg_fft_mask_to0_12_8_lsb 8
1657#define xd_p_reg_fft_mask_from1_7_0 0xA26C
1658#define reg_fft_mask_from1_7_0_pos 0
1659#define reg_fft_mask_from1_7_0_len 8
1660#define reg_fft_mask_from1_7_0_lsb 0
1661#define xd_p_reg_fft_mask_from1_12_8 0xA26D
1662#define reg_fft_mask_from1_12_8_pos 0
1663#define reg_fft_mask_from1_12_8_len 5
1664#define reg_fft_mask_from1_12_8_lsb 8
1665#define xd_p_reg_fft_mask_to1_7_0 0xA26E
1666#define reg_fft_mask_to1_7_0_pos 0
1667#define reg_fft_mask_to1_7_0_len 8
1668#define reg_fft_mask_to1_7_0_lsb 0
1669#define xd_p_reg_fft_mask_to1_12_8 0xA26F
1670#define reg_fft_mask_to1_12_8_pos 0
1671#define reg_fft_mask_to1_12_8_len 5
1672#define reg_fft_mask_to1_12_8_lsb 8
1673#define xd_p_reg_cge_idx0_7_0 0xA280
1674#define reg_cge_idx0_7_0_pos 0
1675#define reg_cge_idx0_7_0_len 8
1676#define reg_cge_idx0_7_0_lsb 0
1677#define xd_p_reg_cge_idx0_12_8 0xA281
1678#define reg_cge_idx0_12_8_pos 0
1679#define reg_cge_idx0_12_8_len 5
1680#define reg_cge_idx0_12_8_lsb 8
1681#define xd_p_reg_cge_idx1_7_0 0xA282
1682#define reg_cge_idx1_7_0_pos 0
1683#define reg_cge_idx1_7_0_len 8
1684#define reg_cge_idx1_7_0_lsb 0
1685#define xd_p_reg_cge_idx1_12_8 0xA283
1686#define reg_cge_idx1_12_8_pos 0
1687#define reg_cge_idx1_12_8_len 5
1688#define reg_cge_idx1_12_8_lsb 8
1689#define xd_p_reg_cge_idx2_7_0 0xA284
1690#define reg_cge_idx2_7_0_pos 0
1691#define reg_cge_idx2_7_0_len 8
1692#define reg_cge_idx2_7_0_lsb 0
1693#define xd_p_reg_cge_idx2_12_8 0xA285
1694#define reg_cge_idx2_12_8_pos 0
1695#define reg_cge_idx2_12_8_len 5
1696#define reg_cge_idx2_12_8_lsb 8
1697#define xd_p_reg_cge_idx3_7_0 0xA286
1698#define reg_cge_idx3_7_0_pos 0
1699#define reg_cge_idx3_7_0_len 8
1700#define reg_cge_idx3_7_0_lsb 0
1701#define xd_p_reg_cge_idx3_12_8 0xA287
1702#define reg_cge_idx3_12_8_pos 0
1703#define reg_cge_idx3_12_8_len 5
1704#define reg_cge_idx3_12_8_lsb 8
1705#define xd_p_reg_cge_idx4_7_0 0xA288
1706#define reg_cge_idx4_7_0_pos 0
1707#define reg_cge_idx4_7_0_len 8
1708#define reg_cge_idx4_7_0_lsb 0
1709#define xd_p_reg_cge_idx4_12_8 0xA289
1710#define reg_cge_idx4_12_8_pos 0
1711#define reg_cge_idx4_12_8_len 5
1712#define reg_cge_idx4_12_8_lsb 8
1713#define xd_p_reg_cge_idx5_7_0 0xA28A
1714#define reg_cge_idx5_7_0_pos 0
1715#define reg_cge_idx5_7_0_len 8
1716#define reg_cge_idx5_7_0_lsb 0
1717#define xd_p_reg_cge_idx5_12_8 0xA28B
1718#define reg_cge_idx5_12_8_pos 0
1719#define reg_cge_idx5_12_8_len 5
1720#define reg_cge_idx5_12_8_lsb 8
1721#define xd_p_reg_cge_idx6_7_0 0xA28C
1722#define reg_cge_idx6_7_0_pos 0
1723#define reg_cge_idx6_7_0_len 8
1724#define reg_cge_idx6_7_0_lsb 0
1725#define xd_p_reg_cge_idx6_12_8 0xA28D
1726#define reg_cge_idx6_12_8_pos 0
1727#define reg_cge_idx6_12_8_len 5
1728#define reg_cge_idx6_12_8_lsb 8
1729#define xd_p_reg_cge_idx7_7_0 0xA28E
1730#define reg_cge_idx7_7_0_pos 0
1731#define reg_cge_idx7_7_0_len 8
1732#define reg_cge_idx7_7_0_lsb 0
1733#define xd_p_reg_cge_idx7_12_8 0xA28F
1734#define reg_cge_idx7_12_8_pos 0
1735#define reg_cge_idx7_12_8_len 5
1736#define reg_cge_idx7_12_8_lsb 8
1737#define xd_p_reg_cge_idx8_7_0 0xA290
1738#define reg_cge_idx8_7_0_pos 0
1739#define reg_cge_idx8_7_0_len 8
1740#define reg_cge_idx8_7_0_lsb 0
1741#define xd_p_reg_cge_idx8_12_8 0xA291
1742#define reg_cge_idx8_12_8_pos 0
1743#define reg_cge_idx8_12_8_len 5
1744#define reg_cge_idx8_12_8_lsb 8
1745#define xd_p_reg_cge_idx9_7_0 0xA292
1746#define reg_cge_idx9_7_0_pos 0
1747#define reg_cge_idx9_7_0_len 8
1748#define reg_cge_idx9_7_0_lsb 0
1749#define xd_p_reg_cge_idx9_12_8 0xA293
1750#define reg_cge_idx9_12_8_pos 0
1751#define reg_cge_idx9_12_8_len 5
1752#define reg_cge_idx9_12_8_lsb 8
1753#define xd_p_reg_cge_idx10_7_0 0xA294
1754#define reg_cge_idx10_7_0_pos 0
1755#define reg_cge_idx10_7_0_len 8
1756#define reg_cge_idx10_7_0_lsb 0
1757#define xd_p_reg_cge_idx10_12_8 0xA295
1758#define reg_cge_idx10_12_8_pos 0
1759#define reg_cge_idx10_12_8_len 5
1760#define reg_cge_idx10_12_8_lsb 8
1761#define xd_p_reg_cge_idx11_7_0 0xA296
1762#define reg_cge_idx11_7_0_pos 0
1763#define reg_cge_idx11_7_0_len 8
1764#define reg_cge_idx11_7_0_lsb 0
1765#define xd_p_reg_cge_idx11_12_8 0xA297
1766#define reg_cge_idx11_12_8_pos 0
1767#define reg_cge_idx11_12_8_len 5
1768#define reg_cge_idx11_12_8_lsb 8
1769#define xd_p_reg_cge_idx12_7_0 0xA298
1770#define reg_cge_idx12_7_0_pos 0
1771#define reg_cge_idx12_7_0_len 8
1772#define reg_cge_idx12_7_0_lsb 0
1773#define xd_p_reg_cge_idx12_12_8 0xA299
1774#define reg_cge_idx12_12_8_pos 0
1775#define reg_cge_idx12_12_8_len 5
1776#define reg_cge_idx12_12_8_lsb 8
1777#define xd_p_reg_cge_idx13_7_0 0xA29A
1778#define reg_cge_idx13_7_0_pos 0
1779#define reg_cge_idx13_7_0_len 8
1780#define reg_cge_idx13_7_0_lsb 0
1781#define xd_p_reg_cge_idx13_12_8 0xA29B
1782#define reg_cge_idx13_12_8_pos 0
1783#define reg_cge_idx13_12_8_len 5
1784#define reg_cge_idx13_12_8_lsb 8
1785#define xd_p_reg_cge_idx14_7_0 0xA29C
1786#define reg_cge_idx14_7_0_pos 0
1787#define reg_cge_idx14_7_0_len 8
1788#define reg_cge_idx14_7_0_lsb 0
1789#define xd_p_reg_cge_idx14_12_8 0xA29D
1790#define reg_cge_idx14_12_8_pos 0
1791#define reg_cge_idx14_12_8_len 5
1792#define reg_cge_idx14_12_8_lsb 8
1793#define xd_p_reg_cge_idx15_7_0 0xA29E
1794#define reg_cge_idx15_7_0_pos 0
1795#define reg_cge_idx15_7_0_len 8
1796#define reg_cge_idx15_7_0_lsb 0
1797#define xd_p_reg_cge_idx15_12_8 0xA29F
1798#define reg_cge_idx15_12_8_pos 0
1799#define reg_cge_idx15_12_8_len 5
1800#define reg_cge_idx15_12_8_lsb 8
1801#define xd_r_reg_fft_crc 0xA2A8
1802#define reg_fft_crc_pos 0
1803#define reg_fft_crc_len 8
1804#define reg_fft_crc_lsb 0
1805#define xd_p_fd_fft_shift_max 0xA2A9
1806#define fd_fft_shift_max_pos 0
1807#define fd_fft_shift_max_len 4
1808#define fd_fft_shift_max_lsb 0
1809#define xd_r_fd_fft_shift 0xA2A9
1810#define fd_fft_shift_pos 4
1811#define fd_fft_shift_len 4
1812#define fd_fft_shift_lsb 0
1813#define xd_r_fd_fft_frame_num 0xA2AA
1814#define fd_fft_frame_num_pos 0
1815#define fd_fft_frame_num_len 2
1816#define fd_fft_frame_num_lsb 0
1817#define xd_r_fd_fft_symbol_count 0xA2AB
1818#define fd_fft_symbol_count_pos 0
1819#define fd_fft_symbol_count_len 7
1820#define fd_fft_symbol_count_lsb 0
1821#define xd_r_reg_fft_idx_max_7_0 0xA2AC
1822#define reg_fft_idx_max_7_0_pos 0
1823#define reg_fft_idx_max_7_0_len 8
1824#define reg_fft_idx_max_7_0_lsb 0
1825#define xd_r_reg_fft_idx_max_12_8 0xA2AD
1826#define reg_fft_idx_max_12_8_pos 0
1827#define reg_fft_idx_max_12_8_len 5
1828#define reg_fft_idx_max_12_8_lsb 8
1829#define xd_p_reg_cge_program 0xA2AE
1830#define reg_cge_program_pos 0
1831#define reg_cge_program_len 1
1832#define reg_cge_program_lsb 0
1833#define xd_p_reg_cge_fixed 0xA2AE
1834#define reg_cge_fixed_pos 1
1835#define reg_cge_fixed_len 1
1836#define reg_cge_fixed_lsb 0
1837#define xd_p_reg_fft_rotate_en 0xA2AE
1838#define reg_fft_rotate_en_pos 2
1839#define reg_fft_rotate_en_len 1
1840#define reg_fft_rotate_en_lsb 0
1841#define xd_p_reg_fft_rotate_base_4_0 0xA2AE
1842#define reg_fft_rotate_base_4_0_pos 3
1843#define reg_fft_rotate_base_4_0_len 5
1844#define reg_fft_rotate_base_4_0_lsb 0
1845#define xd_p_reg_fft_rotate_base_12_5 0xA2AF
1846#define reg_fft_rotate_base_12_5_pos 0
1847#define reg_fft_rotate_base_12_5_len 8
1848#define reg_fft_rotate_base_12_5_lsb 5
1849#define xd_p_reg_gp_trigger_fd 0xA2B8
1850#define reg_gp_trigger_fd_pos 0
1851#define reg_gp_trigger_fd_len 1
1852#define reg_gp_trigger_fd_lsb 0
1853#define xd_p_reg_trigger_sel_fd 0xA2B8
1854#define reg_trigger_sel_fd_pos 1
1855#define reg_trigger_sel_fd_len 2
1856#define reg_trigger_sel_fd_lsb 0
1857#define xd_p_reg_trigger_module_sel_fd 0xA2B9
1858#define reg_trigger_module_sel_fd_pos 0
1859#define reg_trigger_module_sel_fd_len 6
1860#define reg_trigger_module_sel_fd_lsb 0
1861#define xd_p_reg_trigger_set_sel_fd 0xA2BA
1862#define reg_trigger_set_sel_fd_pos 0
1863#define reg_trigger_set_sel_fd_len 6
1864#define reg_trigger_set_sel_fd_lsb 0
1865#define xd_p_reg_fd_noname_7_0 0xA2BC
1866#define reg_fd_noname_7_0_pos 0
1867#define reg_fd_noname_7_0_len 8
1868#define reg_fd_noname_7_0_lsb 0
1869#define xd_p_reg_fd_noname_15_8 0xA2BD
1870#define reg_fd_noname_15_8_pos 0
1871#define reg_fd_noname_15_8_len 8
1872#define reg_fd_noname_15_8_lsb 8
1873#define xd_p_reg_fd_noname_23_16 0xA2BE
1874#define reg_fd_noname_23_16_pos 0
1875#define reg_fd_noname_23_16_len 8
1876#define reg_fd_noname_23_16_lsb 16
1877#define xd_p_reg_fd_noname_31_24 0xA2BF
1878#define reg_fd_noname_31_24_pos 0
1879#define reg_fd_noname_31_24_len 8
1880#define reg_fd_noname_31_24_lsb 24
1881#define xd_r_fd_fpcc_cp_corr_signn 0xA2C0
1882#define fd_fpcc_cp_corr_signn_pos 0
1883#define fd_fpcc_cp_corr_signn_len 8
1884#define fd_fpcc_cp_corr_signn_lsb 0
1885#define xd_p_reg_feq_s1 0xA2C1
1886#define reg_feq_s1_pos 0
1887#define reg_feq_s1_len 5
1888#define reg_feq_s1_lsb 0
1889#define xd_p_fd_fpcc_cp_corr_tone_th 0xA2C2
1890#define fd_fpcc_cp_corr_tone_th_pos 0
1891#define fd_fpcc_cp_corr_tone_th_len 6
1892#define fd_fpcc_cp_corr_tone_th_lsb 0
1893#define xd_p_fd_fpcc_cp_corr_symbol_log_th 0xA2C3
1894#define fd_fpcc_cp_corr_symbol_log_th_pos 0
1895#define fd_fpcc_cp_corr_symbol_log_th_len 4
1896#define fd_fpcc_cp_corr_symbol_log_th_lsb 0
1897#define xd_p_fd_fpcc_cp_corr_int 0xA2C4
1898#define fd_fpcc_cp_corr_int_pos 0
1899#define fd_fpcc_cp_corr_int_len 1
1900#define fd_fpcc_cp_corr_int_lsb 0
1901#define xd_p_reg_sfoe_ns_7_0 0xA320
1902#define reg_sfoe_ns_7_0_pos 0
1903#define reg_sfoe_ns_7_0_len 8
1904#define reg_sfoe_ns_7_0_lsb 0
1905#define xd_p_reg_sfoe_ns_14_8 0xA321
1906#define reg_sfoe_ns_14_8_pos 0
1907#define reg_sfoe_ns_14_8_len 7
1908#define reg_sfoe_ns_14_8_lsb 8
1909#define xd_p_reg_sfoe_c1_7_0 0xA322
1910#define reg_sfoe_c1_7_0_pos 0
1911#define reg_sfoe_c1_7_0_len 8
1912#define reg_sfoe_c1_7_0_lsb 0
1913#define xd_p_reg_sfoe_c1_15_8 0xA323
1914#define reg_sfoe_c1_15_8_pos 0
1915#define reg_sfoe_c1_15_8_len 8
1916#define reg_sfoe_c1_15_8_lsb 8
1917#define xd_p_reg_sfoe_c1_17_16 0xA324
1918#define reg_sfoe_c1_17_16_pos 0
1919#define reg_sfoe_c1_17_16_len 2
1920#define reg_sfoe_c1_17_16_lsb 16
1921#define xd_p_reg_sfoe_c2_7_0 0xA325
1922#define reg_sfoe_c2_7_0_pos 0
1923#define reg_sfoe_c2_7_0_len 8
1924#define reg_sfoe_c2_7_0_lsb 0
1925#define xd_p_reg_sfoe_c2_15_8 0xA326
1926#define reg_sfoe_c2_15_8_pos 0
1927#define reg_sfoe_c2_15_8_len 8
1928#define reg_sfoe_c2_15_8_lsb 8
1929#define xd_p_reg_sfoe_c2_17_16 0xA327
1930#define reg_sfoe_c2_17_16_pos 0
1931#define reg_sfoe_c2_17_16_len 2
1932#define reg_sfoe_c2_17_16_lsb 16
1933#define xd_r_reg_sfoe_out_9_2 0xA328
1934#define reg_sfoe_out_9_2_pos 0
1935#define reg_sfoe_out_9_2_len 8
1936#define reg_sfoe_out_9_2_lsb 0
1937#define xd_r_reg_sfoe_out_1_0 0xA329
1938#define reg_sfoe_out_1_0_pos 0
1939#define reg_sfoe_out_1_0_len 2
1940#define reg_sfoe_out_1_0_lsb 0
1941#define xd_p_reg_sfoe_lm_counter_th 0xA32A
1942#define reg_sfoe_lm_counter_th_pos 0
1943#define reg_sfoe_lm_counter_th_len 4
1944#define reg_sfoe_lm_counter_th_lsb 0
1945#define xd_p_reg_sfoe_convg_th 0xA32B
1946#define reg_sfoe_convg_th_pos 0
1947#define reg_sfoe_convg_th_len 8
1948#define reg_sfoe_convg_th_lsb 0
1949#define xd_p_reg_sfoe_divg_th 0xA32C
1950#define reg_sfoe_divg_th_pos 0
1951#define reg_sfoe_divg_th_len 8
1952#define reg_sfoe_divg_th_lsb 0
1953#define xd_p_fd_tpsd_en 0xA330
1954#define fd_tpsd_en_pos 0
1955#define fd_tpsd_en_len 1
1956#define fd_tpsd_en_lsb 0
1957#define xd_p_fd_tpsd_dis 0xA330
1958#define fd_tpsd_dis_pos 1
1959#define fd_tpsd_dis_len 1
1960#define fd_tpsd_dis_lsb 0
1961#define xd_p_fd_tpsd_rst 0xA330
1962#define fd_tpsd_rst_pos 2
1963#define fd_tpsd_rst_len 1
1964#define fd_tpsd_rst_lsb 0
1965#define xd_p_fd_tpsd_lock 0xA330
1966#define fd_tpsd_lock_pos 3
1967#define fd_tpsd_lock_len 1
1968#define fd_tpsd_lock_lsb 0
1969#define xd_r_fd_tpsd_s19 0xA330
1970#define fd_tpsd_s19_pos 4
1971#define fd_tpsd_s19_len 1
1972#define fd_tpsd_s19_lsb 0
1973#define xd_r_fd_tpsd_s17 0xA330
1974#define fd_tpsd_s17_pos 5
1975#define fd_tpsd_s17_len 1
1976#define fd_tpsd_s17_lsb 0
1977#define xd_p_fd_sfr_ste_en 0xA331
1978#define fd_sfr_ste_en_pos 0
1979#define fd_sfr_ste_en_len 1
1980#define fd_sfr_ste_en_lsb 0
1981#define xd_p_fd_sfr_ste_dis 0xA331
1982#define fd_sfr_ste_dis_pos 1
1983#define fd_sfr_ste_dis_len 1
1984#define fd_sfr_ste_dis_lsb 0
1985#define xd_p_fd_sfr_ste_rst 0xA331
1986#define fd_sfr_ste_rst_pos 2
1987#define fd_sfr_ste_rst_len 1
1988#define fd_sfr_ste_rst_lsb 0
1989#define xd_p_fd_sfr_ste_mode 0xA331
1990#define fd_sfr_ste_mode_pos 3
1991#define fd_sfr_ste_mode_len 1
1992#define fd_sfr_ste_mode_lsb 0
1993#define xd_p_fd_sfr_ste_done 0xA331
1994#define fd_sfr_ste_done_pos 4
1995#define fd_sfr_ste_done_len 1
1996#define fd_sfr_ste_done_lsb 0
1997#define xd_p_reg_cfoe_ffoe_en 0xA332
1998#define reg_cfoe_ffoe_en_pos 0
1999#define reg_cfoe_ffoe_en_len 1
2000#define reg_cfoe_ffoe_en_lsb 0
2001#define xd_p_reg_cfoe_ffoe_dis 0xA332
2002#define reg_cfoe_ffoe_dis_pos 1
2003#define reg_cfoe_ffoe_dis_len 1
2004#define reg_cfoe_ffoe_dis_lsb 0
2005#define xd_p_reg_cfoe_ffoe_rst 0xA332
2006#define reg_cfoe_ffoe_rst_pos 2
2007#define reg_cfoe_ffoe_rst_len 1
2008#define reg_cfoe_ffoe_rst_lsb 0
2009#define xd_p_reg_cfoe_ifoe_en 0xA332
2010#define reg_cfoe_ifoe_en_pos 3
2011#define reg_cfoe_ifoe_en_len 1
2012#define reg_cfoe_ifoe_en_lsb 0
2013#define xd_p_reg_cfoe_ifoe_dis 0xA332
2014#define reg_cfoe_ifoe_dis_pos 4
2015#define reg_cfoe_ifoe_dis_len 1
2016#define reg_cfoe_ifoe_dis_lsb 0
2017#define xd_p_reg_cfoe_ifoe_rst 0xA332
2018#define reg_cfoe_ifoe_rst_pos 5
2019#define reg_cfoe_ifoe_rst_len 1
2020#define reg_cfoe_ifoe_rst_lsb 0
2021#define xd_p_reg_cfoe_fot_en 0xA332
2022#define reg_cfoe_fot_en_pos 6
2023#define reg_cfoe_fot_en_len 1
2024#define reg_cfoe_fot_en_lsb 0
2025#define xd_p_reg_cfoe_fot_lm_en 0xA332
2026#define reg_cfoe_fot_lm_en_pos 7
2027#define reg_cfoe_fot_lm_en_len 1
2028#define reg_cfoe_fot_lm_en_lsb 0
2029#define xd_p_reg_cfoe_fot_rst 0xA333
2030#define reg_cfoe_fot_rst_pos 0
2031#define reg_cfoe_fot_rst_len 1
2032#define reg_cfoe_fot_rst_lsb 0
2033#define xd_r_fd_cfoe_ffoe_done 0xA333
2034#define fd_cfoe_ffoe_done_pos 1
2035#define fd_cfoe_ffoe_done_len 1
2036#define fd_cfoe_ffoe_done_lsb 0
2037#define xd_p_fd_cfoe_metric_vld 0xA333
2038#define fd_cfoe_metric_vld_pos 2
2039#define fd_cfoe_metric_vld_len 1
2040#define fd_cfoe_metric_vld_lsb 0
2041#define xd_p_reg_cfoe_ifod_vld 0xA333
2042#define reg_cfoe_ifod_vld_pos 3
2043#define reg_cfoe_ifod_vld_len 1
2044#define reg_cfoe_ifod_vld_lsb 0
2045#define xd_r_fd_cfoe_ifoe_done 0xA333
2046#define fd_cfoe_ifoe_done_pos 4
2047#define fd_cfoe_ifoe_done_len 1
2048#define fd_cfoe_ifoe_done_lsb 0
2049#define xd_r_fd_cfoe_fot_valid 0xA333
2050#define fd_cfoe_fot_valid_pos 5
2051#define fd_cfoe_fot_valid_len 1
2052#define fd_cfoe_fot_valid_lsb 0
2053#define xd_p_reg_cfoe_divg_int 0xA333
2054#define reg_cfoe_divg_int_pos 6
2055#define reg_cfoe_divg_int_len 1
2056#define reg_cfoe_divg_int_lsb 0
2057#define xd_r_reg_cfoe_divg_flag 0xA333
2058#define reg_cfoe_divg_flag_pos 7
2059#define reg_cfoe_divg_flag_len 1
2060#define reg_cfoe_divg_flag_lsb 0
2061#define xd_p_reg_sfoe_en 0xA334
2062#define reg_sfoe_en_pos 0
2063#define reg_sfoe_en_len 1
2064#define reg_sfoe_en_lsb 0
2065#define xd_p_reg_sfoe_dis 0xA334
2066#define reg_sfoe_dis_pos 1
2067#define reg_sfoe_dis_len 1
2068#define reg_sfoe_dis_lsb 0
2069#define xd_p_reg_sfoe_rst 0xA334
2070#define reg_sfoe_rst_pos 2
2071#define reg_sfoe_rst_len 1
2072#define reg_sfoe_rst_lsb 0
2073#define xd_p_reg_sfoe_vld_int 0xA334
2074#define reg_sfoe_vld_int_pos 3
2075#define reg_sfoe_vld_int_len 1
2076#define reg_sfoe_vld_int_lsb 0
2077#define xd_p_reg_sfoe_lm_en 0xA334
2078#define reg_sfoe_lm_en_pos 4
2079#define reg_sfoe_lm_en_len 1
2080#define reg_sfoe_lm_en_lsb 0
2081#define xd_p_reg_sfoe_divg_int 0xA334
2082#define reg_sfoe_divg_int_pos 5
2083#define reg_sfoe_divg_int_len 1
2084#define reg_sfoe_divg_int_lsb 0
2085#define xd_r_reg_sfoe_divg_flag 0xA334
2086#define reg_sfoe_divg_flag_pos 6
2087#define reg_sfoe_divg_flag_len 1
2088#define reg_sfoe_divg_flag_lsb 0
2089#define xd_p_reg_fft_rst 0xA335
2090#define reg_fft_rst_pos 0
2091#define reg_fft_rst_len 1
2092#define reg_fft_rst_lsb 0
2093#define xd_p_reg_fft_fast_beacon 0xA335
2094#define reg_fft_fast_beacon_pos 1
2095#define reg_fft_fast_beacon_len 1
2096#define reg_fft_fast_beacon_lsb 0
2097#define xd_p_reg_fft_fast_valid 0xA335
2098#define reg_fft_fast_valid_pos 2
2099#define reg_fft_fast_valid_len 1
2100#define reg_fft_fast_valid_lsb 0
2101#define xd_p_reg_fft_mask_en 0xA335
2102#define reg_fft_mask_en_pos 3
2103#define reg_fft_mask_en_len 1
2104#define reg_fft_mask_en_lsb 0
2105#define xd_p_reg_fft_crc_en 0xA335
2106#define reg_fft_crc_en_pos 4
2107#define reg_fft_crc_en_len 1
2108#define reg_fft_crc_en_lsb 0
2109#define xd_p_reg_finr_en 0xA336
2110#define reg_finr_en_pos 0
2111#define reg_finr_en_len 1
2112#define reg_finr_en_lsb 0
2113#define xd_p_fd_fste_en 0xA337
2114#define fd_fste_en_pos 1
2115#define fd_fste_en_len 1
2116#define fd_fste_en_lsb 0
2117#define xd_p_fd_sqi_tps_level_shift 0xA338
2118#define fd_sqi_tps_level_shift_pos 0
2119#define fd_sqi_tps_level_shift_len 8
2120#define fd_sqi_tps_level_shift_lsb 0
2121#define xd_p_fd_pilot_ma_len 0xA339
2122#define fd_pilot_ma_len_pos 0
2123#define fd_pilot_ma_len_len 6
2124#define fd_pilot_ma_len_lsb 0
2125#define xd_p_fd_tps_ma_len 0xA33A
2126#define fd_tps_ma_len_pos 0
2127#define fd_tps_ma_len_len 6
2128#define fd_tps_ma_len_lsb 0
2129#define xd_p_fd_sqi_s3 0xA33B
2130#define fd_sqi_s3_pos 0
2131#define fd_sqi_s3_len 8
2132#define fd_sqi_s3_lsb 0
2133#define xd_p_fd_sqi_dummy_reg_0 0xA33C
2134#define fd_sqi_dummy_reg_0_pos 0
2135#define fd_sqi_dummy_reg_0_len 1
2136#define fd_sqi_dummy_reg_0_lsb 0
2137#define xd_p_fd_sqi_debug_sel 0xA33C
2138#define fd_sqi_debug_sel_pos 1
2139#define fd_sqi_debug_sel_len 2
2140#define fd_sqi_debug_sel_lsb 0
2141#define xd_p_fd_sqi_s2 0xA33C
2142#define fd_sqi_s2_pos 3
2143#define fd_sqi_s2_len 5
2144#define fd_sqi_s2_lsb 0
2145#define xd_p_fd_sqi_dummy_reg_1 0xA33D
2146#define fd_sqi_dummy_reg_1_pos 0
2147#define fd_sqi_dummy_reg_1_len 1
2148#define fd_sqi_dummy_reg_1_lsb 0
2149#define xd_p_fd_inr_ignore 0xA33D
2150#define fd_inr_ignore_pos 1
2151#define fd_inr_ignore_len 1
2152#define fd_inr_ignore_lsb 0
2153#define xd_p_fd_pilot_ignore 0xA33D
2154#define fd_pilot_ignore_pos 2
2155#define fd_pilot_ignore_len 1
2156#define fd_pilot_ignore_lsb 0
2157#define xd_p_fd_etps_ignore 0xA33D
2158#define fd_etps_ignore_pos 3
2159#define fd_etps_ignore_len 1
2160#define fd_etps_ignore_lsb 0
2161#define xd_p_fd_sqi_s1 0xA33D
2162#define fd_sqi_s1_pos 4
2163#define fd_sqi_s1_len 4
2164#define fd_sqi_s1_lsb 0
2165#define xd_p_reg_fste_ehw_7_0 0xA33E
2166#define reg_fste_ehw_7_0_pos 0
2167#define reg_fste_ehw_7_0_len 8
2168#define reg_fste_ehw_7_0_lsb 0
2169#define xd_p_reg_fste_ehw_9_8 0xA33F
2170#define reg_fste_ehw_9_8_pos 0
2171#define reg_fste_ehw_9_8_len 2
2172#define reg_fste_ehw_9_8_lsb 8
2173#define xd_p_reg_fste_i_adj_vld 0xA33F
2174#define reg_fste_i_adj_vld_pos 2
2175#define reg_fste_i_adj_vld_len 1
2176#define reg_fste_i_adj_vld_lsb 0
2177#define xd_p_reg_fste_phase_ini_7_0 0xA340
2178#define reg_fste_phase_ini_7_0_pos 0
2179#define reg_fste_phase_ini_7_0_len 8
2180#define reg_fste_phase_ini_7_0_lsb 0
2181#define xd_p_reg_fste_phase_ini_11_8 0xA341
2182#define reg_fste_phase_ini_11_8_pos 0
2183#define reg_fste_phase_ini_11_8_len 4
2184#define reg_fste_phase_ini_11_8_lsb 8
2185#define xd_p_reg_fste_phase_inc_3_0 0xA341
2186#define reg_fste_phase_inc_3_0_pos 4
2187#define reg_fste_phase_inc_3_0_len 4
2188#define reg_fste_phase_inc_3_0_lsb 0
2189#define xd_p_reg_fste_phase_inc_11_4 0xA342
2190#define reg_fste_phase_inc_11_4_pos 0
2191#define reg_fste_phase_inc_11_4_len 8
2192#define reg_fste_phase_inc_11_4_lsb 4
2193#define xd_p_reg_fste_acum_cost_cnt_max 0xA343
2194#define reg_fste_acum_cost_cnt_max_pos 0
2195#define reg_fste_acum_cost_cnt_max_len 4
2196#define reg_fste_acum_cost_cnt_max_lsb 0
2197#define xd_p_reg_fste_step_size_std 0xA343
2198#define reg_fste_step_size_std_pos 4
2199#define reg_fste_step_size_std_len 4
2200#define reg_fste_step_size_std_lsb 0
2201#define xd_p_reg_fste_step_size_max 0xA344
2202#define reg_fste_step_size_max_pos 0
2203#define reg_fste_step_size_max_len 4
2204#define reg_fste_step_size_max_lsb 0
2205#define xd_p_reg_fste_step_size_min 0xA344
2206#define reg_fste_step_size_min_pos 4
2207#define reg_fste_step_size_min_len 4
2208#define reg_fste_step_size_min_lsb 0
2209#define xd_p_reg_fste_frac_step_size_7_0 0xA345
2210#define reg_fste_frac_step_size_7_0_pos 0
2211#define reg_fste_frac_step_size_7_0_len 8
2212#define reg_fste_frac_step_size_7_0_lsb 0
2213#define xd_p_reg_fste_frac_step_size_15_8 0xA346
2214#define reg_fste_frac_step_size_15_8_pos 0
2215#define reg_fste_frac_step_size_15_8_len 8
2216#define reg_fste_frac_step_size_15_8_lsb 8
2217#define xd_p_reg_fste_frac_step_size_19_16 0xA347
2218#define reg_fste_frac_step_size_19_16_pos 0
2219#define reg_fste_frac_step_size_19_16_len 4
2220#define reg_fste_frac_step_size_19_16_lsb 16
2221#define xd_p_reg_fste_rpd_dir_cnt_max 0xA347
2222#define reg_fste_rpd_dir_cnt_max_pos 4
2223#define reg_fste_rpd_dir_cnt_max_len 4
2224#define reg_fste_rpd_dir_cnt_max_lsb 0
2225#define xd_p_reg_fste_ehs 0xA348
2226#define reg_fste_ehs_pos 0
2227#define reg_fste_ehs_len 4
2228#define reg_fste_ehs_lsb 0
2229#define xd_p_reg_fste_frac_cost_cnt_max_3_0 0xA348
2230#define reg_fste_frac_cost_cnt_max_3_0_pos 4
2231#define reg_fste_frac_cost_cnt_max_3_0_len 4
2232#define reg_fste_frac_cost_cnt_max_3_0_lsb 0
2233#define xd_p_reg_fste_frac_cost_cnt_max_9_4 0xA349
2234#define reg_fste_frac_cost_cnt_max_9_4_pos 0
2235#define reg_fste_frac_cost_cnt_max_9_4_len 6
2236#define reg_fste_frac_cost_cnt_max_9_4_lsb 4
2237#define xd_p_reg_fste_w0_7_0 0xA34A
2238#define reg_fste_w0_7_0_pos 0
2239#define reg_fste_w0_7_0_len 8
2240#define reg_fste_w0_7_0_lsb 0
2241#define xd_p_reg_fste_w0_11_8 0xA34B
2242#define reg_fste_w0_11_8_pos 0
2243#define reg_fste_w0_11_8_len 4
2244#define reg_fste_w0_11_8_lsb 8
2245#define xd_p_reg_fste_w1_3_0 0xA34B
2246#define reg_fste_w1_3_0_pos 4
2247#define reg_fste_w1_3_0_len 4
2248#define reg_fste_w1_3_0_lsb 0
2249#define xd_p_reg_fste_w1_11_4 0xA34C
2250#define reg_fste_w1_11_4_pos 0
2251#define reg_fste_w1_11_4_len 8
2252#define reg_fste_w1_11_4_lsb 4
2253#define xd_p_reg_fste_w2_7_0 0xA34D
2254#define reg_fste_w2_7_0_pos 0
2255#define reg_fste_w2_7_0_len 8
2256#define reg_fste_w2_7_0_lsb 0
2257#define xd_p_reg_fste_w2_11_8 0xA34E
2258#define reg_fste_w2_11_8_pos 0
2259#define reg_fste_w2_11_8_len 4
2260#define reg_fste_w2_11_8_lsb 8
2261#define xd_p_reg_fste_w3_3_0 0xA34E
2262#define reg_fste_w3_3_0_pos 4
2263#define reg_fste_w3_3_0_len 4
2264#define reg_fste_w3_3_0_lsb 0
2265#define xd_p_reg_fste_w3_11_4 0xA34F
2266#define reg_fste_w3_11_4_pos 0
2267#define reg_fste_w3_11_4_len 8
2268#define reg_fste_w3_11_4_lsb 4
2269#define xd_p_reg_fste_w4_7_0 0xA350
2270#define reg_fste_w4_7_0_pos 0
2271#define reg_fste_w4_7_0_len 8
2272#define reg_fste_w4_7_0_lsb 0
2273#define xd_p_reg_fste_w4_11_8 0xA351
2274#define reg_fste_w4_11_8_pos 0
2275#define reg_fste_w4_11_8_len 4
2276#define reg_fste_w4_11_8_lsb 8
2277#define xd_p_reg_fste_w5_3_0 0xA351
2278#define reg_fste_w5_3_0_pos 4
2279#define reg_fste_w5_3_0_len 4
2280#define reg_fste_w5_3_0_lsb 0
2281#define xd_p_reg_fste_w5_11_4 0xA352
2282#define reg_fste_w5_11_4_pos 0
2283#define reg_fste_w5_11_4_len 8
2284#define reg_fste_w5_11_4_lsb 4
2285#define xd_p_reg_fste_w6_7_0 0xA353
2286#define reg_fste_w6_7_0_pos 0
2287#define reg_fste_w6_7_0_len 8
2288#define reg_fste_w6_7_0_lsb 0
2289#define xd_p_reg_fste_w6_11_8 0xA354
2290#define reg_fste_w6_11_8_pos 0
2291#define reg_fste_w6_11_8_len 4
2292#define reg_fste_w6_11_8_lsb 8
2293#define xd_p_reg_fste_w7_3_0 0xA354
2294#define reg_fste_w7_3_0_pos 4
2295#define reg_fste_w7_3_0_len 4
2296#define reg_fste_w7_3_0_lsb 0
2297#define xd_p_reg_fste_w7_11_4 0xA355
2298#define reg_fste_w7_11_4_pos 0
2299#define reg_fste_w7_11_4_len 8
2300#define reg_fste_w7_11_4_lsb 4
2301#define xd_p_reg_fste_w8_7_0 0xA356
2302#define reg_fste_w8_7_0_pos 0
2303#define reg_fste_w8_7_0_len 8
2304#define reg_fste_w8_7_0_lsb 0
2305#define xd_p_reg_fste_w8_11_8 0xA357
2306#define reg_fste_w8_11_8_pos 0
2307#define reg_fste_w8_11_8_len 4
2308#define reg_fste_w8_11_8_lsb 8
2309#define xd_p_reg_fste_w9_3_0 0xA357
2310#define reg_fste_w9_3_0_pos 4
2311#define reg_fste_w9_3_0_len 4
2312#define reg_fste_w9_3_0_lsb 0
2313#define xd_p_reg_fste_w9_11_4 0xA358
2314#define reg_fste_w9_11_4_pos 0
2315#define reg_fste_w9_11_4_len 8
2316#define reg_fste_w9_11_4_lsb 4
2317#define xd_p_reg_fste_wa_7_0 0xA359
2318#define reg_fste_wa_7_0_pos 0
2319#define reg_fste_wa_7_0_len 8
2320#define reg_fste_wa_7_0_lsb 0
2321#define xd_p_reg_fste_wa_11_8 0xA35A
2322#define reg_fste_wa_11_8_pos 0
2323#define reg_fste_wa_11_8_len 4
2324#define reg_fste_wa_11_8_lsb 8
2325#define xd_p_reg_fste_wb_3_0 0xA35A
2326#define reg_fste_wb_3_0_pos 4
2327#define reg_fste_wb_3_0_len 4
2328#define reg_fste_wb_3_0_lsb 0
2329#define xd_p_reg_fste_wb_11_4 0xA35B
2330#define reg_fste_wb_11_4_pos 0
2331#define reg_fste_wb_11_4_len 8
2332#define reg_fste_wb_11_4_lsb 4
2333#define xd_r_fd_fste_i_adj 0xA35C
2334#define fd_fste_i_adj_pos 0
2335#define fd_fste_i_adj_len 5
2336#define fd_fste_i_adj_lsb 0
2337#define xd_r_fd_fste_f_adj_7_0 0xA35D
2338#define fd_fste_f_adj_7_0_pos 0
2339#define fd_fste_f_adj_7_0_len 8
2340#define fd_fste_f_adj_7_0_lsb 0
2341#define xd_r_fd_fste_f_adj_15_8 0xA35E
2342#define fd_fste_f_adj_15_8_pos 0
2343#define fd_fste_f_adj_15_8_len 8
2344#define fd_fste_f_adj_15_8_lsb 8
2345#define xd_r_fd_fste_f_adj_19_16 0xA35F
2346#define fd_fste_f_adj_19_16_pos 0
2347#define fd_fste_f_adj_19_16_len 4
2348#define fd_fste_f_adj_19_16_lsb 16
2349#define xd_p_reg_feq_Leak_Bypass 0xA366
2350#define reg_feq_Leak_Bypass_pos 0
2351#define reg_feq_Leak_Bypass_len 1
2352#define reg_feq_Leak_Bypass_lsb 0
2353#define xd_p_reg_feq_Leak_Mneg1 0xA366
2354#define reg_feq_Leak_Mneg1_pos 1
2355#define reg_feq_Leak_Mneg1_len 3
2356#define reg_feq_Leak_Mneg1_lsb 0
2357#define xd_p_reg_feq_Leak_B_ShiftQ 0xA366
2358#define reg_feq_Leak_B_ShiftQ_pos 4
2359#define reg_feq_Leak_B_ShiftQ_len 4
2360#define reg_feq_Leak_B_ShiftQ_lsb 0
2361#define xd_p_reg_feq_Leak_B_Float0 0xA367
2362#define reg_feq_Leak_B_Float0_pos 0
2363#define reg_feq_Leak_B_Float0_len 8
2364#define reg_feq_Leak_B_Float0_lsb 0
2365#define xd_p_reg_feq_Leak_B_Float1 0xA368
2366#define reg_feq_Leak_B_Float1_pos 0
2367#define reg_feq_Leak_B_Float1_len 8
2368#define reg_feq_Leak_B_Float1_lsb 0
2369#define xd_p_reg_feq_Leak_B_Float2 0xA369
2370#define reg_feq_Leak_B_Float2_pos 0
2371#define reg_feq_Leak_B_Float2_len 8
2372#define reg_feq_Leak_B_Float2_lsb 0
2373#define xd_p_reg_feq_Leak_B_Float3 0xA36A
2374#define reg_feq_Leak_B_Float3_pos 0
2375#define reg_feq_Leak_B_Float3_len 8
2376#define reg_feq_Leak_B_Float3_lsb 0
2377#define xd_p_reg_feq_Leak_B_Float4 0xA36B
2378#define reg_feq_Leak_B_Float4_pos 0
2379#define reg_feq_Leak_B_Float4_len 8
2380#define reg_feq_Leak_B_Float4_lsb 0
2381#define xd_p_reg_feq_Leak_B_Float5 0xA36C
2382#define reg_feq_Leak_B_Float5_pos 0
2383#define reg_feq_Leak_B_Float5_len 8
2384#define reg_feq_Leak_B_Float5_lsb 0
2385#define xd_p_reg_feq_Leak_B_Float6 0xA36D
2386#define reg_feq_Leak_B_Float6_pos 0
2387#define reg_feq_Leak_B_Float6_len 8
2388#define reg_feq_Leak_B_Float6_lsb 0
2389#define xd_p_reg_feq_Leak_B_Float7 0xA36E
2390#define reg_feq_Leak_B_Float7_pos 0
2391#define reg_feq_Leak_B_Float7_len 8
2392#define reg_feq_Leak_B_Float7_lsb 0
2393#define xd_r_reg_feq_data_h2_7_0 0xA36F
2394#define reg_feq_data_h2_7_0_pos 0
2395#define reg_feq_data_h2_7_0_len 8
2396#define reg_feq_data_h2_7_0_lsb 0
2397#define xd_r_reg_feq_data_h2_9_8 0xA370
2398#define reg_feq_data_h2_9_8_pos 0
2399#define reg_feq_data_h2_9_8_len 2
2400#define reg_feq_data_h2_9_8_lsb 8
2401#define xd_p_reg_feq_leak_use_slice_tps 0xA371
2402#define reg_feq_leak_use_slice_tps_pos 0
2403#define reg_feq_leak_use_slice_tps_len 1
2404#define reg_feq_leak_use_slice_tps_lsb 0
2405#define xd_p_reg_feq_read_update 0xA371
2406#define reg_feq_read_update_pos 1
2407#define reg_feq_read_update_len 1
2408#define reg_feq_read_update_lsb 0
2409#define xd_p_reg_feq_data_vld 0xA371
2410#define reg_feq_data_vld_pos 2
2411#define reg_feq_data_vld_len 1
2412#define reg_feq_data_vld_lsb 0
2413#define xd_p_reg_feq_tone_idx_4_0 0xA371
2414#define reg_feq_tone_idx_4_0_pos 3
2415#define reg_feq_tone_idx_4_0_len 5
2416#define reg_feq_tone_idx_4_0_lsb 0
2417#define xd_p_reg_feq_tone_idx_12_5 0xA372
2418#define reg_feq_tone_idx_12_5_pos 0
2419#define reg_feq_tone_idx_12_5_len 8
2420#define reg_feq_tone_idx_12_5_lsb 5
2421#define xd_r_reg_feq_data_re_7_0 0xA373
2422#define reg_feq_data_re_7_0_pos 0
2423#define reg_feq_data_re_7_0_len 8
2424#define reg_feq_data_re_7_0_lsb 0
2425#define xd_r_reg_feq_data_re_10_8 0xA374
2426#define reg_feq_data_re_10_8_pos 0
2427#define reg_feq_data_re_10_8_len 3
2428#define reg_feq_data_re_10_8_lsb 8
2429#define xd_r_reg_feq_data_im_7_0 0xA375
2430#define reg_feq_data_im_7_0_pos 0
2431#define reg_feq_data_im_7_0_len 8
2432#define reg_feq_data_im_7_0_lsb 0
2433#define xd_r_reg_feq_data_im_10_8 0xA376
2434#define reg_feq_data_im_10_8_pos 0
2435#define reg_feq_data_im_10_8_len 3
2436#define reg_feq_data_im_10_8_lsb 8
2437#define xd_r_reg_feq_y_re 0xA377
2438#define reg_feq_y_re_pos 0
2439#define reg_feq_y_re_len 8
2440#define reg_feq_y_re_lsb 0
2441#define xd_r_reg_feq_y_im 0xA378
2442#define reg_feq_y_im_pos 0
2443#define reg_feq_y_im_len 8
2444#define reg_feq_y_im_lsb 0
2445#define xd_r_reg_feq_h_re_7_0 0xA379
2446#define reg_feq_h_re_7_0_pos 0
2447#define reg_feq_h_re_7_0_len 8
2448#define reg_feq_h_re_7_0_lsb 0
2449#define xd_r_reg_feq_h_re_8 0xA37A
2450#define reg_feq_h_re_8_pos 0
2451#define reg_feq_h_re_8_len 1
2452#define reg_feq_h_re_8_lsb 0
2453#define xd_r_reg_feq_h_im_7_0 0xA37B
2454#define reg_feq_h_im_7_0_pos 0
2455#define reg_feq_h_im_7_0_len 8
2456#define reg_feq_h_im_7_0_lsb 0
2457#define xd_r_reg_feq_h_im_8 0xA37C
2458#define reg_feq_h_im_8_pos 0
2459#define reg_feq_h_im_8_len 1
2460#define reg_feq_h_im_8_lsb 0
2461#define xd_p_fec_super_frm_unit_7_0 0xA380
2462#define fec_super_frm_unit_7_0_pos 0
2463#define fec_super_frm_unit_7_0_len 8
2464#define fec_super_frm_unit_7_0_lsb 0
2465#define xd_p_fec_super_frm_unit_15_8 0xA381
2466#define fec_super_frm_unit_15_8_pos 0
2467#define fec_super_frm_unit_15_8_len 8
2468#define fec_super_frm_unit_15_8_lsb 8
2469#define xd_r_fec_vtb_err_bit_cnt_7_0 0xA382
2470#define fec_vtb_err_bit_cnt_7_0_pos 0
2471#define fec_vtb_err_bit_cnt_7_0_len 8
2472#define fec_vtb_err_bit_cnt_7_0_lsb 0
2473#define xd_r_fec_vtb_err_bit_cnt_15_8 0xA383
2474#define fec_vtb_err_bit_cnt_15_8_pos 0
2475#define fec_vtb_err_bit_cnt_15_8_len 8
2476#define fec_vtb_err_bit_cnt_15_8_lsb 8
2477#define xd_r_fec_vtb_err_bit_cnt_23_16 0xA384
2478#define fec_vtb_err_bit_cnt_23_16_pos 0
2479#define fec_vtb_err_bit_cnt_23_16_len 8
2480#define fec_vtb_err_bit_cnt_23_16_lsb 16
2481#define xd_p_fec_rsd_packet_unit_7_0 0xA385
2482#define fec_rsd_packet_unit_7_0_pos 0
2483#define fec_rsd_packet_unit_7_0_len 8
2484#define fec_rsd_packet_unit_7_0_lsb 0
2485#define xd_p_fec_rsd_packet_unit_15_8 0xA386
2486#define fec_rsd_packet_unit_15_8_pos 0
2487#define fec_rsd_packet_unit_15_8_len 8
2488#define fec_rsd_packet_unit_15_8_lsb 8
2489#define xd_r_fec_rsd_bit_err_cnt_7_0 0xA387
2490#define fec_rsd_bit_err_cnt_7_0_pos 0
2491#define fec_rsd_bit_err_cnt_7_0_len 8
2492#define fec_rsd_bit_err_cnt_7_0_lsb 0
2493#define xd_r_fec_rsd_bit_err_cnt_15_8 0xA388
2494#define fec_rsd_bit_err_cnt_15_8_pos 0
2495#define fec_rsd_bit_err_cnt_15_8_len 8
2496#define fec_rsd_bit_err_cnt_15_8_lsb 8
2497#define xd_r_fec_rsd_bit_err_cnt_23_16 0xA389
2498#define fec_rsd_bit_err_cnt_23_16_pos 0
2499#define fec_rsd_bit_err_cnt_23_16_len 8
2500#define fec_rsd_bit_err_cnt_23_16_lsb 16
2501#define xd_r_fec_rsd_abort_packet_cnt_7_0 0xA38A
2502#define fec_rsd_abort_packet_cnt_7_0_pos 0
2503#define fec_rsd_abort_packet_cnt_7_0_len 8
2504#define fec_rsd_abort_packet_cnt_7_0_lsb 0
2505#define xd_r_fec_rsd_abort_packet_cnt_15_8 0xA38B
2506#define fec_rsd_abort_packet_cnt_15_8_pos 0
2507#define fec_rsd_abort_packet_cnt_15_8_len 8
2508#define fec_rsd_abort_packet_cnt_15_8_lsb 8
2509#define xd_p_fec_RSD_PKT_NUM_PER_UNIT_7_0 0xA38C
2510#define fec_RSD_PKT_NUM_PER_UNIT_7_0_pos 0
2511#define fec_RSD_PKT_NUM_PER_UNIT_7_0_len 8
2512#define fec_RSD_PKT_NUM_PER_UNIT_7_0_lsb 0
2513#define xd_p_fec_RSD_PKT_NUM_PER_UNIT_15_8 0xA38D
2514#define fec_RSD_PKT_NUM_PER_UNIT_15_8_pos 0
2515#define fec_RSD_PKT_NUM_PER_UNIT_15_8_len 8
2516#define fec_RSD_PKT_NUM_PER_UNIT_15_8_lsb 8
2517#define xd_p_fec_RS_TH_1_7_0 0xA38E
2518#define fec_RS_TH_1_7_0_pos 0
2519#define fec_RS_TH_1_7_0_len 8
2520#define fec_RS_TH_1_7_0_lsb 0
2521#define xd_p_fec_RS_TH_1_15_8 0xA38F
2522#define fec_RS_TH_1_15_8_pos 0
2523#define fec_RS_TH_1_15_8_len 8
2524#define fec_RS_TH_1_15_8_lsb 8
2525#define xd_p_fec_RS_TH_2 0xA390
2526#define fec_RS_TH_2_pos 0
2527#define fec_RS_TH_2_len 8
2528#define fec_RS_TH_2_lsb 0
2529#define xd_p_fec_mon_en 0xA391
2530#define fec_mon_en_pos 0
2531#define fec_mon_en_len 1
2532#define fec_mon_en_lsb 0
2533#define xd_p_reg_b8to47 0xA391
2534#define reg_b8to47_pos 1
2535#define reg_b8to47_len 1
2536#define reg_b8to47_lsb 0
2537#define xd_p_reg_rsd_sync_rep 0xA391
2538#define reg_rsd_sync_rep_pos 2
2539#define reg_rsd_sync_rep_len 1
2540#define reg_rsd_sync_rep_lsb 0
2541#define xd_p_fec_rsd_retrain_rst 0xA391
2542#define fec_rsd_retrain_rst_pos 3
2543#define fec_rsd_retrain_rst_len 1
2544#define fec_rsd_retrain_rst_lsb 0
2545#define xd_r_fec_rsd_ber_rdy 0xA391
2546#define fec_rsd_ber_rdy_pos 4
2547#define fec_rsd_ber_rdy_len 1
2548#define fec_rsd_ber_rdy_lsb 0
2549#define xd_p_fec_rsd_ber_rst 0xA391
2550#define fec_rsd_ber_rst_pos 5
2551#define fec_rsd_ber_rst_len 1
2552#define fec_rsd_ber_rst_lsb 0
2553#define xd_r_fec_vtb_ber_rdy 0xA391
2554#define fec_vtb_ber_rdy_pos 6
2555#define fec_vtb_ber_rdy_len 1
2556#define fec_vtb_ber_rdy_lsb 0
2557#define xd_p_fec_vtb_ber_rst 0xA391
2558#define fec_vtb_ber_rst_pos 7
2559#define fec_vtb_ber_rst_len 1
2560#define fec_vtb_ber_rst_lsb 0
2561#define xd_p_reg_vtb_clk40en 0xA392
2562#define reg_vtb_clk40en_pos 0
2563#define reg_vtb_clk40en_len 1
2564#define reg_vtb_clk40en_lsb 0
2565#define xd_p_fec_vtb_rsd_mon_en 0xA392
2566#define fec_vtb_rsd_mon_en_pos 1
2567#define fec_vtb_rsd_mon_en_len 1
2568#define fec_vtb_rsd_mon_en_lsb 0
2569#define xd_p_reg_fec_data_en 0xA392
2570#define reg_fec_data_en_pos 2
2571#define reg_fec_data_en_len 1
2572#define reg_fec_data_en_lsb 0
2573#define xd_p_fec_dummy_reg_2 0xA392
2574#define fec_dummy_reg_2_pos 3
2575#define fec_dummy_reg_2_len 3
2576#define fec_dummy_reg_2_lsb 0
2577#define xd_p_reg_sync_chk 0xA392
2578#define reg_sync_chk_pos 6
2579#define reg_sync_chk_len 1
2580#define reg_sync_chk_lsb 0
2581#define xd_p_fec_rsd_bypass 0xA392
2582#define fec_rsd_bypass_pos 7
2583#define fec_rsd_bypass_len 1
2584#define fec_rsd_bypass_lsb 0
2585#define xd_p_fec_sw_rst 0xA393
2586#define fec_sw_rst_pos 0
2587#define fec_sw_rst_len 1
2588#define fec_sw_rst_lsb 0
2589#define xd_r_fec_vtb_pm_crc 0xA394
2590#define fec_vtb_pm_crc_pos 0
2591#define fec_vtb_pm_crc_len 8
2592#define fec_vtb_pm_crc_lsb 0
2593#define xd_r_fec_vtb_tb_7_crc 0xA395
2594#define fec_vtb_tb_7_crc_pos 0
2595#define fec_vtb_tb_7_crc_len 8
2596#define fec_vtb_tb_7_crc_lsb 0
2597#define xd_r_fec_vtb_tb_6_crc 0xA396
2598#define fec_vtb_tb_6_crc_pos 0
2599#define fec_vtb_tb_6_crc_len 8
2600#define fec_vtb_tb_6_crc_lsb 0
2601#define xd_r_fec_vtb_tb_5_crc 0xA397
2602#define fec_vtb_tb_5_crc_pos 0
2603#define fec_vtb_tb_5_crc_len 8
2604#define fec_vtb_tb_5_crc_lsb 0
2605#define xd_r_fec_vtb_tb_4_crc 0xA398
2606#define fec_vtb_tb_4_crc_pos 0
2607#define fec_vtb_tb_4_crc_len 8
2608#define fec_vtb_tb_4_crc_lsb 0
2609#define xd_r_fec_vtb_tb_3_crc 0xA399
2610#define fec_vtb_tb_3_crc_pos 0
2611#define fec_vtb_tb_3_crc_len 8
2612#define fec_vtb_tb_3_crc_lsb 0
2613#define xd_r_fec_vtb_tb_2_crc 0xA39A
2614#define fec_vtb_tb_2_crc_pos 0
2615#define fec_vtb_tb_2_crc_len 8
2616#define fec_vtb_tb_2_crc_lsb 0
2617#define xd_r_fec_vtb_tb_1_crc 0xA39B
2618#define fec_vtb_tb_1_crc_pos 0
2619#define fec_vtb_tb_1_crc_len 8
2620#define fec_vtb_tb_1_crc_lsb 0
2621#define xd_r_fec_vtb_tb_0_crc 0xA39C
2622#define fec_vtb_tb_0_crc_pos 0
2623#define fec_vtb_tb_0_crc_len 8
2624#define fec_vtb_tb_0_crc_lsb 0
2625#define xd_r_fec_rsd_bank0_crc 0xA39D
2626#define fec_rsd_bank0_crc_pos 0
2627#define fec_rsd_bank0_crc_len 8
2628#define fec_rsd_bank0_crc_lsb 0
2629#define xd_r_fec_rsd_bank1_crc 0xA39E
2630#define fec_rsd_bank1_crc_pos 0
2631#define fec_rsd_bank1_crc_len 8
2632#define fec_rsd_bank1_crc_lsb 0
2633#define xd_r_fec_idi_vtb_crc 0xA39F
2634#define fec_idi_vtb_crc_pos 0
2635#define fec_idi_vtb_crc_len 8
2636#define fec_idi_vtb_crc_lsb 0
2637#define xd_g_reg_tpsd_txmod 0xA3C0
2638#define reg_tpsd_txmod_pos 0
2639#define reg_tpsd_txmod_len 2
2640#define reg_tpsd_txmod_lsb 0
2641#define xd_g_reg_tpsd_gi 0xA3C0
2642#define reg_tpsd_gi_pos 2
2643#define reg_tpsd_gi_len 2
2644#define reg_tpsd_gi_lsb 0
2645#define xd_g_reg_tpsd_hier 0xA3C0
2646#define reg_tpsd_hier_pos 4
2647#define reg_tpsd_hier_len 3
2648#define reg_tpsd_hier_lsb 0
2649#define xd_g_reg_bw 0xA3C1
2650#define reg_bw_pos 2
2651#define reg_bw_len 2
2652#define reg_bw_lsb 0
2653#define xd_g_reg_dec_pri 0xA3C1
2654#define reg_dec_pri_pos 4
2655#define reg_dec_pri_len 1
2656#define reg_dec_pri_lsb 0
2657#define xd_g_reg_tpsd_const 0xA3C1
2658#define reg_tpsd_const_pos 6
2659#define reg_tpsd_const_len 2
2660#define reg_tpsd_const_lsb 0
2661#define xd_g_reg_tpsd_hpcr 0xA3C2
2662#define reg_tpsd_hpcr_pos 0
2663#define reg_tpsd_hpcr_len 3
2664#define reg_tpsd_hpcr_lsb 0
2665#define xd_g_reg_tpsd_lpcr 0xA3C2
2666#define reg_tpsd_lpcr_pos 3
2667#define reg_tpsd_lpcr_len 3
2668#define reg_tpsd_lpcr_lsb 0
2669#define xd_g_reg_ofsm_clk 0xA3D0
2670#define reg_ofsm_clk_pos 0
2671#define reg_ofsm_clk_len 3
2672#define reg_ofsm_clk_lsb 0
2673#define xd_g_reg_fclk_cfg 0xA3D1
2674#define reg_fclk_cfg_pos 0
2675#define reg_fclk_cfg_len 1
2676#define reg_fclk_cfg_lsb 0
2677#define xd_g_reg_fclk_idi 0xA3D1
2678#define reg_fclk_idi_pos 1
2679#define reg_fclk_idi_len 1
2680#define reg_fclk_idi_lsb 0
2681#define xd_g_reg_fclk_odi 0xA3D1
2682#define reg_fclk_odi_pos 2
2683#define reg_fclk_odi_len 1
2684#define reg_fclk_odi_lsb 0
2685#define xd_g_reg_fclk_rsd 0xA3D1
2686#define reg_fclk_rsd_pos 3
2687#define reg_fclk_rsd_len 1
2688#define reg_fclk_rsd_lsb 0
2689#define xd_g_reg_fclk_vtb 0xA3D1
2690#define reg_fclk_vtb_pos 4
2691#define reg_fclk_vtb_len 1
2692#define reg_fclk_vtb_lsb 0
2693#define xd_g_reg_fclk_cste 0xA3D1
2694#define reg_fclk_cste_pos 5
2695#define reg_fclk_cste_len 1
2696#define reg_fclk_cste_lsb 0
2697#define xd_g_reg_fclk_mp2if 0xA3D1
2698#define reg_fclk_mp2if_pos 6
2699#define reg_fclk_mp2if_len 1
2700#define reg_fclk_mp2if_lsb 0
2701#define xd_I2C_i2c_m_slave_addr 0xA400
2702#define i2c_m_slave_addr_pos 0
2703#define i2c_m_slave_addr_len 8
2704#define i2c_m_slave_addr_lsb 0
2705#define xd_I2C_i2c_m_data1 0xA401
2706#define i2c_m_data1_pos 0
2707#define i2c_m_data1_len 8
2708#define i2c_m_data1_lsb 0
2709#define xd_I2C_i2c_m_data2 0xA402
2710#define i2c_m_data2_pos 0
2711#define i2c_m_data2_len 8
2712#define i2c_m_data2_lsb 0
2713#define xd_I2C_i2c_m_data3 0xA403
2714#define i2c_m_data3_pos 0
2715#define i2c_m_data3_len 8
2716#define i2c_m_data3_lsb 0
2717#define xd_I2C_i2c_m_data4 0xA404
2718#define i2c_m_data4_pos 0
2719#define i2c_m_data4_len 8
2720#define i2c_m_data4_lsb 0
2721#define xd_I2C_i2c_m_data5 0xA405
2722#define i2c_m_data5_pos 0
2723#define i2c_m_data5_len 8
2724#define i2c_m_data5_lsb 0
2725#define xd_I2C_i2c_m_data6 0xA406
2726#define i2c_m_data6_pos 0
2727#define i2c_m_data6_len 8
2728#define i2c_m_data6_lsb 0
2729#define xd_I2C_i2c_m_data7 0xA407
2730#define i2c_m_data7_pos 0
2731#define i2c_m_data7_len 8
2732#define i2c_m_data7_lsb 0
2733#define xd_I2C_i2c_m_data8 0xA408
2734#define i2c_m_data8_pos 0
2735#define i2c_m_data8_len 8
2736#define i2c_m_data8_lsb 0
2737#define xd_I2C_i2c_m_data9 0xA409
2738#define i2c_m_data9_pos 0
2739#define i2c_m_data9_len 8
2740#define i2c_m_data9_lsb 0
2741#define xd_I2C_i2c_m_data10 0xA40A
2742#define i2c_m_data10_pos 0
2743#define i2c_m_data10_len 8
2744#define i2c_m_data10_lsb 0
2745#define xd_I2C_i2c_m_data11 0xA40B
2746#define i2c_m_data11_pos 0
2747#define i2c_m_data11_len 8
2748#define i2c_m_data11_lsb 0
2749#define xd_I2C_i2c_m_cmd_rw 0xA40C
2750#define i2c_m_cmd_rw_pos 0
2751#define i2c_m_cmd_rw_len 1
2752#define i2c_m_cmd_rw_lsb 0
2753#define xd_I2C_i2c_m_cmd_rwlen 0xA40C
2754#define i2c_m_cmd_rwlen_pos 3
2755#define i2c_m_cmd_rwlen_len 4
2756#define i2c_m_cmd_rwlen_lsb 0
2757#define xd_I2C_i2c_m_status_cmd_exe 0xA40D
2758#define i2c_m_status_cmd_exe_pos 0
2759#define i2c_m_status_cmd_exe_len 1
2760#define i2c_m_status_cmd_exe_lsb 0
2761#define xd_I2C_i2c_m_status_wdat_done 0xA40D
2762#define i2c_m_status_wdat_done_pos 1
2763#define i2c_m_status_wdat_done_len 1
2764#define i2c_m_status_wdat_done_lsb 0
2765#define xd_I2C_i2c_m_status_wdat_fail 0xA40D
2766#define i2c_m_status_wdat_fail_pos 2
2767#define i2c_m_status_wdat_fail_len 1
2768#define i2c_m_status_wdat_fail_lsb 0
2769#define xd_I2C_i2c_m_period 0xA40E
2770#define i2c_m_period_pos 0
2771#define i2c_m_period_len 8
2772#define i2c_m_period_lsb 0
2773#define xd_I2C_i2c_m_reg_msb_lsb 0xA40F
2774#define i2c_m_reg_msb_lsb_pos 0
2775#define i2c_m_reg_msb_lsb_len 1
2776#define i2c_m_reg_msb_lsb_lsb 0
2777#define xd_I2C_reg_ofdm_rst 0xA40F
2778#define reg_ofdm_rst_pos 1
2779#define reg_ofdm_rst_len 1
2780#define reg_ofdm_rst_lsb 0
2781#define xd_I2C_reg_sample_period_on_tuner 0xA40F
2782#define reg_sample_period_on_tuner_pos 2
2783#define reg_sample_period_on_tuner_len 1
2784#define reg_sample_period_on_tuner_lsb 0
2785#define xd_I2C_reg_rst_i2c 0xA40F
2786#define reg_rst_i2c_pos 3
2787#define reg_rst_i2c_len 1
2788#define reg_rst_i2c_lsb 0
2789#define xd_I2C_reg_ofdm_rst_en 0xA40F
2790#define reg_ofdm_rst_en_pos 4
2791#define reg_ofdm_rst_en_len 1
2792#define reg_ofdm_rst_en_lsb 0
2793#define xd_I2C_reg_tuner_sda_sync_on 0xA40F
2794#define reg_tuner_sda_sync_on_pos 5
2795#define reg_tuner_sda_sync_on_len 1
2796#define reg_tuner_sda_sync_on_lsb 0
2797#define xd_p_mp2if_data_access_disable_ofsm 0xA500
2798#define mp2if_data_access_disable_ofsm_pos 0
2799#define mp2if_data_access_disable_ofsm_len 1
2800#define mp2if_data_access_disable_ofsm_lsb 0
2801#define xd_p_reg_mp2_sw_rst_ofsm 0xA500
2802#define reg_mp2_sw_rst_ofsm_pos 1
2803#define reg_mp2_sw_rst_ofsm_len 1
2804#define reg_mp2_sw_rst_ofsm_lsb 0
2805#define xd_p_reg_mp2if_clk_en_ofsm 0xA500
2806#define reg_mp2if_clk_en_ofsm_pos 2
2807#define reg_mp2if_clk_en_ofsm_len 1
2808#define reg_mp2if_clk_en_ofsm_lsb 0
2809#define xd_r_mp2if_sync_byte_locked 0xA500
2810#define mp2if_sync_byte_locked_pos 3
2811#define mp2if_sync_byte_locked_len 1
2812#define mp2if_sync_byte_locked_lsb 0
2813#define xd_r_mp2if_ts_not_188 0xA500
2814#define mp2if_ts_not_188_pos 4
2815#define mp2if_ts_not_188_len 1
2816#define mp2if_ts_not_188_lsb 0
2817#define xd_r_mp2if_psb_empty 0xA500
2818#define mp2if_psb_empty_pos 5
2819#define mp2if_psb_empty_len 1
2820#define mp2if_psb_empty_lsb 0
2821#define xd_r_mp2if_psb_overflow 0xA500
2822#define mp2if_psb_overflow_pos 6
2823#define mp2if_psb_overflow_len 1
2824#define mp2if_psb_overflow_lsb 0
2825#define xd_p_mp2if_keep_sf_sync_byte_ofsm 0xA500
2826#define mp2if_keep_sf_sync_byte_ofsm_pos 7
2827#define mp2if_keep_sf_sync_byte_ofsm_len 1
2828#define mp2if_keep_sf_sync_byte_ofsm_lsb 0
2829#define xd_r_mp2if_psb_mp2if_num_pkt 0xA501
2830#define mp2if_psb_mp2if_num_pkt_pos 0
2831#define mp2if_psb_mp2if_num_pkt_len 6
2832#define mp2if_psb_mp2if_num_pkt_lsb 0
2833#define xd_p_reg_mpeg_full_speed_ofsm 0xA501
2834#define reg_mpeg_full_speed_ofsm_pos 6
2835#define reg_mpeg_full_speed_ofsm_len 1
2836#define reg_mpeg_full_speed_ofsm_lsb 0
2837#define xd_p_mp2if_mpeg_ser_mode_ofsm 0xA501
2838#define mp2if_mpeg_ser_mode_ofsm_pos 7
2839#define mp2if_mpeg_ser_mode_ofsm_len 1
2840#define mp2if_mpeg_ser_mode_ofsm_lsb 0
2841#define xd_p_reg_sw_mon51 0xA600
2842#define reg_sw_mon51_pos 0
2843#define reg_sw_mon51_len 8
2844#define reg_sw_mon51_lsb 0
2845#define xd_p_reg_top_pcsel 0xA601
2846#define reg_top_pcsel_pos 0
2847#define reg_top_pcsel_len 1
2848#define reg_top_pcsel_lsb 0
2849#define xd_p_reg_top_rs232 0xA601
2850#define reg_top_rs232_pos 1
2851#define reg_top_rs232_len 1
2852#define reg_top_rs232_lsb 0
2853#define xd_p_reg_top_pcout 0xA601
2854#define reg_top_pcout_pos 2
2855#define reg_top_pcout_len 1
2856#define reg_top_pcout_lsb 0
2857#define xd_p_reg_top_debug 0xA601
2858#define reg_top_debug_pos 3
2859#define reg_top_debug_len 1
2860#define reg_top_debug_lsb 0
2861#define xd_p_reg_top_adcdly 0xA601
2862#define reg_top_adcdly_pos 4
2863#define reg_top_adcdly_len 2
2864#define reg_top_adcdly_lsb 0
2865#define xd_p_reg_top_pwrdw 0xA601
2866#define reg_top_pwrdw_pos 6
2867#define reg_top_pwrdw_len 1
2868#define reg_top_pwrdw_lsb 0
2869#define xd_p_reg_top_pwrdw_inv 0xA601
2870#define reg_top_pwrdw_inv_pos 7
2871#define reg_top_pwrdw_inv_len 1
2872#define reg_top_pwrdw_inv_lsb 0
2873#define xd_p_reg_top_int_inv 0xA602
2874#define reg_top_int_inv_pos 0
2875#define reg_top_int_inv_len 1
2876#define reg_top_int_inv_lsb 0
2877#define xd_p_reg_top_dio_sel 0xA602
2878#define reg_top_dio_sel_pos 1
2879#define reg_top_dio_sel_len 1
2880#define reg_top_dio_sel_lsb 0
2881#define xd_p_reg_top_gpioon0 0xA603
2882#define reg_top_gpioon0_pos 0
2883#define reg_top_gpioon0_len 1
2884#define reg_top_gpioon0_lsb 0
2885#define xd_p_reg_top_gpioon1 0xA603
2886#define reg_top_gpioon1_pos 1
2887#define reg_top_gpioon1_len 1
2888#define reg_top_gpioon1_lsb 0
2889#define xd_p_reg_top_gpioon2 0xA603
2890#define reg_top_gpioon2_pos 2
2891#define reg_top_gpioon2_len 1
2892#define reg_top_gpioon2_lsb 0
2893#define xd_p_reg_top_gpioon3 0xA603
2894#define reg_top_gpioon3_pos 3
2895#define reg_top_gpioon3_len 1
2896#define reg_top_gpioon3_lsb 0
2897#define xd_p_reg_top_lockon1 0xA603
2898#define reg_top_lockon1_pos 4
2899#define reg_top_lockon1_len 1
2900#define reg_top_lockon1_lsb 0
2901#define xd_p_reg_top_lockon2 0xA603
2902#define reg_top_lockon2_pos 5
2903#define reg_top_lockon2_len 1
2904#define reg_top_lockon2_lsb 0
2905#define xd_p_reg_top_gpioo0 0xA604
2906#define reg_top_gpioo0_pos 0
2907#define reg_top_gpioo0_len 1
2908#define reg_top_gpioo0_lsb 0
2909#define xd_p_reg_top_gpioo1 0xA604
2910#define reg_top_gpioo1_pos 1
2911#define reg_top_gpioo1_len 1
2912#define reg_top_gpioo1_lsb 0
2913#define xd_p_reg_top_gpioo2 0xA604
2914#define reg_top_gpioo2_pos 2
2915#define reg_top_gpioo2_len 1
2916#define reg_top_gpioo2_lsb 0
2917#define xd_p_reg_top_gpioo3 0xA604
2918#define reg_top_gpioo3_pos 3
2919#define reg_top_gpioo3_len 1
2920#define reg_top_gpioo3_lsb 0
2921#define xd_p_reg_top_lock1 0xA604
2922#define reg_top_lock1_pos 4
2923#define reg_top_lock1_len 1
2924#define reg_top_lock1_lsb 0
2925#define xd_p_reg_top_lock2 0xA604
2926#define reg_top_lock2_pos 5
2927#define reg_top_lock2_len 1
2928#define reg_top_lock2_lsb 0
2929#define xd_p_reg_top_gpioen0 0xA605
2930#define reg_top_gpioen0_pos 0
2931#define reg_top_gpioen0_len 1
2932#define reg_top_gpioen0_lsb 0
2933#define xd_p_reg_top_gpioen1 0xA605
2934#define reg_top_gpioen1_pos 1
2935#define reg_top_gpioen1_len 1
2936#define reg_top_gpioen1_lsb 0
2937#define xd_p_reg_top_gpioen2 0xA605
2938#define reg_top_gpioen2_pos 2
2939#define reg_top_gpioen2_len 1
2940#define reg_top_gpioen2_lsb 0
2941#define xd_p_reg_top_gpioen3 0xA605
2942#define reg_top_gpioen3_pos 3
2943#define reg_top_gpioen3_len 1
2944#define reg_top_gpioen3_lsb 0
2945#define xd_p_reg_top_locken1 0xA605
2946#define reg_top_locken1_pos 4
2947#define reg_top_locken1_len 1
2948#define reg_top_locken1_lsb 0
2949#define xd_p_reg_top_locken2 0xA605
2950#define reg_top_locken2_pos 5
2951#define reg_top_locken2_len 1
2952#define reg_top_locken2_lsb 0
2953#define xd_r_reg_top_gpioi0 0xA606
2954#define reg_top_gpioi0_pos 0
2955#define reg_top_gpioi0_len 1
2956#define reg_top_gpioi0_lsb 0
2957#define xd_r_reg_top_gpioi1 0xA606
2958#define reg_top_gpioi1_pos 1
2959#define reg_top_gpioi1_len 1
2960#define reg_top_gpioi1_lsb 0
2961#define xd_r_reg_top_gpioi2 0xA606
2962#define reg_top_gpioi2_pos 2
2963#define reg_top_gpioi2_len 1
2964#define reg_top_gpioi2_lsb 0
2965#define xd_r_reg_top_gpioi3 0xA606
2966#define reg_top_gpioi3_pos 3
2967#define reg_top_gpioi3_len 1
2968#define reg_top_gpioi3_lsb 0
2969#define xd_r_reg_top_locki1 0xA606
2970#define reg_top_locki1_pos 4
2971#define reg_top_locki1_len 1
2972#define reg_top_locki1_lsb 0
2973#define xd_r_reg_top_locki2 0xA606
2974#define reg_top_locki2_pos 5
2975#define reg_top_locki2_len 1
2976#define reg_top_locki2_lsb 0
2977#define xd_p_reg_dummy_7_0 0xA608
2978#define reg_dummy_7_0_pos 0
2979#define reg_dummy_7_0_len 8
2980#define reg_dummy_7_0_lsb 0
2981#define xd_p_reg_dummy_15_8 0xA609
2982#define reg_dummy_15_8_pos 0
2983#define reg_dummy_15_8_len 8
2984#define reg_dummy_15_8_lsb 8
2985#define xd_p_reg_dummy_23_16 0xA60A
2986#define reg_dummy_23_16_pos 0
2987#define reg_dummy_23_16_len 8
2988#define reg_dummy_23_16_lsb 16
2989#define xd_p_reg_dummy_31_24 0xA60B
2990#define reg_dummy_31_24_pos 0
2991#define reg_dummy_31_24_len 8
2992#define reg_dummy_31_24_lsb 24
2993#define xd_p_reg_dummy_39_32 0xA60C
2994#define reg_dummy_39_32_pos 0
2995#define reg_dummy_39_32_len 8
2996#define reg_dummy_39_32_lsb 32
2997#define xd_p_reg_dummy_47_40 0xA60D
2998#define reg_dummy_47_40_pos 0
2999#define reg_dummy_47_40_len 8
3000#define reg_dummy_47_40_lsb 40
3001#define xd_p_reg_dummy_55_48 0xA60E
3002#define reg_dummy_55_48_pos 0
3003#define reg_dummy_55_48_len 8
3004#define reg_dummy_55_48_lsb 48
3005#define xd_p_reg_dummy_63_56 0xA60F
3006#define reg_dummy_63_56_pos 0
3007#define reg_dummy_63_56_len 8
3008#define reg_dummy_63_56_lsb 56
3009#define xd_p_reg_dummy_71_64 0xA610
3010#define reg_dummy_71_64_pos 0
3011#define reg_dummy_71_64_len 8
3012#define reg_dummy_71_64_lsb 64
3013#define xd_p_reg_dummy_79_72 0xA611
3014#define reg_dummy_79_72_pos 0
3015#define reg_dummy_79_72_len 8
3016#define reg_dummy_79_72_lsb 72
3017#define xd_p_reg_dummy_87_80 0xA612
3018#define reg_dummy_87_80_pos 0
3019#define reg_dummy_87_80_len 8
3020#define reg_dummy_87_80_lsb 80
3021#define xd_p_reg_dummy_95_88 0xA613
3022#define reg_dummy_95_88_pos 0
3023#define reg_dummy_95_88_len 8
3024#define reg_dummy_95_88_lsb 88
3025#define xd_p_reg_dummy_103_96 0xA614
3026#define reg_dummy_103_96_pos 0
3027#define reg_dummy_103_96_len 8
3028#define reg_dummy_103_96_lsb 96
3029
3030#define xd_p_reg_unplug_flag 0xA615
3031#define reg_unplug_flag_pos 0
3032#define reg_unplug_flag_len 1
3033#define reg_unplug_flag_lsb 104
3034
3035#define xd_p_reg_api_dca_stes_request 0xA615
3036#define reg_api_dca_stes_request_pos 1
3037#define reg_api_dca_stes_request_len 1
3038#define reg_api_dca_stes_request_lsb 0
3039
3040#define xd_p_reg_back_to_dca_flag 0xA615
3041#define reg_back_to_dca_flag_pos 2
3042#define reg_back_to_dca_flag_len 1
3043#define reg_back_to_dca_flag_lsb 106
3044
3045#define xd_p_reg_api_retrain_request 0xA615
3046#define reg_api_retrain_request_pos 3
3047#define reg_api_retrain_request_len 1
3048#define reg_api_retrain_request_lsb 0
3049
3050#define xd_p_reg_Dyn_Top_Try_flag 0xA615
3051#define reg_Dyn_Top_Try_flag_pos 3
3052#define reg_Dyn_Top_Try_flag_len 1
3053#define reg_Dyn_Top_Try_flag_lsb 107
3054
3055#define xd_p_reg_API_retrain_freeze_flag 0xA615
3056#define reg_API_retrain_freeze_flag_pos 4
3057#define reg_API_retrain_freeze_flag_len 1
3058#define reg_API_retrain_freeze_flag_lsb 108
3059
3060#define xd_p_reg_dummy_111_104 0xA615
3061#define reg_dummy_111_104_pos 0
3062#define reg_dummy_111_104_len 8
3063#define reg_dummy_111_104_lsb 104
3064#define xd_p_reg_dummy_119_112 0xA616
3065#define reg_dummy_119_112_pos 0
3066#define reg_dummy_119_112_len 8
3067#define reg_dummy_119_112_lsb 112
3068#define xd_p_reg_dummy_127_120 0xA617
3069#define reg_dummy_127_120_pos 0
3070#define reg_dummy_127_120_len 8
3071#define reg_dummy_127_120_lsb 120
3072#define xd_p_reg_dummy_135_128 0xA618
3073#define reg_dummy_135_128_pos 0
3074#define reg_dummy_135_128_len 8
3075#define reg_dummy_135_128_lsb 128
3076
3077#define xd_p_reg_dummy_143_136 0xA619
3078#define reg_dummy_143_136_pos 0
3079#define reg_dummy_143_136_len 8
3080#define reg_dummy_143_136_lsb 136
3081
3082#define xd_p_reg_CCIR_dis 0xA619
3083#define reg_CCIR_dis_pos 0
3084#define reg_CCIR_dis_len 1
3085#define reg_CCIR_dis_lsb 0
3086
3087#define xd_p_reg_dummy_151_144 0xA61A
3088#define reg_dummy_151_144_pos 0
3089#define reg_dummy_151_144_len 8
3090#define reg_dummy_151_144_lsb 144
3091
3092#define xd_p_reg_dummy_159_152 0xA61B
3093#define reg_dummy_159_152_pos 0
3094#define reg_dummy_159_152_len 8
3095#define reg_dummy_159_152_lsb 152
3096
3097#define xd_p_reg_dummy_167_160 0xA61C
3098#define reg_dummy_167_160_pos 0
3099#define reg_dummy_167_160_len 8
3100#define reg_dummy_167_160_lsb 160
3101
3102#define xd_p_reg_dummy_175_168 0xA61D
3103#define reg_dummy_175_168_pos 0
3104#define reg_dummy_175_168_len 8
3105#define reg_dummy_175_168_lsb 168
3106
3107#define xd_p_reg_dummy_183_176 0xA61E
3108#define reg_dummy_183_176_pos 0
3109#define reg_dummy_183_176_len 8
3110#define reg_dummy_183_176_lsb 176
3111
3112#define xd_p_reg_ofsm_read_rbc_en 0xA61E
3113#define reg_ofsm_read_rbc_en_pos 2
3114#define reg_ofsm_read_rbc_en_len 1
3115#define reg_ofsm_read_rbc_en_lsb 0
3116
3117#define xd_p_reg_ce_filter_selection_dis 0xA61E
3118#define reg_ce_filter_selection_dis_pos 1
3119#define reg_ce_filter_selection_dis_len 1
3120#define reg_ce_filter_selection_dis_lsb 0
3121
3122#define xd_p_reg_OFSM_version_control_7_0 0xA611
3123#define reg_OFSM_version_control_7_0_pos 0
3124#define reg_OFSM_version_control_7_0_len 8
3125#define reg_OFSM_version_control_7_0_lsb 0
3126
3127#define xd_p_reg_OFSM_version_control_15_8 0xA61F
3128#define reg_OFSM_version_control_15_8_pos 0
3129#define reg_OFSM_version_control_15_8_len 8
3130#define reg_OFSM_version_control_15_8_lsb 0
3131
3132#define xd_p_reg_OFSM_version_control_23_16 0xA620
3133#define reg_OFSM_version_control_23_16_pos 0
3134#define reg_OFSM_version_control_23_16_len 8
3135#define reg_OFSM_version_control_23_16_lsb 0
3136
3137#define xd_p_reg_dummy_191_184 0xA61F
3138#define reg_dummy_191_184_pos 0
3139#define reg_dummy_191_184_len 8
3140#define reg_dummy_191_184_lsb 184
3141
3142#define xd_p_reg_dummy_199_192 0xA620
3143#define reg_dummy_199_192_pos 0
3144#define reg_dummy_199_192_len 8
3145#define reg_dummy_199_192_lsb 192
3146
3147#define xd_p_reg_ce_en 0xABC0
3148#define reg_ce_en_pos 0
3149#define reg_ce_en_len 1
3150#define reg_ce_en_lsb 0
3151#define xd_p_reg_ce_fctrl_en 0xABC0
3152#define reg_ce_fctrl_en_pos 1
3153#define reg_ce_fctrl_en_len 1
3154#define reg_ce_fctrl_en_lsb 0
3155#define xd_p_reg_ce_fste_tdi 0xABC0
3156#define reg_ce_fste_tdi_pos 2
3157#define reg_ce_fste_tdi_len 1
3158#define reg_ce_fste_tdi_lsb 0
3159#define xd_p_reg_ce_dynamic 0xABC0
3160#define reg_ce_dynamic_pos 3
3161#define reg_ce_dynamic_len 1
3162#define reg_ce_dynamic_lsb 0
3163#define xd_p_reg_ce_conf 0xABC0
3164#define reg_ce_conf_pos 4
3165#define reg_ce_conf_len 2
3166#define reg_ce_conf_lsb 0
3167#define xd_p_reg_ce_dyn12 0xABC0
3168#define reg_ce_dyn12_pos 6
3169#define reg_ce_dyn12_len 1
3170#define reg_ce_dyn12_lsb 0
3171#define xd_p_reg_ce_derot_en 0xABC0
3172#define reg_ce_derot_en_pos 7
3173#define reg_ce_derot_en_len 1
3174#define reg_ce_derot_en_lsb 0
3175#define xd_p_reg_ce_dynamic_th_7_0 0xABC1
3176#define reg_ce_dynamic_th_7_0_pos 0
3177#define reg_ce_dynamic_th_7_0_len 8
3178#define reg_ce_dynamic_th_7_0_lsb 0
3179#define xd_p_reg_ce_dynamic_th_15_8 0xABC2
3180#define reg_ce_dynamic_th_15_8_pos 0
3181#define reg_ce_dynamic_th_15_8_len 8
3182#define reg_ce_dynamic_th_15_8_lsb 8
3183#define xd_p_reg_ce_s1 0xABC3
3184#define reg_ce_s1_pos 0
3185#define reg_ce_s1_len 5
3186#define reg_ce_s1_lsb 0
3187#define xd_p_reg_ce_var_forced_value 0xABC3
3188#define reg_ce_var_forced_value_pos 5
3189#define reg_ce_var_forced_value_len 3
3190#define reg_ce_var_forced_value_lsb 0
3191#define xd_p_reg_ce_data_im_7_0 0xABC4
3192#define reg_ce_data_im_7_0_pos 0
3193#define reg_ce_data_im_7_0_len 8
3194#define reg_ce_data_im_7_0_lsb 0
3195#define xd_p_reg_ce_data_im_8 0xABC5
3196#define reg_ce_data_im_8_pos 0
3197#define reg_ce_data_im_8_len 1
3198#define reg_ce_data_im_8_lsb 0
3199#define xd_p_reg_ce_data_re_6_0 0xABC5
3200#define reg_ce_data_re_6_0_pos 1
3201#define reg_ce_data_re_6_0_len 7
3202#define reg_ce_data_re_6_0_lsb 0
3203#define xd_p_reg_ce_data_re_8_7 0xABC6
3204#define reg_ce_data_re_8_7_pos 0
3205#define reg_ce_data_re_8_7_len 2
3206#define reg_ce_data_re_8_7_lsb 7
3207#define xd_p_reg_ce_tone_5_0 0xABC6
3208#define reg_ce_tone_5_0_pos 2
3209#define reg_ce_tone_5_0_len 6
3210#define reg_ce_tone_5_0_lsb 0
3211#define xd_p_reg_ce_tone_12_6 0xABC7
3212#define reg_ce_tone_12_6_pos 0
3213#define reg_ce_tone_12_6_len 7
3214#define reg_ce_tone_12_6_lsb 6
3215#define xd_p_reg_ce_centroid_drift_th 0xABC8
3216#define reg_ce_centroid_drift_th_pos 0
3217#define reg_ce_centroid_drift_th_len 8
3218#define reg_ce_centroid_drift_th_lsb 0
3219#define xd_p_reg_ce_centroid_count_max 0xABC9
3220#define reg_ce_centroid_count_max_pos 0
3221#define reg_ce_centroid_count_max_len 4
3222#define reg_ce_centroid_count_max_lsb 0
3223#define xd_p_reg_ce_centroid_bias_inc_7_0 0xABCA
3224#define reg_ce_centroid_bias_inc_7_0_pos 0
3225#define reg_ce_centroid_bias_inc_7_0_len 8
3226#define reg_ce_centroid_bias_inc_7_0_lsb 0
3227#define xd_p_reg_ce_centroid_bias_inc_8 0xABCB
3228#define reg_ce_centroid_bias_inc_8_pos 0
3229#define reg_ce_centroid_bias_inc_8_len 1
3230#define reg_ce_centroid_bias_inc_8_lsb 0
3231#define xd_p_reg_ce_var_th0_7_0 0xABCC
3232#define reg_ce_var_th0_7_0_pos 0
3233#define reg_ce_var_th0_7_0_len 8
3234#define reg_ce_var_th0_7_0_lsb 0
3235#define xd_p_reg_ce_var_th0_15_8 0xABCD
3236#define reg_ce_var_th0_15_8_pos 0
3237#define reg_ce_var_th0_15_8_len 8
3238#define reg_ce_var_th0_15_8_lsb 8
3239#define xd_p_reg_ce_var_th1_7_0 0xABCE
3240#define reg_ce_var_th1_7_0_pos 0
3241#define reg_ce_var_th1_7_0_len 8
3242#define reg_ce_var_th1_7_0_lsb 0
3243#define xd_p_reg_ce_var_th1_15_8 0xABCF
3244#define reg_ce_var_th1_15_8_pos 0
3245#define reg_ce_var_th1_15_8_len 8
3246#define reg_ce_var_th1_15_8_lsb 8
3247#define xd_p_reg_ce_var_th2_7_0 0xABD0
3248#define reg_ce_var_th2_7_0_pos 0
3249#define reg_ce_var_th2_7_0_len 8
3250#define reg_ce_var_th2_7_0_lsb 0
3251#define xd_p_reg_ce_var_th2_15_8 0xABD1
3252#define reg_ce_var_th2_15_8_pos 0
3253#define reg_ce_var_th2_15_8_len 8
3254#define reg_ce_var_th2_15_8_lsb 8
3255#define xd_p_reg_ce_var_th3_7_0 0xABD2
3256#define reg_ce_var_th3_7_0_pos 0
3257#define reg_ce_var_th3_7_0_len 8
3258#define reg_ce_var_th3_7_0_lsb 0
3259#define xd_p_reg_ce_var_th3_15_8 0xABD3
3260#define reg_ce_var_th3_15_8_pos 0
3261#define reg_ce_var_th3_15_8_len 8
3262#define reg_ce_var_th3_15_8_lsb 8
3263#define xd_p_reg_ce_var_th4_7_0 0xABD4
3264#define reg_ce_var_th4_7_0_pos 0
3265#define reg_ce_var_th4_7_0_len 8
3266#define reg_ce_var_th4_7_0_lsb 0
3267#define xd_p_reg_ce_var_th4_15_8 0xABD5
3268#define reg_ce_var_th4_15_8_pos 0
3269#define reg_ce_var_th4_15_8_len 8
3270#define reg_ce_var_th4_15_8_lsb 8
3271#define xd_p_reg_ce_var_th5_7_0 0xABD6
3272#define reg_ce_var_th5_7_0_pos 0
3273#define reg_ce_var_th5_7_0_len 8
3274#define reg_ce_var_th5_7_0_lsb 0
3275#define xd_p_reg_ce_var_th5_15_8 0xABD7
3276#define reg_ce_var_th5_15_8_pos 0
3277#define reg_ce_var_th5_15_8_len 8
3278#define reg_ce_var_th5_15_8_lsb 8
3279#define xd_p_reg_ce_var_th6_7_0 0xABD8
3280#define reg_ce_var_th6_7_0_pos 0
3281#define reg_ce_var_th6_7_0_len 8
3282#define reg_ce_var_th6_7_0_lsb 0
3283#define xd_p_reg_ce_var_th6_15_8 0xABD9
3284#define reg_ce_var_th6_15_8_pos 0
3285#define reg_ce_var_th6_15_8_len 8
3286#define reg_ce_var_th6_15_8_lsb 8
3287#define xd_p_reg_ce_fctrl_reset 0xABDA
3288#define reg_ce_fctrl_reset_pos 0
3289#define reg_ce_fctrl_reset_len 1
3290#define reg_ce_fctrl_reset_lsb 0
3291#define xd_p_reg_ce_cent_auto_clr_en 0xABDA
3292#define reg_ce_cent_auto_clr_en_pos 1
3293#define reg_ce_cent_auto_clr_en_len 1
3294#define reg_ce_cent_auto_clr_en_lsb 0
3295#define xd_p_reg_ce_fctrl_auto_reset_en 0xABDA
3296#define reg_ce_fctrl_auto_reset_en_pos 2
3297#define reg_ce_fctrl_auto_reset_en_len 1
3298#define reg_ce_fctrl_auto_reset_en_lsb 0
3299#define xd_p_reg_ce_var_forced_en 0xABDA
3300#define reg_ce_var_forced_en_pos 3
3301#define reg_ce_var_forced_en_len 1
3302#define reg_ce_var_forced_en_lsb 0
3303#define xd_p_reg_ce_cent_forced_en 0xABDA
3304#define reg_ce_cent_forced_en_pos 4
3305#define reg_ce_cent_forced_en_len 1
3306#define reg_ce_cent_forced_en_lsb 0
3307#define xd_p_reg_ce_var_max 0xABDA
3308#define reg_ce_var_max_pos 5
3309#define reg_ce_var_max_len 3
3310#define reg_ce_var_max_lsb 0
3311#define xd_p_reg_ce_cent_forced_value_7_0 0xABDB
3312#define reg_ce_cent_forced_value_7_0_pos 0
3313#define reg_ce_cent_forced_value_7_0_len 8
3314#define reg_ce_cent_forced_value_7_0_lsb 0
3315#define xd_p_reg_ce_cent_forced_value_11_8 0xABDC
3316#define reg_ce_cent_forced_value_11_8_pos 0
3317#define reg_ce_cent_forced_value_11_8_len 4
3318#define reg_ce_cent_forced_value_11_8_lsb 8
3319#define xd_p_reg_ce_fctrl_rd 0xABDD
3320#define reg_ce_fctrl_rd_pos 0
3321#define reg_ce_fctrl_rd_len 1
3322#define reg_ce_fctrl_rd_lsb 0
3323#define xd_p_reg_ce_centroid_max_6_0 0xABDD
3324#define reg_ce_centroid_max_6_0_pos 1
3325#define reg_ce_centroid_max_6_0_len 7
3326#define reg_ce_centroid_max_6_0_lsb 0
3327#define xd_p_reg_ce_centroid_max_11_7 0xABDE
3328#define reg_ce_centroid_max_11_7_pos 0
3329#define reg_ce_centroid_max_11_7_len 5
3330#define reg_ce_centroid_max_11_7_lsb 7
3331#define xd_p_reg_ce_var 0xABDF
3332#define reg_ce_var_pos 0
3333#define reg_ce_var_len 3
3334#define reg_ce_var_lsb 0
3335#define xd_p_reg_ce_fctrl_rdy 0xABDF
3336#define reg_ce_fctrl_rdy_pos 3
3337#define reg_ce_fctrl_rdy_len 1
3338#define reg_ce_fctrl_rdy_lsb 0
3339#define xd_p_reg_ce_centroid_out_3_0 0xABDF
3340#define reg_ce_centroid_out_3_0_pos 4
3341#define reg_ce_centroid_out_3_0_len 4
3342#define reg_ce_centroid_out_3_0_lsb 0
3343#define xd_p_reg_ce_centroid_out_11_4 0xABE0
3344#define reg_ce_centroid_out_11_4_pos 0
3345#define reg_ce_centroid_out_11_4_len 8
3346#define reg_ce_centroid_out_11_4_lsb 4
3347#define xd_p_reg_ce_bias_7_0 0xABE1
3348#define reg_ce_bias_7_0_pos 0
3349#define reg_ce_bias_7_0_len 8
3350#define reg_ce_bias_7_0_lsb 0
3351#define xd_p_reg_ce_bias_11_8 0xABE2
3352#define reg_ce_bias_11_8_pos 0
3353#define reg_ce_bias_11_8_len 4
3354#define reg_ce_bias_11_8_lsb 8
3355#define xd_p_reg_ce_m1_3_0 0xABE2
3356#define reg_ce_m1_3_0_pos 4
3357#define reg_ce_m1_3_0_len 4
3358#define reg_ce_m1_3_0_lsb 0
3359#define xd_p_reg_ce_m1_11_4 0xABE3
3360#define reg_ce_m1_11_4_pos 0
3361#define reg_ce_m1_11_4_len 8
3362#define reg_ce_m1_11_4_lsb 4
3363#define xd_p_reg_ce_rh0_7_0 0xABE4
3364#define reg_ce_rh0_7_0_pos 0
3365#define reg_ce_rh0_7_0_len 8
3366#define reg_ce_rh0_7_0_lsb 0
3367#define xd_p_reg_ce_rh0_15_8 0xABE5
3368#define reg_ce_rh0_15_8_pos 0
3369#define reg_ce_rh0_15_8_len 8
3370#define reg_ce_rh0_15_8_lsb 8
3371#define xd_p_reg_ce_rh0_23_16 0xABE6
3372#define reg_ce_rh0_23_16_pos 0
3373#define reg_ce_rh0_23_16_len 8
3374#define reg_ce_rh0_23_16_lsb 16
3375#define xd_p_reg_ce_rh0_31_24 0xABE7
3376#define reg_ce_rh0_31_24_pos 0
3377#define reg_ce_rh0_31_24_len 8
3378#define reg_ce_rh0_31_24_lsb 24
3379#define xd_p_reg_ce_rh3_real_7_0 0xABE8
3380#define reg_ce_rh3_real_7_0_pos 0
3381#define reg_ce_rh3_real_7_0_len 8
3382#define reg_ce_rh3_real_7_0_lsb 0
3383#define xd_p_reg_ce_rh3_real_15_8 0xABE9
3384#define reg_ce_rh3_real_15_8_pos 0
3385#define reg_ce_rh3_real_15_8_len 8
3386#define reg_ce_rh3_real_15_8_lsb 8
3387#define xd_p_reg_ce_rh3_real_23_16 0xABEA
3388#define reg_ce_rh3_real_23_16_pos 0
3389#define reg_ce_rh3_real_23_16_len 8
3390#define reg_ce_rh3_real_23_16_lsb 16
3391#define xd_p_reg_ce_rh3_real_31_24 0xABEB
3392#define reg_ce_rh3_real_31_24_pos 0
3393#define reg_ce_rh3_real_31_24_len 8
3394#define reg_ce_rh3_real_31_24_lsb 24
3395#define xd_p_reg_ce_rh3_imag_7_0 0xABEC
3396#define reg_ce_rh3_imag_7_0_pos 0
3397#define reg_ce_rh3_imag_7_0_len 8
3398#define reg_ce_rh3_imag_7_0_lsb 0
3399#define xd_p_reg_ce_rh3_imag_15_8 0xABED
3400#define reg_ce_rh3_imag_15_8_pos 0
3401#define reg_ce_rh3_imag_15_8_len 8
3402#define reg_ce_rh3_imag_15_8_lsb 8
3403#define xd_p_reg_ce_rh3_imag_23_16 0xABEE
3404#define reg_ce_rh3_imag_23_16_pos 0
3405#define reg_ce_rh3_imag_23_16_len 8
3406#define reg_ce_rh3_imag_23_16_lsb 16
3407#define xd_p_reg_ce_rh3_imag_31_24 0xABEF
3408#define reg_ce_rh3_imag_31_24_pos 0
3409#define reg_ce_rh3_imag_31_24_len 8
3410#define reg_ce_rh3_imag_31_24_lsb 24
3411#define xd_p_reg_feq_fix_eh2_7_0 0xABF0
3412#define reg_feq_fix_eh2_7_0_pos 0
3413#define reg_feq_fix_eh2_7_0_len 8
3414#define reg_feq_fix_eh2_7_0_lsb 0
3415#define xd_p_reg_feq_fix_eh2_15_8 0xABF1
3416#define reg_feq_fix_eh2_15_8_pos 0
3417#define reg_feq_fix_eh2_15_8_len 8
3418#define reg_feq_fix_eh2_15_8_lsb 8
3419#define xd_p_reg_feq_fix_eh2_23_16 0xABF2
3420#define reg_feq_fix_eh2_23_16_pos 0
3421#define reg_feq_fix_eh2_23_16_len 8
3422#define reg_feq_fix_eh2_23_16_lsb 16
3423#define xd_p_reg_feq_fix_eh2_31_24 0xABF3
3424#define reg_feq_fix_eh2_31_24_pos 0
3425#define reg_feq_fix_eh2_31_24_len 8
3426#define reg_feq_fix_eh2_31_24_lsb 24
3427#define xd_p_reg_ce_m2_central_7_0 0xABF4
3428#define reg_ce_m2_central_7_0_pos 0
3429#define reg_ce_m2_central_7_0_len 8
3430#define reg_ce_m2_central_7_0_lsb 0
3431#define xd_p_reg_ce_m2_central_15_8 0xABF5
3432#define reg_ce_m2_central_15_8_pos 0
3433#define reg_ce_m2_central_15_8_len 8
3434#define reg_ce_m2_central_15_8_lsb 8
3435#define xd_p_reg_ce_fftshift 0xABF6
3436#define reg_ce_fftshift_pos 0
3437#define reg_ce_fftshift_len 4
3438#define reg_ce_fftshift_lsb 0
3439#define xd_p_reg_ce_fftshift1 0xABF6
3440#define reg_ce_fftshift1_pos 4
3441#define reg_ce_fftshift1_len 4
3442#define reg_ce_fftshift1_lsb 0
3443#define xd_p_reg_ce_fftshift2 0xABF7
3444#define reg_ce_fftshift2_pos 0
3445#define reg_ce_fftshift2_len 4
3446#define reg_ce_fftshift2_lsb 0
3447#define xd_p_reg_ce_top_mobile 0xABF7
3448#define reg_ce_top_mobile_pos 4
3449#define reg_ce_top_mobile_len 1
3450#define reg_ce_top_mobile_lsb 0
3451#define xd_p_reg_strong_sginal_detected 0xA2BC
3452#define reg_strong_sginal_detected_pos 2
3453#define reg_strong_sginal_detected_len 1
3454#define reg_strong_sginal_detected_lsb 0
3455
3456#define XD_MP2IF_BASE 0xB000
3457#define XD_MP2IF_CSR (0x00 + XD_MP2IF_BASE)
3458#define XD_MP2IF_DMX_CTRL (0x03 + XD_MP2IF_BASE)
3459#define XD_MP2IF_PID_IDX (0x04 + XD_MP2IF_BASE)
3460#define XD_MP2IF_PID_DATA_L (0x05 + XD_MP2IF_BASE)
3461#define XD_MP2IF_PID_DATA_H (0x06 + XD_MP2IF_BASE)
3462#define XD_MP2IF_MISC (0x07 + XD_MP2IF_BASE)
3463
3464extern struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d);
3465extern int af9005_read_ofdm_register(struct dvb_usb_device *d, u16 reg,
3466 u8 * value);
3467extern int af9005_read_ofdm_registers(struct dvb_usb_device *d, u16 reg,
3468 u8 * values, int len);
3469extern int af9005_write_ofdm_register(struct dvb_usb_device *d, u16 reg,
3470 u8 value);
3471extern int af9005_write_ofdm_registers(struct dvb_usb_device *d, u16 reg,
3472 u8 * values, int len);
3473extern int af9005_read_tuner_registers(struct dvb_usb_device *d, u16 reg,
3474 u8 addr, u8 * values, int len);
3475extern int af9005_write_tuner_registers(struct dvb_usb_device *d, u16 reg,
3476 u8 * values, int len);
3477extern int af9005_read_register_bits(struct dvb_usb_device *d, u16 reg,
3478 u8 pos, u8 len, u8 * value);
3479extern int af9005_write_register_bits(struct dvb_usb_device *d, u16 reg,
3480 u8 pos, u8 len, u8 value);
3481extern int af9005_send_command(struct dvb_usb_device *d, u8 command,
3482 u8 * wbuf, int wlen, u8 * rbuf, int rlen);
3483extern int af9005_read_eeprom(struct dvb_usb_device *d, u8 address,
3484 u8 * values, int len);
3485extern int af9005_tuner_attach(struct dvb_usb_adapter *adap);
3486extern int af9005_led_control(struct dvb_usb_device *d, int onoff);
3487
3488extern u8 regmask[8];
3489
3490/* remote control decoder */
3491extern int af9005_rc_decode(struct dvb_usb_device *d, u8 * data, int len,
3492 u32 * event, int *state);
3493extern struct dvb_usb_rc_key af9005_rc_keys[];
3494extern int af9005_rc_keys_size;
3495
3496#endif
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
index 403081689de1..951353153a3c 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
@@ -11,6 +11,7 @@
11 11
12/* Vendor IDs */ 12/* Vendor IDs */
13#define USB_VID_ADSTECH 0x06e1 13#define USB_VID_ADSTECH 0x06e1
14#define USB_VID_AFATECH 0x15a4
14#define USB_VID_ALCOR_MICRO 0x058f 15#define USB_VID_ALCOR_MICRO 0x058f
15#define USB_VID_ANCHOR 0x0547 16#define USB_VID_ANCHOR 0x0547
16#define USB_VID_ANUBIS_ELECTRONIC 0x10fd 17#define USB_VID_ANUBIS_ELECTRONIC 0x10fd
@@ -35,6 +36,7 @@
35#define USB_VID_MSI 0x0db0 36#define USB_VID_MSI 0x0db0
36#define USB_VID_OPERA1 0x695c 37#define USB_VID_OPERA1 0x695c
37#define USB_VID_PINNACLE 0x2304 38#define USB_VID_PINNACLE 0x2304
39#define USB_VID_TERRATEC 0x0ccd
38#define USB_VID_VISIONPLUS 0x13d3 40#define USB_VID_VISIONPLUS 0x13d3
39#define USB_VID_TWINHAN 0x1822 41#define USB_VID_TWINHAN 0x1822
40#define USB_VID_ULTIMA_ELECTRONIC 0x05d8 42#define USB_VID_ULTIMA_ELECTRONIC 0x05d8
@@ -44,6 +46,7 @@
44/* Product IDs */ 46/* Product IDs */
45#define USB_PID_ADSTECH_USB2_COLD 0xa333 47#define USB_PID_ADSTECH_USB2_COLD 0xa333
46#define USB_PID_ADSTECH_USB2_WARM 0xa334 48#define USB_PID_ADSTECH_USB2_WARM 0xa334
49#define USB_PID_AFATECH_AF9005 0x9020
47#define USB_PID_AVERMEDIA_DVBT_USB_COLD 0x0001 50#define USB_PID_AVERMEDIA_DVBT_USB_COLD 0x0001
48#define USB_PID_AVERMEDIA_DVBT_USB_WARM 0x0002 51#define USB_PID_AVERMEDIA_DVBT_USB_WARM 0x0002
49#define USB_PID_AVERMEDIA_DVBT_USB2_COLD 0xa800 52#define USB_PID_AVERMEDIA_DVBT_USB2_COLD 0xa800
@@ -69,6 +72,7 @@
69#define USB_PID_GRANDTEC_DVBT_USB_WARM 0x0fa1 72#define USB_PID_GRANDTEC_DVBT_USB_WARM 0x0fa1
70#define USB_PID_KWORLD_VSTREAM_COLD 0x17de 73#define USB_PID_KWORLD_VSTREAM_COLD 0x17de
71#define USB_PID_KWORLD_VSTREAM_WARM 0x17df 74#define USB_PID_KWORLD_VSTREAM_WARM 0x17df
75#define USB_PID_TERRATEC_CINERGY_T_USB_XE 0x0055
72#define USB_PID_TWINHAN_VP7041_COLD 0x3201 76#define USB_PID_TWINHAN_VP7041_COLD 0x3201
73#define USB_PID_TWINHAN_VP7041_WARM 0x3202 77#define USB_PID_TWINHAN_VP7041_WARM 0x3202
74#define USB_PID_TWINHAN_VP7020_COLD 0x3203 78#define USB_PID_TWINHAN_VP7020_COLD 0x3203
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 01:19:15 -0500