20 files changed, 3984 insertions, 19 deletions

diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index e7390dd0283d..4c68fdedfa10 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -347,6 +347,16 @@ config CPU_SUBTYPE_SH7723
         help
           Select SH7723 if you have an SH-MobileR2 CPU.
 
+config CPU_SUBTYPE_SH7724
+        bool "Support SH7724 processor"
+        select CPU_SH4A
+        select CPU_SHX2
+        select ARCH_SHMOBILE
+        select ARCH_SPARSEMEM_ENABLE
+        select SYS_SUPPORTS_CMT
+        help
+          Select SH7724 if you have an SH-MobileR2R CPU.
+
 config CPU_SUBTYPE_SH7763
         bool "Support SH7763 processor"
         select CPU_SH4A
@@ -495,6 +505,7 @@ config SH_PCLK_FREQ
                               CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
                               CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG    || \
                               CPU_SUBTYPE_SH7786
+        default "41666666" if CPU_SUBTYPE_SH7724
         default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
         default "66000000" if CPU_SUBTYPE_SH4_202
         default "50000000"
diff --git a/arch/sh/configs/sh7724_generic_defconfig b/arch/sh/configs/sh7724_generic_defconfig
new file mode 100644
index 000000000000..268d04ed8cdd
--- /dev/null
+++ b/arch/sh/configs/sh7724_generic_defconfig
@@ -0,0 +1,707 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30-rc2
+# Thu Apr 16 15:42:20 2009
+#
+CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+# CONFIG_SUPERH64 is not set
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_GENERIC_IRQ_PROBE=y
+# CONFIG_GENERIC_GPIO is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_SYS_SUPPORTS_CMT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_HAS_DEFAULT_IDLE=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+
+#
+# RCU Subsystem
+#
+# CONFIG_CLASSIC_RCU is not set
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_NS is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CPUSETS is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_RESOURCE_COUNTERS is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+# CONFIG_UID16 is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_FREEZER=y
+
+#
+# System type
+#
+CONFIG_CPU_SH4=y
+CONFIG_CPU_SH4A=y
+CONFIG_CPU_SHX2=y
+CONFIG_ARCH_SHMOBILE=y
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7201 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+# CONFIG_CPU_SUBTYPE_SH7751R is not set
+# CONFIG_CPU_SUBTYPE_SH7760 is not set
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+CONFIG_CPU_SUBTYPE_SH7724=y
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+# CONFIG_CPU_SUBTYPE_SH7786 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_MEMORY_START=0x08000000
+CONFIG_MEMORY_SIZE=0x04000000
+CONFIG_29BIT=y
+# CONFIG_X2TLB is not set
+CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+
+#
+# Memory hotplug is currently incompatible with Software Suspend
+#
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MIGRATION=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+
+#
+# Cache configuration
+#
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_SH_FPU=y
+# CONFIG_SH_STORE_QUEUES is not set
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_PTEA=y
+CONFIG_CPU_HAS_FPU=y
+
+#
+# Board support
+#
+
+#
+# Timer and clock configuration
+#
+CONFIG_SH_TMU=y
+CONFIG_SH_TIMER_CMT=y
+CONFIG_SH_TIMER_IRQ=16
+CONFIG_SH_PCLK_FREQ=41666666
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_SH_CPU_FREQ=y
+
+#
+# DMA support
+#
+# CONFIG_SH_DMA is not set
+
+#
+# Companion Chips
+#
+
+#
+# Additional SuperH Device Drivers
+#
+# CONFIG_HEARTBEAT is not set
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+CONFIG_KEXEC=y
+# CONFIG_CRASH_DUMP is not set
+CONFIG_KEXEC_JUMP=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00001000
+CONFIG_BOOT_LINK_OFFSET=0x00800000
+# CONFIG_CMDLINE_BOOL is not set
+
+#
+# Bus options
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options (EXPERIMENTAL)
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HIBERNATION=y
+CONFIG_PM_STD_PARTITION=""
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=6
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_UNIX98_PTYS is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_SH_MOBILE=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_REGULATOR is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SH=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+# CONFIG_UIO_PDRV is not set
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+# CONFIG_PROC_FS is not set
+# CONFIG_SYSFS is not set
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_SH_STANDARD_BIOS is not set
+# CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_MORE_COMPILE_OPTIONS is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
index efd511d0803a..8688a88303ee 100644
--- a/arch/sh/include/asm/device.h
+++ b/arch/sh/include/asm/device.h
@@ -10,3 +10,5 @@ struct platform_device;
 int platform_resource_setup_memory(struct platform_device *pdev,
                                    char *name, unsigned long memsize);
 
+void plat_early_device_setup(void);
+
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 1fd58b421438..005c962c8b1c 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
 
         /* SH-4A types */
         CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
-        CPU_SH7723, CPU_SHX3,
+        CPU_SH7723, CPU_SH7724, CPU_SHX3,
 
         /* SH4AL-DSP types */
         CPU_SH7343, CPU_SH7722, CPU_SH7366,
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index 749d1c434337..ccf1d999db6d 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -25,6 +25,24 @@
 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
       defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define FRQCR                   0xffc80000
+#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
+#define FRQCRA                  0xa4150000
+#define FRQCRB                  0xa4150004
+#define VCLKCR                  0xa4150048
+
+#define FCLKACR                 0xa4150008
+#define FCLKBCR                 0xa415000c
+#define FRQCR                   FRQCRA
+#define SCLKACR                 FCLKACR
+#define SCLKBCR                 FCLKBCR
+#define FCLKACR                 0xa4150008
+#define FCLKBCR                 0xa415000c
+#define IrDACLKCR               0xa4150018
+
+#define MSTPCR0                 0xa4150030
+#define MSTPCR1                 0xa4150034
+#define MSTPCR2                 0xa4150038
+
 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 #define FRQCR0                  0xffc80000
 #define FRQCR1                  0xffc80004
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
new file mode 100644
index 000000000000..34605c9e354d
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -0,0 +1,255 @@
+#ifndef __ASM_SH7724_H__
+#define __ASM_SH7724_H__
+
+enum {
+        /* PTA */
+        GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
+        GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
+
+        /* PTB */
+        GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
+        GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
+
+        /* PTC */
+        GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
+        GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
+
+        /* PTD */
+        GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
+        GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
+
+        /* PTE */
+        GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
+        GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
+
+        /* PTF */
+        GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
+        GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
+
+        /* PTG */
+                              GPIO_PTG5, GPIO_PTG4,
+        GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
+
+        /* PTH */
+        GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
+        GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
+
+        /* PTJ */
+        GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5,
+        GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
+
+        /* PTK */
+        GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
+        GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
+
+        /* PTL */
+        GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
+        GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
+
+        /* PTM */
+        GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
+        GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
+
+        /* PTN */
+        GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
+        GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
+
+        /* PTQ */
+        GPIO_PTQ7, GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
+        GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
+
+        /* PTR */
+        GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
+        GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
+
+        /* PTS */
+                   GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
+        GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
+
+        /* PTT */
+        GPIO_PTT7, GPIO_PTT6, GPIO_PTT5, GPIO_PTT4,
+        GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
+
+        /* PTU */
+        GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
+        GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
+
+        /* PTV */
+        GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
+        GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
+
+        /* PTW */
+        GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
+        GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
+
+        /* PTX */
+        GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
+        GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
+
+        /* PTY */
+        GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
+        GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
+
+        /* PTZ */
+        GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
+        GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
+
+        /* BSC (PTA/PTB/PTJ/PTQ/PTR/PTT) */
+        GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
+        GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
+        GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
+        GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
+        GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
+        GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9,  GPIO_FN_D8,
+        GPIO_FN_D7,  GPIO_FN_D6,  GPIO_FN_D5,  GPIO_FN_D4,
+        GPIO_FN_D3,  GPIO_FN_D2,  GPIO_FN_D1,  GPIO_FN_D0,
+        GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22,
+        GPIO_FN_CS6B_CE1B,  GPIO_FN_CS6A_CE2B,
+        GPIO_FN_CS5B_CE1A,  GPIO_FN_CS5A_CE2A,
+        GPIO_FN_WE3_ICIOWR, GPIO_FN_WE2_ICIORD,
+        GPIO_FN_IOIS16,     GPIO_FN_WAIT,
+        GPIO_FN_BS,
+
+        /* KEYSC (PTA/PTB)*/
+        GPIO_FN_KEYOUT5_IN5, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYIN4,
+        GPIO_FN_KEYIN3,  GPIO_FN_KEYIN2,  GPIO_FN_KEYIN1,  GPIO_FN_KEYIN0,
+        GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT2, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT0,
+
+        /* ATAPI (PTA/PTB/PTK/PTR/PTS/PTW) */
+        GPIO_FN_IDED15, GPIO_FN_IDED14, GPIO_FN_IDED13, GPIO_FN_IDED12,
+        GPIO_FN_IDED11, GPIO_FN_IDED10, GPIO_FN_IDED9,  GPIO_FN_IDED8,
+        GPIO_FN_IDED7,  GPIO_FN_IDED6,  GPIO_FN_IDED5,  GPIO_FN_IDED4,
+        GPIO_FN_IDED3,  GPIO_FN_IDED2,  GPIO_FN_IDED1,  GPIO_FN_IDED0,
+        GPIO_FN_IDEA2,     GPIO_FN_IDEA1,     GPIO_FN_IDEA0,  GPIO_FN_IDEIOWR,
+        GPIO_FN_IODREQ,    GPIO_FN_IDECS0,    GPIO_FN_IDECS1, GPIO_FN_IDEIORD,
+        GPIO_FN_DIRECTION, GPIO_FN_EXBUF_ENB, GPIO_FN_IDERST, GPIO_FN_IODACK,
+        GPIO_FN_IDEINT,    GPIO_FN_IDEIORDY,
+
+        /* TPU (PTB/PTR/PTS) */
+        GPIO_FN_TPUTO3, GPIO_FN_TPUTO2, GPIO_FN_TPUTO1, GPIO_FN_TPUTO0,
+        GPIO_FN_TPUTI3, GPIO_FN_TPUTI2,
+
+        /* LCDC (PTC/PTD/PTE/PTF/PTM/PTR) */
+        GPIO_FN_LCDD23, GPIO_FN_LCDD22, GPIO_FN_LCDD21, GPIO_FN_LCDD20,
+        GPIO_FN_LCDD19, GPIO_FN_LCDD18, GPIO_FN_LCDD17, GPIO_FN_LCDD16,
+        GPIO_FN_LCDD15, GPIO_FN_LCDD14, GPIO_FN_LCDD13, GPIO_FN_LCDD12,
+        GPIO_FN_LCDD11, GPIO_FN_LCDD10, GPIO_FN_LCDD9,  GPIO_FN_LCDD8,
+        GPIO_FN_LCDD7,  GPIO_FN_LCDD6,  GPIO_FN_LCDD5,  GPIO_FN_LCDD4,
+        GPIO_FN_LCDD3,  GPIO_FN_LCDD2,  GPIO_FN_LCDD1,  GPIO_FN_LCDD0,
+        GPIO_FN_LCDVSYN,  GPIO_FN_LCDDISP,  GPIO_FN_LCDRS,  GPIO_FN_LCDHSYN,
+        GPIO_FN_LCDCS,    GPIO_FN_LCDDON,   GPIO_FN_LCDDCK, GPIO_FN_LCDWR,
+        GPIO_FN_LCDVEPWC, GPIO_FN_LCDVCPWC, GPIO_FN_LCDRD,  GPIO_FN_LCDLCLK,
+
+        /* SCIF0 (PTF/PTM) */
+        GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD, GPIO_FN_SCIF0_SCK,
+
+        /* SCIF1 (PTL) */
+        GPIO_FN_SCIF1_SCK, GPIO_FN_SCIF1_RXD, GPIO_FN_SCIF1_TXD,
+
+        /* SCIF2 (PTE/PTF/PTN) with LCDC, VOU */
+        GPIO_FN_SCIF2_L_TXD, GPIO_FN_SCIF2_L_SCK, GPIO_FN_SCIF2_L_RXD,
+        GPIO_FN_SCIF2_V_TXD, GPIO_FN_SCIF2_V_SCK, GPIO_FN_SCIF2_V_RXD,
+
+        /* SCIF3 (PTL/PTN/PTZ) with VOU, IRQ */
+        GPIO_FN_SCIF3_V_SCK, GPIO_FN_SCIF3_V_RXD, GPIO_FN_SCIF3_V_TXD,
+        GPIO_FN_SCIF3_V_CTS, GPIO_FN_SCIF3_V_RTS,
+        GPIO_FN_SCIF3_I_SCK, GPIO_FN_SCIF3_I_RXD, GPIO_FN_SCIF3_I_TXD,
+        GPIO_FN_SCIF3_I_CTS, GPIO_FN_SCIF3_I_RTS,
+
+        /* SCIF4 (PTE) */
+        GPIO_FN_SCIF4_SCK, GPIO_FN_SCIF4_RXD, GPIO_FN_SCIF4_TXD,
+
+        /* SCIF5 (PTS) */
+        GPIO_FN_SCIF5_SCK, GPIO_FN_SCIF5_RXD, GPIO_FN_SCIF5_TXD,
+
+        /* FSI (PTE/PTU/PTV) */
+        GPIO_FN_FSIMCKB,   GPIO_FN_FSIMCKA,    GPIO_FN_FSIOASD,
+        GPIO_FN_FSIIABCK,  GPIO_FN_FSIIALRCK,  GPIO_FN_FSIOABCK,
+        GPIO_FN_FSIOALRCK, GPIO_FN_CLKAUDIOAO, GPIO_FN_FSIIBSD,
+        GPIO_FN_FSIOBSD,   GPIO_FN_FSIIBBCK,   GPIO_FN_FSIIBLRCK,
+        GPIO_FN_FSIOBBCK,  GPIO_FN_FSIOBLRCK,  GPIO_FN_CLKAUDIOBO,
+        GPIO_FN_FSIIASD,
+
+        /* AUD (PTG) */
+        GPIO_FN_AUDCK,   GPIO_FN_AUDSYNC, GPIO_FN_AUDATA3,
+        GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
+
+        /* VIO (PTS) (common?) */
+        GPIO_FN_VIO_CKO,
+
+        /* VIO0 (PTH/PTK) */
+        GPIO_FN_VIO0_D15, GPIO_FN_VIO0_D14, GPIO_FN_VIO0_D13, GPIO_FN_VIO0_D12,
+        GPIO_FN_VIO0_D11, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D9,  GPIO_FN_VIO0_D8,
+        GPIO_FN_VIO0_D7,  GPIO_FN_VIO0_D6,  GPIO_FN_VIO0_D5,  GPIO_FN_VIO0_D4,
+        GPIO_FN_VIO0_D3,  GPIO_FN_VIO0_D2,  GPIO_FN_VIO0_D1,  GPIO_FN_VIO0_D0,
+        GPIO_FN_VIO0_VD,  GPIO_FN_VIO0_CLK,
+        GPIO_FN_VIO0_FLD, GPIO_FN_VIO0_HD,
+
+        /* VIO1 (PTK/PTS) */
+        GPIO_FN_VIO1_D7,  GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D5, GPIO_FN_VIO1_D4,
+        GPIO_FN_VIO1_D3,  GPIO_FN_VIO1_D2, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D0,
+        GPIO_FN_VIO1_FLD, GPIO_FN_VIO1_HD, GPIO_FN_VIO1_VD, GPIO_FN_VIO1_CLK,
+
+        /* Eth  (PTL/PTN/PTX) */
+        GPIO_FN_RMII_RXD0,    GPIO_FN_RMII_RXD1,
+        GPIO_FN_RMII_TXD0,    GPIO_FN_RMII_TXD1,
+        GPIO_FN_RMII_REF_CLK, GPIO_FN_RMII_TX_EN,
+        GPIO_FN_RMII_RX_ER,   GPIO_FN_RMII_CRS_DV,
+        GPIO_FN_LNKSTA,       GPIO_FN_MDIO,
+        GPIO_FN_MDC,
+
+        /* System (PTJ) */
+        GPIO_FN_PDSTATUS, GPIO_FN_STATUS2, GPIO_FN_STATUS0,
+
+        /* VOU (PTL/PTM/PTN*/
+        GPIO_FN_DV_D15,  GPIO_FN_DV_D14, GPIO_FN_DV_D13,   GPIO_FN_DV_D12,
+        GPIO_FN_DV_D11,  GPIO_FN_DV_D10, GPIO_FN_DV_D9,    GPIO_FN_DV_D8,
+        GPIO_FN_DV_D7,   GPIO_FN_DV_D6,  GPIO_FN_DV_D5,    GPIO_FN_DV_D4,
+        GPIO_FN_DV_D3,   GPIO_FN_DV_D2,  GPIO_FN_DV_D1,    GPIO_FN_DV_D0,
+        GPIO_FN_DV_CLKI, GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
+
+        /* MSIOF0 (PTL/PTM) */
+        GPIO_FN_MSIOF0_RXD,   GPIO_FN_MSIOF0_TXD,
+        GPIO_FN_MSIOF0_MCK,   GPIO_FN_MSIOF0_TSCK,
+        GPIO_FN_MSIOF0_SS1,   GPIO_FN_MSIOF0_SS2,
+        GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_RSCK,
+        GPIO_FN_MSIOF0_RSYNC,
+
+        /* MSIOF1 (PTV) */
+        GPIO_FN_MSIOF1_RXD,   GPIO_FN_MSIOF1_TXD,
+        GPIO_FN_MSIOF1_MCK,   GPIO_FN_MSIOF1_TSCK,
+        GPIO_FN_MSIOF1_SS1,   GPIO_FN_MSIOF1_SS2,
+        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_MSIOF1_RSCK,
+        GPIO_FN_MSIOF1_RSYNC,
+
+        /* DMAC (PTU/PTX) */
+        GPIO_FN_DMAC_DACK0, GPIO_FN_DMAC_DREQ0,
+        GPIO_FN_DMAC_DACK1, GPIO_FN_DMAC_DREQ1,
+
+        /* SDHI0 (PTY) */
+        GPIO_FN_SDHI0CD, GPIO_FN_SDHI0WP, GPIO_FN_SDHI0CMD, GPIO_FN_SDHI0CLK,
+        GPIO_FN_SDHI0D3, GPIO_FN_SDHI0D2, GPIO_FN_SDHI0D1,  GPIO_FN_SDHI0D0,
+
+        /* SDHI1 (PTW) */
+        GPIO_FN_SDHI1CD, GPIO_FN_SDHI1WP, GPIO_FN_SDHI1CMD, GPIO_FN_SDHI1CLK,
+        GPIO_FN_SDHI1D3, GPIO_FN_SDHI1D2, GPIO_FN_SDHI1D1,  GPIO_FN_SDHI1D0,
+
+        /* MMC (PTW/PTX)*/
+        GPIO_FN_MMC_D7,  GPIO_FN_MMC_D6,  GPIO_FN_MMC_D5, GPIO_FN_MMC_D4,
+        GPIO_FN_MMC_D3,  GPIO_FN_MMC_D2,  GPIO_FN_MMC_D1, GPIO_FN_MMC_D0,
+        GPIO_FN_MMC_CLK, GPIO_FN_MMC_CMD,
+
+        /* IrDA (PTX) */
+        GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN,
+
+        /* TSIF (PTX) */
+        GPIO_FN_TSIF_TS0_SDAT, GPIO_FN_TSIF_TS0_SCK,
+        GPIO_FN_TSIF_TS0_SDEN, GPIO_FN_TSIF_TS0_SPSYNC,
+
+        /* IRQ (PTZ) */
+        GPIO_FN_INTC_IRQ7, GPIO_FN_INTC_IRQ6, GPIO_FN_INTC_IRQ5,
+        GPIO_FN_INTC_IRQ4, GPIO_FN_INTC_IRQ3, GPIO_FN_INTC_IRQ2,
+        GPIO_FN_INTC_IRQ1, GPIO_FN_INTC_IRQ0,
+};
+
+#endif /* __ASM_SH7724_H__ */
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 91e3677ae09d..973ff831c8a8 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -156,6 +156,12 @@ int __init detect_cpu_and_cache_system(void)
                         break;
                 }
                 break;
+        case 0x300b:
+                boot_cpu_data.type = CPU_SH7724;
+                boot_cpu_data.icache.ways = 4;
+                boot_cpu_data.dcache.ways = 4;
+                boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_FPU;
+                break;
         case 0x4000:    /* 1st cut */
         case 0x4001:    /* 2nd cut */
                 boot_cpu_data.type = CPU_SHX3;
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 1a92361feeb9..afd6fba47849 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7786)	+= setup-sh7786.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7343)        += setup-sh7343.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7722)        += setup-sh7722.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7723)        += setup-sh7723.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7724)        += setup-sh7724.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7366)        += setup-sh7366.o
 obj-$(CONFIG_CPU_SUBTYPE_SHX3)          += setup-shx3.o
 
@@ -26,12 +27,14 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7786)	:= clock-sh7786.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7343)      := clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7722)      := clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7723)      := clock-sh7722.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7724)      := clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7366)      := clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SHX3)        := clock-shx3.o
 
 # Pinmux setup
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7722)     := pinmux-sh7722.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7723)     := pinmux-sh7723.o
+pinmux-$(CONFIG_CPU_SUBTYPE_SH7724)     := pinmux-sh7724.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7785)     := pinmux-sh7785.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7786)     := pinmux-sh7786.o
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 0e174af21874..1ccdfc561fef 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -130,6 +130,12 @@ static void adjust_clocks(int originate, int *l, unsigned long v[],
  * is quite simple..
  */
 
+#if defined(CONFIG_CPU_SUBTYPE_SH7724)
+#define STCPLL(frqcr) ((((frqcr >> 24) & 0x3f) + 1) * 2)
+#else
+#define STCPLL(frqcr) (((frqcr >> 24) & 0x1f) + 1)
+#endif
+
 /*
  * Instead of having two separate multipliers/divisors set, like this:
  *
@@ -139,13 +145,17 @@ static void adjust_clocks(int originate, int *l, unsigned long v[],
  * I created the divisors2 array, which is used to calculate rate like
  *   rate = parent * 2 / divisors2[ divisor ];
 */
+#if defined(CONFIG_CPU_SUBTYPE_SH7724)
+static int divisors2[] = { 4, 1, 8, 12, 16, 24, 32, 1, 48, 64, 72, 96, 1, 144 };
+#else
 static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
+#endif
 
 static void master_clk_recalc(struct clk *clk)
 {
         unsigned frqcr = ctrl_inl(FRQCR);
 
-        clk->rate = CONFIG_SH_PCLK_FREQ * (((frqcr >> 24) & 0x1f) + 1);
+        clk->rate = CONFIG_SH_PCLK_FREQ * STCPLL(frqcr);
 }
 
 static void master_clk_init(struct clk *clk)
@@ -161,13 +171,30 @@ static void module_clk_recalc(struct clk *clk)
 {
         unsigned long frqcr = ctrl_inl(FRQCR);
 
-        clk->rate = clk->parent->rate / (((frqcr >> 24) & 0x1f) + 1);
+        clk->rate = clk->parent->rate / STCPLL(frqcr);
 }
 
+#if defined(CONFIG_CPU_SUBTYPE_SH7724)
+#define MASTERDIVS      { 12, 16, 24, 30, 32, 36, 48 }
+#define STCMASK         0x3f
+#define DIVCALC(div)    (div/2-1)
+#define FRQCRKICK       0x80000000
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+#define MASTERDIVS      { 6, 8, 12, 16 }
+#define STCMASK         0x1f
+#define DIVCALC(div)    (div-1)
+#define FRQCRKICK       0x00000000
+#else
+#define MASTERDIVS      { 2, 3, 4, 6, 8, 16 }
+#define STCMASK         0x1f
+#define DIVCALC(div)    (div-1)
+#define FRQCRKICK       0x00000000
+#endif
+
 static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
 {
         int div = rate / clk->rate;
-        int master_divs[] = { 2, 3, 4, 6, 8, 16 };
+        int master_divs[] = MASTERDIVS;
         int index;
         unsigned long frqcr;
 
@@ -180,8 +207,9 @@ static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
         div = master_divs[index - 1];
 
         frqcr = ctrl_inl(FRQCR);
-        frqcr &= ~(0xF << 24);
-        frqcr |= ( (div-1) << 24);
+        frqcr &= ~(STCMASK << 24);
+        frqcr |= (DIVCALC(div) << 24);
+        frqcr |= FRQCRKICK;
         ctrl_outl(frqcr, FRQCR);
 
         return 0;
@@ -377,6 +405,7 @@ static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
         /* clear FRQCR bits */
         frqcr &= ~(ctx.mask << ctx.shift);
         frqcr |= div << ctx.shift;
+        frqcr |= FRQCRKICK;
 
         /* ...and perform actual change */
         ctrl_outl(frqcr, FRQCR);
@@ -542,8 +571,8 @@ static struct clk sh7722_r_clock = {
         .flags = CLK_RATE_PROPAGATES,
 };
 
-#ifndef CONFIG_CPU_SUBTYPE_SH7343
-
+#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
+    !defined(CONFIG_CPU_SUBTYPE_SH7724)
 /*
  * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
  * methods of clk_ops determine which register they should access by
@@ -560,15 +589,16 @@ static struct clk sh7722_siu_b_clock = {
         .arch_flags = SCLKBCR,
         .ops = &sh7722_siu_clk_ops,
 };
+#endif /* CONFIG_CPU_SUBTYPE_SH7343, SH7724 */
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7722)
+#if defined(CONFIG_CPU_SUBTYPE_SH7722) ||\
+    defined(CONFIG_CPU_SUBTYPE_SH7724)
 static struct clk sh7722_irda_clock = {
         .name = "irda_clk",
         .arch_flags = IrDACLKCR,
         .ops = &sh7722_siu_clk_ops,
 };
 #endif
-#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
 
 static struct clk sh7722_video_clock = {
         .name = "video_clk",
@@ -715,6 +745,61 @@ static struct clk sh7722_mstpcr_clocks[] = {
         MSTPCR("vpu0", "bus_clk", 2, 1),
         MSTPCR("lcdc0", "bus_clk", 2, 0),
 #endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7724)
+        /* See Datasheet : Overview -> Block Diagram */
+        MSTPCR("tlb0", "cpu_clk", 0, 31),
+        MSTPCR("ic0", "cpu_clk", 0, 30),
+        MSTPCR("oc0", "cpu_clk", 0, 29),
+        MSTPCR("rs0", "bus_clk", 0, 28),
+        MSTPCR("ilmem0", "cpu_clk", 0, 27),
+        MSTPCR("l2c0", "sh_clk", 0, 26),
+        MSTPCR("fpu0", "cpu_clk", 0, 24),
+        MSTPCR("intc0", "peripheral_clk", 0, 22),
+        MSTPCR("dmac0", "bus_clk", 0, 21),
+        MSTPCR("sh0", "sh_clk", 0, 20),
+        MSTPCR("hudi0", "peripheral_clk", 0, 19),
+        MSTPCR("ubc0", "cpu_clk", 0, 17),
+        MSTPCR("tmu0", "peripheral_clk", 0, 15),
+        MSTPCR("cmt0", "r_clk", 0, 14),
+        MSTPCR("rwdt0", "r_clk", 0, 13),
+        MSTPCR("dmac1", "bus_clk", 0, 12),
+        MSTPCR("tmu1", "peripheral_clk", 0, 10),
+        MSTPCR("scif0", "peripheral_clk", 0, 9),
+        MSTPCR("scif1", "peripheral_clk", 0, 8),
+        MSTPCR("scif2", "peripheral_clk", 0, 7),
+        MSTPCR("scif3", "bus_clk", 0, 6),
+        MSTPCR("scif4", "bus_clk", 0, 5),
+        MSTPCR("scif5", "bus_clk", 0, 4),
+        MSTPCR("msiof0", "bus_clk", 0, 2),
+        MSTPCR("msiof1", "bus_clk", 0, 1),
+        MSTPCR("keysc0", "r_clk", 1, 12),
+        MSTPCR("rtc0", "r_clk", 1, 11),
+        MSTPCR("i2c0", "peripheral_clk", 1, 9),
+        MSTPCR("i2c1", "peripheral_clk", 1, 8),
+        MSTPCR("mmc0", "bus_clk", 2, 29),
+        MSTPCR("eth0", "bus_clk", 2, 28),
+        MSTPCR("atapi0", "bus_clk", 2, 26),
+        MSTPCR("tpu0", "bus_clk", 2, 25),
+        MSTPCR("irda0", "peripheral_clk", 2, 24),
+        MSTPCR("tsif0", "bus_clk", 2, 22),
+        MSTPCR("usb1", "bus_clk", 2, 21),
+        MSTPCR("usb0", "bus_clk", 2, 20),
+        MSTPCR("2dg0", "bus_clk", 2, 19),
+        MSTPCR("sdhi0", "bus_clk", 2, 18),
+        MSTPCR("sdhi1", "bus_clk", 2, 17),
+        MSTPCR("veu1", "bus_clk", 2, 15),
+        MSTPCR("ceu1", "bus_clk", 2, 13),
+        MSTPCR("beu1", "bus_clk", 2, 12),
+        MSTPCR("2ddmac0", "sh_clk", 2, 10),
+        MSTPCR("spu0", "bus_clk", 2, 9),
+        MSTPCR("jpu0", "bus_clk", 2, 6),
+        MSTPCR("vou0", "bus_clk", 2, 5),
+        MSTPCR("beu0", "bus_clk", 2, 4),
+        MSTPCR("ceu0", "bus_clk", 2, 3),
+        MSTPCR("veu0", "bus_clk", 2, 2),
+        MSTPCR("vpu0", "bus_clk", 2, 1),
+        MSTPCR("lcdc0", "bus_clk", 2, 0),
+#endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7343)
         MSTPCR("uram0", "umem_clk", 0, 28),
         MSTPCR("xymem0", "bus_clk", 0, 26),
@@ -786,12 +871,15 @@ static struct clk *sh7722_clocks[] = {
         &sh7722_sh_clock,
         &sh7722_peripheral_clock,
         &sh7722_sdram_clock,
-#ifndef CONFIG_CPU_SUBTYPE_SH7343
+#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
+    !defined(CONFIG_CPU_SUBTYPE_SH7724)
         &sh7722_siu_a_clock,
         &sh7722_siu_b_clock,
-#if defined(CONFIG_CPU_SUBTYPE_SH7722)
-        &sh7722_irda_clock,
 #endif
+/* 7724 should support FSI clock */
+#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7724)
+        &sh7722_irda_clock,
 #endif
         &sh7722_video_clock,
 };
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
new file mode 100644
index 000000000000..1af0f9586379
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
@@ -0,0 +1,2230 @@
+/*
+ * SH7724 Pinmux
+ *
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ *
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * Based on SH7723 Pinmux
+ *  Copyright (C) 2008  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <cpu/sh7724.h>
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+        PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
+        PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+        PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
+        PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+        PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
+        PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+        PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
+        PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
+        PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
+        PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+        PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
+                              PTG5_DATA, PTG4_DATA,
+        PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
+        PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+        PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
+        PTJ7_DATA, PTJ6_DATA, PTJ5_DATA,
+        PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
+        PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
+        PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
+        PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+        PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
+        PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+        PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
+        PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+        PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
+        PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
+        PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
+        PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+        PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
+                   PTS6_DATA, PTS5_DATA, PTS4_DATA,
+        PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
+        PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
+        PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
+        PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
+        PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
+        PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
+        PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
+        PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
+        PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
+        PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
+        PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
+        PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
+        PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
+        PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
+        PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
+        PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
+        PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
+        PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
+        PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
+        PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
+        PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
+        PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
+        PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
+        PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
+        PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
+        PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
+        PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
+        PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
+        PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
+        PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
+        PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
+        PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
+        PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
+        PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
+        PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
+        PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
+        PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
+        PTQ7_IN, PTQ6_IN, PTQ5_IN, PTQ4_IN,
+        PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
+        PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
+        PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
+                 PTS6_IN, PTS5_IN, PTS4_IN,
+        PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
+        PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
+        PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
+        PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
+        PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
+        PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
+        PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
+        PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
+        PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
+        PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
+        PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
+        PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
+        PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
+        PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
+        PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
+        PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
+        PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU,
+        PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU,
+        PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU,
+        PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU,
+        PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
+        PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
+        PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU,
+        PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
+        PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU,
+        PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU,
+        PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
+        PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
+        PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
+        PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU,
+        PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
+        PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU,
+        PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU,
+        PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
+        PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU,
+        PTN7_IN_PU, PTN6_IN_PU, PTN5_IN_PU, PTN4_IN_PU,
+        PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU,
+        PTQ7_IN_PU, PTQ6_IN_PU, PTQ5_IN_PU, PTQ4_IN_PU,
+        PTQ3_IN_PU, PTQ2_IN_PU, PTQ1_IN_PU, PTQ0_IN_PU,
+        PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU,
+        PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU,
+                    PTS6_IN_PU, PTS5_IN_PU, PTS4_IN_PU,
+        PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU,
+        PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU,
+        PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
+        PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
+        PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
+        PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
+        PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
+        PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU,
+        PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU,
+        PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
+        PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
+        PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
+        PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
+        PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU,
+        PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU,
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
+        PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
+        PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
+        PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
+        PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
+        PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
+        PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
+        PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
+        PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
+        PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
+        PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
+        PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
+                            PTG5_OUT, PTG4_OUT,
+        PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
+        PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
+        PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
+        PTJ7_OUT, PTJ6_OUT, PTJ5_OUT,
+        PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
+        PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
+        PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
+        PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
+        PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
+        PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
+        PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
+        PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
+        PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
+        PTQ7_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
+        PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
+        PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
+                            PTR1_OUT, PTR0_OUT,
+                  PTS6_OUT, PTS5_OUT, PTS4_OUT,
+        PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
+        PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
+        PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
+        PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
+        PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
+        PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
+        PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
+        PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
+        PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
+        PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
+        PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
+        PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
+        PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
+        PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
+        PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
+        PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
+        PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
+        PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
+        PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
+        PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
+        PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
+        PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
+        PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
+        PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
+        PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
+        PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
+                          PTG5_FN, PTG4_FN,
+        PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
+        PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
+        PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
+        PTJ7_FN, PTJ6_FN, PTJ5_FN,
+        PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
+        PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
+        PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
+        PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
+        PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
+        PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
+        PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
+        PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
+        PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
+        PTQ7_FN, PTQ6_FN, PTQ5_FN, PTQ4_FN,
+        PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
+        PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
+        PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
+                 PTS6_FN, PTS5_FN, PTS4_FN,
+        PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
+        PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
+        PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
+        PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
+        PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
+        PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
+        PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
+        PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
+        PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
+        PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
+        PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
+        PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
+        PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
+        PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
+        PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
+
+
+        PSA15_0, PSA15_1,
+        PSA14_0, PSA14_1,
+        PSA13_0, PSA13_1,
+        PSA12_0, PSA12_1,
+        PSA10_0, PSA10_1,
+        PSA9_0,  PSA9_1,
+        PSA8_0,  PSA8_1,
+        PSA7_0,  PSA7_1,
+        PSA6_0,  PSA6_1,
+        PSA5_0,  PSA5_1,
+        PSA3_0,  PSA3_1,
+        PSA2_0,  PSA2_1,
+        PSA1_0,  PSA1_1,
+        PSA0_0,  PSA0_1,
+
+        PSB14_0, PSB14_1,
+        PSB13_0, PSB13_1,
+        PSB12_0, PSB12_1,
+        PSB11_0, PSB11_1,
+        PSB10_0, PSB10_1,
+        PSB9_0,  PSB9_1,
+        PSB8_0,  PSB8_1,
+        PSB7_0,  PSB7_1,
+        PSB6_0,  PSB6_1,
+        PSB5_0,  PSB5_1,
+        PSB4_0,  PSB4_1,
+        PSB3_0,  PSB3_1,
+        PSB2_0,  PSB2_1,
+        PSB1_0,  PSB1_1,
+        PSB0_0,  PSB0_1,
+
+        PSC15_0, PSC15_1,
+        PSC14_0, PSC14_1,
+        PSC13_0, PSC13_1,
+        PSC12_0, PSC12_1,
+        PSC11_0, PSC11_1,
+        PSC10_0, PSC10_1,
+        PSC9_0,  PSC9_1,
+        PSC8_0,  PSC8_1,
+        PSC7_0,  PSC7_1,
+        PSC6_0,  PSC6_1,
+        PSC5_0,  PSC5_1,
+        PSC4_0,  PSC4_1,
+        PSC2_0,  PSC2_1,
+        PSC1_0,  PSC1_1,
+        PSC0_0,  PSC0_1,
+
+        PSD15_0, PSD15_1,
+        PSD14_0, PSD14_1,
+        PSD13_0, PSD13_1,
+        PSD12_0, PSD12_1,
+        PSD11_0, PSD11_1,
+        PSD10_0, PSD10_1,
+        PSD9_0,  PSD9_1,
+        PSD8_0,  PSD8_1,
+        PSD7_0,  PSD7_1,
+        PSD6_0,  PSD6_1,
+        PSD5_0,  PSD5_1,
+        PSD4_0,  PSD4_1,
+        PSD3_0,  PSD3_1,
+        PSD2_0,  PSD2_1,
+        PSD1_0,  PSD1_1,
+        PSD0_0,  PSD0_1,
+
+        PSE15_0, PSE15_1,
+        PSE14_0, PSE14_1,
+        PSE13_0, PSE13_1,
+        PSE12_0, PSE12_1,
+        PSE11_0, PSE11_1,
+        PSE10_0, PSE10_1,
+        PSE9_0,  PSE9_1,
+        PSE8_0,  PSE8_1,
+        PSE7_0,  PSE7_1,
+        PSE6_0,  PSE6_1,
+        PSE5_0,  PSE5_1,
+        PSE4_0,  PSE4_1,
+        PSE3_0,  PSE3_1,
+        PSE2_0,  PSE2_1,
+        PSE1_0,  PSE1_1,
+        PSE0_0,  PSE0_1,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        /*PTA*/
+        D23_MARK,       KEYOUT2_MARK,           IDED15_MARK,
+        D22_MARK,       KEYOUT1_MARK,           IDED14_MARK,
+        D21_MARK,       KEYOUT0_MARK,           IDED13_MARK,
+        D20_MARK,       KEYIN4_MARK,            IDED12_MARK,
+        D19_MARK,       KEYIN3_MARK,            IDED11_MARK,
+        D18_MARK,       KEYIN2_MARK,            IDED10_MARK,
+        D17_MARK,       KEYIN1_MARK,            IDED9_MARK,
+        D16_MARK,       KEYIN0_MARK,            IDED8_MARK,
+
+        /*PTB*/
+        D31_MARK,       TPUTO1_MARK,            IDEA1_MARK,
+        D30_MARK,       TPUTO0_MARK,            IDEA0_MARK,
+        D29_MARK,                               IODREQ_MARK,
+        D28_MARK,                               IDECS0_MARK,
+        D27_MARK,                               IDECS1_MARK,
+        D26_MARK,       KEYOUT5_IN5_MARK,       IDEIORD_MARK,
+        D25_MARK,       KEYOUT4_IN6_MARK,       IDEIOWR_MARK,
+        D24_MARK,       KEYOUT3_MARK,           IDEINT_MARK,
+
+        /*PTC*/
+        LCDD7_MARK,
+        LCDD6_MARK,
+        LCDD5_MARK,
+        LCDD4_MARK,
+        LCDD3_MARK,
+        LCDD2_MARK,
+        LCDD1_MARK,
+        LCDD0_MARK,
+
+        /*PTD*/
+        LCDD15_MARK,
+        LCDD14_MARK,
+        LCDD13_MARK,
+        LCDD12_MARK,
+        LCDD11_MARK,
+        LCDD10_MARK,
+        LCDD9_MARK,
+        LCDD8_MARK,
+
+        /*PTE*/
+        FSIMCKB_MARK,
+        FSIMCKA_MARK,
+        LCDD21_MARK,    SCIF2_L_TXD_MARK,
+        LCDD20_MARK,    SCIF4_SCK_MARK,
+        LCDD19_MARK,    SCIF4_RXD_MARK,
+        LCDD18_MARK,    SCIF4_TXD_MARK,
+        LCDD17_MARK,
+        LCDD16_MARK,
+
+        /*PTF*/
+        LCDVSYN_MARK,
+        LCDDISP_MARK,   LCDRS_MARK,
+        LCDHSYN_MARK,   LCDCS_MARK,
+        LCDDON_MARK,
+        LCDDCK_MARK,    LCDWR_MARK,
+        LCDVEPWC_MARK,  SCIF0_TXD_MARK,
+        LCDD23_MARK,    SCIF2_L_SCK_MARK,
+        LCDD22_MARK,    SCIF2_L_RXD_MARK,
+
+        /*PTG*/
+        AUDCK_MARK,
+        AUDSYNC_MARK,
+        AUDATA3_MARK,
+        AUDATA2_MARK,
+        AUDATA1_MARK,
+        AUDATA0_MARK,
+
+        /*PTH*/
+        VIO0_VD_MARK,
+        VIO0_CLK_MARK,
+        VIO0_D7_MARK,
+        VIO0_D6_MARK,
+        VIO0_D5_MARK,
+        VIO0_D4_MARK,
+        VIO0_D3_MARK,
+        VIO0_D2_MARK,
+
+        /*PTJ*/
+        PDSTATUS_MARK,
+        STATUS2_MARK,
+        STATUS0_MARK,
+        A25_MARK,               BS_MARK,
+        A24_MARK,
+        A23_MARK,
+        A22_MARK,
+
+        /*PTK*/
+        VIO1_D5_MARK,   VIO0_D13_MARK,  IDED5_MARK,
+        VIO1_D4_MARK,   VIO0_D12_MARK,  IDED4_MARK,
+        VIO1_D3_MARK,   VIO0_D11_MARK,  IDED3_MARK,
+        VIO1_D2_MARK,   VIO0_D10_MARK,  IDED2_MARK,
+        VIO1_D1_MARK,   VIO0_D9_MARK,   IDED1_MARK,
+        VIO1_D0_MARK,   VIO0_D8_MARK,   IDED0_MARK,
+        VIO0_FLD_MARK,
+        VIO0_HD_MARK,
+
+        /*PTL*/
+        DV_D5_MARK,     SCIF3_V_SCK_MARK,       RMII_RXD0_MARK,
+        DV_D4_MARK,     SCIF3_V_RXD_MARK,       RMII_RXD1_MARK,
+        DV_D3_MARK,     SCIF3_V_TXD_MARK,       RMII_REF_CLK_MARK,
+        DV_D2_MARK,     SCIF1_SCK_MARK,         RMII_TX_EN_MARK,
+        DV_D1_MARK,     SCIF1_RXD_MARK,         RMII_TXD0_MARK,
+        DV_D0_MARK,     SCIF1_TXD_MARK,         RMII_TXD1_MARK,
+        DV_D15_MARK,
+        DV_D14_MARK,    MSIOF0_MCK_MARK,
+
+        /*PTM*/
+        DV_D13_MARK,    MSIOF0_TSCK_MARK,
+        DV_D12_MARK,    MSIOF0_RXD_MARK,
+        DV_D11_MARK,    MSIOF0_TXD_MARK,
+        DV_D10_MARK,    MSIOF0_TSYNC_MARK,
+        DV_D9_MARK,     MSIOF0_SS1_MARK,        MSIOF0_RSCK_MARK,
+        DV_D8_MARK,     MSIOF0_SS2_MARK,        MSIOF0_RSYNC_MARK,
+        LCDVCPWC_MARK,  SCIF0_RXD_MARK,
+        LCDRD_MARK,     SCIF0_SCK_MARK,
+
+        /*PTN*/
+        VIO0_D1_MARK,
+        VIO0_D0_MARK,
+        DV_CLKI_MARK,
+        DV_CLK_MARK,    SCIF2_V_SCK_MARK,
+        DV_VSYNC_MARK,  SCIF2_V_RXD_MARK,
+        DV_HSYNC_MARK,  SCIF2_V_TXD_MARK,
+        DV_D7_MARK,     SCIF3_V_CTS_MARK,       RMII_RX_ER_MARK,
+        DV_D6_MARK,     SCIF3_V_RTS_MARK,       RMII_CRS_DV_MARK,
+
+        /*PTQ*/
+        D7_MARK,
+        D6_MARK,
+        D5_MARK,
+        D4_MARK,
+        D3_MARK,
+        D2_MARK,
+        D1_MARK,
+        D0_MARK,
+
+        /*PTR*/
+        CS6B_CE1B_MARK,
+        CS6A_CE2B_MARK,
+        CS5B_CE1A_MARK,
+        CS5A_CE2A_MARK,
+        IOIS16_MARK,            LCDLCLK_MARK,
+        WAIT_MARK,
+        WE3_ICIOWR_MARK,        TPUTO3_MARK,    TPUTI3_MARK,
+        WE2_ICIORD_MARK,        TPUTO2_MARK,    IDEA2_MARK,
+
+        /*PTS*/
+        VIO_CKO_MARK,
+        VIO1_FLD_MARK,  TPUTI2_MARK,            IDEIORDY_MARK,
+        VIO1_HD_MARK,   SCIF5_SCK_MARK,
+        VIO1_VD_MARK,   SCIF5_RXD_MARK,
+        VIO1_CLK_MARK,  SCIF5_TXD_MARK,
+        VIO1_D7_MARK,   VIO0_D15_MARK,          IDED7_MARK,
+        VIO1_D6_MARK,   VIO0_D14_MARK,          IDED6_MARK,
+
+        /*PTT*/
+        D15_MARK,
+        D14_MARK,
+        D13_MARK,
+        D12_MARK,
+        D11_MARK,
+        D10_MARK,
+        D9_MARK,
+        D8_MARK,
+
+        /*PTU*/
+        DMAC_DACK0_MARK,
+        DMAC_DREQ0_MARK,
+        FSIOASD_MARK,
+        FSIIABCK_MARK,
+        FSIIALRCK_MARK,
+        FSIOABCK_MARK,
+        FSIOALRCK_MARK,
+        CLKAUDIOAO_MARK,
+
+        /*PTV*/
+        FSIIBSD_MARK,           MSIOF1_SS2_MARK,        MSIOF1_RSYNC_MARK,
+        FSIOBSD_MARK,           MSIOF1_SS1_MARK,        MSIOF1_RSCK_MARK,
+        FSIIBBCK_MARK,          MSIOF1_RXD_MARK,
+        FSIIBLRCK_MARK,         MSIOF1_TSYNC_MARK,
+        FSIOBBCK_MARK,          MSIOF1_TSCK_MARK,
+        FSIOBLRCK_MARK,         MSIOF1_TXD_MARK,
+        CLKAUDIOBO_MARK,        MSIOF1_MCK_MARK,
+        FSIIASD_MARK,
+
+        /*PTW*/
+        MMC_D7_MARK,            SDHI1CD_MARK,           IODACK_MARK,
+        MMC_D6_MARK,            SDHI1WP_MARK,           IDERST_MARK,
+        MMC_D5_MARK,            SDHI1D3_MARK,           EXBUF_ENB_MARK,
+        MMC_D4_MARK,            SDHI1D2_MARK,           DIRECTION_MARK,
+        MMC_D3_MARK,            SDHI1D1_MARK,
+        MMC_D2_MARK,            SDHI1D0_MARK,
+        MMC_D1_MARK,            SDHI1CMD_MARK,
+        MMC_D0_MARK,            SDHI1CLK_MARK,
+
+        /*PTX*/
+        DMAC_DACK1_MARK,        IRDA_OUT_MARK,
+        DMAC_DREQ1_MARK,        IRDA_IN_MARK,
+        TSIF_TS0_SDAT_MARK,                             LNKSTA_MARK,
+        TSIF_TS0_SCK_MARK,                              MDIO_MARK,
+        TSIF_TS0_SDEN_MARK,                             MDC_MARK,
+        TSIF_TS0_SPSYNC_MARK,
+        MMC_CLK_MARK,
+        MMC_CMD_MARK,
+
+        /*PTY*/
+        SDHI0CD_MARK,
+        SDHI0WP_MARK,
+        SDHI0D3_MARK,
+        SDHI0D2_MARK,
+        SDHI0D1_MARK,
+        SDHI0D0_MARK,
+        SDHI0CMD_MARK,
+        SDHI0CLK_MARK,
+
+        /*PTZ*/
+        INTC_IRQ7_MARK,         SCIF3_I_CTS_MARK,
+        INTC_IRQ6_MARK,         SCIF3_I_RTS_MARK,
+        INTC_IRQ5_MARK,         SCIF3_I_SCK_MARK,
+        INTC_IRQ4_MARK,         SCIF3_I_RXD_MARK,
+        INTC_IRQ3_MARK,         SCIF3_I_TXD_MARK,
+        INTC_IRQ2_MARK,
+        INTC_IRQ1_MARK,
+        INTC_IRQ0_MARK,
+        PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+        /* PTA GPIO */
+        PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
+        PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
+        PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU),
+        PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU),
+        PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU),
+        PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU),
+        PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU),
+        PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU),
+
+        /* PTB GPIO */
+        PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU),
+        PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU),
+        PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU),
+        PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU),
+        PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU),
+        PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU),
+        PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU),
+        PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU),
+
+        /* PTC GPIO */
+        PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU),
+        PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU),
+        PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU),
+        PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU),
+        PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU),
+        PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU),
+        PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU),
+        PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU),
+
+        /* PTD GPIO */
+        PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU),
+        PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU),
+        PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU),
+        PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU),
+        PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU),
+        PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU),
+        PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU),
+        PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU),
+
+        /* PTE GPIO */
+        PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT, PTE7_IN_PU),
+        PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT, PTE6_IN_PU),
+        PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT, PTE5_IN_PU),
+        PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU),
+        PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU),
+        PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU),
+        PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU),
+        PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU),
+
+        /* PTF GPIO */
+        PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT, PTF7_IN_PU),
+        PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT, PTF6_IN_PU),
+        PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT, PTF5_IN_PU),
+        PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT, PTF4_IN_PU),
+        PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT, PTF3_IN_PU),
+        PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT, PTF2_IN_PU),
+        PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT, PTF1_IN_PU),
+        PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU),
+
+        /* PTG GPIO */
+        PINMUX_DATA(PTG5_DATA, PTG5_OUT),
+        PINMUX_DATA(PTG4_DATA, PTG4_OUT),
+        PINMUX_DATA(PTG3_DATA, PTG3_OUT),
+        PINMUX_DATA(PTG2_DATA, PTG2_OUT),
+        PINMUX_DATA(PTG1_DATA, PTG1_OUT),
+        PINMUX_DATA(PTG0_DATA, PTG0_OUT),
+
+        /* PTH GPIO */
+        PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT, PTH7_IN_PU),
+        PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU),
+        PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU),
+        PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU),
+        PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU),
+        PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU),
+        PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU),
+        PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU),
+
+        /* PTJ GPIO */
+        PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
+        PINMUX_DATA(PTJ6_DATA, PTJ6_OUT),
+        PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
+        PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU),
+        PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU),
+        PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU),
+        PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU),
+
+        /* PTK GPIO */
+        PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT, PTK7_IN_PU),
+        PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT, PTK6_IN_PU),
+        PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT, PTK5_IN_PU),
+        PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT, PTK4_IN_PU),
+        PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU),
+        PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU),
+        PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU),
+        PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU),
+
+        /* PTL GPIO */
+        PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU),
+        PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU),
+        PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU),
+        PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU),
+        PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU),
+        PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT, PTL2_IN_PU),
+        PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT, PTL1_IN_PU),
+        PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT, PTL0_IN_PU),
+
+        /* PTM GPIO */
+        PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU),
+        PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU),
+        PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU),
+        PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU),
+        PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU),
+        PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU),
+        PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU),
+        PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU),
+
+        /* PTN GPIO */
+        PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT, PTN7_IN_PU),
+        PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT, PTN6_IN_PU),
+        PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT, PTN5_IN_PU),
+        PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT, PTN4_IN_PU),
+        PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT, PTN3_IN_PU),
+        PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT, PTN2_IN_PU),
+        PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT, PTN1_IN_PU),
+        PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT, PTN0_IN_PU),
+
+        /* PTQ GPIO */
+        PINMUX_DATA(PTQ7_DATA, PTQ7_IN, PTQ7_OUT, PTQ7_IN_PU),
+        PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT, PTQ6_IN_PU),
+        PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT, PTQ5_IN_PU),
+        PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT, PTQ4_IN_PU),
+        PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT, PTQ3_IN_PU),
+        PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT, PTQ2_IN_PU),
+        PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT, PTQ1_IN_PU),
+        PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT, PTQ0_IN_PU),
+
+        /* PTR GPIO */
+        PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU),
+        PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU),
+        PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU),
+        PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU),
+        PINMUX_DATA(PTR3_DATA, PTR3_IN,           PTR3_IN_PU),
+        PINMUX_DATA(PTR2_DATA, PTR2_IN,           PTR2_IN_PU),
+        PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU),
+        PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU),
+
+        /* PTS GPIO */
+        PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT, PTS6_IN_PU),
+        PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT, PTS5_IN_PU),
+        PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU),
+        PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU),
+        PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU),
+        PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU),
+        PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU),
+
+        /* PTT GPIO */
+        PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT, PTT7_IN_PU),
+        PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT, PTT6_IN_PU),
+        PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT, PTT5_IN_PU),
+        PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU),
+        PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU),
+        PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU),
+        PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU),
+        PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU),
+
+        /* PTU GPIO */
+        PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT, PTU7_IN_PU),
+        PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT, PTU6_IN_PU),
+        PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT, PTU5_IN_PU),
+        PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU),
+        PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU),
+        PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU),
+        PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU),
+        PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU),
+
+        /* PTV GPIO */
+        PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT, PTV7_IN_PU),
+        PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT, PTV6_IN_PU),
+        PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT, PTV5_IN_PU),
+        PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU),
+        PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU),
+        PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU),
+        PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU),
+        PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU),
+
+        /* PTW GPIO */
+        PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT, PTW7_IN_PU),
+        PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT, PTW6_IN_PU),
+        PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT, PTW5_IN_PU),
+        PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT, PTW4_IN_PU),
+        PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT, PTW3_IN_PU),
+        PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT, PTW2_IN_PU),
+        PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT, PTW1_IN_PU),
+        PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT, PTW0_IN_PU),
+
+        /* PTX GPIO */
+        PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT, PTX7_IN_PU),
+        PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT, PTX6_IN_PU),
+        PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT, PTX5_IN_PU),
+        PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT, PTX4_IN_PU),
+        PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT, PTX3_IN_PU),
+        PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT, PTX2_IN_PU),
+        PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT, PTX1_IN_PU),
+        PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT, PTX0_IN_PU),
+
+        /* PTY GPIO */
+        PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT, PTY7_IN_PU),
+        PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT, PTY6_IN_PU),
+        PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT, PTY5_IN_PU),
+        PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT, PTY4_IN_PU),
+        PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT, PTY3_IN_PU),
+        PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT, PTY2_IN_PU),
+        PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT, PTY1_IN_PU),
+        PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT, PTY0_IN_PU),
+
+        /* PTZ GPIO */
+        PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT, PTZ7_IN_PU),
+        PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT, PTZ6_IN_PU),
+        PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT, PTZ5_IN_PU),
+        PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT, PTZ4_IN_PU),
+        PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT, PTZ3_IN_PU),
+        PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT, PTZ2_IN_PU),
+        PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT, PTZ1_IN_PU),
+        PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT, PTZ0_IN_PU),
+
+        /* PTA FN */
+        PINMUX_DATA(D23_MARK,   PSA15_0, PSA14_0, PTA7_FN),
+        PINMUX_DATA(D22_MARK,   PSA15_0, PSA14_0, PTA6_FN),
+        PINMUX_DATA(D21_MARK,   PSA15_0, PSA14_0, PTA5_FN),
+        PINMUX_DATA(D20_MARK,   PSA15_0, PSA14_0, PTA4_FN),
+        PINMUX_DATA(D19_MARK,   PSA15_0, PSA14_0, PTA3_FN),
+        PINMUX_DATA(D18_MARK,   PSA15_0, PSA14_0, PTA2_FN),
+        PINMUX_DATA(D17_MARK,   PSA15_0, PSA14_0, PTA1_FN),
+        PINMUX_DATA(D16_MARK,   PSA15_0, PSA14_0, PTA0_FN),
+
+        PINMUX_DATA(KEYOUT2_MARK,       PSA15_0, PSA14_1, PTA7_FN),
+        PINMUX_DATA(KEYOUT1_MARK,       PSA15_0, PSA14_1, PTA6_FN),
+        PINMUX_DATA(KEYOUT0_MARK,       PSA15_0, PSA14_1, PTA5_FN),
+        PINMUX_DATA(KEYIN4_MARK,        PSA15_0, PSA14_1, PTA4_FN),
+        PINMUX_DATA(KEYIN3_MARK,        PSA15_0, PSA14_1, PTA3_FN),
+        PINMUX_DATA(KEYIN2_MARK,        PSA15_0, PSA14_1, PTA2_FN),
+        PINMUX_DATA(KEYIN1_MARK,        PSA15_0, PSA14_1, PTA1_FN),
+        PINMUX_DATA(KEYIN0_MARK,        PSA15_0, PSA14_1, PTA0_FN),
+
+        PINMUX_DATA(IDED15_MARK,        PSA15_1, PSA14_0, PTA7_FN),
+        PINMUX_DATA(IDED14_MARK,        PSA15_1, PSA14_0, PTA6_FN),
+        PINMUX_DATA(IDED13_MARK,        PSA15_1, PSA14_0, PTA5_FN),
+        PINMUX_DATA(IDED12_MARK,        PSA15_1, PSA14_0, PTA4_FN),
+        PINMUX_DATA(IDED11_MARK,        PSA15_1, PSA14_0, PTA3_FN),
+        PINMUX_DATA(IDED10_MARK,        PSA15_1, PSA14_0, PTA2_FN),
+        PINMUX_DATA(IDED9_MARK,         PSA15_1, PSA14_0, PTA1_FN),
+        PINMUX_DATA(IDED8_MARK,         PSA15_1, PSA14_0, PTA0_FN),
+
+        /* PTB FN */
+        PINMUX_DATA(D31_MARK,           PSE15_0, PSE14_0, PTB7_FN),
+        PINMUX_DATA(D30_MARK,           PSE15_0, PSE14_0, PTB6_FN),
+        PINMUX_DATA(D29_MARK,           PSE11_0,          PTB5_FN),
+        PINMUX_DATA(D28_MARK,           PSE11_0,          PTB4_FN),
+        PINMUX_DATA(D27_MARK,           PSE11_0,          PTB3_FN),
+        PINMUX_DATA(D26_MARK,           PSA15_0, PSA14_0, PTB2_FN),
+        PINMUX_DATA(D25_MARK,           PSA15_0, PSA14_0, PTB1_FN),
+        PINMUX_DATA(D24_MARK,           PSA15_0, PSA14_0, PTB0_FN),
+
+        PINMUX_DATA(IDEA1_MARK,         PSE15_1, PSE14_0, PTB7_FN),
+        PINMUX_DATA(IDEA0_MARK,         PSE15_1, PSE14_0, PTB6_FN),
+        PINMUX_DATA(IODREQ_MARK,        PSE11_1,          PTB5_FN),
+        PINMUX_DATA(IDECS0_MARK,        PSE11_1,          PTB4_FN),
+        PINMUX_DATA(IDECS1_MARK,        PSE11_1,          PTB3_FN),
+        PINMUX_DATA(IDEIORD_MARK,       PSA15_1, PSA14_0, PTB2_FN),
+        PINMUX_DATA(IDEIOWR_MARK,       PSA15_1, PSA14_0, PTB1_FN),
+        PINMUX_DATA(IDEINT_MARK,        PSA15_1, PSA14_0, PTB0_FN),
+
+        PINMUX_DATA(TPUTO1_MARK,        PSE15_0, PSE14_1, PTB7_FN),
+        PINMUX_DATA(TPUTO0_MARK,        PSE15_0, PSE14_1, PTB6_FN),
+
+        PINMUX_DATA(KEYOUT5_IN5_MARK,   PSA15_0, PSA14_1, PTB2_FN),
+        PINMUX_DATA(KEYOUT4_IN6_MARK,   PSA15_0, PSA14_1, PTB1_FN),
+        PINMUX_DATA(KEYOUT3_MARK,       PSA15_0, PSA14_1, PTB0_FN),
+
+        /* PTC FN */
+        PINMUX_DATA(LCDD7_MARK, PSD5_0, PTC7_FN),
+        PINMUX_DATA(LCDD6_MARK, PSD5_0, PTC6_FN),
+        PINMUX_DATA(LCDD5_MARK, PSD5_0, PTC5_FN),
+        PINMUX_DATA(LCDD4_MARK, PSD5_0, PTC4_FN),
+        PINMUX_DATA(LCDD3_MARK, PSD5_0, PTC3_FN),
+        PINMUX_DATA(LCDD2_MARK, PSD5_0, PTC2_FN),
+        PINMUX_DATA(LCDD1_MARK, PSD5_0, PTC1_FN),
+        PINMUX_DATA(LCDD0_MARK, PSD5_0, PTC0_FN),
+
+        /* PTD FN */
+        PINMUX_DATA(LCDD15_MARK, PSD5_0, PTD7_FN),
+        PINMUX_DATA(LCDD14_MARK, PSD5_0, PTD6_FN),
+        PINMUX_DATA(LCDD13_MARK, PSD5_0, PTD5_FN),
+        PINMUX_DATA(LCDD12_MARK, PSD5_0, PTD4_FN),
+        PINMUX_DATA(LCDD11_MARK, PSD5_0, PTD3_FN),
+        PINMUX_DATA(LCDD10_MARK, PSD5_0, PTD2_FN),
+        PINMUX_DATA(LCDD9_MARK,  PSD5_0, PTD1_FN),
+        PINMUX_DATA(LCDD8_MARK,  PSD5_0, PTD0_FN),
+
+        /* PTE FN */
+        PINMUX_DATA(FSIMCKB_MARK, PTE7_FN),
+        PINMUX_DATA(FSIMCKA_MARK, PTE6_FN),
+
+        PINMUX_DATA(LCDD21_MARK,        PSC5_0, PSC4_0, PTE5_FN),
+        PINMUX_DATA(LCDD20_MARK,        PSD3_0, PSD2_0, PTE4_FN),
+        PINMUX_DATA(LCDD19_MARK,        PSA3_0, PSA2_0, PTE3_FN),
+        PINMUX_DATA(LCDD18_MARK,        PSA3_0, PSA2_0, PTE2_FN),
+        PINMUX_DATA(LCDD17_MARK,        PSD5_0,         PTE1_FN),
+        PINMUX_DATA(LCDD16_MARK,        PSD5_0,         PTE0_FN),
+
+        PINMUX_DATA(SCIF2_L_TXD_MARK,   PSC5_0, PSC4_1, PTE5_FN),
+        PINMUX_DATA(SCIF4_SCK_MARK,     PSD3_0, PSD2_1, PTE4_FN),
+        PINMUX_DATA(SCIF4_RXD_MARK,     PSA3_0, PSA2_1, PTE3_FN),
+        PINMUX_DATA(SCIF4_TXD_MARK,     PSA3_0, PSA2_1, PTE2_FN),
+
+        /* PTF FN */
+        PINMUX_DATA(LCDVSYN_MARK,       PSD8_0,          PTF7_FN),
+        PINMUX_DATA(LCDDISP_MARK,       PSD10_0, PSD9_0, PTF6_FN),
+        PINMUX_DATA(LCDHSYN_MARK,       PSD10_0, PSD9_0, PTF5_FN),
+        PINMUX_DATA(LCDDON_MARK,        PSD8_0,          PTF4_FN),
+        PINMUX_DATA(LCDDCK_MARK,        PSD10_0, PSD9_0, PTF3_FN),
+        PINMUX_DATA(LCDVEPWC_MARK,      PSA6_0,          PTF2_FN),
+        PINMUX_DATA(LCDD23_MARK,        PSC7_0,  PSC6_0, PTF1_FN),
+        PINMUX_DATA(LCDD22_MARK,        PSC5_0,  PSC4_0, PTF0_FN),
+
+        PINMUX_DATA(LCDRS_MARK,         PSD10_0, PSD9_1, PTF6_FN),
+        PINMUX_DATA(LCDCS_MARK,         PSD10_0, PSD9_1, PTF5_FN),
+        PINMUX_DATA(LCDWR_MARK,         PSD10_0, PSD9_1, PTF3_FN),
+
+        PINMUX_DATA(SCIF0_TXD_MARK,     PSA6_1,          PTF2_FN),
+        PINMUX_DATA(SCIF2_L_SCK_MARK,   PSC7_0,  PSC6_1, PTF1_FN),
+        PINMUX_DATA(SCIF2_L_RXD_MARK,   PSC5_0,  PSC4_1, PTF0_FN),
+
+        /* PTG FN */
+        PINMUX_DATA(AUDCK_MARK,   PTG5_FN),
+        PINMUX_DATA(AUDSYNC_MARK, PTG4_FN),
+        PINMUX_DATA(AUDATA3_MARK, PTG3_FN),
+        PINMUX_DATA(AUDATA2_MARK, PTG2_FN),
+        PINMUX_DATA(AUDATA1_MARK, PTG1_FN),
+        PINMUX_DATA(AUDATA0_MARK, PTG0_FN),
+
+        /* PTH FN */
+        PINMUX_DATA(VIO0_VD_MARK,  PTH7_FN),
+        PINMUX_DATA(VIO0_CLK_MARK, PTH6_FN),
+        PINMUX_DATA(VIO0_D7_MARK,  PTH5_FN),
+        PINMUX_DATA(VIO0_D6_MARK,  PTH4_FN),
+        PINMUX_DATA(VIO0_D5_MARK,  PTH3_FN),
+        PINMUX_DATA(VIO0_D4_MARK,  PTH2_FN),
+        PINMUX_DATA(VIO0_D3_MARK,  PTH1_FN),
+        PINMUX_DATA(VIO0_D2_MARK,  PTH0_FN),
+
+        /* PTJ FN */
+        PINMUX_DATA(PDSTATUS_MARK,      PTJ7_FN),
+        PINMUX_DATA(STATUS2_MARK,       PTJ6_FN),
+        PINMUX_DATA(STATUS0_MARK,       PTJ5_FN),
+        PINMUX_DATA(A25_MARK,           PSA8_0, PTJ3_FN),
+        PINMUX_DATA(BS_MARK,            PSA8_1, PTJ3_FN),
+        PINMUX_DATA(A24_MARK,           PTJ2_FN),
+        PINMUX_DATA(A23_MARK,           PTJ1_FN),
+        PINMUX_DATA(A22_MARK,           PTJ0_FN),
+
+        /* PTK FN */
+        PINMUX_DATA(VIO1_D5_MARK,       PSB7_0, PSB6_0, PTK7_FN),
+        PINMUX_DATA(VIO1_D4_MARK,       PSB7_0, PSB6_0, PTK6_FN),
+        PINMUX_DATA(VIO1_D3_MARK,       PSB7_0, PSB6_0, PTK5_FN),
+        PINMUX_DATA(VIO1_D2_MARK,       PSB7_0, PSB6_0, PTK4_FN),
+        PINMUX_DATA(VIO1_D1_MARK,       PSB7_0, PSB6_0, PTK3_FN),
+        PINMUX_DATA(VIO1_D0_MARK,       PSB7_0, PSB6_0, PTK2_FN),
+
+        PINMUX_DATA(VIO0_D13_MARK,      PSB7_0, PSB6_1, PTK7_FN),
+        PINMUX_DATA(VIO0_D12_MARK,      PSB7_0, PSB6_1, PTK6_FN),
+        PINMUX_DATA(VIO0_D11_MARK,      PSB7_0, PSB6_1, PTK5_FN),
+        PINMUX_DATA(VIO0_D10_MARK,      PSB7_0, PSB6_1, PTK4_FN),
+        PINMUX_DATA(VIO0_D9_MARK,       PSB7_0, PSB6_1, PTK3_FN),
+        PINMUX_DATA(VIO0_D8_MARK,       PSB7_0, PSB6_1, PTK2_FN),
+
+        PINMUX_DATA(IDED5_MARK,         PSB7_1, PSB6_0, PTK7_FN),
+        PINMUX_DATA(IDED4_MARK,         PSB7_1, PSB6_0, PTK6_FN),
+        PINMUX_DATA(IDED3_MARK,         PSB7_1, PSB6_0, PTK5_FN),
+        PINMUX_DATA(IDED2_MARK,         PSB7_1, PSB6_0, PTK4_FN),
+        PINMUX_DATA(IDED1_MARK,         PSB7_1, PSB6_0, PTK3_FN),
+        PINMUX_DATA(IDED0_MARK,         PSB7_1, PSB6_0, PTK2_FN),
+
+        PINMUX_DATA(VIO0_FLD_MARK,      PTK1_FN),
+        PINMUX_DATA(VIO0_HD_MARK,       PTK0_FN),
+
+        /* PTL FN */
+        PINMUX_DATA(DV_D5_MARK,         PSB9_0, PSB8_0, PTL7_FN),
+        PINMUX_DATA(DV_D4_MARK,         PSB9_0, PSB8_0, PTL6_FN),
+        PINMUX_DATA(DV_D3_MARK,         PSE7_0, PSE6_0, PTL5_FN),
+        PINMUX_DATA(DV_D2_MARK,         PSC9_0, PSC8_0, PTL4_FN),
+        PINMUX_DATA(DV_D1_MARK,         PSC9_0, PSC8_0, PTL3_FN),
+        PINMUX_DATA(DV_D0_MARK,         PSC9_0, PSC8_0, PTL2_FN),
+        PINMUX_DATA(DV_D15_MARK,        PSD4_0,         PTL1_FN),
+        PINMUX_DATA(DV_D14_MARK,        PSE5_0, PSE4_0, PTL0_FN),
+
+        PINMUX_DATA(SCIF3_V_SCK_MARK,   PSB9_0, PSB8_1, PTL7_FN),
+        PINMUX_DATA(SCIF3_V_RXD_MARK,   PSB9_0, PSB8_1, PTL6_FN),
+        PINMUX_DATA(SCIF3_V_TXD_MARK,   PSE7_0, PSE6_1, PTL5_FN),
+        PINMUX_DATA(SCIF1_SCK_MARK,     PSC9_0, PSC8_1, PTL4_FN),
+        PINMUX_DATA(SCIF1_RXD_MARK,     PSC9_0, PSC8_1, PTL3_FN),
+        PINMUX_DATA(SCIF1_TXD_MARK,     PSC9_0, PSC8_1, PTL2_FN),
+
+        PINMUX_DATA(RMII_RXD0_MARK,     PSB9_1, PSB8_0, PTL7_FN),
+        PINMUX_DATA(RMII_RXD1_MARK,     PSB9_1, PSB8_0, PTL6_FN),
+        PINMUX_DATA(RMII_REF_CLK_MARK,  PSE7_1, PSE6_0, PTL5_FN),
+        PINMUX_DATA(RMII_TX_EN_MARK,    PSC9_1, PSC8_0, PTL4_FN),
+        PINMUX_DATA(RMII_TXD0_MARK,     PSC9_1, PSC8_0, PTL3_FN),
+        PINMUX_DATA(RMII_TXD1_MARK,     PSC9_1, PSC8_0, PTL2_FN),
+
+        PINMUX_DATA(MSIOF0_MCK_MARK,    PSE5_0, PSE4_1, PTL0_FN),
+
+        /* PTM FN */
+        PINMUX_DATA(DV_D13_MARK,        PSC13_0, PSC12_0, PTM7_FN),
+        PINMUX_DATA(DV_D12_MARK,        PSC13_0, PSC12_0, PTM6_FN),
+        PINMUX_DATA(DV_D11_MARK,        PSC13_0, PSC12_0, PTM5_FN),
+        PINMUX_DATA(DV_D10_MARK,        PSC13_0, PSC12_0, PTM4_FN),
+        PINMUX_DATA(DV_D9_MARK,         PSC11_0, PSC10_0, PTM3_FN),
+        PINMUX_DATA(DV_D8_MARK,         PSC11_0, PSC10_0, PTM2_FN),
+
+        PINMUX_DATA(MSIOF0_TSCK_MARK,   PSC13_0, PSC12_1, PTM7_FN),
+        PINMUX_DATA(MSIOF0_RXD_MARK,    PSC13_0, PSC12_1, PTM6_FN),
+        PINMUX_DATA(MSIOF0_TXD_MARK,    PSC13_0, PSC12_1, PTM5_FN),
+        PINMUX_DATA(MSIOF0_TSYNC_MARK,  PSC13_0, PSC12_1, PTM4_FN),
+        PINMUX_DATA(MSIOF0_SS1_MARK,    PSC11_0, PSC10_1, PTM3_FN),
+        PINMUX_DATA(MSIOF0_RSCK_MARK,   PSC11_1, PSC10_0, PTM3_FN),
+        PINMUX_DATA(MSIOF0_SS2_MARK,    PSC11_0, PSC10_1, PTM2_FN),
+        PINMUX_DATA(MSIOF0_RSYNC_MARK,  PSC11_1, PSC10_0, PTM2_FN),
+
+        PINMUX_DATA(LCDVCPWC_MARK,      PSA6_0, PTM1_FN),
+        PINMUX_DATA(LCDRD_MARK,         PSA7_0, PTM0_FN),
+
+        PINMUX_DATA(SCIF0_RXD_MARK,     PSA6_1, PTM1_FN),
+        PINMUX_DATA(SCIF0_SCK_MARK,     PSA7_1, PTM0_FN),
+
+        /* PTN FN */
+        PINMUX_DATA(VIO0_D1_MARK,       PTN7_FN),
+        PINMUX_DATA(VIO0_D0_MARK,       PTN6_FN),
+
+        PINMUX_DATA(DV_CLKI_MARK,       PSD11_0,          PTN5_FN),
+        PINMUX_DATA(DV_CLK_MARK,        PSD13_0, PSD12_0, PTN4_FN),
+        PINMUX_DATA(DV_VSYNC_MARK,      PSD15_0, PSD14_0, PTN3_FN),
+        PINMUX_DATA(DV_HSYNC_MARK,      PSB5_0,  PSB4_0,  PTN2_FN),
+        PINMUX_DATA(DV_D7_MARK,         PSB3_0,  PSB2_0,  PTN1_FN),
+        PINMUX_DATA(DV_D6_MARK,         PSB1_0,  PSB0_0,  PTN0_FN),
+
+        PINMUX_DATA(SCIF2_V_SCK_MARK,   PSD13_0, PSD12_1, PTN4_FN),
+        PINMUX_DATA(SCIF2_V_RXD_MARK,   PSD15_0, PSD14_1, PTN3_FN),
+        PINMUX_DATA(SCIF2_V_TXD_MARK,   PSB5_0,  PSB4_1,  PTN2_FN),
+        PINMUX_DATA(SCIF3_V_CTS_MARK,   PSB3_0,  PSB2_1,  PTN1_FN),
+        PINMUX_DATA(SCIF3_V_RTS_MARK,   PSB1_0,  PSB0_1,  PTN0_FN),
+
+        PINMUX_DATA(RMII_RX_ER_MARK,    PSB3_1, PSB2_0, PTN1_FN),
+        PINMUX_DATA(RMII_CRS_DV_MARK,   PSB1_1, PSB0_0, PTN0_FN),
+
+        /* PTQ FN */
+        PINMUX_DATA(D7_MARK, PTQ7_FN),
+        PINMUX_DATA(D6_MARK, PTQ6_FN),
+        PINMUX_DATA(D5_MARK, PTQ5_FN),
+        PINMUX_DATA(D4_MARK, PTQ4_FN),
+        PINMUX_DATA(D3_MARK, PTQ3_FN),
+        PINMUX_DATA(D2_MARK, PTQ2_FN),
+        PINMUX_DATA(D1_MARK, PTQ1_FN),
+        PINMUX_DATA(D0_MARK, PTQ0_FN),
+
+        /* PTR FN */
+        PINMUX_DATA(CS6B_CE1B_MARK,                     PTR7_FN),
+        PINMUX_DATA(CS6A_CE2B_MARK,                     PTR6_FN),
+        PINMUX_DATA(CS5B_CE1A_MARK,                     PTR5_FN),
+        PINMUX_DATA(CS5A_CE2A_MARK,                     PTR4_FN),
+        PINMUX_DATA(IOIS16_MARK,        PSA5_0,         PTR3_FN),
+        PINMUX_DATA(WAIT_MARK,                          PTR2_FN),
+        PINMUX_DATA(WE3_ICIOWR_MARK,    PSA1_0, PSA0_0, PTR1_FN),
+        PINMUX_DATA(WE2_ICIORD_MARK,    PSD1_0, PSD0_0, PTR0_FN),
+
+        PINMUX_DATA(LCDLCLK_MARK,       PSA5_1,         PTR3_FN),
+
+        PINMUX_DATA(IDEA2_MARK,         PSD1_1, PSD0_0, PTR0_FN),
+
+        PINMUX_DATA(TPUTO3_MARK,        PSA1_0, PSA0_1, PTR1_FN),
+        PINMUX_DATA(TPUTI3_MARK,        PSA1_1, PSA0_0, PTR1_FN),
+        PINMUX_DATA(TPUTO2_MARK,        PSD1_0, PSD0_1, PTR0_FN),
+
+        /* PTS FN */
+        PINMUX_DATA(VIO_CKO_MARK,       PTS6_FN),
+
+        PINMUX_DATA(TPUTI2_MARK,        PSE9_0, PSE8_1, PTS5_FN),
+
+        PINMUX_DATA(IDEIORDY_MARK,      PSE9_1, PSE8_0, PTS5_FN),
+
+        PINMUX_DATA(VIO1_FLD_MARK,      PSE9_0, PSE8_0, PTS5_FN),
+        PINMUX_DATA(VIO1_HD_MARK,       PSA10_0,        PTS4_FN),
+        PINMUX_DATA(VIO1_VD_MARK,       PSA9_0,         PTS3_FN),
+        PINMUX_DATA(VIO1_CLK_MARK,      PSA9_0,         PTS2_FN),
+        PINMUX_DATA(VIO1_D7_MARK,       PSB7_0, PSB6_0, PTS1_FN),
+        PINMUX_DATA(VIO1_D6_MARK,       PSB7_0, PSB6_0, PTS0_FN),
+
+        PINMUX_DATA(SCIF5_SCK_MARK,     PSA10_1, PTS4_FN),
+        PINMUX_DATA(SCIF5_RXD_MARK,     PSA9_1,  PTS3_FN),
+        PINMUX_DATA(SCIF5_TXD_MARK,     PSA9_1,  PTS2_FN),
+
+        PINMUX_DATA(VIO0_D15_MARK,      PSB7_0, PSB6_1, PTS1_FN),
+        PINMUX_DATA(VIO0_D14_MARK,      PSB7_0, PSB6_1, PTS0_FN),
+
+        PINMUX_DATA(IDED7_MARK,         PSB7_1, PSB6_0, PTS1_FN),
+        PINMUX_DATA(IDED6_MARK,         PSB7_1, PSB6_0, PTS0_FN),
+
+        /* PTT FN */
+        PINMUX_DATA(D15_MARK, PTT7_FN),
+        PINMUX_DATA(D14_MARK, PTT6_FN),
+        PINMUX_DATA(D13_MARK, PTT5_FN),
+        PINMUX_DATA(D12_MARK, PTT4_FN),
+        PINMUX_DATA(D11_MARK, PTT3_FN),
+        PINMUX_DATA(D10_MARK, PTT2_FN),
+        PINMUX_DATA(D9_MARK,  PTT1_FN),
+        PINMUX_DATA(D8_MARK,  PTT0_FN),
+
+        /* PTU FN */
+        PINMUX_DATA(DMAC_DACK0_MARK, PTU7_FN),
+        PINMUX_DATA(DMAC_DREQ0_MARK, PTU6_FN),
+
+        PINMUX_DATA(FSIOASD_MARK,       PSE1_0, PTU5_FN),
+        PINMUX_DATA(FSIIABCK_MARK,      PSE1_0, PTU4_FN),
+        PINMUX_DATA(FSIIALRCK_MARK,     PSE1_0, PTU3_FN),
+        PINMUX_DATA(FSIOABCK_MARK,      PSE1_0, PTU2_FN),
+        PINMUX_DATA(FSIOALRCK_MARK,     PSE1_0, PTU1_FN),
+        PINMUX_DATA(CLKAUDIOAO_MARK,    PSE0_0, PTU0_FN),
+
+        /* PTV FN */
+        PINMUX_DATA(FSIIBSD_MARK,       PSD7_0,  PSD6_0,  PTV7_FN),
+        PINMUX_DATA(FSIOBSD_MARK,       PSD7_0,  PSD6_0,  PTV6_FN),
+        PINMUX_DATA(FSIIBBCK_MARK,      PSC15_0, PSC14_0, PTV5_FN),
+        PINMUX_DATA(FSIIBLRCK_MARK,     PSC15_0, PSC14_0, PTV4_FN),
+        PINMUX_DATA(FSIOBBCK_MARK,      PSC15_0, PSC14_0, PTV3_FN),
+        PINMUX_DATA(FSIOBLRCK_MARK,     PSC15_0, PSC14_0, PTV2_FN),
+        PINMUX_DATA(CLKAUDIOBO_MARK,    PSE3_0,  PSE2_0,  PTV1_FN),
+        PINMUX_DATA(FSIIASD_MARK,       PSE10_0,          PTV0_FN),
+
+        PINMUX_DATA(MSIOF1_SS2_MARK,    PSD7_0,  PSD6_1,  PTV7_FN),
+        PINMUX_DATA(MSIOF1_RSYNC_MARK,  PSD7_1,  PSD6_0,  PTV7_FN),
+        PINMUX_DATA(MSIOF1_SS1_MARK,    PSD7_0,  PSD6_1,  PTV6_FN),
+        PINMUX_DATA(MSIOF1_RSCK_MARK,   PSD7_1,  PSD6_0,  PTV6_FN),
+        PINMUX_DATA(MSIOF1_RXD_MARK,    PSC15_0, PSC14_1, PTV5_FN),
+        PINMUX_DATA(MSIOF1_TSYNC_MARK,  PSC15_0, PSC14_1, PTV4_FN),
+        PINMUX_DATA(MSIOF1_TSCK_MARK,   PSC15_0, PSC14_1, PTV3_FN),
+        PINMUX_DATA(MSIOF1_TXD_MARK,    PSC15_0, PSC14_1, PTV2_FN),
+        PINMUX_DATA(MSIOF1_MCK_MARK,    PSE3_0,  PSE2_1,  PTV1_FN),
+
+        /* PTW FN */
+        PINMUX_DATA(MMC_D7_MARK,        PSE13_0, PSE12_0, PTW7_FN),
+        PINMUX_DATA(MMC_D6_MARK,        PSE13_0, PSE12_0, PTW6_FN),
+        PINMUX_DATA(MMC_D5_MARK,        PSE13_0, PSE12_0, PTW5_FN),
+        PINMUX_DATA(MMC_D4_MARK,        PSE13_0, PSE12_0, PTW4_FN),
+        PINMUX_DATA(MMC_D3_MARK,        PSA13_0,          PTW3_FN),
+        PINMUX_DATA(MMC_D2_MARK,        PSA13_0,          PTW2_FN),
+        PINMUX_DATA(MMC_D1_MARK,        PSA13_0,          PTW1_FN),
+        PINMUX_DATA(MMC_D0_MARK,        PSA13_0,          PTW0_FN),
+
+        PINMUX_DATA(SDHI1CD_MARK,       PSE13_0, PSE12_1, PTW7_FN),
+        PINMUX_DATA(SDHI1WP_MARK,       PSE13_0, PSE12_1, PTW6_FN),
+        PINMUX_DATA(SDHI1D3_MARK,       PSE13_0, PSE12_1, PTW5_FN),
+        PINMUX_DATA(SDHI1D2_MARK,       PSE13_0, PSE12_1, PTW4_FN),
+        PINMUX_DATA(SDHI1D1_MARK,       PSA13_1,          PTW3_FN),
+        PINMUX_DATA(SDHI1D0_MARK,       PSA13_1,          PTW2_FN),
+        PINMUX_DATA(SDHI1CMD_MARK,      PSA13_1,          PTW1_FN),
+        PINMUX_DATA(SDHI1CLK_MARK,      PSA13_1,          PTW0_FN),
+
+        PINMUX_DATA(IODACK_MARK,        PSE13_1, PSE12_0, PTW7_FN),
+        PINMUX_DATA(IDERST_MARK,        PSE13_1, PSE12_0, PTW6_FN),
+        PINMUX_DATA(EXBUF_ENB_MARK,     PSE13_1, PSE12_0, PTW5_FN),
+        PINMUX_DATA(DIRECTION_MARK,     PSE13_1, PSE12_0, PTW4_FN),
+
+        /* PTX FN */
+        PINMUX_DATA(DMAC_DACK1_MARK,    PSA12_0, PTX7_FN),
+        PINMUX_DATA(DMAC_DREQ1_MARK,    PSA12_0, PTX6_FN),
+
+        PINMUX_DATA(IRDA_OUT_MARK,      PSA12_1, PTX7_FN),
+        PINMUX_DATA(IRDA_IN_MARK,       PSA12_1, PTX6_FN),
+
+        PINMUX_DATA(TSIF_TS0_SDAT_MARK, PSC0_0, PTX5_FN),
+        PINMUX_DATA(TSIF_TS0_SCK_MARK,  PSC1_0, PTX4_FN),
+        PINMUX_DATA(TSIF_TS0_SDEN_MARK, PSC2_0, PTX3_FN),
+        PINMUX_DATA(TSIF_TS0_SPSYNC_MARK,       PTX2_FN),
+
+        PINMUX_DATA(LNKSTA_MARK,        PSC0_1, PTX5_FN),
+        PINMUX_DATA(MDIO_MARK,          PSC1_1, PTX4_FN),
+        PINMUX_DATA(MDC_MARK,           PSC2_1, PTX3_FN),
+
+        PINMUX_DATA(MMC_CLK_MARK, PTX1_FN),
+        PINMUX_DATA(MMC_CMD_MARK, PTX0_FN),
+
+        /* PTY FN */
+        PINMUX_DATA(SDHI0CD_MARK,  PTY7_FN),
+        PINMUX_DATA(SDHI0WP_MARK,  PTY6_FN),
+        PINMUX_DATA(SDHI0D3_MARK,  PTY5_FN),
+        PINMUX_DATA(SDHI0D2_MARK,  PTY4_FN),
+        PINMUX_DATA(SDHI0D1_MARK,  PTY3_FN),
+        PINMUX_DATA(SDHI0D0_MARK,  PTY2_FN),
+        PINMUX_DATA(SDHI0CMD_MARK, PTY1_FN),
+        PINMUX_DATA(SDHI0CLK_MARK, PTY0_FN),
+
+        /* PTZ FN */
+        PINMUX_DATA(INTC_IRQ7_MARK,     PSB10_0, PTZ7_FN),
+        PINMUX_DATA(INTC_IRQ6_MARK,     PSB11_0, PTZ6_FN),
+        PINMUX_DATA(INTC_IRQ5_MARK,     PSB12_0, PTZ5_FN),
+        PINMUX_DATA(INTC_IRQ4_MARK,     PSB13_0, PTZ4_FN),
+        PINMUX_DATA(INTC_IRQ3_MARK,     PSB14_0, PTZ3_FN),
+        PINMUX_DATA(INTC_IRQ2_MARK,              PTZ2_FN),
+        PINMUX_DATA(INTC_IRQ1_MARK,              PTZ1_FN),
+        PINMUX_DATA(INTC_IRQ0_MARK,              PTZ0_FN),
+
+        PINMUX_DATA(SCIF3_I_CTS_MARK,   PSB10_1, PTZ7_FN),
+        PINMUX_DATA(SCIF3_I_RTS_MARK,   PSB11_1, PTZ6_FN),
+        PINMUX_DATA(SCIF3_I_SCK_MARK,   PSB12_1, PTZ5_FN),
+        PINMUX_DATA(SCIF3_I_RXD_MARK,   PSB13_1, PTZ4_FN),
+        PINMUX_DATA(SCIF3_I_TXD_MARK,   PSB14_1, PTZ3_FN),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+        /* PTA */
+        PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
+        PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
+        PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
+        PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
+        PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
+        PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
+        PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
+        PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
+
+        /* PTB */
+        PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
+        PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
+        PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
+        PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
+        PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
+        PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
+        PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
+        PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
+
+        /* PTC */
+        PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
+        PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
+        PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
+        PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
+        PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
+        PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
+        PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
+        PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
+
+        /* PTD */
+        PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
+        PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
+        PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
+        PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
+        PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
+        PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
+        PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
+        PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
+
+        /* PTE */
+        PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
+        PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
+        PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
+        PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
+        PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
+        PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
+        PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
+        PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
+
+        /* PTF */
+        PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
+        PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
+        PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
+        PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
+        PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
+        PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
+        PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
+        PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
+
+        /* PTG */
+        PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
+        PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
+        PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
+        PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
+        PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
+        PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
+
+        /* PTH */
+        PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
+        PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
+        PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
+        PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
+        PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
+        PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
+        PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
+        PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
+
+        /* PTJ */
+        PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
+        PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
+        PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
+        PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
+        PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
+        PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
+        PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
+
+        /* PTK */
+        PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
+        PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
+        PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
+        PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
+        PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
+        PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
+        PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
+        PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
+
+        /* PTL */
+        PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
+        PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
+        PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
+        PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
+        PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
+        PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
+        PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
+        PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
+
+        /* PTM */
+        PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
+        PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
+        PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
+        PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
+        PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
+        PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
+        PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
+        PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
+
+        /* PTN */
+        PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
+        PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
+        PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
+        PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
+        PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
+        PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
+        PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
+        PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
+
+        /* PTQ */
+        PINMUX_GPIO(GPIO_PTQ7, PTQ7_DATA),
+        PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
+        PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
+        PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
+        PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
+        PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
+        PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
+        PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
+
+        /* PTR */
+        PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
+        PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
+        PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
+        PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
+        PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
+        PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
+        PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
+        PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
+
+        /* PTS */
+        PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
+        PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
+        PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
+        PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
+        PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
+        PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
+        PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
+
+        /* PTT */
+        PINMUX_GPIO(GPIO_PTT7, PTT7_DATA),
+        PINMUX_GPIO(GPIO_PTT6, PTT6_DATA),
+        PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
+        PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
+        PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
+        PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
+        PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
+        PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
+
+        /* PTU */
+        PINMUX_GPIO(GPIO_PTU7, PTU7_DATA),
+        PINMUX_GPIO(GPIO_PTU6, PTU6_DATA),
+        PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
+        PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
+        PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
+        PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
+        PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
+        PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
+
+        /* PTV */
+        PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
+        PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
+        PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
+        PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
+        PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
+        PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
+        PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
+        PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
+
+        /* PTW */
+        PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
+        PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
+        PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
+        PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
+        PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
+        PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
+        PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
+        PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
+
+        /* PTX */
+        PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
+        PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
+        PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
+        PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
+        PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
+        PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
+        PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
+        PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
+
+        /* PTY */
+        PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
+        PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
+        PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
+        PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
+        PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
+        PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
+        PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
+        PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
+
+        /* PTZ */
+        PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
+        PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
+        PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
+        PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
+        PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
+        PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
+        PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
+        PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
+
+        /* BSC */
+        PINMUX_GPIO(GPIO_FN_D31,        D31_MARK),
+        PINMUX_GPIO(GPIO_FN_D30,        D30_MARK),
+        PINMUX_GPIO(GPIO_FN_D29,        D29_MARK),
+        PINMUX_GPIO(GPIO_FN_D28,        D28_MARK),
+        PINMUX_GPIO(GPIO_FN_D27,        D27_MARK),
+        PINMUX_GPIO(GPIO_FN_D26,        D26_MARK),
+        PINMUX_GPIO(GPIO_FN_D25,        D25_MARK),
+        PINMUX_GPIO(GPIO_FN_D24,        D24_MARK),
+        PINMUX_GPIO(GPIO_FN_D23,        D23_MARK),
+        PINMUX_GPIO(GPIO_FN_D22,        D22_MARK),
+        PINMUX_GPIO(GPIO_FN_D21,        D21_MARK),
+        PINMUX_GPIO(GPIO_FN_D20,        D20_MARK),
+        PINMUX_GPIO(GPIO_FN_D19,        D19_MARK),
+        PINMUX_GPIO(GPIO_FN_D18,        D18_MARK),
+        PINMUX_GPIO(GPIO_FN_D17,        D17_MARK),
+        PINMUX_GPIO(GPIO_FN_D16,        D16_MARK),
+        PINMUX_GPIO(GPIO_FN_D15,        D15_MARK),
+        PINMUX_GPIO(GPIO_FN_D14,        D14_MARK),
+        PINMUX_GPIO(GPIO_FN_D13,        D13_MARK),
+        PINMUX_GPIO(GPIO_FN_D12,        D12_MARK),
+        PINMUX_GPIO(GPIO_FN_D11,        D11_MARK),
+        PINMUX_GPIO(GPIO_FN_D10,        D10_MARK),
+        PINMUX_GPIO(GPIO_FN_D9,         D9_MARK),
+        PINMUX_GPIO(GPIO_FN_D8,         D8_MARK),
+        PINMUX_GPIO(GPIO_FN_D7,         D7_MARK),
+        PINMUX_GPIO(GPIO_FN_D6,         D6_MARK),
+        PINMUX_GPIO(GPIO_FN_D5,         D5_MARK),
+        PINMUX_GPIO(GPIO_FN_D4,         D4_MARK),
+        PINMUX_GPIO(GPIO_FN_D3,         D3_MARK),
+        PINMUX_GPIO(GPIO_FN_D2,         D2_MARK),
+        PINMUX_GPIO(GPIO_FN_D1,         D1_MARK),
+        PINMUX_GPIO(GPIO_FN_D0,         D0_MARK),
+        PINMUX_GPIO(GPIO_FN_A25,        A25_MARK),
+        PINMUX_GPIO(GPIO_FN_A24,        A24_MARK),
+        PINMUX_GPIO(GPIO_FN_A23,        A23_MARK),
+        PINMUX_GPIO(GPIO_FN_A22,        A22_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6B_CE1B,  CS6B_CE1B_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6A_CE2B,  CS6A_CE2B_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5B_CE1A,  CS5B_CE1A_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5A_CE2A,  CS5A_CE2A_MARK),
+        PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK),
+        PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK),
+        PINMUX_GPIO(GPIO_FN_IOIS16,     IOIS16_MARK),
+        PINMUX_GPIO(GPIO_FN_WAIT,       WAIT_MARK),
+        PINMUX_GPIO(GPIO_FN_BS,         BS_MARK),
+
+        /* KEYSC */
+        PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5,        KEYOUT5_IN5_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6,        KEYOUT4_IN6_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN4,             KEYIN4_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN3,             KEYIN3_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN2,             KEYIN2_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN1,             KEYIN1_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN0,             KEYIN0_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT3,            KEYOUT3_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT2,            KEYOUT2_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT1,            KEYOUT1_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT0,            KEYOUT0_MARK),
+
+        /* ATAPI */
+        PINMUX_GPIO(GPIO_FN_IDED15,     IDED15_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED14,     IDED14_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED13,     IDED13_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED12,     IDED12_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED11,     IDED11_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED10,     IDED10_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED9,      IDED9_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED8,      IDED8_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED7,      IDED7_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED6,      IDED6_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED5,      IDED5_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED4,      IDED4_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED3,      IDED3_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED2,      IDED2_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED1,      IDED1_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED0,      IDED0_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEA2,      IDEA2_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEA1,      IDEA1_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEA0,      IDEA0_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEIOWR,    IDEIOWR_MARK),
+        PINMUX_GPIO(GPIO_FN_IODREQ,     IODREQ_MARK),
+        PINMUX_GPIO(GPIO_FN_IDECS0,     IDECS0_MARK),
+        PINMUX_GPIO(GPIO_FN_IDECS1,     IDECS1_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEIORD,    IDEIORD_MARK),
+        PINMUX_GPIO(GPIO_FN_DIRECTION,  DIRECTION_MARK),
+        PINMUX_GPIO(GPIO_FN_EXBUF_ENB,  EXBUF_ENB_MARK),
+        PINMUX_GPIO(GPIO_FN_IDERST,     IDERST_MARK),
+        PINMUX_GPIO(GPIO_FN_IODACK,     IODACK_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEINT,     IDEINT_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEIORDY,   IDEIORDY_MARK),
+
+        /* TPU */
+        PINMUX_GPIO(GPIO_FN_TPUTO3,     TPUTO3_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTO2,     TPUTO2_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTO1,     TPUTO1_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTO0,     TPUTO0_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTI3,     TPUTI3_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTI2,     TPUTI2_MARK),
+
+        /* LCDC */
+        PINMUX_GPIO(GPIO_FN_LCDD23,     LCDD23_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD22,     LCDD22_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD21,     LCDD21_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD20,     LCDD20_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD19,     LCDD19_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD18,     LCDD18_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD17,     LCDD17_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD16,     LCDD16_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD15,     LCDD15_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD14,     LCDD14_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD13,     LCDD13_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD12,     LCDD12_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD11,     LCDD11_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD10,     LCDD10_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD9,      LCDD9_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD8,      LCDD8_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD7,      LCDD7_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD6,      LCDD6_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD5,      LCDD5_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD4,      LCDD4_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD3,      LCDD3_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD2,      LCDD2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD1,      LCDD1_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD0,      LCDD0_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVSYN,    LCDVSYN_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDDISP,    LCDDISP_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDRS,      LCDRS_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDHSYN,    LCDHSYN_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDCS,      LCDCS_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDDON,     LCDDON_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDDCK,     LCDDCK_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDWR,      LCDWR_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVEPWC,   LCDVEPWC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVCPWC,   LCDVCPWC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDRD,      LCDRD_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDLCLK,    LCDLCLK_MARK),
+
+        /* SCIF0 */
+        PINMUX_GPIO(GPIO_FN_SCIF0_TXD,  SCIF0_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_RXD,  SCIF0_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_SCK,  SCIF0_SCK_MARK),
+
+        /* SCIF1 */
+        PINMUX_GPIO(GPIO_FN_SCIF1_SCK,  SCIF1_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_RXD,  SCIF1_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_TXD,  SCIF1_TXD_MARK),
+
+        /* SCIF2 */
+        PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD,        SCIF2_L_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK,        SCIF2_L_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD,        SCIF2_L_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD,        SCIF2_V_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK,        SCIF2_V_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD,        SCIF2_V_RXD_MARK),
+
+        /* SCIF3 */
+        PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK,        SCIF3_V_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD,        SCIF3_V_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD,        SCIF3_V_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS,        SCIF3_V_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS,        SCIF3_V_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK,        SCIF3_I_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD,        SCIF3_I_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD,        SCIF3_I_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS,        SCIF3_I_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS,        SCIF3_I_RTS_MARK),
+
+        /* SCIF4 */
+        PINMUX_GPIO(GPIO_FN_SCIF4_SCK,  SCIF4_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF4_RXD,  SCIF4_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF4_TXD,  SCIF4_TXD_MARK),
+
+        /* SCIF5 */
+        PINMUX_GPIO(GPIO_FN_SCIF5_SCK,  SCIF5_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF5_RXD,  SCIF5_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF5_TXD,  SCIF5_TXD_MARK),
+
+        /* FSI */
+        PINMUX_GPIO(GPIO_FN_FSIMCKB,    FSIMCKB_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIMCKA,    FSIMCKA_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOASD,    FSIOASD_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIABCK,   FSIIABCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIALRCK,  FSIIALRCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOABCK,   FSIOABCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOALRCK,  FSIOALRCK_MARK),
+        PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIBSD,    FSIIBSD_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOBSD,    FSIOBSD_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIBBCK,   FSIIBBCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIBLRCK,  FSIIBLRCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOBBCK,   FSIOBBCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOBLRCK,  FSIOBLRCK_MARK),
+        PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIASD,    FSIIASD_MARK),
+
+        /* AUD */
+        PINMUX_GPIO(GPIO_FN_AUDCK,      AUDCK_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDSYNC,    AUDSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA3,    AUDATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA2,    AUDATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA1,    AUDATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA0,    AUDATA0_MARK),
+
+        /* VIO */
+        PINMUX_GPIO(GPIO_FN_VIO_CKO,    VIO_CKO_MARK),
+
+        /* VIO0 */
+        PINMUX_GPIO(GPIO_FN_VIO0_D15,   VIO0_D15_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D14,   VIO0_D14_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D13,   VIO0_D13_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D12,   VIO0_D12_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D11,   VIO0_D11_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D10,   VIO0_D10_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D9,    VIO0_D9_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D8,    VIO0_D8_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D7,    VIO0_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D6,    VIO0_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D5,    VIO0_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D4,    VIO0_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D3,    VIO0_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D2,    VIO0_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D1,    VIO0_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D0,    VIO0_D0_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_VD,    VIO0_VD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_CLK,   VIO0_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_FLD,   VIO0_FLD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_HD,    VIO0_HD_MARK),
+
+        /* VIO1 */
+        PINMUX_GPIO(GPIO_FN_VIO1_D7,    VIO1_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D6,    VIO1_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D5,    VIO1_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D4,    VIO1_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D3,    VIO1_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D2,    VIO1_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D1,    VIO1_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D0,    VIO1_D0_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_FLD,   VIO1_FLD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_HD,    VIO1_HD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_VD,    VIO1_VD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_CLK,   VIO1_CLK_MARK),
+
+        /* Eth */
+        PINMUX_GPIO(GPIO_FN_RMII_RXD0,          RMII_RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_RXD1,          RMII_RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_TXD0,          RMII_TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_TXD1,          RMII_TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_REF_CLK,       RMII_REF_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_TX_EN,         RMII_TX_EN_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_RX_ER,         RMII_RX_ER_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_CRS_DV,        RMII_CRS_DV_MARK),
+        PINMUX_GPIO(GPIO_FN_LNKSTA,             LNKSTA_MARK),
+        PINMUX_GPIO(GPIO_FN_MDIO,               MDIO_MARK),
+        PINMUX_GPIO(GPIO_FN_MDC,                MDC_MARK),
+
+        /* System */
+        PINMUX_GPIO(GPIO_FN_PDSTATUS,   PDSTATUS_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS2,    STATUS2_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS0,    STATUS0_MARK),
+
+        /* VOU */
+        PINMUX_GPIO(GPIO_FN_DV_D15,     DV_D15_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D14,     DV_D14_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D13,     DV_D13_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D12,     DV_D12_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D11,     DV_D11_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D10,     DV_D10_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D9,      DV_D9_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D8,      DV_D8_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D7,      DV_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D6,      DV_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D5,      DV_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D4,      DV_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D3,      DV_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D2,      DV_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D1,      DV_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D0,      DV_D0_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_CLKI,    DV_CLKI_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_CLK,     DV_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_VSYNC,   DV_VSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_HSYNC,   DV_HSYNC_MARK),
+
+        /* MSIOF0 */
+        PINMUX_GPIO(GPIO_FN_MSIOF0_RXD,         MSIOF0_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_TXD,         MSIOF0_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_MCK,         MSIOF0_MCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK,        MSIOF0_TSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_SS1,         MSIOF0_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_SS2,         MSIOF0_SS2_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC,       MSIOF0_TSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK,        MSIOF0_RSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC,       MSIOF0_RSYNC_MARK),
+
+        /* MSIOF1 */
+        PINMUX_GPIO(GPIO_FN_MSIOF1_RXD,         MSIOF1_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_TXD,         MSIOF1_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_MCK,         MSIOF1_MCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK,        MSIOF1_TSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_SS1,         MSIOF1_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_SS2,         MSIOF1_SS2_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC,       MSIOF1_TSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK,        MSIOF1_RSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC,       MSIOF1_RSYNC_MARK),
+
+        /* DMAC */
+        PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK),
+        PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK),
+        PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK),
+
+        /* SDHI0 */
+        PINMUX_GPIO(GPIO_FN_SDHI0CD,    SDHI0CD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0WP,    SDHI0WP_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0CMD,   SDHI0CMD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0CLK,   SDHI0CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D3,    SDHI0D3_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D2,    SDHI0D2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D1,    SDHI0D1_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D0,    SDHI0D0_MARK),
+
+        /* SDHI1 */
+        PINMUX_GPIO(GPIO_FN_SDHI1CD,    SDHI1CD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1WP,    SDHI1WP_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1CMD,   SDHI1CMD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1CLK,   SDHI1CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D3,    SDHI1D3_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D2,    SDHI1D2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D1,    SDHI1D1_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D0,    SDHI1D0_MARK),
+
+        /* MMC */
+        PINMUX_GPIO(GPIO_FN_MMC_D7,     MMC_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D6,     MMC_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D5,     MMC_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D4,     MMC_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D3,     MMC_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D2,     MMC_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D1,     MMC_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D0,     MMC_D0_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_CLK,    MMC_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_CMD,    MMC_CMD_MARK),
+
+        /* IrDA */
+        PINMUX_GPIO(GPIO_FN_IRDA_OUT,   IRDA_OUT_MARK),
+        PINMUX_GPIO(GPIO_FN_IRDA_IN,    IRDA_IN_MARK),
+
+        /* TSIF */
+        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT,      TSIF_TS0_SDAT_MARK),
+        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK,       TSIF_TS0_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN,      TSIF_TS0_SDEN_MARK),
+        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC,    TSIF_TS0_SPSYNC_MARK),
+
+        /* IRQ */
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ7,  INTC_IRQ7_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ6,  INTC_IRQ6_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ5,  INTC_IRQ5_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ4,  INTC_IRQ4_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ3,  INTC_IRQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ2,  INTC_IRQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ1,  INTC_IRQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ0,  INTC_IRQ0_MARK),
+ };
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
+                PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
+                PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
+                PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN,
+                PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
+                PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
+                PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
+                PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
+                PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
+        },
+        { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
+                PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN,
+                PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN,
+                PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN,
+                PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN,
+                PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN,
+                PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN,
+                PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN,
+                PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN }
+        },
+        { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
+                PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN,
+                PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN,
+                PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN,
+                PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN,
+                PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN,
+                PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN,
+                PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN,
+                PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN }
+        },
+        { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
+                PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN,
+                PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
+                PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
+                PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
+                PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
+                PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
+                PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
+                PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN }
+        },
+        { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
+                PTE7_FN, PTE7_OUT, PTE7_IN_PU, PTE7_IN,
+                PTE6_FN, PTE6_OUT, PTE6_IN_PU, PTE6_IN,
+                PTE5_FN, PTE5_OUT, PTE5_IN_PU, PTE5_IN,
+                PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN,
+                PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN,
+                PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN,
+                PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN,
+                PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN }
+        },
+        { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
+                PTF7_FN, PTF7_OUT, PTF7_IN_PU, PTF7_IN,
+                PTF6_FN, PTF6_OUT, PTF6_IN_PU, PTF6_IN,
+                PTF5_FN, PTF5_OUT, PTF5_IN_PU, PTF5_IN,
+                PTF4_FN, PTF4_OUT, PTF4_IN_PU, PTF4_IN,
+                PTF3_FN, PTF3_OUT, PTF3_IN_PU, PTF3_IN,
+                PTF2_FN, PTF2_OUT, PTF2_IN_PU, PTF2_IN,
+                PTF1_FN, PTF1_OUT, PTF1_IN_PU, PTF1_IN,
+                PTF0_FN, PTF0_OUT, PTF0_IN_PU, PTF0_IN }
+        },
+        { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTG5_FN, PTG5_OUT, 0, 0,
+                PTG4_FN, PTG4_OUT, 0, 0,
+                PTG3_FN, PTG3_OUT, 0, 0,
+                PTG2_FN, PTG2_OUT, 0, 0,
+                PTG1_FN, PTG1_OUT, 0, 0,
+                PTG0_FN, PTG0_OUT, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
+                PTH7_FN, PTH7_OUT, PTH7_IN_PU, PTH7_IN,
+                PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN,
+                PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN,
+                PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN,
+                PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN,
+                PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN,
+                PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN,
+                PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN }
+        },
+        { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
+                PTJ7_FN, PTJ7_OUT, 0, 0,
+                PTJ6_FN, PTJ6_OUT, 0, 0,
+                PTJ5_FN, PTJ5_OUT, 0, 0,
+                0, 0, 0, 0,
+                PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN,
+                PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN,
+                PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
+                PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
+        },
+        { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
+                PTK7_FN, PTK7_OUT, PTK7_IN_PU, PTK7_IN,
+                PTK6_FN, PTK6_OUT, PTK6_IN_PU, PTK6_IN,
+                PTK5_FN, PTK5_OUT, PTK5_IN_PU, PTK5_IN,
+                PTK4_FN, PTK4_OUT, PTK4_IN_PU, PTK4_IN,
+                PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN,
+                PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN,
+                PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN,
+                PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN }
+        },
+        { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
+                PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN,
+                PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN,
+                PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN,
+                PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN,
+                PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN,
+                PTL2_FN, PTL2_OUT, PTL2_IN_PU, PTL2_IN,
+                PTL1_FN, PTL1_OUT, PTL1_IN_PU, PTL1_IN,
+                PTL0_FN, PTL0_OUT, PTL0_IN_PU, PTL0_IN }
+        },
+        { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
+                PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN,
+                PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN,
+                PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN,
+                PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN,
+                PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN,
+                PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN,
+                PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN,
+                PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN }
+        },
+        { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
+                PTN7_FN, PTN7_OUT, PTN7_IN_PU, PTN7_IN,
+                PTN6_FN, PTN6_OUT, PTN6_IN_PU, PTN6_IN,
+                PTN5_FN, PTN5_OUT, PTN5_IN_PU, PTN5_IN,
+                PTN4_FN, PTN4_OUT, PTN4_IN_PU, PTN4_IN,
+                PTN3_FN, PTN3_OUT, PTN3_IN_PU, PTN3_IN,
+                PTN2_FN, PTN2_OUT, PTN2_IN_PU, PTN2_IN,
+                PTN1_FN, PTN1_OUT, PTN1_IN_PU, PTN1_IN,
+                PTN0_FN, PTN0_OUT, PTN0_IN_PU, PTN0_IN }
+        },
+        { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
+                PTQ7_FN, PTQ7_OUT, PTQ7_IN_PU, PTQ7_IN,
+                PTQ6_FN, PTQ6_OUT, PTQ6_IN_PU, PTQ6_IN,
+                PTQ5_FN, PTQ5_OUT, PTQ5_IN_PU, PTQ5_IN,
+                PTQ4_FN, PTQ4_OUT, PTQ4_IN_PU, PTQ4_IN,
+                PTQ3_FN, PTQ3_OUT, PTQ3_IN_PU, PTQ3_IN,
+                PTQ2_FN, PTQ2_OUT, PTQ2_IN_PU, PTQ2_IN,
+                PTQ1_FN, PTQ1_OUT, PTQ1_IN_PU, PTQ1_IN,
+                PTQ0_FN, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN }
+        },
+        { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
+                PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN,
+                PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN,
+                PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN,
+                PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN,
+                PTR3_FN, 0,        PTR3_IN_PU, PTR3_IN,
+                PTR2_FN, 0,        PTR2_IN_PU, PTR2_IN,
+                PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN,
+                PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN }
+        },
+        { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
+                0, 0, 0, 0,
+                PTS6_FN, PTS6_OUT, PTS6_IN_PU, PTS6_IN,
+                PTS5_FN, PTS5_OUT, PTS5_IN_PU, PTS5_IN,
+                PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN,
+                PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN,
+                PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN,
+                PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN,
+                PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN }
+        },
+        { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
+                PTT7_FN, PTT7_OUT, PTT7_IN_PU, PTT7_IN,
+                PTT6_FN, PTT6_OUT, PTT6_IN_PU, PTT6_IN,
+                PTT5_FN, PTT5_OUT, PTT5_IN_PU, PTT5_IN,
+                PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN,
+                PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN,
+                PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN,
+                PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN,
+                PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN }
+        },
+        { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
+                PTU7_FN, PTU7_OUT, PTU7_IN_PU, PTU7_IN,
+                PTU6_FN, PTU6_OUT, PTU6_IN_PU, PTU6_IN,
+                PTU5_FN, PTU5_OUT, PTU5_IN_PU, PTU5_IN,
+                PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN,
+                PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN,
+                PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN,
+                PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN,
+                PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN }
+        },
+        { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
+                PTV7_FN, PTV7_OUT, PTV7_IN_PU, PTV7_IN,
+                PTV6_FN, PTV6_OUT, PTV6_IN_PU, PTV6_IN,
+                PTV5_FN, PTV5_OUT, PTV5_IN_PU, PTV5_IN,
+                PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN,
+                PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN,
+                PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN,
+                PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN,
+                PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN }
+        },
+        { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
+                PTW7_FN, PTW7_OUT, PTW7_IN_PU, PTW7_IN,
+                PTW6_FN, PTW6_OUT, PTW6_IN_PU, PTW6_IN,
+                PTW5_FN, PTW5_OUT, PTW5_IN_PU, PTW5_IN,
+                PTW4_FN, PTW4_OUT, PTW4_IN_PU, PTW4_IN,
+                PTW3_FN, PTW3_OUT, PTW3_IN_PU, PTW3_IN,
+                PTW2_FN, PTW2_OUT, PTW2_IN_PU, PTW2_IN,
+                PTW1_FN, PTW1_OUT, PTW1_IN_PU, PTW1_IN,
+                PTW0_FN, PTW0_OUT, PTW0_IN_PU, PTW0_IN }
+        },
+        { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
+                PTX7_FN, PTX7_OUT, PTX7_IN_PU, PTX7_IN,
+                PTX6_FN, PTX6_OUT, PTX6_IN_PU, PTX6_IN,
+                PTX5_FN, PTX5_OUT, PTX5_IN_PU, PTX5_IN,
+                PTX4_FN, PTX4_OUT, PTX4_IN_PU, PTX4_IN,
+                PTX3_FN, PTX3_OUT, PTX3_IN_PU, PTX3_IN,
+                PTX2_FN, PTX2_OUT, PTX2_IN_PU, PTX2_IN,
+                PTX1_FN, PTX1_OUT, PTX1_IN_PU, PTX1_IN,
+                PTX0_FN, PTX0_OUT, PTX0_IN_PU, PTX0_IN }
+        },
+        { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
+                PTY7_FN, PTY7_OUT, PTY7_IN_PU, PTY7_IN,
+                PTY6_FN, PTY6_OUT, PTY6_IN_PU, PTY6_IN,
+                PTY5_FN, PTY5_OUT, PTY5_IN_PU, PTY5_IN,
+                PTY4_FN, PTY4_OUT, PTY4_IN_PU, PTY4_IN,
+                PTY3_FN, PTY3_OUT, PTY3_IN_PU, PTY3_IN,
+                PTY2_FN, PTY2_OUT, PTY2_IN_PU, PTY2_IN,
+                PTY1_FN, PTY1_OUT, PTY1_IN_PU, PTY1_IN,
+                PTY0_FN, PTY0_OUT, PTY0_IN_PU, PTY0_IN }
+        },
+        { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
+                PTZ7_FN, PTZ7_OUT, PTZ7_IN_PU, PTZ7_IN,
+                PTZ6_FN, PTZ6_OUT, PTZ6_IN_PU, PTZ6_IN,
+                PTZ5_FN, PTZ5_OUT, PTZ5_IN_PU, PTZ5_IN,
+                PTZ4_FN, PTZ4_OUT, PTZ4_IN_PU, PTZ4_IN,
+                PTZ3_FN, PTZ3_OUT, PTZ3_IN_PU, PTZ3_IN,
+                PTZ2_FN, PTZ2_OUT, PTZ2_IN_PU, PTZ2_IN,
+                PTZ1_FN, PTZ1_OUT, PTZ1_IN_PU, PTZ1_IN,
+                PTZ0_FN, PTZ0_OUT, PTZ0_IN_PU, PTZ0_IN }
+        },
+        { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) {
+                PSA15_0, PSA15_1,
+                PSA14_0, PSA14_1,
+                PSA13_0, PSA13_1,
+                PSA12_0, PSA12_1,
+                0, 0,
+                PSA10_0, PSA10_1,
+                PSA9_0,  PSA9_1,
+                PSA8_0,  PSA8_1,
+                PSA7_0,  PSA7_1,
+                PSA6_0,  PSA6_1,
+                PSA5_0,  PSA5_1,
+                0, 0,
+                PSA3_0,  PSA3_1,
+                PSA2_0,  PSA2_1,
+                PSA1_0,  PSA1_1,
+                PSA0_0,  PSA0_1}
+        },
+        { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) {
+                0, 0,
+                PSB14_0, PSB14_1,
+                PSB13_0, PSB13_1,
+                PSB12_0, PSB12_1,
+                PSB11_0, PSB11_1,
+                PSB10_0, PSB10_1,
+                PSB9_0,  PSB9_1,
+                PSB8_0,  PSB8_1,
+                PSB7_0,  PSB7_1,
+                PSB6_0,  PSB6_1,
+                PSB5_0,  PSB5_1,
+                PSB4_0,  PSB4_1,
+                PSB3_0,  PSB3_1,
+                PSB2_0,  PSB2_1,
+                PSB1_0,  PSB1_1,
+                PSB0_0,  PSB0_1}
+        },
+        { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) {
+                PSC15_0, PSC15_1,
+                PSC14_0, PSC14_1,
+                PSC13_0, PSC13_1,
+                PSC12_0, PSC12_1,
+                PSC11_0, PSC11_1,
+                PSC10_0, PSC10_1,
+                PSC9_0,  PSC9_1,
+                PSC8_0,  PSC8_1,
+                PSC7_0,  PSC7_1,
+                PSC6_0,  PSC6_1,
+                PSC5_0,  PSC5_1,
+                PSC4_0,  PSC4_1,
+                0, 0,
+                PSC2_0,  PSC2_1,
+                PSC1_0,  PSC1_1,
+                PSC0_0,  PSC0_1}
+        },
+        { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) {
+                PSD15_0, PSD15_1,
+                PSD14_0, PSD14_1,
+                PSD13_0, PSD13_1,
+                PSD12_0, PSD12_1,
+                PSD11_0, PSD11_1,
+                PSD10_0, PSD10_1,
+                PSD9_0,  PSD9_1,
+                PSD8_0,  PSD8_1,
+                PSD7_0,  PSD7_1,
+                PSD6_0,  PSD6_1,
+                PSD5_0,  PSD5_1,
+                PSD4_0,  PSD4_1,
+                PSD3_0,  PSD3_1,
+                PSD2_0,  PSD2_1,
+                PSD1_0,  PSD1_1,
+                PSD0_0,  PSD0_1}
+        },
+        { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) {
+                PSE15_0, PSE15_1,
+                PSE14_0, PSE14_1,
+                PSE13_0, PSE13_1,
+                PSE12_0, PSE12_1,
+                PSE11_0, PSE11_1,
+                PSE10_0, PSE10_1,
+                PSE9_0,  PSE9_1,
+                PSE8_0,  PSE8_1,
+                PSE7_0,  PSE7_1,
+                PSE6_0,  PSE6_1,
+                PSE5_0,  PSE5_1,
+                PSE4_0,  PSE4_1,
+                PSE3_0,  PSE3_1,
+                PSE2_0,  PSE2_1,
+                PSE1_0,  PSE1_1,
+                PSE0_0,  PSE0_1}
+        },
+        {}
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
+                PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+                PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
+        },
+        { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
+                PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+                PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
+        },
+        { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
+                PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+                PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
+        },
+        { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
+                PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+                PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
+        },
+        { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
+                PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
+                PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
+        },
+        { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
+                PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+                PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
+        },
+        { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
+                0,         0,         PTG5_DATA, PTG4_DATA,
+                PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
+        },
+        { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
+                PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+                PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
+        },
+        { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
+                PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
+                PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
+        },
+        { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
+                PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
+                PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
+        },
+        { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
+                PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+                PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
+        },
+        { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
+                PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+                PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
+        },
+        { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
+                PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+                PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
+        },
+        { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
+                PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
+                PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
+        },
+        { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
+                PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+                PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
+        },
+        { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
+                0,         PTS6_DATA, PTS5_DATA, PTS4_DATA,
+                PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
+        },
+        { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
+                PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
+                PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
+        },
+        { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
+                PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
+                PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
+        },
+        { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
+                PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
+                PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
+        },
+        { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
+                PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
+                PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
+        },
+        { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
+                PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
+                PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
+        },
+        { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
+                PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
+                PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
+        },
+        { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
+                PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
+                PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh7724_pinmux_info = {
+        .name = "sh7724_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PTA7,
+        .last_gpio = GPIO_FN_INTC_IRQ0,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+static int __init plat_pinmux_setup(void)
+{
+        return register_pinmux(&sh7724_pinmux_info);
+}
+arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index c1549382c87c..cb5b4db1ca25 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -234,6 +234,16 @@ static int __init sh7343_devices_setup(void)
 }
 __initcall(sh7343_devices_setup);
 
+static struct platform_device *sh7343_early_devices[] __initdata = {
+        &cmt_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7343_early_devices,
+                                   ARRAY_SIZE(sh7343_early_devices));
+}
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 93ecf8ed5c6c..2a771f48e9e0 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -226,6 +226,16 @@ static int __init sh7366_devices_setup(void)
 }
 __initcall(sh7366_devices_setup);
 
+static struct platform_device *sh7366_early_devices[] __initdata = {
+        &cmt_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7366_early_devices,
+                                   ARRAY_SIZE(sh7366_early_devices));
+}
+
 enum {
         UNUSED=0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 406747f07dc0..793c50da6a84 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -269,6 +269,16 @@ static int __init sh7722_devices_setup(void)
 }
 __initcall(sh7722_devices_setup);
 
+static struct platform_device *sh7722_early_devices[] __initdata = {
+        &cmt_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7722_early_devices,
+                                   ARRAY_SIZE(sh7722_early_devices));
+}
+
 enum {
         UNUSED=0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index a800466b938c..dbb44949ed19 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -280,6 +280,16 @@ static int __init sh7723_devices_setup(void)
 }
 __initcall(sh7723_devices_setup);
 
+static struct platform_device *sh7723_early_devices[] __initdata = {
+        &cmt_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7723_early_devices,
+                                   ARRAY_SIZE(sh7723_early_devices));
+}
+
 enum {
         UNUSED=0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
new file mode 100644
index 000000000000..8429396acb59
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -0,0 +1,556 @@
+/*
+ * SH7724 Setup
+ *
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ *
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * Based on SH7723 Setup
+ * Copyright (C) 2008  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/mm.h>
+#include <linux/serial_sci.h>
+#include <linux/uio_driver.h>
+#include <linux/sh_cmt.h>
+#include <linux/io.h>
+#include <asm/clock.h>
+#include <asm/mmzone.h>
+
+/* Serial */
+static struct plat_sci_port sci_platform_data[] = {
+        {
+                .mapbase        = 0xffe00000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 80, 80, 80, 80 },
+        }, {
+                .mapbase        = 0xffe10000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 81, 81, 81, 81 },
+        }, {
+                .mapbase        = 0xffe20000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 82, 82, 82, 82 },
+        }, {
+                .mapbase        = 0xa4e30000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIFA,
+                .irqs           = { 56, 56, 56, 56 },
+        }, {
+                .mapbase        = 0xa4e40000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIFA,
+                .irqs           = { 88, 88, 88, 88 },
+        }, {
+                .mapbase        = 0xa4e50000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIFA,
+                .irqs           = { 109, 109, 109, 109 },
+        }, {
+                .flags = 0,
+        }
+};
+
+static struct platform_device sci_device = {
+        .name           = "sh-sci",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = sci_platform_data,
+        },
+};
+
+/* RTC */
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = 0xa465fec0,
+                .end    = 0xa465fec0 + 0x58 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        [1] = {
+                /* Period IRQ */
+                .start  = 69,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* Carry IRQ */
+                .start  = 70,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                /* Alarm IRQ */
+                .start  = 68,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device rtc_device = {
+        .name           = "sh-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(rtc_resources),
+        .resource       = rtc_resources,
+};
+
+/* I2C0 */
+static struct resource iic0_resources[] = {
+        [0] = {
+                .name   = "IIC0",
+                .start  = 0x04470000,
+                .end    = 0x04470018 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 96,
+                .end    = 99,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device iic0_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 0, /* "i2c0" clock */
+        .num_resources  = ARRAY_SIZE(iic0_resources),
+        .resource       = iic0_resources,
+};
+
+/* I2C1 */
+static struct resource iic1_resources[] = {
+        [0] = {
+                .name   = "IIC1",
+                .start  = 0x04750000,
+                .end    = 0x04750018 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 92,
+                .end    = 95,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device iic1_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 1, /* "i2c1" clock */
+        .num_resources  = ARRAY_SIZE(iic1_resources),
+        .resource       = iic1_resources,
+};
+
+/* VPU */
+static struct uio_info vpu_platform_data = {
+        .name = "VPU5F",
+        .version = "0",
+        .irq = 60,
+};
+
+static struct resource vpu_resources[] = {
+        [0] = {
+                .name   = "VPU",
+                .start  = 0xfe900000,
+                .end    = 0xfe902807,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device vpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &vpu_platform_data,
+        },
+        .resource       = vpu_resources,
+        .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+/* VEU0 */
+static struct uio_info veu0_platform_data = {
+        .name = "VEU3F0",
+        .version = "0",
+        .irq = 83,
+};
+
+static struct resource veu0_resources[] = {
+        [0] = {
+                .name   = "VEU3F0",
+                .start  = 0xfe920000,
+                .end    = 0xfe9200cb - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device veu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &veu0_platform_data,
+        },
+        .resource       = veu0_resources,
+        .num_resources  = ARRAY_SIZE(veu0_resources),
+};
+
+/* VEU1 */
+static struct uio_info veu1_platform_data = {
+        .name = "VEU3F1",
+        .version = "0",
+        .irq = 54,
+};
+
+static struct resource veu1_resources[] = {
+        [0] = {
+                .name   = "VEU3F1",
+                .start  = 0xfe924000,
+                .end    = 0xfe9240cb - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device veu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &veu1_platform_data,
+        },
+        .resource       = veu1_resources,
+        .num_resources  = ARRAY_SIZE(veu1_resources),
+};
+
+static struct sh_cmt_config cmt_platform_data = {
+        .name = "CMT",
+        .channel_offset = 0x60,
+        .timer_bit = 5,
+        .clk = "cmt0",
+        .clockevent_rating = 125,
+        .clocksource_rating = 200,
+};
+
+static struct resource cmt_resources[] = {
+        [0] = {
+                .name   = "CMT",
+                .start  = 0x044a0060,
+                .end    = 0x044a006b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 104,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt_device = {
+        .name           = "sh_cmt",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &cmt_platform_data,
+        },
+        .resource       = cmt_resources,
+        .num_resources  = ARRAY_SIZE(cmt_resources),
+};
+
+static struct platform_device *sh7724_devices[] __initdata = {
+        &cmt_device,
+        &sci_device,
+        &rtc_device,
+        &iic0_device,
+        &iic1_device,
+        &vpu_device,
+        &veu0_device,
+        &veu1_device,
+};
+
+static int __init sh7724_devices_setup(void)
+{
+        clk_always_enable("vpu0");   /* VPU */
+        clk_always_enable("veu1");   /* VEU3F1 */
+        clk_always_enable("veu0");   /* VEU3F0 */
+
+        platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
+        platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
+        platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
+
+        return platform_add_devices(sh7724_devices,
+                                    ARRAY_SIZE(sh7724_devices));
+}
+device_initcall(sh7724_devices_setup);
+
+static struct platform_device *sh7724_early_devices[] __initdata = {
+        &cmt_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7724_early_devices,
+                                   ARRAY_SIZE(sh7724_early_devices));
+}
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources */
+        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+        HUDI,
+        DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
+        _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK,
+        DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
+        VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI,
+        SCIFA_SCIFA0,
+        VPU_VPUI,
+        TPU_TPUI,
+        CEU21I,
+        BEU21I,
+        USB_USI0,
+        ATAPI,
+        RTC_ATI, RTC_PRI, RTC_CUI,
+        DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
+        DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
+        KEYSC_KEYI,
+        SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
+        VEU3F0I,
+        MSIOF_MSIOFI0, MSIOF_MSIOFI1,
+        SPU_SPUI0, SPU_SPUI1,
+        SCIFA_SCIFA1,
+/*      ICB_ICBI, */
+        ETHI,
+        I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
+        I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
+        SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2,
+        CMT_CMTI,
+        TSIF_TSIFI,
+/*      ICB_LMBI, */
+        FSI_FSI,
+        SCIFA_SCIFA2,
+        TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
+        IRDA_IRDAI,
+        SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
+        JPU_JPUI,
+        MMC_MMCI0, MMC_MMCI1, MMC_MMCI2,
+        LCDC_LCDCI,
+        TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
+
+        /* interrupt groups */
+        DMAC1A, _2DG, DMAC0A, VIO, RTC,
+        DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMC,
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
+        INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
+        INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
+        INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
+
+        INTC_VECT(DMAC1A_DEI0, 0x700),
+        INTC_VECT(DMAC1A_DEI1, 0x720),
+        INTC_VECT(DMAC1A_DEI2, 0x740),
+        INTC_VECT(DMAC1A_DEI3, 0x760),
+
+        INTC_VECT(_2DG_TRI, 0x780),
+        INTC_VECT(_2DG_INI, 0x7A0),
+        INTC_VECT(_2DG_CEI, 0x7C0),
+        INTC_VECT(_2DG_BRK, 0x7E0),
+
+        INTC_VECT(DMAC0A_DEI0, 0x800),
+        INTC_VECT(DMAC0A_DEI1, 0x820),
+        INTC_VECT(DMAC0A_DEI2, 0x840),
+        INTC_VECT(DMAC0A_DEI3, 0x860),
+
+        INTC_VECT(VIO_CEU20I, 0x880),
+        INTC_VECT(VIO_BEU20I, 0x8A0),
+        INTC_VECT(VIO_VEU3F1, 0x8C0),
+        INTC_VECT(VIO_VOUI, 0x8E0),
+
+        INTC_VECT(SCIFA_SCIFA0, 0x900),
+        INTC_VECT(VPU_VPUI, 0x980),
+        INTC_VECT(TPU_TPUI, 0x9A0),
+        INTC_VECT(CEU21I, 0x9E0),
+        INTC_VECT(BEU21I, 0xA00),
+        INTC_VECT(USB_USI0, 0xA20),
+        INTC_VECT(ATAPI, 0xA60),
+
+        INTC_VECT(RTC_ATI, 0xA80),
+        INTC_VECT(RTC_PRI, 0xAA0),
+        INTC_VECT(RTC_CUI, 0xAC0),
+
+        INTC_VECT(DMAC1B_DEI4, 0xB00),
+        INTC_VECT(DMAC1B_DEI5, 0xB20),
+        INTC_VECT(DMAC1B_DADERR, 0xB40),
+
+        INTC_VECT(DMAC0B_DEI4, 0xB80),
+        INTC_VECT(DMAC0B_DEI5, 0xBA0),
+        INTC_VECT(DMAC0B_DADERR, 0xBC0),
+
+        INTC_VECT(KEYSC_KEYI, 0xBE0),
+        INTC_VECT(SCIF_SCIF0, 0xC00),
+        INTC_VECT(SCIF_SCIF1, 0xC20),
+        INTC_VECT(SCIF_SCIF2, 0xC40),
+        INTC_VECT(VEU3F0I, 0xC60),
+        INTC_VECT(MSIOF_MSIOFI0, 0xC80),
+        INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
+        INTC_VECT(SPU_SPUI0, 0xCC0),
+        INTC_VECT(SPU_SPUI1, 0xCE0),
+        INTC_VECT(SCIFA_SCIFA1, 0xD00),
+
+/*      INTC_VECT(ICB_ICBI, 0xD20), */
+        INTC_VECT(ETHI, 0xD60),
+
+        INTC_VECT(I2C1_ALI, 0xD80),
+        INTC_VECT(I2C1_TACKI, 0xDA0),
+        INTC_VECT(I2C1_WAITI, 0xDC0),
+        INTC_VECT(I2C1_DTEI, 0xDE0),
+
+        INTC_VECT(I2C0_ALI, 0xE00),
+        INTC_VECT(I2C0_TACKI, 0xE20),
+        INTC_VECT(I2C0_WAITI, 0xE40),
+        INTC_VECT(I2C0_DTEI, 0xE60),
+
+        INTC_VECT(SDHI0_SDHII0, 0xE80),
+        INTC_VECT(SDHI0_SDHII1, 0xEA0),
+        INTC_VECT(SDHI0_SDHII2, 0xEC0),
+
+        INTC_VECT(CMT_CMTI, 0xF00),
+        INTC_VECT(TSIF_TSIFI, 0xF20),
+/*      INTC_VECT(ICB_LMBI, 0xF60), */
+        INTC_VECT(FSI_FSI, 0xF80),
+        INTC_VECT(SCIFA_SCIFA2, 0xFA0),
+
+        INTC_VECT(TMU0_TUNI0, 0x400),
+        INTC_VECT(TMU0_TUNI1, 0x420),
+        INTC_VECT(TMU0_TUNI2, 0x440),
+
+        INTC_VECT(IRDA_IRDAI, 0x480),
+
+        INTC_VECT(SDHI1_SDHII0, 0x4E0),
+        INTC_VECT(SDHI1_SDHII1, 0x500),
+        INTC_VECT(SDHI1_SDHII2, 0x520),
+
+        INTC_VECT(JPU_JPUI, 0x560),
+
+        INTC_VECT(MMC_MMCI0, 0x580),
+        INTC_VECT(MMC_MMCI1, 0x5A0),
+        INTC_VECT(MMC_MMCI2, 0x5C0),
+
+        INTC_VECT(LCDC_LCDCI, 0xF40),
+
+        INTC_VECT(TMU1_TUNI0, 0x920),
+        INTC_VECT(TMU1_TUNI1, 0x940),
+        INTC_VECT(TMU1_TUNI2, 0x960),
+};
+
+static struct intc_group groups[] __initdata = {
+        INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
+        INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK),
+        INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
+        INTC_GROUP(VIO, VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI),
+        INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
+        INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
+        INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
+        INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
+        INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
+        INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2),
+        INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
+        INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
+        INTC_GROUP(MMC, MMC_MMCI0, MMC_MMCI1, MMC_MMCI2),
+};
+
+/* FIXMEEEEEEEEEEEEEEEEEEE !!!!! */
+/* very bad manual !! */
+static struct intc_mask_reg mask_registers[] __initdata = {
+        { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
+          { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
+            /*SDHII3?*/0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
+        { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
+          { VIO_VOUI, VIO_VEU3F1, VIO_BEU20I, VIO_CEU20I,
+            DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
+        { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
+          { 0, 0, 0, VPU_VPUI, ATAPI, ETHI, 0, /*SCIFA3*/SCIFA_SCIFA0 } },
+        { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
+          { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
+            SPU_SPUI1, SPU_SPUI0, BEU21I, IRDA_IRDAI } },
+        { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
+          { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
+            JPU_JPUI, 0, 0, LCDC_LCDCI } },
+        { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
+          { KEYSC_KEYI, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
+            VEU3F0I, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
+        { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
+          { 0, 0, /*ICB_ICBI*/0, /*SCIFA4*/SCIFA_SCIFA1,
+            CEU21I, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
+        { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
+          { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
+            I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
+        { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
+          { /*SDHII3*/0, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
+            0, 0, /*SCIFA5*/SCIFA_SCIFA2, FSI_FSI } },
+        { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
+          { 0, 0, 0, CMT_CMTI, 0, /*USB1*/0, USB_USI0, 0 } },
+        { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
+          { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
+            0, RTC_ATI, RTC_PRI, RTC_CUI } },
+        { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
+          { _2DG_BRK, _2DG_CEI, _2DG_INI, _2DG_TRI,
+            0, TPU_TPUI, /*ICB_LMBI*/0, TSIF_TSIFI } },
+        { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
+          { 0, 0, 0, 0, 0, 0, 0, 0/*2DDMAC*/ } },
+        { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
+                                             TMU0_TUNI2, IRDA_IRDAI } },
+        { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU_JPUI, LCDC_LCDCI,
+                                             DMAC1A, BEU21I } },
+        { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
+                                             TMU1_TUNI2, SPU } },
+        { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMC, 0, ATAPI } },
+        { 0xa4080010, 0, 16, 4, /* IPRE */
+          { DMAC0A, /*BEU?VEU?*/VIO, /*SCIFA3*/SCIFA_SCIFA0, /*VPU5F*/
+            VPU_VPUI } },
+        { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B,
+                                             USB_USI0, CMT_CMTI } },
+        { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
+                                             SCIF_SCIF2, VEU3F0I } },
+        { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
+                                             I2C1, I2C0 } },
+        { 0xa4080020, 0, 16, 4, /* IPRI */ { /*SCIFA4*/SCIFA_SCIFA1, /*ICB*/0,
+                                             TSIF_TSIFI, _2DG/*ICB?*/ } },
+        { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU21I, ETHI, FSI_FSI, SDHI1 } },
+        { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, /*ICB?*/0, SDHI0 } },
+        { 0xa408002c, 0, 16, 4, /* IPRL */ { /*SCIFA5*/SCIFA_SCIFA2, 0,
+                                             TPU_TPUI, /*2DDMAC*/0 } },
+        { 0xa4140010, 0, 32, 4, /* INTPRI00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_sense_reg sense_registers[] __initdata = {
+        { 0xa414001c, 16, 2, /* ICR1 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_mask_reg ack_registers[] __initdata = {
+        { 0xa4140024, 0, 8, /* INTREQ00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
+                             mask_registers, prio_registers, sense_registers,
+                             ack_registers);
+
+void __init plat_irq_setup(void)
+{
+        register_intc_controller(&intc_desc);
+}
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 04a6004fccc4..38515a795920 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -29,6 +29,7 @@
 #include <linux/mmzone.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/platform_device.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/page.h>
@@ -328,6 +329,10 @@ static int __init parse_elfcorehdr(char *arg)
 early_param("elfcorehdr", parse_elfcorehdr);
 #endif
 
+void __init __attribute__ ((weak)) plat_early_device_setup(void)
+{
+}
+
 void __init setup_arch(char **cmdline_p)
 {
         enable_mmu();
@@ -381,6 +386,8 @@ void __init setup_arch(char **cmdline_p)
 
         parse_early_param();
 
+        plat_early_device_setup();
+
         sh_mv_setup();
 
         /*
@@ -435,7 +442,8 @@ static const char *cpu_name[] = {
         [CPU_SH7722]    = "SH7722",     [CPU_SHX3]      = "SH-X3",
         [CPU_SH5_101]   = "SH5-101",    [CPU_SH5_103]   = "SH5-103",
         [CPU_MXG]       = "MX-G",       [CPU_SH7723]    = "SH7723",
-        [CPU_SH7366]    = "SH7366",     [CPU_SH_NONE]   = "Unknown"
+        [CPU_SH7366]    = "SH7366",     [CPU_SH7724]    = "SH7724",
+        [CPU_SH_NONE]   = "Unknown"
 };
 
 const char *get_cpu_subtype(struct sh_cpuinfo *c)
diff --git a/arch/sh/kernel/time_32.c b/arch/sh/kernel/time_32.c
index 1700d2465f6c..c770413c3213 100644
--- a/arch/sh/kernel/time_32.c
+++ b/arch/sh/kernel/time_32.c
@@ -17,6 +17,7 @@
 #include <linux/sched.h>
 #include <linux/clockchips.h>
 #include <linux/mc146818rtc.h>  /* for rtc_lock */
+#include <linux/platform_device.h>
 #include <linux/smp.h>
 #include <asm/clock.h>
 #include <asm/rtc.h>
@@ -229,6 +230,14 @@ void __init time_init(void)
 #endif
 
         /*
+         * Make sure all compiled-in early timers register themselves.
+         * Run probe() for one "earlytimer" device.
+         */
+        early_platform_driver_register_all("earlytimer");
+        if (early_platform_driver_probe("earlytimer", 1, 0))
+                return;
+
+        /*
          * Find the timer to use as the system timer, it will be
          * initialized for us.
          */
diff --git a/arch/sh/oprofile/common.c b/arch/sh/oprofile/common.c
index 1b9d4304b3bf..44f4e31c6d63 100644
--- a/arch/sh/oprofile/common.c
+++ b/arch/sh/oprofile/common.c
@@ -109,6 +109,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
         case CPU_SH7785:
         case CPU_SH7786:
         case CPU_SH7723:
+        case CPU_SH7724:
         case CPU_SHX3:
                 lmodel = &op_model_sh4a_ops;
                 break;
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 1c92c39a53aa..02bae3994abe 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -566,9 +566,19 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
 static int __devinit sh_cmt_probe(struct platform_device *pdev)
 {
         struct sh_cmt_priv *p = platform_get_drvdata(pdev);
+        struct sh_cmt_config *cfg = pdev->dev.platform_data;
         int ret;
 
-        p = kmalloc(sizeof(*p), GFP_KERNEL);
+        if (p) {
+                pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name);
+                return 0;
+        }
+
+        if (is_early_platform_device(pdev))
+                p = alloc_bootmem(sizeof(*p));
+        else
+                p = kmalloc(sizeof(*p), GFP_KERNEL);
+
         if (p == NULL) {
                 dev_err(&pdev->dev, "failed to allocate driver data\n");
                 return -ENOMEM;
@@ -576,7 +586,10 @@ static int __devinit sh_cmt_probe(struct platform_device *pdev)
 
         ret = sh_cmt_setup(p, pdev);
         if (ret) {
-                kfree(p);
+                if (is_early_platform_device(pdev))
+                        free_bootmem(__pa(p), sizeof(*p));
+                else
+                        kfree(p);
 
                 platform_set_drvdata(pdev, NULL);
         }
@@ -606,6 +619,7 @@ static void __exit sh_cmt_exit(void)
         platform_driver_unregister(&sh_cmt_device_driver);
 }
 
+early_platform_init("earlytimer", &sh_cmt_device_driver);
 module_init(sh_cmt_init);
 module_exit(sh_cmt_exit);
 
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index d0aa82d7fce0..84cc6512f081 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -91,6 +91,9 @@
 # define SCSPTR5                0xa4050128
 # define SCIF_ORER              0x0001  /* overrun error bit */
 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
+# define SCIF_ORER              0x0001  /* overrun error bit */
+# define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001   /* overrun error bit */
@@ -361,7 +364,8 @@
                  h8_sci_offset, h8_sci_size) \
   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
+      defined(CONFIG_CPU_SUBTYPE_SH7724)
         #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
                 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
         #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
@@ -390,7 +394,8 @@ SCIF_FNS(SCFDR,  0x1c, 16)
 SCIF_FNS(SCxTDR, 0x20,  8)
 SCIF_FNS(SCxRDR, 0x24,  8)
 SCIF_FNS(SCLSR,  0x24, 16)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
+      defined(CONFIG_CPU_SUBTYPE_SH7724)
 SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
 SCIx_FNS(SCBRR,  0x04,  8, 0x04,  8)
 SCIx_FNS(SCSCR,  0x08, 16, 0x08, 16)
@@ -604,6 +609,17 @@ static inline int sci_rxd_in(struct uart_port *port)
                 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
         return 1;
 }
+#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
+#  define SCFSR    0x0010
+#  define SCASSR   0x0014
+static inline int sci_rxd_in(struct uart_port *port)
+{
+        if (port->type == PORT_SCIF)
+                return ctrl_inw((port->mapbase + SCFSR))  & SCIF_BRK ? 1 : 0;
+        if (port->type == PORT_SCIFA)
+                return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0;
+        return 1;
+}
 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 static inline int sci_rxd_in(struct uart_port *port)
 {
@@ -757,7 +773,8 @@ static inline int sci_rxd_in(struct uart_port *port)
       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
       defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
+      defined(CONFIG_CPU_SUBTYPE_SH7724)
 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 {
         if (port->type == PORT_SCIF)