diff options
| -rw-r--r-- | arch/mips/include/asm/gic.h | 4 | ||||
| -rw-r--r-- | arch/mips/kernel/irq-gic.c | 15 |
2 files changed, 8 insertions, 11 deletions
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 954807d9d66a..e8fdd92c52c7 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h | |||
| @@ -20,7 +20,11 @@ | |||
| 20 | #define GIC_TRIG_EDGE 1 | 20 | #define GIC_TRIG_EDGE 1 |
| 21 | #define GIC_TRIG_LEVEL 0 | 21 | #define GIC_TRIG_LEVEL 0 |
| 22 | 22 | ||
| 23 | #if CONFIG_SMP | ||
| 24 | #define GIC_NUM_INTRS (24 + NR_CPUS * 2) | ||
| 25 | #else | ||
| 23 | #define GIC_NUM_INTRS 32 | 26 | #define GIC_NUM_INTRS 32 |
| 27 | #endif | ||
| 24 | 28 | ||
| 25 | #define MSK(n) ((1 << (n)) - 1) | 29 | #define MSK(n) ((1 << (n)) - 1) |
| 26 | #define REG32(addr) (*(volatile unsigned int *) (addr)) | 30 | #define REG32(addr) (*(volatile unsigned int *) (addr)) |
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 39000f103f2c..5c85e1ce0499 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c | |||
| @@ -107,9 +107,7 @@ static unsigned int gic_irq_startup(unsigned int irq) | |||
| 107 | { | 107 | { |
| 108 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | 108 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); |
| 109 | irq -= _irqbase; | 109 | irq -= _irqbase; |
| 110 | /* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */ | 110 | GIC_SET_INTR_MASK(irq, 1); |
| 111 | GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))), | ||
| 112 | 1 << (irq % 32)); | ||
| 113 | return 0; | 111 | return 0; |
| 114 | } | 112 | } |
| 115 | 113 | ||
| @@ -120,8 +118,7 @@ static void gic_irq_ack(unsigned int irq) | |||
| 120 | #endif | 118 | #endif |
| 121 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | 119 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); |
| 122 | irq -= _irqbase; | 120 | irq -= _irqbase; |
| 123 | GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))), | 121 | GIC_CLR_INTR_MASK(irq, 1); |
| 124 | 1 << (irq % 32)); | ||
| 125 | 122 | ||
| 126 | if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) { | 123 | if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) { |
| 127 | if (!gic_wedgeb2bok) | 124 | if (!gic_wedgeb2bok) |
| @@ -138,18 +135,14 @@ static void gic_mask_irq(unsigned int irq) | |||
| 138 | { | 135 | { |
| 139 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | 136 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); |
| 140 | irq -= _irqbase; | 137 | irq -= _irqbase; |
| 141 | /* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */ | 138 | GIC_CLR_INTR_MASK(irq, 1); |
| 142 | GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))), | ||
| 143 | 1 << (irq % 32)); | ||
| 144 | } | 139 | } |
| 145 | 140 | ||
| 146 | static void gic_unmask_irq(unsigned int irq) | 141 | static void gic_unmask_irq(unsigned int irq) |
| 147 | { | 142 | { |
| 148 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | 143 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); |
| 149 | irq -= _irqbase; | 144 | irq -= _irqbase; |
| 150 | /* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */ | 145 | GIC_SET_INTR_MASK(irq, 1); |
| 151 | GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))), | ||
| 152 | 1 << (irq % 32)); | ||
| 153 | } | 146 | } |
| 154 | 147 | ||
| 155 | #ifdef CONFIG_SMP | 148 | #ifdef CONFIG_SMP |
