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-rw-r--r--include/asm-powerpc/mmu-hash64.h400
-rw-r--r--include/asm-powerpc/mmu.h406
2 files changed, 406 insertions, 400 deletions
diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h
new file mode 100644
index 000000000000..6739457d8bc0
--- /dev/null
+++ b/include/asm-powerpc/mmu-hash64.h
@@ -0,0 +1,400 @@
1#ifndef _ASM_POWERPC_MMU_HASH64_H_
2#define _ASM_POWERPC_MMU_HASH64_H_
3/*
4 * PowerPC64 memory management structures
5 *
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
7 * PPC64 rework.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <asm/asm-compat.h>
16#include <asm/page.h>
17
18/*
19 * Segment table
20 */
21
22#define STE_ESID_V 0x80
23#define STE_ESID_KS 0x20
24#define STE_ESID_KP 0x10
25#define STE_ESID_N 0x08
26
27#define STE_VSID_SHIFT 12
28
29/* Location of cpu0's segment table */
30#define STAB0_PAGE 0x6
31#define STAB0_OFFSET (STAB0_PAGE << 12)
32#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
33
34#ifndef __ASSEMBLY__
35extern char initial_stab[];
36#endif /* ! __ASSEMBLY */
37
38/*
39 * SLB
40 */
41
42#define SLB_NUM_BOLTED 3
43#define SLB_CACHE_ENTRIES 8
44
45/* Bits in the SLB ESID word */
46#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
47
48/* Bits in the SLB VSID word */
49#define SLB_VSID_SHIFT 12
50#define SLB_VSID_B ASM_CONST(0xc000000000000000)
51#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
52#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
53#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
54#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
55#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
56#define SLB_VSID_L ASM_CONST(0x0000000000000100)
57#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
58#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
59#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
60#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
61#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
62#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
63#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
64
65#define SLB_VSID_KERNEL (SLB_VSID_KP)
66#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
67
68#define SLBIE_C (0x08000000)
69
70/*
71 * Hash table
72 */
73
74#define HPTES_PER_GROUP 8
75
76#define HPTE_V_AVPN_SHIFT 7
77#define HPTE_V_AVPN ASM_CONST(0xffffffffffffff80)
78#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
79#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & HPTE_V_AVPN))
80#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
81#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
82#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
83#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
84#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
85
86#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
87#define HPTE_R_TS ASM_CONST(0x4000000000000000)
88#define HPTE_R_RPN_SHIFT 12
89#define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
90#define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
91#define HPTE_R_PP ASM_CONST(0x0000000000000003)
92#define HPTE_R_N ASM_CONST(0x0000000000000004)
93#define HPTE_R_C ASM_CONST(0x0000000000000080)
94#define HPTE_R_R ASM_CONST(0x0000000000000100)
95
96/* Values for PP (assumes Ks=0, Kp=1) */
97/* pp0 will always be 0 for linux */
98#define PP_RWXX 0 /* Supervisor read/write, User none */
99#define PP_RWRX 1 /* Supervisor read/write, User read */
100#define PP_RWRW 2 /* Supervisor read/write, User read/write */
101#define PP_RXRX 3 /* Supervisor read, User read */
102
103#ifndef __ASSEMBLY__
104
105typedef struct {
106 unsigned long v;
107 unsigned long r;
108} hpte_t;
109
110extern hpte_t *htab_address;
111extern unsigned long htab_size_bytes;
112extern unsigned long htab_hash_mask;
113
114/*
115 * Page size definition
116 *
117 * shift : is the "PAGE_SHIFT" value for that page size
118 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
119 * directly to a slbmte "vsid" value
120 * penc : is the HPTE encoding mask for the "LP" field:
121 *
122 */
123struct mmu_psize_def
124{
125 unsigned int shift; /* number of bits */
126 unsigned int penc; /* HPTE encoding */
127 unsigned int tlbiel; /* tlbiel supported for that page size */
128 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
129 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
130};
131
132#endif /* __ASSEMBLY__ */
133
134/*
135 * The kernel use the constants below to index in the page sizes array.
136 * The use of fixed constants for this purpose is better for performances
137 * of the low level hash refill handlers.
138 *
139 * A non supported page size has a "shift" field set to 0
140 *
141 * Any new page size being implemented can get a new entry in here. Whether
142 * the kernel will use it or not is a different matter though. The actual page
143 * size used by hugetlbfs is not defined here and may be made variable
144 */
145
146#define MMU_PAGE_4K 0 /* 4K */
147#define MMU_PAGE_64K 1 /* 64K */
148#define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */
149#define MMU_PAGE_1M 3 /* 1M */
150#define MMU_PAGE_16M 4 /* 16M */
151#define MMU_PAGE_16G 5 /* 16G */
152#define MMU_PAGE_COUNT 6
153
154#ifndef __ASSEMBLY__
155
156/*
157 * The current system page sizes
158 */
159extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
160extern int mmu_linear_psize;
161extern int mmu_virtual_psize;
162extern int mmu_vmalloc_psize;
163extern int mmu_io_psize;
164
165/*
166 * If the processor supports 64k normal pages but not 64k cache
167 * inhibited pages, we have to be prepared to switch processes
168 * to use 4k pages when they create cache-inhibited mappings.
169 * If this is the case, mmu_ci_restrictions will be set to 1.
170 */
171extern int mmu_ci_restrictions;
172
173#ifdef CONFIG_HUGETLB_PAGE
174/*
175 * The page size index of the huge pages for use by hugetlbfs
176 */
177extern int mmu_huge_psize;
178
179#endif /* CONFIG_HUGETLB_PAGE */
180
181/*
182 * This function sets the AVPN and L fields of the HPTE appropriately
183 * for the page size
184 */
185static inline unsigned long hpte_encode_v(unsigned long va, int psize)
186{
187 unsigned long v =
188 v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
189 v <<= HPTE_V_AVPN_SHIFT;
190 if (psize != MMU_PAGE_4K)
191 v |= HPTE_V_LARGE;
192 return v;
193}
194
195/*
196 * This function sets the ARPN, and LP fields of the HPTE appropriately
197 * for the page size. We assume the pa is already "clean" that is properly
198 * aligned for the requested page size
199 */
200static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
201{
202 unsigned long r;
203
204 /* A 4K page needs no special encoding */
205 if (psize == MMU_PAGE_4K)
206 return pa & HPTE_R_RPN;
207 else {
208 unsigned int penc = mmu_psize_defs[psize].penc;
209 unsigned int shift = mmu_psize_defs[psize].shift;
210 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
211 }
212 return r;
213}
214
215/*
216 * This hashes a virtual address for a 256Mb segment only for now
217 */
218
219static inline unsigned long hpt_hash(unsigned long va, unsigned int shift)
220{
221 return ((va >> 28) & 0x7fffffffffUL) ^ ((va & 0x0fffffffUL) >> shift);
222}
223
224extern int __hash_page_4K(unsigned long ea, unsigned long access,
225 unsigned long vsid, pte_t *ptep, unsigned long trap,
226 unsigned int local);
227extern int __hash_page_64K(unsigned long ea, unsigned long access,
228 unsigned long vsid, pte_t *ptep, unsigned long trap,
229 unsigned int local);
230struct mm_struct;
231extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
232extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
233 unsigned long ea, unsigned long vsid, int local,
234 unsigned long trap);
235
236extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
237 unsigned long pstart, unsigned long mode,
238 int psize);
239
240extern void htab_initialize(void);
241extern void htab_initialize_secondary(void);
242extern void hpte_init_native(void);
243extern void hpte_init_lpar(void);
244extern void hpte_init_iSeries(void);
245extern void hpte_init_beat(void);
246
247extern void stabs_alloc(void);
248extern void slb_initialize(void);
249extern void slb_flush_and_rebolt(void);
250extern void stab_initialize(unsigned long stab);
251
252#endif /* __ASSEMBLY__ */
253
254/*
255 * VSID allocation
256 *
257 * We first generate a 36-bit "proto-VSID". For kernel addresses this
258 * is equal to the ESID, for user addresses it is:
259 * (context << 15) | (esid & 0x7fff)
260 *
261 * The two forms are distinguishable because the top bit is 0 for user
262 * addresses, whereas the top two bits are 1 for kernel addresses.
263 * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
264 * now.
265 *
266 * The proto-VSIDs are then scrambled into real VSIDs with the
267 * multiplicative hash:
268 *
269 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
270 * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
271 * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
272 *
273 * This scramble is only well defined for proto-VSIDs below
274 * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
275 * reserved. VSID_MULTIPLIER is prime, so in particular it is
276 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
277 * Because the modulus is 2^n-1 we can compute it efficiently without
278 * a divide or extra multiply (see below).
279 *
280 * This scheme has several advantages over older methods:
281 *
282 * - We have VSIDs allocated for every kernel address
283 * (i.e. everything above 0xC000000000000000), except the very top
284 * segment, which simplifies several things.
285 *
286 * - We allow for 15 significant bits of ESID and 20 bits of
287 * context for user addresses. i.e. 8T (43 bits) of address space for
288 * up to 1M contexts (although the page table structure and context
289 * allocation will need changes to take advantage of this).
290 *
291 * - The scramble function gives robust scattering in the hash
292 * table (at least based on some initial results). The previous
293 * method was more susceptible to pathological cases giving excessive
294 * hash collisions.
295 */
296/*
297 * WARNING - If you change these you must make sure the asm
298 * implementations in slb_allocate (slb_low.S), do_stab_bolted
299 * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
300 *
301 * You'll also need to change the precomputed VSID values in head.S
302 * which are used by the iSeries firmware.
303 */
304
305#define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */
306#define VSID_BITS 36
307#define VSID_MODULUS ((1UL<<VSID_BITS)-1)
308
309#define CONTEXT_BITS 19
310#define USER_ESID_BITS 16
311
312#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
313
314/*
315 * This macro generates asm code to compute the VSID scramble
316 * function. Used in slb_allocate() and do_stab_bolted. The function
317 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
318 *
319 * rt = register continaing the proto-VSID and into which the
320 * VSID will be stored
321 * rx = scratch register (clobbered)
322 *
323 * - rt and rx must be different registers
324 * - The answer will end up in the low 36 bits of rt. The higher
325 * bits may contain other garbage, so you may need to mask the
326 * result.
327 */
328#define ASM_VSID_SCRAMBLE(rt, rx) \
329 lis rx,VSID_MULTIPLIER@h; \
330 ori rx,rx,VSID_MULTIPLIER@l; \
331 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
332 \
333 srdi rx,rt,VSID_BITS; \
334 clrldi rt,rt,(64-VSID_BITS); \
335 add rt,rt,rx; /* add high and low bits */ \
336 /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
337 * 2^36-1+2^28-1. That in particular means that if r3 >= \
338 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
339 * the bit clear, r3 already has the answer we want, if it \
340 * doesn't, the answer is the low 36 bits of r3+1. So in all \
341 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
342 addi rx,rt,1; \
343 srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \
344 add rt,rt,rx
345
346
347#ifndef __ASSEMBLY__
348
349typedef unsigned long mm_context_id_t;
350
351typedef struct {
352 mm_context_id_t id;
353 u16 user_psize; /* page size index */
354 u16 sllp; /* SLB entry page size encoding */
355#ifdef CONFIG_HUGETLB_PAGE
356 u16 low_htlb_areas, high_htlb_areas;
357#endif
358 unsigned long vdso_base;
359} mm_context_t;
360
361
362static inline unsigned long vsid_scramble(unsigned long protovsid)
363{
364#if 0
365 /* The code below is equivalent to this function for arguments
366 * < 2^VSID_BITS, which is all this should ever be called
367 * with. However gcc is not clever enough to compute the
368 * modulus (2^n-1) without a second multiply. */
369 return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
370#else /* 1 */
371 unsigned long x;
372
373 x = protovsid * VSID_MULTIPLIER;
374 x = (x >> VSID_BITS) + (x & VSID_MODULUS);
375 return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
376#endif /* 1 */
377}
378
379/* This is only valid for addresses >= KERNELBASE */
380static inline unsigned long get_kernel_vsid(unsigned long ea)
381{
382 return vsid_scramble(ea >> SID_SHIFT);
383}
384
385/* This is only valid for user addresses (which are below 2^41) */
386static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
387{
388 return vsid_scramble((context << USER_ESID_BITS)
389 | (ea >> SID_SHIFT));
390}
391
392#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
393#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
394
395/* Physical address used by some IO functions */
396typedef unsigned long phys_addr_t;
397
398#endif /* __ASSEMBLY__ */
399
400#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
index e22fd8811505..06b3e6d336cb 100644
--- a/include/asm-powerpc/mmu.h
+++ b/include/asm-powerpc/mmu.h
@@ -2,408 +2,14 @@
2#define _ASM_POWERPC_MMU_H_ 2#define _ASM_POWERPC_MMU_H_
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#ifndef CONFIG_PPC64 5#ifdef CONFIG_PPC64
6#include <asm-ppc/mmu.h> 6/* 64-bit classic hash table MMU */
7# include <asm/mmu-hash64.h>
7#else 8#else
8 9/* 32-bit. FIXME: split up the 32-bit MMU types, and revise for
9/* 10 * arch/powerpc */
10 * PowerPC memory management structures 11# include <asm-ppc/mmu.h>
11 *
12 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
13 * PPC64 rework.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21#include <asm/asm-compat.h>
22#include <asm/page.h>
23
24/*
25 * Segment table
26 */
27
28#define STE_ESID_V 0x80
29#define STE_ESID_KS 0x20
30#define STE_ESID_KP 0x10
31#define STE_ESID_N 0x08
32
33#define STE_VSID_SHIFT 12
34
35/* Location of cpu0's segment table */
36#define STAB0_PAGE 0x6
37#define STAB0_OFFSET (STAB0_PAGE << 12)
38#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
39
40#ifndef __ASSEMBLY__
41extern char initial_stab[];
42#endif /* ! __ASSEMBLY */
43
44/*
45 * SLB
46 */
47
48#define SLB_NUM_BOLTED 3
49#define SLB_CACHE_ENTRIES 8
50
51/* Bits in the SLB ESID word */
52#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
53
54/* Bits in the SLB VSID word */
55#define SLB_VSID_SHIFT 12
56#define SLB_VSID_B ASM_CONST(0xc000000000000000)
57#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
58#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
59#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
60#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
61#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
62#define SLB_VSID_L ASM_CONST(0x0000000000000100)
63#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
64#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
65#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
66#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
67#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
68#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
69#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
70
71#define SLB_VSID_KERNEL (SLB_VSID_KP)
72#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
73
74#define SLBIE_C (0x08000000)
75
76/*
77 * Hash table
78 */
79
80#define HPTES_PER_GROUP 8
81
82#define HPTE_V_AVPN_SHIFT 7
83#define HPTE_V_AVPN ASM_CONST(0xffffffffffffff80)
84#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
85#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & HPTE_V_AVPN))
86#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
87#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
88#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
89#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
90#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
91
92#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
93#define HPTE_R_TS ASM_CONST(0x4000000000000000)
94#define HPTE_R_RPN_SHIFT 12
95#define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
96#define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
97#define HPTE_R_PP ASM_CONST(0x0000000000000003)
98#define HPTE_R_N ASM_CONST(0x0000000000000004)
99#define HPTE_R_C ASM_CONST(0x0000000000000080)
100#define HPTE_R_R ASM_CONST(0x0000000000000100)
101
102/* Values for PP (assumes Ks=0, Kp=1) */
103/* pp0 will always be 0 for linux */
104#define PP_RWXX 0 /* Supervisor read/write, User none */
105#define PP_RWRX 1 /* Supervisor read/write, User read */
106#define PP_RWRW 2 /* Supervisor read/write, User read/write */
107#define PP_RXRX 3 /* Supervisor read, User read */
108
109#ifndef __ASSEMBLY__
110
111typedef struct {
112 unsigned long v;
113 unsigned long r;
114} hpte_t;
115
116extern hpte_t *htab_address;
117extern unsigned long htab_size_bytes;
118extern unsigned long htab_hash_mask;
119
120/*
121 * Page size definition
122 *
123 * shift : is the "PAGE_SHIFT" value for that page size
124 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
125 * directly to a slbmte "vsid" value
126 * penc : is the HPTE encoding mask for the "LP" field:
127 *
128 */
129struct mmu_psize_def
130{
131 unsigned int shift; /* number of bits */
132 unsigned int penc; /* HPTE encoding */
133 unsigned int tlbiel; /* tlbiel supported for that page size */
134 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
135 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
136};
137
138#endif /* __ASSEMBLY__ */
139
140/*
141 * The kernel use the constants below to index in the page sizes array.
142 * The use of fixed constants for this purpose is better for performances
143 * of the low level hash refill handlers.
144 *
145 * A non supported page size has a "shift" field set to 0
146 *
147 * Any new page size being implemented can get a new entry in here. Whether
148 * the kernel will use it or not is a different matter though. The actual page
149 * size used by hugetlbfs is not defined here and may be made variable
150 */
151
152#define MMU_PAGE_4K 0 /* 4K */
153#define MMU_PAGE_64K 1 /* 64K */
154#define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */
155#define MMU_PAGE_1M 3 /* 1M */
156#define MMU_PAGE_16M 4 /* 16M */
157#define MMU_PAGE_16G 5 /* 16G */
158#define MMU_PAGE_COUNT 6
159
160#ifndef __ASSEMBLY__
161
162/*
163 * The current system page sizes
164 */
165extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
166extern int mmu_linear_psize;
167extern int mmu_virtual_psize;
168extern int mmu_vmalloc_psize;
169extern int mmu_io_psize;
170
171/*
172 * If the processor supports 64k normal pages but not 64k cache
173 * inhibited pages, we have to be prepared to switch processes
174 * to use 4k pages when they create cache-inhibited mappings.
175 * If this is the case, mmu_ci_restrictions will be set to 1.
176 */
177extern int mmu_ci_restrictions;
178
179#ifdef CONFIG_HUGETLB_PAGE
180/*
181 * The page size index of the huge pages for use by hugetlbfs
182 */
183extern int mmu_huge_psize;
184
185#endif /* CONFIG_HUGETLB_PAGE */
186
187/*
188 * This function sets the AVPN and L fields of the HPTE appropriately
189 * for the page size
190 */
191static inline unsigned long hpte_encode_v(unsigned long va, int psize)
192{
193 unsigned long v =
194 v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
195 v <<= HPTE_V_AVPN_SHIFT;
196 if (psize != MMU_PAGE_4K)
197 v |= HPTE_V_LARGE;
198 return v;
199}
200
201/*
202 * This function sets the ARPN, and LP fields of the HPTE appropriately
203 * for the page size. We assume the pa is already "clean" that is properly
204 * aligned for the requested page size
205 */
206static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
207{
208 unsigned long r;
209
210 /* A 4K page needs no special encoding */
211 if (psize == MMU_PAGE_4K)
212 return pa & HPTE_R_RPN;
213 else {
214 unsigned int penc = mmu_psize_defs[psize].penc;
215 unsigned int shift = mmu_psize_defs[psize].shift;
216 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
217 }
218 return r;
219}
220
221/*
222 * This hashes a virtual address for a 256Mb segment only for now
223 */
224
225static inline unsigned long hpt_hash(unsigned long va, unsigned int shift)
226{
227 return ((va >> 28) & 0x7fffffffffUL) ^ ((va & 0x0fffffffUL) >> shift);
228}
229
230extern int __hash_page_4K(unsigned long ea, unsigned long access,
231 unsigned long vsid, pte_t *ptep, unsigned long trap,
232 unsigned int local);
233extern int __hash_page_64K(unsigned long ea, unsigned long access,
234 unsigned long vsid, pte_t *ptep, unsigned long trap,
235 unsigned int local);
236struct mm_struct;
237extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
238extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
239 unsigned long ea, unsigned long vsid, int local,
240 unsigned long trap);
241
242extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
243 unsigned long pstart, unsigned long mode,
244 int psize);
245
246extern void htab_initialize(void);
247extern void htab_initialize_secondary(void);
248extern void hpte_init_native(void);
249extern void hpte_init_lpar(void);
250extern void hpte_init_iSeries(void);
251extern void hpte_init_beat(void);
252
253extern void stabs_alloc(void);
254extern void slb_initialize(void);
255extern void slb_flush_and_rebolt(void);
256extern void stab_initialize(unsigned long stab);
257
258#endif /* __ASSEMBLY__ */
259
260/*
261 * VSID allocation
262 *
263 * We first generate a 36-bit "proto-VSID". For kernel addresses this
264 * is equal to the ESID, for user addresses it is:
265 * (context << 15) | (esid & 0x7fff)
266 *
267 * The two forms are distinguishable because the top bit is 0 for user
268 * addresses, whereas the top two bits are 1 for kernel addresses.
269 * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
270 * now.
271 *
272 * The proto-VSIDs are then scrambled into real VSIDs with the
273 * multiplicative hash:
274 *
275 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
276 * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
277 * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
278 *
279 * This scramble is only well defined for proto-VSIDs below
280 * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
281 * reserved. VSID_MULTIPLIER is prime, so in particular it is
282 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
283 * Because the modulus is 2^n-1 we can compute it efficiently without
284 * a divide or extra multiply (see below).
285 *
286 * This scheme has several advantages over older methods:
287 *
288 * - We have VSIDs allocated for every kernel address
289 * (i.e. everything above 0xC000000000000000), except the very top
290 * segment, which simplifies several things.
291 *
292 * - We allow for 15 significant bits of ESID and 20 bits of
293 * context for user addresses. i.e. 8T (43 bits) of address space for
294 * up to 1M contexts (although the page table structure and context
295 * allocation will need changes to take advantage of this).
296 *
297 * - The scramble function gives robust scattering in the hash
298 * table (at least based on some initial results). The previous
299 * method was more susceptible to pathological cases giving excessive
300 * hash collisions.
301 */
302/*
303 * WARNING - If you change these you must make sure the asm
304 * implementations in slb_allocate (slb_low.S), do_stab_bolted
305 * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
306 *
307 * You'll also need to change the precomputed VSID values in head.S
308 * which are used by the iSeries firmware.
309 */
310
311#define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */
312#define VSID_BITS 36
313#define VSID_MODULUS ((1UL<<VSID_BITS)-1)
314
315#define CONTEXT_BITS 19
316#define USER_ESID_BITS 16
317
318#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
319
320/*
321 * This macro generates asm code to compute the VSID scramble
322 * function. Used in slb_allocate() and do_stab_bolted. The function
323 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
324 *
325 * rt = register continaing the proto-VSID and into which the
326 * VSID will be stored
327 * rx = scratch register (clobbered)
328 *
329 * - rt and rx must be different registers
330 * - The answer will end up in the low 36 bits of rt. The higher
331 * bits may contain other garbage, so you may need to mask the
332 * result.
333 */
334#define ASM_VSID_SCRAMBLE(rt, rx) \
335 lis rx,VSID_MULTIPLIER@h; \
336 ori rx,rx,VSID_MULTIPLIER@l; \
337 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
338 \
339 srdi rx,rt,VSID_BITS; \
340 clrldi rt,rt,(64-VSID_BITS); \
341 add rt,rt,rx; /* add high and low bits */ \
342 /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
343 * 2^36-1+2^28-1. That in particular means that if r3 >= \
344 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
345 * the bit clear, r3 already has the answer we want, if it \
346 * doesn't, the answer is the low 36 bits of r3+1. So in all \
347 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
348 addi rx,rt,1; \
349 srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \
350 add rt,rt,rx
351
352
353#ifndef __ASSEMBLY__
354
355typedef unsigned long mm_context_id_t;
356
357typedef struct {
358 mm_context_id_t id;
359 u16 user_psize; /* page size index */
360 u16 sllp; /* SLB entry page size encoding */
361#ifdef CONFIG_HUGETLB_PAGE
362 u16 low_htlb_areas, high_htlb_areas;
363#endif 12#endif
364 unsigned long vdso_base;
365} mm_context_t;
366
367
368static inline unsigned long vsid_scramble(unsigned long protovsid)
369{
370#if 0
371 /* The code below is equivalent to this function for arguments
372 * < 2^VSID_BITS, which is all this should ever be called
373 * with. However gcc is not clever enough to compute the
374 * modulus (2^n-1) without a second multiply. */
375 return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
376#else /* 1 */
377 unsigned long x;
378
379 x = protovsid * VSID_MULTIPLIER;
380 x = (x >> VSID_BITS) + (x & VSID_MODULUS);
381 return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
382#endif /* 1 */
383}
384
385/* This is only valid for addresses >= KERNELBASE */
386static inline unsigned long get_kernel_vsid(unsigned long ea)
387{
388 return vsid_scramble(ea >> SID_SHIFT);
389}
390
391/* This is only valid for user addresses (which are below 2^41) */
392static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
393{
394 return vsid_scramble((context << USER_ESID_BITS)
395 | (ea >> SID_SHIFT));
396}
397
398#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
399#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
400
401/* Physical address used by some IO functions */
402typedef unsigned long phys_addr_t;
403
404
405#endif /* __ASSEMBLY */
406 13
407#endif /* CONFIG_PPC64 */
408#endif /* __KERNEL__ */ 14#endif /* __KERNEL__ */
409#endif /* _ASM_POWERPC_MMU_H_ */ 15#endif /* _ASM_POWERPC_MMU_H_ */
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