diff options
| -rw-r--r-- | drivers/mtd/nand/denali.c | 208 | ||||
| -rw-r--r-- | drivers/mtd/nand/denali.h | 18 |
2 files changed, 42 insertions, 184 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index e4462c0740b2..f59dd03f36d4 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c | |||
| @@ -119,9 +119,6 @@ static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP, | |||
| 119 | INTR_STATUS2__RST_COMP, | 119 | INTR_STATUS2__RST_COMP, |
| 120 | INTR_STATUS3__RST_COMP}; | 120 | INTR_STATUS3__RST_COMP}; |
| 121 | 121 | ||
| 122 | /* specifies the debug level of the driver */ | ||
| 123 | static int nand_debug_level; | ||
| 124 | |||
| 125 | /* forward declarations */ | 122 | /* forward declarations */ |
| 126 | static void clear_interrupts(struct denali_nand_info *denali); | 123 | static void clear_interrupts(struct denali_nand_info *denali); |
| 127 | static uint32_t wait_for_irq(struct denali_nand_info *denali, | 124 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
| @@ -130,8 +127,6 @@ static void denali_irq_enable(struct denali_nand_info *denali, | |||
| 130 | uint32_t int_mask); | 127 | uint32_t int_mask); |
| 131 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); | 128 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
| 132 | 129 | ||
| 133 | #define DEBUG_DENALI 0 | ||
| 134 | |||
| 135 | /* Certain operations for the denali NAND controller use | 130 | /* Certain operations for the denali NAND controller use |
| 136 | * an indexed mode to read/write data. The operation is | 131 | * an indexed mode to read/write data. The operation is |
| 137 | * performed by writing the address value of the command | 132 | * performed by writing the address value of the command |
| @@ -181,11 +176,6 @@ static void read_status(struct denali_nand_info *denali) | |||
| 181 | 176 | ||
| 182 | /* update buffer with status value */ | 177 | /* update buffer with status value */ |
| 183 | write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10)); | 178 | write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10)); |
| 184 | |||
| 185 | #if DEBUG_DENALI | ||
| 186 | printk(KERN_INFO "device reporting status value of 0x%2x\n", | ||
| 187 | denali->buf.buf[0]); | ||
| 188 | #endif | ||
| 189 | } | 179 | } |
| 190 | 180 | ||
| 191 | /* resets a specific device connected to the core */ | 181 | /* resets a specific device connected to the core */ |
| @@ -204,7 +194,7 @@ static void reset_bank(struct denali_nand_info *denali) | |||
| 204 | irq_status = wait_for_irq(denali, irq_mask); | 194 | irq_status = wait_for_irq(denali, irq_mask); |
| 205 | 195 | ||
| 206 | if (irq_status & operation_timeout[denali->flash_bank]) | 196 | if (irq_status & operation_timeout[denali->flash_bank]) |
| 207 | printk(KERN_ERR "reset bank failed.\n"); | 197 | dev_err(&denali->dev->dev, "reset bank failed.\n"); |
| 208 | } | 198 | } |
| 209 | 199 | ||
| 210 | /* Reset the flash controller */ | 200 | /* Reset the flash controller */ |
| @@ -212,7 +202,7 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali) | |||
| 212 | { | 202 | { |
| 213 | uint32_t i; | 203 | uint32_t i; |
| 214 | 204 | ||
| 215 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", | 205 | dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n", |
| 216 | __FILE__, __LINE__, __func__); | 206 | __FILE__, __LINE__, __func__); |
| 217 | 207 | ||
| 218 | for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) | 208 | for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) |
| @@ -228,7 +218,7 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali) | |||
| 228 | ; | 218 | ; |
| 229 | if (ioread32(denali->flash_reg + intr_status_addresses[i]) & | 219 | if (ioread32(denali->flash_reg + intr_status_addresses[i]) & |
| 230 | operation_timeout[i]) | 220 | operation_timeout[i]) |
| 231 | nand_dbg_print(NAND_DBG_WARN, | 221 | dev_dbg(&denali->dev->dev, |
| 232 | "NAND Reset operation timed out on bank %d\n", i); | 222 | "NAND Reset operation timed out on bank %d\n", i); |
| 233 | } | 223 | } |
| 234 | 224 | ||
| @@ -266,7 +256,7 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali, | |||
| 266 | uint16_t acc_clks; | 256 | uint16_t acc_clks; |
| 267 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | 257 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; |
| 268 | 258 | ||
| 269 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", | 259 | dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n", |
| 270 | __FILE__, __LINE__, __func__); | 260 | __FILE__, __LINE__, __func__); |
| 271 | 261 | ||
| 272 | en_lo = CEIL_DIV(Trp[mode], CLK_X); | 262 | en_lo = CEIL_DIV(Trp[mode], CLK_X); |
| @@ -303,7 +293,7 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali, | |||
| 303 | acc_clks++; | 293 | acc_clks++; |
| 304 | 294 | ||
| 305 | if ((data_invalid - acc_clks * CLK_X) < 2) | 295 | if ((data_invalid - acc_clks * CLK_X) < 2) |
| 306 | nand_dbg_print(NAND_DBG_WARN, "%s, Line %d: Warning!\n", | 296 | dev_warn(&denali->dev->dev, "%s, Line %d: Warning!\n", |
| 307 | __FILE__, __LINE__); | 297 | __FILE__, __LINE__); |
| 308 | 298 | ||
| 309 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); | 299 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); |
| @@ -431,7 +421,7 @@ static void get_hynix_nand_para(struct denali_nand_info *denali, | |||
| 431 | #endif | 421 | #endif |
| 432 | break; | 422 | break; |
| 433 | default: | 423 | default: |
| 434 | nand_dbg_print(NAND_DBG_WARN, | 424 | dev_warn(&denali->dev->dev, |
| 435 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." | 425 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." |
| 436 | "Will use default parameter values instead.\n", | 426 | "Will use default parameter values instead.\n", |
| 437 | device_id); | 427 | device_id); |
| @@ -453,7 +443,7 @@ static void find_valid_banks(struct denali_nand_info *denali) | |||
| 453 | index_addr_read_data(denali, | 443 | index_addr_read_data(denali, |
| 454 | (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); | 444 | (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); |
| 455 | 445 | ||
| 456 | nand_dbg_print(NAND_DBG_DEBUG, | 446 | dev_dbg(&denali->dev->dev, |
| 457 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); | 447 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
| 458 | 448 | ||
| 459 | if (i == 0) { | 449 | if (i == 0) { |
| @@ -473,12 +463,13 @@ static void find_valid_banks(struct denali_nand_info *denali) | |||
| 473 | * Multichip support is not enabled. | 463 | * Multichip support is not enabled. |
| 474 | */ | 464 | */ |
| 475 | if (denali->total_used_banks != 1) { | 465 | if (denali->total_used_banks != 1) { |
| 476 | printk(KERN_ERR "Sorry, Intel CE4100 only supports " | 466 | dev_err(&denali->dev->dev, |
| 467 | "Sorry, Intel CE4100 only supports " | ||
| 477 | "a single NAND device.\n"); | 468 | "a single NAND device.\n"); |
| 478 | BUG(); | 469 | BUG(); |
| 479 | } | 470 | } |
| 480 | } | 471 | } |
| 481 | nand_dbg_print(NAND_DBG_DEBUG, | 472 | dev_dbg(&denali->dev->dev, |
| 482 | "denali->total_used_banks: %d\n", denali->total_used_banks); | 473 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
| 483 | } | 474 | } |
| 484 | 475 | ||
| @@ -512,8 +503,9 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) | |||
| 512 | uint32_t id_bytes[5], addr; | 503 | uint32_t id_bytes[5], addr; |
| 513 | uint8_t i, maf_id, device_id; | 504 | uint8_t i, maf_id, device_id; |
| 514 | 505 | ||
| 515 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", | 506 | dev_dbg(&denali->dev->dev, |
| 516 | __FILE__, __LINE__, __func__); | 507 | "%s, Line %d, Function: %s\n", |
| 508 | __FILE__, __LINE__, __func__); | ||
| 517 | 509 | ||
| 518 | /* Use read id method to get device ID and other | 510 | /* Use read id method to get device ID and other |
| 519 | * params. For some NAND chips, controller can't | 511 | * params. For some NAND chips, controller can't |
| @@ -540,12 +532,14 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) | |||
| 540 | get_hynix_nand_para(denali, device_id); | 532 | get_hynix_nand_para(denali, device_id); |
| 541 | } | 533 | } |
| 542 | 534 | ||
| 543 | nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:" | 535 | dev_info(&denali->dev->dev, |
| 544 | "acc_clks: %d, re_2_we: %d, we_2_re: %d," | 536 | "Dump timing register values:" |
| 545 | "addr_2_data: %d, rdwr_en_lo_cnt: %d, " | 537 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" |
| 538 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" | ||
| 546 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", | 539 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
| 547 | ioread32(denali->flash_reg + ACC_CLKS), | 540 | ioread32(denali->flash_reg + ACC_CLKS), |
| 548 | ioread32(denali->flash_reg + RE_2_WE), | 541 | ioread32(denali->flash_reg + RE_2_WE), |
| 542 | ioread32(denali->flash_reg + RE_2_RE), | ||
| 549 | ioread32(denali->flash_reg + WE_2_RE), | 543 | ioread32(denali->flash_reg + WE_2_RE), |
| 550 | ioread32(denali->flash_reg + ADDR_2_DATA), | 544 | ioread32(denali->flash_reg + ADDR_2_DATA), |
| 551 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), | 545 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), |
| @@ -568,7 +562,7 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) | |||
| 568 | static void denali_set_intr_modes(struct denali_nand_info *denali, | 562 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
| 569 | uint16_t INT_ENABLE) | 563 | uint16_t INT_ENABLE) |
| 570 | { | 564 | { |
| 571 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", | 565 | dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n", |
| 572 | __FILE__, __LINE__, __func__); | 566 | __FILE__, __LINE__, __func__); |
| 573 | 567 | ||
| 574 | if (INT_ENABLE) | 568 | if (INT_ENABLE) |
| @@ -645,11 +639,6 @@ static void clear_interrupts(struct denali_nand_info *denali) | |||
| 645 | status = read_interrupt_status(denali); | 639 | status = read_interrupt_status(denali); |
| 646 | clear_interrupt(denali, status); | 640 | clear_interrupt(denali, status); |
| 647 | 641 | ||
| 648 | #if DEBUG_DENALI | ||
| 649 | denali->irq_debug_array[denali->idx++] = 0x30000000 | status; | ||
| 650 | denali->idx %= 32; | ||
| 651 | #endif | ||
| 652 | |||
| 653 | denali->irq_status = 0x0; | 642 | denali->irq_status = 0x0; |
| 654 | spin_unlock_irq(&denali->irq_lock); | 643 | spin_unlock_irq(&denali->irq_lock); |
| 655 | } | 644 | } |
| @@ -663,17 +652,6 @@ static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |||
| 663 | return ioread32(denali->flash_reg + intr_status_reg); | 652 | return ioread32(denali->flash_reg + intr_status_reg); |
| 664 | } | 653 | } |
| 665 | 654 | ||
| 666 | #if DEBUG_DENALI | ||
| 667 | static void print_irq_log(struct denali_nand_info *denali) | ||
| 668 | { | ||
| 669 | int i = 0; | ||
| 670 | |||
| 671 | printk(KERN_INFO "ISR debug log index = %X\n", denali->idx); | ||
| 672 | for (i = 0; i < 32; i++) | ||
| 673 | printk(KERN_INFO "%08X: %08X\n", i, denali->irq_debug_array[i]); | ||
| 674 | } | ||
| 675 | #endif | ||
| 676 | |||
| 677 | /* This is the interrupt service routine. It handles all interrupts | 655 | /* This is the interrupt service routine. It handles all interrupts |
| 678 | * sent to this device. Note that on CE4100, this is a shared | 656 | * sent to this device. Note that on CE4100, this is a shared |
| 679 | * interrupt. | 657 | * interrupt. |
| @@ -694,13 +672,6 @@ static irqreturn_t denali_isr(int irq, void *dev_id) | |||
| 694 | * the interrupt, since this is a shared interrupt */ | 672 | * the interrupt, since this is a shared interrupt */ |
| 695 | irq_status = denali_irq_detected(denali); | 673 | irq_status = denali_irq_detected(denali); |
| 696 | if (irq_status != 0) { | 674 | if (irq_status != 0) { |
| 697 | #if DEBUG_DENALI | ||
| 698 | denali->irq_debug_array[denali->idx++] = | ||
| 699 | 0x10000000 | irq_status; | ||
| 700 | denali->idx %= 32; | ||
| 701 | |||
| 702 | printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status); | ||
| 703 | #endif | ||
| 704 | /* handle interrupt */ | 675 | /* handle interrupt */ |
| 705 | /* first acknowledge it */ | 676 | /* first acknowledge it */ |
| 706 | clear_interrupt(denali, irq_status); | 677 | clear_interrupt(denali, irq_status); |
| @@ -726,41 +697,20 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |||
| 726 | unsigned long timeout = msecs_to_jiffies(1000); | 697 | unsigned long timeout = msecs_to_jiffies(1000); |
| 727 | 698 | ||
| 728 | do { | 699 | do { |
| 729 | #if DEBUG_DENALI | ||
| 730 | printk(KERN_INFO "waiting for 0x%x\n", irq_mask); | ||
| 731 | #endif | ||
| 732 | comp_res = | 700 | comp_res = |
| 733 | wait_for_completion_timeout(&denali->complete, timeout); | 701 | wait_for_completion_timeout(&denali->complete, timeout); |
| 734 | spin_lock_irq(&denali->irq_lock); | 702 | spin_lock_irq(&denali->irq_lock); |
| 735 | intr_status = denali->irq_status; | 703 | intr_status = denali->irq_status; |
| 736 | 704 | ||
| 737 | #if DEBUG_DENALI | ||
| 738 | denali->irq_debug_array[denali->idx++] = | ||
| 739 | 0x20000000 | (irq_mask << 16) | intr_status; | ||
| 740 | denali->idx %= 32; | ||
| 741 | #endif | ||
| 742 | |||
| 743 | if (intr_status & irq_mask) { | 705 | if (intr_status & irq_mask) { |
| 744 | denali->irq_status &= ~irq_mask; | 706 | denali->irq_status &= ~irq_mask; |
| 745 | spin_unlock_irq(&denali->irq_lock); | 707 | spin_unlock_irq(&denali->irq_lock); |
| 746 | #if DEBUG_DENALI | ||
| 747 | if (retry) | ||
| 748 | printk(KERN_INFO "status on retry = 0x%x\n", | ||
| 749 | intr_status); | ||
| 750 | #endif | ||
| 751 | /* our interrupt was detected */ | 708 | /* our interrupt was detected */ |
| 752 | break; | 709 | break; |
| 753 | } else { | 710 | } else { |
| 754 | /* these are not the interrupts you are looking for - | 711 | /* these are not the interrupts you are looking for - |
| 755 | * need to wait again */ | 712 | * need to wait again */ |
| 756 | spin_unlock_irq(&denali->irq_lock); | 713 | spin_unlock_irq(&denali->irq_lock); |
| 757 | #if DEBUG_DENALI | ||
| 758 | print_irq_log(denali); | ||
| 759 | printk(KERN_INFO "received irq nobody cared:" | ||
| 760 | " irq_status = 0x%x, irq_mask = 0x%x," | ||
| 761 | " timeout = %ld\n", intr_status, | ||
| 762 | irq_mask, comp_res); | ||
| 763 | #endif | ||
| 764 | retry = true; | 714 | retry = true; |
| 765 | } | 715 | } |
| 766 | } while (comp_res != 0); | 716 | } while (comp_res != 0); |
| @@ -814,16 +764,6 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |||
| 814 | 764 | ||
| 815 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | 765 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); |
| 816 | 766 | ||
| 817 | #if DEBUG_DENALI | ||
| 818 | spin_lock_irq(&denali->irq_lock); | ||
| 819 | denali->irq_debug_array[denali->idx++] = | ||
| 820 | 0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) | | ||
| 821 | (access_type << 4); | ||
| 822 | denali->idx %= 32; | ||
| 823 | spin_unlock_irq(&denali->irq_lock); | ||
| 824 | #endif | ||
| 825 | |||
| 826 | |||
| 827 | /* clear interrupts */ | 767 | /* clear interrupts */ |
| 828 | clear_interrupts(denali); | 768 | clear_interrupts(denali); |
| 829 | 769 | ||
| @@ -862,9 +802,10 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |||
| 862 | irq_status = wait_for_irq(denali, irq_mask); | 802 | irq_status = wait_for_irq(denali, irq_mask); |
| 863 | 803 | ||
| 864 | if (irq_status == 0) { | 804 | if (irq_status == 0) { |
| 865 | printk(KERN_ERR "cmd, page, addr on timeout " | 805 | dev_err(&denali->dev->dev, |
| 866 | "(0x%x, 0x%x, 0x%x)\n", cmd, | 806 | "cmd, page, addr on timeout " |
| 867 | denali->page, addr); | 807 | "(0x%x, 0x%x, 0x%x)\n", |
| 808 | cmd, denali->page, addr); | ||
| 868 | status = FAIL; | 809 | status = FAIL; |
| 869 | } else { | 810 | } else { |
| 870 | cmd = MODE_01 | addr; | 811 | cmd = MODE_01 | addr; |
| @@ -932,24 +873,15 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |||
| 932 | DENALI_WRITE) == PASS) { | 873 | DENALI_WRITE) == PASS) { |
| 933 | write_data_to_flash_mem(denali, buf, mtd->oobsize); | 874 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
| 934 | 875 | ||
| 935 | #if DEBUG_DENALI | ||
| 936 | spin_lock_irq(&denali->irq_lock); | ||
| 937 | denali->irq_debug_array[denali->idx++] = | ||
| 938 | 0x80000000 | mtd->oobsize; | ||
| 939 | denali->idx %= 32; | ||
| 940 | spin_unlock_irq(&denali->irq_lock); | ||
| 941 | #endif | ||
| 942 | |||
| 943 | |||
| 944 | /* wait for operation to complete */ | 876 | /* wait for operation to complete */ |
| 945 | irq_status = wait_for_irq(denali, irq_mask); | 877 | irq_status = wait_for_irq(denali, irq_mask); |
| 946 | 878 | ||
| 947 | if (irq_status == 0) { | 879 | if (irq_status == 0) { |
| 948 | printk(KERN_ERR "OOB write failed\n"); | 880 | dev_err(&denali->dev->dev, "OOB write failed\n"); |
| 949 | status = -EIO; | 881 | status = -EIO; |
| 950 | } | 882 | } |
| 951 | } else { | 883 | } else { |
| 952 | printk(KERN_ERR "unable to send pipeline command\n"); | 884 | dev_err(&denali->dev->dev, "unable to send pipeline command\n"); |
| 953 | status = -EIO; | 885 | status = -EIO; |
| 954 | } | 886 | } |
| 955 | return status; | 887 | return status; |
| @@ -964,9 +896,6 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |||
| 964 | 896 | ||
| 965 | denali->page = page; | 897 | denali->page = page; |
| 966 | 898 | ||
| 967 | #if DEBUG_DENALI | ||
| 968 | printk(KERN_INFO "read_oob %d\n", page); | ||
| 969 | #endif | ||
| 970 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, | 899 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
| 971 | DENALI_READ) == PASS) { | 900 | DENALI_READ) == PASS) { |
| 972 | read_data_from_flash_mem(denali, buf, mtd->oobsize); | 901 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
| @@ -977,7 +906,7 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |||
| 977 | irq_status = wait_for_irq(denali, irq_mask); | 906 | irq_status = wait_for_irq(denali, irq_mask); |
| 978 | 907 | ||
| 979 | if (irq_status == 0) | 908 | if (irq_status == 0) |
| 980 | printk(KERN_ERR "page on OOB timeout %d\n", | 909 | dev_err(&denali->dev->dev, "page on OOB timeout %d\n", |
| 981 | denali->page); | 910 | denali->page); |
| 982 | 911 | ||
| 983 | /* We set the device back to MAIN_ACCESS here as I observed | 912 | /* We set the device back to MAIN_ACCESS here as I observed |
| @@ -989,14 +918,6 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |||
| 989 | addr = BANK(denali->flash_bank) | denali->page; | 918 | addr = BANK(denali->flash_bank) | denali->page; |
| 990 | cmd = MODE_10 | addr; | 919 | cmd = MODE_10 | addr; |
| 991 | index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); | 920 | index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); |
| 992 | |||
| 993 | #if DEBUG_DENALI | ||
| 994 | spin_lock_irq(&denali->irq_lock); | ||
| 995 | denali->irq_debug_array[denali->idx++] = | ||
| 996 | 0x60000000 | mtd->oobsize; | ||
| 997 | denali->idx %= 32; | ||
| 998 | spin_unlock_irq(&denali->irq_lock); | ||
| 999 | #endif | ||
| 1000 | } | 921 | } |
| 1001 | } | 922 | } |
| 1002 | 923 | ||
| @@ -1070,13 +991,6 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, | |||
| 1070 | * */ | 991 | * */ |
| 1071 | check_erased_page = true; | 992 | check_erased_page = true; |
| 1072 | } | 993 | } |
| 1073 | |||
| 1074 | #if DEBUG_DENALI | ||
| 1075 | printk(KERN_INFO "Detected ECC error in page %d:" | ||
| 1076 | " err_addr = 0x%08x, info to fix is" | ||
| 1077 | " 0x%08x\n", denali->page, err_address, | ||
| 1078 | err_correction_info); | ||
| 1079 | #endif | ||
| 1080 | } while (!ECC_LAST_ERR(err_correction_info)); | 994 | } while (!ECC_LAST_ERR(err_correction_info)); |
| 1081 | /* Once handle all ecc errors, controller will triger | 995 | /* Once handle all ecc errors, controller will triger |
| 1082 | * a ECC_TRANSACTION_DONE interrupt, so here just wait | 996 | * a ECC_TRANSACTION_DONE interrupt, so here just wait |
| @@ -1170,8 +1084,9 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
| 1170 | irq_status = wait_for_irq(denali, irq_mask); | 1084 | irq_status = wait_for_irq(denali, irq_mask); |
| 1171 | 1085 | ||
| 1172 | if (irq_status == 0) { | 1086 | if (irq_status == 0) { |
| 1173 | printk(KERN_ERR "timeout on write_page" | 1087 | dev_err(&denali->dev->dev, |
| 1174 | " (type = %d)\n", raw_xfer); | 1088 | "timeout on write_page (type = %d)\n", |
| 1089 | raw_xfer); | ||
| 1175 | denali->status = | 1090 | denali->status = |
| 1176 | (irq_status & INTR_STATUS0__PROGRAM_FAIL) ? | 1091 | (irq_status & INTR_STATUS0__PROGRAM_FAIL) ? |
| 1177 | NAND_STATUS_FAIL : PASS; | 1092 | NAND_STATUS_FAIL : PASS; |
| @@ -1308,18 +1223,13 @@ static uint8_t denali_read_byte(struct mtd_info *mtd) | |||
| 1308 | if (denali->buf.head < denali->buf.tail) | 1223 | if (denali->buf.head < denali->buf.tail) |
| 1309 | result = denali->buf.buf[denali->buf.head++]; | 1224 | result = denali->buf.buf[denali->buf.head++]; |
| 1310 | 1225 | ||
| 1311 | #if DEBUG_DENALI | ||
| 1312 | printk(KERN_INFO "read byte -> 0x%02x\n", result); | ||
| 1313 | #endif | ||
| 1314 | return result; | 1226 | return result; |
| 1315 | } | 1227 | } |
| 1316 | 1228 | ||
| 1317 | static void denali_select_chip(struct mtd_info *mtd, int chip) | 1229 | static void denali_select_chip(struct mtd_info *mtd, int chip) |
| 1318 | { | 1230 | { |
| 1319 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1231 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1320 | #if DEBUG_DENALI | 1232 | |
| 1321 | printk(KERN_INFO "denali select chip %d\n", chip); | ||
| 1322 | #endif | ||
| 1323 | spin_lock_irq(&denali->irq_lock); | 1233 | spin_lock_irq(&denali->irq_lock); |
| 1324 | denali->flash_bank = chip; | 1234 | denali->flash_bank = chip; |
| 1325 | spin_unlock_irq(&denali->irq_lock); | 1235 | spin_unlock_irq(&denali->irq_lock); |
| @@ -1331,9 +1241,6 @@ static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |||
| 1331 | int status = denali->status; | 1241 | int status = denali->status; |
| 1332 | denali->status = 0; | 1242 | denali->status = 0; |
| 1333 | 1243 | ||
| 1334 | #if DEBUG_DENALI | ||
| 1335 | printk(KERN_INFO "waitfunc %d\n", status); | ||
| 1336 | #endif | ||
| 1337 | return status; | 1244 | return status; |
| 1338 | } | 1245 | } |
| 1339 | 1246 | ||
| @@ -1343,9 +1250,6 @@ static void denali_erase(struct mtd_info *mtd, int page) | |||
| 1343 | 1250 | ||
| 1344 | uint32_t cmd = 0x0, irq_status = 0; | 1251 | uint32_t cmd = 0x0, irq_status = 0; |
| 1345 | 1252 | ||
| 1346 | #if DEBUG_DENALI | ||
| 1347 | printk(KERN_INFO "erase page: %d\n", page); | ||
| 1348 | #endif | ||
| 1349 | /* clear interrupts */ | 1253 | /* clear interrupts */ |
| 1350 | clear_interrupts(denali); | 1254 | clear_interrupts(denali); |
| 1351 | 1255 | ||
| @@ -1368,9 +1272,6 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, | |||
| 1368 | uint32_t addr, id; | 1272 | uint32_t addr, id; |
| 1369 | int i; | 1273 | int i; |
| 1370 | 1274 | ||
| 1371 | #if DEBUG_DENALI | ||
| 1372 | printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page); | ||
| 1373 | #endif | ||
| 1374 | switch (cmd) { | 1275 | switch (cmd) { |
| 1375 | case NAND_CMD_PAGEPROG: | 1276 | case NAND_CMD_PAGEPROG: |
| 1376 | break; | 1277 | break; |
| @@ -1414,7 +1315,9 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, | |||
| 1414 | static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, | 1315 | static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, |
| 1415 | uint8_t *ecc_code) | 1316 | uint8_t *ecc_code) |
| 1416 | { | 1317 | { |
| 1417 | printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n"); | 1318 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1319 | dev_err(&denali->dev->dev, | ||
| 1320 | "denali_ecc_calculate called unexpectedly\n"); | ||
| 1418 | BUG(); | 1321 | BUG(); |
| 1419 | return -EIO; | 1322 | return -EIO; |
| 1420 | } | 1323 | } |
| @@ -1422,14 +1325,18 @@ static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, | |||
| 1422 | static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, | 1325 | static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, |
| 1423 | uint8_t *read_ecc, uint8_t *calc_ecc) | 1326 | uint8_t *read_ecc, uint8_t *calc_ecc) |
| 1424 | { | 1327 | { |
| 1425 | printk(KERN_ERR "denali_ecc_correct called unexpectedly\n"); | 1328 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1329 | dev_err(&denali->dev->dev, | ||
| 1330 | "denali_ecc_correct called unexpectedly\n"); | ||
| 1426 | BUG(); | 1331 | BUG(); |
| 1427 | return -EIO; | 1332 | return -EIO; |
| 1428 | } | 1333 | } |
| 1429 | 1334 | ||
| 1430 | static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) | 1335 | static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) |
| 1431 | { | 1336 | { |
| 1432 | printk(KERN_ERR "denali_ecc_hwctl called unexpectedly\n"); | 1337 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1338 | dev_err(&denali->dev->dev, | ||
| 1339 | "denali_ecc_hwctl called unexpectedly\n"); | ||
| 1433 | BUG(); | 1340 | BUG(); |
| 1434 | } | 1341 | } |
| 1435 | /* end NAND core entry points */ | 1342 | /* end NAND core entry points */ |
| @@ -1525,9 +1432,6 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
| 1525 | unsigned long csr_len, mem_len; | 1432 | unsigned long csr_len, mem_len; |
| 1526 | struct denali_nand_info *denali; | 1433 | struct denali_nand_info *denali; |
| 1527 | 1434 | ||
| 1528 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", | ||
| 1529 | __FILE__, __LINE__, __func__); | ||
| 1530 | |||
| 1531 | denali = kzalloc(sizeof(*denali), GFP_KERNEL); | 1435 | denali = kzalloc(sizeof(*denali), GFP_KERNEL); |
| 1532 | if (!denali) | 1436 | if (!denali) |
| 1533 | return -ENOMEM; | 1437 | return -ENOMEM; |
| @@ -1562,11 +1466,6 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
| 1562 | if (!mem_len) { | 1466 | if (!mem_len) { |
| 1563 | mem_base = csr_base + csr_len; | 1467 | mem_base = csr_base + csr_len; |
| 1564 | mem_len = csr_len; | 1468 | mem_len = csr_len; |
| 1565 | nand_dbg_print(NAND_DBG_WARN, | ||
| 1566 | "Spectra: No second" | ||
| 1567 | " BAR for PCI device;" | ||
| 1568 | " assuming %08Lx\n", | ||
| 1569 | (uint64_t)csr_base); | ||
| 1570 | } | 1469 | } |
| 1571 | } | 1470 | } |
| 1572 | 1471 | ||
| @@ -1583,7 +1482,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
| 1583 | PCI_DMA_BIDIRECTIONAL); | 1482 | PCI_DMA_BIDIRECTIONAL); |
| 1584 | 1483 | ||
| 1585 | if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) { | 1484 | if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) { |
| 1586 | printk(KERN_ERR "Spectra: failed to map DMA buffer\n"); | 1485 | dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n"); |
| 1587 | goto failed_enable_dev; | 1486 | goto failed_enable_dev; |
| 1588 | } | 1487 | } |
| 1589 | 1488 | ||
| @@ -1602,8 +1501,6 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
| 1602 | ret = -ENOMEM; | 1501 | ret = -ENOMEM; |
| 1603 | goto failed_req_regions; | 1502 | goto failed_req_regions; |
| 1604 | } | 1503 | } |
| 1605 | nand_dbg_print(NAND_DBG_DEBUG, "Spectra: CSR 0x%08Lx -> 0x%p (0x%lx)\n", | ||
| 1606 | (uint64_t)csr_base, denali->flash_reg, csr_len); | ||
| 1607 | 1504 | ||
| 1608 | denali->flash_mem = ioremap_nocache(mem_base, mem_len); | 1505 | denali->flash_mem = ioremap_nocache(mem_base, mem_len); |
| 1609 | if (!denali->flash_mem) { | 1506 | if (!denali->flash_mem) { |
| @@ -1612,15 +1509,9 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
| 1612 | goto failed_remap_reg; | 1509 | goto failed_remap_reg; |
| 1613 | } | 1510 | } |
| 1614 | 1511 | ||
| 1615 | nand_dbg_print(NAND_DBG_WARN, | ||
| 1616 | "Spectra: Remapped flash base address: " | ||
| 1617 | "0x%p, len: %ld\n", | ||
| 1618 | denali->flash_mem, csr_len); | ||
| 1619 | |||
| 1620 | denali_hw_init(denali); | 1512 | denali_hw_init(denali); |
| 1621 | denali_drv_init(denali); | 1513 | denali_drv_init(denali); |
| 1622 | 1514 | ||
| 1623 | nand_dbg_print(NAND_DBG_DEBUG, "Spectra: IRQ %d\n", dev->irq); | ||
| 1624 | if (request_irq(dev->irq, denali_isr, IRQF_SHARED, | 1515 | if (request_irq(dev->irq, denali_isr, IRQF_SHARED, |
| 1625 | DENALI_NAND_NAME, denali)) { | 1516 | DENALI_NAND_NAME, denali)) { |
| 1626 | printk(KERN_ERR "Spectra: Unable to allocate IRQ\n"); | 1517 | printk(KERN_ERR "Spectra: Unable to allocate IRQ\n"); |
| @@ -1635,18 +1526,6 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
| 1635 | 1526 | ||
| 1636 | denali_nand_timing_set(denali); | 1527 | denali_nand_timing_set(denali); |
| 1637 | 1528 | ||
| 1638 | nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:" | ||
| 1639 | "acc_clks: %d, re_2_we: %d, we_2_re: %d," | ||
| 1640 | "addr_2_data: %d, rdwr_en_lo_cnt: %d, " | ||
| 1641 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", | ||
| 1642 | ioread32(denali->flash_reg + ACC_CLKS), | ||
| 1643 | ioread32(denali->flash_reg + RE_2_WE), | ||
| 1644 | ioread32(denali->flash_reg + WE_2_RE), | ||
| 1645 | ioread32(denali->flash_reg + ADDR_2_DATA), | ||
| 1646 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), | ||
| 1647 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), | ||
| 1648 | ioread32(denali->flash_reg + CS_SETUP_CNT)); | ||
| 1649 | |||
| 1650 | denali->mtd.name = "Denali NAND"; | 1529 | denali->mtd.name = "Denali NAND"; |
| 1651 | denali->mtd.owner = THIS_MODULE; | 1530 | denali->mtd.owner = THIS_MODULE; |
| 1652 | denali->mtd.priv = &denali->nand; | 1531 | denali->mtd.priv = &denali->nand; |
| @@ -1772,8 +1651,8 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
| 1772 | 1651 | ||
| 1773 | ret = add_mtd_device(&denali->mtd); | 1652 | ret = add_mtd_device(&denali->mtd); |
| 1774 | if (ret) { | 1653 | if (ret) { |
| 1775 | printk(KERN_ERR "Spectra: Failed to register" | 1654 | dev_err(&dev->dev, "Spectra: Failed to register MTD: %d\n", |
| 1776 | " MTD device: %d\n", ret); | 1655 | ret); |
| 1777 | goto failed_req_irq; | 1656 | goto failed_req_irq; |
| 1778 | } | 1657 | } |
| 1779 | return 0; | 1658 | return 0; |
| @@ -1801,9 +1680,6 @@ static void denali_pci_remove(struct pci_dev *dev) | |||
| 1801 | { | 1680 | { |
| 1802 | struct denali_nand_info *denali = pci_get_drvdata(dev); | 1681 | struct denali_nand_info *denali = pci_get_drvdata(dev); |
| 1803 | 1682 | ||
| 1804 | nand_dbg_print(NAND_DBG_WARN, "%s, Line %d, Function: %s\n", | ||
| 1805 | __FILE__, __LINE__, __func__); | ||
| 1806 | |||
| 1807 | nand_release(&denali->mtd); | 1683 | nand_release(&denali->mtd); |
| 1808 | del_mtd_device(&denali->mtd); | 1684 | del_mtd_device(&denali->mtd); |
| 1809 | 1685 | ||
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index b680474e6333..3918bcb1561e 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h | |||
| @@ -635,24 +635,6 @@ | |||
| 635 | #define CLK_X 5 | 635 | #define CLK_X 5 |
| 636 | #define CLK_MULTI 4 | 636 | #define CLK_MULTI 4 |
| 637 | 637 | ||
| 638 | /* ffsport.h */ | ||
| 639 | #define VERBOSE 1 | ||
| 640 | |||
| 641 | #define NAND_DBG_WARN 1 | ||
| 642 | #define NAND_DBG_DEBUG 2 | ||
| 643 | #define NAND_DBG_TRACE 3 | ||
| 644 | |||
| 645 | #ifdef VERBOSE | ||
| 646 | #define nand_dbg_print(level, args...) \ | ||
| 647 | do { \ | ||
| 648 | if (level <= nand_debug_level) \ | ||
| 649 | printk(KERN_ALERT args); \ | ||
| 650 | } while (0) | ||
| 651 | #else | ||
| 652 | #define nand_dbg_print(level, args...) | ||
| 653 | #endif | ||
| 654 | |||
| 655 | |||
| 656 | /* spectraswconfig.h */ | 638 | /* spectraswconfig.h */ |
| 657 | #define CMD_DMA 0 | 639 | #define CMD_DMA 0 |
| 658 | 640 | ||
