diff options
-rw-r--r-- | arch/arm/mach-omap2/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock24xx.c | 319 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock24xx.h | 320 | ||||
-rw-r--r-- | arch/arm/mach-omap2/memory.c | 48 | ||||
-rw-r--r-- | arch/arm/mach-omap2/memory.h | 2 | ||||
-rw-r--r-- | arch/arm/plat-omap/clock.c | 42 | ||||
-rw-r--r-- | include/asm-arm/arch-omap/clock.h | 65 |
8 files changed, 562 insertions, 238 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index be2b671552a6..a3b2507fcc58 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
@@ -3,7 +3,7 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | # Common support | 5 | # Common support |
6 | obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o mux.o \ | 6 | obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \ |
7 | devices.o serial.o gpmc.o timer-gp.o | 7 | devices.o serial.o gpmc.o timer-gp.o |
8 | 8 | ||
9 | # Power Management | 9 | # Power Management |
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index a921efd43a70..b76c9fc1b8e9 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -122,7 +122,7 @@ u32 omap2_get_dpll_rate(struct clk *clk) | |||
122 | if (dd->div2_reg) { | 122 | if (dd->div2_reg) { |
123 | dpll = __raw_readl(dd->div2_reg); | 123 | dpll = __raw_readl(dd->div2_reg); |
124 | dpll_div = dpll & dd->div2_mask; | 124 | dpll_div = dpll & dd->div2_mask; |
125 | dpll_div >>= __fss(dd->div2_mask); | 125 | dpll_div >>= __ffs(dd->div2_mask); |
126 | do_div(dpll_clk, dpll_div + 1); | 126 | do_div(dpll_clk, dpll_div + 1); |
127 | } | 127 | } |
128 | 128 | ||
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index 5c24781f6d9b..c3ccac1b7218 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c | |||
@@ -15,6 +15,8 @@ | |||
15 | * it under the terms of the GNU General Public License version 2 as | 15 | * it under the terms of the GNU General Public License version 2 as |
16 | * published by the Free Software Foundation. | 16 | * published by the Free Software Foundation. |
17 | */ | 17 | */ |
18 | #undef DEBUG | ||
19 | |||
18 | #include <linux/module.h> | 20 | #include <linux/module.h> |
19 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
20 | #include <linux/device.h> | 22 | #include <linux/device.h> |
@@ -23,29 +25,64 @@ | |||
23 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
24 | #include <linux/clk.h> | 26 | #include <linux/clk.h> |
25 | 27 | ||
26 | #include <asm/io.h> | 28 | #include <linux/io.h> |
29 | #include <linux/cpufreq.h> | ||
27 | 30 | ||
28 | #include <asm/arch/clock.h> | 31 | #include <asm/arch/clock.h> |
29 | #include <asm/arch/sram.h> | 32 | #include <asm/arch/sram.h> |
30 | #include <asm/div64.h> | 33 | #include <asm/div64.h> |
34 | #include <asm/bitops.h> | ||
31 | 35 | ||
32 | #include "prcm-regs.h" | ||
33 | #include "memory.h" | 36 | #include "memory.h" |
37 | #include "clock.h" | ||
34 | #include "clock24xx.h" | 38 | #include "clock24xx.h" |
39 | #include "prm.h" | ||
40 | #include "prm-regbits-24xx.h" | ||
41 | #include "cm.h" | ||
42 | #include "cm-regbits-24xx.h" | ||
35 | 43 | ||
36 | #undef DEBUG | 44 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ |
45 | #define EN_APLL_STOPPED 0 | ||
46 | #define EN_APLL_LOCKED 3 | ||
37 | 47 | ||
38 | //#define DOWN_VARIABLE_DPLL 1 /* Experimental */ | 48 | /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ |
49 | #define APLLS_CLKIN_19_2MHZ 0 | ||
50 | #define APLLS_CLKIN_13MHZ 2 | ||
51 | #define APLLS_CLKIN_12MHZ 3 | ||
52 | |||
53 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ | ||
39 | 54 | ||
40 | static struct prcm_config *curr_prcm_set; | 55 | static struct prcm_config *curr_prcm_set; |
41 | static u32 curr_perf_level = PRCM_FULL_SPEED; | ||
42 | static struct clk *vclk; | 56 | static struct clk *vclk; |
43 | static struct clk *sclk; | 57 | static struct clk *sclk; |
44 | 58 | ||
45 | /*------------------------------------------------------------------------- | 59 | /*------------------------------------------------------------------------- |
46 | * Omap2 specific clock functions | 60 | * Omap24xx specific clock functions |
47 | *-------------------------------------------------------------------------*/ | 61 | *-------------------------------------------------------------------------*/ |
48 | 62 | ||
63 | static int omap2_enable_osc_ck(struct clk *clk) | ||
64 | { | ||
65 | u32 pcc; | ||
66 | |||
67 | pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); | ||
68 | |||
69 | __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, | ||
70 | OMAP24XX_PRCM_CLKSRC_CTRL); | ||
71 | |||
72 | return 0; | ||
73 | } | ||
74 | |||
75 | static void omap2_disable_osc_ck(struct clk *clk) | ||
76 | { | ||
77 | u32 pcc; | ||
78 | |||
79 | pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); | ||
80 | |||
81 | __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, | ||
82 | OMAP24XX_PRCM_CLKSRC_CTRL); | ||
83 | } | ||
84 | |||
85 | #ifdef OLD_CK | ||
49 | /* Recalculate SYST_CLK */ | 86 | /* Recalculate SYST_CLK */ |
50 | static void omap2_sys_clk_recalc(struct clk * clk) | 87 | static void omap2_sys_clk_recalc(struct clk * clk) |
51 | { | 88 | { |
@@ -55,17 +92,18 @@ static void omap2_sys_clk_recalc(struct clk * clk) | |||
55 | clk->rate = (clk->parent->rate / div); | 92 | clk->rate = (clk->parent->rate / div); |
56 | propagate_rate(clk); | 93 | propagate_rate(clk); |
57 | } | 94 | } |
95 | #endif /* OLD_CK */ | ||
58 | 96 | ||
59 | static u32 omap2_get_dpll_rate(struct clk * tclk) | 97 | /* This actually returns the rate of core_ck, not dpll_ck. */ |
98 | static u32 omap2_get_dpll_rate_24xx(struct clk *tclk) | ||
60 | { | 99 | { |
61 | long long dpll_clk; | 100 | long long dpll_clk; |
62 | int dpll_mult, dpll_div, amult; | 101 | u8 amult; |
102 | |||
103 | dpll_clk = omap2_get_dpll_rate(tclk); | ||
63 | 104 | ||
64 | dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */ | 105 | amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
65 | dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */ | 106 | amult &= OMAP24XX_CORE_CLK_SRC_MASK; |
66 | dpll_clk = (long long)tclk->parent->rate * dpll_mult; | ||
67 | do_div(dpll_clk, dpll_div + 1); | ||
68 | amult = CM_CLKSEL2_PLL & 0x3; | ||
69 | dpll_clk *= amult; | 107 | dpll_clk *= amult; |
70 | 108 | ||
71 | return dpll_clk; | 109 | return dpll_clk; |
@@ -84,6 +122,7 @@ static void omap2_propagate_rate(struct clk * clk) | |||
84 | propagate_rate(clk); | 122 | propagate_rate(clk); |
85 | } | 123 | } |
86 | 124 | ||
125 | #ifdef OLD_CK | ||
87 | static void omap2_set_osc_ck(int enable) | 126 | static void omap2_set_osc_ck(int enable) |
88 | { | 127 | { |
89 | if (enable) | 128 | if (enable) |
@@ -91,39 +130,40 @@ static void omap2_set_osc_ck(int enable) | |||
91 | else | 130 | else |
92 | PRCM_CLKSRC_CTRL |= 0x3 << 3; | 131 | PRCM_CLKSRC_CTRL |= 0x3 << 3; |
93 | } | 132 | } |
133 | #endif /* OLD_CK */ | ||
94 | 134 | ||
95 | /* Enable an APLL if off */ | 135 | /* Enable an APLL if off */ |
96 | static void omap2_clk_fixed_enable(struct clk *clk) | 136 | static int omap2_clk_fixed_enable(struct clk *clk) |
97 | { | 137 | { |
98 | u32 cval, i=0; | 138 | u32 cval, apll_mask; |
99 | 139 | ||
100 | if (clk->enable_bit == 0xff) /* Parent will do it */ | 140 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; |
101 | return; | ||
102 | 141 | ||
103 | cval = CM_CLKEN_PLL; | 142 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
104 | 143 | ||
105 | if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit)) | 144 | if ((cval & apll_mask) == apll_mask) |
106 | return; | 145 | return 0; /* apll already enabled */ |
107 | 146 | ||
108 | cval &= ~(0x3 << clk->enable_bit); | 147 | cval &= ~apll_mask; |
109 | cval |= (0x3 << clk->enable_bit); | 148 | cval |= apll_mask; |
110 | CM_CLKEN_PLL = cval; | 149 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); |
111 | 150 | ||
112 | if (clk == &apll96_ck) | 151 | if (clk == &apll96_ck) |
113 | cval = (1 << 8); | 152 | cval = OMAP24XX_ST_96M_APLL; |
114 | else if (clk == &apll54_ck) | 153 | else if (clk == &apll54_ck) |
115 | cval = (1 << 6); | 154 | cval = OMAP24XX_ST_54M_APLL; |
116 | 155 | ||
117 | while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */ | 156 | omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, |
118 | ++i; | 157 | clk->name); |
119 | udelay(1); | 158 | |
120 | if (i == 100000) { | 159 | /* |
121 | printk(KERN_ERR "Clock %s didn't lock\n", clk->name); | 160 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() |
122 | break; | 161 | * fails? |
123 | } | 162 | */ |
124 | } | 163 | return 0; |
125 | } | 164 | } |
126 | 165 | ||
166 | #ifdef OLD_CK | ||
127 | static void omap2_clk_wait_ready(struct clk *clk) | 167 | static void omap2_clk_wait_ready(struct clk *clk) |
128 | { | 168 | { |
129 | unsigned long reg, other_reg, st_reg; | 169 | unsigned long reg, other_reg, st_reg; |
@@ -199,20 +239,19 @@ static int _omap2_clk_enable(struct clk * clk) | |||
199 | 239 | ||
200 | return 0; | 240 | return 0; |
201 | } | 241 | } |
242 | #endif /* OLD_CK */ | ||
202 | 243 | ||
203 | /* Stop APLL */ | 244 | /* Stop APLL */ |
204 | static void omap2_clk_fixed_disable(struct clk *clk) | 245 | static void omap2_clk_fixed_disable(struct clk *clk) |
205 | { | 246 | { |
206 | u32 cval; | 247 | u32 cval; |
207 | 248 | ||
208 | if(clk->enable_bit == 0xff) /* let parent off do it */ | 249 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
209 | return; | 250 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); |
210 | 251 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | |
211 | cval = CM_CLKEN_PLL; | ||
212 | cval &= ~(0x3 << clk->enable_bit); | ||
213 | CM_CLKEN_PLL = cval; | ||
214 | } | 252 | } |
215 | 253 | ||
254 | #ifdef OLD_CK | ||
216 | /* Disables clock without considering parent dependencies or use count */ | 255 | /* Disables clock without considering parent dependencies or use count */ |
217 | static void _omap2_clk_disable(struct clk *clk) | 256 | static void _omap2_clk_disable(struct clk *clk) |
218 | { | 257 | { |
@@ -269,6 +308,7 @@ static void omap2_clk_disable(struct clk *clk) | |||
269 | omap2_clk_disable(clk->parent); | 308 | omap2_clk_disable(clk->parent); |
270 | } | 309 | } |
271 | } | 310 | } |
311 | #endif /* OLD_CK */ | ||
272 | 312 | ||
273 | /* | 313 | /* |
274 | * Uses the current prcm set to tell if a rate is valid. | 314 | * Uses the current prcm set to tell if a rate is valid. |
@@ -276,9 +316,12 @@ static void omap2_clk_disable(struct clk *clk) | |||
276 | */ | 316 | */ |
277 | static u32 omap2_dpll_round_rate(unsigned long target_rate) | 317 | static u32 omap2_dpll_round_rate(unsigned long target_rate) |
278 | { | 318 | { |
279 | u32 high, low; | 319 | u32 high, low, core_clk_src; |
280 | 320 | ||
281 | if ((CM_CLKSEL2_PLL & 0x3) == 1) { /* DPLL clockout */ | 321 | core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
322 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
323 | |||
324 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ | ||
282 | high = curr_prcm_set->dpll_speed * 2; | 325 | high = curr_prcm_set->dpll_speed * 2; |
283 | low = curr_prcm_set->dpll_speed; | 326 | low = curr_prcm_set->dpll_speed; |
284 | } else { /* DPLL clockout x 2 */ | 327 | } else { /* DPLL clockout x 2 */ |
@@ -300,6 +343,7 @@ static u32 omap2_dpll_round_rate(unsigned long target_rate) | |||
300 | 343 | ||
301 | } | 344 | } |
302 | 345 | ||
346 | #ifdef OLD_CK | ||
303 | /* | 347 | /* |
304 | * Used for clocks that are part of CLKSEL_xyz governed clocks. | 348 | * Used for clocks that are part of CLKSEL_xyz governed clocks. |
305 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? | 349 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? |
@@ -486,55 +530,72 @@ static u32 omap2_reprogram_sdrc(u32 level, u32 force) | |||
486 | 530 | ||
487 | return prev; | 531 | return prev; |
488 | } | 532 | } |
533 | #endif /* OLD_CK */ | ||
534 | |||
535 | static void omap2_dpll_recalc(struct clk *clk) | ||
536 | { | ||
537 | clk->rate = omap2_get_dpll_rate_24xx(clk); | ||
538 | |||
539 | propagate_rate(clk); | ||
540 | } | ||
489 | 541 | ||
490 | static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate) | 542 | static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate) |
491 | { | 543 | { |
492 | u32 flags, cur_rate, low, mult, div, valid_rate, done_rate; | 544 | u32 cur_rate, low, mult, div, valid_rate, done_rate; |
493 | u32 bypass = 0; | 545 | u32 bypass = 0; |
494 | struct prcm_config tmpset; | 546 | struct prcm_config tmpset; |
547 | const struct dpll_data *dd; | ||
548 | unsigned long flags; | ||
495 | int ret = -EINVAL; | 549 | int ret = -EINVAL; |
496 | 550 | ||
497 | local_irq_save(flags); | 551 | local_irq_save(flags); |
498 | cur_rate = omap2_get_dpll_rate(&dpll_ck); | 552 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); |
499 | mult = CM_CLKSEL2_PLL & 0x3; | 553 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
554 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
500 | 555 | ||
501 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | 556 | if ((rate == (cur_rate / 2)) && (mult == 2)) { |
502 | omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1); | 557 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); |
503 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { | 558 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { |
504 | omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); | 559 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); |
505 | } else if (rate != cur_rate) { | 560 | } else if (rate != cur_rate) { |
506 | valid_rate = omap2_dpll_round_rate(rate); | 561 | valid_rate = omap2_dpll_round_rate(rate); |
507 | if (valid_rate != rate) | 562 | if (valid_rate != rate) |
508 | goto dpll_exit; | 563 | goto dpll_exit; |
509 | 564 | ||
510 | if ((CM_CLKSEL2_PLL & 0x3) == 1) | 565 | if (mult == 1) |
511 | low = curr_prcm_set->dpll_speed; | 566 | low = curr_prcm_set->dpll_speed; |
512 | else | 567 | else |
513 | low = curr_prcm_set->dpll_speed / 2; | 568 | low = curr_prcm_set->dpll_speed / 2; |
514 | 569 | ||
515 | tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL; | 570 | dd = clk->dpll_data; |
516 | tmpset.cm_clksel1_pll &= ~(0x3FFF << 8); | 571 | if (!dd) |
572 | goto dpll_exit; | ||
573 | |||
574 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); | ||
575 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | ||
576 | dd->div1_mask); | ||
517 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); | 577 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); |
518 | tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL; | 578 | tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
519 | tmpset.cm_clksel2_pll &= ~0x3; | 579 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; |
520 | if (rate > low) { | 580 | if (rate > low) { |
521 | tmpset.cm_clksel2_pll |= 0x2; | 581 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; |
522 | mult = ((rate / 2) / 1000000); | 582 | mult = ((rate / 2) / 1000000); |
523 | done_rate = PRCM_FULL_SPEED; | 583 | done_rate = CORE_CLK_SRC_DPLL_X2; |
524 | } else { | 584 | } else { |
525 | tmpset.cm_clksel2_pll |= 0x1; | 585 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; |
526 | mult = (rate / 1000000); | 586 | mult = (rate / 1000000); |
527 | done_rate = PRCM_HALF_SPEED; | 587 | done_rate = CORE_CLK_SRC_DPLL; |
528 | } | 588 | } |
529 | tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12)); | 589 | tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); |
590 | tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); | ||
530 | 591 | ||
531 | /* Worst case */ | 592 | /* Worst case */ |
532 | tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS; | 593 | tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; |
533 | 594 | ||
534 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ | 595 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ |
535 | bypass = 1; | 596 | bypass = 1; |
536 | 597 | ||
537 | omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */ | 598 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */ |
538 | 599 | ||
539 | /* Force dll lock mode */ | 600 | /* Force dll lock mode */ |
540 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, | 601 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, |
@@ -544,7 +605,7 @@ static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate) | |||
544 | omap2_init_memory_params(omap2_dll_force_needed()); | 605 | omap2_init_memory_params(omap2_dll_force_needed()); |
545 | omap2_reprogram_sdrc(done_rate, 0); | 606 | omap2_reprogram_sdrc(done_rate, 0); |
546 | } | 607 | } |
547 | omap2_clksel_recalc(&dpll_ck); | 608 | omap2_dpll_recalc(&dpll_ck); |
548 | ret = 0; | 609 | ret = 0; |
549 | 610 | ||
550 | dpll_exit: | 611 | dpll_exit: |
@@ -552,8 +613,13 @@ dpll_exit: | |||
552 | return(ret); | 613 | return(ret); |
553 | } | 614 | } |
554 | 615 | ||
555 | /* Just return the MPU speed */ | 616 | /** |
556 | static void omap2_mpu_recalc(struct clk * clk) | 617 | * omap2_table_mpu_recalc - just return the MPU speed |
618 | * @clk: virt_prcm_set struct clk | ||
619 | * | ||
620 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. | ||
621 | */ | ||
622 | static void omap2_table_mpu_recalc(struct clk *clk) | ||
557 | { | 623 | { |
558 | clk->rate = curr_prcm_set->mpu_speed; | 624 | clk->rate = curr_prcm_set->mpu_speed; |
559 | } | 625 | } |
@@ -565,9 +631,9 @@ static void omap2_mpu_recalc(struct clk * clk) | |||
565 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and | 631 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and |
566 | * just uses the ARM rates. | 632 | * just uses the ARM rates. |
567 | */ | 633 | */ |
568 | static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate) | 634 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) |
569 | { | 635 | { |
570 | struct prcm_config * ptr; | 636 | struct prcm_config *ptr; |
571 | long highest_rate; | 637 | long highest_rate; |
572 | 638 | ||
573 | if (clk != &virt_prcm_set) | 639 | if (clk != &virt_prcm_set) |
@@ -576,6 +642,8 @@ static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate) | |||
576 | highest_rate = -EINVAL; | 642 | highest_rate = -EINVAL; |
577 | 643 | ||
578 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { | 644 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { |
645 | if (!(ptr->flags & cpu_mask)) | ||
646 | continue; | ||
579 | if (ptr->xtal_speed != sys_ck.rate) | 647 | if (ptr->xtal_speed != sys_ck.rate) |
580 | continue; | 648 | continue; |
581 | 649 | ||
@@ -588,6 +656,7 @@ static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate) | |||
588 | return highest_rate; | 656 | return highest_rate; |
589 | } | 657 | } |
590 | 658 | ||
659 | #ifdef OLD_CK | ||
591 | /* | 660 | /* |
592 | * omap2_convert_field_to_div() - turn field value into integer divider | 661 | * omap2_convert_field_to_div() - turn field value into integer divider |
593 | */ | 662 | */ |
@@ -938,24 +1007,19 @@ static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | |||
938 | set_parent_error: | 1007 | set_parent_error: |
939 | return ret; | 1008 | return ret; |
940 | } | 1009 | } |
1010 | #endif /* OLD_CK */ | ||
941 | 1011 | ||
942 | /* Sets basic clocks based on the specified rate */ | 1012 | /* Sets basic clocks based on the specified rate */ |
943 | static int omap2_select_table_rate(struct clk * clk, unsigned long rate) | 1013 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate) |
944 | { | 1014 | { |
945 | u32 flags, cur_rate, done_rate, bypass = 0; | 1015 | u32 cur_rate, done_rate, bypass = 0, tmp; |
946 | u8 cpu_mask = 0; | ||
947 | struct prcm_config *prcm; | 1016 | struct prcm_config *prcm; |
948 | unsigned long found_speed = 0; | 1017 | unsigned long found_speed = 0; |
1018 | unsigned long flags; | ||
949 | 1019 | ||
950 | if (clk != &virt_prcm_set) | 1020 | if (clk != &virt_prcm_set) |
951 | return -EINVAL; | 1021 | return -EINVAL; |
952 | 1022 | ||
953 | /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */ | ||
954 | if (cpu_is_omap2420()) | ||
955 | cpu_mask = RATE_IN_242X; | ||
956 | else if (cpu_is_omap2430()) | ||
957 | cpu_mask = RATE_IN_243X; | ||
958 | |||
959 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | 1023 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
960 | if (!(prcm->flags & cpu_mask)) | 1024 | if (!(prcm->flags & cpu_mask)) |
961 | continue; | 1025 | continue; |
@@ -976,38 +1040,42 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate) | |||
976 | } | 1040 | } |
977 | 1041 | ||
978 | curr_prcm_set = prcm; | 1042 | curr_prcm_set = prcm; |
979 | cur_rate = omap2_get_dpll_rate(&dpll_ck); | 1043 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); |
980 | 1044 | ||
981 | if (prcm->dpll_speed == cur_rate / 2) { | 1045 | if (prcm->dpll_speed == cur_rate / 2) { |
982 | omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1); | 1046 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); |
983 | } else if (prcm->dpll_speed == cur_rate * 2) { | 1047 | } else if (prcm->dpll_speed == cur_rate * 2) { |
984 | omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); | 1048 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); |
985 | } else if (prcm->dpll_speed != cur_rate) { | 1049 | } else if (prcm->dpll_speed != cur_rate) { |
986 | local_irq_save(flags); | 1050 | local_irq_save(flags); |
987 | 1051 | ||
988 | if (prcm->dpll_speed == prcm->xtal_speed) | 1052 | if (prcm->dpll_speed == prcm->xtal_speed) |
989 | bypass = 1; | 1053 | bypass = 1; |
990 | 1054 | ||
991 | if ((prcm->cm_clksel2_pll & 0x3) == 2) | 1055 | if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == |
992 | done_rate = PRCM_FULL_SPEED; | 1056 | CORE_CLK_SRC_DPLL_X2) |
1057 | done_rate = CORE_CLK_SRC_DPLL_X2; | ||
993 | else | 1058 | else |
994 | done_rate = PRCM_HALF_SPEED; | 1059 | done_rate = CORE_CLK_SRC_DPLL; |
995 | 1060 | ||
996 | /* MPU divider */ | 1061 | /* MPU divider */ |
997 | CM_CLKSEL_MPU = prcm->cm_clksel_mpu; | 1062 | cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); |
998 | 1063 | ||
999 | /* dsp + iva1 div(2420), iva2.1(2430) */ | 1064 | /* dsp + iva1 div(2420), iva2.1(2430) */ |
1000 | CM_CLKSEL_DSP = prcm->cm_clksel_dsp; | 1065 | cm_write_mod_reg(prcm->cm_clksel_dsp, |
1066 | OMAP24XX_DSP_MOD, CM_CLKSEL); | ||
1001 | 1067 | ||
1002 | CM_CLKSEL_GFX = prcm->cm_clksel_gfx; | 1068 | cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); |
1003 | 1069 | ||
1004 | /* Major subsystem dividers */ | 1070 | /* Major subsystem dividers */ |
1005 | CM_CLKSEL1_CORE = prcm->cm_clksel1_core; | 1071 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; |
1072 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); | ||
1006 | if (cpu_is_omap2430()) | 1073 | if (cpu_is_omap2430()) |
1007 | CM_CLKSEL_MDM = prcm->cm_clksel_mdm; | 1074 | cm_write_mod_reg(prcm->cm_clksel_mdm, |
1075 | OMAP2430_MDM_MOD, CM_CLKSEL); | ||
1008 | 1076 | ||
1009 | /* x2 to enter init_mem */ | 1077 | /* x2 to enter init_mem */ |
1010 | omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); | 1078 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); |
1011 | 1079 | ||
1012 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, | 1080 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, |
1013 | bypass); | 1081 | bypass); |
@@ -1017,7 +1085,7 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate) | |||
1017 | 1085 | ||
1018 | local_irq_restore(flags); | 1086 | local_irq_restore(flags); |
1019 | } | 1087 | } |
1020 | omap2_clksel_recalc(&dpll_ck); | 1088 | omap2_dpll_recalc(&dpll_ck); |
1021 | 1089 | ||
1022 | return 0; | 1090 | return 0; |
1023 | } | 1091 | } |
@@ -1051,27 +1119,45 @@ static struct clk_functions omap2_clk_functions = { | |||
1051 | .clk_disable_unused = omap2_clk_disable_unused, | 1119 | .clk_disable_unused = omap2_clk_disable_unused, |
1052 | }; | 1120 | }; |
1053 | 1121 | ||
1054 | static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys) | 1122 | static u32 omap2_get_apll_clkin(void) |
1055 | { | 1123 | { |
1056 | u32 div, aplls, sclk = 13000000; | 1124 | u32 aplls, sclk = 0; |
1057 | 1125 | ||
1058 | aplls = CM_CLKSEL1_PLL; | 1126 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); |
1059 | aplls &= ((1 << 23) | (1 << 24) | (1 << 25)); | 1127 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; |
1060 | aplls >>= 23; /* Isolate field, 0,2,3 */ | 1128 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; |
1061 | 1129 | ||
1062 | if (aplls == 0) | 1130 | if (aplls == APLLS_CLKIN_19_2MHZ) |
1063 | sclk = 19200000; | 1131 | sclk = 19200000; |
1064 | else if (aplls == 2) | 1132 | else if (aplls == APLLS_CLKIN_13MHZ) |
1065 | sclk = 13000000; | 1133 | sclk = 13000000; |
1066 | else if (aplls == 3) | 1134 | else if (aplls == APLLS_CLKIN_12MHZ) |
1067 | sclk = 12000000; | 1135 | sclk = 12000000; |
1068 | 1136 | ||
1069 | div = PRCM_CLKSRC_CTRL; | 1137 | return sclk; |
1070 | div &= ((1 << 7) | (1 << 6)); | 1138 | } |
1071 | div >>= sys->rate_offset; | 1139 | |
1140 | static u32 omap2_get_sysclkdiv(void) | ||
1141 | { | ||
1142 | u32 div; | ||
1143 | |||
1144 | div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); | ||
1145 | div &= OMAP_SYSCLKDIV_MASK; | ||
1146 | div >>= OMAP_SYSCLKDIV_SHIFT; | ||
1072 | 1147 | ||
1073 | osc->rate = sclk * div; | 1148 | return div; |
1074 | sys->rate = sclk; | 1149 | } |
1150 | |||
1151 | static void omap2_osc_clk_recalc(struct clk *clk) | ||
1152 | { | ||
1153 | clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); | ||
1154 | propagate_rate(clk); | ||
1155 | } | ||
1156 | |||
1157 | static void omap2_sys_clk_recalc(struct clk *clk) | ||
1158 | { | ||
1159 | clk->rate = clk->parent->rate / omap2_get_sysclkdiv(); | ||
1160 | propagate_rate(clk); | ||
1075 | } | 1161 | } |
1076 | 1162 | ||
1077 | /* | 1163 | /* |
@@ -1100,8 +1186,7 @@ static int __init omap2_clk_arch_init(void) | |||
1100 | if (omap2_select_table_rate(&virt_prcm_set, mpurate)) | 1186 | if (omap2_select_table_rate(&virt_prcm_set, mpurate)) |
1101 | printk(KERN_ERR "Could not find matching MPU rate\n"); | 1187 | printk(KERN_ERR "Could not find matching MPU rate\n"); |
1102 | 1188 | ||
1103 | propagate_rate(&osc_ck); /* update main root fast */ | 1189 | recalculate_root_clocks(); |
1104 | propagate_rate(&func_32k_ck); /* update main root slow */ | ||
1105 | 1190 | ||
1106 | printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " | 1191 | printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " |
1107 | "%ld.%01ld/%ld/%ld MHz\n", | 1192 | "%ld.%01ld/%ld/%ld MHz\n", |
@@ -1115,13 +1200,21 @@ arch_initcall(omap2_clk_arch_init); | |||
1115 | int __init omap2_clk_init(void) | 1200 | int __init omap2_clk_init(void) |
1116 | { | 1201 | { |
1117 | struct prcm_config *prcm; | 1202 | struct prcm_config *prcm; |
1118 | struct clk ** clkp; | 1203 | struct clk **clkp; |
1119 | u32 clkrate; | 1204 | u32 clkrate; |
1120 | 1205 | ||
1206 | if (cpu_is_omap242x()) | ||
1207 | cpu_mask = RATE_IN_242X; | ||
1208 | else if (cpu_is_omap2430()) | ||
1209 | cpu_mask = RATE_IN_243X; | ||
1210 | |||
1121 | clk_init(&omap2_clk_functions); | 1211 | clk_init(&omap2_clk_functions); |
1122 | omap2_get_crystal_rate(&osc_ck, &sys_ck); | ||
1123 | 1212 | ||
1124 | for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks); | 1213 | omap2_osc_clk_recalc(&osc_ck); |
1214 | omap2_sys_clk_recalc(&sys_ck); | ||
1215 | |||
1216 | for (clkp = onchip_24xx_clks; | ||
1217 | clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); | ||
1125 | clkp++) { | 1218 | clkp++) { |
1126 | 1219 | ||
1127 | if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { | 1220 | if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { |
@@ -1136,8 +1229,10 @@ int __init omap2_clk_init(void) | |||
1136 | } | 1229 | } |
1137 | 1230 | ||
1138 | /* Check the MPU rate set by bootloader */ | 1231 | /* Check the MPU rate set by bootloader */ |
1139 | clkrate = omap2_get_dpll_rate(&dpll_ck); | 1232 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); |
1140 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | 1233 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
1234 | if (!(prcm->flags & cpu_mask)) | ||
1235 | continue; | ||
1141 | if (prcm->xtal_speed != sys_ck.rate) | 1236 | if (prcm->xtal_speed != sys_ck.rate) |
1142 | continue; | 1237 | continue; |
1143 | if (prcm->dpll_speed <= clkrate) | 1238 | if (prcm->dpll_speed <= clkrate) |
@@ -1145,8 +1240,7 @@ int __init omap2_clk_init(void) | |||
1145 | } | 1240 | } |
1146 | curr_prcm_set = prcm; | 1241 | curr_prcm_set = prcm; |
1147 | 1242 | ||
1148 | propagate_rate(&osc_ck); /* update main root fast */ | 1243 | recalculate_root_clocks(); |
1149 | propagate_rate(&func_32k_ck); /* update main root slow */ | ||
1150 | 1244 | ||
1151 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " | 1245 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " |
1152 | "%ld.%01ld/%ld/%ld MHz\n", | 1246 | "%ld.%01ld/%ld/%ld MHz\n", |
@@ -1157,16 +1251,7 @@ int __init omap2_clk_init(void) | |||
1157 | * Only enable those clocks we will need, let the drivers | 1251 | * Only enable those clocks we will need, let the drivers |
1158 | * enable other clocks as necessary | 1252 | * enable other clocks as necessary |
1159 | */ | 1253 | */ |
1160 | clk_enable(&sync_32k_ick); | 1254 | clk_enable_init_clocks(); |
1161 | clk_enable(&omapctrl_ick); | ||
1162 | |||
1163 | /* Force the APLLs always active. The clocks are idled | ||
1164 | * automatically by hardware. */ | ||
1165 | clk_enable(&apll96_ck); | ||
1166 | clk_enable(&apll54_ck); | ||
1167 | |||
1168 | if (cpu_is_omap2430()) | ||
1169 | clk_enable(&sdrc_ick); | ||
1170 | 1255 | ||
1171 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | 1256 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ |
1172 | vclk = clk_get(NULL, "virt_prcm_set"); | 1257 | vclk = clk_get(NULL, "virt_prcm_set"); |
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 4f791866b910..9363c207f581 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h | |||
@@ -14,24 +14,29 @@ | |||
14 | * published by the Free Software Foundation. | 14 | * published by the Free Software Foundation. |
15 | */ | 15 | */ |
16 | 16 | ||
17 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H | 17 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H |
18 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H | 18 | #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H |
19 | 19 | ||
20 | static void omap2_sys_clk_recalc(struct clk * clk); | 20 | #include "clock.h" |
21 | static void omap2_clksel_recalc(struct clk * clk); | 21 | |
22 | static void omap2_followparent_recalc(struct clk * clk); | 22 | #include "prm.h" |
23 | static void omap2_propagate_rate(struct clk * clk); | 23 | #include "cm.h" |
24 | static void omap2_mpu_recalc(struct clk * clk); | 24 | #include "prm-regbits-24xx.h" |
25 | #include "cm-regbits-24xx.h" | ||
26 | #include "sdrc.h" | ||
27 | |||
28 | static void omap2_table_mpu_recalc(struct clk * clk); | ||
25 | static int omap2_select_table_rate(struct clk * clk, unsigned long rate); | 29 | static int omap2_select_table_rate(struct clk * clk, unsigned long rate); |
26 | static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate); | 30 | static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate); |
27 | static void omap2_clk_disable(struct clk *clk); | ||
28 | static void omap2_sys_clk_recalc(struct clk * clk); | 31 | static void omap2_sys_clk_recalc(struct clk * clk); |
29 | static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val); | 32 | static void omap2_osc_clk_recalc(struct clk * clk); |
30 | static u32 omap2_clksel_get_divisor(struct clk *clk); | 33 | static void omap2_sys_clk_recalc(struct clk * clk); |
31 | 34 | static void omap2_dpll_recalc(struct clk * clk); | |
32 | 35 | static int omap2_clk_fixed_enable(struct clk * clk); | |
33 | #define RATE_IN_242X (1 << 0) | 36 | static void omap2_clk_fixed_disable(struct clk * clk); |
34 | #define RATE_IN_243X (1 << 1) | 37 | static int omap2_enable_osc_ck(struct clk * clk); |
38 | static void omap2_disable_osc_ck(struct clk * clk); | ||
39 | static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate); | ||
35 | 40 | ||
36 | /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | 41 | /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. |
37 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP | 42 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP |
@@ -52,16 +57,6 @@ struct prcm_config { | |||
52 | unsigned char flags; | 57 | unsigned char flags; |
53 | }; | 58 | }; |
54 | 59 | ||
55 | /* Mask for clksel which support parent settign in set_rate */ | ||
56 | #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \ | ||
57 | CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1) | ||
58 | |||
59 | /* Mask for clksel regs which support rate operations */ | ||
60 | #define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \ | ||
61 | CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \ | ||
62 | CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \ | ||
63 | CM_SYSCLKOUT_SEL1) | ||
64 | |||
65 | /* | 60 | /* |
66 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. | 61 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. |
67 | * These configurations are characterized by voltage and speed for clocks. | 62 | * These configurations are characterized by voltage and speed for clocks. |
@@ -174,7 +169,7 @@ struct prcm_config { | |||
174 | #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ | 169 | #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ |
175 | #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ | 170 | #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ |
176 | #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ | 171 | #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ |
177 | #define RII_CLKSEL_IVA (6 << 8) /* iva1 - 200MHz */ | 172 | #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ |
178 | #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ | 173 | #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ |
179 | #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \ | 174 | #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \ |
180 | RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ | 175 | RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ |
@@ -182,6 +177,27 @@ struct prcm_config { | |||
182 | #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ | 177 | #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ |
183 | #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX | 178 | #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX |
184 | 179 | ||
180 | /* 2420-PRCM I 660MHz core */ | ||
181 | #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ | ||
182 | #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ | ||
183 | #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ | ||
184 | #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \ | ||
185 | RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ | ||
186 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
187 | RI_CLKSEL_L4 | RI_CLKSEL_L3 | ||
188 | #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ | ||
189 | #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU | ||
190 | #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ | ||
191 | #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ | ||
192 | #define RI_SYNC_DSP (1 << 7) /* Activate sync */ | ||
193 | #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ | ||
194 | #define RI_SYNC_IVA (0 << 13) /* Bypass sync */ | ||
195 | #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \ | ||
196 | RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ | ||
197 | RI_CLKSEL_DSP | ||
198 | #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ | ||
199 | #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX | ||
200 | |||
185 | /* 2420-PRCM VII (boot) */ | 201 | /* 2420-PRCM VII (boot) */ |
186 | #define RVII_CLKSEL_L3 (1 << 0) | 202 | #define RVII_CLKSEL_L3 (1 << 0) |
187 | #define RVII_CLKSEL_L4 (1 << 5) | 203 | #define RVII_CLKSEL_L4 (1 << 5) |
@@ -224,7 +240,6 @@ struct prcm_config { | |||
224 | 240 | ||
225 | /* | 241 | /* |
226 | * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed | 242 | * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed |
227 | * #2 (ratio1) baseport-target | ||
228 | * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz | 243 | * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz |
229 | */ | 244 | */ |
230 | #define M5A_DPLL_MULT_12 (133 << 12) | 245 | #define M5A_DPLL_MULT_12 (133 << 12) |
@@ -232,13 +247,13 @@ struct prcm_config { | |||
232 | #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | 247 | #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
233 | M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ | 248 | M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ |
234 | MX_APLLS_CLIKIN_12 | 249 | MX_APLLS_CLIKIN_12 |
235 | #define M5A_DPLL_MULT_13 (266 << 12) | 250 | #define M5A_DPLL_MULT_13 (61 << 12) |
236 | #define M5A_DPLL_DIV_13 (12 << 8) | 251 | #define M5A_DPLL_DIV_13 (2 << 8) |
237 | #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | 252 | #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
238 | M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ | 253 | M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ |
239 | MX_APLLS_CLIKIN_13 | 254 | MX_APLLS_CLIKIN_13 |
240 | #define M5A_DPLL_MULT_19 (180 << 12) | 255 | #define M5A_DPLL_MULT_19 (55 << 12) |
241 | #define M5A_DPLL_DIV_19 (12 << 8) | 256 | #define M5A_DPLL_DIV_19 (3 << 8) |
242 | #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | 257 | #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ |
243 | M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ | 258 | M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ |
244 | MX_APLLS_CLIKIN_19_2 | 259 | MX_APLLS_CLIKIN_19_2 |
@@ -260,7 +275,27 @@ struct prcm_config { | |||
260 | M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ | 275 | M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ |
261 | MX_APLLS_CLIKIN_19_2 | 276 | MX_APLLS_CLIKIN_19_2 |
262 | /* | 277 | /* |
263 | * #4 (ratio2) | 278 | * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz |
279 | */ | ||
280 | #define M4_DPLL_MULT_12 (133 << 12) | ||
281 | #define M4_DPLL_DIV_12 (3 << 8) | ||
282 | #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
283 | M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ | ||
284 | MX_APLLS_CLIKIN_12 | ||
285 | |||
286 | #define M4_DPLL_MULT_13 (399 << 12) | ||
287 | #define M4_DPLL_DIV_13 (12 << 8) | ||
288 | #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
289 | M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ | ||
290 | MX_APLLS_CLIKIN_13 | ||
291 | |||
292 | #define M4_DPLL_MULT_19 (145 << 12) | ||
293 | #define M4_DPLL_DIV_19 (6 << 8) | ||
294 | #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
295 | M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ | ||
296 | MX_APLLS_CLIKIN_19_2 | ||
297 | |||
298 | /* | ||
264 | * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz | 299 | * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz |
265 | */ | 300 | */ |
266 | #define M3_DPLL_MULT_12 (55 << 12) | 301 | #define M3_DPLL_MULT_12 (55 << 12) |
@@ -268,16 +303,41 @@ struct prcm_config { | |||
268 | #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | 303 | #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
269 | M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ | 304 | M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ |
270 | MX_APLLS_CLIKIN_12 | 305 | MX_APLLS_CLIKIN_12 |
271 | #define M3_DPLL_MULT_13 (330 << 12) | 306 | #define M3_DPLL_MULT_13 (76 << 12) |
272 | #define M3_DPLL_DIV_13 (12 << 8) | 307 | #define M3_DPLL_DIV_13 (2 << 8) |
273 | #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | 308 | #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
274 | M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ | 309 | M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ |
275 | MX_APLLS_CLIKIN_13 | 310 | MX_APLLS_CLIKIN_13 |
276 | #define M3_DPLL_MULT_19 (275 << 12) | 311 | #define M3_DPLL_MULT_19 (17 << 12) |
277 | #define M3_DPLL_DIV_19 (15 << 8) | 312 | #define M3_DPLL_DIV_19 (0 << 8) |
278 | #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | 313 | #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ |
279 | M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ | 314 | M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ |
280 | MX_APLLS_CLIKIN_19_2 | 315 | MX_APLLS_CLIKIN_19_2 |
316 | |||
317 | /* | ||
318 | * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz | ||
319 | */ | ||
320 | #define M2_DPLL_MULT_12 (55 << 12) | ||
321 | #define M2_DPLL_DIV_12 (1 << 8) | ||
322 | #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
323 | M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ | ||
324 | MX_APLLS_CLIKIN_12 | ||
325 | |||
326 | /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, | ||
327 | * relock time issue */ | ||
328 | /* Core frequency changed from 330/165 to 329/164 MHz*/ | ||
329 | #define M2_DPLL_MULT_13 (76 << 12) | ||
330 | #define M2_DPLL_DIV_13 (2 << 8) | ||
331 | #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
332 | M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ | ||
333 | MX_APLLS_CLIKIN_13 | ||
334 | |||
335 | #define M2_DPLL_MULT_19 (17 << 12) | ||
336 | #define M2_DPLL_DIV_19 (0 << 8) | ||
337 | #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
338 | M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ | ||
339 | MX_APLLS_CLIKIN_19_2 | ||
340 | |||
281 | /* boot (boot) */ | 341 | /* boot (boot) */ |
282 | #define MB_DPLL_MULT (1 << 12) | 342 | #define MB_DPLL_MULT (1 << 12) |
283 | #define MB_DPLL_DIV (0 << 8) | 343 | #define MB_DPLL_DIV (0 << 8) |
@@ -300,6 +360,13 @@ struct prcm_config { | |||
300 | * boot (boot) | 360 | * boot (boot) |
301 | */ | 361 | */ |
302 | 362 | ||
363 | /* PRCM I target DPLL = 2*330MHz = 660MHz */ | ||
364 | #define MI_DPLL_MULT_12 (55 << 12) | ||
365 | #define MI_DPLL_DIV_12 (1 << 8) | ||
366 | #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
367 | MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ | ||
368 | MX_APLLS_CLIKIN_12 | ||
369 | |||
303 | /* | 370 | /* |
304 | * 2420 Equivalent - mode registers | 371 | * 2420 Equivalent - mode registers |
305 | * PRCM II , target DPLL = 2*300MHz = 600MHz | 372 | * PRCM II , target DPLL = 2*300MHz = 600MHz |
@@ -335,28 +402,6 @@ struct prcm_config { | |||
335 | #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) | 402 | #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) |
336 | #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) | 403 | #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) |
337 | 404 | ||
338 | /* | ||
339 | * These represent optimal values for common parts, it won't work for all. | ||
340 | * As long as you scale down, most parameters are still work, they just | ||
341 | * become sub-optimal. The RFR value goes in the opposite direction. If you | ||
342 | * don't adjust it down as your clock period increases the refresh interval | ||
343 | * will not be met. Setting all parameters for complete worst case may work, | ||
344 | * but may cut memory performance by 2x. Due to errata the DLLs need to be | ||
345 | * unlocked and their value needs run time calibration. A dynamic call is | ||
346 | * need for that as no single right value exists acorss production samples. | ||
347 | * | ||
348 | * Only the FULL speed values are given. Current code is such that rate | ||
349 | * changes must be made at DPLLoutx2. The actual value adjustment for low | ||
350 | * frequency operation will be handled by omap_set_performance() | ||
351 | * | ||
352 | * By having the boot loader boot up in the fastest L4 speed available likely | ||
353 | * will result in something which you can switch between. | ||
354 | */ | ||
355 | #define V24XX_SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) | ||
356 | #define V24XX_SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) | ||
357 | #define V24XX_SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ | ||
358 | #define V24XX_SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ | ||
359 | |||
360 | /* MPU speed defines */ | 405 | /* MPU speed defines */ |
361 | #define S12M 12000000 | 406 | #define S12M 12000000 |
362 | #define S13M 13000000 | 407 | #define S13M 13000000 |
@@ -365,15 +410,21 @@ struct prcm_config { | |||
365 | #define S100M 100000000 | 410 | #define S100M 100000000 |
366 | #define S133M 133000000 | 411 | #define S133M 133000000 |
367 | #define S150M 150000000 | 412 | #define S150M 150000000 |
413 | #define S164M 164000000 | ||
368 | #define S165M 165000000 | 414 | #define S165M 165000000 |
415 | #define S199M 199000000 | ||
369 | #define S200M 200000000 | 416 | #define S200M 200000000 |
370 | #define S266M 266000000 | 417 | #define S266M 266000000 |
371 | #define S300M 300000000 | 418 | #define S300M 300000000 |
419 | #define S329M 329000000 | ||
372 | #define S330M 330000000 | 420 | #define S330M 330000000 |
421 | #define S399M 399000000 | ||
373 | #define S400M 400000000 | 422 | #define S400M 400000000 |
374 | #define S532M 532000000 | 423 | #define S532M 532000000 |
375 | #define S600M 600000000 | 424 | #define S600M 600000000 |
425 | #define S658M 658000000 | ||
376 | #define S660M 660000000 | 426 | #define S660M 660000000 |
427 | #define S798M 798000000 | ||
377 | 428 | ||
378 | /*------------------------------------------------------------------------- | 429 | /*------------------------------------------------------------------------- |
379 | * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | 430 | * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. |
@@ -394,78 +445,93 @@ struct prcm_config { | |||
394 | * Note: This table needs to be sorted, fastest to slowest. | 445 | * Note: This table needs to be sorted, fastest to slowest. |
395 | *-------------------------------------------------------------------------*/ | 446 | *-------------------------------------------------------------------------*/ |
396 | static struct prcm_config rate_table[] = { | 447 | static struct prcm_config rate_table[] = { |
448 | /* PRCM I - FAST */ | ||
449 | {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ | ||
450 | RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL, | ||
451 | RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL, | ||
452 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz, | ||
453 | RATE_IN_242X}, | ||
454 | |||
397 | /* PRCM II - FAST */ | 455 | /* PRCM II - FAST */ |
398 | {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ | 456 | {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ |
399 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | 457 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
400 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, | 458 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, |
401 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, | 459 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, |
402 | RATE_IN_242X}, | 460 | RATE_IN_242X}, |
403 | 461 | ||
404 | {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ | 462 | {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ |
405 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | 463 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
406 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, | 464 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, |
407 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, | 465 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, |
408 | RATE_IN_242X}, | 466 | RATE_IN_242X}, |
409 | 467 | ||
410 | /* PRCM III - FAST */ | 468 | /* PRCM III - FAST */ |
411 | {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | 469 | {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ |
412 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | 470 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
413 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, | 471 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, |
414 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, | 472 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, |
415 | RATE_IN_242X}, | 473 | RATE_IN_242X}, |
416 | 474 | ||
417 | {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | 475 | {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ |
418 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | 476 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
419 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, | 477 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, |
420 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, | 478 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, |
421 | RATE_IN_242X}, | 479 | RATE_IN_242X}, |
422 | 480 | ||
423 | /* PRCM II - SLOW */ | 481 | /* PRCM II - SLOW */ |
424 | {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ | 482 | {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ |
425 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | 483 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
426 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, | 484 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, |
427 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, | 485 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, |
428 | RATE_IN_242X}, | 486 | RATE_IN_242X}, |
429 | 487 | ||
430 | {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ | 488 | {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ |
431 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | 489 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
432 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, | 490 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, |
433 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, | 491 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, |
434 | RATE_IN_242X}, | 492 | RATE_IN_242X}, |
435 | 493 | ||
436 | /* PRCM III - SLOW */ | 494 | /* PRCM III - SLOW */ |
437 | {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | 495 | {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ |
438 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | 496 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
439 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, | 497 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, |
440 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, | 498 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, |
441 | RATE_IN_242X}, | 499 | RATE_IN_242X}, |
442 | 500 | ||
443 | {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | 501 | {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ |
444 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | 502 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
445 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, | 503 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, |
446 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, | 504 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, |
447 | RATE_IN_242X}, | 505 | RATE_IN_242X}, |
448 | 506 | ||
449 | /* PRCM-VII (boot-bypass) */ | 507 | /* PRCM-VII (boot-bypass) */ |
450 | {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ | 508 | {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ |
451 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, | 509 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, |
452 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, | 510 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, |
453 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS, | 511 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, |
454 | RATE_IN_242X}, | 512 | RATE_IN_242X}, |
455 | 513 | ||
456 | /* PRCM-VII (boot-bypass) */ | 514 | /* PRCM-VII (boot-bypass) */ |
457 | {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ | 515 | {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ |
458 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, | 516 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, |
459 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, | 517 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, |
460 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS, | 518 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, |
461 | RATE_IN_242X}, | 519 | RATE_IN_242X}, |
462 | 520 | ||
463 | /* PRCM #3 - ratio2 (ES2) - FAST */ | 521 | /* PRCM #4 - ratio2 (ES2.1) - FAST */ |
464 | {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ | 522 | {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ |
465 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | 523 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, |
466 | R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL, | 524 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, |
467 | MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, | 525 | MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, |
468 | V24XX_SDRC_RFR_CTRL_110MHz, | 526 | SDRC_RFR_CTRL_133MHz, |
527 | RATE_IN_243X}, | ||
528 | |||
529 | /* PRCM #2 - ratio1 (ES2) - FAST */ | ||
530 | {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ | ||
531 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
532 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, | ||
533 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
534 | SDRC_RFR_CTRL_165MHz, | ||
469 | RATE_IN_243X}, | 535 | RATE_IN_243X}, |
470 | 536 | ||
471 | /* PRCM #5a - ratio1 - FAST */ | 537 | /* PRCM #5a - ratio1 - FAST */ |
@@ -473,7 +539,7 @@ static struct prcm_config rate_table[] = { | |||
473 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | 539 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
474 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | 540 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, |
475 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | 541 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, |
476 | V24XX_SDRC_RFR_CTRL_133MHz, | 542 | SDRC_RFR_CTRL_133MHz, |
477 | RATE_IN_243X}, | 543 | RATE_IN_243X}, |
478 | 544 | ||
479 | /* PRCM #5b - ratio1 - FAST */ | 545 | /* PRCM #5b - ratio1 - FAST */ |
@@ -481,15 +547,23 @@ static struct prcm_config rate_table[] = { | |||
481 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | 547 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
482 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | 548 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, |
483 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | 549 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, |
484 | V24XX_SDRC_RFR_CTRL_100MHz, | 550 | SDRC_RFR_CTRL_100MHz, |
485 | RATE_IN_243X}, | 551 | RATE_IN_243X}, |
486 | 552 | ||
487 | /* PRCM #3 - ratio2 (ES2) - SLOW */ | 553 | /* PRCM #4 - ratio1 (ES2.1) - SLOW */ |
488 | {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ | 554 | {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ |
489 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | 555 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, |
490 | R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL, | 556 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, |
491 | MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, | 557 | MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, |
492 | V24XX_SDRC_RFR_CTRL_110MHz, | 558 | SDRC_RFR_CTRL_133MHz, |
559 | RATE_IN_243X}, | ||
560 | |||
561 | /* PRCM #2 - ratio1 (ES2) - SLOW */ | ||
562 | {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ | ||
563 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
564 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, | ||
565 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
566 | SDRC_RFR_CTRL_165MHz, | ||
493 | RATE_IN_243X}, | 567 | RATE_IN_243X}, |
494 | 568 | ||
495 | /* PRCM #5a - ratio1 - SLOW */ | 569 | /* PRCM #5a - ratio1 - SLOW */ |
@@ -497,7 +571,7 @@ static struct prcm_config rate_table[] = { | |||
497 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | 571 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
498 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | 572 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, |
499 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | 573 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, |
500 | V24XX_SDRC_RFR_CTRL_133MHz, | 574 | SDRC_RFR_CTRL_133MHz, |
501 | RATE_IN_243X}, | 575 | RATE_IN_243X}, |
502 | 576 | ||
503 | /* PRCM #5b - ratio1 - SLOW*/ | 577 | /* PRCM #5b - ratio1 - SLOW*/ |
@@ -505,7 +579,7 @@ static struct prcm_config rate_table[] = { | |||
505 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | 579 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
506 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | 580 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, |
507 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | 581 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, |
508 | V24XX_SDRC_RFR_CTRL_100MHz, | 582 | SDRC_RFR_CTRL_100MHz, |
509 | RATE_IN_243X}, | 583 | RATE_IN_243X}, |
510 | 584 | ||
511 | /* PRCM-boot/bypass */ | 585 | /* PRCM-boot/bypass */ |
@@ -513,7 +587,7 @@ static struct prcm_config rate_table[] = { | |||
513 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | 587 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, |
514 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, | 588 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, |
515 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | 589 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, |
516 | V24XX_SDRC_RFR_CTRL_BYPASS, | 590 | SDRC_RFR_CTRL_BYPASS, |
517 | RATE_IN_243X}, | 591 | RATE_IN_243X}, |
518 | 592 | ||
519 | /* PRCM-boot/bypass */ | 593 | /* PRCM-boot/bypass */ |
@@ -521,7 +595,7 @@ static struct prcm_config rate_table[] = { | |||
521 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | 595 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, |
522 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, | 596 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, |
523 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | 597 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, |
524 | V24XX_SDRC_RFR_CTRL_BYPASS, | 598 | SDRC_RFR_CTRL_BYPASS, |
525 | RATE_IN_243X}, | 599 | RATE_IN_243X}, |
526 | 600 | ||
527 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | 601 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
@@ -547,6 +621,7 @@ static struct prcm_config rate_table[] = { | |||
547 | * clocks. | 621 | * clocks. |
548 | *-------------------------------------------------------------------------*/ | 622 | *-------------------------------------------------------------------------*/ |
549 | 623 | ||
624 | #ifdef OLD_CK | ||
550 | /* Base external input clocks */ | 625 | /* Base external input clocks */ |
551 | static struct clk func_32k_ck = { | 626 | static struct clk func_32k_ck = { |
552 | .name = "func_32k_ck", | 627 | .name = "func_32k_ck", |
@@ -554,7 +629,7 @@ static struct clk func_32k_ck = { | |||
554 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 629 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
555 | RATE_FIXED | ALWAYS_ENABLED, | 630 | RATE_FIXED | ALWAYS_ENABLED, |
556 | }; | 631 | }; |
557 | 632 | #endif /* OLD_CK */ | |
558 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ | 633 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
559 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | 634 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ |
560 | .name = "osc_ck", | 635 | .name = "osc_ck", |
@@ -570,10 +645,9 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ | |||
570 | .rate = 13000000, | 645 | .rate = 13000000, |
571 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 646 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
572 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | 647 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, |
573 | .rate_offset = 6, /* sysclkdiv 1 or 2, already handled or no boot */ | ||
574 | .recalc = &omap2_sys_clk_recalc, | 648 | .recalc = &omap2_sys_clk_recalc, |
575 | }; | 649 | }; |
576 | 650 | #ifdef OLD_CK | |
577 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | 651 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
578 | .name = "alt_ck", | 652 | .name = "alt_ck", |
579 | .rate = 54000000, | 653 | .rate = 54000000, |
@@ -581,29 +655,43 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | |||
581 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | 655 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, |
582 | .recalc = &omap2_propagate_rate, | 656 | .recalc = &omap2_propagate_rate, |
583 | }; | 657 | }; |
584 | 658 | #endif /* OLD_CK */ | |
585 | /* | 659 | /* |
586 | * Analog domain root source clocks | 660 | * Analog domain root source clocks |
587 | */ | 661 | */ |
588 | 662 | ||
589 | /* dpll_ck, is broken out in to special cases through clksel */ | 663 | /* dpll_ck, is broken out in to special cases through clksel */ |
664 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... | ||
665 | * deal with this | ||
666 | */ | ||
667 | |||
668 | static const struct dpll_data dpll_dd = { | ||
669 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
670 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | ||
671 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | ||
672 | }; | ||
673 | |||
590 | static struct clk dpll_ck = { | 674 | static struct clk dpll_ck = { |
591 | .name = "dpll_ck", | 675 | .name = "dpll_ck", |
592 | .parent = &sys_ck, /* Can be func_32k also */ | 676 | .parent = &sys_ck, /* Can be func_32k also */ |
677 | .dpll_data = &dpll_dd, | ||
593 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 678 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
594 | RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1, | 679 | RATE_PROPAGATES | ALWAYS_ENABLED, |
595 | .recalc = &omap2_clksel_recalc, | 680 | .recalc = &omap2_dpll_recalc, |
681 | .set_rate = &omap2_reprogram_dpll, | ||
596 | }; | 682 | }; |
597 | 683 | ||
598 | static struct clk apll96_ck = { | 684 | static struct clk apll96_ck = { |
599 | .name = "apll96_ck", | 685 | .name = "apll96_ck", |
600 | .parent = &sys_ck, | 686 | .parent = &sys_ck, |
601 | .rate = 96000000, | 687 | .rate = 96000000, |
602 | .flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X | | 688 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
603 | RATE_FIXED | RATE_PROPAGATES, | 689 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, |
604 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, | 690 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
605 | .enable_bit = 0x2, | 691 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, |
606 | .recalc = &omap2_propagate_rate, | 692 | .enable = &omap2_clk_fixed_enable, |
693 | .disable = &omap2_clk_fixed_disable, | ||
694 | .recalc = &propagate_rate, | ||
607 | }; | 695 | }; |
608 | 696 | ||
609 | static struct clk apll54_ck = { | 697 | static struct clk apll54_ck = { |
@@ -611,15 +699,18 @@ static struct clk apll54_ck = { | |||
611 | .parent = &sys_ck, | 699 | .parent = &sys_ck, |
612 | .rate = 54000000, | 700 | .rate = 54000000, |
613 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 701 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
614 | RATE_FIXED | RATE_PROPAGATES, | 702 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, |
615 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, | 703 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
616 | .enable_bit = 0x6, | 704 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, |
617 | .recalc = &omap2_propagate_rate, | 705 | .enable = &omap2_clk_fixed_enable, |
706 | .disable = &omap2_clk_fixed_disable, | ||
707 | .recalc = &propagate_rate, | ||
618 | }; | 708 | }; |
619 | 709 | ||
620 | /* | 710 | /* |
621 | * PRCM digital base sources | 711 | * PRCM digital base sources |
622 | */ | 712 | */ |
713 | #ifdef OLD_CK | ||
623 | static struct clk func_54m_ck = { | 714 | static struct clk func_54m_ck = { |
624 | .name = "func_54m_ck", | 715 | .name = "func_54m_ck", |
625 | .parent = &apll54_ck, /* can also be alt_clk */ | 716 | .parent = &apll54_ck, /* can also be alt_clk */ |
@@ -631,15 +722,15 @@ static struct clk func_54m_ck = { | |||
631 | .enable_bit = 0xff, | 722 | .enable_bit = 0xff, |
632 | .recalc = &omap2_propagate_rate, | 723 | .recalc = &omap2_propagate_rate, |
633 | }; | 724 | }; |
634 | 725 | #endif /* OLD_CK */ | |
635 | static struct clk core_ck = { | 726 | static struct clk core_ck = { |
636 | .name = "core_ck", | 727 | .name = "core_ck", |
637 | .parent = &dpll_ck, /* can also be 32k */ | 728 | .parent = &dpll_ck, /* can also be 32k */ |
638 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 729 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
639 | ALWAYS_ENABLED | RATE_PROPAGATES, | 730 | ALWAYS_ENABLED | RATE_PROPAGATES, |
640 | .recalc = &omap2_propagate_rate, | 731 | .recalc = &followparent_recalc, |
641 | }; | 732 | }; |
642 | 733 | #ifdef OLD_CK | |
643 | static struct clk sleep_ck = { /* sys_clk or 32k */ | 734 | static struct clk sleep_ck = { /* sys_clk or 32k */ |
644 | .name = "sleep_ck", | 735 | .name = "sleep_ck", |
645 | .parent = &func_32k_ck, | 736 | .parent = &func_32k_ck, |
@@ -726,7 +817,7 @@ static struct clk emul_ck = { | |||
726 | .recalc = &omap2_propagate_rate, | 817 | .recalc = &omap2_propagate_rate, |
727 | 818 | ||
728 | }; | 819 | }; |
729 | 820 | #endif /* OLD_CK */ | |
730 | /* | 821 | /* |
731 | * MPU clock domain | 822 | * MPU clock domain |
732 | * Clocks: | 823 | * Clocks: |
@@ -740,13 +831,17 @@ static struct clk emul_ck = { | |||
740 | static struct clk mpu_ck = { /* Control cpu */ | 831 | static struct clk mpu_ck = { /* Control cpu */ |
741 | .name = "mpu_ck", | 832 | .name = "mpu_ck", |
742 | .parent = &core_ck, | 833 | .parent = &core_ck, |
743 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL | | 834 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
744 | ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP | | 835 | ALWAYS_ENABLED | DELAYED_APP | |
745 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | 836 | CONFIG_PARTICIPANT | RATE_PROPAGATES, |
746 | .rate_offset = 0, /* bits 0-4 */ | 837 | .init = &omap2_init_clksel_parent, |
838 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | ||
839 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | ||
747 | .recalc = &omap2_clksel_recalc, | 840 | .recalc = &omap2_clksel_recalc, |
841 | .round_rate = &omap2_clksel_round_rate, | ||
842 | .set_rate = &omap2_clksel_set_rate | ||
748 | }; | 843 | }; |
749 | 844 | #ifdef OLD_CK | |
750 | /* | 845 | /* |
751 | * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain | 846 | * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain |
752 | * Clocks: | 847 | * Clocks: |
@@ -1933,7 +2028,7 @@ static struct clk mmchsdb2_fck = { | |||
1933 | .enable_bit = 17, | 2028 | .enable_bit = 17, |
1934 | .recalc = &omap2_followparent_recalc, | 2029 | .recalc = &omap2_followparent_recalc, |
1935 | }; | 2030 | }; |
1936 | 2031 | #endif /* OLD_CK */ | |
1937 | /* | 2032 | /* |
1938 | * This clock is a composite clock which does entire set changes then | 2033 | * This clock is a composite clock which does entire set changes then |
1939 | * forces a rebalance. It keys on the MPU speed, but it really could | 2034 | * forces a rebalance. It keys on the MPU speed, but it really could |
@@ -1953,11 +2048,10 @@ static struct clk virt_prcm_set = { | |||
1953 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 2048 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
1954 | VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, | 2049 | VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, |
1955 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ | 2050 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
1956 | .recalc = &omap2_mpu_recalc, /* sets are keyed on mpu rate */ | ||
1957 | .set_rate = &omap2_select_table_rate, | 2051 | .set_rate = &omap2_select_table_rate, |
1958 | .round_rate = &omap2_round_to_table_rate, | 2052 | .round_rate = &omap2_round_to_table_rate, |
1959 | }; | 2053 | }; |
1960 | 2054 | #ifdef OLD_CK | |
1961 | static struct clk *onchip_clks[] = { | 2055 | static struct clk *onchip_clks[] = { |
1962 | /* external root sources */ | 2056 | /* external root sources */ |
1963 | &func_32k_ck, | 2057 | &func_32k_ck, |
@@ -2107,5 +2201,17 @@ static struct clk *onchip_clks[] = { | |||
2107 | &mmchsdb1_fck, | 2201 | &mmchsdb1_fck, |
2108 | &mmchsdb2_fck, | 2202 | &mmchsdb2_fck, |
2109 | }; | 2203 | }; |
2204 | #endif /* OLD_CK */ | ||
2205 | |||
2206 | static struct clk *onchip_24xx_clks[] __initdata = { | ||
2207 | /* external root sources */ | ||
2208 | &osc_ck, | ||
2209 | &sys_ck, | ||
2210 | /* internal analog sources */ | ||
2211 | &dpll_ck, | ||
2212 | &apll96_ck, | ||
2213 | &apll54_ck, | ||
2214 | }; | ||
2110 | 2215 | ||
2111 | #endif | 2216 | #endif |
2217 | |||
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index b56c1a082d92..12479081881a 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c | |||
@@ -53,6 +53,54 @@ u32 omap2_memory_get_type(void) | |||
53 | return mem_timings.m_type; | 53 | return mem_timings.m_type; |
54 | } | 54 | } |
55 | 55 | ||
56 | /* | ||
57 | * Check the DLL lock state, and return tue if running in unlock mode. | ||
58 | * This is needed to compensate for the shifted DLL value in unlock mode. | ||
59 | */ | ||
60 | u32 omap2_dll_force_needed(void) | ||
61 | { | ||
62 | /* dlla and dllb are a set */ | ||
63 | u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); | ||
64 | |||
65 | if ((dll_state & (1 << 2)) == (1 << 2)) | ||
66 | return 1; | ||
67 | else | ||
68 | return 0; | ||
69 | } | ||
70 | |||
71 | /* | ||
72 | * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. | ||
73 | * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or | ||
74 | * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) | ||
75 | */ | ||
76 | u32 omap2_reprogram_sdrc(u32 level, u32 force) | ||
77 | { | ||
78 | u32 dll_ctrl, m_type; | ||
79 | u32 prev = curr_perf_level; | ||
80 | unsigned long flags; | ||
81 | |||
82 | if ((curr_perf_level == level) && !force) | ||
83 | return prev; | ||
84 | |||
85 | if (level == CORE_CLK_SRC_DPLL) { | ||
86 | dll_ctrl = omap2_memory_get_slow_dll_ctrl(); | ||
87 | } else if (level == CORE_CLK_SRC_DPLL_X2) { | ||
88 | dll_ctrl = omap2_memory_get_fast_dll_ctrl(); | ||
89 | } else { | ||
90 | return prev; | ||
91 | } | ||
92 | |||
93 | m_type = omap2_memory_get_type(); | ||
94 | |||
95 | local_irq_save(flags); | ||
96 | __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); | ||
97 | omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); | ||
98 | curr_perf_level = level; | ||
99 | local_irq_restore(flags); | ||
100 | |||
101 | return prev; | ||
102 | } | ||
103 | |||
56 | void omap2_init_memory_params(u32 force_lock_to_unlock_mode) | 104 | void omap2_init_memory_params(u32 force_lock_to_unlock_mode) |
57 | { | 105 | { |
58 | unsigned long dll_cnt; | 106 | unsigned long dll_cnt; |
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h index d212eea83a05..9a280b50a893 100644 --- a/arch/arm/mach-omap2/memory.h +++ b/arch/arm/mach-omap2/memory.h | |||
@@ -32,3 +32,5 @@ extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode); | |||
32 | extern u32 omap2_memory_get_slow_dll_ctrl(void); | 32 | extern u32 omap2_memory_get_slow_dll_ctrl(void); |
33 | extern u32 omap2_memory_get_fast_dll_ctrl(void); | 33 | extern u32 omap2_memory_get_fast_dll_ctrl(void); |
34 | extern u32 omap2_memory_get_type(void); | 34 | extern u32 omap2_memory_get_type(void); |
35 | u32 omap2_dll_force_needed(void); | ||
36 | u32 omap2_reprogram_sdrc(u32 level, u32 force); | ||
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 0a603242f367..32a533ba9ada 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c | |||
@@ -304,6 +304,23 @@ void propagate_rate(struct clk * tclk) | |||
304 | } | 304 | } |
305 | } | 305 | } |
306 | 306 | ||
307 | /** | ||
308 | * recalculate_root_clocks - recalculate and propagate all root clocks | ||
309 | * | ||
310 | * Recalculates all root clocks (clocks with no parent), which if the | ||
311 | * clock's .recalc is set correctly, should also propagate their rates. | ||
312 | * Called at init. | ||
313 | */ | ||
314 | void recalculate_root_clocks(void) | ||
315 | { | ||
316 | struct clk *clkp; | ||
317 | |||
318 | list_for_each_entry(clkp, &clocks, node) { | ||
319 | if (unlikely(!clkp->parent) && likely((u32)clkp->recalc)) | ||
320 | clkp->recalc(clkp); | ||
321 | } | ||
322 | } | ||
323 | |||
307 | int clk_register(struct clk *clk) | 324 | int clk_register(struct clk *clk) |
308 | { | 325 | { |
309 | if (clk == NULL || IS_ERR(clk)) | 326 | if (clk == NULL || IS_ERR(clk)) |
@@ -358,6 +375,30 @@ void clk_allow_idle(struct clk *clk) | |||
358 | } | 375 | } |
359 | EXPORT_SYMBOL(clk_allow_idle); | 376 | EXPORT_SYMBOL(clk_allow_idle); |
360 | 377 | ||
378 | void clk_enable_init_clocks(void) | ||
379 | { | ||
380 | struct clk *clkp; | ||
381 | |||
382 | list_for_each_entry(clkp, &clocks, node) { | ||
383 | if (clkp->flags & ENABLE_ON_INIT) | ||
384 | clk_enable(clkp); | ||
385 | } | ||
386 | } | ||
387 | EXPORT_SYMBOL(clk_enable_init_clocks); | ||
388 | |||
389 | #ifdef CONFIG_CPU_FREQ | ||
390 | void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | ||
391 | { | ||
392 | unsigned long flags; | ||
393 | |||
394 | spin_lock_irqsave(&clockfw_lock, flags); | ||
395 | if (arch_clock->clk_init_cpufreq_table) | ||
396 | arch_clock->clk_init_cpufreq_table(table); | ||
397 | spin_unlock_irqrestore(&clockfw_lock, flags); | ||
398 | } | ||
399 | EXPORT_SYMBOL(clk_init_cpufreq_table); | ||
400 | #endif | ||
401 | |||
361 | /*-------------------------------------------------------------------------*/ | 402 | /*-------------------------------------------------------------------------*/ |
362 | 403 | ||
363 | #ifdef CONFIG_OMAP_RESET_CLOCKS | 404 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
@@ -396,3 +437,4 @@ int __init clk_init(struct clk_functions * custom_clocks) | |||
396 | 437 | ||
397 | return 0; | 438 | return 0; |
398 | } | 439 | } |
440 | |||
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index fc7b80643852..ff0f94de2de9 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h | |||
@@ -14,6 +14,30 @@ | |||
14 | #define __ARCH_ARM_OMAP_CLOCK_H | 14 | #define __ARCH_ARM_OMAP_CLOCK_H |
15 | 15 | ||
16 | struct module; | 16 | struct module; |
17 | struct clk; | ||
18 | |||
19 | #if defined(CONFIG_ARCH_OMAP2) | ||
20 | |||
21 | struct clksel_rate { | ||
22 | u8 div; | ||
23 | u32 val; | ||
24 | u8 flags; | ||
25 | }; | ||
26 | |||
27 | struct clksel { | ||
28 | struct clk *parent; | ||
29 | const struct clksel_rate *rates; | ||
30 | }; | ||
31 | |||
32 | struct dpll_data { | ||
33 | void __iomem *mult_div1_reg; | ||
34 | u32 mult_mask; | ||
35 | u32 div1_mask; | ||
36 | void __iomem *div2_reg; | ||
37 | u32 div2_mask; | ||
38 | }; | ||
39 | |||
40 | #endif | ||
17 | 41 | ||
18 | struct clk { | 42 | struct clk { |
19 | struct list_head node; | 43 | struct list_head node; |
@@ -25,8 +49,6 @@ struct clk { | |||
25 | __u32 flags; | 49 | __u32 flags; |
26 | void __iomem *enable_reg; | 50 | void __iomem *enable_reg; |
27 | __u8 enable_bit; | 51 | __u8 enable_bit; |
28 | __u8 rate_offset; | ||
29 | __u8 src_offset; | ||
30 | __s8 usecount; | 52 | __s8 usecount; |
31 | void (*recalc)(struct clk *); | 53 | void (*recalc)(struct clk *); |
32 | int (*set_rate)(struct clk *, unsigned long); | 54 | int (*set_rate)(struct clk *, unsigned long); |
@@ -34,6 +56,16 @@ struct clk { | |||
34 | void (*init)(struct clk *); | 56 | void (*init)(struct clk *); |
35 | int (*enable)(struct clk *); | 57 | int (*enable)(struct clk *); |
36 | void (*disable)(struct clk *); | 58 | void (*disable)(struct clk *); |
59 | #if defined(CONFIG_ARCH_OMAP2) | ||
60 | u8 fixed_div; | ||
61 | void __iomem *clksel_reg; | ||
62 | u32 clksel_mask; | ||
63 | const struct clksel *clksel; | ||
64 | const struct dpll_data *dpll_data; | ||
65 | #else | ||
66 | __u8 rate_offset; | ||
67 | __u8 src_offset; | ||
68 | #endif | ||
37 | }; | 69 | }; |
38 | 70 | ||
39 | struct clk_functions { | 71 | struct clk_functions { |
@@ -54,10 +86,12 @@ extern int clk_init(struct clk_functions * custom_clocks); | |||
54 | extern int clk_register(struct clk *clk); | 86 | extern int clk_register(struct clk *clk); |
55 | extern void clk_unregister(struct clk *clk); | 87 | extern void clk_unregister(struct clk *clk); |
56 | extern void propagate_rate(struct clk *clk); | 88 | extern void propagate_rate(struct clk *clk); |
89 | extern void recalculate_root_clocks(void); | ||
57 | extern void followparent_recalc(struct clk * clk); | 90 | extern void followparent_recalc(struct clk * clk); |
58 | extern void clk_allow_idle(struct clk *clk); | 91 | extern void clk_allow_idle(struct clk *clk); |
59 | extern void clk_deny_idle(struct clk *clk); | 92 | extern void clk_deny_idle(struct clk *clk); |
60 | extern int clk_get_usecount(struct clk *clk); | 93 | extern int clk_get_usecount(struct clk *clk); |
94 | extern void clk_enable_init_clocks(void); | ||
61 | 95 | ||
62 | /* Clock flags */ | 96 | /* Clock flags */ |
63 | #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ | 97 | #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ |
@@ -71,22 +105,29 @@ extern int clk_get_usecount(struct clk *clk); | |||
71 | #define CLOCK_NO_IDLE_PARENT (1 << 8) | 105 | #define CLOCK_NO_IDLE_PARENT (1 << 8) |
72 | #define DELAYED_APP (1 << 9) /* Delay application of clock */ | 106 | #define DELAYED_APP (1 << 9) /* Delay application of clock */ |
73 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ | 107 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ |
74 | #define CM_MPU_SEL1 (1 << 11) /* Domain divider/source */ | 108 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ |
75 | #define CM_DSP_SEL1 (1 << 12) | 109 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ |
76 | #define CM_GFX_SEL1 (1 << 13) | 110 | /* bits 13-20 are currently free */ |
77 | #define CM_MODEM_SEL1 (1 << 14) | ||
78 | #define CM_CORE_SEL1 (1 << 15) /* Sets divider for many */ | ||
79 | #define CM_CORE_SEL2 (1 << 16) /* sets parent for GPT */ | ||
80 | #define CM_WKUP_SEL1 (1 << 17) | ||
81 | #define CM_PLL_SEL1 (1 << 18) | ||
82 | #define CM_PLL_SEL2 (1 << 19) | ||
83 | #define CM_SYSCLKOUT_SEL1 (1 << 20) | ||
84 | #define CLOCK_IN_OMAP310 (1 << 21) | 111 | #define CLOCK_IN_OMAP310 (1 << 21) |
85 | #define CLOCK_IN_OMAP730 (1 << 22) | 112 | #define CLOCK_IN_OMAP730 (1 << 22) |
86 | #define CLOCK_IN_OMAP1510 (1 << 23) | 113 | #define CLOCK_IN_OMAP1510 (1 << 23) |
87 | #define CLOCK_IN_OMAP16XX (1 << 24) | 114 | #define CLOCK_IN_OMAP16XX (1 << 24) |
88 | #define CLOCK_IN_OMAP242X (1 << 25) | 115 | #define CLOCK_IN_OMAP242X (1 << 25) |
89 | #define CLOCK_IN_OMAP243X (1 << 26) | 116 | #define CLOCK_IN_OMAP243X (1 << 26) |
117 | #define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */ | ||
118 | #define PARENT_CONTROLS_CLOCK (1 << 28) | ||
119 | #define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */ | ||
120 | #define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */ | ||
121 | |||
122 | /* Clksel_rate flags */ | ||
123 | #define DEFAULT_RATE (1 << 0) | ||
124 | #define RATE_IN_242X (1 << 1) | ||
125 | #define RATE_IN_243X (1 << 2) | ||
126 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ | ||
127 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ | ||
128 | |||
129 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | ||
130 | |||
90 | 131 | ||
91 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ | 132 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ |
92 | #define CORE_CLK_SRC_32K 0 | 133 | #define CORE_CLK_SRC_32K 0 |