128 files changed, 12023 insertions, 905 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index e182992ff799..deae37416eec 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -348,6 +348,13 @@ P:	Ian Molton
 M:      spyro@f2s.com
 S:      Maintained
 
+ARM/ATMEL AT91RM9200 ARM ARCHITECTURE
+P:      Andrew Victor
+M:      andrew@sanpeople.com
+L:      linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
+W:      http://maxim.org.za/at91_26.html
+S:      Maintained
+
 ARM/CORGI MACHINE SUPPORT
 P:      Richard Purdie
 M:      rpurdie@rpsys.net
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7be67ef4b84f..8c05d4321ae9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -223,6 +223,12 @@ config ARCH_IOP33X
         help
           Support for Intel's IOP33X (XScale) family of processors.
 
+config ARCH_IOP13XX
+        bool "IOP13xx-based"
+        select PCI
+        help
+          Support for Intel's IOP13XX (XScale) family of processors.
+
 config ARCH_IXP4XX
         bool "IXP4xx-based"
         depends on MMU
@@ -331,6 +337,8 @@ source "arch/arm/mach-iop32x/Kconfig"
 
 source "arch/arm/mach-iop33x/Kconfig"
 
+source "arch/arm/mach-iop13xx/Kconfig"
+
 source "arch/arm/mach-ixp4xx/Kconfig"
 
 source "arch/arm/mach-ixp2000/Kconfig"
@@ -591,7 +599,7 @@ config LEDS
                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
                    ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
-                   ARCH_AT91RM9200 || MACH_TRIZEPS4
+                   ARCH_AT91 || MACH_TRIZEPS4
         help
           If you say Y here, the LEDs on your machine will be used
           to provide useful information about your current system status.
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index b6001f97c80c..000f1100b553 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -110,6 +110,7 @@ endif
  machine-$(CONFIG_ARCH_CLPS711X)   := clps711x
  machine-$(CONFIG_ARCH_IOP32X)     := iop32x
  machine-$(CONFIG_ARCH_IOP33X)     := iop33x
+ machine-$(CONFIG_ARCH_IOP13XX)    := iop13xx
  machine-$(CONFIG_ARCH_IXP4XX)     := ixp4xx
  machine-$(CONFIG_ARCH_IXP2000)    := ixp2000
  machine-$(CONFIG_ARCH_IXP23XX)    := ixp23xx
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
index 02164c1a301c..e10d003566d6 100644
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ b/arch/arm/configs/at91rm9200dk_defconfig
@@ -357,9 +357,9 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x10000000
-CONFIG_MTD_PHYSMAP_LEN=0x200000
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+CONFIG_MTD_PHYSMAP_START=0
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_IMPA7 is not set
 # CONFIG_MTD_PLATRAM is not set
@@ -585,7 +585,9 @@ CONFIG_AT91RM9200_WATCHDOG=y
 # CONFIG_USBPCWATCHDOG is not set
 # CONFIG_NVRAM is not set
 # CONFIG_RTC is not set
-CONFIG_AT91_RTC=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index bee410cc4e92..834dddb51314 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -348,9 +348,9 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x10000000
-CONFIG_MTD_PHYSMAP_LEN=0x800000
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+CONFIG_MTD_PHYSMAP_START=0
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_IMPA7 is not set
 # CONFIG_MTD_PLATRAM is not set
@@ -566,7 +566,9 @@ CONFIG_AT91RM9200_WATCHDOG=y
 # CONFIG_USBPCWATCHDOG is not set
 # CONFIG_NVRAM is not set
 # CONFIG_RTC is not set
-CONFIG_AT91_RTC=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig
new file mode 100644
index 000000000000..79049206dfa5
--- /dev/null
+++ b/arch/arm/configs/at91sam9260ek_defconfig
@@ -0,0 +1,950 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.19-rc6
+# Fri Nov 17 18:42:21 2006
+#
+CONFIG_ARM=y
+# CONFIG_GENERIC_TIME is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_RELAY is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+
+#
+# AT91SAM9260 Board Type
+#
+CONFIG_MACH_AT91SAM9260EK=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+
+#
+# Bus support
+#
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+# CONFIG_APM is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Network device support
+#
+# CONFIG_NETDEVICES is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+# CONFIG_TIFM_CORE is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DEBUG=y
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_TOUCHSCREEN is not set
+# CONFIG_USB_YEALINK is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+# CONFIG_USB_ATI_REMOTE2 is not set
+# CONFIG_USB_KEYSPAN_REMOTE is not set
+# CONFIG_USB_APPLETOUCH is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ETH is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig
new file mode 100644
index 000000000000..784ad7c0186d
--- /dev/null
+++ b/arch/arm/configs/at91sam9261ek_defconfig
@@ -0,0 +1,1106 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.19-rc6
+# Fri Nov 17 18:00:38 2006
+#
+CONFIG_ARM=y
+# CONFIG_GENERIC_TIME is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_RELAY is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+CONFIG_ARCH_AT91SAM9261=y
+
+#
+# AT91SAM9261 Board Type
+#
+CONFIG_MACH_AT91SAM9261EK=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+
+#
+# Bus support
+#
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+# CONFIG_APM is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+# CONFIG_MTD_NAND_NANDSIM is not set
+
+#
+# OneNAND Flash Device Drivers
+#
+# CONFIG_MTD_ONENAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# PHY device support
+#
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_SMC91X is not set
+CONFIG_DM9000=y
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_AT91=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+# CONFIG_TIFM_CORE is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DEBUG=y
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_TOUCHSCREEN is not set
+# CONFIG_USB_YEALINK is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+# CONFIG_USB_ATI_REMOTE2 is not set
+# CONFIG_USB_KEYSPAN_REMOTE is not set
+# CONFIG_USB_APPLETOUCH is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ETH is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_AT91=m
+# CONFIG_MMC_TIFM_SD is not set
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
diff --git a/arch/arm/configs/carmeva_defconfig b/arch/arm/configs/carmeva_defconfig
index d24ae8777c35..d392833b31fb 100644
--- a/arch/arm/configs/carmeva_defconfig
+++ b/arch/arm/configs/carmeva_defconfig
@@ -474,7 +474,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_WATCHDOG is not set
 # CONFIG_NVRAM is not set
 # CONFIG_RTC is not set
-# CONFIG_AT91_RTC is not set
+# CONFIG_AT91RM9200_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
diff --git a/arch/arm/configs/csb637_defconfig b/arch/arm/configs/csb637_defconfig
index 807f7fc8d777..94908c1df4cf 100644
--- a/arch/arm/configs/csb637_defconfig
+++ b/arch/arm/configs/csb637_defconfig
@@ -623,7 +623,7 @@ CONFIG_AT91RM9200_WATCHDOG=y
 # CONFIG_USBPCWATCHDOG is not set
 # CONFIG_NVRAM is not set
 CONFIG_RTC=y
-# CONFIG_AT91_RTC is not set
+# CONFIG_AT91RM9200_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 58d5974f41d0..f8a66b72ad5d 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -125,6 +125,7 @@ CONFIG_CRUNCH=y
 #
 # EP93xx Platforms
 #
+CONFIG_MACH_ADSSPHERE=y
 CONFIG_MACH_EDB9302=y
 CONFIG_MACH_EDB9312=y
 CONFIG_MACH_EDB9315=y
diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig
new file mode 100644
index 000000000000..f6e46193fd26
--- /dev/null
+++ b/arch/arm/configs/iop13xx_defconfig
@@ -0,0 +1,1134 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.19
+# Fri Dec  1 10:51:01 2006
+#
+CONFIG_ARM=y
+# CONFIG_GENERIC_TIME is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_RELAY is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+CONFIG_ARCH_IOP13XX=y
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# IOP13XX Implementation Options
+#
+
+#
+# IOP13XX Platform Support
+#
+CONFIG_MACH_IQ81340SC=y
+CONFIG_MACH_IQ81340MC=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSC3=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_IO_36=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+
+#
+# Bus support
+#
+CONFIG_PCI=y
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="ip=bootp root=nfs console=ttyS0,115200 nfsroot=,tcp,v3,wsize=8192,rsize=8192"
+# CONFIG_XIP_KERNEL is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+# CONFIG_APM is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0xfa000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# OneNAND Flash Device Drivers
+#
+# CONFIG_MTD_ONENAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+# CONFIG_SCSI_SAS_LIBSAS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Serial ATA (prod) and Parallel ATA (experimental) drivers
+#
+# CONFIG_ATA is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+# CONFIG_MD_LINEAR is not set
+CONFIG_MD_RAID0=y
+CONFIG_MD_RAID1=y
+CONFIG_MD_RAID10=y
+CONFIG_MD_RAID456=y
+# CONFIG_MD_RAID5_RESHAPE is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_DEBUG is not set
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
+# CONFIG_FUSION_SAS is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+
+#
+# Ethernet (10 or 100Mbit)
+#
+# CONFIG_NET_ETHERNET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+CONFIG_E1000_NAPI=y
+# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_ALGOPCF=m
+CONFIG_I2C_ALGOPCA=m
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_IOP3XX=y
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Misc devices
+#
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_NFSD_TCP=y
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_FS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_USER=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
diff --git a/arch/arm/configs/kb9202_defconfig b/arch/arm/configs/kb9202_defconfig
index 89e116f955b1..c16537d9d67a 100644
--- a/arch/arm/configs/kb9202_defconfig
+++ b/arch/arm/configs/kb9202_defconfig
@@ -437,7 +437,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_WATCHDOG is not set
 # CONFIG_NVRAM is not set
 # CONFIG_RTC is not set
-# CONFIG_AT91_RTC is not set
+# CONFIG_AT91RM9200_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 6f12d2686aaf..238dd9b6db84 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -438,16 +438,19 @@ __early_param("initrd=", early_initrd);
 
 static void __init arm_add_memory(unsigned long start, unsigned long size)
 {
+        struct membank *bank;
+
         /*
          * Ensure that start/size are aligned to a page boundary.
          * Size is appropriately rounded down, start is rounded up.
          */
         size -= start & ~PAGE_MASK;
 
-        meminfo.bank[meminfo.nr_banks].start = PAGE_ALIGN(start);
-        meminfo.bank[meminfo.nr_banks].size  = size & PAGE_MASK;
-        meminfo.bank[meminfo.nr_banks].node  = PHYS_TO_NID(start);
-        meminfo.nr_banks += 1;
+        bank = &meminfo.bank[meminfo.nr_banks++];
+
+        bank->start = PAGE_ALIGN(start);
+        bank->size  = size & PAGE_MASK;
+        bank->node  = PHYS_TO_NID(start);
 }
 
 /*
diff --git a/arch/arm/mach-at91rm9200/Kconfig b/arch/arm/mach-at91rm9200/Kconfig
index 2f85e8693b1b..9f11db8af233 100644
--- a/arch/arm/mach-at91rm9200/Kconfig
+++ b/arch/arm/mach-at91rm9200/Kconfig
@@ -2,7 +2,8 @@ if ARCH_AT91
 
 menu "Atmel AT91 System-on-Chip"
 
-comment "Atmel AT91 Processors"
+choice
+        prompt "Atmel AT91 Processor"
 
 config ARCH_AT91RM9200
         bool "AT91RM9200"
@@ -13,6 +14,8 @@ config ARCH_AT91SAM9260
 config ARCH_AT91SAM9261
         bool "AT91SAM9261"
 
+endchoice
+
 # ----------------------------------------------------------
 
 if ARCH_AT91RM9200
@@ -33,7 +36,6 @@ config ARCH_AT91RM9200DK
           Select this if you are using Atmel's AT91RM9200-DK Development board.
           (Discontinued)
 
-
 config MACH_AT91RM9200EK
         bool "Atmel AT91RM9200-EK Evaluation Kit"
         depends on ARCH_AT91RM9200
@@ -90,6 +92,13 @@ if ARCH_AT91SAM9260
 
 comment "AT91SAM9260 Board Type"
 
+config MACH_AT91SAM9260EK
+        bool "Atmel AT91SAM9260-EK Evaluation Kit"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using Atmel's AT91SAM9260-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
+
 endif
 
 # ----------------------------------------------------------
@@ -98,8 +107,31 @@ if ARCH_AT91SAM9261
 
 comment "AT91SAM9261 Board Type"
 
+config MACH_AT91SAM9261EK
+        bool "Atmel AT91SAM9261-EK Evaluation Kit"
+        depends on ARCH_AT91SAM9261
+        help
+          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
+
 endif
 
+# ----------------------------------------------------------
+
+comment "AT91 Board Options"
+
+config MTD_AT91_DATAFLASH_CARD
+        bool "Enable DataFlash Card support"
+        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK)
+        help
+          Enable support for the DataFlash card.
+
+config MTD_NAND_AT91_BUSWIDTH_16
+        bool "Enable 16-bit data bus interface to NAND flash"
+        depends on (MACH_AT91SAM9261EK || MACH_AT91SAM9260EK)
+        help
+          On AT91SAM926x boards both types of NAND flash can be present
+          (8 and 16 bit data bus width).
 
 # ----------------------------------------------------------
 
diff --git a/arch/arm/mach-at91rm9200/Makefile b/arch/arm/mach-at91rm9200/Makefile
index c174805c24e5..cf777007847a 100644
--- a/arch/arm/mach-at91rm9200/Makefile
+++ b/arch/arm/mach-at91rm9200/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
 
-obj-y           := clock.o irq.o gpio.o devices.o
+obj-y           := clock.o irq.o gpio.o
 obj-m           :=
 obj-n           :=
 obj-            :=
@@ -10,11 +10,11 @@ obj-		:=
 obj-$(CONFIG_PM)                += pm.o
 
 # CPU-specific support
-obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200.o at91rm9200_time.o
-obj-$(CONFIG_ARCH_AT91SAM9260)  +=
-obj-$(CONFIG_ARCH_AT91SAM9261)  +=
+obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9261)  += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
 
-# AT91RM9200 Board-specific support
+# AT91RM9200 board-specific support
 obj-$(CONFIG_MACH_ONEARM)       += board-1arm.o
 obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o
 obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o
@@ -26,8 +26,10 @@ obj-$(CONFIG_MACH_ATEB9200)	+= board-eb9200.o
 obj-$(CONFIG_MACH_KAFA)         += board-kafa.o
 
 # AT91SAM9260 board-specific support
+obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
 
 # AT91SAM9261 board-specific support
+obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
 
 # LEDs support
 led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o
diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c
index dcf6136fedf9..a92e9a495b07 100644
--- a/arch/arm/mach-at91rm9200/at91rm9200.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200.c
@@ -14,8 +14,10 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/arch/at91rm9200.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_st.h>
 
-#include <asm/hardware.h>
 #include "generic.h"
 #include "clock.h"
 
@@ -26,32 +28,12 @@ static struct map_desc at91rm9200_io_desc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = AT91_VA_BASE_SPI,
-                .pfn            = __phys_to_pfn(AT91RM9200_BASE_SPI),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = AT91_VA_BASE_EMAC,
                 .pfn            = __phys_to_pfn(AT91RM9200_BASE_EMAC),
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = AT91_VA_BASE_TWI,
-                .pfn            = __phys_to_pfn(AT91RM9200_BASE_TWI),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = AT91_VA_BASE_MCI,
-                .pfn            = __phys_to_pfn(AT91RM9200_BASE_MCI),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = AT91_VA_BASE_UDP,
-                .pfn            = __phys_to_pfn(AT91RM9200_BASE_UDP),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = AT91_SRAM_VIRT_BASE,
+                .virtual        = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE,
                 .pfn            = __phys_to_pfn(AT91RM9200_SRAM_BASE),
                 .length         = AT91RM9200_SRAM_SIZE,
                 .type           = MT_DEVICE,
@@ -222,6 +204,16 @@ static struct at91_gpio_bank at91rm9200_gpio[] = {
         }
 };
 
+static void at91rm9200_reset(void)
+{
+        /*
+         * Perform a hardware reset with the use of the Watchdog timer.
+         */
+        at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
+        at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
+}
+
+
 /* --------------------------------------------------------------------
  *  AT91RM9200 processor initialization
  * -------------------------------------------------------------------- */
@@ -230,6 +222,12 @@ void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks
         /* Map peripherals */
         iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
 
+        at91_arch_reset = at91rm9200_reset;
+        at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
+                        | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
+                        | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
+                        | (1 << AT91RM9200_ID_IRQ6);
+
         /* Init clock subsystem */
         at91_clock_init(main_clock);
 
diff --git a/arch/arm/mach-at91rm9200/devices.c b/arch/arm/mach-at91rm9200/at91rm9200_devices.c
index 059824376629..4641b99db0ee 100644
--- a/arch/arm/mach-at91rm9200/devices.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200_devices.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-at91rm9200/devices.c
+ * arch/arm/mach-at91rm9200/at91rm9200_devices.c
  *
  *  Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
  *  Copyright (C) 2005 David Brownell
@@ -15,9 +15,10 @@
 
 #include <linux/platform_device.h>
 
-#include <asm/hardware.h>
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/at91rm9200.h>
+#include <asm/arch/at91rm9200_mc.h>
 
 #include "generic.h"
 
@@ -33,7 +34,7 @@
 static u64 ohci_dmamask = 0xffffffffUL;
 static struct at91_usbh_data usbh_data;
 
-static struct resource at91_usbh_resources[] = {
+static struct resource usbh_resources[] = {
         [0] = {
                 .start  = AT91RM9200_UHP_BASE,
                 .end    = AT91RM9200_UHP_BASE + SZ_1M - 1,
@@ -54,8 +55,8 @@ static struct platform_device at91rm9200_usbh_device = {
                                 .coherent_dma_mask      = 0xffffffff,
                                 .platform_data          = &usbh_data,
         },
-        .resource       = at91_usbh_resources,
-        .num_resources  = ARRAY_SIZE(at91_usbh_resources),
+        .resource       = usbh_resources,
+        .num_resources  = ARRAY_SIZE(usbh_resources),
 };
 
 void __init at91_add_device_usbh(struct at91_usbh_data *data)
@@ -78,7 +79,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
 #ifdef CONFIG_USB_GADGET_AT91
 static struct at91_udc_data udc_data;
 
-static struct resource at91_udc_resources[] = {
+static struct resource udc_resources[] = {
         [0] = {
                 .start  = AT91RM9200_BASE_UDP,
                 .end    = AT91RM9200_BASE_UDP + SZ_16K - 1,
@@ -97,8 +98,8 @@ static struct platform_device at91rm9200_udc_device = {
         .dev            = {
                                 .platform_data          = &udc_data,
         },
-        .resource       = at91_udc_resources,
-        .num_resources  = ARRAY_SIZE(at91_udc_resources),
+        .resource       = udc_resources,
+        .num_resources  = ARRAY_SIZE(udc_resources),
 };
 
 void __init at91_add_device_udc(struct at91_udc_data *data)
@@ -129,7 +130,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {}
 static u64 eth_dmamask = 0xffffffffUL;
 static struct at91_eth_data eth_data;
 
-static struct resource at91_eth_resources[] = {
+static struct resource eth_resources[] = {
         [0] = {
                 .start  = AT91_VA_BASE_EMAC,
                 .end    = AT91_VA_BASE_EMAC + SZ_16K - 1,
@@ -150,8 +151,8 @@ static struct platform_device at91rm9200_eth_device = {
                                 .coherent_dma_mask      = 0xffffffff,
                                 .platform_data          = &eth_data,
         },
-        .resource       = at91_eth_resources,
-        .num_resources  = ARRAY_SIZE(at91_eth_resources),
+        .resource       = eth_resources,
+        .num_resources  = ARRAY_SIZE(eth_resources),
 };
 
 void __init at91_add_device_eth(struct at91_eth_data *data)
@@ -202,11 +203,13 @@ void __init at91_add_device_eth(struct at91_eth_data *data) {}
 #if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
 static struct at91_cf_data cf_data;
 
-static struct resource at91_cf_resources[] = {
+#define CF_BASE         AT91_CHIPSELECT_4
+
+static struct resource cf_resources[] = {
         [0] = {
-                .start  = AT91_CF_BASE,
+                .start  = CF_BASE,
                 /* ties up CS4, CS5 and CS6 */
-                .end    = AT91_CF_BASE + (0x30000000 - 1),
+                .end    = CF_BASE + (0x30000000 - 1),
                 .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
         },
 };
@@ -217,15 +220,38 @@ static struct platform_device at91rm9200_cf_device = {
         .dev            = {
                                 .platform_data          = &cf_data,
         },
-        .resource       = at91_cf_resources,
-        .num_resources  = ARRAY_SIZE(at91_cf_resources),
+        .resource       = cf_resources,
+        .num_resources  = ARRAY_SIZE(cf_resources),
 };
 
 void __init at91_add_device_cf(struct at91_cf_data *data)
 {
+        unsigned int csa;
+
         if (!data)
                 return;
 
+        data->chipselect = 4;           /* can only use EBI ChipSelect 4 */
+
+        /* CF takes over CS4, CS5, CS6 */
+        csa = at91_sys_read(AT91_EBI_CSA);
+        at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
+
+        /*
+         * Static memory controller timing adjustments.
+         * REVISIT:  these timings are in terms of MCK cycles, so
+         * when MCK changes (cpufreq etc) so must these values...
+         */
+        at91_sys_write(AT91_SMC_CSR(4),
+                                  AT91_SMC_ACSS_STD
+                                | AT91_SMC_DBW_16
+                                | AT91_SMC_BAT
+                                | AT91_SMC_WSEN
+                                | AT91_SMC_NWS_(32)     /* wait states */
+                                | AT91_SMC_RWSETUP_(6)  /* setup time */
+                                | AT91_SMC_RWHOLD_(4)   /* hold time */
+        );
+
         /* input/irq */
         if (data->irq_pin) {
                 at91_set_gpio_input(data->irq_pin, 1);
@@ -245,6 +271,9 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
         at91_set_A_periph(AT91_PIN_PC11, 0);    /* NCS5/CFCE1 */
         at91_set_A_periph(AT91_PIN_PC12, 0);    /* NCS6/CFCE2 */
 
+        /* nWAIT is _not_ a default setting */
+        at91_set_A_periph(AT91_PIN_PC6, 1);     /*  nWAIT */
+
         cf_data = *data;
         platform_device_register(&at91rm9200_cf_device);
 }
@@ -257,11 +286,11 @@ void __init at91_add_device_cf(struct at91_cf_data *data) {}
  *  MMC / SD
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MMC_AT91RM9200) || defined(CONFIG_MMC_AT91RM9200_MODULE)
+#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
 static u64 mmc_dmamask = 0xffffffffUL;
 static struct at91_mmc_data mmc_data;
 
-static struct resource at91_mmc_resources[] = {
+static struct resource mmc_resources[] = {
         [0] = {
                 .start  = AT91RM9200_BASE_MCI,
                 .end    = AT91RM9200_BASE_MCI + SZ_16K - 1,
@@ -282,8 +311,8 @@ static struct platform_device at91rm9200_mmc_device = {
                                 .coherent_dma_mask      = 0xffffffff,
                                 .platform_data          = &mmc_data,
         },
-        .resource       = at91_mmc_resources,
-        .num_resources  = ARRAY_SIZE(at91_mmc_resources),
+        .resource       = mmc_resources,
+        .num_resources  = ARRAY_SIZE(mmc_resources),
 };
 
 void __init at91_add_device_mmc(struct at91_mmc_data *data)
@@ -298,31 +327,33 @@ void __init at91_add_device_mmc(struct at91_mmc_data *data)
         }
         if (data->wp_pin)
                 at91_set_gpio_input(data->wp_pin, 1);
+        if (data->vcc_pin)
+                at91_set_gpio_output(data->vcc_pin, 0);
 
         /* CLK */
         at91_set_A_periph(AT91_PIN_PA27, 0);
 
-        if (data->is_b) {
+        if (data->slot_b) {
                 /* CMD */
-                at91_set_B_periph(AT91_PIN_PA8, 0);
+                at91_set_B_periph(AT91_PIN_PA8, 1);
 
                 /* DAT0, maybe DAT1..DAT3 */
-                at91_set_B_periph(AT91_PIN_PA9, 0);
+                at91_set_B_periph(AT91_PIN_PA9, 1);
                 if (data->wire4) {
-                        at91_set_B_periph(AT91_PIN_PA10, 0);
-                        at91_set_B_periph(AT91_PIN_PA11, 0);
-                        at91_set_B_periph(AT91_PIN_PA12, 0);
+                        at91_set_B_periph(AT91_PIN_PA10, 1);
+                        at91_set_B_periph(AT91_PIN_PA11, 1);
+                        at91_set_B_periph(AT91_PIN_PA12, 1);
                 }
         } else {
                 /* CMD */
-                at91_set_A_periph(AT91_PIN_PA28, 0);
+                at91_set_A_periph(AT91_PIN_PA28, 1);
 
                 /* DAT0, maybe DAT1..DAT3 */
-                at91_set_A_periph(AT91_PIN_PA29, 0);
+                at91_set_A_periph(AT91_PIN_PA29, 1);
                 if (data->wire4) {
-                        at91_set_B_periph(AT91_PIN_PB3, 0);
-                        at91_set_B_periph(AT91_PIN_PB4, 0);
-                        at91_set_B_periph(AT91_PIN_PB5, 0);
+                        at91_set_B_periph(AT91_PIN_PB3, 1);
+                        at91_set_B_periph(AT91_PIN_PB4, 1);
+                        at91_set_B_periph(AT91_PIN_PB5, 1);
                 }
         }
 
@@ -341,29 +372,45 @@ void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
 static struct at91_nand_data nand_data;
 
-static struct resource at91_nand_resources[] = {
+#define NAND_BASE       AT91_CHIPSELECT_3
+
+static struct resource nand_resources[] = {
         {
-                .start  = AT91_SMARTMEDIA_BASE,
-                .end    = AT91_SMARTMEDIA_BASE + SZ_8M - 1,
+                .start  = NAND_BASE,
+                .end    = NAND_BASE + SZ_8M - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
 
-static struct platform_device at91_nand_device = {
+static struct platform_device at91rm9200_nand_device = {
         .name           = "at91_nand",
         .id             = -1,
         .dev            = {
                                 .platform_data  = &nand_data,
         },
-        .resource       = at91_nand_resources,
-        .num_resources  = ARRAY_SIZE(at91_nand_resources),
+        .resource       = nand_resources,
+        .num_resources  = ARRAY_SIZE(nand_resources),
 };
 
 void __init at91_add_device_nand(struct at91_nand_data *data)
 {
+        unsigned int csa;
+
         if (!data)
                 return;
 
+        /* enable the address range of CS3 */
+        csa = at91_sys_read(AT91_EBI_CSA);
+        at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
+
+        /* set the bus interface characteristics */
+        at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
+                | AT91_SMC_NWS_(5)
+                | AT91_SMC_TDF_(1)
+                | AT91_SMC_RWSETUP_(0)  /* tDS Data Set up Time 30 - ns */
+                | AT91_SMC_RWHOLD_(1)   /* tDH Data Hold Time 20 - ns */
+        );
+
         /* enable pin */
         if (data->enable_pin)
                 at91_set_gpio_output(data->enable_pin, 1);
@@ -380,7 +427,7 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
         at91_set_A_periph(AT91_PIN_PC3, 0);             /* SMWE */
 
         nand_data = *data;
-        platform_device_register(&at91_nand_device);
+        platform_device_register(&at91rm9200_nand_device);
 }
 #else
 void __init at91_add_device_nand(struct at91_nand_data *data) {}
@@ -392,10 +439,25 @@ void __init at91_add_device_nand(struct at91_nand_data *data) {}
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
+
+static struct resource twi_resources[] = {
+        [0] = {
+                .start  = AT91RM9200_BASE_TWI,
+                .end    = AT91RM9200_BASE_TWI + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91RM9200_ID_TWI,
+                .end    = AT91RM9200_ID_TWI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
 static struct platform_device at91rm9200_twi_device = {
         .name           = "at91_i2c",
         .id             = -1,
-        .num_resources  = 0,
+        .resource       = twi_resources,
+        .num_resources  = ARRAY_SIZE(twi_resources),
 };
 
 void __init at91_add_device_i2c(void)
@@ -421,7 +483,7 @@ void __init at91_add_device_i2c(void) {}
 #if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
 static u64 spi_dmamask = 0xffffffffUL;
 
-static struct resource at91_spi_resources[] = {
+static struct resource spi_resources[] = {
         [0] = {
                 .start  = AT91RM9200_BASE_SPI,
                 .end    = AT91RM9200_BASE_SPI + SZ_16K - 1,
@@ -438,14 +500,14 @@ static struct platform_device at91rm9200_spi_device = {
         .name           = "at91_spi",
         .id             = 0,
         .dev            = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
         },
-        .resource       = at91_spi_resources,
-        .num_resources  = ARRAY_SIZE(at91_spi_resources),
+        .resource       = spi_resources,
+        .num_resources  = ARRAY_SIZE(spi_resources),
 };
 
-static const unsigned at91_spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
+static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
 
 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 {
@@ -461,7 +523,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 if (devices[i].controller_data)
                         cs_pin = (unsigned long) devices[i].controller_data;
                 else
-                        cs_pin = at91_spi_standard_cs[devices[i].chip_select];
+                        cs_pin = spi_standard_cs[devices[i].chip_select];
 
 #ifdef CONFIG_SPI_AT91_MANUAL_CS
                 at91_set_gpio_output(cs_pin, 1);
@@ -474,7 +536,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
         }
 
         spi_register_board_info(devices, nr_devices);
-        at91_clock_associate("spi0_clk", &at91rm9200_spi_device.dev, "spi");
+        at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi");
         platform_device_register(&at91rm9200_spi_device);
 }
 #else
@@ -486,7 +548,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
  *  RTC
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_RTC_DRV_AT91) || defined(CONFIG_RTC_DRV_AT91_MODULE)
+#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
 static struct platform_device at91rm9200_rtc_device = {
         .name           = "at91_rtc",
         .id             = -1,
@@ -506,7 +568,7 @@ static void __init at91_add_device_rtc(void) {}
  *  Watchdog
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_AT91_WATCHDOG) || defined(CONFIG_AT91_WATCHDOG_MODULE)
+#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
 static struct platform_device at91rm9200_wdt_device = {
         .name           = "at91_wdt",
         .id             = -1,
diff --git a/arch/arm/mach-at91rm9200/at91rm9200_time.c b/arch/arm/mach-at91rm9200/at91rm9200_time.c
index 07c9cea8961d..b999e192a7e9 100644
--- a/arch/arm/mach-at91rm9200/at91rm9200_time.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200_time.c
@@ -30,6 +30,8 @@
 #include <asm/io.h>
 #include <asm/mach/time.h>
 
+#include <asm/arch/at91_st.h>
+
 static unsigned long last_crtr;
 
 /*
@@ -99,6 +101,9 @@ void at91rm9200_timer_reset(void)
         /* Set Period Interval timer */
         at91_sys_write(AT91_ST_PIMR, LATCH);
 
+        /* Clear any pending interrupts */
+        (void) at91_sys_read(AT91_ST_SR);
+
         /* Enable Period Interval Timer interrupt */
         at91_sys_write(AT91_ST_IER, AT91_ST_PITS);
 }
diff --git a/arch/arm/mach-at91rm9200/at91sam9260.c b/arch/arm/mach-at91rm9200/at91sam9260.c
new file mode 100644
index 000000000000..203f073a53e6
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam9260.c
@@ -0,0 +1,294 @@
+/*
+ * arch/arm/mach-at91rm9200/at91sam9260.c
+ *
+ *  Copyright (C) 2006 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91_pmc.h>
+
+#include "generic.h"
+#include "clock.h"
+
+static struct map_desc at91sam9260_io_desc[] __initdata = {
+        {
+                .virtual        = AT91_VA_BASE_SYS,
+                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
+                .pfn            = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
+                .length         = AT91SAM9260_SRAM0_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
+                .pfn            = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
+                .length         = AT91SAM9260_SRAM1_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioA_clk = {
+        .name           = "pioA_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+        .name           = "pioB_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+        .name           = "pioC_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk adc_clk = {
+        .name           = "adc_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_US0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_US1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_US2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc_clk = {
+        .name           = "mci_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udc_clk = {
+        .name           = "udc_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi_clk = {
+        .name           = "twi_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ohci_clk = {
+        .name           = "ohci_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ether_clk = {
+        .name           = "ether_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk isi_clk = {
+        .name           = "isi_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart3_clk = {
+        .name           = "usart3_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_US3,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart4_clk = {
+        .name           = "usart4_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_US4,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart5_clk = {
+        .name           = "usart5_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_US5,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+        &pioA_clk,
+        &pioB_clk,
+        &pioC_clk,
+        &adc_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &mmc_clk,
+        &udc_clk,
+        &twi_clk,
+        &spi0_clk,
+        &spi1_clk,
+        // ssc
+        // tc0 .. tc2
+        &ohci_clk,
+        &ether_clk,
+        &isi_clk,
+        &usart3_clk,
+        &usart4_clk,
+        &usart5_clk,
+        // tc3 .. tc5
+        // irq0 .. irq2
+};
+
+/*
+ * The two programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+
+static void __init at91sam9260_register_clocks(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+
+        clk_register(&pck0);
+        clk_register(&pck1);
+}
+
+/* --------------------------------------------------------------------
+ *  GPIO
+ * -------------------------------------------------------------------- */
+
+static struct at91_gpio_bank at91sam9260_gpio[] = {
+        {
+                .id             = AT91SAM9260_ID_PIOA,
+                .offset         = AT91_PIOA,
+                .clock          = &pioA_clk,
+        }, {
+                .id             = AT91SAM9260_ID_PIOB,
+                .offset         = AT91_PIOB,
+                .clock          = &pioB_clk,
+        }, {
+                .id             = AT91SAM9260_ID_PIOC,
+                .offset         = AT91_PIOC,
+                .clock          = &pioC_clk,
+        }
+};
+
+static void at91sam9260_reset(void)
+{
+#warning "Implement CPU reset"
+}
+
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9260 processor initialization
+ * -------------------------------------------------------------------- */
+
+void __init at91sam9260_initialize(unsigned long main_clock)
+{
+        /* Map peripherals */
+        iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
+
+        at91_arch_reset = at91sam9260_reset;
+        at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
+                        | (1 << AT91SAM9260_ID_IRQ2);
+
+        /* Init clock subsystem */
+        at91_clock_init(main_clock);
+
+        /* Register the processor-specific clocks */
+        at91sam9260_register_clocks();
+
+        /* Register GPIO subsystem */
+        at91_gpio_init(at91sam9260_gpio, 3);
+}
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
+        7,      /* Advanced Interrupt Controller */
+        7,      /* System Peripherals */
+        0,      /* Parallel IO Controller A */
+        0,      /* Parallel IO Controller B */
+        0,      /* Parallel IO Controller C */
+        0,      /* Analog-to-Digital Converter */
+        6,      /* USART 0 */
+        6,      /* USART 1 */
+        6,      /* USART 2 */
+        0,      /* Multimedia Card Interface */
+        4,      /* USB Device Port */
+        0,      /* Two-Wire Interface */
+        6,      /* Serial Peripheral Interface 0 */
+        6,      /* Serial Peripheral Interface 1 */
+        5,      /* Serial Synchronous Controller */
+        0,
+        0,
+        0,      /* Timer Counter 0 */
+        0,      /* Timer Counter 1 */
+        0,      /* Timer Counter 2 */
+        3,      /* USB Host port */
+        3,      /* Ethernet */
+        0,      /* Image Sensor Interface */
+        6,      /* USART 3 */
+        6,      /* USART 4 */
+        6,      /* USART 5 */
+        0,      /* Timer Counter 3 */
+        0,      /* Timer Counter 4 */
+        0,      /* Timer Counter 5 */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+};
+
+void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
+{
+        if (!priority)
+                priority = at91sam9260_default_irq_priority;
+
+        /* Initialize the AIC interrupt controller */
+        at91_aic_init(priority);
+
+        /* Enable GPIO interrupts */
+        at91_gpio_irq_setup();
+}
diff --git a/arch/arm/mach-at91rm9200/at91sam9260_devices.c b/arch/arm/mach-at91rm9200/at91sam9260_devices.c
new file mode 100644
index 000000000000..a6c596dc4516
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam9260_devices.c
@@ -0,0 +1,866 @@
+/*
+ * arch/arm/mach-at91rm9200/at91sam9260_devices.c
+ *
+ *  Copyright (C) 2006 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <linux/platform_device.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam926x_mc.h>
+
+#include "generic.h"
+
+#define SZ_512  0x00000200
+#define SZ_256  0x00000100
+#define SZ_16   0x00000010
+
+/* --------------------------------------------------------------------
+ *  USB Host
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static u64 ohci_dmamask = 0xffffffffUL;
+static struct at91_usbh_data usbh_data;
+
+static struct resource usbh_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_UHP_BASE,
+                .end    = AT91SAM9260_UHP_BASE + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_UHP,
+                .end    = AT91SAM9260_ID_UHP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91_usbh_device = {
+        .name           = "at91_ohci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &ohci_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+                                .platform_data          = &usbh_data,
+        },
+        .resource       = usbh_resources,
+        .num_resources  = ARRAY_SIZE(usbh_resources),
+};
+
+void __init at91_add_device_usbh(struct at91_usbh_data *data)
+{
+        if (!data)
+                return;
+
+        usbh_data = *data;
+        platform_device_register(&at91_usbh_device);
+}
+#else
+void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  USB Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_USB_GADGET_AT91
+static struct at91_udc_data udc_data;
+
+static struct resource udc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_UDP,
+                .end    = AT91SAM9260_BASE_UDP + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_UDP,
+                .end    = AT91SAM9260_ID_UDP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91_udc_device = {
+        .name           = "at91_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data          = &udc_data,
+        },
+        .resource       = udc_resources,
+        .num_resources  = ARRAY_SIZE(udc_resources),
+};
+
+void __init at91_add_device_udc(struct at91_udc_data *data)
+{
+        if (!data)
+                return;
+
+        if (data->vbus_pin) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+        }
+
+        /* Pullup pin is handled internally by USB device peripheral */
+
+        udc_data = *data;
+        platform_device_register(&at91_udc_device);
+}
+#else
+void __init at91_add_device_udc(struct at91_udc_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  Ethernet
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
+static u64 eth_dmamask = 0xffffffffUL;
+static struct eth_platform_data eth_data;
+
+static struct resource eth_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_EMAC,
+                .end    = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_EMAC,
+                .end    = AT91SAM9260_ID_EMAC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9260_eth_device = {
+        .name           = "macb",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &eth_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+                                .platform_data          = &eth_data,
+        },
+        .resource       = eth_resources,
+        .num_resources  = ARRAY_SIZE(eth_resources),
+};
+
+void __init at91_add_device_eth(struct eth_platform_data *data)
+{
+        if (!data)
+                return;
+
+        if (data->phy_irq_pin) {
+                at91_set_gpio_input(data->phy_irq_pin, 0);
+                at91_set_deglitch(data->phy_irq_pin, 1);
+        }
+
+        /* Pins used for MII and RMII */
+        at91_set_A_periph(AT91_PIN_PA19, 0);    /* ETXCK_EREFCK */
+        at91_set_A_periph(AT91_PIN_PA17, 0);    /* ERXDV */
+        at91_set_A_periph(AT91_PIN_PA14, 0);    /* ERX0 */
+        at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERX1 */
+        at91_set_A_periph(AT91_PIN_PA18, 0);    /* ERXER */
+        at91_set_A_periph(AT91_PIN_PA16, 0);    /* ETXEN */
+        at91_set_A_periph(AT91_PIN_PA12, 0);    /* ETX0 */
+        at91_set_A_periph(AT91_PIN_PA13, 0);    /* ETX1 */
+        at91_set_A_periph(AT91_PIN_PA21, 0);    /* EMDIO */
+        at91_set_A_periph(AT91_PIN_PA20, 0);    /* EMDC */
+
+        if (!data->is_rmii) {
+                at91_set_B_periph(AT91_PIN_PA28, 0);    /* ECRS */
+                at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECOL */
+                at91_set_B_periph(AT91_PIN_PA25, 0);    /* ERX2 */
+                at91_set_B_periph(AT91_PIN_PA26, 0);    /* ERX3 */
+                at91_set_B_periph(AT91_PIN_PA27, 0);    /* ERXCK */
+                at91_set_B_periph(AT91_PIN_PA23, 0);    /* ETX2 */
+                at91_set_B_periph(AT91_PIN_PA24, 0);    /* ETX3 */
+                at91_set_B_periph(AT91_PIN_PA22, 0);    /* ETXER */
+        }
+
+        eth_data = *data;
+        platform_device_register(&at91sam9260_eth_device);
+}
+#else
+void __init at91_add_device_eth(struct eth_platform_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  MMC / SD
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+static u64 mmc_dmamask = 0xffffffffUL;
+static struct at91_mmc_data mmc_data;
+
+static struct resource mmc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_MCI,
+                .end    = AT91SAM9260_BASE_MCI + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_MCI,
+                .end    = AT91SAM9260_ID_MCI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9260_mmc_device = {
+        .name           = "at91_mci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &mmc_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+                                .platform_data          = &mmc_data,
+        },
+        .resource       = mmc_resources,
+        .num_resources  = ARRAY_SIZE(mmc_resources),
+};
+
+void __init at91_add_device_mmc(struct at91_mmc_data *data)
+{
+        if (!data)
+                return;
+
+        /* input/irq */
+        if (data->det_pin) {
+                at91_set_gpio_input(data->det_pin, 1);
+                at91_set_deglitch(data->det_pin, 1);
+        }
+        if (data->wp_pin)
+                at91_set_gpio_input(data->wp_pin, 1);
+        if (data->vcc_pin)
+                at91_set_gpio_output(data->vcc_pin, 0);
+
+        /* CLK */
+        at91_set_A_periph(AT91_PIN_PA8, 0);
+
+        if (data->slot_b) {
+                /* CMD */
+                at91_set_B_periph(AT91_PIN_PA1, 1);
+
+                /* DAT0, maybe DAT1..DAT3 */
+                at91_set_B_periph(AT91_PIN_PA0, 1);
+                if (data->wire4) {
+                        at91_set_B_periph(AT91_PIN_PA5, 1);
+                        at91_set_B_periph(AT91_PIN_PA4, 1);
+                        at91_set_B_periph(AT91_PIN_PA3, 1);
+                }
+        } else {
+                /* CMD */
+                at91_set_A_periph(AT91_PIN_PA7, 1);
+
+                /* DAT0, maybe DAT1..DAT3 */
+                at91_set_A_periph(AT91_PIN_PA6, 1);
+                if (data->wire4) {
+                        at91_set_A_periph(AT91_PIN_PA9, 1);
+                        at91_set_A_periph(AT91_PIN_PA10, 1);
+                        at91_set_A_periph(AT91_PIN_PA11, 1);
+                }
+        }
+
+        mmc_data = *data;
+        platform_device_register(&at91sam9260_mmc_device);
+}
+#else
+void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  NAND / SmartMedia
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
+static struct at91_nand_data nand_data;
+
+#define NAND_BASE       AT91_CHIPSELECT_3
+
+static struct resource nand_resources[] = {
+        {
+                .start  = NAND_BASE,
+                .end    = NAND_BASE + SZ_8M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device at91sam9260_nand_device = {
+        .name           = "at91_nand",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &nand_data,
+        },
+        .resource       = nand_resources,
+        .num_resources  = ARRAY_SIZE(nand_resources),
+};
+
+void __init at91_add_device_nand(struct at91_nand_data *data)
+{
+        unsigned long csa, mode;
+
+        if (!data)
+                return;
+
+        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC);
+
+        /* set the bus interface characteristics */
+        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
+                        | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+
+        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
+                        | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
+
+        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+
+        if (data->bus_width_16)
+                mode = AT91_SMC_DBW_16;
+        else
+                mode = AT91_SMC_DBW_8;
+        at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
+
+        /* enable pin */
+        if (data->enable_pin)
+                at91_set_gpio_output(data->enable_pin, 1);
+
+        /* ready/busy pin */
+        if (data->rdy_pin)
+                at91_set_gpio_input(data->rdy_pin, 1);
+
+        /* card detect pin */
+        if (data->det_pin)
+                at91_set_gpio_input(data->det_pin, 1);
+
+        nand_data = *data;
+        platform_device_register(&at91sam9260_nand_device);
+}
+#else
+void __init at91_add_device_nand(struct at91_nand_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  TWI (i2c)
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
+
+static struct resource twi_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_TWI,
+                .end    = AT91SAM9260_BASE_TWI + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_TWI,
+                .end    = AT91SAM9260_ID_TWI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9260_twi_device = {
+        .name           = "at91_i2c",
+        .id             = -1,
+        .resource       = twi_resources,
+        .num_resources  = ARRAY_SIZE(twi_resources),
+};
+
+void __init at91_add_device_i2c(void)
+{
+        /* pins used for TWI interface */
+        at91_set_A_periph(AT91_PIN_PA23, 0);            /* TWD */
+        at91_set_multi_drive(AT91_PIN_PA23, 1);
+
+        at91_set_A_periph(AT91_PIN_PA24, 0);            /* TWCK */
+        at91_set_multi_drive(AT91_PIN_PA24, 1);
+
+        platform_device_register(&at91sam9260_twi_device);
+}
+#else
+void __init at91_add_device_i2c(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  SPI
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+static u64 spi_dmamask = 0xffffffffUL;
+
+static struct resource spi0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_SPI0,
+                .end    = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_SPI0,
+                .end    = AT91SAM9260_ID_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9260_spi0_device = {
+        .name           = "atmel_spi",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+        },
+        .resource       = spi0_resources,
+        .num_resources  = ARRAY_SIZE(spi0_resources),
+};
+
+static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
+
+static struct resource spi1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_SPI1,
+                .end    = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_SPI1,
+                .end    = AT91SAM9260_ID_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9260_spi1_device = {
+        .name           = "atmel_spi",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+        },
+        .resource       = spi1_resources,
+        .num_resources  = ARRAY_SIZE(spi1_resources),
+};
+
+static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
+
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+{
+        int i;
+        unsigned long cs_pin;
+        short enable_spi0 = 0;
+        short enable_spi1 = 0;
+
+        /* Choose SPI chip-selects */
+        for (i = 0; i < nr_devices; i++) {
+                if (devices[i].controller_data)
+                        cs_pin = (unsigned long) devices[i].controller_data;
+                else if (devices[i].bus_num == 0)
+                        cs_pin = spi0_standard_cs[devices[i].chip_select];
+                else
+                        cs_pin = spi1_standard_cs[devices[i].chip_select];
+
+                if (devices[i].bus_num == 0)
+                        enable_spi0 = 1;
+                else
+                        enable_spi1 = 1;
+
+                /* enable chip-select pin */
+                at91_set_gpio_output(cs_pin, 1);
+
+                /* pass chip-select pin to driver */
+                devices[i].controller_data = (void *) cs_pin;
+        }
+
+        spi_register_board_info(devices, nr_devices);
+
+        /* Configure SPI bus(es) */
+        if (enable_spi0) {
+                at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
+                at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
+                at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI1_SPCK */
+
+                at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk");
+                platform_device_register(&at91sam9260_spi0_device);
+        }
+        if (enable_spi1) {
+                at91_set_A_periph(AT91_PIN_PB0, 0);     /* SPI1_MISO */
+                at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI1_MOSI */
+                at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI1_SPCK */
+
+                at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk");
+                platform_device_register(&at91sam9260_spi1_device);
+        }
+}
+#else
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  LEDs
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_LEDS)
+u8 at91_leds_cpu;
+u8 at91_leds_timer;
+
+void __init at91_init_leds(u8 cpu_led, u8 timer_led)
+{
+        at91_leds_cpu   = cpu_led;
+        at91_leds_timer = timer_led;
+}
+#else
+void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  UART
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_SERIAL_ATMEL)
+static struct resource dbgu_resources[] = {
+        [0] = {
+                .start  = AT91_VA_BASE_SYS + AT91_DBGU,
+                .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_SYS,
+                .end    = AT91_ID_SYS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data dbgu_data = {
+        .use_dma_tx     = 0,
+        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+        .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
+};
+
+static struct platform_device at91sam9260_dbgu_device = {
+        .name           = "atmel_usart",
+        .id             = 0,
+        .dev            = {
+                                .platform_data  = &dbgu_data,
+                                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource       = dbgu_resources,
+        .num_resources  = ARRAY_SIZE(dbgu_resources),
+};
+
+static inline void configure_dbgu_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PB14, 0);            /* DRXD */
+        at91_set_A_periph(AT91_PIN_PB15, 1);            /* DTXD */
+}
+
+static struct resource uart0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_US0,
+                .end    = AT91SAM9260_BASE_US0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_US0,
+                .end    = AT91SAM9260_ID_US0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart0_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9260_uart0_device = {
+        .name           = "atmel_usart",
+        .id             = 1,
+        .dev            = {
+                                .platform_data  = &uart0_data,
+                                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource       = uart0_resources,
+        .num_resources  = ARRAY_SIZE(uart0_resources),
+};
+
+static inline void configure_usart0_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD0 */
+        at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD0 */
+        at91_set_A_periph(AT91_PIN_PB26, 0);            /* RTS0 */
+        at91_set_A_periph(AT91_PIN_PB27, 0);            /* CTS0 */
+        at91_set_A_periph(AT91_PIN_PB24, 0);            /* DTR0 */
+        at91_set_A_periph(AT91_PIN_PB22, 0);            /* DSR0 */
+        at91_set_A_periph(AT91_PIN_PB23, 0);            /* DCD0 */
+        at91_set_A_periph(AT91_PIN_PB25, 0);            /* RI0 */
+}
+
+static struct resource uart1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_US1,
+                .end    = AT91SAM9260_BASE_US1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_US1,
+                .end    = AT91SAM9260_ID_US1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart1_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9260_uart1_device = {
+        .name           = "atmel_usart",
+        .id             = 2,
+        .dev            = {
+                                .platform_data  = &uart1_data,
+                                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource       = uart1_resources,
+        .num_resources  = ARRAY_SIZE(uart1_resources),
+};
+
+static inline void configure_usart1_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PB6, 1);             /* TXD1 */
+        at91_set_A_periph(AT91_PIN_PB7, 0);             /* RXD1 */
+        at91_set_A_periph(AT91_PIN_PB28, 0);            /* RTS1 */
+        at91_set_A_periph(AT91_PIN_PB29, 0);            /* CTS1 */
+}
+
+static struct resource uart2_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_US2,
+                .end    = AT91SAM9260_BASE_US2 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_US2,
+                .end    = AT91SAM9260_ID_US2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart2_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9260_uart2_device = {
+        .name           = "atmel_usart",
+        .id             = 3,
+        .dev            = {
+                                .platform_data  = &uart2_data,
+                                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource       = uart2_resources,
+        .num_resources  = ARRAY_SIZE(uart2_resources),
+};
+
+static inline void configure_usart2_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PB8, 1);             /* TXD2 */
+        at91_set_A_periph(AT91_PIN_PB9, 0);             /* RXD2 */
+}
+
+static struct resource uart3_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_US3,
+                .end    = AT91SAM9260_BASE_US3 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_US3,
+                .end    = AT91SAM9260_ID_US3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart3_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9260_uart3_device = {
+        .name           = "atmel_usart",
+        .id             = 4,
+        .dev            = {
+                                .platform_data  = &uart3_data,
+                                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource       = uart3_resources,
+        .num_resources  = ARRAY_SIZE(uart3_resources),
+};
+
+static inline void configure_usart3_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PB10, 1);            /* TXD3 */
+        at91_set_A_periph(AT91_PIN_PB11, 0);            /* RXD3 */
+}
+
+static struct resource uart4_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_US4,
+                .end    = AT91SAM9260_BASE_US4 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_US4,
+                .end    = AT91SAM9260_ID_US4,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart4_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9260_uart4_device = {
+        .name           = "atmel_usart",
+        .id             = 5,
+        .dev            = {
+                                .platform_data  = &uart4_data,
+                                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource       = uart4_resources,
+        .num_resources  = ARRAY_SIZE(uart4_resources),
+};
+
+static inline void configure_usart4_pins(void)
+{
+        at91_set_B_periph(AT91_PIN_PA31, 1);            /* TXD4 */
+        at91_set_B_periph(AT91_PIN_PA30, 0);            /* RXD4 */
+}
+
+static struct resource uart5_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_US5,
+                .end    = AT91SAM9260_BASE_US5 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_US5,
+                .end    = AT91SAM9260_ID_US5,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart5_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9260_uart5_device = {
+        .name           = "atmel_usart",
+        .id             = 6,
+        .dev            = {
+                                .platform_data  = &uart5_data,
+                                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource       = uart5_resources,
+        .num_resources  = ARRAY_SIZE(uart5_resources),
+};
+
+static inline void configure_usart5_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PB12, 1);            /* TXD5 */
+        at91_set_A_periph(AT91_PIN_PB13, 0);            /* RXD5 */
+}
+
+struct platform_device *at91_uarts[ATMEL_MAX_UART];     /* the UARTs to use */
+struct platform_device *atmel_default_console_device;   /* the serial console device */
+
+void __init at91_init_serial(struct at91_uart_config *config)
+{
+        int i;
+
+        /* Fill in list of supported UARTs */
+        for (i = 0; i < config->nr_tty; i++) {
+                switch (config->tty_map[i]) {
+                        case 0:
+                                configure_usart0_pins();
+                                at91_uarts[i] = &at91sam9260_uart0_device;
+                                at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
+                                break;
+                        case 1:
+                                configure_usart1_pins();
+                                at91_uarts[i] = &at91sam9260_uart1_device;
+                                at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
+                                break;
+                        case 2:
+                                configure_usart2_pins();
+                                at91_uarts[i] = &at91sam9260_uart2_device;
+                                at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
+                                break;
+                        case 3:
+                                configure_usart3_pins();
+                                at91_uarts[i] = &at91sam9260_uart3_device;
+                                at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
+                                break;
+                        case 4:
+                                configure_usart4_pins();
+                                at91_uarts[i] = &at91sam9260_uart4_device;
+                                at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
+                                break;
+                        case 5:
+                                configure_usart5_pins();
+                                at91_uarts[i] = &at91sam9260_uart5_device;
+                                at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
+                                break;
+                        case 6:
+                                configure_dbgu_pins();
+                                at91_uarts[i] = &at91sam9260_dbgu_device;
+                                at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
+                                break;
+                        default:
+                                continue;
+                }
+                at91_uarts[i]->id = i;          /* update ID number to mapped ID */
+        }
+
+        /* Set serial console device */
+        if (config->console_tty < ATMEL_MAX_UART)
+                atmel_default_console_device = at91_uarts[config->console_tty];
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
+}
+
+void __init at91_add_device_serial(void)
+{
+        int i;
+
+        for (i = 0; i < ATMEL_MAX_UART; i++) {
+                if (at91_uarts[i])
+                        platform_device_register(at91_uarts[i]);
+        }
+}
+#else
+void __init at91_init_serial(struct at91_uart_config *config) {}
+void __init at91_add_device_serial(void) {}
+#endif
+
+
+/* -------------------------------------------------------------------- */
+/*
+ * These devices are always present and don't need any board-specific
+ * setup.
+ */
+static int __init at91_add_standard_devices(void)
+{
+        return 0;
+}
+
+arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91rm9200/at91sam9261.c b/arch/arm/mach-at91rm9200/at91sam9261.c
new file mode 100644
index 000000000000..5a82f35da2e9
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam9261.c
@@ -0,0 +1,289 @@
+/*
+ * arch/arm/mach-at91rm9200/at91sam9261.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91_pmc.h>
+
+#include "generic.h"
+#include "clock.h"
+
+static struct map_desc at91sam9261_io_desc[] __initdata = {
+        {
+                .virtual        = AT91_VA_BASE_SYS,
+                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
+                .pfn            = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
+                .length         = AT91SAM9261_SRAM_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioA_clk = {
+        .name           = "pioA_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_PIOA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+        .name           = "pioB_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_PIOB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+        .name           = "pioC_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_PIOC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_US0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_US1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_US2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc_clk = {
+        .name           = "mci_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_MCI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udc_clk = {
+        .name           = "udc_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_UDP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi_clk = {
+        .name           = "twi_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_TWI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ohci_clk = {
+        .name           = "ohci_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk lcdc_clk = {
+        .name           = "lcdc_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_LCDC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+        &pioA_clk,
+        &pioB_clk,
+        &pioC_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &mmc_clk,
+        &udc_clk,
+        &twi_clk,
+        &spi0_clk,
+        &spi1_clk,
+        // ssc 0 .. ssc2
+        // tc0 .. tc2
+        &ohci_clk,
+        &lcdc_clk,
+        // irq0 .. irq2
+};
+
+/*
+ * The four programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+static struct clk pck2 = {
+        .name           = "pck2",
+        .pmc_mask       = AT91_PMC_PCK2,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 2,
+};
+static struct clk pck3 = {
+        .name           = "pck3",
+        .pmc_mask       = AT91_PMC_PCK3,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 3,
+};
+
+/* HClocks */
+static struct clk hck0 = {
+        .name           = "hck0",
+        .pmc_mask       = AT91_PMC_HCK0,
+        .type           = CLK_TYPE_SYSTEM,
+        .id             = 0,
+};
+static struct clk hck1 = {
+        .name           = "hck1",
+        .pmc_mask       = AT91_PMC_HCK1,
+        .type           = CLK_TYPE_SYSTEM,
+        .id             = 1,
+};
+
+static void __init at91sam9261_register_clocks(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+
+        clk_register(&pck0);
+        clk_register(&pck1);
+        clk_register(&pck2);
+        clk_register(&pck3);
+
+        clk_register(&hck0);
+        clk_register(&hck1);
+}
+
+/* --------------------------------------------------------------------
+ *  GPIO
+ * -------------------------------------------------------------------- */
+
+static struct at91_gpio_bank at91sam9261_gpio[] = {
+        {
+                .id             = AT91SAM9261_ID_PIOA,
+                .offset         = AT91_PIOA,
+                .clock          = &pioA_clk,
+        }, {
+                .id             = AT91SAM9261_ID_PIOB,
+                .offset         = AT91_PIOB,
+                .clock          = &pioB_clk,
+        }, {
+                .id             = AT91SAM9261_ID_PIOC,
+                .offset         = AT91_PIOC,
+                .clock          = &pioC_clk,
+        }
+};
+
+static void at91sam9261_reset(void)
+{
+#warning "Implement CPU reset"
+}
+
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9261 processor initialization
+ * -------------------------------------------------------------------- */
+
+void __init at91sam9261_initialize(unsigned long main_clock)
+{
+        /* Map peripherals */
+        iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
+
+        at91_arch_reset = at91sam9261_reset;
+        at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
+                        | (1 << AT91SAM9261_ID_IRQ2);
+
+        /* Init clock subsystem */
+        at91_clock_init(main_clock);
+
+        /* Register the processor-specific clocks */
+        at91sam9261_register_clocks();
+
+        /* Register GPIO subsystem */
+        at91_gpio_init(at91sam9261_gpio, 3);
+}
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
+        7,      /* Advanced Interrupt Controller */
+        7,      /* System Peripherals */
+        0,      /* Parallel IO Controller A */
+        0,      /* Parallel IO Controller B */
+        0,      /* Parallel IO Controller C */
+        0,
+        6,      /* USART 0 */
+        6,      /* USART 1 */
+        6,      /* USART 2 */
+        0,      /* Multimedia Card Interface */
+        4,      /* USB Device Port */
+        0,      /* Two-Wire Interface */
+        6,      /* Serial Peripheral Interface 0 */
+        6,      /* Serial Peripheral Interface 1 */
+        5,      /* Serial Synchronous Controller 0 */
+        5,      /* Serial Synchronous Controller 1 */
+        5,      /* Serial Synchronous Controller 2 */
+        0,      /* Timer Counter 0 */
+        0,      /* Timer Counter 1 */
+        0,      /* Timer Counter 2 */
+        3,      /* USB Host port */
+        3,      /* LCD Controller */
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+};
+
+void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])
+{
+        if (!priority)
+                priority = at91sam9261_default_irq_priority;
+
+        /* Initialize the AIC interrupt controller */
+        at91_aic_init(priority);
+
+        /* Enable GPIO interrupts */
+        at91_gpio_irq_setup();
+}
diff --git a/arch/arm/mach-at91rm9200/at91sam9261_devices.c b/arch/arm/mach-at91rm9200/at91sam9261_devices.c
new file mode 100644
index 000000000000..ed1d79081b35
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam9261_devices.c
@@ -0,0 +1,741 @@
+/*
+ * arch/arm/mach-at91rm9200/at91sam9261_devices.c
+ *
+ *  Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
+ *  Copyright (C) 2005 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <linux/platform_device.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91sam9261_matrix.h>
+#include <asm/arch/at91sam926x_mc.h>
+
+#include "generic.h"
+
+#define SZ_512  0x00000200
+#define SZ_256  0x00000100
+#define SZ_16   0x00000010
+
+/* --------------------------------------------------------------------
+ *  USB Host
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static u64 ohci_dmamask = 0xffffffffUL;
+static struct at91_usbh_data usbh_data;
+
+static struct resource usbh_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_UHP_BASE,
+                .end    = AT91SAM9261_UHP_BASE + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_UHP,
+                .end    = AT91SAM9261_ID_UHP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9261_usbh_device = {
+        .name           = "at91_ohci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &ohci_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+                                .platform_data          = &usbh_data,
+        },
+        .resource       = usbh_resources,
+        .num_resources  = ARRAY_SIZE(usbh_resources),
+};
+
+void __init at91_add_device_usbh(struct at91_usbh_data *data)
+{
+        if (!data)
+                return;
+
+        usbh_data = *data;
+        platform_device_register(&at91sam9261_usbh_device);
+}
+#else
+void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  USB Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_USB_GADGET_AT91
+static struct at91_udc_data udc_data;
+
+static struct resource udc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_UDP,
+                .end    = AT91SAM9261_BASE_UDP + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_UDP,
+                .end    = AT91SAM9261_ID_UDP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9261_udc_device = {
+        .name           = "at91_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data          = &udc_data,
+        },
+        .resource       = udc_resources,
+        .num_resources  = ARRAY_SIZE(udc_resources),
+};
+
+void __init at91_add_device_udc(struct at91_udc_data *data)
+{
+        unsigned long x;
+
+        if (!data)
+                return;
+
+        if (data->vbus_pin) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+        }
+
+        /* Pullup pin is handled internally */
+        x = at91_sys_read(AT91_MATRIX_USBPUCR);
+        at91_sys_write(AT91_MATRIX_USBPUCR, x | AT91_MATRIX_USBPUCR_PUON);
+
+        udc_data = *data;
+        platform_device_register(&at91sam9261_udc_device);
+}
+#else
+void __init at91_add_device_udc(struct at91_udc_data *data) {}
+#endif
+
+/* --------------------------------------------------------------------
+ *  MMC / SD
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+static u64 mmc_dmamask = 0xffffffffUL;
+static struct at91_mmc_data mmc_data;
+
+static struct resource mmc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_MCI,
+                .end    = AT91SAM9261_BASE_MCI + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_MCI,
+                .end    = AT91SAM9261_ID_MCI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9261_mmc_device = {
+        .name           = "at91_mci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &mmc_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+                                .platform_data          = &mmc_data,
+        },
+        .resource       = mmc_resources,
+        .num_resources  = ARRAY_SIZE(mmc_resources),
+};
+
+void __init at91_add_device_mmc(struct at91_mmc_data *data)
+{
+        if (!data)
+                return;
+
+        /* input/irq */
+        if (data->det_pin) {
+                at91_set_gpio_input(data->det_pin, 1);
+                at91_set_deglitch(data->det_pin, 1);
+        }
+        if (data->wp_pin)
+                at91_set_gpio_input(data->wp_pin, 1);
+        if (data->vcc_pin)
+                at91_set_gpio_output(data->vcc_pin, 0);
+
+        /* CLK */
+        at91_set_B_periph(AT91_PIN_PA2, 0);
+
+        /* CMD */
+        at91_set_B_periph(AT91_PIN_PA1, 1);
+
+        /* DAT0, maybe DAT1..DAT3 */
+        at91_set_B_periph(AT91_PIN_PA0, 1);
+        if (data->wire4) {
+                at91_set_B_periph(AT91_PIN_PA4, 1);
+                at91_set_B_periph(AT91_PIN_PA5, 1);
+                at91_set_B_periph(AT91_PIN_PA6, 1);
+        }
+
+        mmc_data = *data;
+        platform_device_register(&at91sam9261_mmc_device);
+}
+#else
+void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  NAND / SmartMedia
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
+static struct at91_nand_data nand_data;
+
+#define NAND_BASE       AT91_CHIPSELECT_3
+
+static struct resource nand_resources[] = {
+        {
+                .start  = NAND_BASE,
+                .end    = NAND_BASE + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device at91_nand_device = {
+        .name           = "at91_nand",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &nand_data,
+        },
+        .resource       = nand_resources,
+        .num_resources  = ARRAY_SIZE(nand_resources),
+};
+
+void __init at91_add_device_nand(struct at91_nand_data *data)
+{
+        unsigned long csa, mode;
+
+        if (!data)
+                return;
+
+        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC);
+
+        /* set the bus interface characteristics */
+        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
+                        | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+
+        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
+                        | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
+
+        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+
+        if (data->bus_width_16)
+                mode = AT91_SMC_DBW_16;
+        else
+                mode = AT91_SMC_DBW_8;
+        at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
+
+        /* enable pin */
+        if (data->enable_pin)
+                at91_set_gpio_output(data->enable_pin, 1);
+
+        /* ready/busy pin */
+        if (data->rdy_pin)
+                at91_set_gpio_input(data->rdy_pin, 1);
+
+        /* card detect pin */
+        if (data->det_pin)
+                at91_set_gpio_input(data->det_pin, 1);
+
+        at91_set_A_periph(AT91_PIN_PC0, 0);             /* NANDOE */
+        at91_set_A_periph(AT91_PIN_PC1, 0);             /* NANDWE */
+
+        nand_data = *data;
+        platform_device_register(&at91_nand_device);
+}
+
+#else
+void __init at91_add_device_nand(struct at91_nand_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  TWI (i2c)
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
+
+static struct resource twi_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_TWI,
+                .end    = AT91SAM9261_BASE_TWI + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_TWI,
+                .end    = AT91SAM9261_ID_TWI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9261_twi_device = {
+        .name           = "at91_i2c",
+        .id             = -1,
+        .resource       = twi_resources,
+        .num_resources  = ARRAY_SIZE(twi_resources),
+};
+
+void __init at91_add_device_i2c(void)
+{
+        /* pins used for TWI interface */
+        at91_set_A_periph(AT91_PIN_PA7, 0);             /* TWD */
+        at91_set_multi_drive(AT91_PIN_PA7, 1);
+
+        at91_set_A_periph(AT91_PIN_PA8, 0);             /* TWCK */
+        at91_set_multi_drive(AT91_PIN_PA8, 1);
+
+        platform_device_register(&at91sam9261_twi_device);
+}
+#else
+void __init at91_add_device_i2c(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  SPI
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+static u64 spi_dmamask = 0xffffffffUL;
+
+static struct resource spi0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_SPI0,
+                .end    = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_SPI0,
+                .end    = AT91SAM9261_ID_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9261_spi0_device = {
+        .name           = "atmel_spi",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+        },
+        .resource       = spi0_resources,
+        .num_resources  = ARRAY_SIZE(spi0_resources),
+};
+
+static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
+
+static struct resource spi1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_SPI1,
+                .end    = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_SPI1,
+                .end    = AT91SAM9261_ID_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9261_spi1_device = {
+        .name           = "atmel_spi",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+        },
+        .resource       = spi1_resources,
+        .num_resources  = ARRAY_SIZE(spi1_resources),
+};
+
+static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
+
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+{
+        int i;
+        unsigned long cs_pin;
+        short enable_spi0 = 0;
+        short enable_spi1 = 0;
+
+        /* Choose SPI chip-selects */
+        for (i = 0; i < nr_devices; i++) {
+                if (devices[i].controller_data)
+                        cs_pin = (unsigned long) devices[i].controller_data;
+                else if (devices[i].bus_num == 0)
+                        cs_pin = spi0_standard_cs[devices[i].chip_select];
+                else
+                        cs_pin = spi1_standard_cs[devices[i].chip_select];
+
+                if (devices[i].bus_num == 0)
+                        enable_spi0 = 1;
+                else
+                        enable_spi1 = 1;
+
+                /* enable chip-select pin */
+                at91_set_gpio_output(cs_pin, 1);
+
+                /* pass chip-select pin to driver */
+                devices[i].controller_data = (void *) cs_pin;
+        }
+
+        spi_register_board_info(devices, nr_devices);
+
+        /* Configure SPI bus(es) */
+        if (enable_spi0) {
+                at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
+                at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
+                at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
+
+                at91_clock_associate("spi0_clk", &at91sam9261_spi0_device.dev, "spi_clk");
+                platform_device_register(&at91sam9261_spi0_device);
+        }
+        if (enable_spi1) {
+                at91_set_A_periph(AT91_PIN_PB30, 0);    /* SPI1_MISO */
+                at91_set_A_periph(AT91_PIN_PB31, 0);    /* SPI1_MOSI */
+                at91_set_A_periph(AT91_PIN_PB29, 0);    /* SPI1_SPCK */
+
+                at91_clock_associate("spi1_clk", &at91sam9261_spi1_device.dev, "spi_clk");
+                platform_device_register(&at91sam9261_spi1_device);
+        }
+}
+#else
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  LCD Controller
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_FB_AT91) || defined(CONFIG_FB_AT91_MODULE)
+static u64 lcdc_dmamask = 0xffffffffUL;
+static struct at91fb_info lcdc_data;
+
+static struct resource lcdc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_LCDC_BASE,
+                .end    = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_LCDC,
+                .end    = AT91SAM9261_ID_LCDC,
+                .flags  = IORESOURCE_IRQ,
+        },
+#if defined(CONFIG_FB_INTSRAM)
+        [2] = {
+                .start  = AT91SAM9261_SRAM_BASE,
+                .end    = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+#endif
+};
+
+static struct platform_device at91_lcdc_device = {
+        .name           = "at91-fb",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &lcdc_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+                                .platform_data          = &lcdc_data,
+        },
+        .resource       = lcdc_resources,
+        .num_resources  = ARRAY_SIZE(lcdc_resources),
+};
+
+void __init at91_add_device_lcdc(struct at91fb_info *data)
+{
+        if (!data) {
+                return;
+        }
+
+        at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
+        at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
+        at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
+        at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
+        at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
+        at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
+        at91_set_A_periph(AT91_PIN_PB9, 0);     /* LCDD4 */
+        at91_set_A_periph(AT91_PIN_PB10, 0);    /* LCDD5 */
+        at91_set_A_periph(AT91_PIN_PB11, 0);    /* LCDD6 */
+        at91_set_A_periph(AT91_PIN_PB12, 0);    /* LCDD7 */
+        at91_set_A_periph(AT91_PIN_PB15, 0);    /* LCDD10 */
+        at91_set_A_periph(AT91_PIN_PB16, 0);    /* LCDD11 */
+        at91_set_A_periph(AT91_PIN_PB17, 0);    /* LCDD12 */
+        at91_set_A_periph(AT91_PIN_PB18, 0);    /* LCDD13 */
+        at91_set_A_periph(AT91_PIN_PB19, 0);    /* LCDD14 */
+        at91_set_A_periph(AT91_PIN_PB20, 0);    /* LCDD15 */
+        at91_set_B_periph(AT91_PIN_PB23, 0);    /* LCDD18 */
+        at91_set_B_periph(AT91_PIN_PB24, 0);    /* LCDD19 */
+        at91_set_B_periph(AT91_PIN_PB25, 0);    /* LCDD20 */
+        at91_set_B_periph(AT91_PIN_PB26, 0);    /* LCDD21 */
+        at91_set_B_periph(AT91_PIN_PB27, 0);    /* LCDD22 */
+        at91_set_B_periph(AT91_PIN_PB28, 0);    /* LCDD23 */
+
+        lcdc_data = *data;
+        platform_device_register(&at91_lcdc_device);
+}
+#else
+void __init at91_add_device_lcdc(struct at91fb_info *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  LEDs
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_LEDS)
+u8 at91_leds_cpu;
+u8 at91_leds_timer;
+
+void __init at91_init_leds(u8 cpu_led, u8 timer_led)
+{
+        at91_leds_cpu   = cpu_led;
+        at91_leds_timer = timer_led;
+}
+#else
+void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  UART
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SERIAL_ATMEL)
+static struct resource dbgu_resources[] = {
+        [0] = {
+                .start  = AT91_VA_BASE_SYS + AT91_DBGU,
+                .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_SYS,
+                .end    = AT91_ID_SYS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data dbgu_data = {
+        .use_dma_tx     = 0,
+        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+        .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
+};
+
+static struct platform_device at91sam9261_dbgu_device = {
+        .name           = "atmel_usart",
+        .id             = 0,
+        .dev            = {
+                                .platform_data  = &dbgu_data,
+                                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource       = dbgu_resources,
+        .num_resources  = ARRAY_SIZE(dbgu_resources),
+};
+
+static inline void configure_dbgu_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PA9, 0);             /* DRXD */
+        at91_set_A_periph(AT91_PIN_PA10, 1);            /* DTXD */
+}
+
+static struct resource uart0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_US0,
+                .end    = AT91SAM9261_BASE_US0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_US0,
+                .end    = AT91SAM9261_ID_US0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart0_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9261_uart0_device = {
+        .name           = "atmel_usart",
+        .id             = 1,
+        .dev            = {
+                                .platform_data  = &uart0_data,
+                                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource       = uart0_resources,
+        .num_resources  = ARRAY_SIZE(uart0_resources),
+};
+
+static inline void configure_usart0_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PC8, 1);             /* TXD0 */
+        at91_set_A_periph(AT91_PIN_PC9, 0);             /* RXD0 */
+        at91_set_A_periph(AT91_PIN_PC10, 0);            /* RTS0 */
+        at91_set_A_periph(AT91_PIN_PC11, 0);            /* CTS0 */
+}
+
+static struct resource uart1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_US1,
+                .end    = AT91SAM9261_BASE_US1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_US1,
+                .end    = AT91SAM9261_ID_US1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart1_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9261_uart1_device = {
+        .name           = "atmel_usart",
+        .id             = 2,
+        .dev            = {
+                                .platform_data  = &uart1_data,
+                                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource       = uart1_resources,
+        .num_resources  = ARRAY_SIZE(uart1_resources),
+};
+
+static inline void configure_usart1_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PC12, 1);            /* TXD1 */
+        at91_set_A_periph(AT91_PIN_PC13, 0);            /* RXD1 */
+}
+
+static struct resource uart2_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_US2,
+                .end    = AT91SAM9261_BASE_US2 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_US2,
+                .end    = AT91SAM9261_ID_US2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart2_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9261_uart2_device = {
+        .name           = "atmel_usart",
+        .id             = 3,
+        .dev            = {
+                                .platform_data  = &uart2_data,
+                                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource       = uart2_resources,
+        .num_resources  = ARRAY_SIZE(uart2_resources),
+};
+
+static inline void configure_usart2_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PC15, 0);            /* RXD2 */
+        at91_set_A_periph(AT91_PIN_PC14, 1);            /* TXD2 */
+}
+
+struct platform_device *at91_uarts[ATMEL_MAX_UART];     /* the UARTs to use */
+struct platform_device *atmel_default_console_device;   /* the serial console device */
+
+void __init at91_init_serial(struct at91_uart_config *config)
+{
+        int i;
+
+        /* Fill in list of supported UARTs */
+        for (i = 0; i < config->nr_tty; i++) {
+                switch (config->tty_map[i]) {
+                        case 0:
+                                configure_usart0_pins();
+                                at91_uarts[i] = &at91sam9261_uart0_device;
+                                at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart");
+                                break;
+                        case 1:
+                                configure_usart1_pins();
+                                at91_uarts[i] = &at91sam9261_uart1_device;
+                                at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart");
+                                break;
+                        case 2:
+                                configure_usart2_pins();
+                                at91_uarts[i] = &at91sam9261_uart2_device;
+                                at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart");
+                                break;
+                        case 3:
+                                configure_dbgu_pins();
+                                at91_uarts[i] = &at91sam9261_dbgu_device;
+                                at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart");
+                                break;
+                        default:
+                                continue;
+                }
+                at91_uarts[i]->id = i;          /* update ID number to mapped ID */
+        }
+
+        /* Set serial console device */
+        if (config->console_tty < ATMEL_MAX_UART)
+                atmel_default_console_device = at91_uarts[config->console_tty];
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
+}
+
+void __init at91_add_device_serial(void)
+{
+        int i;
+
+        for (i = 0; i < ATMEL_MAX_UART; i++) {
+                if (at91_uarts[i])
+                        platform_device_register(at91_uarts[i]);
+        }
+}
+#else
+void __init at91_init_serial(struct at91_uart_config *config) {}
+void __init at91_add_device_serial(void) {}
+#endif
+
+
+/* -------------------------------------------------------------------- */
+
+/*
+ * These devices are always present and don't need any board-specific
+ * setup.
+ */
+static int __init at91_add_standard_devices(void)
+{
+        return 0;
+}
+
+arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91rm9200/at91sam926x_time.c b/arch/arm/mach-at91rm9200/at91sam926x_time.c
new file mode 100644
index 000000000000..99df5f6ee42e
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam926x_time.c
@@ -0,0 +1,114 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/at91sam926x_time.c
+ *
+ * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
+ * Revision      2005 M. Nicolas Diremdjian, ATMEL Rousset, France
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/time.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/mach/time.h>
+
+#include <asm/arch/at91_pit.h>
+
+
+#define PIT_CPIV(x)     ((x) & AT91_PIT_CPIV)
+#define PIT_PICNT(x)    (((x) & AT91_PIT_PICNT) >> 20)
+
+/*
+ * Returns number of microseconds since last timer interrupt.  Note that interrupts
+ * will have been disabled by do_gettimeofday()
+ *  'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
+ *  'tick' is usecs per jiffy (linux/timex.h).
+ */
+static unsigned long at91sam926x_gettimeoffset(void)
+{
+        unsigned long elapsed;
+        unsigned long t = at91_sys_read(AT91_PIT_PIIR);
+
+        elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t);         /* hardware clock cycles */
+
+        return (unsigned long)(elapsed * 1000000) / LATCH;
+}
+
+/*
+ * IRQ handler for the timer.
+ */
+static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
+{
+        volatile long nr_ticks;
+
+        if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) {       /* This is a shared interrupt */
+                write_seqlock(&xtime_lock);
+
+                /* Get number to ticks performed before interrupt and clear PIT interrupt */
+                nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+                do {
+                        timer_tick();
+                        nr_ticks--;
+                } while (nr_ticks);
+
+                write_sequnlock(&xtime_lock);
+                return IRQ_HANDLED;
+        } else
+                return IRQ_NONE;                /* not handled */
+}
+
+static struct irqaction at91sam926x_timer_irq = {
+        .name           = "at91_tick",
+        .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER,
+        .handler        = at91sam926x_timer_interrupt
+};
+
+void at91sam926x_timer_reset(void)
+{
+        /* Disable timer */
+        at91_sys_write(AT91_PIT_MR, 0);
+
+        /* Clear any pending interrupts */
+        (void) at91_sys_read(AT91_PIT_PIVR);
+
+        /* Set Period Interval timer and enable its interrupt */
+        at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN);
+}
+
+/*
+ * Set up timer interrupt.
+ */
+void __init at91sam926x_timer_init(void)
+{
+        /* Initialize and enable the timer */
+        at91sam926x_timer_reset();
+
+        /* Make IRQs happen for the system timer. */
+        setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
+}
+
+#ifdef CONFIG_PM
+static void at91sam926x_timer_suspend(void)
+{
+        /* Disable timer */
+        at91_sys_write(AT91_PIT_MR, 0);
+}
+#else
+#define at91sam926x_timer_suspend       NULL
+#endif
+
+struct sys_timer at91sam926x_timer = {
+        .init           = at91sam926x_timer_init,
+        .offset         = at91sam926x_gettimeoffset,
+        .suspend        = at91sam926x_timer_suspend,
+        .resume         = at91sam926x_timer_reset,
+};
+
diff --git a/arch/arm/mach-at91rm9200/board-carmeva.c b/arch/arm/mach-at91rm9200/board-carmeva.c
index 98208740e7c5..654f0379550a 100644
--- a/arch/arm/mach-at91rm9200/board-carmeva.c
+++ b/arch/arm/mach-at91rm9200/board-carmeva.c
@@ -65,7 +65,6 @@ static void __init carmeva_init_irq(void)
         at91rm9200_init_interrupts(NULL);
 }
 
-
 static struct at91_eth_data __initdata carmeva_eth_data = {
         .phy_irq_pin    = AT91_PIN_PC4,
         .is_rmii        = 1,
@@ -89,8 +88,33 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
 // };
 
 static struct at91_mmc_data __initdata carmeva_mmc_data = {
-        .is_b           = 0,
+        .slot_b         = 0,
         .wire4          = 1,
+        .det_pin        = AT91_PIN_PB10,
+        .wp_pin         = AT91_PIN_PC14,
+};
+
+static struct spi_board_info carmeva_spi_devices[] = {
+        { /* DataFlash chip */
+                .modalias = "mtd_dataflash",
+                .chip_select  = 0,
+                .max_speed_hz = 10 * 1000 * 1000,
+        },
+        { /* User accessable spi - cs1 (250KHz) */
+                .modalias = "spi-cs1",
+                .chip_select  = 1,
+                .max_speed_hz = 250 *  1000,
+        },
+        { /* User accessable spi - cs2 (1MHz) */
+                .modalias = "spi-cs2",
+                .chip_select  = 2,
+                .max_speed_hz = 1 * 1000 *  1000,
+        },
+        { /* User accessable spi - cs3 (10MHz) */
+                .modalias = "spi-cs3",
+                .chip_select  = 3,
+                .max_speed_hz = 10 * 1000 *  1000,
+        },
 };
 
 static void __init carmeva_board_init(void)
@@ -105,10 +129,10 @@ static void __init carmeva_board_init(void)
         at91_add_device_udc(&carmeva_udc_data);
         /* I2C */
         at91_add_device_i2c();
+        /* SPI */
+        at91_add_device_spi(carmeva_spi_devices, ARRAY_SIZE(carmeva_spi_devices));
         /* Compact Flash */
 //      at91_add_device_cf(&carmeva_cf_data);
-        /* SPI */
-//      at91_add_device_spi(NULL, 0);
         /* MMC */
         at91_add_device_mmc(&carmeva_mmc_data);
 }
diff --git a/arch/arm/mach-at91rm9200/board-csb337.c b/arch/arm/mach-at91rm9200/board-csb337.c
index 8eeae491ce71..b8bb8052607a 100644
--- a/arch/arm/mach-at91rm9200/board-csb337.c
+++ b/arch/arm/mach-at91rm9200/board-csb337.c
@@ -99,7 +99,7 @@ static struct at91_cf_data __initdata csb337_cf_data = {
 
 static struct at91_mmc_data __initdata csb337_mmc_data = {
         .det_pin        = AT91_PIN_PD5,
-        .is_b           = 0,
+        .slot_b         = 0,
         .wire4          = 1,
         .wp_pin         = AT91_PIN_PD6,
 };
diff --git a/arch/arm/mach-at91rm9200/board-dk.c b/arch/arm/mach-at91rm9200/board-dk.c
index c699f3984d4b..7522bf91bce8 100644
--- a/arch/arm/mach-at91rm9200/board-dk.c
+++ b/arch/arm/mach-at91rm9200/board-dk.c
@@ -27,6 +27,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/mtd/physmap.h>
 
 #include <asm/hardware.h>
 #include <asm/setup.h>
@@ -39,6 +40,7 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/at91rm9200_mc.h>
 
 #include "generic.h"
 
@@ -93,7 +95,7 @@ static struct at91_cf_data __initdata dk_cf_data = {
 };
 
 static struct at91_mmc_data __initdata dk_mmc_data = {
-        .is_b           = 0,
+        .slot_b         = 0,
         .wire4          = 1,
 };
 
@@ -145,6 +147,30 @@ static struct at91_nand_data __initdata dk_nand_data = {
         .partition_info = nand_partitions,
 };
 
+#define DK_FLASH_BASE   AT91_CHIPSELECT_0
+#define DK_FLASH_SIZE   0x200000
+
+static struct physmap_flash_data dk_flash_data = {
+        .width  = 2,
+};
+
+static struct resource dk_flash_resource = {
+        .start          = DK_FLASH_BASE,
+        .end            = DK_FLASH_BASE + DK_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device dk_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                                .platform_data  = &dk_flash_data,
+                        },
+        .resource       = &dk_flash_resource,
+        .num_resources  = 1,
+};
+
+
 static void __init dk_board_init(void)
 {
         /* Serial */
@@ -172,6 +198,8 @@ static void __init dk_board_init(void)
 #endif
         /* NAND */
         at91_add_device_nand(&dk_nand_data);
+        /* NOR Flash */
+        platform_device_register(&dk_flash);
         /* VGA */
 //      dk_add_device_video();
 }
diff --git a/arch/arm/mach-at91rm9200/board-eb9200.c b/arch/arm/mach-at91rm9200/board-eb9200.c
index 65e867ba2df3..80b72cf7264c 100644
--- a/arch/arm/mach-at91rm9200/board-eb9200.c
+++ b/arch/arm/mach-at91rm9200/board-eb9200.c
@@ -87,7 +87,7 @@ static struct at91_cf_data __initdata eb9200_cf_data = {
 };
 
 static struct at91_mmc_data __initdata eb9200_mmc_data = {
-        .is_b           = 0,
+        .slot_b         = 0,
         .wire4          = 1,
 };
 
diff --git a/arch/arm/mach-at91rm9200/board-ek.c b/arch/arm/mach-at91rm9200/board-ek.c
index 830eb7932178..c4fdb415f20e 100644
--- a/arch/arm/mach-at91rm9200/board-ek.c
+++ b/arch/arm/mach-at91rm9200/board-ek.c
@@ -27,6 +27,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/mtd/physmap.h>
 
 #include <asm/hardware.h>
 #include <asm/setup.h>
@@ -39,6 +40,7 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/at91rm9200_mc.h>
 
 #include "generic.h"
 
@@ -87,7 +89,7 @@ static struct at91_udc_data __initdata ek_udc_data = {
 
 static struct at91_mmc_data __initdata ek_mmc_data = {
         .det_pin        = AT91_PIN_PB27,
-        .is_b           = 0,
+        .slot_b         = 0,
         .wire4          = 1,
         .wp_pin         = AT91_PIN_PA17,
 };
@@ -107,6 +109,30 @@ static struct spi_board_info ek_spi_devices[] = {
 #endif
 };
 
+#define EK_FLASH_BASE   AT91_CHIPSELECT_0
+#define EK_FLASH_SIZE   0x200000
+
+static struct physmap_flash_data ek_flash_data = {
+        .width  = 2,
+};
+
+static struct resource ek_flash_resource = {
+        .start          = EK_FLASH_BASE,
+        .end            = EK_FLASH_BASE + EK_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device ek_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                                .platform_data  = &ek_flash_data,
+                        },
+        .resource       = &ek_flash_resource,
+        .num_resources  = 1,
+};
+
+
 static void __init ek_board_init(void)
 {
         /* Serial */
@@ -130,6 +156,8 @@ static void __init ek_board_init(void)
         at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
         at91_add_device_mmc(&ek_mmc_data);
 #endif
+        /* NOR Flash */
+        platform_device_register(&ek_flash);
         /* VGA */
 //      ek_add_device_video();
 }
diff --git a/arch/arm/mach-at91rm9200/board-kb9202.c b/arch/arm/mach-at91rm9200/board-kb9202.c
index 35a954a44b1b..759d8191854f 100644
--- a/arch/arm/mach-at91rm9200/board-kb9202.c
+++ b/arch/arm/mach-at91rm9200/board-kb9202.c
@@ -84,7 +84,7 @@ static struct at91_udc_data __initdata kb9202_udc_data = {
 
 static struct at91_mmc_data __initdata kb9202_mmc_data = {
         .det_pin        = AT91_PIN_PB2,
-        .is_b           = 0,
+        .slot_b         = 0,
         .wire4          = 1,
 };
 
diff --git a/arch/arm/mach-at91rm9200/board-sam9260ek.c b/arch/arm/mach-at91rm9200/board-sam9260ek.c
new file mode 100644
index 000000000000..ffca9bdec37b
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/board-sam9260ek.c
@@ -0,0 +1,201 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/board-ek.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91sam926x_mc.h>
+
+#include "generic.h"
+
+
+/*
+ * Serial port configuration.
+ *    0 .. 5 = USART0 .. USART5
+ *    6      = DBGU
+ */
+static struct at91_uart_config __initdata ek_uart_config = {
+        .console_tty    = 0,                            /* ttyS0 */
+        .nr_tty         = 3,
+        .tty_map        = { 6, 0, 1, -1, -1, -1, -1 }   /* ttyS0, ..., ttyS6 */
+};
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91sam9260_initialize(18432000);
+
+        /* Setup the serial ports and console */
+        at91_init_serial(&ek_uart_config);
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PC5,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+#if !defined(CONFIG_MMC_AT91)
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 1,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+        {       /* DataFlash card */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#endif
+#endif
+#if defined(CONFIG_SND_AT73C213)
+        {       /* AT73C213 DAC */
+                .modalias       = "snd_at73c213",
+                .chip_select    = 0,
+                .max_speed_hz   = 10 * 1000 * 1000,
+                .bus_num        = 1,
+        },
+#endif
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct __initdata eth_platform_data ek_macb_data = {
+        .is_rmii        = 1,
+};
+
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Partition 1",
+                .offset = 0,
+                .size   = 256 * 1024,
+        },
+        {
+                .name   = "Partition 2",
+                .offset = 256 * 1024,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition *nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+//      .det_pin        = ... not connected
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata ek_mmc_data = {
+        .slot_b         = 1,
+        .wire4          = 1,
+//      .det_pin        = ... not connected
+//      .wp_pin         = ... not connected
+//      .vcc_pin        = ... not connected
+};
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* MMC */
+        at91_add_device_mmc(&ek_mmc_data);
+}
+
+MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
+        /* Maintainer: Atmel */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91rm9200/board-sam9261ek.c b/arch/arm/mach-at91rm9200/board-sam9261ek.c
new file mode 100644
index 000000000000..30b490d8886b
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/board-sam9261ek.c
@@ -0,0 +1,259 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/board-ek.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/dm9000.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91sam926x_mc.h>
+
+#include "generic.h"
+
+
+/*
+ * Serial port configuration.
+ *    0 .. 2 = USART0 .. USART2
+ *    3      = DBGU
+ */
+static struct at91_uart_config __initdata ek_uart_config = {
+        .console_tty    = 0,                            /* ttyS0 */
+        .nr_tty         = 1,
+        .tty_map        = { 3, -1, -1, -1 }             /* ttyS0, ..., ttyS3 */
+};
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91sam9261_initialize(18432000);
+
+        /* Setup the serial ports and console */
+        at91_init_serial(&ek_uart_config);
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9261_init_interrupts(NULL);
+}
+
+
+/*
+ * DM9000 ethernet device
+ */
+#if defined(CONFIG_DM9000)
+static struct resource at91sam9261_dm9000_resource[] = {
+        [0] = {
+                .start  = AT91_CHIPSELECT_2,
+                .end    = AT91_CHIPSELECT_2 + 3,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start  = AT91_CHIPSELECT_2 + 0x44,
+                .end    = AT91_CHIPSELECT_2 + 0xFF,
+                .flags  = IORESOURCE_MEM
+        },
+        [2] = {
+                .start  = AT91_PIN_PC11,
+                .end    = AT91_PIN_PC11,
+                .flags  = IORESOURCE_IRQ
+        }
+};
+
+static struct dm9000_plat_data dm9000_platdata = {
+        .flags          = DM9000_PLATF_16BITONLY,
+};
+
+static struct platform_device at91sam9261_dm9000_device = {
+        .name           = "dm9000",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(at91sam9261_dm9000_resource),
+        .resource       = at91sam9261_dm9000_resource,
+        .dev            = {
+                .platform_data  = &dm9000_platdata,
+        }
+};
+
+static void __init ek_add_device_dm9000(void)
+{
+        /*
+         * Configure Chip-Select 2 on SMC for the DM9000.
+         * Note: These timings were calculated for MASTER_CLOCK = 100000000
+         *  according to the DM9000 timings.
+         */
+        at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
+        at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
+        at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
+        at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
+
+        /* Configure Reset signal as output */
+        at91_set_gpio_output(AT91_PIN_PC10, 0);
+
+        /* Configure Interrupt pin as input, no pull-up */
+        at91_set_gpio_input(AT91_PIN_PC11, 0);
+
+        platform_device_register(&at91sam9261_dm9000_device);
+}
+#else
+static void __init ek_add_device_dm9000(void) {}
+#endif /* CONFIG_DM9000 */
+
+
+/*
+ * USB Host Port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+
+/*
+ * USB Device Port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PB29,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata ek_mmc_data = {
+        .wire4          = 1,
+//      .det_pin        = ... not connected
+//      .wp_pin         = ... not connected
+//      .vcc_pin        = ... not connected
+};
+
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Partition 1",
+                .offset = 0,
+                .size   = 256 * 1024,
+        },
+        {
+                .name   = "Partition 2",
+                .offset = 256 * 1024 ,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition *nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 22,
+        .cle            = 21,
+//      .det_pin        = ... not connected
+        .rdy_pin        = AT91_PIN_PC15,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+/*
+ * SPI devices
+ */
+static struct spi_board_info ek_spi_devices[] = {
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+        {       /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 3,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#elif defined(CONFIG_SND_AT73C213)
+        {       /* AT73C213 DAC */
+                .modalias       = "snd_at73c213",
+                .chip_select    = 3,
+                .max_speed_hz   = 10 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#endif
+};
+
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* I2C */
+        at91_add_device_i2c();
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* DM9000 ethernet */
+        ek_add_device_dm9000();
+
+        /* spi0 and mmc/sd share the same PIO pins */
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+#else
+        /* MMC */
+        at91_add_device_mmc(&ek_mmc_data);
+#endif
+}
+
+MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
+        /* Maintainer: Atmel */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91rm9200/clock.c b/arch/arm/mach-at91rm9200/clock.c
index a43b061a7c85..4dee21fefe5a 100644
--- a/arch/arm/mach-at91rm9200/clock.c
+++ b/arch/arm/mach-at91rm9200/clock.c
@@ -28,6 +28,8 @@
 #include <asm/mach-types.h>
 
 #include <asm/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/cpu.h>
 
 #include "clock.h"
 
@@ -41,6 +43,7 @@
 #define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
 #define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
 #define clk_is_peripheral(x)    ((x)->type & CLK_TYPE_PERIPHERAL)
+#define clk_is_sys(x)           ((x)->type & CLK_TYPE_SYSTEM)
 
 
 static LIST_HEAD(clocks);
@@ -114,13 +117,11 @@ static void pmc_sys_mode(struct clk *clk, int is_on)
 static struct clk udpck = {
         .name           = "udpck",
         .parent         = &pllb,
-        .pmc_mask       = AT91_PMC_UDP,
         .mode           = pmc_sys_mode,
 };
 static struct clk uhpck = {
         .name           = "uhpck",
         .parent         = &pllb,
-        .pmc_mask       = AT91_PMC_UHP,
         .mode           = pmc_sys_mode,
 };
 
@@ -434,6 +435,12 @@ int __init clk_register(struct clk *clk)
                 clk->mode = pmc_periph_mode;
                 list_add_tail(&clk->node, &clocks);
         }
+        else if (clk_is_sys(clk)) {
+                clk->parent = &mck;
+                clk->mode = pmc_sys_mode;
+
+                list_add_tail(&clk->node, &clocks);
+        }
 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
         else if (clk_is_programmable(clk)) {
                 clk->mode = pmc_sys_mode;
@@ -586,9 +593,21 @@ int __init at91_clock_init(unsigned long main_clock)
          */
         at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
-        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP);
+        if (cpu_is_at91rm9200()) {
+                uhpck.pmc_mask = AT91RM9200_PMC_UHP;
+                udpck.pmc_mask = AT91RM9200_PMC_UDP;
+                at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP);
+                at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
+        } else if (cpu_is_at91sam9260()) {
+                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
+                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
+                at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP);
+        } else if (cpu_is_at91sam9261()) {
+                uhpck.pmc_mask = (AT91SAM926x_PMC_UHP | AT91_PMC_HCK0);
+                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
+                at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91_PMC_HCK0 | AT91SAM926x_PMC_UDP);
+        }
         at91_sys_write(AT91_CKGR_PLLBR, 0);
-        at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);
 
         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
diff --git a/arch/arm/mach-at91rm9200/clock.h b/arch/arm/mach-at91rm9200/clock.h
index 0592e662ab37..b5c7a2eb2d1d 100644
--- a/arch/arm/mach-at91rm9200/clock.h
+++ b/arch/arm/mach-at91rm9200/clock.h
@@ -10,6 +10,7 @@
 #define CLK_TYPE_PLL            0x2
 #define CLK_TYPE_PROGRAMMABLE   0x4
 #define CLK_TYPE_PERIPHERAL     0x8
+#define CLK_TYPE_SYSTEM         0x10
 
 
 struct clk {
diff --git a/arch/arm/mach-at91rm9200/generic.h b/arch/arm/mach-at91rm9200/generic.h
index 694e411e285f..8c4d5a77d485 100644
--- a/arch/arm/mach-at91rm9200/generic.h
+++ b/arch/arm/mach-at91rm9200/generic.h
@@ -10,14 +10,19 @@
 
  /* Processors */
 extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks);
+extern void __init at91sam9260_initialize(unsigned long main_clock);
+extern void __init at91sam9261_initialize(unsigned long main_clock);
 
  /* Interrupts */
 extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
+extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
+extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
 
  /* Timer */
 struct sys_timer;
 extern struct sys_timer at91rm9200_timer;
+extern struct sys_timer at91sam926x_timer;
 
  /* Clocks */
 extern int __init at91_clock_init(unsigned long main_clock);
@@ -39,3 +44,6 @@ struct at91_gpio_bank {
 };
 extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
 extern void __init at91_gpio_irq_setup(void);
+
+extern void (*at91_arch_reset)(void);
+extern int at91_extern_irq;
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
index cec3862651d0..3f188508c391 100644
--- a/arch/arm/mach-at91rm9200/gpio.c
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -19,6 +19,8 @@
 
 #include <asm/io.h>
 #include <asm/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c
index cab0de9b8fa0..2148daafd29c 100644
--- a/arch/arm/mach-at91rm9200/irq.c
+++ b/arch/arm/mach-at91rm9200/irq.c
@@ -47,6 +47,10 @@ static void at91_aic_unmask_irq(unsigned int irq)
         at91_sys_write(AT91_AIC_IECR, 1 << irq);
 }
 
+unsigned int at91_extern_irq;
+
+#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
+
 static int at91_aic_set_type(unsigned irq, unsigned type)
 {
         unsigned int smr, srctype;
@@ -59,14 +63,16 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
                 srctype = AT91_AIC_SRCTYPE_RISING;
                 break;
         case IRQT_LOW:
-                if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0))  /* only supported on external interrupts */
+                if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))         /* only supported on external interrupts */
+                        srctype = AT91_AIC_SRCTYPE_LOW;
+                else
                         return -EINVAL;
-                srctype = AT91_AIC_SRCTYPE_LOW;
                 break;
         case IRQT_FALLING:
-                if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0))  /* only supported on external interrupts */
+                if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))         /* only supported on external interrupts */
+                        srctype = AT91_AIC_SRCTYPE_FALLING;
+                else
                         return -EINVAL;
-                srctype = AT91_AIC_SRCTYPE_FALLING;
                 break;
         default:
                 return -EINVAL;
diff --git a/arch/arm/mach-at91rm9200/pm.c b/arch/arm/mach-at91rm9200/pm.c
index 32c95d8eaacf..67aa5572a3ea 100644
--- a/arch/arm/mach-at91rm9200/pm.c
+++ b/arch/arm/mach-at91rm9200/pm.c
@@ -26,7 +26,10 @@
 #include <asm/mach/irq.h>
 #include <asm/mach-types.h>
 
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91rm9200_mc.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/cpu.h>
 
 #include "generic.h"
 
@@ -68,9 +71,15 @@ static int at91_pm_verify_clocks(void)
         scsr = at91_sys_read(AT91_PMC_SCSR);
 
         /* USB must not be using PLLB */
-        if ((scsr & (AT91_PMC_UHP | AT91_PMC_UDP)) != 0) {
-                pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
-                return 0;
+        if (cpu_is_at91rm9200()) {
+                if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) {
+                        pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
+                        return 0;
+                }
+        } else if (cpu_is_at91sam9260()) {
+#warning "Check SAM9260 USB clocks"
+        } else if (cpu_is_at91sam9261()) {
+#warning "Check SAM9261 USB clocks"
         }
 
 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
@@ -112,7 +121,6 @@ EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
 static void (*slow_clock)(void);
 
 
-
 static int at91_pm_enter(suspend_state_t state)
 {
         at91_gpio_suspend();
@@ -123,13 +131,7 @@ static int at91_pm_enter(suspend_state_t state)
                         (at91_sys_read(AT91_PMC_PCSR)
                                         | (1 << AT91_ID_FIQ)
                                         | (1 << AT91_ID_SYS)
-                                        | (1 << AT91RM9200_ID_IRQ0)
-                                        | (1 << AT91RM9200_ID_IRQ1)
-                                        | (1 << AT91RM9200_ID_IRQ2)
-                                        | (1 << AT91RM9200_ID_IRQ3)
-                                        | (1 << AT91RM9200_ID_IRQ4)
-                                        | (1 << AT91RM9200_ID_IRQ5)
-                                        | (1 << AT91RM9200_ID_IRQ6))
+                                        | (at91_extern_irq))
                                 & at91_sys_read(AT91_AIC_IMR),
                         state);
 
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index e346b03cd921..af7904b3d0a8 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -9,12 +9,24 @@ config CRUNCH
 
 comment "EP93xx Platforms"
 
+config MACH_ADSSPHERE
+        bool "Support ADS Sphere"
+        help
+          Say 'Y' here if you want your kernel to support the ADS
+          Sphere board.
+
 config MACH_EDB9302
         bool "Support Cirrus Logic EDB9302"
         help
           Say 'Y' here if you want your kernel to support the Cirrus
           Logic EDB9302 Evaluation Board.
 
+config MACH_EDB9302A
+        bool "Support Cirrus Logic EDB9302A"
+        help
+          Say 'Y' here if you want your kernel to support the Cirrus
+          Logic EDB9302A Evaluation Board.
+
 config MACH_EDB9312
         bool "Support Cirrus Logic EDB9312"
         help
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index c2eb18b530c2..b06641dd450d 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -6,7 +6,9 @@ obj-m			:=
 obj-n                   :=
 obj-                    :=
 
+obj-$(CONFIG_MACH_ADSSPHERE)    += adssphere.o
 obj-$(CONFIG_MACH_EDB9302)      += edb9302.o
+obj-$(CONFIG_MACH_EDB9302A)     += edb9302a.o
 obj-$(CONFIG_MACH_EDB9312)      += edb9312.o
 obj-$(CONFIG_MACH_EDB9315)      += edb9315.o
 obj-$(CONFIG_MACH_EDB9315A)     += edb9315a.o
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
new file mode 100644
index 000000000000..ac5d5818eb7b
--- /dev/null
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -0,0 +1,91 @@
+/*
+ * arch/arm/mach-ep93xx/adssphere.c
+ * ADS Sphere support.
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static struct physmap_flash_data adssphere_flash_data = {
+        .width          = 4,
+};
+
+static struct resource adssphere_flash_resource = {
+        .start          = 0x60000000,
+        .end            = 0x61ffffff,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device adssphere_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &adssphere_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &adssphere_flash_resource,
+};
+
+static struct ep93xx_eth_data adssphere_eth_data = {
+        .phy_id         = 1,
+};
+
+static struct resource adssphere_eth_resource[] = {
+        {
+                .start  = EP93XX_ETHERNET_PHYS_BASE,
+                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_EP93XX_ETHERNET,
+                .end    = IRQ_EP93XX_ETHERNET,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device adssphere_eth_device = {
+        .name           = "ep93xx-eth",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &adssphere_eth_data,
+        },
+        .num_resources  = 2,
+        .resource       = adssphere_eth_resource,
+};
+
+static void __init adssphere_init_machine(void)
+{
+        ep93xx_init_devices();
+        platform_device_register(&adssphere_flash);
+
+        memcpy(adssphere_eth_data.dev_addr,
+                (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
+        platform_device_register(&adssphere_eth_device);
+}
+
+MACHINE_START(ADSSPHERE, "ADS Sphere board")
+        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = adssphere_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ep93xx/edb9302a.c b/arch/arm/mach-ep93xx/edb9302a.c
new file mode 100644
index 000000000000..62e064bab1d2
--- /dev/null
+++ b/arch/arm/mach-ep93xx/edb9302a.c
@@ -0,0 +1,91 @@
+/*
+ * arch/arm/mach-ep93xx/edb9302a.c
+ * Cirrus Logic EDB9302A support.
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static struct physmap_flash_data edb9302a_flash_data = {
+        .width          = 2,
+};
+
+static struct resource edb9302a_flash_resource = {
+        .start          = 0x60000000,
+        .end            = 0x60ffffff,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device edb9302a_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &edb9302a_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &edb9302a_flash_resource,
+};
+
+static struct ep93xx_eth_data edb9302a_eth_data = {
+        .phy_id                 = 1,
+};
+
+static struct resource edb9302a_eth_resource[] = {
+        {
+                .start  = EP93XX_ETHERNET_PHYS_BASE,
+                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_EP93XX_ETHERNET,
+                .end    = IRQ_EP93XX_ETHERNET,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device edb9302a_eth_device = {
+        .name           = "ep93xx-eth",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &edb9302a_eth_data,
+        },
+        .num_resources  = 2,
+        .resource       = edb9302a_eth_resource,
+};
+
+static void __init edb9302a_init_machine(void)
+{
+        ep93xx_init_devices();
+        platform_device_register(&edb9302a_flash);
+
+        memcpy(edb9302a_eth_data.dev_addr,
+                (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
+        platform_device_register(&edb9302a_eth_device);
+}
+
+MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
+        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0xc0000100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = edb9302a_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-iop13xx/Kconfig b/arch/arm/mach-iop13xx/Kconfig
new file mode 100644
index 000000000000..40c2d689f2eb
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Kconfig
@@ -0,0 +1,20 @@
+if ARCH_IOP13XX
+
+menu "IOP13XX Implementation Options"
+
+comment "IOP13XX Platform Support"
+
+config MACH_IQ81340SC
+        bool "Enable IQ81340SC Hardware Support"
+        help
+          Say Y here if you want to support running on the Intel IQ81340SC
+          evaluation kit.
+
+config MACH_IQ81340MC
+        bool "Enable IQ81340MC Hardware Support"
+        help
+          Say Y here if you want to support running on the Intel IQ81340MC
+          evaluation kit.
+
+endmenu
+endif
diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile
new file mode 100644
index 000000000000..c3d6c08f2d4c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Makefile
@@ -0,0 +1,12 @@
+obj-y                   :=
+obj-m                   :=
+obj-n                   :=
+obj-                    :=
+
+obj-$(CONFIG_ARCH_IOP13XX) += setup.o
+obj-$(CONFIG_ARCH_IOP13XX) += irq.o
+obj-$(CONFIG_ARCH_IOP13XX) += time.o
+obj-$(CONFIG_ARCH_IOP13XX) += pci.o
+obj-$(CONFIG_ARCH_IOP13XX) += io.o
+obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
+obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o
diff --git a/arch/arm/mach-iop13xx/Makefile.boot b/arch/arm/mach-iop13xx/Makefile.boot
new file mode 100644
index 000000000000..0b0e19fdfe6c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
new file mode 100644
index 000000000000..fbf9f88e46ea
--- /dev/null
+++ b/arch/arm/mach-iop13xx/io.c
@@ -0,0 +1,93 @@
+/*
+ * iop13xx custom ioremap implementation
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+
+void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
+        unsigned long flags)
+{
+        void __iomem * retval;
+
+        switch (cookie) {
+        case IOP13XX_PCIX_LOWER_MEM_RA ... IOP13XX_PCIX_UPPER_MEM_RA:
+                if (unlikely(!iop13xx_atux_mem_base))
+                        retval = NULL;
+                else
+                        retval = (void *)(iop13xx_atux_mem_base +
+                                 (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
+                break;
+        case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
+                if (unlikely(!iop13xx_atue_mem_base))
+                        retval = NULL;
+                else
+                        retval = (void *)(iop13xx_atue_mem_base +
+                                 (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
+                break;
+        case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
+                retval = __ioremap(IOP13XX_PBI_LOWER_MEM_PA +
+                                  (cookie - IOP13XX_PBI_LOWER_MEM_RA),
+                                  size, flags);
+                break;
+        case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
+                retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
+                break;
+        case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
+                retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
+                break;
+        case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
+                retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
+                break;
+        default:
+                retval = __ioremap(cookie, size, flags);
+        }
+
+        return retval;
+}
+EXPORT_SYMBOL(__iop13xx_ioremap);
+
+void __iop13xx_iounmap(void __iomem *addr)
+{
+        extern void __iounmap(volatile void __iomem *addr);
+
+        if (iop13xx_atue_mem_base)
+                if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
+                    addr < (void __iomem *) (iop13xx_atue_mem_base +
+                                             iop13xx_atue_mem_size))
+                    goto skip;
+
+        if (iop13xx_atux_mem_base)
+                if (addr >= (void __iomem *) iop13xx_atux_mem_base &&
+                    addr < (void __iomem *) (iop13xx_atux_mem_base +
+                                             iop13xx_atux_mem_size))
+                    goto skip;
+
+        switch ((u32) addr) {
+        case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
+        case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
+        case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
+                goto skip;
+        }
+        __iounmap(addr);
+
+skip:
+        return;
+}
+EXPORT_SYMBOL(__iop13xx_iounmap);
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
new file mode 100644
index 000000000000..ee595786cd22
--- /dev/null
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -0,0 +1,98 @@
+/*
+ * iq81340mc board support
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#include <linux/pci.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/arch/pci.h>
+#include <asm/mach/time.h>
+
+extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
+
+static int __init
+iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+{
+        switch (idsel) {
+        case 1:
+                switch (pin) {
+                case 1: return ATUX_INTB;
+                case 2: return ATUX_INTC;
+                case 3: return ATUX_INTD;
+                case 4: return ATUX_INTA;
+                default: return -1;
+                }
+        case 2:
+                switch (pin) {
+                case 1: return ATUX_INTC;
+                case 2: return ATUX_INTD;
+                case 3: return ATUX_INTC;
+                case 4: return ATUX_INTD;
+                default: return -1;
+                }
+        default: return -1;
+        }
+}
+
+static struct hw_pci iq81340mc_pci __initdata = {
+        .swizzle        = pci_std_swizzle,
+        .nr_controllers = 0,
+        .setup          = iop13xx_pci_setup,
+        .map_irq        = iq81340mc_pcix_map_irq,
+        .scan           = iop13xx_scan_bus,
+        .preinit        = iop13xx_pci_init,
+};
+
+static int __init iq81340mc_pci_init(void)
+{
+        iop13xx_atu_select(&iq81340mc_pci);
+        pci_common_init(&iq81340mc_pci);
+        iop13xx_map_pci_memory();
+
+        return 0;
+}
+
+static void __init iq81340mc_init(void)
+{
+        iop13xx_platform_init();
+        iq81340mc_pci_init();
+}
+
+static void __init iq81340mc_timer_init(void)
+{
+        iop13xx_init_time(400000000);
+}
+
+static struct sys_timer iq81340mc_timer = {
+       .init       = iq81340mc_timer_init,
+       .offset     = iop13xx_gettimeoffset,
+};
+
+MACHINE_START(IQ81340MC, "Intel IQ81340MC")
+        /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
+        .phys_io        = PHYS_IO,
+        .io_pg_offst    = IO_PG_OFFSET,
+        .map_io         = iop13xx_map_io,
+        .init_irq       = iop13xx_init_irq,
+        .timer          = &iq81340mc_timer,
+        .boot_params    = BOOT_PARAM_OFFSET,
+        .init_machine   = iq81340mc_init,
+MACHINE_END
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
new file mode 100644
index 000000000000..6677e14b61bf
--- /dev/null
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -0,0 +1,100 @@
+/*
+ * iq81340sc board support
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#include <linux/pci.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/arch/pci.h>
+#include <asm/mach/time.h>
+
+extern int init_atu;
+
+static int __init
+iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+{
+        WARN_ON(idsel < 1 || idsel > 2);
+
+        switch (idsel) {
+        case 1:
+                switch (pin) {
+                case 1: return ATUX_INTB;
+                case 2: return ATUX_INTC;
+                case 3: return ATUX_INTD;
+                case 4: return ATUX_INTA;
+                default: return -1;
+                }
+        case 2:
+                switch (pin) {
+                case 1: return ATUX_INTC;
+                case 2: return ATUX_INTC;
+                case 3: return ATUX_INTC;
+                case 4: return ATUX_INTC;
+                default: return -1;
+                }
+        default: return -1;
+        }
+}
+
+static struct hw_pci iq81340sc_pci __initdata = {
+        .swizzle        = pci_std_swizzle,
+        .nr_controllers = 0,
+        .setup          = iop13xx_pci_setup,
+        .scan           = iop13xx_scan_bus,
+        .map_irq        = iq81340sc_atux_map_irq,
+        .preinit        = iop13xx_pci_init
+};
+
+static int __init iq81340sc_pci_init(void)
+{
+        iop13xx_atu_select(&iq81340sc_pci);
+        pci_common_init(&iq81340sc_pci);
+        iop13xx_map_pci_memory();
+
+        return 0;
+}
+
+static void __init iq81340sc_init(void)
+{
+        iop13xx_platform_init();
+        iq81340sc_pci_init();
+}
+
+static void __init iq81340sc_timer_init(void)
+{
+        iop13xx_init_time(400000000);
+}
+
+static struct sys_timer iq81340sc_timer = {
+       .init       = iq81340sc_timer_init,
+       .offset     = iop13xx_gettimeoffset,
+};
+
+MACHINE_START(IQ81340SC, "Intel IQ81340SC")
+        /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
+        .phys_io        = PHYS_IO,
+        .io_pg_offst    = IO_PG_OFFSET,
+        .map_io         = iop13xx_map_io,
+        .init_irq       = iop13xx_init_irq,
+        .timer          = &iq81340sc_timer,
+        .boot_params    = BOOT_PARAM_OFFSET,
+        .init_machine   = iq81340sc_init,
+MACHINE_END
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
new file mode 100644
index 000000000000..c4d9c8c5579c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -0,0 +1,286 @@
+/*
+ * iop13xx IRQ handling / support functions
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/sysctl.h>
+#include <asm/uaccess.h>
+#include <asm/mach/irq.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/arch/irqs.h>
+
+/* INTCTL0 CP6 R0 Page 4
+ */
+static inline u32 read_intctl_0(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
+        return val;
+}
+static inline void write_intctl_0(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
+}
+
+/* INTCTL1 CP6 R1 Page 4
+ */
+static inline u32 read_intctl_1(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
+        return val;
+}
+static inline void write_intctl_1(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
+}
+
+/* INTCTL2 CP6 R2 Page 4
+ */
+static inline u32 read_intctl_2(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
+        return val;
+}
+static inline void write_intctl_2(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
+}
+
+/* INTCTL3 CP6 R3 Page 4
+ */
+static inline u32 read_intctl_3(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
+        return val;
+}
+static inline void write_intctl_3(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
+}
+
+/* INTSTR0 CP6 R0 Page 5
+ */
+static inline u32 read_intstr_0(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
+        return val;
+}
+static inline void write_intstr_0(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
+}
+
+/* INTSTR1 CP6 R1 Page 5
+ */
+static inline u32 read_intstr_1(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
+        return val;
+}
+static void write_intstr_1(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
+}
+
+/* INTSTR2 CP6 R2 Page 5
+ */
+static inline u32 read_intstr_2(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
+        return val;
+}
+static void write_intstr_2(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
+}
+
+/* INTSTR3 CP6 R3 Page 5
+ */
+static inline u32 read_intstr_3(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
+        return val;
+}
+static void write_intstr_3(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
+}
+
+/* INTBASE CP6 R0 Page 2
+ */
+static inline u32 read_intbase(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
+        return val;
+}
+static void write_intbase(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
+}
+
+/* INTSIZE CP6 R2 Page 2
+ */
+static inline u32 read_intsize(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
+        return val;
+}
+static void write_intsize(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
+}
+
+/* 0 = Interrupt Masked and 1 = Interrupt not masked */
+static void
+iop13xx_irq_mask0 (unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
+        iop13xx_cp6_restore(cp_flags);
+}
+
+static void
+iop13xx_irq_mask1 (unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
+        iop13xx_cp6_restore(cp_flags);
+}
+
+static void
+iop13xx_irq_mask2 (unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
+        iop13xx_cp6_restore(cp_flags);
+}
+
+static void
+iop13xx_irq_mask3 (unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
+        iop13xx_cp6_restore(cp_flags);
+}
+
+static void
+iop13xx_irq_unmask0(unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
+        iop13xx_cp6_restore(cp_flags);
+}
+
+static void
+iop13xx_irq_unmask1(unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
+        iop13xx_cp6_restore(cp_flags);
+}
+
+static void
+iop13xx_irq_unmask2(unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
+        iop13xx_cp6_restore(cp_flags);
+}
+
+static void
+iop13xx_irq_unmask3(unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
+        iop13xx_cp6_restore(cp_flags);
+}
+
+static struct irqchip iop13xx_irqchip0 = {
+        .ack    = iop13xx_irq_mask0,
+        .mask   = iop13xx_irq_mask0,
+        .unmask = iop13xx_irq_unmask0,
+};
+
+static struct irqchip iop13xx_irqchip1 = {
+        .ack    = iop13xx_irq_mask1,
+        .mask   = iop13xx_irq_mask1,
+        .unmask = iop13xx_irq_unmask1,
+};
+
+static struct irqchip iop13xx_irqchip2 = {
+        .ack    = iop13xx_irq_mask2,
+        .mask   = iop13xx_irq_mask2,
+        .unmask = iop13xx_irq_unmask2,
+};
+
+static struct irqchip iop13xx_irqchip3 = {
+        .ack    = iop13xx_irq_mask3,
+        .mask   = iop13xx_irq_mask3,
+        .unmask = iop13xx_irq_unmask3,
+};
+
+void __init iop13xx_init_irq(void)
+{
+        unsigned int i;
+
+        u32 cp_flags = iop13xx_cp6_save();
+
+        /* disable all interrupts */
+        write_intctl_0(0);
+        write_intctl_1(0);
+        write_intctl_2(0);
+        write_intctl_3(0);
+
+        /* treat all as IRQ */
+        write_intstr_0(0);
+        write_intstr_1(0);
+        write_intstr_2(0);
+        write_intstr_3(0);
+
+        /* initialize the interrupt vector generator */
+        write_intbase(INTBASE);
+        write_intsize(INTSIZE_4);
+
+        for(i = 0; i < NR_IOP13XX_IRQS; i++) {
+                if (i < 32)
+                        set_irq_chip(i, &iop13xx_irqchip0);
+                else if (i < 64)
+                        set_irq_chip(i, &iop13xx_irqchip1);
+                else if (i < 96)
+                        set_irq_chip(i, &iop13xx_irqchip2);
+                else
+                        set_irq_chip(i, &iop13xx_irqchip3);
+
+                set_irq_handler(i, do_level_IRQ);
+                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+        }
+
+        iop13xx_cp6_restore(cp_flags);
+}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
new file mode 100644
index 000000000000..89ec70ea3187
--- /dev/null
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -0,0 +1,1113 @@
+/*
+ * iop13xx PCI support
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+
+#include <linux/pci.h>
+#include <linux/delay.h>
+
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/sizes.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/pci.h>
+
+#define IOP13XX_PCI_DEBUG 0
+#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
+
+u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
+u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
+static struct pci_bus *pci_bus_atux = 0;
+static struct pci_bus *pci_bus_atue = 0;
+u32 iop13xx_atue_mem_base;
+u32 iop13xx_atux_mem_base;
+size_t iop13xx_atue_mem_size;
+size_t iop13xx_atux_mem_size;
+unsigned long iop13xx_pcibios_min_io = 0;
+unsigned long iop13xx_pcibios_min_mem = 0;
+
+EXPORT_SYMBOL(iop13xx_atue_mem_base);
+EXPORT_SYMBOL(iop13xx_atux_mem_base);
+EXPORT_SYMBOL(iop13xx_atue_mem_size);
+EXPORT_SYMBOL(iop13xx_atux_mem_size);
+
+int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
+static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
+                                                 access */
+
+/* Scan the initialized busses and ioremap the requested memory range
+ */
+void iop13xx_map_pci_memory(void)
+{
+        int atu;
+        struct pci_bus *bus;
+        struct pci_dev *dev;
+        resource_size_t end = 0;
+
+        for (atu = 0; atu < 2; atu++) {
+                bus = atu ? pci_bus_atue : pci_bus_atux;
+                if (bus) {
+                        list_for_each_entry(dev, &bus->devices, bus_list) {
+                                int i;
+                                int max = 7;
+
+                                if (dev->subordinate)
+                                        max = DEVICE_COUNT_RESOURCE;
+
+                                for (i = 0; i < max; i++) {
+                                        struct resource *res = &dev->resource[i];
+                                        if (res->flags & IORESOURCE_MEM)
+                                                end = max(res->end, end);
+                                }
+                        }
+
+                        switch(atu) {
+                        case 0:
+                                iop13xx_atux_mem_size =
+                                        (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
+
+                                /* 16MB align the request */
+                                if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
+                                        iop13xx_atux_mem_size &= ~(SZ_16M - 1);
+                                        iop13xx_atux_mem_size += SZ_16M;
+                                }
+
+                                if (end) {
+                                        iop13xx_atux_mem_base =
+                                        (u32) __ioremap_pfn(
+                                        __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
+                                        , 0, iop13xx_atux_mem_size, 0);
+                                        if (!iop13xx_atux_mem_base) {
+                                                printk("%s: atux allocation "
+                                                       "failed\n", __FUNCTION__);
+                                                BUG();
+                                        }
+                                } else
+                                        iop13xx_atux_mem_size = 0;
+                                PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                                __FUNCTION__, atu, iop13xx_atux_mem_size,
+                                iop13xx_atux_mem_base);
+                                break;
+                        case 1:
+                                iop13xx_atue_mem_size =
+                                        (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
+
+                                /* 16MB align the request */
+                                if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
+                                        iop13xx_atue_mem_size &= ~(SZ_16M - 1);
+                                        iop13xx_atue_mem_size += SZ_16M;
+                                }
+
+                                if (end) {
+                                        iop13xx_atue_mem_base =
+                                        (u32) __ioremap_pfn(
+                                        __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
+                                        , 0, iop13xx_atue_mem_size, 0);
+                                        if (!iop13xx_atue_mem_base) {
+                                                printk("%s: atue allocation "
+                                                       "failed\n", __FUNCTION__);
+                                                BUG();
+                                        }
+                                } else
+                                        iop13xx_atue_mem_size = 0;
+                                PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                                __FUNCTION__, atu, iop13xx_atue_mem_size,
+                                iop13xx_atue_mem_base);
+                                break;
+                        }
+
+                        printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
+                        atu ? "ATUE" : "ATUX",
+                        (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
+                        SZ_1M,
+                        atu ? IOP13XX_PCIE_LOWER_MEM_RA :
+                        IOP13XX_PCIX_LOWER_MEM_RA,
+                        atu ? iop13xx_atue_mem_base :
+                        iop13xx_atux_mem_base);
+                        end = 0;
+                }
+
+        }
+}
+
+static inline int iop13xx_atu_function(int atu)
+{
+        int func = 0;
+        /* the function number depends on the value of the
+         * IOP13XX_INTERFACE_SEL_PCIX reset strap
+         * see C-Spec section 3.17
+         */
+        switch(atu) {
+        case IOP13XX_INIT_ATU_ATUX:
+                if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
+                        func = 5;
+                else
+                        func = 0;
+                break;
+        case IOP13XX_INIT_ATU_ATUE:
+                if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
+                        func = 0;
+                else
+                        func = 5;
+                break;
+        default:
+                BUG();
+        }
+
+        return func;
+}
+
+/* iop13xx_atux_cfg_address - format a configuration address for atux
+ * @bus: Target bus to access
+ * @devfn: Combined device number and function number
+ * @where: Desired register's address offset
+ *
+ * Convert the parameters to a configuration address formatted
+ * according the PCI-X 2.0 specification
+ */
+static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
+{
+        struct pci_sys_data *sys = bus->sysdata;
+        u32 addr;
+
+        if (sys->busnr == bus->number)
+                addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
+        else
+                addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
+
+        addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
+        addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
+
+        return addr;
+}
+
+/* iop13xx_atue_cfg_address - format a configuration address for atue
+ * @bus: Target bus to access
+ * @devfn: Combined device number and function number
+ * @where: Desired register's address offset
+ *
+ * Convert the parameters to an address usable by the ATUE_OCCAR
+ */
+static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
+{
+        struct pci_sys_data *sys = bus->sysdata;
+        u32 addr;
+
+        PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
+                bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
+        addr = ((u32) bus->number)     << IOP13XX_ATUE_OCCAR_BUS_NUM |
+                   ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
+                   ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
+                   (where & ~0x3);
+
+        if (sys->busnr != bus->number)
+                addr |= 1; /* type 1 access */
+
+        return addr;
+}
+
+/* This routine checks the status of the last configuration cycle.  If an error
+ * was detected it returns >0, else it returns a 0.  The errors being checked
+ * are parity, master abort, target abort (master and target).  These types of
+ * errors occure during a config cycle where there is no device, like during
+ * the discovery stage.
+ */
+static int iop13xx_atux_pci_status(int clear)
+{
+        unsigned int status;
+        int err = 0;
+
+        /*
+         * Check the status registers.
+         */
+        status = __raw_readw(IOP13XX_ATUX_ATUSR);
+        if (status & IOP_PCI_STATUS_ERROR)
+        {
+                PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
+                if(clear)
+                        __raw_writew(status & IOP_PCI_STATUS_ERROR,
+                                IOP13XX_ATUX_ATUSR);
+                err = 1;
+        }
+        status = __raw_readl(IOP13XX_ATUX_ATUISR);
+        if (status & IOP13XX_ATUX_ATUISR_ERROR)
+        {
+                PRINTK("\t\t\tPCI error interrupt:  ATUISR %#08x", status);
+                if(clear)
+                        __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
+                                IOP13XX_ATUX_ATUISR);
+                err = 1;
+        }
+        return err;
+}
+
+/* Simply write the address register and read the configuration
+ * data.  Note that the data dependency on %0 encourages an abort
+ * to be detected before we return.
+ */
+static inline u32 iop13xx_atux_read(unsigned long addr)
+{
+        u32 val;
+
+        __asm__ __volatile__(
+                "str    %1, [%2]\n\t"
+                "ldr    %0, [%3]\n\t"
+                "mov    %0, %0\n\t"
+                : "=r" (val)
+                : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
+
+        return val;
+}
+
+/* The read routines must check the error status of the last configuration
+ * cycle.  If there was an error, the routine returns all hex f's.
+ */
+static int
+iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+                int size, u32 *value)
+{
+        unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
+        u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
+
+        if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
+                __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
+                        IOP13XX_XBG_BECSR);
+                val = 0xffffffff;
+        }
+
+        *value = val;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+                int size, u32 value)
+{
+        unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
+        u32 val;
+
+        if (size != 4) {
+                val = iop13xx_atux_read(addr);
+                if (!iop13xx_atux_pci_status(1) == 0)
+                        return PCIBIOS_SUCCESSFUL;
+
+                where = (where & 3) * 8;
+
+                if (size == 1)
+                        val &= ~(0xff << where);
+                else
+                        val &= ~(0xffff << where);
+
+                __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
+        } else {
+                __raw_writel(addr, IOP13XX_ATUX_OCCAR);
+                __raw_writel(value, IOP13XX_ATUX_OCCDR);
+        }
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops iop13xx_atux_ops = {
+        .read   = iop13xx_atux_read_config,
+        .write  = iop13xx_atux_write_config,
+};
+
+/* This routine checks the status of the last configuration cycle.  If an error
+ * was detected it returns >0, else it returns a 0.  The errors being checked
+ * are parity, master abort, target abort (master and target).  These types of
+ * errors occure during a config cycle where there is no device, like during
+ * the discovery stage.
+ */
+static int iop13xx_atue_pci_status(int clear)
+{
+        unsigned int status;
+        int err = 0;
+
+        /*
+         * Check the status registers.
+         */
+
+        /* standard pci status register */
+        status = __raw_readw(IOP13XX_ATUE_ATUSR);
+        if (status & IOP_PCI_STATUS_ERROR) {
+                PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
+                if(clear)
+                        __raw_writew(status & IOP_PCI_STATUS_ERROR,
+                                IOP13XX_ATUE_ATUSR);
+                err++;
+        }
+
+        /* check the normal status bits in the ATUISR */
+        status = __raw_readl(IOP13XX_ATUE_ATUISR);
+        if (status & IOP13XX_ATUE_ATUISR_ERROR) {
+                PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
+                if (clear)
+                        __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
+                                IOP13XX_ATUE_ATUISR);
+                err++;
+
+                /* check the PCI-E status if the ATUISR reports an interface error */
+                if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
+                        /* get the unmasked errors */
+                        status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
+                                        ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
+
+                        if (status) {
+                                PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
+                                        __raw_readl(IOP13XX_ATUE_PIE_STS));
+                                err++;
+                        } else {
+                                PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
+                                        __raw_readl(IOP13XX_ATUE_PIE_STS));
+                                PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
+                                        __raw_readl(IOP13XX_ATUE_PIE_MSK));
+                                BUG();
+                        }
+
+                        if(clear)
+                                __raw_writel(status, IOP13XX_ATUE_PIE_STS);
+                }
+        }
+
+        return err;
+}
+
+static inline int __init
+iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+{
+        WARN_ON(idsel != 0);
+
+        switch (pin) {
+        case 1: return ATUE_INTA;
+        case 2: return ATUE_INTB;
+        case 3: return ATUE_INTC;
+        case 4: return ATUE_INTD;
+        default: return -1;
+        }
+}
+
+static inline u32 iop13xx_atue_read(unsigned long addr)
+{
+        u32 val;
+
+        __raw_writel(addr, IOP13XX_ATUE_OCCAR);
+        val = __raw_readl(IOP13XX_ATUE_OCCDR);
+
+        rmb();
+
+        return val;
+}
+
+/* The read routines must check the error status of the last configuration
+ * cycle.  If there was an error, the routine returns all hex f's.
+ */
+static int
+iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+                int size, u32 *value)
+{
+        u32 val;
+        unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
+
+        /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
+        if (!PCI_SLOT(devfn) || (addr & 1)) {
+                val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
+                if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
+                        __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
+                                IOP13XX_XBG_BECSR);
+                        val = 0xffffffff;
+                }
+
+                PRINTK("addr=%#0lx, val=%#010x", addr, val);
+        } else
+                val = 0xffffffff;
+
+        *value = val;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+                int size, u32 value)
+{
+        unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
+        u32 val;
+
+        if (size != 4) {
+                val = iop13xx_atue_read(addr);
+                if (!iop13xx_atue_pci_status(1) == 0)
+                        return PCIBIOS_SUCCESSFUL;
+
+                where = (where & 3) * 8;
+
+                if (size == 1)
+                        val &= ~(0xff << where);
+                else
+                        val &= ~(0xffff << where);
+
+                __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
+        } else {
+                __raw_writel(addr, IOP13XX_ATUE_OCCAR);
+                __raw_writel(value, IOP13XX_ATUE_OCCDR);
+        }
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops iop13xx_atue_ops = {
+        .read   = iop13xx_atue_read_config,
+        .write  = iop13xx_atue_write_config,
+};
+
+/* When a PCI device does not exist during config cycles, the XScale gets a
+ * bus error instead of returning 0xffffffff.  We can't rely on the ATU status
+ * bits to tell us that it was indeed a configuration cycle that caused this
+ * error especially in the case when the ATUE link is down.  Instead we rely
+ * on data from the south XSI bridge to validate the abort
+ */
+int
+iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+{
+        PRINTK("Data abort: address = 0x%08lx "
+                    "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
+                addr, fsr, regs->ARM_pc, regs->ARM_lr);
+
+        PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
+        PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
+        PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
+
+        /*  If it was an imprecise abort, then we need to correct the
+         *  return address to be _after_ the instruction.
+         */
+        if (fsr & (1 << 10))
+                regs->ARM_pc += 4;
+
+        if (is_atue_occdr_error() || is_atux_occdr_error())
+                return 0;
+        else
+                return 1;
+}
+
+/* Scan an IOP13XX PCI bus.  nr selects which ATU we use.
+ */
+struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        int which_atu;
+        struct pci_bus *bus = NULL;
+
+        switch (init_atu) {
+        case IOP13XX_INIT_ATU_ATUX:
+                which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
+                break;
+        case IOP13XX_INIT_ATU_ATUE:
+                which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
+                break;
+        case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
+                which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
+                break;
+        default:
+                which_atu = 0;
+        }
+
+        if (!which_atu) {
+                BUG();
+                return NULL;
+        }
+
+        switch (which_atu) {
+        case IOP13XX_INIT_ATU_ATUX:
+                if (time_after_eq(jiffies + msecs_to_jiffies(1000),
+                                  atux_trhfa_timeout))  /* ensure not wrap */
+                        while(time_before(jiffies, atux_trhfa_timeout))
+                                udelay(100);
+
+                bus = pci_bus_atux = pci_scan_bus(sys->busnr,
+                                                  &iop13xx_atux_ops,
+                                                  sys);
+                break;
+        case IOP13XX_INIT_ATU_ATUE:
+                bus = pci_bus_atue = pci_scan_bus(sys->busnr,
+                                                  &iop13xx_atue_ops,
+                                                  sys);
+                break;
+        }
+
+        return bus;
+}
+
+/* This function is called from iop13xx_pci_init() after assigning valid
+ * values to iop13xx_atue_pmmr_offset.  This is the location for common
+ * setup of ATUE for all IOP13XX implementations.
+ */
+void __init iop13xx_atue_setup(void)
+{
+        int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
+        u32 reg_val;
+
+        /* BAR 1 (1:1 mapping with Physical RAM) */
+        /* Set limit and enable */
+        __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
+                        IOP13XX_ATUE_IALR1);
+        __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
+
+        /* Set base at the top of the reserved address space */
+        __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
+                        PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
+
+        /* 1:1 mapping with physical ram
+         * (leave big endian byte swap disabled)
+         */
+         __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
+         __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
+
+        /* Outbound window 1 (PCIX/PCIE memory window) */
+        /* 32 bit Address Space */
+        __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
+        /* PA[35:32] */
+        __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
+                        (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
+                        IOP13XX_ATUE_OUMBAR1);
+
+        /* Setup the I/O Bar
+         * A[35-16] in 31-12
+         */
+        __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
+                IOP13XX_ATUE_OIOBAR);
+        __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
+
+        /* clear startup errors */
+        iop13xx_atue_pci_status(1);
+
+        /* OIOBAR function number
+         */
+        reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
+        reg_val &= ~0x7;
+        reg_val |= func;
+        __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
+
+        /* OUMBAR function numbers
+         */
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
+
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
+
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
+
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
+
+        /* Enable inbound and outbound cycles
+         */
+        reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
+        reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+                        PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
+        __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
+
+        reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
+        reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
+                        IOP13XX_ATUE_ATUCR_IVM;
+        __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
+}
+
+void __init iop13xx_atue_disable(void)
+{
+        u32 reg_val;
+
+        __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
+        __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
+
+        /* wait for cycles to quiesce */
+        while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
+                                             IOP13XX_ATUE_PCSR_IN_Q_BUSY |
+                                             IOP13XX_ATUE_PCSR_LLRB_BUSY))
+                cpu_relax();
+
+        /* BAR 0 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
+        __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
+        __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
+        __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
+        __raw_writel(0x0, IOP13XX_ATUE_IALR0);
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
+        reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
+
+        /* BAR 1 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
+        __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
+        __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
+        __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
+        __raw_writel(0x0, IOP13XX_ATUE_IALR1);
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
+        reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
+
+        /* BAR 2 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
+        __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
+        __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
+        __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
+        __raw_writel(0x0, IOP13XX_ATUE_IALR2);
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
+        reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
+
+        /* BAR 3 ( Disabled ) */
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
+        reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
+
+        /* Setup the I/O Bar
+         * A[35-16] in 31-12
+         */
+        __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
+                        IOP13XX_ATUE_OIOBAR);
+        __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
+}
+
+/* This function is called from iop13xx_pci_init() after assigning valid
+ * values to iop13xx_atux_pmmr_offset.  This is the location for common
+ * setup of ATUX for all IOP13XX implementations.
+ */
+void __init iop13xx_atux_setup(void)
+{
+        u32 reg_val;
+        int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
+
+        /* Take PCI-X bus out of reset if bootloader hasn't already.
+         * According to spec, we should wait for 2^25 PCI clocks to meet
+         * the PCI timing parameter Trhfa (RST# high to first access).
+         * This is rarely necessary and often ignored.
+         */
+        reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
+        if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
+                int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
+                msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
+                __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
+                                IOP13XX_ATUX_PCSR);
+                atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
+        }
+        else
+                atux_trhfa_timeout = jiffies;
+
+        /* BAR 1 (1:1 mapping with Physical RAM) */
+        /* Set limit and enable */
+        __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
+                        IOP13XX_ATUX_IALR1);
+        __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
+
+        /* Set base at the top of the reserved address space */
+        __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
+                        PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
+
+        /* 1:1 mapping with physical ram
+         * (leave big endian byte swap disabled)
+         */
+        __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
+        __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
+
+        /* Outbound window 1 (PCIX/PCIE memory window) */
+        /* 32 bit Address Space */
+        __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
+        /* PA[35:32] */
+        __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
+                        IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
+                        IOP13XX_ATUX_OUMBAR1);
+
+        /* Setup the I/O Bar
+         * A[35-16] in 31-12
+         */
+        __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
+                IOP13XX_ATUX_OIOBAR);
+        __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
+
+        /* clear startup errors */
+        iop13xx_atux_pci_status(1);
+
+        /* OIOBAR function number
+         */
+        reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
+        reg_val &= ~0x7;
+        reg_val |= func;
+        __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
+
+        /* OUMBAR function numbers
+         */
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
+
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
+
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
+
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
+
+        /* Enable inbound and outbound cycles
+         */
+        reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
+        reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+                        PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
+        __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
+
+        reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
+        reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
+        __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
+}
+
+void __init iop13xx_atux_disable(void)
+{
+        u32 reg_val;
+
+        __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
+        __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
+
+        /* wait for cycles to quiesce */
+        while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
+                                     IOP13XX_ATUX_PCSR_IN_Q_BUSY))
+                cpu_relax();
+
+        /* BAR 0 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
+        __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
+        __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
+        __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
+        __raw_writel(0x0, IOP13XX_ATUX_IALR0);
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
+        reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
+
+        /* BAR 1 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
+        __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
+        __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
+        __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
+        __raw_writel(0x0, IOP13XX_ATUX_IALR1);
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
+        reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
+
+        /* BAR 2 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
+        __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
+        __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
+        __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
+        __raw_writel(0x0, IOP13XX_ATUX_IALR2);
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
+        reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
+
+        /* BAR 3 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
+        __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
+        __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
+        __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
+        __raw_writel(0x0, IOP13XX_ATUX_IALR3);
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
+        reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
+
+        /* Setup the I/O Bar
+        * A[35-16] in 31-12
+        */
+        __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
+                        IOP13XX_ATUX_OIOBAR);
+        __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
+}
+
+void __init iop13xx_set_atu_mmr_bases(void)
+{
+        /* Based on ESSR0, determine the ATU X/E offsets */
+        switch(__raw_readl(IOP13XX_ESSR0) &
+                (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
+        /* both asserted */
+        case 0:
+                iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
+                iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
+                break;
+        /* IOP13XX_CONTROLLER_ONLY = deasserted
+         * IOP13XX_INTERFACE_SEL_PCIX = asserted
+         */
+        case IOP13XX_CONTROLLER_ONLY:
+                iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
+                iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
+                break;
+        /* IOP13XX_CONTROLLER_ONLY = asserted
+         * IOP13XX_INTERFACE_SEL_PCIX = deasserted
+         */
+        case IOP13XX_INTERFACE_SEL_PCIX:
+                iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
+                iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
+                break;
+        /* both deasserted */
+        case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
+                iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
+                iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
+                break;
+        default:
+                BUG();
+        }
+}
+
+void __init iop13xx_atu_select(struct hw_pci *plat_pci)
+{
+        int i;
+
+        /* set system defaults
+         * note: if "iop13xx_init_atu=" is specified this autodetect
+         * sequence will be bypassed
+         */
+        if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
+                /* check for single/dual interface */
+                if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
+                        /* ATUE must be present check the device id
+                         * to see if ATUX is present.
+                         */
+                        init_atu |= IOP13XX_INIT_ATU_ATUE;
+                        switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
+                        case 0x70:
+                        case 0x80:
+                        case 0xc0:
+                                init_atu |= IOP13XX_INIT_ATU_ATUX;
+                                break;
+                        }
+                } else {
+                        /* ATUX must be present check the device id
+                         * to see if ATUE is present.
+                         */
+                        init_atu |= IOP13XX_INIT_ATU_ATUX;
+                        switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
+                        case 0x70:
+                        case 0x80:
+                        case 0xc0:
+                                init_atu |= IOP13XX_INIT_ATU_ATUE;
+                                break;
+                        }
+                }
+
+                /* check central resource and root complex capability */
+                if (init_atu & IOP13XX_INIT_ATU_ATUX)
+                        if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
+                                IOP13XX_ATUX_PCSR_CENTRAL_RES))
+                                init_atu &= ~IOP13XX_INIT_ATU_ATUX;
+
+                if (init_atu & IOP13XX_INIT_ATU_ATUE)
+                        if (__raw_readl(IOP13XX_ATUE_PCSR) &
+                                IOP13XX_ATUE_PCSR_END_POINT)
+                                init_atu &= ~IOP13XX_INIT_ATU_ATUE;
+        }
+
+        for (i = 0; i < 2; i++) {
+                if((init_atu & (1 << i)) == (1 << i))
+                        plat_pci->nr_controllers++;
+        }
+}
+
+void __init iop13xx_pci_init(void)
+{
+        /* clear pre-existing south bridge errors */
+        __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
+
+        /* Setup the Min Address for PCI memory... */
+        iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
+
+        /* if Linux is given control of an ATU
+         * clear out its prior configuration,
+         * otherwise do not touch the registers
+         */
+        if (init_atu & IOP13XX_INIT_ATU_ATUE) {
+                iop13xx_atue_disable();
+                iop13xx_atue_setup();
+        }
+
+        if (init_atu & IOP13XX_INIT_ATU_ATUX) {
+                iop13xx_atux_disable();
+                iop13xx_atux_setup();
+        }
+
+        hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS,
+                        "imprecise external abort");
+}
+
+/* intialize the pci memory space.  handle any combination of
+ * atue and atux enabled/disabled
+ */
+int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
+{
+        struct resource *res;
+        int which_atu;
+        u32 pcixsr, pcsr;
+
+        if (nr > 1)
+                return 0;
+
+        res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        if (!res)
+                panic("PCI: unable to alloc resources");
+
+        memset(res, 0, sizeof(struct resource) * 2);
+
+        /* 'nr' assumptions:
+         * ATUX is always 0
+         * ATUE is 1 when ATUX is also enabled
+         * ATUE is 0 when ATUX is disabled
+         */
+        switch(init_atu) {
+        case IOP13XX_INIT_ATU_ATUX:
+                which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
+                break;
+        case IOP13XX_INIT_ATU_ATUE:
+                which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
+                break;
+        case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
+                which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
+                break;
+        default:
+                which_atu = 0;
+        }
+
+        if (!which_atu)
+                return 0;
+
+        switch(which_atu) {
+        case IOP13XX_INIT_ATU_ATUX:
+                pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
+                pcixsr &= ~0xffff;
+                pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
+                          0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
+                          iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
+                                  << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
+                __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
+
+                res[0].start = IOP13XX_PCIX_LOWER_IO_PA;
+                res[0].end   = IOP13XX_PCIX_UPPER_IO_PA;
+                res[0].name  = "IQ81340 ATUX PCI I/O Space";
+                res[0].flags = IORESOURCE_IO;
+
+                res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
+                res[1].end   = IOP13XX_PCIX_UPPER_MEM_RA;
+                res[1].name  = "IQ81340 ATUX PCI Memory Space";
+                res[1].flags = IORESOURCE_MEM;
+                sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
+                sys->io_offset = IOP13XX_PCIX_IO_OFFSET;
+                break;
+        case IOP13XX_INIT_ATU_ATUE:
+                /* Note: the function number field in the PCSR is ro */
+                pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
+                pcsr &= ~(0xfff8 << 16);
+                pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
+                                0 << IOP13XX_ATUE_PCSR_DEV_NUM;
+
+                __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
+
+                res[0].start = IOP13XX_PCIE_LOWER_IO_PA;
+                res[0].end   = IOP13XX_PCIE_UPPER_IO_PA;
+                res[0].name  = "IQ81340 ATUE PCI I/O Space";
+                res[0].flags = IORESOURCE_IO;
+
+                res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
+                res[1].end   = IOP13XX_PCIE_UPPER_MEM_RA;
+                res[1].name  = "IQ81340 ATUE PCI Memory Space";
+                res[1].flags = IORESOURCE_MEM;
+                sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
+                sys->io_offset = IOP13XX_PCIE_IO_OFFSET;
+                sys->map_irq = iop13xx_pcie_map_irq;
+                break;
+        default:
+                return 0;
+        }
+
+        request_resource(&ioport_resource, &res[0]);
+        request_resource(&iomem_resource, &res[1]);
+
+        sys->resource[0] = &res[0];
+        sys->resource[1] = &res[1];
+        sys->resource[2] = NULL;
+
+        return 1;
+}
+
+u16 iop13xx_dev_id(void)
+{
+        if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
+                return __raw_readw(IOP13XX_ATUE_DID);
+        else
+                return __raw_readw(IOP13XX_ATUX_DID);
+}
+
+static int __init iop13xx_init_atu_setup(char *str)
+{
+        init_atu = IOP13XX_INIT_ATU_NONE;
+        if (str) {
+                while (*str != '\0') {
+                        switch (*str) {
+                        case 'x':
+                        case 'X':
+                                init_atu |= IOP13XX_INIT_ATU_ATUX;
+                                init_atu &= ~IOP13XX_INIT_ATU_NONE;
+                                break;
+                        case 'e':
+                        case 'E':
+                                init_atu |= IOP13XX_INIT_ATU_ATUE;
+                                init_atu &= ~IOP13XX_INIT_ATU_NONE;
+                                break;
+                        case ',':
+                        case '=':
+                                break;
+                        default:
+                                PRINTK("\"iop13xx_init_atu\" malformed at "
+                                            "character: \'%c\'", *str);
+                                *(str + 1) = '\0';
+                                init_atu = IOP13XX_INIT_ATU_DEFAULT;
+                        }
+                        str++;
+                }
+        }
+        return 1;
+}
+
+__setup("iop13xx_init_atu", iop13xx_init_atu_setup);
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
new file mode 100644
index 000000000000..3756d2ccb1a7
--- /dev/null
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -0,0 +1,406 @@
+/*
+ * iop13xx platform Initialization
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+
+#include <linux/serial_8250.h>
+#ifdef CONFIG_MTD_PHYSMAP
+#include <linux/mtd/physmap.h>
+#endif
+#include <asm/mach/map.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+
+#define IOP13XX_UART_XTAL 33334000
+#define IOP13XX_SETUP_DEBUG 0
+#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
+
+/* Standard IO mapping for all IOP13XX based systems
+ */
+static struct map_desc iop13xx_std_desc[] __initdata = {
+        {    /* mem mapped registers */
+                .virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
+                .pfn     = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
+                .length  = IOP13XX_PMMR_SIZE,
+                .type    = MT_DEVICE,
+        }, { /* PCIE IO space */
+                .virtual = IOP13XX_PCIE_LOWER_IO_VA,
+                .pfn     = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
+                .length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
+                .type    = MT_DEVICE,
+        }, { /* PCIX IO space */
+                .virtual = IOP13XX_PCIX_LOWER_IO_VA,
+                .pfn     = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
+                .length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
+                .type    = MT_DEVICE,
+        },
+};
+
+static struct resource iop13xx_uart0_resources[] = {
+        [0] = {
+                .start = IOP13XX_UART0_PHYS,
+                .end = IOP13XX_UART0_PHYS + 0x3f,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_UART0,
+                .end = IRQ_IOP13XX_UART0,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct resource iop13xx_uart1_resources[] = {
+        [0] = {
+                .start = IOP13XX_UART1_PHYS,
+                .end = IOP13XX_UART1_PHYS + 0x3f,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_UART1,
+                .end = IRQ_IOP13XX_UART1,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct plat_serial8250_port iop13xx_uart0_data[] = {
+        {
+       .membase     = (char*)(IOP13XX_UART0_VIRT),
+       .mapbase     = (IOP13XX_UART0_PHYS),
+       .irq         = IRQ_IOP13XX_UART0,
+       .uartclk     = IOP13XX_UART_XTAL,
+       .regshift    = 2,
+       .iotype      = UPIO_MEM,
+       .flags       = UPF_SKIP_TEST,
+        },
+        {  },
+};
+
+static struct plat_serial8250_port iop13xx_uart1_data[] = {
+        {
+       .membase     = (char*)(IOP13XX_UART1_VIRT),
+       .mapbase     = (IOP13XX_UART1_PHYS),
+       .irq         = IRQ_IOP13XX_UART1,
+       .uartclk     = IOP13XX_UART_XTAL,
+       .regshift    = 2,
+       .iotype      = UPIO_MEM,
+       .flags       = UPF_SKIP_TEST,
+        },
+        {  },
+};
+
+/* The ids are fixed up later in iop13xx_platform_init */
+static struct platform_device iop13xx_uart0 = {
+       .name = "serial8250",
+       .id = 0,
+       .dev.platform_data = iop13xx_uart0_data,
+       .num_resources = 2,
+       .resource = iop13xx_uart0_resources,
+};
+
+static struct platform_device iop13xx_uart1 = {
+       .name = "serial8250",
+       .id = 0,
+       .dev.platform_data = iop13xx_uart1_data,
+       .num_resources = 2,
+       .resource = iop13xx_uart1_resources
+};
+
+static struct resource iop13xx_i2c_0_resources[] = {
+        [0] = {
+                .start = IOP13XX_I2C0_PHYS,
+                .end = IOP13XX_I2C0_PHYS + 0x18,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_I2C_0,
+                .end = IRQ_IOP13XX_I2C_0,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct resource iop13xx_i2c_1_resources[] = {
+        [0] = {
+                .start = IOP13XX_I2C1_PHYS,
+                .end = IOP13XX_I2C1_PHYS + 0x18,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_I2C_1,
+                .end = IRQ_IOP13XX_I2C_1,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct resource iop13xx_i2c_2_resources[] = {
+        [0] = {
+                .start = IOP13XX_I2C2_PHYS,
+                .end = IOP13XX_I2C2_PHYS + 0x18,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_I2C_2,
+                .end = IRQ_IOP13XX_I2C_2,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
+ * we just use the same device name.
+ */
+
+/* The ids are fixed up later in iop13xx_platform_init */
+static struct platform_device iop13xx_i2c_0_controller = {
+        .name = "IOP3xx-I2C",
+        .id = 0,
+        .num_resources = 2,
+        .resource = iop13xx_i2c_0_resources
+};
+
+static struct platform_device iop13xx_i2c_1_controller = {
+        .name = "IOP3xx-I2C",
+        .id = 0,
+        .num_resources = 2,
+        .resource = iop13xx_i2c_1_resources
+};
+
+static struct platform_device iop13xx_i2c_2_controller = {
+        .name = "IOP3xx-I2C",
+        .id = 0,
+        .num_resources = 2,
+        .resource = iop13xx_i2c_2_resources
+};
+
+#ifdef CONFIG_MTD_PHYSMAP
+/* PBI Flash Device
+ */
+static struct physmap_flash_data iq8134x_flash_data = {
+        .width = 2,
+};
+
+static struct resource iq8134x_flash_resource = {
+        .start = IQ81340_FLASHBASE,
+        .end   = 0,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device iq8134x_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = { .platform_data  = &iq8134x_flash_data, },
+        .num_resources  = 1,
+        .resource       = &iq8134x_flash_resource,
+};
+
+static unsigned long iq8134x_probe_flash_size(void)
+{
+        uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
+        int i;
+        char query[3];
+        unsigned long size = 0;
+        int width = iq8134x_flash_data.width;
+
+        if (flash_addr) {
+                /* send CFI 'query' command */
+                writew(0x98, flash_addr);
+
+                /* check for CFI compliance */
+                for (i = 0; i < 3 * width; i += width)
+                        query[i / width] = readb(flash_addr + (0x10 * width) + i);
+
+                /* read the size */
+                if (memcmp(query, "QRY", 3) == 0)
+                        size = 1 << readb(flash_addr + (0x27 * width));
+
+                /* send CFI 'read array' command */
+                writew(0xff, flash_addr);
+
+                iounmap(flash_addr);
+        }
+
+        return size;
+}
+#endif
+
+void __init iop13xx_map_io(void)
+{
+        /* Initialize the Static Page Table maps */
+        iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
+}
+
+static int init_uart = 0;
+static int init_i2c = 0;
+
+void __init iop13xx_platform_init(void)
+{
+        int i;
+        u32 uart_idx, i2c_idx, plat_idx;
+        struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
+
+        /* set the bases so we can read the device id */
+        iop13xx_set_atu_mmr_bases();
+
+        memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
+
+        if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
+                switch (iop13xx_dev_id()) {
+                /* enable both uarts on iop341 and iop342 */
+                case 0x3380:
+                case 0x3384:
+                case 0x3388:
+                case 0x338c:
+                case 0x3382:
+                case 0x3386:
+                case 0x338a:
+                case 0x338e:
+                        init_uart |= IOP13XX_INIT_UART_0;
+                        init_uart |= IOP13XX_INIT_UART_1;
+                        break;
+                /* only enable uart 1 */
+                default:
+                        init_uart |= IOP13XX_INIT_UART_1;
+                }
+        }
+
+        if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
+                switch (iop13xx_dev_id()) {
+                /* enable all i2c units on iop341 and iop342 */
+                case 0x3380:
+                case 0x3384:
+                case 0x3388:
+                case 0x338c:
+                case 0x3382:
+                case 0x3386:
+                case 0x338a:
+                case 0x338e:
+                        init_i2c |= IOP13XX_INIT_I2C_0;
+                        init_i2c |= IOP13XX_INIT_I2C_1;
+                        init_i2c |= IOP13XX_INIT_I2C_2;
+                        break;
+                /* only enable i2c 1 and 2 */
+                default:
+                        init_i2c |= IOP13XX_INIT_I2C_1;
+                        init_i2c |= IOP13XX_INIT_I2C_2;
+                }
+        }
+
+        plat_idx = 0;
+        uart_idx = 0;
+        i2c_idx = 0;
+
+        /* uart 1 (if enabled) is ttyS0 */
+        if (init_uart & IOP13XX_INIT_UART_1) {
+                PRINTK("Adding uart1 to platform device list\n");
+                iop13xx_uart1.id = uart_idx++;
+                iop13xx_devices[plat_idx++] = &iop13xx_uart1;
+        }
+        if (init_uart & IOP13XX_INIT_UART_0) {
+                PRINTK("Adding uart0 to platform device list\n");
+                iop13xx_uart0.id = uart_idx++;
+                iop13xx_devices[plat_idx++] = &iop13xx_uart0;
+        }
+
+        for(i = 0; i < IQ81340_NUM_I2C; i++) {
+                if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
+                        printk("Adding i2c%d to platform device list\n", i);
+                switch(init_i2c & (1 << i)) {
+                case IOP13XX_INIT_I2C_0:
+                        iop13xx_i2c_0_controller.id = i2c_idx++;
+                        iop13xx_devices[plat_idx++] =
+                                &iop13xx_i2c_0_controller;
+                        break;
+                case IOP13XX_INIT_I2C_1:
+                        iop13xx_i2c_1_controller.id = i2c_idx++;
+                        iop13xx_devices[plat_idx++] =
+                                &iop13xx_i2c_1_controller;
+                        break;
+                case IOP13XX_INIT_I2C_2:
+                        iop13xx_i2c_2_controller.id = i2c_idx++;
+                        iop13xx_devices[plat_idx++] =
+                                &iop13xx_i2c_2_controller;
+                        break;
+                }
+        }
+
+#ifdef CONFIG_MTD_PHYSMAP
+        iq8134x_flash_resource.end = iq8134x_flash_resource.start +
+                                iq8134x_probe_flash_size();
+        if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
+                iop13xx_devices[plat_idx++] = &iq8134x_flash;
+        else
+                printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
+#endif
+
+        platform_add_devices(iop13xx_devices, plat_idx);
+}
+
+static int __init iop13xx_init_uart_setup(char *str)
+{
+        if (str) {
+                while (*str != '\0') {
+                        switch(*str) {
+                        case '0':
+                                init_uart |= IOP13XX_INIT_UART_0;
+                                break;
+                        case '1':
+                                init_uart |= IOP13XX_INIT_UART_1;
+                                break;
+                        case ',':
+                        case '=':
+                                break;
+                        default:
+                                PRINTK("\"iop13xx_init_uart\" malformed"
+                                            " at character: \'%c\'", *str);
+                                *(str + 1) = '\0';
+                                init_uart = IOP13XX_INIT_UART_DEFAULT;
+                        }
+                        str++;
+                }
+        }
+        return 1;
+}
+
+static int __init iop13xx_init_i2c_setup(char *str)
+{
+        if (str) {
+                while (*str != '\0') {
+                        switch(*str) {
+                        case '0':
+                                init_i2c |= IOP13XX_INIT_I2C_0;
+                                break;
+                        case '1':
+                                init_i2c |= IOP13XX_INIT_I2C_1;
+                                break;
+                        case '2':
+                                init_i2c |= IOP13XX_INIT_I2C_2;
+                                break;
+                        case ',':
+                        case '=':
+                                break;
+                        default:
+                                PRINTK("\"iop13xx_init_i2c\" malformed"
+                                            " at character: \'%c\'", *str);
+                                *(str + 1) = '\0';
+                                init_i2c = IOP13XX_INIT_I2C_DEFAULT;
+                        }
+                        str++;
+                }
+        }
+        return 1;
+}
+
+__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
+__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
diff --git a/arch/arm/mach-iop13xx/time.c b/arch/arm/mach-iop13xx/time.c
new file mode 100644
index 000000000000..8b21365f653f
--- /dev/null
+++ b/arch/arm/mach-iop13xx/time.c
@@ -0,0 +1,102 @@
+/*
+ * arch/arm/mach-iop13xx/time.c
+ *
+ * Timer code for IOP13xx (copied from IOP32x/IOP33x implementation)
+ *
+ * Author: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright 2002-2003 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/init.h>
+#include <linux/timex.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+
+static unsigned long ticks_per_jiffy;
+static unsigned long ticks_per_usec;
+static unsigned long next_jiffy_time;
+
+static inline u32 read_tcr1(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
+        return val;
+}
+
+unsigned long iop13xx_gettimeoffset(void)
+{
+        unsigned long offset;
+        u32 cp_flags;
+
+        cp_flags = iop13xx_cp6_save();
+        offset = next_jiffy_time - read_tcr1();
+        iop13xx_cp6_restore(cp_flags);
+
+        return offset / ticks_per_usec;
+}
+
+static irqreturn_t
+iop13xx_timer_interrupt(int irq, void *dev_id)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+
+        write_seqlock(&xtime_lock);
+
+        asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1));
+
+        while ((signed long)(next_jiffy_time - read_tcr1())
+                                                        >= ticks_per_jiffy) {
+                timer_tick();
+                next_jiffy_time -= ticks_per_jiffy;
+        }
+
+        write_sequnlock(&xtime_lock);
+
+        iop13xx_cp6_restore(cp_flags);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction iop13xx_timer_irq = {
+        .name           = "IOP13XX Timer Tick",
+        .handler        = iop13xx_timer_interrupt,
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+};
+
+void __init iop13xx_init_time(unsigned long tick_rate)
+{
+        u32 timer_ctl;
+        u32 cp_flags;
+
+        ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
+        ticks_per_usec = tick_rate / 1000000;
+        next_jiffy_time = 0xffffffff;
+
+        timer_ctl = IOP13XX_TMR_EN | IOP13XX_TMR_PRIVILEGED |
+                        IOP13XX_TMR_RELOAD | IOP13XX_TMR_RATIO_1_1;
+
+        /*
+         * We use timer 0 for our timer interrupt, and timer 1 as
+         * monotonic counter for tracking missed jiffies.
+         */
+        cp_flags = iop13xx_cp6_save();
+        asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1));
+        asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl));
+        asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff));
+        asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl));
+        iop13xx_cp6_restore(cp_flags);
+
+        setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq);
+}
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 45fb2c3bcf82..6ae605857ca9 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -25,6 +25,10 @@
 #include <linux/pm.h>
 #include <linux/string.h>
 
+#include <linux/sched.h>
+#include <asm/cnt32_to_63.h>
+#include <asm/div64.h>
+
 #include <asm/hardware.h>
 #include <asm/irq.h>
 #include <asm/system.h>
@@ -41,6 +45,62 @@
 #include "generic.h"
 
 /*
+ * This is the PXA2xx sched_clock implementation. This has a resolution
+ * of at least 308ns and a maximum value that depends on the value of
+ * CLOCK_TICK_RATE.
+ *
+ * The return value is guaranteed to be monotonic in that range as
+ * long as there is always less than 582 seconds between successive
+ * calls to this function.
+ */
+unsigned long long sched_clock(void)
+{
+        unsigned long long v = cnt32_to_63(OSCR);
+        /* Note: top bit ov v needs cleared unless multiplier is even. */
+
+#if     CLOCK_TICK_RATE == 3686400
+        /* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */
+        /* The <<1 is used to get rid of tick.hi top bit */
+        v *= 78125<<1;
+        do_div(v, 288<<1);
+#elif   CLOCK_TICK_RATE == 3250000
+        /* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */
+        v *= 4000;
+        do_div(v, 13);
+#elif   CLOCK_TICK_RATE == 3249600
+        /* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */
+        v *= 625000;
+        do_div(v, 2031);
+#else
+#warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE"
+        /*
+         * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for
+         * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand
+         * years range which is nice, but with higher computation cost.
+         */
+        {
+                union {
+                        unsigned long long val;
+                        struct { unsigned long lo, hi; };
+                } x;
+                unsigned long long y;
+
+                x.val = v;
+                x.hi &= 0x7fffffff;
+                y = (unsigned long long)x.lo * NSEC_PER_SEC;
+                x.lo = y;
+                y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC;
+                x.hi = do_div(y, CLOCK_TICK_RATE);
+                do_div(x.val, CLOCK_TICK_RATE);
+                x.hi += y;
+                v = x.val;
+        }
+#endif
+
+        return v;
+}
+
+/*
  * Handy function to set GPIO alternate functions
  */
 
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 4575f316e141..e510295c2580 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -20,6 +20,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/div64.h>
+#include <asm/cnt32_to_63.h>
 #include <asm/hardware.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -118,15 +119,21 @@ EXPORT_SYMBOL(cpufreq_get);
 
 /*
  * This is the SA11x0 sched_clock implementation.  This has
- * a resolution of 271ns, and a maximum value of 1165s.
+ * a resolution of 271ns, and a maximum value of 32025597s (370 days).
+ *
+ * The return value is guaranteed to be monotonic in that range as
+ * long as there is always less than 582 seconds between successive
+ * calls to this function.
+ *
  *  ( * 1E9 / 3686400 => * 78125 / 288)
  */
 unsigned long long sched_clock(void)
 {
-        unsigned long long v;
+        unsigned long long v = cnt32_to_63(OSCR);
 
-        v = (unsigned long long)OSCR * 78125;
-        do_div(v, 288);
+        /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
+        v *= 78125<<1;
+        do_div(v, 288<<1);
 
         return v;
 }
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index dcc2ca3dcde9..57196947559f 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -27,6 +27,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 
+#include <asm/cnt32_to_63.h>
 #include <asm/system.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
@@ -228,14 +229,19 @@ void __init versatile_map_io(void)
 
 /*
  * This is the Versatile sched_clock implementation.  This has
- * a resolution of 41.7ns, and a maximum value of about 179s.
+ * a resolution of 41.7ns, and a maximum value of about 35583 days.
+ *
+ * The return value is guaranteed to be monotonic in that range as
+ * long as there is always less than 89 seconds between successive
+ * calls to this function.
  */
 unsigned long long sched_clock(void)
 {
-        unsigned long long v;
+        unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
 
-        v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
-        do_div(v, 3);
+        /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
+        v *= 125<<1;
+        do_div(v, 3<<1);
 
         return v;
 }
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index efebd6050285..125cb3ff5589 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -333,7 +333,7 @@ config CPU_XSCALE
 # XScale Core Version 3
 config CPU_XSC3
         bool
-        depends on ARCH_IXP23XX
+        depends on ARCH_IXP23XX || ARCH_IOP13XX
         default y
         select CPU_32v5
         select CPU_ABRT_EV5T
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 579c69ae9ff7..8bcb838e5444 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Mon Oct 16 21:13:36 2006
+# Last update: Thu Dec 7 17:19:20 2006
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -79,7 +79,7 @@ psionw			ARCH_PSIONW		PSIONW			60
 aln                     SA1100_ALN              ALN                     61
 epxa                    ARCH_CAMELOT            CAMELOT                 62
 gds2200                 SA1100_GDS2200          GDS2200                 63
-psion_series7           SA1100_PSION_SERIES7    PSION_SERIES7           64
+netbook                 SA1100_PSION_SERIES7    PSION_SERIES7           64
 xfile                   SA1100_XFILE            XFILE                   65
 accelent_ep9312         ARCH_ACCELENT_EP9312    ACCELENT_EP9312         66
 ic200                   ARCH_IC200              IC200                   67
@@ -810,9 +810,9 @@ sb3010			MACH_SB3010		SB3010			795
 rm9200                  MACH_RM9200             RM9200                  796
 dma03                   MACH_DMA03              DMA03                   797
 road_s101               MACH_ROAD_S101          ROAD_S101               798
-iq_nextgen_a            MACH_IQ_NEXTGEN_A       IQ_NEXTGEN_A            799
+iq81340sc               MACH_IQ81340SC          IQ81340SC               799
 iq_nextgen_b            MACH_IQ_NEXTGEN_B       IQ_NEXTGEN_B            800
-iq_nextgen_c            MACH_IQ_NEXTGEN_C       IQ_NEXTGEN_C            801
+iq81340mc               MACH_IQ81340MC          IQ81340MC               801
 iq_nextgen_d            MACH_IQ_NEXTGEN_D       IQ_NEXTGEN_D            802
 iq_nextgen_e            MACH_IQ_NEXTGEN_E       IQ_NEXTGEN_E            803
 mallow_at91             MACH_MALLOW_AT91        MALLOW_AT91             804
@@ -1165,9 +1165,57 @@ pnx4010			MACH_PNX4010		PNX4010			1151
 oxnas                   MACH_OXNAS              OXNAS                   1152
 fiori                   MACH_FIORI              FIORI                   1153
 ml1200                  MACH_ML1200             ML1200                  1154
-cactus                  MACH_CACTUS             CACTUS                  1155
+pecos                   MACH_PECOS              PECOS                   1155
 nb2xxx                  MACH_NB2XXX             NB2XXX                  1156
 hw6900                  MACH_HW6900             HW6900                  1157
 cdcs_quoll              MACH_CDCS_QUOLL         CDCS_QUOLL              1158
 quicksilver             MACH_QUICKSILVER        QUICKSILVER             1159
 uplat926                MACH_UPLAT926           UPLAT926                1160
+dep2410_dep2410         MACH_DEP2410_THOMAS     DEP2410_THOMAS          1161
+dtk2410                 MACH_DTK2410            DTK2410                 1162
+chili                   MACH_CHILI              CHILI                   1163
+demeter                 MACH_DEMETER            DEMETER                 1164
+dionysus                MACH_DIONYSUS           DIONYSUS                1165
+as352x                  MACH_AS352X             AS352X                  1166
+service                 MACH_SERVICE            SERVICE                 1167
+cs_e9301                MACH_CS_E9301           CS_E9301                1168
+micro9m                 MACH_MICRO9M            MICRO9M                 1169
+ia_mospck               MACH_IA_MOSPCK          IA_MOSPCK               1170
+ql201b                  MACH_QL201B             QL201B                  1171
+bbm                     MACH_BBM                BBM                     1174
+exxx                    MACH_EXXX               EXXX                    1175
+wma11b                  MACH_WMA11B             WMA11B                  1176
+pelco_atlas             MACH_PELCO_ATLAS        PELCO_ATLAS             1177
+g500                    MACH_G500               G500                    1178
+bug                     MACH_BUG                BUG                     1179
+mx33ads                 MACH_MX33ADS            MX33ADS                 1180
+chub                    MACH_CHUB               CHUB                    1181
+gta01                   MACH_GTA01              GTA01                   1182
+w90n740                 MACH_W90N740            W90N740                 1183
+medallion_sa2410        MACH_MEDALLION_SA2410   MEDALLION_SA2410        1184
+ia_cpu_9200_2           MACH_IA_CPU_9200_2      IA_CPU_9200_2           1185
+dimmrm9200              MACH_DIMMRM9200         DIMMRM9200              1186
+pm9261                  MACH_PM9261             PM9261                  1187
+mx21                    MACH_MX21               MX21                    1188
+ml7304                  MACH_ML7304             ML7304                  1189
+ucp250                  MACH_UCP250             UCP250                  1190
+intboard                MACH_INTBOARD           INTBOARD                1191
+gulfstream              MACH_GULFSTREAM         GULFSTREAM              1192
+labquest                MACH_LABQUEST           LABQUEST                1193
+vcmx313                 MACH_VCMX313            VCMX313                 1194
+urg200                  MACH_URG200             URG200                  1195
+cpux255lcdnet           MACH_CPUX255LCDNET      CPUX255LCDNET           1196
+netdcu9                 MACH_NETDCU9            NETDCU9                 1197
+netdcu10                MACH_NETDCU10           NETDCU10                1198
+dspg_dga                MACH_DSPG_DGA           DSPG_DGA                1199
+dspg_dvw                MACH_DSPG_DVW           DSPG_DVW                1200
+solos                   MACH_SOLOS              SOLOS                   1201
+at91sam9263ek           MACH_AT91SAM9263EK      AT91SAM9263EK           1202
+osstbox                 MACH_OSSTBOX            OSSTBOX                 1203
+kbat9261                MACH_KBAT9261           KBAT9261                1204
+ct1100                  MACH_CT1100             CT1100                  1205
+akcppxa                 MACH_AKCPPXA            AKCPPXA                 1206
+zevio_1020              MACH_ZEVIO_1020         ZEVIO_1020              1207
+hitrack                 MACH_HITRACK            HITRACK                 1208
+syme1                   MACH_SYME1              SYME1                   1209
+syhl1                   MACH_SYHL1              SYHL1                   1210
diff --git a/drivers/char/watchdog/at91rm9200_wdt.c b/drivers/char/watchdog/at91rm9200_wdt.c
index 4e7a1145e78f..cb86967e2c5f 100644
--- a/drivers/char/watchdog/at91rm9200_wdt.c
+++ b/drivers/char/watchdog/at91rm9200_wdt.c
@@ -21,6 +21,7 @@
 #include <linux/watchdog.h>
 #include <asm/bitops.h>
 #include <asm/uaccess.h>
+#include <asm/arch/at91_st.h>
 
 
 #define WDT_DEFAULT_TIME        5       /* seconds */
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 510816c16da3..5cbf8b9d5141 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -195,11 +195,11 @@ config I2C_IBM_IIC
           will be called i2c-ibm_iic.
 
 config I2C_IOP3XX
-        tristate "Intel IOP3xx and IXP4xx on-chip I2C interface"
-        depends on (ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX) && I2C
+        tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface"
+        depends on (ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX) && I2C
         help
           Say Y here if you want to use the IIC bus controller on
-          the Intel IOP3xx I/O Processors or IXP4xx Network Processors.
+          the Intel IOPx3xx I/O Processors or IXP4xx Network Processors.
 
           This driver can also be built as a module.  If so, the module
           will be called i2c-iop3xx.
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index ea41852ec8cd..fbef8da60043 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -91,11 +91,11 @@ config MMC_AU1X
 
           If unsure, say N.
 
-config MMC_AT91RM9200
-        tristate "AT91RM9200 SD/MMC Card Interface support"
-        depends on ARCH_AT91RM9200 && MMC
+config MMC_AT91
+        tristate "AT91 SD/MMC Card Interface support"
+        depends on ARCH_AT91 && MMC
         help
-          This selects the AT91RM9200 MCI controller.
+          This selects the AT91 MCI controller.
 
           If unsure, say N.
 
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index acfd4de0aba5..83ffb9326a54 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_MMC_SDHCI)		+= sdhci.o
 obj-$(CONFIG_MMC_WBSD)          += wbsd.o
 obj-$(CONFIG_MMC_AU1X)          += au1xmmc.o
 obj-$(CONFIG_MMC_OMAP)          += omap.o
-obj-$(CONFIG_MMC_AT91RM9200)    += at91_mci.o
+obj-$(CONFIG_MMC_AT91)          += at91_mci.o
 obj-$(CONFIG_MMC_TIFM_SD)       += tifm_sd.o
 
 mmc_core-y := mmc.o mmc_sysfs.o
diff --git a/drivers/mmc/at91_mci.c b/drivers/mmc/at91_mci.c
index 494b23fb0a01..41761f7189a6 100644
--- a/drivers/mmc/at91_mci.c
+++ b/drivers/mmc/at91_mci.c
@@ -73,8 +73,8 @@
 #include <asm/mach/mmc.h>
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91rm9200_mci.h>
-#include <asm/arch/at91rm9200_pdc.h>
+#include <asm/arch/at91_mci.h>
+#include <asm/arch/at91_pdc.h>
 
 #define DRIVER_NAME "at91_mci"
 
diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c
index 3bcb7dc32995..697966703512 100644
--- a/drivers/pcmcia/at91_cf.c
+++ b/drivers/pcmcia/at91_cf.c
@@ -23,9 +23,9 @@
 #include <asm/io.h>
 #include <asm/sizes.h>
 
-#include <asm/arch/at91rm9200.h>
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/at91rm9200_mc.h>
 
 
 /*
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
index 391a1f4167a4..9217ee6c7865 100644
--- a/drivers/serial/atmel_serial.c
+++ b/drivers/serial/atmel_serial.c
@@ -1,5 +1,5 @@
 /*
- *  linux/drivers/char/at91_serial.c
+ *  linux/drivers/char/atmel_serial.c
  *
  *  Driver for Atmel AT91 / AT32 Serial ports
  *  Copyright (C) 2003 Rick Bronson
@@ -36,11 +36,11 @@
 
 #include <asm/io.h>
 
-#include <asm/arch/at91rm9200_pdc.h>
 #include <asm/mach/serial_at91.h>
 #include <asm/arch/board.h>
+#include <asm/arch/at91_pdc.h>
 #ifdef CONFIG_ARM
-#include <asm/arch/system.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #endif
 
@@ -137,8 +137,8 @@ static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
         unsigned int control = 0;
         unsigned int mode;
 
-#ifdef CONFIG_ARM
-        if (arch_identify() == ARCH_ID_AT91RM9200) {
+#ifdef CONFIG_ARCH_AT91RM9200
+        if (cpu_is_at91rm9200()) {
                 /*
                  * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
                  *  We need to drive the pin manually.
diff --git a/drivers/serial/atmel_serial.h b/drivers/serial/atmel_serial.h
index eced2ad1a8d9..fe1763b2a6d5 100644
--- a/drivers/serial/atmel_serial.h
+++ b/drivers/serial/atmel_serial.h
@@ -31,8 +31,8 @@
 #define         ATMEL_US_RSTIT          (1 << 13)               /* Reset Iterations */
 #define         ATMEL_US_RSTNACK        (1 << 14)               /* Reset Non Acknowledge */
 #define         ATMEL_US_RETTO          (1 << 15)               /* Rearm Time-out */
-#define         ATMEL_US_DTREN          (1 << 16)               /* Data Terminal Ready Enable */
-#define         ATMEL_US_DTRDIS         (1 << 17)               /* Data Terminal Ready Disable */
+#define         ATMEL_US_DTREN          (1 << 16)               /* Data Terminal Ready Enable [AT91RM9200 only] */
+#define         ATMEL_US_DTRDIS         (1 << 17)               /* Data Terminal Ready Disable [AT91RM9200 only] */
 #define         ATMEL_US_RTSEN          (1 << 18)               /* Request To Send Enable */
 #define         ATMEL_US_RTSDIS         (1 << 19)               /* Request To Send Disable */
 
@@ -92,9 +92,9 @@
 #define         ATMEL_US_TXBUFE         (1 << 11)               /* Transmission Buffer Empty */
 #define         ATMEL_US_RXBUFF         (1 << 12)               /* Reception Buffer Full */
 #define         ATMEL_US_NACK           (1 << 13)               /* Non Acknowledge */
-#define         ATMEL_US_RIIC           (1 << 16)               /* Ring Indicator Input Change */
-#define         ATMEL_US_DSRIC          (1 << 17)               /* Data Set Ready Input Change */
-#define         ATMEL_US_DCDIC          (1 << 18)               /* Data Carrier Detect Input Change */
+#define         ATMEL_US_RIIC           (1 << 16)               /* Ring Indicator Input Change [AT91RM9200 only] */
+#define         ATMEL_US_DSRIC          (1 << 17)               /* Data Set Ready Input Change [AT91RM9200 only] */
+#define         ATMEL_US_DCDIC          (1 << 18)               /* Data Carrier Detect Input Change [AT91RM9200 only] */
 #define         ATMEL_US_CTSIC          (1 << 19)               /* Clear to Send Input Change */
 #define         ATMEL_US_RI             (1 << 20)               /* RI */
 #define         ATMEL_US_DSR            (1 << 21)               /* DSR */
@@ -106,6 +106,7 @@
 #define ATMEL_US_CSR            0x14                    /* Channel Status Register */
 #define ATMEL_US_RHR            0x18                    /* Receiver Holding Register */
 #define ATMEL_US_THR            0x1c                    /* Transmitter Holding Register */
+#define         ATMEL_US_SYNH           (1 << 15)               /* Transmit/Receive Sync [SAM9 only] */
 
 #define ATMEL_US_BRGR           0x20                    /* Baud Rate Generator Register */
 #define         ATMEL_US_CD             (0xffff << 0)           /* Clock Divider */
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index f9b1719b9a37..9980a4ddfed9 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -24,7 +24,7 @@ config USB_ARCH_HAS_OHCI
         default y if ARCH_S3C2410
         default y if PXA27x
         default y if ARCH_EP93XX
-        default y if (ARCH_AT91RM9200 || ARCH_AT91SAM9261)
+        default y if ARCH_AT91
         default y if ARCH_PNX4008
         # PPC:
         default y if STB03xxx
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index bbbc82a8336a..4097a86c4b5e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -189,7 +189,7 @@ config USB_OTG
 
 config USB_GADGET_AT91
         boolean "AT91 USB Device Port"
-        depends on ARCH_AT91RM9200
+        depends on ARCH_AT91
         select USB_GADGET_SELECTED
         help
            Many Atmel AT91 processors (such as the AT91RM2000) have a
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index ea4714e557e4..4776b3bdf9c8 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -935,7 +935,7 @@ MODULE_LICENSE ("GPL");
 #include "ohci-ppc-soc.c"
 #endif
 
-#if defined(CONFIG_ARCH_AT91RM9200) || defined(CONFIG_ARCH_AT91SAM9261)
+#ifdef CONFIG_ARCH_AT91
 #include "ohci-at91.c"
 #endif
 
@@ -952,8 +952,7 @@ MODULE_LICENSE ("GPL");
       || defined (CONFIG_ARCH_EP93XX) \
       || defined (CONFIG_SOC_AU1X00) \
       || defined (CONFIG_USB_OHCI_HCD_PPC_SOC) \
-      || defined (CONFIG_ARCH_AT91RM9200) \
-      || defined (CONFIG_ARCH_AT91SAM9261) \
+      || defined (CONFIG_ARCH_AT91) \
       || defined (CONFIG_ARCH_PNX4008) \
         )
 #error "missing bus glue for ohci-hcd"
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
index 24b51cccde8f..9eceb4148922 100644
--- a/include/asm-arm/arch-aaec2000/memory.h
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -17,8 +17,6 @@
 #define __virt_to_bus(x)        __virt_to_phys(x)
 #define __bus_to_virt(x)        __phys_to_virt(x)
 
-#ifdef CONFIG_DISCONTIGMEM
-
 /*
  * The nodes are the followings:
  *
@@ -27,42 +25,6 @@
  *   node 2: 0xf800.0000 - 0xfbff.ffff
  *   node 3: 0xfc00.0000 - 0xffff.ffff
  */
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) \
-        (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn) \
-        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and return the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and return the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-/*
- *  Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- *  and returns the index corresponding to the appropriate page in the
- *  node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
-
-#define NODE_MAX_MEM_SHIFT      26
-#define NODE_MAX_MEM_SIZE       (1 << NODE_MAX_MEM_SHIFT)
-
-#endif /* CONFIG_DISCONTIGMEM */
+#define NODE_MEM_SIZE_BITS      26
 
 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/include/asm-arm/arch-at91rm9200/at91_aic.h b/include/asm-arm/arch-at91rm9200/at91_aic.h
new file mode 100644
index 000000000000..267e69812e26
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_aic.h
@@ -0,0 +1,53 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_aic.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Advanced Interrupt Controller (AIC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_AIC_H
+#define AT91_AIC_H
+
+#define AT91_AIC_SMR(n)         (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
+#define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
+#define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
+#define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
+#define                 AT91_AIC_SRCTYPE_FALLING        (1 << 5)
+#define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
+#define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
+
+#define AT91_AIC_SVR(n)         (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
+#define AT91_AIC_IVR            (AT91_AIC + 0x100)      /* Interrupt Vector Register */
+#define AT91_AIC_FVR            (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
+#define AT91_AIC_ISR            (AT91_AIC + 0x108)      /* Interrupt Status Register */
+#define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
+
+#define AT91_AIC_IPR            (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
+#define AT91_AIC_IMR            (AT91_AIC + 0x110)      /* Interrupt Mask Register */
+#define AT91_AIC_CISR           (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
+#define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
+#define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
+
+#define AT91_AIC_IECR           (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
+#define AT91_AIC_IDCR           (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
+#define AT91_AIC_ICCR           (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
+#define AT91_AIC_ISCR           (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
+#define AT91_AIC_EOICR          (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
+#define AT91_AIC_SPU            (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
+#define AT91_AIC_DCR            (AT91_AIC + 0x138)      /* Debug Control Register */
+#define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
+#define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
+
+#define AT91_AIC_FFER           (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC_FFDR           (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC_FFSR           (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_dbgu.h b/include/asm-arm/arch-at91rm9200/at91_dbgu.h
new file mode 100644
index 000000000000..e4b8b27acfca
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_dbgu.h
@@ -0,0 +1,45 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_dbgu.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Debug Unit (DBGU) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_DBGU_H
+#define AT91_DBGU_H
+
+#define AT91_DBGU_CR            (AT91_DBGU + 0x00)      /* Control Register */
+#define AT91_DBGU_MR            (AT91_DBGU + 0x04)      /* Mode Register */
+#define AT91_DBGU_IER           (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
+#define         AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
+#define         AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
+#define AT91_DBGU_IDR           (AT91_DBGU + 0x0c)      /* Interrupt Disable Register */
+#define AT91_DBGU_IMR           (AT91_DBGU + 0x10)      /* Interrupt Mask Register */
+#define AT91_DBGU_SR            (AT91_DBGU + 0x14)      /* Status Register */
+#define AT91_DBGU_RHR           (AT91_DBGU + 0x18)      /* Receiver Holding Register */
+#define AT91_DBGU_THR           (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
+#define AT91_DBGU_BRGR          (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
+
+#define AT91_DBGU_CIDR          (AT91_DBGU + 0x40)      /* Chip ID Register */
+#define AT91_DBGU_EXID          (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
+#define         AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
+#define         AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
+#define         AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
+#define         AT91_CIDR_NVPSIZ2       (0xf  << 12)            /* Second Nonvolatile Program Memory Size */
+#define         AT91_CIDR_SRAMSIZ       (0xf  << 16)            /* Internal SRAM Size */
+#define         AT91_CIDR_ARCH          (0xff << 20)            /* Architecture Identifier */
+#define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
+#define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
+
+#define AT91_DBGU_FNR           (AT91_DBGU + 0x48)      /* Force NTRST Register [SAM9 only] */
+#define         AT91_DBGU_FNTRST        (1 << 0)                /* Force NTRST */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_ecc.h b/include/asm-arm/arch-at91rm9200/at91_ecc.h
new file mode 100644
index 000000000000..fddf256a98d3
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_ecc.h
@@ -0,0 +1,38 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_ecc.h
+ *
+ * Error Corrected Code Controller (ECC) - System peripherals regsters.
+ * Based on AT91SAM9260 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef AT91_ECC_H
+#define AT91_ECC_H
+
+#define AT91_ECC_CR             (AT91_ECC + 0x00)       /* Control register */
+#define         AT91_ECC_RST            (1 << 0)                /* Reset parity */
+
+#define AT91_ECC_MR             (AT91_ECC + 0x04)       /* Mode register */
+#define         AT91_ECC_PAGESIZE       (3 << 0)                /* Page Size */
+#define                 AT91_ECC_PAGESIZE_528           (0)
+#define                 AT91_ECC_PAGESIZE_1056          (1)
+#define                 AT91_ECC_PAGESIZE_2112          (2)
+#define                 AT91_ECC_PAGESIZE_4224          (3)
+
+#define AT91_ECC_SR             (AT91_ECC + 0x08)       /* Status register */
+#define         AT91_ECC_RECERR         (1 << 0)                /* Recoverable Error */
+#define         AT91_ECC_ECCERR         (1 << 1)                /* ECC Single Bit Error */
+#define         AT91_ECC_MULERR         (1 << 2)                /* Multiple Errors */
+
+#define AT91_ECC_PR             (AT91_ECC + 0x0c)       /* Parity register */
+#define         AT91_ECC_BITADDR        (0xf << 0)              /* Bit Error Address */
+#define         AT91_ECC_WORDADDR       (0xfff << 4)            /* Word Error Address */
+
+#define AT91_ECC_NPR            (AT91_ECC + 0x10)       /* NParity register */
+#define         AT91_ECC_NPARITY        (0xffff << 0)           /* NParity */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_lcdc.h b/include/asm-arm/arch-at91rm9200/at91_lcdc.h
new file mode 100644
index 000000000000..9cbfcdd3c471
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_lcdc.h
@@ -0,0 +1,148 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_lcdc.h
+ *
+ * LCD Controller (LCDC).
+ * Based on AT91SAM9261 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_LCDC_H
+#define AT91_LCDC_H
+
+#define AT91_LCDC_DMABADDR1     0x00            /* DMA Base Address Register 1 */
+#define AT91_LCDC_DMABADDR2     0x04            /* DMA Base Address Register 2 */
+#define AT91_LCDC_DMAFRMPT1     0x08            /* DMA Frame Pointer Register 1 */
+#define AT91_LCDC_DMAFRMPT2     0x0c            /* DMA Frame Pointer Register 2 */
+#define AT91_LCDC_DMAFRMADD1    0x10            /* DMA Frame Address Register 1 */
+#define AT91_LCDC_DMAFRMADD2    0x14            /* DMA Frame Address Register 2 */
+
+#define AT91_LCDC_DMAFRMCFG     0x18            /* DMA Frame Configuration Register */
+#define         AT91_LCDC_FRSIZE        (0x7fffff <<  0)        /* Frame Size */
+#define         AT91_LCDC_BLENGTH       (0x7f     << 24)        /* Burst Length */
+
+#define AT91_LCDC_DMACON        0x1c            /* DMA Control Register */
+#define         AT91_LCDC_DMAEN         (0x1 << 0)      /* DMA Enable */
+#define         AT91_LCDC_DMARST        (0x1 << 1)      /* DMA Reset */
+#define         AT91_LCDC_DMABUSY       (0x1 << 2)      /* DMA Busy */
+
+#define AT91_LCDC_LCDCON1       0x0800          /* LCD Control Register 1 */
+#define         AT91_LCDC_BYPASS        (1     <<  0)   /* Bypass lcd_dotck divider */
+#define         AT91_LCDC_CLKVAL        (0x1ff << 12)   /* Clock Divider */
+#define         AT91_LCDC_LINCNT        (0x7ff << 21)   /* Line Counter */
+
+#define AT91_LCDC_LCDCON2       0x0804          /* LCD Control Register 2 */
+#define         AT91_LCDC_DISTYPE       (3 << 0)        /* Display Type */
+#define                 AT91_LCDC_DISTYPE_STNMONO       (0 << 0)
+#define                 AT91_LCDC_DISTYPE_STNCOLOR      (1 << 0)
+#define                 AT91_LCDC_DISTYPE_TFT           (2 << 0)
+#define         AT91_LCDC_SCANMOD       (1 << 2)        /* Scan Mode */
+#define                 AT91_LCDC_SCANMOD_SINGLE        (0 << 2)
+#define                 AT91_LCDC_SCANMOD_DUAL          (1 << 2)
+#define         AT91_LCDC_IFWIDTH       (3 << 3)        /*Interface Width */
+#define                 AT91_LCDC_IFWIDTH_4             (0 << 3)
+#define                 AT91_LCDC_IFWIDTH_8             (1 << 3)
+#define                 AT91_LCDC_IFWIDTH_16            (2 << 3)
+#define         AT91_LCDC_PIXELSIZE     (7 << 5)        /* Bits per pixel */
+#define                 AT91_LCDC_PIXELSIZE_1           (0 << 5)
+#define                 AT91_LCDC_PIXELSIZE_2           (1 << 5)
+#define                 AT91_LCDC_PIXELSIZE_4           (2 << 5)
+#define                 AT91_LCDC_PIXELSIZE_8           (3 << 5)
+#define                 AT91_LCDC_PIXELSIZE_16          (4 << 5)
+#define                 AT91_LCDC_PIXELSIZE_24          (5 << 5)
+#define         AT91_LCDC_INVVD         (1 << 8)        /* LCD Data polarity */
+#define                 AT91_LCDC_INVVD_NORMAL          (0 << 8)
+#define                 AT91_LCDC_INVVD_INVERTED        (1 << 8)
+#define         AT91_LCDC_INVFRAME      (1 << 9 )       /* LCD VSync polarity */
+#define                 AT91_LCDC_INVFRAME_NORMAL       (0 << 9)
+#define                 AT91_LCDC_INVFRAME_INVERTED     (1 << 9)
+#define         AT91_LCDC_INVLINE       (1 << 10)       /* LCD HSync polarity */
+#define                 AT91_LCDC_INVLINE_NORMAL        (0 << 10)
+#define                 AT91_LCDC_INVLINE_INVERTED      (1 << 10)
+#define         AT91_LCDC_INVCLK        (1 << 11)       /* LCD dotclk polarity */
+#define                 AT91_LCDC_INVCLK_NORMAL         (0 << 11)
+#define                 AT91_LCDC_INVCLK_INVERTED       (1 << 11)
+#define         AT91_LCDC_INVDVAL       (1 << 12)       /* LCD dval polarity */
+#define                 AT91_LCDC_INVDVAL_NORMAL        (0 << 12)
+#define                 AT91_LCDC_INVDVAL_INVERTED      (1 << 12)
+#define         AT91_LCDC_CLKMOD        (1 << 15)       /* LCD dotclk mode */
+#define                 AT91_LCDC_CLKMOD_ACTIVEDISPLAY  (0 << 15)
+#define                 AT91_LCDC_CLKMOD_ALWAYSACTIVE   (1 << 15)
+#define         AT91_LCDC_MEMOR         (1 << 31)       /* Memory Ordering Format */
+#define                 AT91_LCDC_MEMOR_BIG             (0 << 31)
+#define                 AT91_LCDC_MEMOR_LITTLE          (1 << 31)
+
+#define AT91_LCDC_TIM1          0x0808          /* LCD Timing Register 1 */
+#define         AT91_LCDC_VFP           (0xff <<  0)    /* Vertical Front Porch */
+#define         AT91_LCDC_VBP           (0xff <<  8)    /* Vertical Back Porch */
+#define         AT91_LCDC_VPW           (0x3f << 16)    /* Vertical Synchronization Pulse Width */
+#define         AT91_LCDC_VHDLY         (0xf  << 24)    /* Vertical to Horizontal Delay */
+
+#define AT91_LCDC_TIM2          0x080c          /* LCD Timing Register 2 */
+#define         AT91_LCDC_HBP           (0xff  <<  0)   /* Horizontal Back Porch */
+#define         AT91_LCDC_HPW           (0x3f  <<  8)   /* Horizontal Synchronization Pulse Width */
+#define         AT91_LCDC_HFP           (0x7ff << 21)   /* Horizontal Front Porch */
+
+#define AT91_LCDC_LCDFRMCFG     0x0810          /* LCD Frame Configuration Register */
+#define         AT91_LCDC_LINEVAL       (0x7ff <<  0)   /* Vertical Size of LCD Module */
+#define         AT91_LCDC_HOZVAL        (0x7ff << 21)   /* Horizontal Size of LCD Module */
+
+#define AT91_LCDC_FIFO          0x0814          /* LCD FIFO Register */
+#define         AT91_LCDC_FIFOTH        (0xffff)        /* FIFO Threshold */
+
+#define AT91_LCDC_DP1_2         0x081c          /* Dithering Pattern DP1_2 Register */
+#define AT91_LCDC_DP4_7         0x0820          /* Dithering Pattern DP4_7 Register */
+#define AT91_LCDC_DP3_5         0x0824          /* Dithering Pattern DP3_5 Register */
+#define AT91_LCDC_DP2_3         0x0828          /* Dithering Pattern DP2_3 Register */
+#define AT91_LCDC_DP5_7         0x082c          /* Dithering Pattern DP5_7 Register */
+#define AT91_LCDC_DP3_4         0x0830          /* Dithering Pattern DP3_4 Register */
+#define AT91_LCDC_DP4_5         0x0834          /* Dithering Pattern DP4_5 Register */
+#define AT91_LCDC_DP6_7         0x0838          /* Dithering Pattern DP6_7 Register */
+#define         AT91_LCDC_DP1_2_VAL     (0xff)
+#define         AT91_LCDC_DP4_7_VAL     (0xfffffff)
+#define         AT91_LCDC_DP3_5_VAL     (0xfffff)
+#define         AT91_LCDC_DP2_3_VAL     (0xfff)
+#define         AT91_LCDC_DP5_7_VAL     (0xfffffff)
+#define         AT91_LCDC_DP3_4_VAL     (0xffff)
+#define         AT91_LCDC_DP4_5_VAL     (0xfffff)
+#define         AT91_LCDC_DP6_7_VAL     (0xfffffff)
+
+#define AT91_LCDC_PWRCON        0x083c          /* Power Control Register */
+#define         AT91_LCDC_PWR           (1    <<  0)    /* LCD Module Power Control */
+#define         AT91_LCDC_GUARDT        (0x7f <<  1)    /* Delay in Frame Period */
+#define         AT91_LCDC_BUSY          (1    << 31)    /* LCD Busy */
+
+#define AT91_LCDC_CONTRAST_CTR  0x0840          /* Contrast Control Register */
+#define         AT91_LCDC_PS            (3 << 0)        /* Contrast Counter Prescaler */
+#define                 AT91_LCDC_PS_DIV1               (0 << 0)
+#define                 AT91_LCDC_PS_DIV2               (1 << 0)
+#define                 AT91_LCDC_PS_DIV4               (2 << 0)
+#define                 AT91_LCDC_PS_DIV8               (3 << 0)
+#define         AT91_LCDC_POL           (1 << 2)        /* Polarity of output Pulse */
+#define                 AT91_LCDC_POL_NEGATIVE          (0 << 2)
+#define                 AT91_LCDC_POL_POSITIVE          (1 << 2)
+#define         AT91_LCDC_ENA           (1 << 3)        /* PWM generator Control */
+#define                 AT91_LCDC_ENA_PWMDISABLE        (0 << 3)
+#define                 AT91_LCDC_ENA_PWMENABLE         (1 << 3)
+
+#define AT91_LCDC_CONTRAST_VAL  0x0844          /* Contrast Value Register */
+#define         AT91_LCDC_CVAL          (0xff)          /* PWM compare value */
+
+#define AT91_LCDC_IER           0x0848          /* Interrupt Enable Register */
+#define AT91_LCDC_IDR           0x084c          /* Interrupt Disable Register */
+#define AT91_LCDC_IMR           0x0850          /* Interrupt Mask Register */
+#define AT91_LCDC_ISR           0x0854          /* Interrupt Enable Register */
+#define AT91_LCDC_ICR           0x0858          /* Interrupt Clear Register */
+#define         AT91_LCDC_LNI           (1 << 0)        /* Line Interrupt */
+#define         AT91_LCDC_LSTLNI        (1 << 1)        /* Last Line Interrupt */
+#define         AT91_LCDC_EOFI          (1 << 2)        /* DMA End Of Frame Interrupt */
+#define         AT91_LCDC_UFLWI         (1 << 4)        /* FIFO Underflow Interrupt */
+#define         AT91_LCDC_OWRI          (1 << 5)        /* FIFO Overwrite Interrupt */
+#define         AT91_LCDC_MERI          (1 << 6)        /* DMA Memory Error Interrupt */
+
+#define AT91_LCDC_LUT_(n)       (0x0c00 + ((n)*4))      /* Palette Entry 0..255 */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h b/include/asm-arm/arch-at91rm9200/at91_mci.h
index f28636d61e39..9a552cb743c0 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
+++ b/include/asm-arm/arch-at91rm9200/at91_mci.h
@@ -1,11 +1,11 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
+ * include/asm-arm/arch-at91rm9200/at91_mci.h
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
  *
  * MultiMedia Card Interface (MCI) registers.
- * Based on AT91RM9200 datasheet revision E.
+ * Based on AT91RM9200 datasheet revision F.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,8 +13,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_MCI_H
-#define AT91RM9200_MCI_H
+#ifndef AT91_MCI_H
+#define AT91_MCI_H
 
 #define AT91_MCI_CR             0x00            /* Control Register */
 #define         AT91_MCI_MCIEN          (1 <<  0)       /* Multi-Media Interface Enable */
@@ -25,10 +25,10 @@
 
 #define AT91_MCI_MR             0x04            /* Mode Register */
 #define         AT91_MCI_CLKDIV         (0xff  <<  0)   /* Clock Divider */
-#define         AT91_MCI_PWSDIV         (3     <<  8)   /* Power Saving Divider */
+#define         AT91_MCI_PWSDIV         (7     <<  8)   /* Power Saving Divider */
 #define         AT91_MCI_PDCPADV        (1     << 14)   /* PDC Padding Value */
 #define         AT91_MCI_PDCMODE        (1     << 15)   /* PDC-orientated Mode */
-#define         AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
+#define         AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
 
 #define AT91_MCI_DTOR           0x08            /* Data Timeout Register */
 #define         AT91_MCI_DTOCYC         (0xf << 0)      /* Data Timeout Cycle Number */
@@ -43,8 +43,8 @@
 #define         AT91_MCI_DTOMUL_1M              (7 <<  4)
 
 #define AT91_MCI_SDCR           0x0c            /* SD Card Register */
-#define         AT91_MCI_SDCSEL         (0xf << 0)      /* SD Card Selector */
-#define         AT91_MCI_SDCBUS         (1   << 7)      /* 1-bit or 4-bit bus */
+#define         AT91_MCI_SDCSEL         (3 << 0)        /* SD Card Selector */
+#define         AT91_MCI_SDCBUS         (1 << 7)        /* 1-bit or 4-bit bus */
 
 #define AT91_MCI_ARGR           0x10            /* Argument Register */
 
@@ -78,18 +78,20 @@
 
 #define AT91_MCI_SR             0x40            /* Status Register */
 #define         AT91_MCI_CMDRDY         (1 <<  0)       /* Command Ready */
-#define         AT91_MCI_RXRDY          (1 <<  1)       /* Receiver Ready */
+#define         AT91_MCI_RXRDY          (1 <<  1)       /* Receiver Ready */
 #define         AT91_MCI_TXRDY          (1 <<  2)       /* Transmit Ready */
 #define         AT91_MCI_BLKE           (1 <<  3)       /* Data Block Ended */
 #define         AT91_MCI_DTIP           (1 <<  4)       /* Data Transfer in Progress */
 #define         AT91_MCI_NOTBUSY        (1 <<  5)       /* Data Not Busy */
 #define         AT91_MCI_ENDRX          (1 <<  6)       /* End of RX Buffer */
 #define         AT91_MCI_ENDTX          (1 <<  7)       /* End fo TX Buffer */
+#define         AT91_MCI_SDIOIRQA       (1 <<  8)       /* SDIO Interrupt for Slot A */
+#define         At91_MCI_SDIOIRQB       (1 <<  9)       /* SDIO Interrupt for Slot B [AT91RM9200 only] */
 #define         AT91_MCI_RXBUFF         (1 << 14)       /* RX Buffer Full */
 #define         AT91_MCI_TXBUFE         (1 << 15)       /* TX Buffer Empty */
-#define         AT91_MCI_RINDE          (1 << 16)       /* Response Index Error */
+#define         AT91_MCI_RINDE          (1 << 16)       /* Response Index Error */
 #define         AT91_MCI_RDIRE          (1 << 17)       /* Response Direction Error */
-#define         AT91_MCI_RCRCE          (1 << 18)       /* Response CRC Error */
+#define         AT91_MCI_RCRCE          (1 << 18)       /* Response CRC Error */
 #define         AT91_MCI_RENDE          (1 << 19)       /* Response End Bit Error */
 #define         AT91_MCI_RTOE           (1 << 20)       /* Reponse Time-out Error */
 #define         AT91_MCI_DCRCE          (1 << 21)       /* Data CRC Error */
diff --git a/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h b/include/asm-arm/arch-at91rm9200/at91_pdc.h
index ce1150d4438d..79d6e02fa45e 100644
--- a/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_pdc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+ * include/asm-arm/arch-at91rm9200/at91_pdc.h
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
@@ -13,8 +13,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_PDC_H
-#define AT91RM9200_PDC_H
+#ifndef AT91_PDC_H
+#define AT91_PDC_H
 
 #define AT91_PDC_RPR            0x100   /* Receive Pointer Register */
 #define AT91_PDC_RCR            0x104   /* Receive Counter Register */
diff --git a/include/asm-arm/arch-at91rm9200/at91_pio.h b/include/asm-arm/arch-at91rm9200/at91_pio.h
new file mode 100644
index 000000000000..680eaa1f5915
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_pio.h
@@ -0,0 +1,49 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_pio.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Parallel I/O Controller (PIO) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIO_H
+#define AT91_PIO_H
+
+#define PIO_PER         0x00    /* Enable Register */
+#define PIO_PDR         0x04    /* Disable Register */
+#define PIO_PSR         0x08    /* Status Register */
+#define PIO_OER         0x10    /* Output Enable Register */
+#define PIO_ODR         0x14    /* Output Disable Register */
+#define PIO_OSR         0x18    /* Output Status Register */
+#define PIO_IFER        0x20    /* Glitch Input Filter Enable */
+#define PIO_IFDR        0x24    /* Glitch Input Filter Disable */
+#define PIO_IFSR        0x28    /* Glitch Input Filter Status */
+#define PIO_SODR        0x30    /* Set Output Data Register */
+#define PIO_CODR        0x34    /* Clear Output Data Register */
+#define PIO_ODSR        0x38    /* Output Data Status Register */
+#define PIO_PDSR        0x3c    /* Pin Data Status Register */
+#define PIO_IER         0x40    /* Interrupt Enable Register */
+#define PIO_IDR         0x44    /* Interrupt Disable Register */
+#define PIO_IMR         0x48    /* Interrupt Mask Register */
+#define PIO_ISR         0x4c    /* Interrupt Status Register */
+#define PIO_MDER        0x50    /* Multi-driver Enable Register */
+#define PIO_MDDR        0x54    /* Multi-driver Disable Register */
+#define PIO_MDSR        0x58    /* Multi-driver Status Register */
+#define PIO_PUDR        0x60    /* Pull-up Disable Register */
+#define PIO_PUER        0x64    /* Pull-up Enable Register */
+#define PIO_PUSR        0x68    /* Pull-up Status Register */
+#define PIO_ASR         0x70    /* Peripheral A Select Register */
+#define PIO_BSR         0x74    /* Peripheral B Select Register */
+#define PIO_ABSR        0x78    /* AB Status Register */
+#define PIO_OWER        0xa0    /* Output Write Enable Register */
+#define PIO_OWDR        0xa4    /* Output Write Disable Register */
+#define PIO_OWSR        0xa8    /* Output Write Status Register */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_pit.h b/include/asm-arm/arch-at91rm9200/at91_pit.h
new file mode 100644
index 000000000000..4a30d009c588
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_pit.h
@@ -0,0 +1,29 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_pit.h
+ *
+ * Periodic Interval Timer (PIT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIT_H
+#define AT91_PIT_H
+
+#define AT91_PIT_MR             (AT91_PIT + 0x00)       /* Mode Register */
+#define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
+#define         AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
+#define         AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
+
+#define AT91_PIT_SR             (AT91_PIT + 0x04)       /* Status Register */
+#define         AT91_PIT_PITS           (1 << 0)                /* Timer Status */
+
+#define AT91_PIT_PIVR           (AT91_PIT + 0x08)       /* Periodic Interval Value Register */
+#define AT91_PIT_PIIR           (AT91_PIT + 0x0c)       /* Periodic Interval Image Register */
+#define         AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
+#define         AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_pmc.h b/include/asm-arm/arch-at91rm9200/at91_pmc.h
new file mode 100644
index 000000000000..de8c3da74a01
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_pmc.h
@@ -0,0 +1,92 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_pmc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Power Management Controller (PMC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PMC_H
+#define AT91_PMC_H
+
+#define AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
+#define AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
+
+#define AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
+#define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
+#define         AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
+#define         AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
+#define         AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
+#define         AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
+#define         AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
+#define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
+#define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
+#define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
+#define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
+#define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
+#define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
+
+#define AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
+
+#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
+#define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
+#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [AT91SAM926x only] */
+#define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
+
+#define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
+#define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
+#define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
+
+#define AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
+#define AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
+#define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
+#define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
+#define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
+#define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
+#define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
+
+#define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
+#define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
+#define                 AT91_PMC_CSS_SLOW               (0 << 0)
+#define                 AT91_PMC_CSS_MAIN               (1 << 0)
+#define                 AT91_PMC_CSS_PLLA               (2 << 0)
+#define                 AT91_PMC_CSS_PLLB               (3 << 0)
+#define         AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
+#define                 AT91_PMC_PRES_1                 (0 << 2)
+#define                 AT91_PMC_PRES_2                 (1 << 2)
+#define                 AT91_PMC_PRES_4                 (2 << 2)
+#define                 AT91_PMC_PRES_8                 (3 << 2)
+#define                 AT91_PMC_PRES_16                (4 << 2)
+#define                 AT91_PMC_PRES_32                (5 << 2)
+#define                 AT91_PMC_PRES_64                (6 << 2)
+#define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
+#define                 AT91_PMC_MDIV_1                 (0 << 8)
+#define                 AT91_PMC_MDIV_2                 (1 << 8)
+#define                 AT91_PMC_MDIV_3                 (2 << 8)
+#define                 AT91_PMC_MDIV_4                 (3 << 8)
+
+#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
+
+#define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
+#define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
+#define AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
+#define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
+#define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
+#define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
+#define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
+#define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
+#define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
+#define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
+#define         AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
+#define AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_rstc.h b/include/asm-arm/arch-at91rm9200/at91_rstc.h
new file mode 100644
index 000000000000..ccdc52da973d
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_rstc.h
@@ -0,0 +1,39 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_rstc.h
+ *
+ * Reset Controller (RSTC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RSTC_H
+#define AT91_RSTC_H
+
+#define AT91_RSTC_CR            (AT91_RSTC + 0x00)      /* Reset Controller Control Register */
+#define         AT91_RSTC_PROCRST       (1 << 0)                /* Processor Reset */
+#define         AT91_RSTC_PERRST        (1 << 2)                /* Peripheral Reset */
+#define         AT91_RSTC_EXTRST        (1 << 3)                /* External Reset */
+#define         AT01_RSTC_KEY           (0xff << 24)            /* KEY Password */
+
+#define AT91_RSTC_SR            (AT91_RSTC + 0x04)      /* Reset Controller Status Register */
+#define         AT91_RSTC_URSTS         (1 << 0)                /* User Reset Status */
+#define         AT91_RSTC_RSTTYP        (7 << 8)                /* Reset Type */
+#define                 AT91_RSTC_RSTTYP_GENERAL        (0 << 8)
+#define                 AT91_RSTC_RSTTYP_WAKEUP         (1 << 8)
+#define                 AT91_RSTC_RSTTYP_WATCHDOG       (2 << 8)
+#define                 AT91_RSTC_RSTTYP_SOFTWARE       (3 << 8)
+#define                 AT91_RSTC_RSTTYP_USER   (4 << 8)
+#define         AT91_RSTC_NRSTL         (1 << 16)               /* NRST Pin Level */
+#define         AT91_RSTC_SRCMP         (1 << 17)               /* Software Reset Command in Progress */
+
+#define AT91_RSTC_MR            (AT91_RSTC + 0x08)      /* Reset Controller Mode Register */
+#define         AT91_RSTC_URSTEN        (1 << 0)                /* User Reset Enable */
+#define         AT91_RSTC_URSTIEN       (1 << 4)                /* User Reset Interrupt Enable */
+#define         AT91_RSTC_ERSTL         (0xf << 8)              /* External Reset Length */
+#define         AT91_RSTC_KEY           (0xff << 24)            /* KEY Password */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtc.h b/include/asm-arm/arch-at91rm9200/at91_rtc.h
new file mode 100644
index 000000000000..6e5065d56260
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_rtc.h
@@ -0,0 +1,75 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_rtc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Real Time Clock (RTC) - System peripheral registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RTC_H
+#define AT91_RTC_H
+
+#define AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
+#define         AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
+#define         AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
+#define         AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
+#define                 AT91_RTC_TIMEVSEL_MINUTE        (0 << 8)
+#define                 AT91_RTC_TIMEVSEL_HOUR          (1 << 8)
+#define                 AT91_RTC_TIMEVSEL_DAY24         (2 << 8)
+#define                 AT91_RTC_TIMEVSEL_DAY12         (3 << 8)
+#define         AT91_RTC_CALEVSEL       (3 << 16)               /* Calendar Event Selection */
+#define                 AT91_RTC_CALEVSEL_WEEK          (0 << 16)
+#define                 AT91_RTC_CALEVSEL_MONTH         (1 << 16)
+#define                 AT91_RTC_CALEVSEL_YEAR          (2 << 16)
+
+#define AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
+#define         AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
+
+#define AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
+#define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
+#define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
+#define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
+#define         AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
+
+#define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
+#define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
+#define         AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
+#define         AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
+#define         AT91_RTC_DAY            (7    << 21)            /* Current Day */
+#define         AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
+
+#define AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
+#define         AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
+#define         AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
+#define         AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
+
+#define AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
+#define         AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
+#define         AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
+
+#define AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
+#define         AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
+#define         AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
+#define         AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
+#define         AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
+#define         AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
+
+#define AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
+#define AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
+#define AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
+#define AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
+
+#define AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
+#define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
+#define         AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
+#define         AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
+#define         AT91_RTC_NVCALALR       (1 <<  3)               /* Non valid Calendar Alarm */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtt.h b/include/asm-arm/arch-at91rm9200/at91_rtt.h
new file mode 100644
index 000000000000..c6751ba3cccc
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_rtt.h
@@ -0,0 +1,32 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_rtt.h
+ *
+ * Real-time Timer (RTT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RTT_H
+#define AT91_RTT_H
+
+#define AT91_RTT_MR             (AT91_RTT + 0x00)       /* Real-time Mode Register */
+#define         AT91_RTT_RTPRES         (0xffff << 0)           /* Real-time Timer Prescaler Value */
+#define         AT91_RTT_ALMIEN         (1 << 16)               /* Alarm Interrupt Enable */
+#define         AT91_RTT_RTTINCIEN      (1 << 17)               /* Real Time Timer Increment Interrupt Enable */
+#define         AT91_RTT_RTTRST         (1 << 18)               /* Real Time Timer Restart */
+
+#define AT91_RTT_AR             (AT91_RTT + 0x04)       /* Real-time Alarm Register */
+#define         AT91_RTT_ALMV           (0xffffffff)            /* Alarm Value */
+
+#define AT91_RTT_VR             (AT91_RTT + 0x08)       /* Real-time Value Register */
+#define         AT91_RTT_CRTV           (0xffffffff)            /* Current Real-time Value */
+
+#define AT91_RTT_SR             (AT91_RTT + 0x0c)       /* Real-time Status Register */
+#define         AT91_RTT_ALMS           (1 << 0)                /* Real-time Alarm Status */
+#define         AT91_RTT_RTTINC         (1 << 1)                /* Real-time Timer Increment */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_shdwc.h b/include/asm-arm/arch-at91rm9200/at91_shdwc.h
new file mode 100644
index 000000000000..0439250553c9
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_shdwc.h
@@ -0,0 +1,33 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_shdwc.h
+ *
+ * Shutdown Controller (SHDWC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_SHDWC_H
+#define AT91_SHDWC_H
+
+#define AT91_SHDW_CR            (AT91_SHDWC + 0x00)     /* Shut Down Control Register */
+#define         AT91_SHDW_SHDW          (1    << 0)             /* Processor Reset */
+#define         AT91_SHDW_KEY           (0xff << 24)            /* KEY Password */
+
+#define AT91_SHDW_MR            (AT91_SHDWC + 0x04)     /* Shut Down Mode Register */
+#define         AT91_SHDW_WKMODE0       (3 << 0)                /* Wake-up 0 Mode Selection */
+#define                 AT91_SHDW_WKMODE0_NONE          0
+#define                 AT91_SHDW_WKMODE0_HIGH          1
+#define                 AT91_SHDW_WKMODE0_LOW           2
+#define                 AT91_SHDW_WKMODE0_ANYLEVEL      3
+#define         AT91_SHDW_CPTWK0        (0xf << 4)              /* Counter On Wake Up 0 */
+#define         AT91_SHDW_RTTWKEN       (1   << 16)             /* Real Time Timer Wake-up Enable */
+
+#define AT91_SHDW_SR            (AT91_SHDWC + 0x08)     /* Shut Down Status Register */
+#define         AT91_SHDW_WAKEUP0       (1 <<  0)               /* Wake-up 0 Status */
+#define         AT91_SHDW_RTTWK         (1 << 16)               /* Real-time Timer Wake-up */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h b/include/asm-arm/arch-at91rm9200/at91_spi.h
index bff5ea45f604..bec48ca89bba 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
+++ b/include/asm-arm/arch-at91rm9200/at91_spi.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
+ * include/asm-arm/arch-at91rm9200/at91_spi.h
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
@@ -13,8 +13,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_SPI_H
-#define AT91RM9200_SPI_H
+#ifndef AT91_SPI_H
+#define AT91_SPI_H
 
 #define AT91_SPI_CR                     0x00            /* Control Register */
 #define         AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */
@@ -28,7 +28,7 @@
 #define                 AT91_SPI_PS_FIXED       (0 << 1)
 #define                 AT91_SPI_PS_VARIABLE    (1 << 1)
 #define         AT91_SPI_PCSDEC         (1    <<  2)            /* Chip Select Decode */
-#define         AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection */
+#define         AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection [AT91RM9200 only] */
 #define         AT91_SPI_MODFDIS        (1    <<  4)            /* Mode Fault Detection */
 #define         AT91_SPI_LLB            (1    <<  7)            /* Local Loopback Enable */
 #define         AT91_SPI_PCS            (0xf  << 16)            /* Peripheral Chip Select */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h b/include/asm-arm/arch-at91rm9200/at91_ssc.h
index ac880227147f..694bcaa8f7c2 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_ssc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
+ * include/asm-arm/arch-at91rm9200/at91_ssc.h
  *
  * Copyright (C) SAN People
  *
@@ -12,8 +12,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_SSC_H
-#define AT91RM9200_SSC_H
+#ifndef AT91_SSC_H
+#define AT91_SSC_H
 
 #define AT91_SSC_CR             0x00    /* Control Register */
 #define         AT91_SSC_RXEN           (1 <<  0)       /* Receive Enable */
@@ -36,6 +36,10 @@
 #define         AT91_SSC_CKI            (1    <<  5)    /* Clock Inversion */
 #define                 AT91_SSC_CKI_FALLING            (0 << 5)
 #define                 AT91_SSC_CK_RISING              (1 << 5)
+#define         AT91_SSC_CKG            (1    <<  6)    /* Receive Clock Gating Selection [AT91SAM9261 only] */
+#define                 AT91_SSC_CKG_NONE               (0 << 6)
+#define                 AT91_SSC_CKG_RFLOW              (1 << 6)
+#define                 AT91_SSC_CKG_RFHIGH             (2 << 6)
 #define         AT91_SSC_START          (0xf  <<  8)    /* Start Selection */
 #define                 AT91_SSC_START_CONTINUOUS       (0 << 8)
 #define                 AT91_SSC_START_TX_RX            (1 << 8)
@@ -45,6 +49,7 @@
 #define                 AT91_SSC_START_RISING_RF        (5 << 8)
 #define                 AT91_SSC_START_LEVEL_RF         (6 << 8)
 #define                 AT91_SSC_START_EDGE_RF          (7 << 8)
+#define         AT91_SSC_STOP           (1    << 12)    /* Receive Stop Selection [AT91SAM9261 only] */
 #define         AT91_SSC_STTDLY         (0xff << 16)    /* Start Delay */
 #define         AT91_SSC_PERIOD         (0xff << 24)    /* Period Divider Selection */
 
@@ -75,6 +80,9 @@
 #define AT91_SSC_RSHR           0x30    /* Receive Sync Holding Register */
 #define AT91_SSC_TSHR           0x34    /* Transmit Sync Holding Register */
 
+#define AT91_SSC_RC0R           0x38    /* Receive Compare 0 Register [AT91SAM9261 only] */
+#define AT91_SSC_RC1R           0x3c    /* Receive Compare 1 Register [AT91SAM9261 only] */
+
 #define AT91_SSC_SR             0x40    /* Status Register */
 #define         AT91_SSC_TXRDY          (1 <<  0)       /* Transmit Ready */
 #define         AT91_SSC_TXEMPTY        (1 <<  1)       /* Transmit Empty */
@@ -84,6 +92,8 @@
 #define         AT91_SSC_OVRUN          (1 <<  5)       /* Receive Overrun */
 #define         AT91_SSC_ENDRX          (1 <<  6)       /* End of Reception */
 #define         AT91_SSC_RXBUFF         (1 <<  7)       /* Receive Buffer Full */
+#define         AT91_SSC_CP0            (1 <<  8)       /* Compare 0 [AT91SAM9261 only] */
+#define         AT91_SSC_CP1            (1 <<  9)       /* Compare 1 [AT91SAM9261 only] */
 #define         AT91_SSC_TXSYN          (1 << 10)       /* Transmit Sync */
 #define         AT91_SSC_RXSYN          (1 << 11)       /* Receive Sync */
 #define         AT91_SSC_TXENA          (1 << 16)       /* Transmit Enable */
diff --git a/include/asm-arm/arch-at91rm9200/at91_st.h b/include/asm-arm/arch-at91rm9200/at91_st.h
new file mode 100644
index 000000000000..2432ddfc6c47
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_st.h
@@ -0,0 +1,49 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_st.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * System Timer (ST) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_ST_H
+#define AT91_ST_H
+
+#define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
+#define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
+
+#define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
+#define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
+
+#define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
+#define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
+#define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
+#define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
+
+#define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
+#define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
+
+#define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
+#define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
+#define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
+#define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
+#define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
+
+#define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
+#define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
+#define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
+
+#define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
+#define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
+
+#define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
+#define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h b/include/asm-arm/arch-at91rm9200/at91_tc.h
index f4da752bb0c8..8d06eb078e1d 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_tc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
+ * include/asm-arm/arch-at91rm9200/at91_tc.h
  *
  * Copyright (C) SAN People
  *
@@ -12,8 +12,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_TC_H
-#define AT91RM9200_TC_H
+#ifndef AT91_TC_H
+#define AT91_TC_H
 
 #define AT91_TC_BCR             0xc0            /* TC Block Control Register */
 #define         AT91_TC_SYNC            (1 << 0)        /* Synchro Command */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h b/include/asm-arm/arch-at91rm9200/at91_twi.h
index 93547d7482bd..cda914f1e740 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
+++ b/include/asm-arm/arch-at91rm9200/at91_twi.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
+ * include/asm-arm/arch-at91rm9200/at91_twi.h
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
@@ -13,8 +13,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_TWI_H
-#define AT91RM9200_TWI_H
+#ifndef AT91_TWI_H
+#define AT91_TWI_H
 
 #define AT91_TWI_CR             0x00            /* Control Register */
 #define         AT91_TWI_START          (1 <<  0)       /* Send a Start Condition */
@@ -43,8 +43,8 @@
 #define         AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
 #define         AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
 #define         AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
-#define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error */
-#define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error */
+#define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error [AT91RM9200 only] */
+#define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error [AT91RM9200 only] */
 #define         AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
 
 #define AT91_TWI_IER            0x24            /* Interrupt Enable Register */
diff --git a/include/asm-arm/arch-at91rm9200/at91_wdt.h b/include/asm-arm/arch-at91rm9200/at91_wdt.h
new file mode 100644
index 000000000000..ac63e775772c
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_wdt.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91_wdt.h
+ *
+ * Watchdog Timer (WDT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_WDT_H
+#define AT91_WDT_H
+
+#define AT91_WDT_CR             (AT91_WDT + 0x00)       /* Watchdog Control Register */
+#define         AT91_WDT_WDRSTT         (1    << 0)             /* Restart */
+#define         AT91_WDT_KEY            (0xff << 24)            /* KEY Password */
+
+#define AT91_WDT_MR             (AT91_WDT + 0x04)       /* Watchdog Mode Register */
+#define         AT91_WDT_WDV            (0xfff << 0)            /* Counter Value */
+#define         AT91_WDT_WDFIEN         (1     << 12)           /* Fault Interrupt Enable */
+#define         AT91_WDT_WDRSTEN        (1     << 13)           /* Reset Processor */
+#define         AT91_WDT_WDRPROC        (1     << 14)           /* Timer Restart */
+#define         AT91_WDT_WDDIS          (1     << 15)           /* Watchdog Disable */
+#define         AT91_WDT_WDD            (0xfff << 16)           /* Delta Value */
+#define         AT91_WDT_WDDBGHLT       (1     << 28)           /* Debug Halt */
+#define         AT91_WDT_WDIDLEHLT      (1     << 29)           /* Idle Halt */
+
+#define AT91_WDT_SR             (AT91_WDT + 0x08)       /* Watchdog Status Register */
+#define         AT91_WDT_WDUNF          (1 << 0)                /* Watchdog Underflow */
+#define         AT91_WDT_WDERR          (1 << 1)                /* Watchdog Error */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
index a5a86b1ff886..4d51177efddd 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -80,6 +80,22 @@
 
 
 /*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)    /* Debug Unit */
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)    /* PIO Controller A */
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)    /* PIO Controller B */
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)    /* PIO Controller C */
+#define AT91_PIOD       (0xfffffa00 - AT91_BASE_SYS)    /* PIO Controller D */
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)    /* Power Management Controller */
+#define AT91_ST         (0xfffffd00 - AT91_BASE_SYS)    /* System Timer */
+#define AT91_RTC        (0xfffffe00 - AT91_BASE_SYS)    /* Real-Time Clock */
+#define AT91_MC         (0xffffff00 - AT91_BASE_SYS)    /* Memory Controllers */
+
+#define AT91_MATRIX     0       /* not supported */
+
+/*
  * Internal Memory.
  */
 #define AT91RM9200_ROM_BASE     0x00100000      /* Internal ROM base address */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
new file mode 100644
index 000000000000..0c0d81480b3a
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
@@ -0,0 +1,160 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_MC_H
+#define AT91RM9200_MC_H
+
+/* Memory Controller */
+#define AT91_MC_RCR             (AT91_MC + 0x00)        /* MC Remap Control Register */
+#define         AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
+
+#define AT91_MC_ASR             (AT91_MC + 0x04)        /* MC Abort Status Register */
+#define         AT91_MC_UNADD           (1 <<  0)               /* Undefined Address Abort Status */
+#define         AT91_MC_MISADD          (1 <<  1)               /* Misaligned Address Abort Status */
+#define         AT91_MC_ABTSZ           (3 <<  8)               /* Abort Size Status */
+#define                 AT91_MC_ABTSZ_BYTE              (0 << 8)
+#define                 AT91_MC_ABTSZ_HALFWORD          (1 << 8)
+#define                 AT91_MC_ABTSZ_WORD              (2 << 8)
+#define         AT91_MC_ABTTYP          (3 << 10)               /* Abort Type Status */
+#define                 AT91_MC_ABTTYP_DATAREAD         (0 << 10)
+#define                 AT91_MC_ABTTYP_DATAWRITE        (1 << 10)
+#define                 AT91_MC_ABTTYP_FETCH            (2 << 10)
+#define         AT91_MC_MST0            (1 << 16)               /* ARM920T Abort Source */
+#define         AT91_MC_MST1            (1 << 17)               /* PDC Abort Source */
+#define         AT91_MC_MST2            (1 << 18)               /* UHP Abort Source */
+#define         AT91_MC_MST3            (1 << 19)               /* EMAC Abort Source */
+#define         AT91_MC_SVMST0          (1 << 24)               /* Saved ARM920T Abort Source */
+#define         AT91_MC_SVMST1          (1 << 25)               /* Saved PDC Abort Source */
+#define         AT91_MC_SVMST2          (1 << 26)               /* Saved UHP Abort Source */
+#define         AT91_MC_SVMST3          (1 << 27)               /* Saved EMAC Abort Source */
+
+#define AT91_MC_AASR            (AT91_MC + 0x08)        /* MC Abort Address Status Register */
+
+#define AT91_MC_MPR             (AT91_MC + 0x0c)        /* MC Master Priority Register */
+#define         AT91_MPR_MSTP0          (7 <<  0)               /* ARM920T Priority */
+#define         AT91_MPR_MSTP1          (7 <<  4)               /* PDC Priority */
+#define         AT91_MPR_MSTP2          (7 <<  8)               /* UHP Priority */
+#define         AT91_MPR_MSTP3          (7 << 12)               /* EMAC Priority */
+
+/* External Bus Interface (EBI) registers */
+#define AT91_EBI_CSA            (AT91_MC + 0x60)        /* Chip Select Assignment Register */
+#define         AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
+#define                 AT91_EBI_CS0A_SMC               (0 << 0)
+#define                 AT91_EBI_CS0A_BFC               (1 << 0)
+#define         AT91_EBI_CS1A           (1 << 1)                /* Chip Select 1 Assignment */
+#define                 AT91_EBI_CS1A_SMC               (0 << 1)
+#define                 AT91_EBI_CS1A_SDRAMC            (1 << 1)
+#define         AT91_EBI_CS3A           (1 << 3)                /* Chip Select 2 Assignment */
+#define                 AT91_EBI_CS3A_SMC               (0 << 3)
+#define                 AT91_EBI_CS3A_SMC_SMARTMEDIA    (1 << 3)
+#define         AT91_EBI_CS4A           (1 << 4)                /* Chip Select 3 Assignment */
+#define                 AT91_EBI_CS4A_SMC               (0 << 4)
+#define                 AT91_EBI_CS4A_SMC_COMPACTFLASH  (1 << 4)
+#define AT91_EBI_CFGR           (AT91_MC + 0x64)        /* Configuration Register */
+#define         AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
+
+/* Static Memory Controller (SMC) registers */
+#define AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
+#define         AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
+#define                 AT91_SMC_NWS_(x)        ((x) << 0)
+#define         AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
+#define         AT91_SMC_TDF            (0xf  <<  8)            /* Data Float Time */
+#define                 AT91_SMC_TDF_(x)        ((x) << 8)
+#define         AT91_SMC_BAT            (1    << 12)            /* Byte Access Type */
+#define         AT91_SMC_DBW            (3    << 13)            /* Data Bus Width */
+#define                 AT91_SMC_DBW_16         (1 << 13)
+#define                 AT91_SMC_DBW_8          (2 << 13)
+#define         AT91_SMC_DPR            (1 << 15)               /* Data Read Protocol */
+#define         AT91_SMC_ACSS           (3 << 16)               /* Address to Chip Select Setup */
+#define                 AT91_SMC_ACSS_STD       (0 << 16)
+#define                 AT91_SMC_ACSS_1         (1 << 16)
+#define                 AT91_SMC_ACSS_2         (2 << 16)
+#define                 AT91_SMC_ACSS_3         (3 << 16)
+#define         AT91_SMC_RWSETUP        (7 << 24)               /* Read & Write Signal Time Setup */
+#define                 AT91_SMC_RWSETUP_(x)    ((x) << 24)
+#define         AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
+#define                 AT91_SMC_RWHOLD_(x)     ((x) << 28)
+
+/* SDRAM Controller registers */
+#define AT91_SDRAMC_MR          (AT91_MC + 0x90)        /* Mode Register */
+#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
+#define                 AT91_SDRAMC_MODE_NORMAL         (0 << 0)
+#define                 AT91_SDRAMC_MODE_NOP            (1 << 0)
+#define                 AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
+#define                 AT91_SDRAMC_MODE_LMR            (3 << 0)
+#define                 AT91_SDRAMC_MODE_REFRESH        (4 << 0)
+#define         AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
+#define                 AT91_SDRAMC_DBW_32      (0 << 4)
+#define                 AT91_SDRAMC_DBW_16      (1 << 4)
+
+#define AT91_SDRAMC_TR          (AT91_MC + 0x94)        /* Refresh Timer Register */
+#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
+
+#define AT91_SDRAMC_CR          (AT91_MC + 0x98)        /* Configuration Register */
+#define         AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
+#define                 AT91_SDRAMC_NC_8        (0 << 0)
+#define                 AT91_SDRAMC_NC_9        (1 << 0)
+#define                 AT91_SDRAMC_NC_10       (2 << 0)
+#define                 AT91_SDRAMC_NC_11       (3 << 0)
+#define         AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
+#define                 AT91_SDRAMC_NR_11       (0 << 2)
+#define                 AT91_SDRAMC_NR_12       (1 << 2)
+#define                 AT91_SDRAMC_NR_13       (2 << 2)
+#define         AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
+#define                 AT91_SDRAMC_NB_2        (0 << 4)
+#define                 AT91_SDRAMC_NB_4        (1 << 4)
+#define         AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
+#define                 AT91_SDRAMC_CAS_2       (2 << 5)
+#define         AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
+#define         AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
+#define         AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
+#define         AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
+#define         AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
+#define         AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_SRR         (AT91_MC + 0x9c)        /* Self Refresh Register */
+#define AT91_SDRAMC_LPR         (AT91_MC + 0xa0)        /* Low Power Register */
+#define AT91_SDRAMC_IER         (AT91_MC + 0xa4)        /* Interrupt Enable Register */
+#define AT91_SDRAMC_IDR         (AT91_MC + 0xa8)        /* Interrupt Disable Register */
+#define AT91_SDRAMC_IMR         (AT91_MC + 0xac)        /* Interrupt Mask Register */
+#define AT91_SDRAMC_ISR         (AT91_MC + 0xb0)        /* Interrupt Status Register */
+
+/* Burst Flash Controller register */
+#define AT91_BFC_MR             (AT91_MC + 0xc0)        /* Mode Register */
+#define         AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */
+#define                 AT91_BFC_BFCOM_DISABLED (0 << 0)
+#define                 AT91_BFC_BFCOM_ASYNC    (1 << 0)
+#define                 AT91_BFC_BFCOM_BURST    (2 << 0)
+#define         AT91_BFC_BFCC           (3   <<  2)             /* Burst Flash Controller Clock */
+#define                 AT91_BFC_BFCC_MCK       (1 << 2)
+#define                 AT91_BFC_BFCC_DIV2      (2 << 2)
+#define                 AT91_BFC_BFCC_DIV4      (3 << 2)
+#define         AT91_BFC_AVL            (0xf <<  4)             /* Address Valid Latency */
+#define         AT91_BFC_PAGES          (7   <<  8)             /* Page Size */
+#define                 AT91_BFC_PAGES_NO_PAGE  (0 << 8)
+#define                 AT91_BFC_PAGES_16       (1 << 8)
+#define                 AT91_BFC_PAGES_32       (2 << 8)
+#define                 AT91_BFC_PAGES_64       (3 << 8)
+#define                 AT91_BFC_PAGES_128      (4 << 8)
+#define                 AT91_BFC_PAGES_256      (5 << 8)
+#define                 AT91_BFC_PAGES_512      (6 << 8)
+#define                 AT91_BFC_PAGES_1024     (7 << 8)
+#define         AT91_BFC_OEL            (3   << 12)             /* Output Enable Latency */
+#define         AT91_BFC_BAAEN          (1   << 16)             /* Burst Address Advance Enable */
+#define         AT91_BFC_BFOEH          (1   << 17)             /* Burst Flash Output Enable Handling */
+#define         AT91_BFC_MUXEN          (1   << 18)             /* Multiplexed Bus Enable */
+#define         AT91_BFC_RDYEN          (1   << 19)             /* Ready Enable Mode */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
deleted file mode 100644
index 73693fea76a2..000000000000
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
- * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_SYS_H
-#define AT91RM9200_SYS_H
-
-/*
- * Advanced Interrupt Controller.
- */
-#define AT91_AIC        0x000
-
-#define AT91_AIC_SMR(n)         (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
-#define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
-#define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
-#define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
-#define                 AT91_AIC_SRCTYPE_FALLING        (1 << 5)
-#define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
-#define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
-
-#define AT91_AIC_SVR(n)         (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
-#define AT91_AIC_IVR            (AT91_AIC + 0x100)      /* Interrupt Vector Register */
-#define AT91_AIC_FVR            (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
-#define AT91_AIC_ISR            (AT91_AIC + 0x108)      /* Interrupt Status Register */
-#define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
-
-#define AT91_AIC_IPR            (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
-#define AT91_AIC_IMR            (AT91_AIC + 0x110)      /* Interrupt Mask Register */
-#define AT91_AIC_CISR           (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
-#define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
-#define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
-
-#define AT91_AIC_IECR           (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
-#define AT91_AIC_IDCR           (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
-#define AT91_AIC_ICCR           (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
-#define AT91_AIC_ISCR           (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
-#define AT91_AIC_EOICR          (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
-#define AT91_AIC_SPU            (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
-#define AT91_AIC_DCR            (AT91_AIC + 0x138)      /* Debug Control Register */
-#define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
-#define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
-
-
-/*
- * Debug Unit.
- */
-#define AT91_DBGU       0x200
-
-#define AT91_DBGU_CR            (AT91_DBGU + 0x00)      /* Control Register */
-#define AT91_DBGU_MR            (AT91_DBGU + 0x04)      /* Mode Register */
-#define AT91_DBGU_IER           (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
-#define         AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
-#define         AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
-#define AT91_DBGU_IDR           (AT91_DBGU + 0x0c)      /* Interrupt Disable Register */
-#define AT91_DBGU_IMR           (AT91_DBGU + 0x10)      /* Interrupt Mask Register */
-#define AT91_DBGU_SR            (AT91_DBGU + 0x14)      /* Status Register */
-#define AT91_DBGU_RHR           (AT91_DBGU + 0x18)      /* Receiver Holding Register */
-#define AT91_DBGU_THR           (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
-#define AT91_DBGU_BRGR          (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
-
-#define AT91_DBGU_CIDR          (AT91_DBGU + 0x40)      /* Chip ID Register */
-#define AT91_DBGU_EXID          (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
-#define         AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
-#define         AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
-#define         AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
-#define         AT91_CIDR_NVPSIZ2       (0xf  << 12)            /* Second Nonvolatile Program Memory Size */
-#define         AT91_CIDR_SRAMSIZ       (0xf  << 16)            /* Internal SRAM Size */
-#define         AT91_CIDR_ARCH          (0xff << 20)            /* Architecture Identifier */
-#define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
-#define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
-
-#define AT91_AIC_FFER           (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
-#define AT91_AIC_FFDR           (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
-#define AT91_AIC_FFSR           (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
-
-/*
- * PIO Controllers.
- */
-#define AT91_PIOA       0x400
-#define AT91_PIOB       0x600
-#define AT91_PIOC       0x800
-#define AT91_PIOD       0xa00
-
-#define PIO_PER         0x00    /* Enable Register */
-#define PIO_PDR         0x04    /* Disable Register */
-#define PIO_PSR         0x08    /* Status Register */
-#define PIO_OER         0x10    /* Output Enable Register */
-#define PIO_ODR         0x14    /* Output Disable Register */
-#define PIO_OSR         0x18    /* Output Status Register */
-#define PIO_IFER        0x20    /* Glitch Input Filter Enable */
-#define PIO_IFDR        0x24    /* Glitch Input Filter Disable */
-#define PIO_IFSR        0x28    /* Glitch Input Filter Status */
-#define PIO_SODR        0x30    /* Set Output Data Register */
-#define PIO_CODR        0x34    /* Clear Output Data Register */
-#define PIO_ODSR        0x38    /* Output Data Status Register */
-#define PIO_PDSR        0x3c    /* Pin Data Status Register */
-#define PIO_IER         0x40    /* Interrupt Enable Register */
-#define PIO_IDR         0x44    /* Interrupt Disable Register */
-#define PIO_IMR         0x48    /* Interrupt Mask Register */
-#define PIO_ISR         0x4c    /* Interrupt Status Register */
-#define PIO_MDER        0x50    /* Multi-driver Enable Register */
-#define PIO_MDDR        0x54    /* Multi-driver Disable Register */
-#define PIO_MDSR        0x58    /* Multi-driver Status Register */
-#define PIO_PUDR        0x60    /* Pull-up Disable Register */
-#define PIO_PUER        0x64    /* Pull-up Enable Register */
-#define PIO_PUSR        0x68    /* Pull-up Status Register */
-#define PIO_ASR         0x70    /* Peripheral A Select Register */
-#define PIO_BSR         0x74    /* Peripheral B Select Register */
-#define PIO_ABSR        0x78    /* AB Status Register */
-#define PIO_OWER        0xa0    /* Output Write Enable Register */
-#define PIO_OWDR        0xa4    /* Output Write Disable Register */
-#define PIO_OWSR        0xa8    /* Output Write Status Register */
-
-#define AT91_PIO_P(n)   (1 << (n))
-
-
-/*
- * Power Management Controller.
- */
-#define AT91_PMC        0xc00
-
-#define AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
-#define AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
-
-#define AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
-#define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
-#define         AT91_PMC_UDP            (1 <<  1)               /* USB Devcice Port Clock */
-#define         AT91_PMC_MCKUDP         (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend */
-#define         AT91_PMC_UHP            (1 <<  4)               /* USB Host Port Clock */
-#define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
-#define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
-#define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
-#define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
-
-#define AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
-#define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
-#define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
-
-#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
-#define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
-#define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
-
-#define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
-#define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
-#define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
-
-#define AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
-#define AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
-#define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
-#define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
-#define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
-#define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
-#define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
-
-#define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
-#define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
-#define                 AT91_PMC_CSS_SLOW               (0 << 0)
-#define                 AT91_PMC_CSS_MAIN               (1 << 0)
-#define                 AT91_PMC_CSS_PLLA               (2 << 0)
-#define                 AT91_PMC_CSS_PLLB               (3 << 0)
-#define         AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
-#define                 AT91_PMC_PRES_1                 (0 << 2)
-#define                 AT91_PMC_PRES_2                 (1 << 2)
-#define                 AT91_PMC_PRES_4                 (2 << 2)
-#define                 AT91_PMC_PRES_8                 (3 << 2)
-#define                 AT91_PMC_PRES_16                (4 << 2)
-#define                 AT91_PMC_PRES_32                (5 << 2)
-#define                 AT91_PMC_PRES_64                (6 << 2)
-#define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
-#define                 AT91_PMC_MDIV_1                 (0 << 8)
-#define                 AT91_PMC_MDIV_2                 (1 << 8)
-#define                 AT91_PMC_MDIV_3                 (2 << 8)
-#define                 AT91_PMC_MDIV_4                 (3 << 8)
-
-#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
-
-#define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
-#define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
-#define AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
-#define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
-#define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
-#define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
-#define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
-#define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
-#define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
-#define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
-#define         AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
-#define AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
-
-
-/*
- * System Timer.
- */
-#define AT91_ST         0xd00
-
-#define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
-#define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
-#define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
-#define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
-#define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
-#define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
-#define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
-#define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
-#define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
-#define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
-#define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
-#define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
-#define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
-#define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
-#define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
-#define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
-#define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
-#define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
-#define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
-#define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
-#define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
-#define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
-
-
-/*
- * Real-time Clock.
- */
-#define AT91_RTC        0xe00
-
-#define AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
-#define         AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
-#define         AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
-#define         AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
-#define                 AT91_RTC_TIMEVSEL_MINUTE        (0 << 8)
-#define                 AT91_RTC_TIMEVSEL_HOUR          (1 << 8)
-#define                 AT91_RTC_TIMEVSEL_DAY24         (2 << 8)
-#define                 AT91_RTC_TIMEVSEL_DAY12         (3 << 8)
-#define         AT91_RTC_CALEVSEL       (3 << 16)               /* Calendar Event Selection */
-#define                 AT91_RTC_CALEVSEL_WEEK          (0 << 16)
-#define                 AT91_RTC_CALEVSEL_MONTH         (1 << 16)
-#define                 AT91_RTC_CALEVSEL_YEAR          (2 << 16)
-
-#define AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
-#define         AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
-
-#define AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
-#define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
-#define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
-#define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
-#define         AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
-
-#define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
-#define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
-#define         AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
-#define         AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
-#define         AT91_RTC_DAY            (7    << 21)            /* Current Day */
-#define         AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
-
-#define AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
-#define         AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
-#define         AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
-#define         AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
-
-#define AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
-#define         AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
-#define         AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
-
-#define AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
-#define         AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
-#define         AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
-#define         AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
-#define         AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
-#define         AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
-
-#define AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
-#define AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
-#define AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
-#define AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
-
-#define AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
-#define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
-#define         AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
-#define         AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
-#define         AT91_RTC_NVCALALR       (1 <<  3)               /* Non valid Calendar Alarm */
-
-
-/*
- * Memory Controller.
- */
-#define AT91_MC         0xf00
-
-#define AT91_MC_RCR             (AT91_MC + 0x00)        /* MC Remap Control Register */
-#define         AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
-
-#define AT91_MC_ASR             (AT91_MC + 0x04)        /* MC Abort Status Register */
-#define         AT91_MC_UNADD           (1 <<  0)               /* Undefined Address Abort Status */
-#define         AT91_MC_MISADD          (1 <<  1)               /* Misaligned Address Abort Status */
-#define         AT91_MC_ABTSZ           (3 <<  8)               /* Abort Size Status */
-#define                 AT91_MC_ABTSZ_BYTE              (0 << 8)
-#define                 AT91_MC_ABTSZ_HALFWORD          (1 << 8)
-#define                 AT91_MC_ABTSZ_WORD              (2 << 8)
-#define         AT91_MC_ABTTYP          (3 << 10)               /* Abort Type Status */
-#define                 AT91_MC_ABTTYP_DATAREAD         (0 << 10)
-#define                 AT91_MC_ABTTYP_DATAWRITE        (1 << 10)
-#define                 AT91_MC_ABTTYP_FETCH            (2 << 10)
-#define         AT91_MC_MST0            (1 << 16)               /* ARM920T Abort Source */
-#define         AT91_MC_MST1            (1 << 17)               /* PDC Abort Source */
-#define         AT91_MC_MST2            (1 << 18)               /* UHP Abort Source */
-#define         AT91_MC_MST3            (1 << 19)               /* EMAC Abort Source */
-#define         AT91_MC_SVMST0          (1 << 24)               /* Saved ARM920T Abort Source */
-#define         AT91_MC_SVMST1          (1 << 25)               /* Saved PDC Abort Source */
-#define         AT91_MC_SVMST2          (1 << 26)               /* Saved UHP Abort Source */
-#define         AT91_MC_SVMST3          (1 << 27)               /* Saved EMAC Abort Source */
-
-#define AT91_MC_AASR            (AT91_MC + 0x08)        /* MC Abort Address Status Register */
-
-#define AT91_MC_MPR             (AT91_MC + 0x0c)        /* MC Master Priority Register */
-#define         AT91_MPR_MSTP0          (7 <<  0)               /* ARM920T Priority */
-#define         AT91_MPR_MSTP1          (7 <<  4)               /* PDC Priority */
-#define         AT91_MPR_MSTP2          (7 <<  8)               /* UHP Priority */
-#define         AT91_MPR_MSTP3          (7 << 12)               /* EMAC Priority */
-
-/* External Bus Interface (EBI) registers */
-#define AT91_EBI_CSA            (AT91_MC + 0x60)        /* Chip Select Assignment Register */
-#define         AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
-#define                 AT91_EBI_CS0A_SMC               (0 << 0)
-#define                 AT91_EBI_CS0A_BFC               (1 << 0)
-#define         AT91_EBI_CS1A           (1 << 1)                /* Chip Select 1 Assignment */
-#define                 AT91_EBI_CS1A_SMC               (0 << 1)
-#define                 AT91_EBI_CS1A_SDRAMC            (1 << 1)
-#define         AT91_EBI_CS3A           (1 << 3)                /* Chip Select 2 Assignment */
-#define                 AT91_EBI_CS3A_SMC               (0 << 3)
-#define                 AT91_EBI_CS3A_SMC_SMARTMEDIA    (1 << 3)
-#define         AT91_EBI_CS4A           (1 << 4)                /* Chip Select 3 Assignment */
-#define                 AT91_EBI_CS4A_SMC               (0 << 4)
-#define                 AT91_EBI_CS4A_SMC_COMPACTFLASH  (1 << 4)
-#define AT91_EBI_CFGR           (AT91_MC + 0x64)        /* Configuration Register */
-#define         AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
-
-/* Static Memory Controller (SMC) registers */
-#define AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
-#define         AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
-#define                 AT91_SMC_NWS_(x)        ((x) << 0)
-#define         AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
-#define         AT91_SMC_TDF            (0xf  <<  8)            /* Data Float Time */
-#define                 AT91_SMC_TDF_(x)        ((x) << 8)
-#define         AT91_SMC_BAT            (1    << 12)            /* Byte Access Type */
-#define         AT91_SMC_DBW            (3    << 13)            /* Data Bus Width */
-#define                 AT91_SMC_DBW_16         (1 << 13)
-#define                 AT91_SMC_DBW_8          (2 << 13)
-#define         AT91_SMC_DPR            (1 << 15)               /* Data Read Protocol */
-#define         AT91_SMC_ACSS           (3 << 16)               /* Address to Chip Select Setup */
-#define                 AT91_SMC_ACSS_STD       (0 << 16)
-#define                 AT91_SMC_ACSS_1         (1 << 16)
-#define                 AT91_SMC_ACSS_2         (2 << 16)
-#define                 AT91_SMC_ACSS_3         (3 << 16)
-#define         AT91_SMC_RWSETUP        (7 << 24)               /* Read & Write Signal Time Setup */
-#define                 AT91_SMC_RWSETUP_(x)    ((x) << 24)
-#define         AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
-#define                 AT91_SMC_RWHOLD_(x)     ((x) << 28)
-
-/* SDRAM Controller registers */
-#define AT91_SDRAMC_MR          (AT91_MC + 0x90)        /* Mode Register */
-#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
-#define                 AT91_SDRAMC_MODE_NORMAL         (0 << 0)
-#define                 AT91_SDRAMC_MODE_NOP            (1 << 0)
-#define                 AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
-#define                 AT91_SDRAMC_MODE_LMR            (3 << 0)
-#define                 AT91_SDRAMC_MODE_REFRESH        (4 << 0)
-#define         AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
-#define                 AT91_SDRAMC_DBW_32      (0 << 4)
-#define                 AT91_SDRAMC_DBW_16      (1 << 4)
-
-#define AT91_SDRAMC_TR          (AT91_MC + 0x94)        /* Refresh Timer Register */
-#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
-
-#define AT91_SDRAMC_CR          (AT91_MC + 0x98)        /* Configuration Register */
-#define         AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
-#define                 AT91_SDRAMC_NC_8        (0 << 0)
-#define                 AT91_SDRAMC_NC_9        (1 << 0)
-#define                 AT91_SDRAMC_NC_10       (2 << 0)
-#define                 AT91_SDRAMC_NC_11       (3 << 0)
-#define         AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
-#define                 AT91_SDRAMC_NR_11       (0 << 2)
-#define                 AT91_SDRAMC_NR_12       (1 << 2)
-#define                 AT91_SDRAMC_NR_13       (2 << 2)
-#define         AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
-#define                 AT91_SDRAMC_NB_2        (0 << 4)
-#define                 AT91_SDRAMC_NB_4        (1 << 4)
-#define         AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
-#define                 AT91_SDRAMC_CAS_2       (2 << 5)
-#define         AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
-#define         AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
-#define         AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
-#define         AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
-#define         AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
-#define         AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_SRR         (AT91_MC + 0x9c)        /* Self Refresh Register */
-#define AT91_SDRAMC_LPR         (AT91_MC + 0xa0)        /* Low Power Register */
-#define AT91_SDRAMC_IER         (AT91_MC + 0xa4)        /* Interrupt Enable Register */
-#define AT91_SDRAMC_IDR         (AT91_MC + 0xa8)        /* Interrupt Disable Register */
-#define AT91_SDRAMC_IMR         (AT91_MC + 0xac)        /* Interrupt Mask Register */
-#define AT91_SDRAMC_ISR         (AT91_MC + 0xb0)        /* Interrupt Status Register */
-
-/* Burst Flash Controller register */
-#define AT91_BFC_MR             (AT91_MC + 0xc0)        /* Mode Register */
-#define         AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */
-#define                 AT91_BFC_BFCOM_DISABLED (0 << 0)
-#define                 AT91_BFC_BFCOM_ASYNC    (1 << 0)
-#define                 AT91_BFC_BFCOM_BURST    (2 << 0)
-#define         AT91_BFC_BFCC           (3   <<  2)             /* Burst Flash Controller Clock */
-#define                 AT91_BFC_BFCC_MCK       (1 << 2)
-#define                 AT91_BFC_BFCC_DIV2      (2 << 2)
-#define                 AT91_BFC_BFCC_DIV4      (3 << 2)
-#define         AT91_BFC_AVL            (0xf <<  4)             /* Address Valid Latency */
-#define         AT91_BFC_PAGES          (7   <<  8)             /* Page Size */
-#define                 AT91_BFC_PAGES_NO_PAGE  (0 << 8)
-#define                 AT91_BFC_PAGES_16       (1 << 8)
-#define                 AT91_BFC_PAGES_32       (2 << 8)
-#define                 AT91_BFC_PAGES_64       (3 << 8)
-#define                 AT91_BFC_PAGES_128      (4 << 8)
-#define                 AT91_BFC_PAGES_256      (5 << 8)
-#define                 AT91_BFC_PAGES_512      (6 << 8)
-#define                 AT91_BFC_PAGES_1024     (7 << 8)
-#define         AT91_BFC_OEL            (3   << 12)             /* Output Enable Latency */
-#define         AT91_BFC_BAAEN          (1   << 16)             /* Burst Address Advance Enable */
-#define         AT91_BFC_BFOEH          (1   << 17)             /* Burst Flash Output Enable Handling */
-#define         AT91_BFC_MUXEN          (1   << 18)             /* Multiplexed Bus Enable */
-#define         AT91_BFC_RDYEN          (1   << 19)             /* Ready Enable Mode */
-
-#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h b/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
deleted file mode 100644
index 951e3f61cef4..000000000000
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * USB Device Port (UDP) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_UDP_H
-#define AT91RM9200_UDP_H
-
-#define AT91_UDP_FRM_NUM        0x00            /* Frame Number Register */
-#define         AT91_UDP_NUM            (0x7ff <<  0)           /* Frame Number */
-#define         AT91_UDP_FRM_ERR        (1     << 16)           /* Frame Error */
-#define         AT91_UDP_FRM_OK         (1     << 17)           /* Frame OK */
-
-#define AT91_UDP_GLB_STAT       0x04            /* Global State Register */
-#define         AT91_UDP_FADDEN         (1 <<  0)               /* Function Address Enable */
-#define         AT91_UDP_CONFG          (1 <<  1)               /* Configured */
-#define         AT91_UDP_ESR            (1 <<  2)               /* Enable Send Resume */
-#define         AT91_UDP_RSMINPR        (1 <<  3)               /* Resume has been sent */
-#define         AT91_UDP_RMWUPE         (1 <<  4)               /* Remote Wake Up Enable */
-
-#define AT91_UDP_FADDR          0x08            /* Function Address Register */
-#define         AT91_UDP_FADD           (0x7f << 0)             /* Function Address Value */
-#define         AT91_UDP_FEN            (1    << 8)             /* Function Enable */
-
-#define AT91_UDP_IER            0x10            /* Interrupt Enable Register */
-#define AT91_UDP_IDR            0x14            /* Interrupt Disable Register */
-#define AT91_UDP_IMR            0x18            /* Interrupt Mask Register */
-
-#define AT91_UDP_ISR            0x1c            /* Interrupt Status Register */
-#define         AT91_UDP_EP(n)          (1 << (n))              /* Endpoint Interrupt Status */
-#define         AT91_UDP_RXSUSP         (1 <<  8)               /* USB Suspend Interrupt Status */
-#define         AT91_UDP_RXRSM          (1 <<  9)               /* USB Resume Interrupt Status */
-#define         AT91_UDP_EXTRSM         (1 << 10)               /* External Resume Interrupt Status */
-#define         AT91_UDP_SOFINT         (1 << 11)               /* Start of Frame Interrupt Status */
-#define         AT91_UDP_ENDBUSRES      (1 << 12)               /* End of Bus Reset Interrpt Status */
-#define         AT91_UDP_WAKEUP         (1 << 13)               /* USB Wakeup Interrupt Status */
-
-#define AT91_UDP_ICR            0x20            /* Interrupt Clear Register */
-#define AT91_UDP_RST_EP         0x28            /* Reset Endpoint Register */
-
-#define AT91_UDP_CSR(n)         (0x30 + ((n) * 4))      /* Endpoint Control/Status Registers 0-7 */
-#define         AT91_UDP_TXCOMP         (1 <<  0)               /* Generates IN packet with data previously written in DPR */
-#define         AT91_UDP_RX_DATA_BK0    (1 <<  1)               /* Receive Data Bank 0 */
-#define         AT91_UDP_RXSETUP        (1 <<  2)               /* Send STALL to the host */
-#define         AT91_UDP_STALLSENT      (1 <<  3)               /* Stall Sent / Isochronous error (Isochronous endpoints) */
-#define         AT91_UDP_TXPKTRDY       (1 <<  4)               /* Transmit Packet Ready */
-#define         AT91_UDP_FORCESTALL     (1 <<  5)               /* Force Stall */
-#define         AT91_UDP_RX_DATA_BK1    (1 <<  6)               /* Receive Data Bank 1 */
-#define         AT91_UDP_DIR            (1 <<  7)               /* Transfer Direction */
-#define         AT91_UDP_EPTYPE         (7 <<  8)               /* Endpoint Type */
-#define                 AT91_UDP_EPTYPE_CTRL            (0 <<  8)
-#define                 AT91_UDP_EPTYPE_ISO_OUT         (1 <<  8)
-#define                 AT91_UDP_EPTYPE_BULK_OUT        (2 <<  8)
-#define                 AT91_UDP_EPTYPE_INT_OUT         (3 <<  8)
-#define                 AT91_UDP_EPTYPE_ISO_IN          (5 <<  8)
-#define                 AT91_UDP_EPTYPE_BULK_IN         (6 <<  8)
-#define                 AT91_UDP_EPTYPE_INT_IN          (7 <<  8)
-#define         AT91_UDP_DTGLE          (1 << 11)               /* Data Toggle */
-#define         AT91_UDP_EPEDS          (1 << 15)               /* Endpoint Enable/Disable */
-#define         AT91_UDP_RXBYTECNT      (0x7ff << 16)           /* Number of bytes in FIFO */
-
-#define AT91_UDP_FDR(n)         (0x50 + ((n) * 4))      /* Endpoint FIFO Data Registers 0-7 */
-
-#define AT91_UDP_TXVC           0x74            /* Transceiver Control Register */
-#define         AT91_UDP_TXVC_TXVDIS    (1 << 8)                /* Transceiver Disable */
-
-#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260.h b/include/asm-arm/arch-at91rm9200/at91sam9260.h
new file mode 100644
index 000000000000..46f4dd65c035
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9260.h
@@ -0,0 +1,125 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91sam9260.h
+ *
+ * (C) 2006 Andrew Victor
+ *
+ * Common definitions.
+ * Based on AT91SAM9260 datasheet revision A (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9260_H
+#define AT91SAM9260_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT91SAM9260_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT91SAM9260_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT91SAM9260_ID_PIOC     4       /* Parallel IO Controller C */
+#define AT91SAM9260_ID_ADC      5       /* Analog-to-Digital Converter */
+#define AT91SAM9260_ID_US0      6       /* USART 0 */
+#define AT91SAM9260_ID_US1      7       /* USART 1 */
+#define AT91SAM9260_ID_US2      8       /* USART 2 */
+#define AT91SAM9260_ID_MCI      9       /* Multimedia Card Interface */
+#define AT91SAM9260_ID_UDP      10      /* USB Device Port */
+#define AT91SAM9260_ID_TWI      11      /* Two-Wire Interface */
+#define AT91SAM9260_ID_SPI0     12      /* Serial Peripheral Interface 0 */
+#define AT91SAM9260_ID_SPI1     13      /* Serial Peripheral Interface 1 */
+#define AT91SAM9260_ID_SSC      14      /* Serial Synchronous Controller */
+#define AT91SAM9260_ID_TC0      17      /* Timer Counter 0 */
+#define AT91SAM9260_ID_TC1      18      /* Timer Counter 1 */
+#define AT91SAM9260_ID_TC2      19      /* Timer Counter 2 */
+#define AT91SAM9260_ID_UHP      20      /* USB Host port */
+#define AT91SAM9260_ID_EMAC     21      /* Ethernet */
+#define AT91SAM9260_ID_ISI      22      /* Image Sensor Interface */
+#define AT91SAM9260_ID_US3      23      /* USART 3 */
+#define AT91SAM9260_ID_US4      24      /* USART 4 */
+#define AT91SAM9260_ID_US5      25      /* USART 5 */
+#define AT91SAM9260_ID_TC3      26      /* Timer Counter 3 */
+#define AT91SAM9260_ID_TC4      27      /* Timer Counter 4 */
+#define AT91SAM9260_ID_TC5      28      /* Timer Counter 5 */
+#define AT91SAM9260_ID_IRQ0     29      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9260_ID_IRQ1     30      /* Advanced Interrupt Controller (IRQ1) */
+#define AT91SAM9260_ID_IRQ2     31      /* Advanced Interrupt Controller (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9260_BASE_TCB0           0xfffa0000
+#define AT91SAM9260_BASE_TC0            0xfffa0000
+#define AT91SAM9260_BASE_TC1            0xfffa0040
+#define AT91SAM9260_BASE_TC2            0xfffa0080
+#define AT91SAM9260_BASE_UDP            0xfffa4000
+#define AT91SAM9260_BASE_MCI            0xfffa8000
+#define AT91SAM9260_BASE_TWI            0xfffac000
+#define AT91SAM9260_BASE_US0            0xfffb0000
+#define AT91SAM9260_BASE_US1            0xfffb4000
+#define AT91SAM9260_BASE_US2            0xfffb8000
+#define AT91SAM9260_BASE_SSC            0xfffbc000
+#define AT91SAM9260_BASE_ISI            0xfffc0000
+#define AT91SAM9260_BASE_EMAC           0xfffc4000
+#define AT91SAM9260_BASE_SPI0           0xfffc8000
+#define AT91SAM9260_BASE_SPI1           0xfffcc000
+#define AT91SAM9260_BASE_US3            0xfffd0000
+#define AT91SAM9260_BASE_US4            0xfffd4000
+#define AT91SAM9260_BASE_US5            0xfffd8000
+#define AT91SAM9260_BASE_TCB1           0xfffdc000
+#define AT91SAM9260_BASE_TC3            0xfffdc000
+#define AT91SAM9260_BASE_TC4            0xfffdc040
+#define AT91SAM9260_BASE_TC5            0xfffdc080
+#define AT91SAM9260_BASE_ADC            0xfffe0000
+#define AT91_BASE_SYS                   0xffffe800
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9260_ROM_BASE    0x00100000      /* Internal ROM base address */
+#define AT91SAM9260_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT91SAM9260_SRAM0_BASE  0x00200000      /* Internal SRAM 0 base address */
+#define AT91SAM9260_SRAM0_SIZE  SZ_4K           /* Internal SRAM 0 size (4Kb) */
+#define AT91SAM9260_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
+#define AT91SAM9260_SRAM1_SIZE  SZ_4K           /* Internal SRAM 1 size (4Kb) */
+
+#define AT91SAM9260_UHP_BASE    0x00500000      /* USB Host controller */
+
+#if 0
+/*
+ * PIO pin definitions (peripheral A/B multiplexing).
+ */
+
+// TODO: Add
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
new file mode 100644
index 000000000000..746d973705bf
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
@@ -0,0 +1,78 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9260 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9260_MATRIX_H
+#define AT91SAM9260_MATRIX_H
+
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x04)    /* Master Configuration Register 5 */
+#define         AT91_MATRIX_ULBT                (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff <<  0)    /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_CS1A                (1 << 1)         /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define         AT91_MATRIX_CS5A                (1 << 5 )       /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+#define         AT91_MATRIX_VDDIOMSEL           (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
+#define                 AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261.h b/include/asm-arm/arch-at91rm9200/at91sam9261.h
new file mode 100644
index 000000000000..8d39672d5b82
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9261.h
@@ -0,0 +1,292 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91sam9261.h
+ *
+ * Copyright (C) SAN People
+ *
+ * Common definitions.
+ * Based on AT91SAM9261 datasheet revision E. (Preliminary)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9261_H
+#define AT91SAM9261_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT91SAM9261_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT91SAM9261_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT91SAM9261_ID_PIOC     4       /* Parallel IO Controller C */
+#define AT91SAM9261_ID_US0      6       /* USART 0 */
+#define AT91SAM9261_ID_US1      7       /* USART 1 */
+#define AT91SAM9261_ID_US2      8       /* USART 2 */
+#define AT91SAM9261_ID_MCI      9       /* Multimedia Card Interface */
+#define AT91SAM9261_ID_UDP      10      /* USB Device Port */
+#define AT91SAM9261_ID_TWI      11      /* Two-Wire Interface */
+#define AT91SAM9261_ID_SPI0     12      /* Serial Peripheral Interface 0 */
+#define AT91SAM9261_ID_SPI1     13      /* Serial Peripheral Interface 1 */
+#define AT91SAM9261_ID_SSC0     14      /* Serial Synchronous Controller 0 */
+#define AT91SAM9261_ID_SSC1     15      /* Serial Synchronous Controller 1 */
+#define AT91SAM9261_ID_SSC2     16      /* Serial Synchronous Controller 2 */
+#define AT91SAM9261_ID_TC0      17      /* Timer Counter 0 */
+#define AT91SAM9261_ID_TC1      18      /* Timer Counter 1 */
+#define AT91SAM9261_ID_TC2      19      /* Timer Counter 2 */
+#define AT91SAM9261_ID_UHP      20      /* USB Host port */
+#define AT91SAM9261_ID_LCDC     21      /* LDC Controller */
+#define AT91SAM9261_ID_IRQ0     29      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9261_ID_IRQ1     30      /* Advanced Interrupt Controller (IRQ1) */
+#define AT91SAM9261_ID_IRQ2     31      /* Advanced Interrupt Controller (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9261_BASE_TCB0           0xfffa0000
+#define AT91SAM9261_BASE_TC0            0xfffa0000
+#define AT91SAM9261_BASE_TC1            0xfffa0040
+#define AT91SAM9261_BASE_TC2            0xfffa0080
+#define AT91SAM9261_BASE_UDP            0xfffa4000
+#define AT91SAM9261_BASE_MCI            0xfffa8000
+#define AT91SAM9261_BASE_TWI            0xfffac000
+#define AT91SAM9261_BASE_US0            0xfffb0000
+#define AT91SAM9261_BASE_US1            0xfffb4000
+#define AT91SAM9261_BASE_US2            0xfffb8000
+#define AT91SAM9261_BASE_SSC0           0xfffbc000
+#define AT91SAM9261_BASE_SSC1           0xfffc0000
+#define AT91SAM9261_BASE_SSC2           0xfffc4000
+#define AT91SAM9261_BASE_SPI0           0xfffc8000
+#define AT91SAM9261_BASE_SPI1           0xfffcc000
+#define AT91_BASE_SYS                   0xffffea00
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9261_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT91SAM9261_SRAM_SIZE   0x00028000      /* Internal SRAM size (160Kb) */
+
+#define AT91SAM9261_ROM_BASE    0x00400000      /* Internal ROM base address */
+#define AT91SAM9261_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT91SAM9261_UHP_BASE    0x00500000      /* USB Host controller */
+#define AT91SAM9261_LCDC_BASE   0x00600000      /* LDC controller */
+
+
+#if 0
+/*
+ * PIO pin definitions (peripheral A/B multiplexing).
+ */
+#define AT91_PA0_SPI0_MISO      (1 <<  0)       /* A: SPI0 Master In Slave */
+#define AT91_PA0_MCDA0          (1 <<  0)       /* B: Multimedia Card A Data 0 */
+#define AT91_PA1_SPI0_MOSI      (1 <<  1)       /* A: SPI0 Master Out Slave */
+#define AT91_PA1_MCCDA          (1 <<  1)       /* B: Multimedia Card A Command */
+#define AT91_PA2_SPI0_SPCK      (1 <<  2)       /* A: SPI0 Serial Clock */
+#define AT91_PA2_MCCK           (1 <<  2)       /* B: Multimedia Card Clock */
+#define AT91_PA3_SPI0_NPCS0     (1 <<  3)       /* A: SPI0 Peripheral Chip Select 0 */
+#define AT91_PA4_SPI0_NPCS1     (1 <<  4)       /* A: SPI0 Peripheral Chip Select 1 */
+#define AT91_PA4_MCDA1          (1 <<  4)       /* B: Multimedia Card A Data 1 */
+#define AT91_PA5_SPI0_NPCS2     (1 <<  5)       /* A: SPI0 Peripheral Chip Select 2 */
+#define AT91_PA5_MCDA2          (1 <<  5)       /* B: Multimedia Card A Data 2 */
+#define AT91_PA6_SPI0_NPCS3     (1 <<  6)       /* A: SPI0 Peripheral Chip Select 3 */
+#define AT91_PA6_MCDA3          (1 <<  6)       /* B: Multimedia Card A Data 3 */
+#define AT91_PA7_TWD            (1 <<  7)       /* A: TWI Two-wire Serial Data */
+#define AT91_PA7_PCK0           (1 <<  7)       /* B: PMC Programmable clock Output 0 */
+#define AT91_PA8_TWCK           (1 <<  8)       /* A: TWI Two-wire Serial Clock */
+#define AT91_PA8_PCK1           (1 <<  8)       /* B: PMC Programmable clock Output 1 */
+#define AT91_PA9_DRXD           (1 <<  9)       /* A: DBGU Debug Receive Data */
+#define AT91_PA9_PCK2           (1 <<  9)       /* B: PMC Programmable clock Output 2 */
+#define AT91_PA10_DTXD          (1 << 10)       /* A: DBGU Debug Transmit Data */
+#define AT91_PA10_PCK3          (1 << 10)       /* B: PMC Programmable clock Output 3 */
+#define AT91_PA11_TSYNC         (1 << 11)       /* A: Trace Synchronization Signal */
+#define AT91_PA11_SCK1          (1 << 11)       /* B: USART1 Serial Clock */
+#define AT91_PA12_TCLK          (1 << 12)       /* A: Trace Clock */
+#define AT91_PA12_RTS1          (1 << 12)       /* B: USART1 Ready To Send */
+#define AT91_PA13_TPS0          (1 << 13)       /* A: Trace ARM Pipeline Status 0 */
+#define AT91_PA13_CTS1          (1 << 13)       /* B: USART1 Clear To Send */
+#define AT91_PA14_TPS1          (1 << 14)       /* A: Trace ARM Pipeline Status 1 */
+#define AT91_PA14_SCK2          (1 << 14)       /* B: USART2 Serial Clock */
+#define AT91_PA15_TPS2          (1 << 15)       /* A: Trace ARM Pipeline Status 2 */
+#define AT91_PA15_RTS2          (1 << 15)       /* B: USART2 Ready To Send */
+#define AT91_PA16_TPK0          (1 << 16)       /* A: Trace Packet Port 0 */
+#define AT91_PA16_CTS2          (1 << 16)       /* B: USART2 Clear To Send */
+#define AT91_PA17_TPK1          (1 << 17)       /* A: Trace Packet Port 1 */
+#define AT91_PA17_TF1           (1 << 17)       /* B: SSC1 Transmit Frame Sync */
+#define AT91_PA18_TPK2          (1 << 18)       /* A: Trace Packet Port 2 */
+#define AT91_PA18_TK1           (1 << 18)       /* B: SSC1 Transmit Clock */
+#define AT91_PA19_TPK3          (1 << 19)       /* A: Trace Packet Port 3 */
+#define AT91_PA19_TD1           (1 << 19)       /* B: SSC1 Transmit Data */
+#define AT91_PA20_TPK4          (1 << 20)       /* A: Trace Packet Port 4 */
+#define AT91_PA20_RD1           (1 << 20)       /* B: SSC1 Receive Data */
+#define AT91_PA21_TPK5          (1 << 21)       /* A: Trace Packet Port 5 */
+#define AT91_PA21_RK1           (1 << 21)       /* B: SSC1 Receive Clock */
+#define AT91_PA22_TPK6          (1 << 22)       /* A: Trace Packet Port 6 */
+#define AT91_PA22_RF1           (1 << 22)       /* B: SSC1 Receive Frame Sync */
+#define AT91_PA23_TPK7          (1 << 23)       /* A: Trace Packet Port 7 */
+#define AT91_PA23_RTS0          (1 << 23)       /* B: USART0 Ready To Send */
+#define AT91_PA24_TPK8          (1 << 24)       /* A: Trace Packet Port 8 */
+#define AT91_PA24_SPI1_NPCS1    (1 << 24)       /* B: SPI1 Peripheral Chip Select 1 */
+#define AT91_PA25_TPK9          (1 << 25)       /* A: Trace Packet Port 9 */
+#define AT91_PA25_SPI1_NPCS2    (1 << 25)       /* B: SPI1 Peripheral Chip Select 2 */
+#define AT91_PA26_TPK10         (1 << 26)       /* A: Trace Packet Port 10 */
+#define AT91_PA26_SPI1_NPCS3    (1 << 26)       /* B: SPI1 Peripheral Chip Select 3 */
+#define AT91_PA27_TPK11         (1 << 27)       /* A: Trace Packet Port 11 */
+#define AT91_PA27_SPI0_NPCS1    (1 << 27)       /* B: SPI0 Peripheral Chip Select 1 */
+#define AT91_PA28_TPK12         (1 << 28)       /* A: Trace Packet Port 12 */
+#define AT91_PA28_SPI0_NPCS2    (1 << 28)       /* B: SPI0 Peripheral Chip Select 2 */
+#define AT91_PA29_TPK13         (1 << 29)       /* A: Trace Packet Port 13 */
+#define AT91_PA29_SPI0_NPCS3    (1 << 29)       /* B: SPI0 Peripheral Chip Select 3 */
+#define AT91_PA30_TPK14         (1 << 30)       /* A: Trace Packet Port 14 */
+#define AT91_PA30_A23           (1 << 30)       /* B: Address Bus bit 23 */
+#define AT91_PA31_TPK15         (1 << 31)       /* A: Trace Packet Port 15 */
+#define AT91_PA31_A24           (1 << 31)       /* B: Address Bus bit 24 */
+
+#define AT91_PB0_LCDVSYNC       (1 <<  0)       /* A: LCD Vertical Synchronization */
+#define AT91_PB1_LCDHSYNC       (1 <<  1)       /* A: LCD Horizontal Synchronization */
+#define AT91_PB2_LCDDOTCK       (1 <<  2)       /* A: LCD Dot Clock */
+#define AT91_PB2_PCK0           (1 <<  2)       /* B: PMC Programmable clock Output 0 */
+#define AT91_PB3_LCDDEN         (1 <<  3)       /* A: LCD Data Enable */
+#define AT91_PB4_LCDCC          (1 <<  4)       /* A: LCD Contrast Control */
+#define AT91_PB4_LCDD2          (1 <<  4)       /* B: LCD Data Bus Bit 2 */
+#define AT91_PB5_LCDD0          (1 <<  5)       /* A: LCD Data Bus Bit 0 */
+#define AT91_PB5_LCDD3          (1 <<  5)       /* B: LCD Data Bus Bit 3 */
+#define AT91_PB6_LCDD1          (1 <<  6)       /* A: LCD Data Bus Bit 1 */
+#define AT91_PB6_LCDD4          (1 <<  6)       /* B: LCD Data Bus Bit 4 */
+#define AT91_PB7_LCDD2          (1 <<  7)       /* A: LCD Data Bus Bit 2 */
+#define AT91_PB7_LCDD5          (1 <<  7)       /* B: LCD Data Bus Bit 5 */
+#define AT91_PB8_LCDD3          (1 <<  8)       /* A: LCD Data Bus Bit 3 */
+#define AT91_PB8_LCDD6          (1 <<  8)       /* B: LCD Data Bus Bit 6 */
+#define AT91_PB9_LCDD4          (1 <<  9)       /* A: LCD Data Bus Bit 4 */
+#define AT91_PB9_LCDD7          (1 <<  9)       /* B: LCD Data Bus Bit 7 */
+#define AT91_PB10_LCDD5         (1 << 10)       /* A: LCD Data Bus Bit 5 */
+#define AT91_PB10_LCDD10        (1 << 10)       /* B: LCD Data Bus Bit 10 */
+#define AT91_PB11_LCDD6         (1 << 11)       /* A: LCD Data Bus Bit 6 */
+#define AT91_PB11_LCDD11        (1 << 11)       /* B: LCD Data Bus Bit 11 */
+#define AT91_PB12_LCDD7         (1 << 12)       /* A: LCD Data Bus Bit 7 */
+#define AT91_PB12_LCDD12        (1 << 12)       /* B: LCD Data Bus Bit 12 */
+#define AT91_PB13_LCDD8         (1 << 13)       /* A: LCD Data Bus Bit 8 */
+#define AT91_PB13_LCDD13        (1 << 13)       /* B: LCD Data Bus Bit 13 */
+#define AT91_PB14_LCDD9         (1 << 14)       /* A: LCD Data Bus Bit 9 */
+#define AT91_PB14_LCDD14        (1 << 14)       /* B: LCD Data Bus Bit 14 */
+#define AT91_PB15_LCDD10        (1 << 15)       /* A: LCD Data Bus Bit 10 */
+#define AT91_PB15_LCDD15        (1 << 15)       /* B: LCD Data Bus Bit 15 */
+#define AT91_PB16_LCDD11        (1 << 16)       /* A: LCD Data Bus Bit 11 */
+#define AT91_PB16_LCDD19        (1 << 16)       /* B: LCD Data Bus Bit 19 */
+#define AT91_PB17_LCDD12        (1 << 17)       /* A: LCD Data Bus Bit 12 */
+#define AT91_PB17_LCDD20        (1 << 17)       /* B: LCD Data Bus Bit 20 */
+#define AT91_PB18_LCDD13        (1 << 18)       /* A: LCD Data Bus Bit 13 */
+#define AT91_PB18_LCDD21        (1 << 18)       /* B: LCD Data Bus Bit 21 */
+#define AT91_PB19_LCDD14        (1 << 19)       /* A: LCD Data Bus Bit 14 */
+#define AT91_PB19_LCDD22        (1 << 19)       /* B: LCD Data Bus Bit 22 */
+#define AT91_PB20_LCDD15        (1 << 20)       /* A: LCD Data Bus Bit 15 */
+#define AT91_PB20_LCDD23        (1 << 20)       /* B: LCD Data Bus Bit 23 */
+#define AT91_PB21_TF0           (1 << 21)       /* A: SSC0 Transmit Frame Sync */
+#define AT91_PB21_LCDD16        (1 << 21)       /* B: LCD Data Bus Bit 16 */
+#define AT91_PB22_TK0           (1 << 22)       /* A: SSC0 Transmit Clock */
+#define AT91_PB22_LCDD17        (1 << 22)       /* B: LCD Data Bus Bit 17 */
+#define AT91_PB23_TD0           (1 << 23)       /* A: SSC0 Transmit Data */
+#define AT91_PB23_LCDD18        (1 << 23)       /* B: LCD Data Bus Bit 18 */
+#define AT91_PB24_RD0           (1 << 24)       /* A: SSC0 Receive Data */
+#define AT91_PB24_LCDD19        (1 << 24)       /* B: LCD Data Bus Bit 19 */
+#define AT91_PB25_RK0           (1 << 25)       /* A: SSC0 Receive Clock */
+#define AT91_PB25_LCDD20        (1 << 25)       /* B: LCD Data Bus Bit 20 */
+#define AT91_PB26_RF0           (1 << 26)       /* A: SSC0 Receive Frame Sync */
+#define AT91_PB26_LCDD21        (1 << 26)       /* B: LCD Data Bus Bit 21 */
+#define AT91_PB27_SPI1_NPCS1    (1 << 27)       /* A: SPI1 Peripheral Chip Select 1 */
+#define AT91_PB27_LCDD22        (1 << 27)       /* B: LCD Data Bus Bit 22 */
+#define AT91_PB28_SPI1_NPCS0    (1 << 28)       /* A: SPI1 Peripheral Chip Select 0 */
+#define AT91_PB28_LCDD23        (1 << 28)       /* B: LCD Data Bus Bit 23 */
+#define AT91_PB29_SPI1_SPCK     (1 << 29)       /* A: SPI1 Serial Clock */
+#define AT91_PB29_IRQ2          (1 << 29)       /* B: Interrupt input 2 */
+#define AT91_PB30_SPI1_MISO     (1 << 30)       /* A: SPI1 Master In Slave */
+#define AT91_PB30_IRQ1          (1 << 30)       /* B: Interrupt input 1 */
+#define AT91_PB31_SPI1_MOSI     (1 << 31)       /* A: SPI1 Master Out Slave */
+#define AT91_PB31_PCK2          (1 << 31)       /* B: PMC Programmable clock Output 2 */
+
+#define AT91_PC0_SMOE           (1 << 0)        /* A: SmartMedia Output Enable */
+#define AT91_PC0_NCS6           (1 << 0)        /* B: Chip Select 6 */
+#define AT91_PC1_SMWE           (1 << 1)        /* A: SmartMedia Write Enable */
+#define AT91_PC1_NCS7           (1 << 1)        /* B: Chip Select 7 */
+#define AT91_PC2_NWAIT          (1 << 2)        /* A: NWAIT */
+#define AT91_PC2_IRQ0           (1 << 2)        /* B: Interrupt input 0 */
+#define AT91_PC3_A25_CFRNW      (1 << 3)        /* A: Address Bus[25] / Compact Flash Read Not Write */
+#define AT91_PC4_NCS4_CFCS0     (1 << 4)        /* A: Chip Select 4 / CompactFlash Chip Select 0 */
+#define AT91_PC5_NCS5_CFCS1     (1 << 5)        /* A: Chip Select 5 / CompactFlash Chip Select 1 */
+#define AT91_PC6_CFCE1          (1 << 6)        /* A: CompactFlash Chip Enable 1 */
+#define AT91_PC7_CFCE2          (1 << 7)        /* A: CompactFlash Chip Enable 2 */
+#define AT91_PC8_TXD0           (1 << 8)        /* A: USART0 Transmit Data */
+#define AT91_PC8_PCK2           (1 << 8)        /* B: PMC Programmable clock Output 2 */
+#define AT91_PC9_RXD0           (1 << 9)        /* A: USART0 Receive Data */
+#define AT91_PC9_PCK3           (1 << 9)        /* B: PMC Programmable clock Output 3 */
+#define AT91_PC10_RTS0          (1 << 10)       /* A: USART0 Ready To Send */
+#define AT91_PC10_SCK0          (1 << 10)       /* B: USART0 Serial Clock */
+#define AT91_PC11_CTS0          (1 << 11)       /* A: USART0 Clear To Send */
+#define AT91_PC11_FIQ           (1 << 11)       /* B: AIC Fast Interrupt Input */
+#define AT91_PC12_TXD1          (1 << 12)       /* A: USART1 Transmit Data */
+#define AT91_PC12_NCS6          (1 << 12)       /* B: Chip Select 6 */
+#define AT91_PC13_RXD1          (1 << 13)       /* A: USART1 Receive Data */
+#define AT91_PC13_NCS7          (1 << 13)       /* B: Chip Select 7 */
+#define AT91_PC14_TXD2          (1 << 14)       /* A: USART2 Transmit Data */
+#define AT91_PC14_SPI1_NPCS2    (1 << 14)       /* B: SPI1 Peripheral Chip Select 2 */
+#define AT91_PC15_RXD2          (1 << 15)       /* A: USART2 Receive Data */
+#define AT91_PC15_SPI1_NPCS3    (1 << 15)       /* B: SPI1 Peripheral Chip Select 3 */
+#define AT91_PC16_D16           (1 << 16)       /* A: Data Bus [16] */
+#define AT91_PC16_TCLK0         (1 << 16)       /* B: Timer Counter 0 external clock input */
+#define AT91_PC17_D17           (1 << 17)       /* A: Data Bus [17] */
+#define AT91_PC17_TCLK1         (1 << 17)       /* B: Timer Counter 1 external clock input */
+#define AT91_PC18_D18           (1 << 18)       /* A: Data Bus [18] */
+#define AT91_PC18_TCLK2         (1 << 18)       /* B: Timer Counter 2 external clock input */
+#define AT91_PC19_D19           (1 << 19)       /* A: Data Bus [19] */
+#define AT91_PC19_TIOA0         (1 << 19)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
+#define AT91_PC20_D20           (1 << 20)       /* A: Data Bus [20] */
+#define AT91_PC20_TIOB0         (1 << 20)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
+#define AT91_PC21_D21           (1 << 21)       /* A: Data Bus [21] */
+#define AT91_PC21_TIOA1         (1 << 21)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
+#define AT91_PC22_D22           (1 << 22)       /* A: Data Bus [22] */
+#define AT91_PC22_TIOB1         (1 << 22)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
+#define AT91_PC23_D23           (1 << 23)       /* A: Data Bus [23] */
+#define AT91_PC23_TIOA2         (1 << 23)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
+#define AT91_PC24_D24           (1 << 24)       /* A: Data Bus [24] */
+#define AT91_PC24_TIOB2         (1 << 24)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
+#define AT91_PC25_D25           (1 << 25)       /* A: Data Bus [25] */
+#define AT91_PC25_TF2           (1 << 25)       /* B: SSC2 Transmit Frame Sync */
+#define AT91_PC26_D26           (1 << 26)       /* A: Data Bus [26] */
+#define AT91_PC26_TK2           (1 << 26)       /* B: SSC2 Transmit Clock */
+#define AT91_PC27_D27           (1 << 27)       /* A: Data Bus [27] */
+#define AT91_PC27_TD2           (1 << 27)       /* B: SSC2 Transmit Data */
+#define AT91_PC28_D28           (1 << 28)       /* A: Data Bus [28] */
+#define AT91_PC28_RD2           (1 << 28)       /* B: SSC2 Receive Data */
+#define AT91_PC29_D29           (1 << 29)       /* A: Data Bus [29] */
+#define AT91_PC29_RK2           (1 << 29)       /* B: SSC2 Receive Clock */
+#define AT91_PC30_D30           (1 << 30)       /* A: Data Bus [30] */
+#define AT91_PC30_RF2           (1 << 30)       /* B: SSC2 Receive Frame Sync */
+#define AT91_PC31_D31           (1 << 31)       /* A: Data Bus [31] */
+#define AT91_PC31_PCK1          (1 << 31)       /* B: PMC Programmable clock Output 1 */
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
new file mode 100644
index 000000000000..270a5dcdf1cd
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
@@ -0,0 +1,62 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9261_MATRIX_H
+#define AT91SAM9261_MATRIX_H
+
+#define AT91_MATRIX_MCFG        (AT91_MATRIX + 0x00)    /* Master Configuration Register */
+#define         AT91_MATRIX_RCB0        (1 << 0)                /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT01_MATRIX_RCB1        (1 << 1)                /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x04)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x08)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x0C)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x10)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x14)    /* Slave Configuration Register 4 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
+
+#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x24)    /* TCM Configuration Register */
+#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                 AT91_MATRIX_ITCM_0              (0 << 0)
+#define                 AT91_MATRIX_ITCM_16             (5 << 0)
+#define                 AT91_MATRIX_ITCM_32             (6 << 0)
+#define                 AT91_MATRIX_ITCM_64             (7 << 0)
+#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                 AT91_MATRIX_DTCM_0              (0 << 4)
+#define                 AT91_MATRIX_DTCM_16             (5 << 4)
+#define                 AT91_MATRIX_DTCM_32             (6 << 4)
+#define                 AT91_MATRIX_DTCM_64             (7 << 4)
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x30)    /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+
+#define AT91_MATRIX_USBPUCR     (AT91_MATRIX + 0x34)    /* USB Pad Pull-Up Control Register */
+#define         AT91_MATRIX_USBPUCR_PUON        (1 << 30)       /* USB Device PAD Pull-up Enable */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
new file mode 100644
index 000000000000..7d94968b5d57
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
@@ -0,0 +1,134 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
+ *
+ * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM926x_MC_H
+#define AT91SAM926x_MC_H
+
+/* SDRAM Controller (SDRAMC) registers */
+#define AT91_SDRAMC_MR          (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
+#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
+#define                 AT91_SDRAMC_MODE_NORMAL         0
+#define                 AT91_SDRAMC_MODE_NOP            1
+#define                 AT91_SDRAMC_MODE_PRECHARGE      2
+#define                 AT91_SDRAMC_MODE_LMR            3
+#define                 AT91_SDRAMC_MODE_REFRESH        4
+#define                 AT91_SDRAMC_MODE_EXT_LMR        5
+#define                 AT91_SDRAMC_MODE_DEEP           6
+
+#define AT91_SDRAMC_TR          (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
+#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_SDRAMC_CR          (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
+#define         AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
+#define                 AT91_SDRAMC_NC_8        (0 << 0)
+#define                 AT91_SDRAMC_NC_9        (1 << 0)
+#define                 AT91_SDRAMC_NC_10       (2 << 0)
+#define                 AT91_SDRAMC_NC_11       (3 << 0)
+#define         AT91_SDRAMC_NR          (3 << 2)                /* Number of Row Bits */
+#define                 AT91_SDRAMC_NR_11       (0 << 2)
+#define                 AT91_SDRAMC_NR_12       (1 << 2)
+#define                 AT91_SDRAMC_NR_13       (2 << 2)
+#define         AT91_SDRAMC_NB          (1 << 4)                /* Number of Banks */
+#define                 AT91_SDRAMC_NB_2        (0 << 4)
+#define                 AT91_SDRAMC_NB_4        (1 << 4)
+#define         AT91_SDRAMC_CAS         (3 << 5)                /* CAS Latency */
+#define                 AT91_SDRAMC_CAS_1       (1 << 5)
+#define                 AT91_SDRAMC_CAS_2       (2 << 5)
+#define                 AT91_SDRAMC_CAS_3       (3 << 5)
+#define         AT91_SDRAMC_DBW         (1 << 7)                /* Data Bus Width */
+#define                 AT91_SDRAMC_DBW_32      (0 << 7)
+#define                 AT91_SDRAMC_DBW_16      (1 << 7)
+#define         AT91_SDRAMC_TWR         (0xf <<  8)             /* Write Recovery Delay */
+#define         AT91_SDRAMC_TRC         (0xf << 12)             /* Row Cycle Delay */
+#define         AT91_SDRAMC_TRP         (0xf << 16)             /* Row Precharge Delay */
+#define         AT91_SDRAMC_TRCD        (0xf << 20)             /* Row to Column Delay */
+#define         AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
+#define         AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_LPR         (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
+#define         AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
+#define                 AT91_SDRAMC_LPCB_DISABLE                0
+#define                 AT91_SDRAMC_LPCB_SELF_REFRESH           1
+#define                 AT91_SDRAMC_LPCB_POWER_DOWN             2
+#define                 AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
+#define         AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
+#define         AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
+#define         AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strenght */
+#define         AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                 AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
+#define                 AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
+#define                 AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
+
+#define AT91_SDRAMC_IER         (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR         (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR         (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR         (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
+#define         AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
+
+#define AT91_SDRAMC_MDR         (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
+#define         AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
+#define                 AT91_SDRAMC_MD_SDRAM            0
+#define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
+
+
+/* Static Memory Controller (SMC) registers */
+#define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
+#define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
+#define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
+#define                 AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
+#define         AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
+#define                 AT91_SMC_NRDSETUP_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
+#define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
+
+#define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
+#define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
+#define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
+#define                 AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
+#define         AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
+#define                 AT91_SMC_NRDPULSE_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
+#define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
+
+#define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
+#define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
+#define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
+#define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
+#define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
+
+#define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
+#define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
+#define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
+#define         AT91_SMC_EXNWMODE       (3 <<  5)                       /* NWAIT Mode */
+#define                 AT91_SMC_EXNWMODE_DISABLE       (0 << 5)
+#define                 AT91_SMC_EXNWMODE_FROZEN        (2 << 5)
+#define                 AT91_SMC_EXNWMODE_READY         (3 << 5)
+#define         AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
+#define                 AT91_SMC_BAT_SELECT             (0 << 8)
+#define                 AT91_SMC_BAT_WRITE              (1 << 8)
+#define         AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
+#define                 AT91_SMC_DBW_8                  (0 << 12)
+#define                 AT91_SMC_DBW_16                 (1 << 12)
+#define                 AT91_SMC_DBW_32                 (2 << 12)
+#define         AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
+#define                 AT91_SMC_TDF_(x)                ((x) << 16)
+#define         AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
+#define         AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
+#define         AT91_SMC_PS             (3 << 28)                       /* Page Size */
+#define                 AT91_SMC_PS_4                   (0 << 28)
+#define                 AT91_SMC_PS_8                   (1 << 28)
+#define                 AT91_SMC_PS_16                  (2 << 28)
+#define                 AT91_SMC_PS_32                  (3 << 28)
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h
index 3cc9aec80f9d..768e0fc6aa2f 100644
--- a/include/asm-arm/arch-at91rm9200/board.h
+++ b/include/asm-arm/arch-at91rm9200/board.h
@@ -48,13 +48,14 @@ struct at91_cf_data {
         u8      det_pin;                /* Card detect */
         u8      vcc_pin;                /* power switching */
         u8      rst_pin;                /* card reset */
+        u8      chipselect;             /* EBI Chip Select number */
 };
 extern void __init at91_add_device_cf(struct at91_cf_data *data);
 
  /* MMC / SD */
 struct at91_mmc_data {
         u8              det_pin;        /* card detect IRQ */
-        unsigned        is_b:1;         /* uses B side (vs A) */
+        unsigned        slot_b:1;       /* uses Slot B */
         unsigned        wire4:1;        /* (SD) supports DAT0..DAT3 */
         u8              wp_pin;         /* (SD) writeprotect detect */
         u8              vcc_pin;        /* power switching (high == on) */
@@ -81,7 +82,8 @@ struct at91_nand_data {
         u8              rdy_pin;        /* ready/busy */
         u8              ale;            /* address line number connected to ALE */
         u8              cle;            /* address line number connected to CLE */
-        struct mtd_partition* (*partition_info)(int, int*);
+        u8              bus_width_16;   /* buswidth is 16 bit */
+        struct mtd_partition* (*partition_info)(int, int*);
 };
 extern void __init at91_add_device_nand(struct at91_nand_data *data);
 
diff --git a/include/asm-arm/arch-at91rm9200/cpu.h b/include/asm-arm/arch-at91rm9200/cpu.h
new file mode 100644
index 000000000000..6f8d09b08692
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/cpu.h
@@ -0,0 +1,49 @@
+/*
+ * include/asm-arm/arch-at91rm9200/cpu.h
+ *
+ *  Copyright (C) 2006 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_CPU_H
+#define __ASM_ARCH_CPU_H
+
+#include <asm/hardware.h>
+#include <asm/arch/at91_dbgu.h>
+
+
+#define ARCH_ID_AT91RM9200      0x09290780
+#define ARCH_ID_AT91SAM9260     0x019803a0
+#define ARCH_ID_AT91SAM9261     0x019703a0
+
+
+static inline unsigned long at91_cpu_identify(void)
+{
+        return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
+}
+
+
+#ifdef CONFIG_ARCH_AT91RM9200
+#define cpu_is_at91rm9200()     (at91_cpu_identify() == ARCH_ID_AT91RM9200)
+#else
+#define cpu_is_at91rm9200()     (0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91SAM9260
+#define cpu_is_at91sam9260()    (at91_cpu_identify() == ARCH_ID_AT91SAM9260)
+#else
+#define cpu_is_at91sam9260()    (0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91SAM9261
+#define cpu_is_at91sam9261()    (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
+#else
+#define cpu_is_at91sam9261()    (0)
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/debug-macro.S b/include/asm-arm/arch-at91rm9200/debug-macro.S
index f496b54c4c3e..85cdadf26634 100644
--- a/include/asm-arm/arch-at91rm9200/debug-macro.S
+++ b/include/asm-arm/arch-at91rm9200/debug-macro.S
@@ -12,6 +12,7 @@
 */
 
 #include <asm/hardware.h>
+#include <asm/arch/at91_dbgu.h>
 
         .macro  addruart,rx
         mrc     p15, 0, \rx, c1, c0
diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S
index 61a326e94909..57248a796472 100644
--- a/include/asm-arm/arch-at91rm9200/entry-macro.S
+++ b/include/asm-arm/arch-at91rm9200/entry-macro.S
@@ -11,6 +11,7 @@
  */
 
 #include <asm/hardware.h>
+#include <asm/arch/at91_aic.h>
 
         .macro  disable_fiq
         .endm
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 9ca4cc9c0b2e..9ea5bfe06320 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -16,8 +16,16 @@
 
 #include <asm/sizes.h>
 
+#if defined(CONFIG_ARCH_AT91RM9200)
 #include <asm/arch/at91rm9200.h>
-#include <asm/arch/at91rm9200_sys.h>
+#elif defined(CONFIG_ARCH_AT91SAM9260)
+#include <asm/arch/at91sam9260.h>
+#elif defined(CONFIG_ARCH_AT91SAM9261)
+#include <asm/arch/at91sam9261.h>
+#else
+#error "Unsupported AT91 processor"
+#endif
+
 
 /*
  * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
@@ -34,29 +42,27 @@
  * Virtual to Physical Address mapping for IO devices.
  */
 #define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
-#define AT91_VA_BASE_SPI        AT91_IO_P2V(AT91RM9200_BASE_SPI)
 #define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91RM9200_BASE_EMAC)
-#define AT91_VA_BASE_TWI        AT91_IO_P2V(AT91RM9200_BASE_TWI)
-#define AT91_VA_BASE_MCI        AT91_IO_P2V(AT91RM9200_BASE_MCI)
-#define AT91_VA_BASE_UDP        AT91_IO_P2V(AT91RM9200_BASE_UDP)
 
  /* Internal SRAM is mapped below the IO devices */
-#define AT91_SRAM_VIRT_BASE     (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
+#define AT91_SRAM_MAX           SZ_1M
+#define AT91_VIRT_BASE          (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
 
 /* Serial ports */
-#define ATMEL_MAX_UART          5               /* 4 USART3's and one DBGU port */
-
-/* FLASH */
-#define AT91_FLASH_BASE         0x10000000      /* NCS0: Flash physical base address */
+#define ATMEL_MAX_UART          7               /* 6 USART3's and one DBGU port (SAM9260) */
+
+/* External Memory Map */
+#define AT91_CHIPSELECT_0       0x10000000
+#define AT91_CHIPSELECT_1       0x20000000
+#define AT91_CHIPSELECT_2       0x30000000
+#define AT91_CHIPSELECT_3       0x40000000
+#define AT91_CHIPSELECT_4       0x50000000
+#define AT91_CHIPSELECT_5       0x60000000
+#define AT91_CHIPSELECT_6       0x70000000
+#define AT91_CHIPSELECT_7       0x80000000
 
 /* SDRAM */
-#define AT91_SDRAM_BASE         0x20000000      /* NCS1: SDRAM physical base address */
-
-/* SmartMedia */
-#define AT91_SMARTMEDIA_BASE    0x40000000      /* NCS3: Smartmedia physical base address */
-
-/* Compact Flash */
-#define AT91_CF_BASE            0x50000000      /* NCS4-NCS6: Compact Flash physical base address */
+#define AT91_SDRAM_BASE         AT91_CHIPSELECT_1
 
 /* Clocks */
 #define AT91_SLOW_CLOCK         32768           /* slow clock */
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
index 763cb96c418b..c0679eaefaf2 100644
--- a/include/asm-arm/arch-at91rm9200/irqs.h
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -21,6 +21,8 @@
 #ifndef __ASM_ARCH_IRQS_H
 #define __ASM_ARCH_IRQS_H
 
+#include <asm/arch/at91_aic.h>
+
 #define NR_AIC_IRQS 32
 
 
diff --git a/include/asm-arm/arch-at91rm9200/system.h b/include/asm-arm/arch-at91rm9200/system.h
index 8a2ff472e4cf..9c67130603b2 100644
--- a/include/asm-arm/arch-at91rm9200/system.h
+++ b/include/asm-arm/arch-at91rm9200/system.h
@@ -22,6 +22,8 @@
 #define __ASM_ARCH_SYSTEM_H
 
 #include <asm/hardware.h>
+#include <asm/arch/at91_st.h>
+#include <asm/arch/at91_dbgu.h>
 
 static inline void arch_idle(void)
 {
@@ -39,21 +41,13 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
-{
-        /*
-         * Perform a hardware reset with the use of the Watchdog timer.
-         */
-        at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
-        at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
-}
-
-#define ARCH_ID_AT91RM9200      0x09200080
-#define ARCH_ID_AT91SAM9261     0x019000a0
+void (*at91_arch_reset)(void);
 
-static inline unsigned long arch_identify(void)
+static inline void arch_reset(char mode)
 {
-        return at91_sys_read(AT91_DBGU_CIDR) & (AT91_CIDR_EPROC | AT91_CIDR_ARCH);
+        /* call the CPU-specific reset function */
+        if (at91_arch_reset)
+                (at91_arch_reset)();
 }
 
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/timex.h b/include/asm-arm/arch-at91rm9200/timex.h
index 88687cefe6eb..faeca45a8d44 100644
--- a/include/asm-arm/arch-at91rm9200/timex.h
+++ b/include/asm-arm/arch-at91rm9200/timex.h
@@ -23,6 +23,15 @@
 
 #include <asm/hardware.h>
 
+#if defined(CONFIG_ARCH_AT91RM9200)
+
 #define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
 
+#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
+
+#define AT91SAM9_MASTER_CLOCK   99300000
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
+#endif
+
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h
index ec7811ab0a52..34b4b93fa015 100644
--- a/include/asm-arm/arch-at91rm9200/uncompress.h
+++ b/include/asm-arm/arch-at91rm9200/uncompress.h
@@ -22,11 +22,11 @@
 #define __ASM_ARCH_UNCOMPRESS_H
 
 #include <asm/hardware.h>
+#include <asm/arch/at91_dbgu.h>
 
 /*
  * The following code assumes the serial port has already been
- * initialized by the bootloader.  We search for the first enabled
- * port in the most probable order.  If you didn't setup a port in
+ * initialized by the bootloader.  If you didn't setup a port in
  * your bootloader then nothing will appear (which might be desired).
  *
  * This does not append a newline
diff --git a/include/asm-arm/arch-at91rm9200/vmalloc.h b/include/asm-arm/arch-at91rm9200/vmalloc.h
index 4c367eb57f47..0a23b8c562b9 100644
--- a/include/asm-arm/arch-at91rm9200/vmalloc.h
+++ b/include/asm-arm/arch-at91rm9200/vmalloc.h
@@ -21,6 +21,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END             (AT91_SRAM_VIRT_BASE & PGDIR_MASK)
+#define VMALLOC_END             (AT91_VIRT_BASE & PGDIR_MASK)
 
 #endif
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
index c6e8dcf674de..42768cc8bfb4 100644
--- a/include/asm-arm/arch-clps711x/memory.h
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -62,7 +62,15 @@
  * memory bank.  For those systems, simply undefine CONFIG_DISCONTIGMEM.
  */
 
-#ifdef CONFIG_DISCONTIGMEM
+/*
+ * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
+ * uses only one of the two banks (bank #1).  However, even within
+ * bank #1, memory is discontiguous.
+ *
+ * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
+ * them, so we use 24 for the node max shift to get 16MB node sizes.
+ */
+
 /*
  * Because of the wide memory address space between physical RAM banks on the 
  * SA1100, it's much more convenient to use Linux's NUMA support to implement
@@ -80,48 +88,7 @@
  *      node 2:  0xd0000000 - 0xd7ffffff
  *      node 3:  0xd8000000 - 0xdfffffff
  */
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) \
-                (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn) \
-        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr) \
-                        NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
-
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-/*
- * Given a kaddr, LOCAL_MAR_NR finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
-
-/*
- * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
- * uses only one of the two banks (bank #1).  However, even within
- * bank #1, memory is discontiguous.
- *
- * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
- * them, so we use 24 for the node max shift to get 16MB node sizes.
- */
-#define NODE_MAX_MEM_SHIFT      24
-#define NODE_MAX_MEM_SIZE       (1<<NODE_MAX_MEM_SHIFT)
-
-#endif /* CONFIG_DISCONTIGMEM */
+#define NODE_MEM_SIZE_BITS      24
 
 #endif
 
diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S
new file mode 100644
index 000000000000..788b4e386c16
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/debug-macro.S
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-iop13xx/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+        .macro  addruart, rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                 @ mmu enabled?
+        moveq   \rx, #0xff000000        @ physical
+        orreq   \rx, \rx, #0x00d80000
+        movne   \rx, #0xfe000000        @ virtual
+        orrne   \rx, \rx, #0x00e80000
+        orr     \rx, \rx, #0x00002300
+        orr     \rx, \rx, #0x00000040
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
new file mode 100644
index 000000000000..2e15da53ff79
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -0,0 +1,3 @@
+#ifndef _IOP13XX_DMA_H
+#define _IOP13XX_DMA_H_
+#endif
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S
new file mode 100644
index 000000000000..94c50283dc56
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * iop13xx low level irq macros
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+        .macro  disable_fiq
+        .endm
+
+        /*
+         * Note: a 1-cycle window exists where iintvec will return the value
+         * of iintbase, so we explicitly check for "bad zeros"
+         */
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        mrc     p15, 0, \tmp, c15, c1, 0
+        orr     \tmp, \tmp, #(1 << 6)
+        mcr     p15, 0, \tmp, c15, c1, 0        @ Enable cp6 access
+
+        mrc     p6, 0, \irqnr, c3, c2, 0        @ Read IINTVEC
+        cmp     \irqnr, #0
+        mrceq   p6, 0, \irqnr, c3, c2, 0        @ Re-read on potentially bad zero
+        adds    \irqstat, \irqnr, #1            @ Check for 0xffffffff
+        movne   \irqnr, \irqnr, lsr #2          @ Convert to irqnr
+
+        biceq   \tmp, \tmp, #(1 << 6)
+        mcreq   p15, 0, \tmp, c15, c1, 0        @ Disable cp6 access if no more interrupts
+        .endm
diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/include/asm-arm/arch-iop13xx/hardware.h
new file mode 100644
index 000000000000..8e1d56289846
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/hardware.h
@@ -0,0 +1,28 @@
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include <asm/types.h>
+
+#define pcibios_assign_all_busses() 1
+
+#ifndef __ASSEMBLY__
+extern unsigned long iop13xx_pcibios_min_io;
+extern unsigned long iop13xx_pcibios_min_mem;
+extern u16 iop13xx_dev_id(void);
+extern void iop13xx_set_atu_mmr_bases(void);
+#endif
+
+#define PCIBIOS_MIN_IO      (iop13xx_pcibios_min_io)
+#define PCIBIOS_MIN_MEM     (iop13xx_pcibios_min_mem)
+
+/*
+ * Generic chipset bits
+ *
+ */
+#include "iop13xx.h"
+
+/*
+ * Board specific bits
+ */
+#include "iq81340.h"
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h
new file mode 100644
index 000000000000..db6de2480a24
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/io.h
@@ -0,0 +1,41 @@
+/*
+ * iop13xx custom ioremap implementation
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)      (a)
+#define __mem_pci(a) (a)
+#define __mem_isa(a) (a)
+
+extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
+extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
+        unsigned long flags);
+extern void __iop13xx_iounmap(void __iomem *addr);
+
+extern u32 iop13xx_atue_mem_base;
+extern u32 iop13xx_atux_mem_base;
+extern size_t iop13xx_atue_mem_size;
+extern size_t iop13xx_atux_mem_size;
+
+#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
+#define __arch_iounmap(a)        __iop13xx_iounmap(a)
+
+#endif
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
new file mode 100644
index 000000000000..a88522a0ff8e
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -0,0 +1,492 @@
+#ifndef _IOP13XX_HW_H_
+#define _IOP13XX_HW_H_
+
+#ifndef __ASSEMBLY__
+/* The ATU offsets can change based on the strapping */
+extern u32 iop13xx_atux_pmmr_offset;
+extern u32 iop13xx_atue_pmmr_offset;
+void iop13xx_init_irq(void);
+void iop13xx_map_io(void);
+void iop13xx_platform_init(void);
+void iop13xx_init_irq(void);
+void iop13xx_init_time(unsigned long tickrate);
+unsigned long iop13xx_gettimeoffset(void);
+
+/* handle cp6 access
+ * to do: handle access in entry-armv5.S and unify with
+ * the iop3xx implementation
+ * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
+ * when interrupts are enabled
+ */
+static inline unsigned long iop13xx_cp6_save(void)
+{
+        u32 temp, cp_flags;
+
+        asm volatile (
+                "mrc    p15, 0, %1, c15, c1, 0\n\t"
+                "orr    %0, %1, #(1 << 6)\n\t"
+                "mcr    p15, 0, %0, c15, c1, 0\n\t"
+                : "=r" (temp), "=r"(cp_flags));
+
+        return cp_flags;
+}
+
+static inline void iop13xx_cp6_restore(unsigned long cp_flags)
+{
+        asm volatile (
+                "mcr    p15, 0, %0, c15, c1, 0\n\t"
+                : : "r" (cp_flags) );
+}
+
+/* CPUID CP6 R0 Page 0 */
+static inline int iop13xx_cpu_id(void)
+{
+        int id;
+        asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
+        return id;
+}
+
+#endif
+
+/*
+ * IOP13XX I/O and Mem space regions for PCI autoconfiguration
+ */
+#define IOP13XX_MAX_RAM_SIZE    0x80000000UL  /* 2GB */
+#define IOP13XX_PCI_OFFSET       IOP13XX_MAX_RAM_SIZE
+
+/* PCI MAP
+ * 0x0000.0000 - 0x8000.0000           1:1 mapping with Physical RAM
+ * 0x8000.0000 - 0x8800.0000           PCIX/PCIE memory window (128MB)
+*/
+#define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
+#define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
+#define IOP13XX_PCIX_LOWER_IO_VA      0xfec60000UL
+#define IOP13XX_PCIX_LOWER_IO_BA      0x0fff0000UL
+#define IOP13XX_PCIX_UPPER_IO_PA      (IOP13XX_PCIX_LOWER_IO_PA +\
+                                       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_UPPER_IO_VA      (IOP13XX_PCIX_LOWER_IO_VA +\
+                                       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_IO_OFFSET        (IOP13XX_PCIX_LOWER_IO_VA -\
+                                       IOP13XX_PCIX_LOWER_IO_BA)
+#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
+                                           (IOP13XX_PCIX_LOWER_IO_PA\
+                                           - IOP13XX_PCIX_LOWER_IO_VA))
+
+#define IOP13XX_PCIX_MEM_PHYS_OFFSET  0x100000000ULL
+#define IOP13XX_PCIX_MEM_WINDOW_SIZE  0x3a000000UL
+#define IOP13XX_PCIX_LOWER_MEM_BA     (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
+#define IOP13XX_PCIX_LOWER_MEM_PA     (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
+                                       IOP13XX_PCIX_LOWER_MEM_BA)
+#define IOP13XX_PCIX_UPPER_MEM_PA     (IOP13XX_PCIX_LOWER_MEM_PA +\
+                                       IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_UPPER_MEM_BA     (IOP13XX_PCIX_LOWER_MEM_BA +\
+                                       IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
+
+#define IOP13XX_PCIX_MEM_COOKIE        0x80000000UL
+#define IOP13XX_PCIX_LOWER_MEM_RA      IOP13XX_PCIX_MEM_COOKIE
+#define IOP13XX_PCIX_UPPER_MEM_RA      (IOP13XX_PCIX_LOWER_MEM_RA +\
+                                        IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_MEM_OFFSET        (IOP13XX_PCIX_MEM_COOKIE -\
+                                        IOP13XX_PCIX_LOWER_MEM_BA)
+
+/* PCI-E ranges */
+#define IOP13XX_PCIE_IO_WINDOW_SIZE      0x10000UL
+#define IOP13XX_PCIE_LOWER_IO_PA         0xfffd0000UL
+#define IOP13XX_PCIE_LOWER_IO_VA         0xfed70000UL
+#define IOP13XX_PCIE_LOWER_IO_BA         0x0fff0000UL
+#define IOP13XX_PCIE_UPPER_IO_PA         (IOP13XX_PCIE_LOWER_IO_PA +\
+                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_UPPER_IO_VA         (IOP13XX_PCIE_LOWER_IO_VA +\
+                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_UPPER_IO_BA         (IOP13XX_PCIE_LOWER_IO_BA +\
+                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_IO_OFFSET           (IOP13XX_PCIE_LOWER_IO_VA -\
+                                         IOP13XX_PCIE_LOWER_IO_BA)
+#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
+                                           (IOP13XX_PCIE_LOWER_IO_PA\
+                                           - IOP13XX_PCIE_LOWER_IO_VA))
+
+#define IOP13XX_PCIE_MEM_PHYS_OFFSET     0x200000000ULL
+#define IOP13XX_PCIE_MEM_WINDOW_SIZE     0x3a000000UL
+#define IOP13XX_PCIE_LOWER_MEM_BA        (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
+#define IOP13XX_PCIE_LOWER_MEM_PA        (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
+                                         IOP13XX_PCIE_LOWER_MEM_BA)
+#define IOP13XX_PCIE_UPPER_MEM_PA        (IOP13XX_PCIE_LOWER_MEM_PA +\
+                                         IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_UPPER_MEM_BA        (IOP13XX_PCIE_LOWER_MEM_BA +\
+                                         IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
+
+/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
+#define IOP13XX_PCIE_MEM_COOKIE          0xc0000000UL
+#define IOP13XX_PCIE_LOWER_MEM_RA        IOP13XX_PCIE_MEM_COOKIE
+#define IOP13XX_PCIE_UPPER_MEM_RA        (IOP13XX_PCIE_LOWER_MEM_RA +\
+                                         IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_MEM_OFFSET          (IOP13XX_PCIE_MEM_COOKIE -\
+                                         IOP13XX_PCIE_LOWER_MEM_BA)
+
+/* PBI Ranges */
+#define IOP13XX_PBI_LOWER_MEM_PA          0xf0000000UL
+#define IOP13XX_PBI_MEM_WINDOW_SIZE       0x04000000UL
+#define IOP13XX_PBI_MEM_COOKIE            0xfa000000UL
+#define IOP13XX_PBI_LOWER_MEM_RA          IOP13XX_PBI_MEM_COOKIE
+#define IOP13XX_PBI_UPPER_MEM_RA          (IOP13XX_PBI_LOWER_MEM_RA +\
+                                          IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
+
+/*
+ * IOP13XX chipset registers
+ */
+#define IOP13XX_PMMR_PHYS_MEM_BASE         0xffd80000UL  /* PMMR phys. address */
+#define IOP13XX_PMMR_VIRT_MEM_BASE         0xfee80000UL  /* PMMR phys. address */
+#define IOP13XX_PMMR_MEM_WINDOW_SIZE       0x80000
+#define IOP13XX_PMMR_UPPER_MEM_VA          (IOP13XX_PMMR_VIRT_MEM_BASE +\
+                                           IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PMMR_UPPER_MEM_PA          (IOP13XX_PMMR_PHYS_MEM_BASE +\
+                                           IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (u32) ((u32) addr +\
+                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
+                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
+#define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (u32) ((u32) addr -\
+                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
+                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
+#define IOP13XX_REG_ADDR32(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR16(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR8(reg)             (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR32_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR16_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR8_PHYS(reg)       (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
+#define IOP13XX_PMMR_SIZE                  0x00080000
+
+/*=================== Defines for Platform Devices =====================*/
+#define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
+#define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
+#define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
+#define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
+
+#define IOP13XX_I2C0_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
+#define IOP13XX_I2C1_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
+#define IOP13XX_I2C2_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
+#define IOP13XX_I2C0_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
+#define IOP13XX_I2C1_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
+#define IOP13XX_I2C2_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
+
+/* ATU selection flags */
+/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
+#define IOP13XX_INIT_ATU_DEFAULT     (0)
+#define IOP13XX_INIT_ATU_ATUX         (1 << 0)
+#define IOP13XX_INIT_ATU_ATUE         (1 << 1)
+#define IOP13XX_INIT_ATU_NONE         (1 << 2)
+
+/* UART selection flags */
+/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
+#define IOP13XX_INIT_UART_DEFAULT    (0)
+#define IOP13XX_INIT_UART_0           (1 << 0)
+#define IOP13XX_INIT_UART_1           (1 << 1)
+
+/* I2C selection flags */
+/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
+#define IOP13XX_INIT_I2C_DEFAULT     (0)
+#define IOP13XX_INIT_I2C_0            (1 << 0)
+#define IOP13XX_INIT_I2C_1            (1 << 1)
+#define IOP13XX_INIT_I2C_2            (1 << 2)
+
+#define IQ81340_NUM_UART     2
+#define IQ81340_NUM_I2C      3
+#define IQ81340_NUM_PHYS_MAP_FLASH 1
+#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
+                                IQ81340_NUM_I2C +\
+                                IQ81340_NUM_PHYS_MAP_FLASH)
+
+/*========================== PMMR offsets for key registers ============*/
+#define IOP13XX_ATU0_PMMR_OFFSET        0x00048000
+#define IOP13XX_ATU1_PMMR_OFFSET        0x0004c000
+#define IOP13XX_ATU2_PMMR_OFFSET        0x0004d000
+#define IOP13XX_ADMA0_PMMR_OFFSET       0x00000000
+#define IOP13XX_ADMA1_PMMR_OFFSET       0x00000200
+#define IOP13XX_ADMA2_PMMR_OFFSET       0x00000400
+#define IOP13XX_PBI_PMMR_OFFSET         0x00001580
+#define IOP13XX_ESSR0_PMMR_OFFSET       0x00002188
+#define IOP13XX_ESSR0                   IOP13XX_REG_ADDR32(0x00002188)
+
+#define IOP13XX_ESSR0_IFACE_MASK        0x00004000  /* Interface PCI-X / PCI-E */
+#define IOP13XX_CONTROLLER_ONLY         (1 << 14)
+#define IOP13XX_INTERFACE_SEL_PCIX      (1 << 15)
+
+#define IOP13XX_PMON_PMMR_OFFSET        0x0001A000
+#define IOP13XX_PMON_BASE               (IOP13XX_PMMR_VIRT_MEM_BASE +\
+                                        IOP13XX_PMON_PMMR_OFFSET)
+#define IOP13XX_PMON_PHYSBASE           (IOP13XX_PMMR_PHYS_MEM_BASE +\
+                                        IOP13XX_PMON_PMMR_OFFSET)
+
+#define IOP13XX_PMON_CMD0               (IOP13XX_PMON_BASE + 0x0)
+#define IOP13XX_PMON_EVR0               (IOP13XX_PMON_BASE + 0x4)
+#define IOP13XX_PMON_STS0               (IOP13XX_PMON_BASE + 0x8)
+#define IOP13XX_PMON_DATA0              (IOP13XX_PMON_BASE + 0xC)
+
+#define IOP13XX_PMON_CMD3               (IOP13XX_PMON_BASE + 0x30)
+#define IOP13XX_PMON_EVR3               (IOP13XX_PMON_BASE + 0x34)
+#define IOP13XX_PMON_STS3               (IOP13XX_PMON_BASE + 0x38)
+#define IOP13XX_PMON_DATA3              (IOP13XX_PMON_BASE + 0x3C)
+
+#define IOP13XX_PMON_CMD7               (IOP13XX_PMON_BASE + 0x70)
+#define IOP13XX_PMON_EVR7               (IOP13XX_PMON_BASE + 0x74)
+#define IOP13XX_PMON_STS7               (IOP13XX_PMON_BASE + 0x78)
+#define IOP13XX_PMON_DATA7              (IOP13XX_PMON_BASE + 0x7C)
+
+#define IOP13XX_PMONEN                  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
+#define IOP13XX_PMONSTAT                (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
+
+/*================================ATU===================================*/
+#define IOP13XX_ATUX_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
+                                        iop13xx_atux_pmmr_offset + (ofs))
+
+#define IOP13XX_ATUX_DID                IOP13XX_REG_ADDR16(\
+                                        iop13xx_atux_pmmr_offset + 0x2)
+
+#define IOP13XX_ATUX_ATUCMD             IOP13XX_REG_ADDR16(\
+                                        iop13xx_atux_pmmr_offset + 0x4)
+#define IOP13XX_ATUX_ATUSR              IOP13XX_REG_ADDR16(\
+                                        iop13xx_atux_pmmr_offset + 0x6)
+
+#define IOP13XX_ATUX_IABAR0             IOP13XX_ATUX_OFFSET(0x10)
+#define IOP13XX_ATUX_IAUBAR0            IOP13XX_ATUX_OFFSET(0x14)
+#define IOP13XX_ATUX_IABAR1             IOP13XX_ATUX_OFFSET(0x18)
+#define IOP13XX_ATUX_IAUBAR1            IOP13XX_ATUX_OFFSET(0x1c)
+#define IOP13XX_ATUX_IABAR2             IOP13XX_ATUX_OFFSET(0x20)
+#define IOP13XX_ATUX_IAUBAR2            IOP13XX_ATUX_OFFSET(0x24)
+#define IOP13XX_ATUX_IALR0              IOP13XX_ATUX_OFFSET(0x40)
+#define IOP13XX_ATUX_IATVR0             IOP13XX_ATUX_OFFSET(0x44)
+#define IOP13XX_ATUX_IAUTVR0            IOP13XX_ATUX_OFFSET(0x48)
+#define IOP13XX_ATUX_IALR1              IOP13XX_ATUX_OFFSET(0x4c)
+#define IOP13XX_ATUX_IATVR1             IOP13XX_ATUX_OFFSET(0x50)
+#define IOP13XX_ATUX_IAUTVR1            IOP13XX_ATUX_OFFSET(0x54)
+#define IOP13XX_ATUX_IALR2              IOP13XX_ATUX_OFFSET(0x58)
+#define IOP13XX_ATUX_IATVR2             IOP13XX_ATUX_OFFSET(0x5c)
+#define IOP13XX_ATUX_IAUTVR2            IOP13XX_ATUX_OFFSET(0x60)
+#define IOP13XX_ATUX_ATUCR              IOP13XX_ATUX_OFFSET(0x70)
+#define IOP13XX_ATUX_PCSR               IOP13XX_ATUX_OFFSET(0x74)
+#define IOP13XX_ATUX_ATUISR             IOP13XX_ATUX_OFFSET(0x78)
+#define IOP13XX_ATUX_PCIXSR             IOP13XX_ATUX_OFFSET(0xD4)
+#define IOP13XX_ATUX_IABAR3             IOP13XX_ATUX_OFFSET(0x200)
+#define IOP13XX_ATUX_IAUBAR3            IOP13XX_ATUX_OFFSET(0x204)
+#define IOP13XX_ATUX_IALR3              IOP13XX_ATUX_OFFSET(0x208)
+#define IOP13XX_ATUX_IATVR3             IOP13XX_ATUX_OFFSET(0x20c)
+#define IOP13XX_ATUX_IAUTVR3            IOP13XX_ATUX_OFFSET(0x210)
+
+#define IOP13XX_ATUX_OIOBAR             IOP13XX_ATUX_OFFSET(0x300)
+#define IOP13XX_ATUX_OIOWTVR            IOP13XX_ATUX_OFFSET(0x304)
+#define IOP13XX_ATUX_OUMBAR0            IOP13XX_ATUX_OFFSET(0x308)
+#define IOP13XX_ATUX_OUMWTVR0           IOP13XX_ATUX_OFFSET(0x30c)
+#define IOP13XX_ATUX_OUMBAR1            IOP13XX_ATUX_OFFSET(0x310)
+#define IOP13XX_ATUX_OUMWTVR1           IOP13XX_ATUX_OFFSET(0x314)
+#define IOP13XX_ATUX_OUMBAR2            IOP13XX_ATUX_OFFSET(0x318)
+#define IOP13XX_ATUX_OUMWTVR2           IOP13XX_ATUX_OFFSET(0x31c)
+#define IOP13XX_ATUX_OUMBAR3            IOP13XX_ATUX_OFFSET(0x320)
+#define IOP13XX_ATUX_OUMWTVR3           IOP13XX_ATUX_OFFSET(0x324)
+#define IOP13XX_ATUX_OUDMABAR           IOP13XX_ATUX_OFFSET(0x328)
+#define IOP13XX_ATUX_OUMSIBAR           IOP13XX_ATUX_OFFSET(0x32c)
+#define IOP13XX_ATUX_OCCAR              IOP13XX_ATUX_OFFSET(0x330)
+#define IOP13XX_ATUX_OCCDR              IOP13XX_ATUX_OFFSET(0x334)
+
+#define IOP13XX_ATUX_ATUCR_OUT_EN               (1 << 1)
+#define IOP13XX_ATUX_PCSR_CENTRAL_RES           (1 << 25)
+#define IOP13XX_ATUX_PCSR_P_RSTOUT              (1 << 21)
+#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY            (1 << 15)
+#define IOP13XX_ATUX_PCSR_IN_Q_BUSY             (1 << 14)
+#define IOP13XX_ATUX_PCSR_FREQ_OFFSET           (16)
+
+#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
+#define IOP13XX_ATUX_STAT_VPD_ADDR              (1 << 17)
+#define IOP13XX_ATUX_STAT_INT_PAR_ERR           (1 << 16)
+#define IOP13XX_ATUX_STAT_CFG_WRITE             (1 << 15)
+#define IOP13XX_ATUX_STAT_ERR_COR               (1 << 14)
+#define IOP13XX_ATUX_STAT_TX_SCEM               (1 << 13)
+#define IOP13XX_ATUX_STAT_REC_SCEM              (1 << 12)
+#define IOP13XX_ATUX_STAT_POWER_TRAN            (1 << 11)
+#define IOP13XX_ATUX_STAT_TX_SERR               (1 << 10)
+#define IOP13XX_ATUX_STAT_DET_PAR_ERR           (1 << 9 )
+#define IOP13XX_ATUX_STAT_BIST                  (1 << 8 )
+#define IOP13XX_ATUX_STAT_INT_REC_MABORT        (1 << 7 )
+#define IOP13XX_ATUX_STAT_REC_SERR              (1 << 4 )
+#define IOP13XX_ATUX_STAT_EXT_REC_MABORT        (1 << 3 )
+#define IOP13XX_ATUX_STAT_EXT_REC_TABORT        (1 << 2 )
+#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT        (1 << 1 )
+#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR       (1 << 0 )
+
+#define IOP13XX_ATUX_PCIXSR_BUS_NUM     (8)
+#define IOP13XX_ATUX_PCIXSR_DEV_NUM     (3)
+#define IOP13XX_ATUX_PCIXSR_FUNC_NUM    (0)
+
+#define IOP13XX_ATUX_IALR_DISABLE       0x00000001
+#define IOP13XX_ATUX_OUMBAR_ENABLE      0x80000000
+
+#define IOP13XX_ATUE_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
+                                        iop13xx_atue_pmmr_offset + (ofs))
+
+#define IOP13XX_ATUE_DID                IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0x2)
+#define IOP13XX_ATUE_ATUCMD             IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0x4)
+#define IOP13XX_ATUE_ATUSR              IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0x6)
+
+#define IOP13XX_ATUE_IABAR0             IOP13XX_ATUE_OFFSET(0x10)
+#define IOP13XX_ATUE_IAUBAR0            IOP13XX_ATUE_OFFSET(0x14)
+#define IOP13XX_ATUE_IABAR1             IOP13XX_ATUE_OFFSET(0x18)
+#define IOP13XX_ATUE_IAUBAR1            IOP13XX_ATUE_OFFSET(0x1c)
+#define IOP13XX_ATUE_IABAR2             IOP13XX_ATUE_OFFSET(0x20)
+#define IOP13XX_ATUE_IAUBAR2            IOP13XX_ATUE_OFFSET(0x24)
+#define IOP13XX_ATUE_IALR0              IOP13XX_ATUE_OFFSET(0x40)
+#define IOP13XX_ATUE_IATVR0             IOP13XX_ATUE_OFFSET(0x44)
+#define IOP13XX_ATUE_IAUTVR0            IOP13XX_ATUE_OFFSET(0x48)
+#define IOP13XX_ATUE_IALR1              IOP13XX_ATUE_OFFSET(0x4c)
+#define IOP13XX_ATUE_IATVR1             IOP13XX_ATUE_OFFSET(0x50)
+#define IOP13XX_ATUE_IAUTVR1            IOP13XX_ATUE_OFFSET(0x54)
+#define IOP13XX_ATUE_IALR2              IOP13XX_ATUE_OFFSET(0x58)
+#define IOP13XX_ATUE_IATVR2             IOP13XX_ATUE_OFFSET(0x5c)
+#define IOP13XX_ATUE_IAUTVR2            IOP13XX_ATUE_OFFSET(0x60)
+#define IOP13XX_ATUE_PE_LSTS            IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0xe2)
+#define IOP13XX_ATUE_OIOWTVR            IOP13XX_ATUE_OFFSET(0x304)
+#define IOP13XX_ATUE_OUMBAR0            IOP13XX_ATUE_OFFSET(0x308)
+#define IOP13XX_ATUE_OUMWTVR0           IOP13XX_ATUE_OFFSET(0x30c)
+#define IOP13XX_ATUE_OUMBAR1            IOP13XX_ATUE_OFFSET(0x310)
+#define IOP13XX_ATUE_OUMWTVR1           IOP13XX_ATUE_OFFSET(0x314)
+#define IOP13XX_ATUE_OUMBAR2            IOP13XX_ATUE_OFFSET(0x318)
+#define IOP13XX_ATUE_OUMWTVR2           IOP13XX_ATUE_OFFSET(0x31c)
+#define IOP13XX_ATUE_OUMBAR3            IOP13XX_ATUE_OFFSET(0x320)
+#define IOP13XX_ATUE_OUMWTVR3           IOP13XX_ATUE_OFFSET(0x324)
+
+#define IOP13XX_ATUE_ATUCR              IOP13XX_ATUE_OFFSET(0x70)
+#define IOP13XX_ATUE_PCSR               IOP13XX_ATUE_OFFSET(0x74)
+#define IOP13XX_ATUE_ATUISR             IOP13XX_ATUE_OFFSET(0x78)
+#define IOP13XX_ATUE_OIOBAR             IOP13XX_ATUE_OFFSET(0x300)
+#define IOP13XX_ATUE_OCCAR              IOP13XX_ATUE_OFFSET(0x32c)
+#define IOP13XX_ATUE_OCCDR              IOP13XX_ATUE_OFFSET(0x330)
+
+#define IOP13XX_ATUE_PIE_STS            IOP13XX_ATUE_OFFSET(0x384)
+#define IOP13XX_ATUE_PIE_MSK            IOP13XX_ATUE_OFFSET(0x388)
+
+#define IOP13XX_ATUE_ATUCR_IVM          (1 << 6)
+#define IOP13XX_ATUE_ATUCR_OUT_EN       (1 << 1)
+#define IOP13XX_ATUE_OCCAR_BUS_NUM      (24)
+#define IOP13XX_ATUE_OCCAR_DEV_NUM      (19)
+#define IOP13XX_ATUE_OCCAR_FUNC_NUM     (16)
+#define IOP13XX_ATUE_OCCAR_EXT_REG      (8)
+#define IOP13XX_ATUE_OCCAR_REG          (2)
+
+#define IOP13XX_ATUE_PCSR_BUS_NUM       (24)
+#define IOP13XX_ATUE_PCSR_DEV_NUM       (19)
+#define IOP13XX_ATUE_PCSR_FUNC_NUM      (16)
+#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY    (1 << 15)
+#define IOP13XX_ATUE_PCSR_IN_Q_BUSY     (1 << 14)
+#define IOP13XX_ATUE_PCSR_END_POINT     (1 << 13)
+#define IOP13XX_ATUE_PCSR_LLRB_BUSY     (1 << 12)
+
+#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK          (0xff)
+#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK          (0x1f)
+#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
+
+#define IOP13XX_ATUE_PCSR_CORE_RESET            (8)
+#define IOP13XX_ATUE_PCSR_FUNC_NUM              (16)
+
+#define IOP13XX_ATUE_LSTS_TRAINING              (1 << 11)
+#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG          (1 << 28)
+#define IOP13XX_ATUE_STAT_PME                   (1 << 27)
+#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG          (1 << 26)
+#define IOP13XX_ATUE_STAT_IVM                   (1 << 25)
+#define IOP13XX_ATUE_STAT_BIST                  (1 << 24)
+#define IOP13XX_ATUE_STAT_CFG_WRITE             (1 << 18)
+#define IOP13XX_ATUE_STAT_VPD_ADDR              (1 << 17)
+#define IOP13XX_ATUE_STAT_POWER_TRAN            (1 << 16)
+#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
+#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR          (1 << 12)
+#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG          (1 << 11)
+#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
+#define IOP13XX_ATUE_STAT_ERR_COR               (1 << 9 )
+#define IOP13XX_ATUE_STAT_ERR_UNCOR             (1 << 8 )
+#define IOP13XX_ATUE_STAT_CRS                   (1 << 7 )
+#define IOP13XX_ATUE_STAT_LNK_DWN               (1 << 6 )
+#define IOP13XX_ATUE_STAT_INT_REC_MABORT        (1 << 5 )
+#define IOP13XX_ATUE_STAT_DET_PAR_ERR           (1 << 4 )
+#define IOP13XX_ATUE_STAT_EXT_REC_MABORT        (1 << 3 )
+#define IOP13XX_ATUE_STAT_SIG_TABORT            (1 << 2 )
+#define IOP13XX_ATUE_STAT_EXT_REC_TABORT        (1 << 1 )
+#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR       (1 << 0 )
+
+#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ     (1 << 31)
+#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT          (1 << 30)
+#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP              (1 << 29)
+#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR                   (1 << 28)
+#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ          (1 << 20)
+#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR         (1 << 19)
+#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP            (1 << 18)
+#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
+#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP          (1 << 16)
+#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT               (1 << 15)
+#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT         (1 << 14)
+#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR             (1 << 13)
+#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP             (1 << 12)
+#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR         (1 << 4 )
+#define IOP13XX_ATUE_ESTAT_TRAINING_ERR         (1 << 0 )
+
+#define IOP13XX_ATUE_IALR_DISABLE               (0x00000001)
+#define IOP13XX_ATUE_OUMBAR_ENABLE              (0x80000000)
+#define IOP13XX_ATU_OUMBAR_FUNC_NUM             (28)
+#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK        (0x7)
+/*=======================================================================*/
+
+/*==============================ADMA UNITS===============================*/
+#define IOP13XX_ADMA_PHYS_BASE(chan)    IOP13XX_REG_ADDR32_PHYS((chan << 9))
+#define IOP13XX_ADMA_UPPER_PA(chan)     (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
+#define IOP13XX_ADMA_OFFSET(chan, ofs)  IOP13XX_REG_ADDR32((chan << 9) + (ofs))
+
+#define IOP13XX_ADMA_ACCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x0)
+#define IOP13XX_ADMA_ACSR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x4)
+#define IOP13XX_ADMA_ADAR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x8)
+#define IOP13XX_ADMA_IIPCR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x18)
+#define IOP13XX_ADMA_IIPAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x1c)
+#define IOP13XX_ADMA_IIPUAR(chan)    IOP13XX_ADMA_OFFSET(chan, 0x20)
+#define IOP13XX_ADMA_ANDAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x24)
+#define IOP13XX_ADMA_ADCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x28)
+#define IOP13XX_ADMA_CARMD(chan)     IOP13XX_ADMA_OFFSET(chan, 0x2c)
+#define IOP13XX_ADMA_ABCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x30)
+#define IOP13XX_ADMA_DLADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x34)
+#define IOP13XX_ADMA_DUADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x38)
+#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
+#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
+
+/*==============================XSI BRIDGE===============================*/
+#define IOP13XX_XBG_BECSR               IOP13XX_REG_ADDR32(0x178c)
+#define IOP13XX_XBG_BERAR               IOP13XX_REG_ADDR32(0x1790)
+#define IOP13XX_XBG_BERUAR              IOP13XX_REG_ADDR32(0x1794)
+#define is_atue_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
+                                        IOP13XX_PMMR_VIRT_TO_PHYS(\
+                                        IOP13XX_ATUE_OCCDR))\
+                                        && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
+#define is_atux_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
+                                        IOP13XX_PMMR_VIRT_TO_PHYS(\
+                                        IOP13XX_ATUX_OCCDR))\
+                                        && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
+/*=======================================================================*/
+
+#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
+                                                        (ofs))
+
+#define IOP13XX_PBI_CR                  IOP13XX_PBI_OFFSET(0x0)
+#define IOP13XX_PBI_SR                  IOP13XX_PBI_OFFSET(0x4)
+#define IOP13XX_PBI_BAR0                IOP13XX_PBI_OFFSET(0x8)
+#define IOP13XX_PBI_LR0                 IOP13XX_PBI_OFFSET(0xc)
+#define IOP13XX_PBI_BAR1                IOP13XX_PBI_OFFSET(0x10)
+#define IOP13XX_PBI_LR1                 IOP13XX_PBI_OFFSET(0x14)
+
+#define IOP13XX_TMR_TC                  0x01
+#define IOP13XX_TMR_EN                  0x02
+#define IOP13XX_TMR_RELOAD              0x04
+#define IOP13XX_TMR_PRIVILEGED          0x08
+
+#define IOP13XX_TMR_RATIO_1_1           0x00
+#define IOP13XX_TMR_RATIO_4_1           0x10
+#define IOP13XX_TMR_RATIO_8_1           0x20
+#define IOP13XX_TMR_RATIO_16_1          0x30
+
+#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/include/asm-arm/arch-iop13xx/iq81340.h
new file mode 100644
index 000000000000..b98f8f109c22
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iq81340.h
@@ -0,0 +1,31 @@
+#ifndef _IQ81340_H_
+#define _IQ81340_H_
+
+#define IQ81340_PCE_BAR0    IOP13XX_PBI_LOWER_MEM_RA
+#define IQ81340_PCE_BAR1    (IQ81340_PCE_BAR0 + 0x02000000)
+
+#define IQ81340_FLASHBASE   IQ81340_PCE_BAR0    /* Flash */
+
+#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
+
+#define IQ81340_PRD_CODE    IQ81340_PCE_BAR1_OFFSET(0)
+#define IQ81340_BRD_STEP    IQ81340_PCE_BAR1_OFFSET(0x10000)
+#define IQ81340_CPLD_REV    IQ81340_PCE_BAR1_OFFSET(0x20000)
+#define IQ81340_LED          IQ81340_PCE_BAR1_OFFSET(0x30000)
+#define IQ81340_LHEX         IQ81340_PCE_BAR1_OFFSET(0x40000)
+#define IQ81340_RHEX         IQ81340_PCE_BAR1_OFFSET(0x50000)
+#define IQ81340_BUZZER       IQ81340_PCE_BAR1_OFFSET(0x60000)
+#define IQ81340_32K_NVRAM   IQ81340_PCE_BAR1_OFFSET(0x70000)
+#define IQ81340_256K_NVRAM  IQ81340_PCE_BAR1_OFFSET(0x80000)
+#define IQ81340_ROTARY_SW   IQ81340_PCE_BAR1_OFFSET(0xd0000)
+#define IQ81340_BATT_STAT   IQ81340_PCE_BAR1_OFFSET(0xf0000)
+#define IQ81340_CMP_FLSH    IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
+
+#define PBI_CF_IDE_BASE     (IQ81340_CMP_FLSH)
+#define PBI_CF_BAR_ADDR     (IOP13XX_PBI_BAR1)
+
+/* These are the values used in the Machine description */
+#define PHYS_IO         0xfeffff00
+#define IO_PG_OFFSET    0xffffff00
+#define BOOT_PARAM_OFFSET  0x00000100
+#endif  /* _IQ81340_H_ */
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h
new file mode 100644
index 000000000000..442e35a40359
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/irqs.h
@@ -0,0 +1,207 @@
+#ifndef _IOP13XX_IRQS_H_
+#define _IOP13XX_IRQS_H_
+
+#ifndef __ASSEMBLER__
+#include <linux/types.h>
+#include <asm/system.h> /* local_irq_save */
+#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
+
+/* INTPND0 CP6 R0 Page 3
+ */
+static inline u32 read_intpnd_0(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
+        return val;
+}
+
+/* INTPND1 CP6 R1 Page 3
+ */
+static inline u32 read_intpnd_1(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
+        return val;
+}
+
+/* INTPND2 CP6 R2 Page 3
+ */
+static inline u32 read_intpnd_2(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
+        return val;
+}
+
+/* INTPND3 CP6 R3 Page 3
+ */
+static inline u32 read_intpnd_3(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
+        return val;
+}
+
+static inline void
+iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
+{
+        local_irq_save(*irq_flags);
+        *cp_flags = iop13xx_cp6_save();
+}
+
+static inline void
+iop13xx_cp6_irq_restore(unsigned long *cp_flags,
+        unsigned long *irq_flags)
+{
+        iop13xx_cp6_restore(*cp_flags);
+        local_irq_restore(*irq_flags);
+}
+#endif
+
+#define INTBASE 0
+#define INTSIZE_4 1
+
+/*
+ * iop34x chipset interrupts
+ */
+#define IOP13XX_IRQ(x)          (IOP13XX_IRQ_OFS + (x))
+
+/*
+ * On IRQ or FIQ register
+ */
+#define IRQ_IOP13XX_ADMA0_EOT   (0)
+#define IRQ_IOP13XX_ADMA0_EOC   (1)
+#define IRQ_IOP13XX_ADMA1_EOT   (2)
+#define IRQ_IOP13XX_ADMA1_EOC   (3)
+#define IRQ_IOP13XX_ADMA2_EOT   (4)
+#define IRQ_IOP13XX_ADMA2_EOC   (5)
+#define IRQ_IOP134_WATCHDOG     (6)
+#define IRQ_IOP13XX_RSVD_7      (7)
+#define IRQ_IOP13XX_TIMER0      (8)
+#define IRQ_IOP13XX_TIMER1      (9)
+#define IRQ_IOP13XX_I2C_0       (10)
+#define IRQ_IOP13XX_I2C_1       (11)
+#define IRQ_IOP13XX_MSG (12)
+#define IRQ_IOP13XX_MSGIBQ      (13)
+#define IRQ_IOP13XX_ATU_IM      (14)
+#define IRQ_IOP13XX_ATU_BIST    (15)
+#define IRQ_IOP13XX_PPMU        (16)
+#define IRQ_IOP13XX_COREPMU     (17)
+#define IRQ_IOP13XX_CORECACHE   (18)
+#define IRQ_IOP13XX_RSVD_19     (19)
+#define IRQ_IOP13XX_RSVD_20     (20)
+#define IRQ_IOP13XX_RSVD_21     (21)
+#define IRQ_IOP13XX_RSVD_22     (22)
+#define IRQ_IOP13XX_RSVD_23     (23)
+#define IRQ_IOP13XX_XINT0       (24)
+#define IRQ_IOP13XX_XINT1       (25)
+#define IRQ_IOP13XX_XINT2       (26)
+#define IRQ_IOP13XX_XINT3       (27)
+#define IRQ_IOP13XX_XINT4       (28)
+#define IRQ_IOP13XX_XINT5       (29)
+#define IRQ_IOP13XX_XINT6       (30)
+#define IRQ_IOP13XX_XINT7       (31)
+                                      /* IINTSRC1 bit */
+#define IRQ_IOP13XX_XINT8       (32)  /* 0  */
+#define IRQ_IOP13XX_XINT9       (33)  /* 1  */
+#define IRQ_IOP13XX_XINT10      (34)  /* 2  */
+#define IRQ_IOP13XX_XINT11      (35)  /* 3  */
+#define IRQ_IOP13XX_XINT12      (36)  /* 4  */
+#define IRQ_IOP13XX_XINT13      (37)  /* 5  */
+#define IRQ_IOP13XX_XINT14      (38)  /* 6  */
+#define IRQ_IOP13XX_XINT15      (39)  /* 7  */
+#define IRQ_IOP13XX_RSVD_40     (40)  /* 8  */
+#define IRQ_IOP13XX_RSVD_41     (41)  /* 9  */
+#define IRQ_IOP13XX_RSVD_42     (42)  /* 10 */
+#define IRQ_IOP13XX_RSVD_43     (43)  /* 11 */
+#define IRQ_IOP13XX_RSVD_44     (44)  /* 12 */
+#define IRQ_IOP13XX_RSVD_45     (45)  /* 13 */
+#define IRQ_IOP13XX_RSVD_46     (46)  /* 14 */
+#define IRQ_IOP13XX_RSVD_47     (47)  /* 15 */
+#define IRQ_IOP13XX_RSVD_48     (48)  /* 16 */
+#define IRQ_IOP13XX_RSVD_49     (49)  /* 17 */
+#define IRQ_IOP13XX_RSVD_50     (50)  /* 18 */
+#define IRQ_IOP13XX_UART0       (51)  /* 19 */
+#define IRQ_IOP13XX_UART1       (52)  /* 20 */
+#define IRQ_IOP13XX_PBIE        (53)  /* 21 */
+#define IRQ_IOP13XX_ATU_CRW     (54)  /* 22 */
+#define IRQ_IOP13XX_ATU_ERR     (55)  /* 23 */
+#define IRQ_IOP13XX_MCU_ERR     (56)  /* 24 */
+#define IRQ_IOP13XX_ADMA0_ERR   (57)  /* 25 */
+#define IRQ_IOP13XX_ADMA1_ERR   (58)  /* 26 */
+#define IRQ_IOP13XX_ADMA2_ERR   (59)  /* 27 */
+#define IRQ_IOP13XX_RSVD_60     (60)  /* 28 */
+#define IRQ_IOP13XX_RSVD_61     (61)  /* 29 */
+#define IRQ_IOP13XX_MSG_ERR     (62)  /* 30 */
+#define IRQ_IOP13XX_RSVD_63     (63)  /* 31 */
+                                      /* IINTSRC2 bit */
+#define IRQ_IOP13XX_INTERPROC   (64)  /* 0  */
+#define IRQ_IOP13XX_RSVD_65     (65)  /* 1  */
+#define IRQ_IOP13XX_RSVD_66     (66)  /* 2  */
+#define IRQ_IOP13XX_RSVD_67     (67)  /* 3  */
+#define IRQ_IOP13XX_RSVD_68     (68)  /* 4  */
+#define IRQ_IOP13XX_RSVD_69     (69)  /* 5  */
+#define IRQ_IOP13XX_RSVD_70     (70)  /* 6  */
+#define IRQ_IOP13XX_RSVD_71     (71)  /* 7  */
+#define IRQ_IOP13XX_RSVD_72     (72)  /* 8  */
+#define IRQ_IOP13XX_RSVD_73     (73)  /* 9  */
+#define IRQ_IOP13XX_RSVD_74     (74)  /* 10 */
+#define IRQ_IOP13XX_RSVD_75     (75)  /* 11 */
+#define IRQ_IOP13XX_RSVD_76     (76)  /* 12 */
+#define IRQ_IOP13XX_RSVD_77     (77)  /* 13 */
+#define IRQ_IOP13XX_RSVD_78     (78)  /* 14 */
+#define IRQ_IOP13XX_RSVD_79     (79)  /* 15 */
+#define IRQ_IOP13XX_RSVD_80     (80)  /* 16 */
+#define IRQ_IOP13XX_RSVD_81     (81)  /* 17 */
+#define IRQ_IOP13XX_RSVD_82     (82)  /* 18 */
+#define IRQ_IOP13XX_RSVD_83     (83)  /* 19 */
+#define IRQ_IOP13XX_RSVD_84     (84)  /* 20 */
+#define IRQ_IOP13XX_RSVD_85     (85)  /* 21 */
+#define IRQ_IOP13XX_RSVD_86     (86)  /* 22 */
+#define IRQ_IOP13XX_RSVD_87     (87)  /* 23 */
+#define IRQ_IOP13XX_RSVD_88     (88)  /* 24 */
+#define IRQ_IOP13XX_RSVD_89     (89)  /* 25 */
+#define IRQ_IOP13XX_RSVD_90     (90)  /* 26 */
+#define IRQ_IOP13XX_RSVD_91     (91)  /* 27 */
+#define IRQ_IOP13XX_RSVD_92     (92)  /* 28 */
+#define IRQ_IOP13XX_RSVD_93     (93)  /* 29 */
+#define IRQ_IOP13XX_SIB_ERR     (94)  /* 30 */
+#define IRQ_IOP13XX_SRAM_ERR    (95)  /* 31 */
+                                      /* IINTSRC3 bit */
+#define IRQ_IOP13XX_I2C_2       (96)  /* 0  */
+#define IRQ_IOP13XX_ATUE_BIST   (97)  /* 1  */
+#define IRQ_IOP13XX_ATUE_CRW    (98)  /* 2  */
+#define IRQ_IOP13XX_ATUE_ERR    (99)  /* 3  */
+#define IRQ_IOP13XX_IMU (100) /* 4  */
+#define IRQ_IOP13XX_RSVD_101    (101) /* 5  */
+#define IRQ_IOP13XX_RSVD_102    (102) /* 6  */
+#define IRQ_IOP13XX_TPMI0_OUT   (103) /* 7  */
+#define IRQ_IOP13XX_TPMI1_OUT   (104) /* 8  */
+#define IRQ_IOP13XX_TPMI2_OUT   (105) /* 9  */
+#define IRQ_IOP13XX_TPMI3_OUT   (106) /* 10 */
+#define IRQ_IOP13XX_ATUE_IMA    (107) /* 11 */
+#define IRQ_IOP13XX_ATUE_IMB    (108) /* 12 */
+#define IRQ_IOP13XX_ATUE_IMC    (109) /* 13 */
+#define IRQ_IOP13XX_ATUE_IMD    (110) /* 14 */
+#define IRQ_IOP13XX_MU_MSI_TB   (111) /* 15 */
+#define IRQ_IOP13XX_RSVD_112    (112) /* 16 */
+#define IRQ_IOP13XX_RSVD_113    (113) /* 17 */
+#define IRQ_IOP13XX_RSVD_114    (114) /* 18 */
+#define IRQ_IOP13XX_RSVD_115    (115) /* 19 */
+#define IRQ_IOP13XX_RSVD_116    (116) /* 20 */
+#define IRQ_IOP13XX_RSVD_117    (117) /* 21 */
+#define IRQ_IOP13XX_RSVD_118    (118) /* 22 */
+#define IRQ_IOP13XX_RSVD_119    (119) /* 23 */
+#define IRQ_IOP13XX_RSVD_120    (120) /* 24 */
+#define IRQ_IOP13XX_RSVD_121    (121) /* 25 */
+#define IRQ_IOP13XX_RSVD_122    (122) /* 26 */
+#define IRQ_IOP13XX_RSVD_123    (123) /* 27 */
+#define IRQ_IOP13XX_RSVD_124    (124) /* 28 */
+#define IRQ_IOP13XX_RSVD_125    (125) /* 29 */
+#define IRQ_IOP13XX_RSVD_126    (126) /* 30 */
+#define IRQ_IOP13XX_HPI (127) /* 31 */
+
+#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
+#define NR_IRQS         NR_IOP13XX_IRQS
+
+#endif /* _IOP13XX_IRQ_H_ */
diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h
new file mode 100644
index 000000000000..031a0fa78eff
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/memory.h
@@ -0,0 +1,64 @@
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/arch/hardware.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+#define TASK_SIZE       UL(0x3f000000)
+#define PAGE_OFFSET     UL(0x40000000)
+#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_ARCH_IOP13XX)
+#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
+#define IOP13XX_PMMR_V_END   (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
+#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
+#define IOP13XX_PMMR_P_END   (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
+
+/*
+ * Virtual view <-> PCI DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+
+/* RAM has 1:1 mapping on the PCIe/x Busses */
+#define __virt_to_bus(x)        (__virt_to_phys(x))
+#define __bus_to_virt(x)    (__phys_to_virt(x))
+
+#define virt_to_lbus(x)                                            \
+(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) &&                  \
+((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ?                       \
+((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
+((x) - PAGE_OFFSET + PHYS_OFFSET))
+
+#define lbus_to_virt(x)                                            \
+(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
+((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
+((x) - PHYS_OFFSET + PAGE_OFFSET))
+
+/* Device is an lbus device if it is on the platform bus of the IOP13XX */
+#define is_lbus_device(dev) (dev &&\
+                             (strncmp(dev->bus->name, "platform", 8) == 0))
+
+#define __arch_page_to_dma(dev, page)                                   \
+({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
+(dma_addr_t)__virt_to_bus(page_address(page));})
+
+#define __arch_dma_to_virt(dev, addr) \
+({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
+
+#define __arch_virt_to_dma(dev, addr) \
+({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
+
+#endif /* CONFIG_ARCH_IOP13XX */
+#endif /* !ASSEMBLY */
+
+#define PFN_TO_NID(addr)        (0)
+
+#endif
diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h
new file mode 100644
index 000000000000..4041f30d4cd3
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/pci.h
@@ -0,0 +1,57 @@
+#ifndef _IOP13XX_PCI_H_
+#define _IOP13XX_PCI_H_
+#include <asm/arch/irqs.h>
+#include <asm/io.h>
+
+struct pci_sys_data;
+struct hw_pci;
+int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
+struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
+void iop13xx_atu_select(struct hw_pci *plat_pci);
+void iop13xx_pci_init(void);
+void iop13xx_map_pci_memory(void);
+
+#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY |            \
+                               PCI_STATUS_SIG_TARGET_ABORT | \
+                               PCI_STATUS_REC_TARGET_ABORT | \
+                               PCI_STATUS_REC_TARGET_ABORT | \
+                               PCI_STATUS_REC_MASTER_ABORT | \
+                               PCI_STATUS_SIG_SYSTEM_ERROR | \
+                               PCI_STATUS_DETECTED_PARITY)
+
+#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR |  \
+                                    IOP13XX_ATUE_STAT_ROOT_SYS_ERR |   \
+                                    IOP13XX_ATUE_STAT_PCI_IFACE_ERR |  \
+                                    IOP13XX_ATUE_STAT_ERR_COR |        \
+                                    IOP13XX_ATUE_STAT_ERR_UNCOR |      \
+                                    IOP13XX_ATUE_STAT_CRS |            \
+                                    IOP13XX_ATUE_STAT_DET_PAR_ERR |    \
+                                    IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
+                                    IOP13XX_ATUE_STAT_SIG_TABORT |     \
+                                    IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
+                                    IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
+
+#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM |        \
+                                    IOP13XX_ATUX_STAT_REC_SCEM |       \
+                                    IOP13XX_ATUX_STAT_TX_SERR |        \
+                                    IOP13XX_ATUX_STAT_DET_PAR_ERR |    \
+                                    IOP13XX_ATUX_STAT_INT_REC_MABORT | \
+                                    IOP13XX_ATUX_STAT_REC_SERR |       \
+                                    IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
+                                    IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
+                                    IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
+                                    IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
+
+/* PCI interrupts
+ */
+#define ATUX_INTA IRQ_IOP13XX_XINT0
+#define ATUX_INTB IRQ_IOP13XX_XINT1
+#define ATUX_INTC IRQ_IOP13XX_XINT2
+#define ATUX_INTD IRQ_IOP13XX_XINT3
+
+#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
+#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
+#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
+#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
+
+#endif /* _IOP13XX_PCI_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
new file mode 100644
index 000000000000..ee3a62530af2
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -0,0 +1,59 @@
+/*
+ * linux/include/asm-arm/arch-iop13xx/system.h
+ *
+ *  Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/arch/iop13xx.h>
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+/* WDTCR CP6 R7 Page 9 */
+static inline u32 read_wdtcr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtcr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
+}
+
+/* WDTSR CP6 R8 Page 9 */
+static inline u32 read_wdtsr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtsr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
+}
+
+#define IOP13XX_WDTCR_EN_ARM    0x1e1e1e1e
+#define IOP13XX_WDTCR_EN        0xe1e1e1e1
+#define IOP13XX_WDTCR_DIS_ARM   0x1f1f1f1f
+#define IOP13XX_WDTCR_DIS       0xf1f1f1f1
+#define IOP13XX_WDTSR_WRITE_EN  (1 << 31)
+#define IOP13XX_WDTCR_IB_RESET  (1 << 0)
+static inline void arch_reset(char mode)
+{
+        /*
+         * Reset the internal bus (warning both cores are reset)
+         */
+        u32 cp_flags = iop13xx_cp6_save();
+        write_wdtcr(IOP13XX_WDTCR_EN_ARM);
+        write_wdtcr(IOP13XX_WDTCR_EN);
+        write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
+        write_wdtcr(0x1000);
+        iop13xx_cp6_restore(cp_flags);
+
+        for(;;);
+}
diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h
new file mode 100644
index 000000000000..f0c51dd97ed8
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/timex.h
@@ -0,0 +1,3 @@
+#include <asm/hardware.h>
+
+#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
new file mode 100644
index 000000000000..b9525d59b7ad
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/uncompress.h
@@ -0,0 +1,24 @@
+#include <asm/types.h>
+#include <linux/serial_reg.h>
+#include <asm/hardware.h>
+#include <asm/processor.h>
+
+#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
+#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
+
+static inline void putc(char c)
+{
+        while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
+                cpu_relax();
+        UART_BASE[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/include/asm-arm/arch-iop13xx/vmalloc.h
new file mode 100644
index 000000000000..c53456740345
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/vmalloc.h
@@ -0,0 +1,4 @@
+#ifndef _VMALLOC_H_
+#define _VMALLOC_H_
+#define VMALLOC_END     0xfa000000UL
+#endif
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
index 9f1a58cbf407..9b0c8012e713 100644
--- a/include/asm-arm/arch-lh7a40x/memory.h
+++ b/include/asm-arm/arch-lh7a40x/memory.h
@@ -58,18 +58,6 @@
 #endif
 
 /*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and return the mem_map of that node.
- */
-# define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and return the mem_map of that node.
- */
-# define PFN_TO_MAPBASE(pfn)    NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-/*
  * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
  * and returns the index corresponding to the appropriate page in the
  * node's mem_map.
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index eaf6d43939e9..e17f9881faf0 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -27,7 +27,6 @@
 #define __virt_to_bus(x)         __virt_to_phys(x)
 #define __bus_to_virt(x)         __phys_to_virt(x)
 
-#ifdef CONFIG_DISCONTIGMEM
 /*
  * The nodes are matched with the physical SDRAM banks as follows:
  *
@@ -35,38 +34,9 @@
  *      node 1:  0xa4000000-0xa7ffffff  -->  0xc4000000-0xc7ffffff
  *      node 2:  0xa8000000-0xabffffff  -->  0xc8000000-0xcbffffff
  *      node 3:  0xac000000-0xafffffff  -->  0xcc000000-0xcfffffff
+ *
+ * This needs a node mem size of 26 bits.
  */
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn)         (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT)
-
-#endif
+#define NODE_MEM_SIZE_BITS      26
 
 #endif
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
index 1ff172dc8e33..0e907fc6d42a 100644
--- a/include/asm-arm/arch-sa1100/memory.h
+++ b/include/asm-arm/arch-sa1100/memory.h
@@ -39,7 +39,6 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
 #define __virt_to_bus(x)         __virt_to_phys(x)
 #define __bus_to_virt(x)         __phys_to_virt(x)
 
-#ifdef CONFIG_DISCONTIGMEM
 /*
  * Because of the wide memory address space between physical RAM banks on the 
  * SA1100, it's much convenient to use Linux's NUMA support to implement our 
@@ -57,38 +56,7 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
  *      node 2:  0xd0000000 - 0xd7ffffff
  *      node 3:  0xd8000000 - 0xdfffffff
  */
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 27)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn)         (((pfn) - PHYS_PFN_OFFSET) >> (27 - PAGE_SHIFT))
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and return the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and return the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & 0x07ffffff) >> PAGE_SHIFT)
-
-#endif
+#define NODE_MEM_SIZE_BITS      27
 
 /*
  * Cache flushing area - SA1100 zero bank
diff --git a/include/asm-arm/cnt32_to_63.h b/include/asm-arm/cnt32_to_63.h
new file mode 100644
index 000000000000..480c873fa746
--- /dev/null
+++ b/include/asm-arm/cnt32_to_63.h
@@ -0,0 +1,78 @@
+/*
+ *  include/asm/cnt32_to_63.h -- extend a 32-bit counter to 63 bits
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    December 3, 2006
+ *  Copyright:  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __INCLUDE_CNT32_TO_63_H__
+#define __INCLUDE_CNT32_TO_63_H__
+
+#include <linux/compiler.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+
+/*
+ * Prototype: u64 cnt32_to_63(u32 cnt)
+ * Many hardware clock counters are only 32 bits wide and therefore have
+ * a relatively short period making wrap-arounds rather frequent.  This
+ * is a problem when implementing sched_clock() for example, where a 64-bit
+ * non-wrapping monotonic value is expected to be returned.
+ *
+ * To overcome that limitation, let's extend a 32-bit counter to 63 bits
+ * in a completely lock free fashion. Bits 0 to 31 of the clock are provided
+ * by the hardware while bits 32 to 62 are stored in memory.  The top bit in
+ * memory is used to synchronize with the hardware clock half-period.  When
+ * the top bit of both counters (hardware and in memory) differ then the
+ * memory is updated with a new value, incrementing it when the hardware
+ * counter wraps around.
+ *
+ * Because a word store in memory is atomic then the incremented value will
+ * always be in synch with the top bit indicating to any potential concurrent
+ * reader if the value in memory is up to date or not with regards to the
+ * needed increment.  And any race in updating the value in memory is harmless
+ * as the same value would simply be stored more than once.
+ *
+ * The only restriction for the algorithm to work properly is that this
+ * code must be executed at least once per each half period of the 32-bit
+ * counter to properly update the state bit in memory. This is usually not a
+ * problem in practice, but if it is then a kernel timer could be scheduled
+ * to manage for this code to be executed often enough.
+ *
+ * Note that the top bit (bit 63) in the returned value should be considered
+ * as garbage.  It is not cleared here because callers are likely to use a
+ * multiplier on the returned value which can get rid of the top bit
+ * implicitly by making the multiplier even, therefore saving on a runtime
+ * clear-bit instruction. Otherwise caller must remember to clear the top
+ * bit explicitly.
+ */
+
+/* this is used only to give gcc a clue about good code generation */
+typedef union {
+        struct {
+#if defined(__LITTLE_ENDIAN)
+                u32 lo, hi;
+#elif defined(__BIG_ENDIAN)
+                u32 hi, lo;
+#endif
+        };
+        u64 val;
+} cnt32_to_63_t;
+
+#define cnt32_to_63(cnt_lo) \
+({ \
+        static volatile u32 __m_cnt_hi = 0; \
+        cnt32_to_63_t __x; \
+        __x.hi = __m_cnt_hi; \
+        __x.lo = (cnt_lo); \
+        if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \
+                __m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \
+        __x.val; \
+})
+
+#endif
diff --git a/include/asm-arm/div64.h b/include/asm-arm/div64.h
index 3682616804ca..37e0a96e8789 100644
--- a/include/asm-arm/div64.h
+++ b/include/asm-arm/div64.h
@@ -27,7 +27,7 @@
 #define __xh "r1"
 #endif
 
-#define do_div(n,base)                                          \
+#define __do_div_asm(n, base)                                   \
 ({                                                              \
         register unsigned int __base      asm("r4") = base;     \
         register unsigned long long __n   asm("r0") = n;        \
@@ -45,4 +45,182 @@
         __rem;                                                  \
 })
 
+#if __GNUC__ < 4
+
+/*
+ * gcc versions earlier than 4.0 are simply too problematic for the
+ * optimized implementation below. First there is gcc PR 15089 that
+ * tend to trig on more complex constructs, spurious .global __udivsi3
+ * are inserted even if none of those symbols are referenced in the
+ * generated code, and those gcc versions are not able to do constant
+ * propagation on long long values anyway.
+ */
+#define do_div(n, base) __do_div_asm(n, base)
+
+#elif __GNUC__ >= 4
+
+#include <asm/bug.h>
+
+/*
+ * If the divisor happens to be constant, we determine the appropriate
+ * inverse at compile time to turn the division into a few inline
+ * multiplications instead which is much faster. And yet only if compiling
+ * for ARMv4 or higher (we need umull/umlal) and if the gcc version is
+ * sufficiently recent to perform proper long long constant propagation.
+ * (It is unfortunate that gcc doesn't perform all this internally.)
+ */
+#define do_div(n, base)                                                 \
+({                                                                      \
+        unsigned int __r, __b = (base);                                 \
+        if (!__builtin_constant_p(__b) || __b == 0 ||                   \
+            (__LINUX_ARM_ARCH__ < 4 && (__b & (__b - 1)) != 0)) {       \
+                /* non-constant divisor (or zero): slow path */         \
+                __r = __do_div_asm(n, __b);                             \
+        } else if ((__b & (__b - 1)) == 0) {                            \
+                /* Trivial: __b is constant and a power of 2 */         \
+                /* gcc does the right thing with this code.  */         \
+                __r = n;                                                \
+                __r &= (__b - 1);                                       \
+                n /= __b;                                               \
+        } else {                                                        \
+                /* Multiply by inverse of __b: n/b = n*(p/b)/p       */ \
+                /* We rely on the fact that most of this code gets   */ \
+                /* optimized away at compile time due to constant    */ \
+                /* propagation and only a couple inline assembly     */ \
+                /* instructions should remain. Better avoid any      */ \
+                /* code construct that might prevent that.           */ \
+                unsigned long long __res, __x, __t, __m, __n = n;       \
+                unsigned int __c, __p, __z = 0;                         \
+                /* preserve low part of n for reminder computation */   \
+                __r = __n;                                              \
+                /* determine number of bits to represent __b */         \
+                __p = 1 << __div64_fls(__b);                            \
+                /* compute __m = ((__p << 64) + __b - 1) / __b */       \
+                __m = (~0ULL / __b) * __p;                              \
+                __m += (((~0ULL % __b + 1) * __p) + __b - 1) / __b;     \
+                /* compute __res = __m*(~0ULL/__b*__b-1)/(__p << 64) */ \
+                __x = ~0ULL / __b * __b - 1;                            \
+                __res = (__m & 0xffffffff) * (__x & 0xffffffff);        \
+                __res >>= 32;                                           \
+                __res += (__m & 0xffffffff) * (__x >> 32);              \
+                __t = __res;                                            \
+                __res += (__x & 0xffffffff) * (__m >> 32);              \
+                __t = (__res < __t) ? (1ULL << 32) : 0;                 \
+                __res = (__res >> 32) + __t;                            \
+                __res += (__m >> 32) * (__x >> 32);                     \
+                __res /= __p;                                           \
+                /* Now sanitize and optimize what we've got. */         \
+                if (~0ULL % (__b / (__b & -__b)) == 0) {                \
+                        /* those cases can be simplified with: */       \
+                        __n /= (__b & -__b);                            \
+                        __m = ~0ULL / (__b / (__b & -__b));             \
+                        __p = 1;                                        \
+                        __c = 1;                                        \
+                } else if (__res != __x / __b) {                        \
+                        /* We can't get away without a correction    */ \
+                        /* to compensate for bit truncation errors.  */ \
+                        /* To avoid it we'd need an additional bit   */ \
+                        /* to represent __m which would overflow it. */ \
+                        /* Instead we do m=p/b and n/b=(n*m+m)/p.    */ \
+                        __c = 1;                                        \
+                        /* Compute __m = (__p << 64) / __b */           \
+                        __m = (~0ULL / __b) * __p;                      \
+                        __m += ((~0ULL % __b + 1) * __p) / __b;         \
+                } else {                                                \
+                        /* Reduce __m/__p, and try to clear bit 31   */ \
+                        /* of __m when possible otherwise that'll    */ \
+                        /* need extra overflow handling later.       */ \
+                        unsigned int __bits = -(__m & -__m);            \
+                        __bits |= __m >> 32;                            \
+                        __bits = (~__bits) << 1;                        \
+                        /* If __bits == 0 then setting bit 31 is     */ \
+                        /* unavoidable.  Simply apply the maximum    */ \
+                        /* possible reduction in that case.          */ \
+                        /* Otherwise the MSB of __bits indicates the */ \
+                        /* best reduction we should apply.           */ \
+                        if (!__bits) {                                  \
+                                __p /= (__m & -__m);                    \
+                                __m /= (__m & -__m);                    \
+                        } else {                                        \
+                                __p >>= __div64_fls(__bits);            \
+                                __m >>= __div64_fls(__bits);            \
+                        }                                               \
+                        /* No correction needed. */                     \
+                        __c = 0;                                        \
+                }                                                       \
+                /* Now we have a combination of 2 conditions:        */ \
+                /* 1) whether or not we need a correction (__c), and */ \
+                /* 2) whether or not there might be an overflow in   */ \
+                /*    the cross product (__m & ((1<<63) | (1<<31)))  */ \
+                /* Select the best insn combination to perform the   */ \
+                /* actual __m * __n / (__p << 64) operation.         */ \
+                if (!__c) {                                             \
+                        asm (   "umull  %Q0, %R0, %1, %Q2\n\t"          \
+                                "mov    %Q0, #0"                        \
+                                : "=&r" (__res)                         \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                } else if (!(__m & ((1ULL << 63) | (1ULL << 31)))) {    \
+                        __res = __m;                                    \
+                        asm (   "umlal  %Q0, %R0, %Q1, %Q2\n\t"         \
+                                "mov    %Q0, #0"                        \
+                                : "+r" (__res)                          \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                } else {                                                \
+                        asm (   "umull  %Q0, %R0, %Q1, %Q2\n\t"         \
+                                "cmn    %Q0, %Q1\n\t"                   \
+                                "adcs   %R0, %R0, %R1\n\t"              \
+                                "adc    %Q0, %3, #0"                    \
+                                : "=&r" (__res)                         \
+                                : "r" (__m), "r" (__n), "r" (__z)       \
+                                : "cc" );                               \
+                }                                                       \
+                if (!(__m & ((1ULL << 63) | (1ULL << 31)))) {           \
+                        asm (   "umlal  %R0, %Q0, %R1, %Q2\n\t"         \
+                                "umlal  %R0, %Q0, %Q1, %R2\n\t"         \
+                                "mov    %R0, #0\n\t"                    \
+                                "umlal  %Q0, %R0, %R1, %R2"             \
+                                : "+r" (__res)                          \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                } else {                                                \
+                        asm (   "umlal  %R0, %Q0, %R2, %Q3\n\t"         \
+                                "umlal  %R0, %1, %Q2, %R3\n\t"          \
+                                "mov    %R0, #0\n\t"                    \
+                                "adds   %Q0, %1, %Q0\n\t"               \
+                                "adc    %R0, %R0, #0\n\t"               \
+                                "umlal  %Q0, %R0, %R2, %R3"             \
+                                : "+r" (__res), "+r" (__z)              \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                }                                                       \
+                __res /= __p;                                           \
+                /* The reminder can be computed with 32-bit regs     */ \
+                /* only, and gcc is good at that.                    */ \
+                {                                                       \
+                        unsigned int __res0 = __res;                    \
+                        unsigned int __b0 = __b;                        \
+                        __r -= __res0 * __b0;                           \
+                }                                                       \
+                /* BUG_ON(__r >= __b || __res * __b + __r != n); */     \
+                n = __res;                                              \
+        }                                                               \
+        __r;                                                            \
+})
+
+/* our own fls implementation to make sure constant propagation is fine */
+#define __div64_fls(bits)                                               \
+({                                                                      \
+        unsigned int __left = (bits), __nr = 0;                         \
+        if (__left & 0xffff0000) __nr += 16, __left >>= 16;             \
+        if (__left & 0x0000ff00) __nr +=  8, __left >>=  8;             \
+        if (__left & 0x000000f0) __nr +=  4, __left >>=  4;             \
+        if (__left & 0x0000000c) __nr +=  2, __left >>=  2;             \
+        if (__left & 0x00000002) __nr +=  1;                            \
+        __nr;                                                           \
+})
+
+#endif
+
 #endif
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index 91d536c215d7..d9bfb39adabf 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -215,6 +215,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
  *  virt_addr_valid(k)  indicates whether a virtual address is valid
  */
 #ifndef CONFIG_DISCONTIGMEM
+
 #define ARCH_PFN_OFFSET         PHYS_PFN_OFFSET
 #define pfn_valid(pfn)          ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
 
@@ -230,6 +231,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
  * around in memory.
  */
 #include <linux/numa.h>
+
 #define arch_pfn_to_nid(pfn)    PFN_TO_NID(pfn)
 #define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
 
@@ -256,6 +258,43 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
  */
 #define PHYS_TO_NID(addr)       PFN_TO_NID((addr) >> PAGE_SHIFT)
 
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
+
+/*
+ * Given a page frame number, find the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
+
+#ifdef NODE_MEM_SIZE_BITS
+#define NODE_MEM_SIZE_MASK      ((1 << NODE_MEM_SIZE_BITS) - 1)
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) \
+        (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS)
+
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+#define PFN_TO_NID(pfn) \
+        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT))
+
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+#define LOCAL_MAP_NR(addr) \
+        (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT)
+
+#endif /* NODE_MEM_SIZE_BITS */
+
 #endif /* !CONFIG_DISCONTIGMEM */
 
 /*
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h b/include/asm-avr32/arch-at32ap/at91_pdc.h
index ce1150d4438d..79d6e02fa45e 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+++ b/include/asm-avr32/arch-at32ap/at91_pdc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+ * include/asm-arm/arch-at91rm9200/at91_pdc.h
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
@@ -13,8 +13,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91RM9200_PDC_H
-#define AT91RM9200_PDC_H
+#ifndef AT91_PDC_H
+#define AT91_PDC_H
 
 #define AT91_PDC_RPR            0x100   /* Receive Pointer Register */
 #define AT91_PDC_RCR            0x104   /* Receive Counter Register */