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-rw-r--r--MAINTAINERS7
-rw-r--r--arch/arm/Kconfig18
-rw-r--r--arch/arm/Kconfig.debug4
-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/common/gic.c2
-rw-r--r--arch/arm/common/locomo.c84
-rw-r--r--arch/arm/common/sa1111.c30
-rw-r--r--arch/arm/common/vic.c8
-rw-r--r--arch/arm/configs/at91rm9200dk_defconfig11
-rw-r--r--arch/arm/configs/at91rm9200ek_defconfig11
-rw-r--r--arch/arm/configs/at91sam9260ek_defconfig950
-rw-r--r--arch/arm/configs/at91sam9261ek_defconfig1106
-rw-r--r--arch/arm/configs/badge4_defconfig1
-rw-r--r--arch/arm/configs/carmeva_defconfig2
-rw-r--r--arch/arm/configs/cerfcube_defconfig1
-rw-r--r--arch/arm/configs/collie_defconfig1
-rw-r--r--arch/arm/configs/corgi_defconfig1
-rw-r--r--arch/arm/configs/csb337_defconfig1
-rw-r--r--arch/arm/configs/csb637_defconfig3
-rw-r--r--arch/arm/configs/ep93xx_defconfig2
-rw-r--r--arch/arm/configs/h7202_defconfig1
-rw-r--r--arch/arm/configs/hackkit_defconfig1
-rw-r--r--arch/arm/configs/integrator_defconfig1
-rw-r--r--arch/arm/configs/iop13xx_defconfig1134
-rw-r--r--arch/arm/configs/iop32x_defconfig1
-rw-r--r--arch/arm/configs/iop33x_defconfig1
-rw-r--r--arch/arm/configs/ixp2000_defconfig1
-rw-r--r--arch/arm/configs/ixp23xx_defconfig1
-rw-r--r--arch/arm/configs/ixp4xx_defconfig1
-rw-r--r--arch/arm/configs/jornada720_defconfig1
-rw-r--r--arch/arm/configs/kb9202_defconfig3
-rw-r--r--arch/arm/configs/lpd270_defconfig1
-rw-r--r--arch/arm/configs/lpd7a400_defconfig1
-rw-r--r--arch/arm/configs/lpd7a404_defconfig1
-rw-r--r--arch/arm/configs/lubbock_defconfig1
-rw-r--r--arch/arm/configs/mainstone_defconfig1
-rw-r--r--arch/arm/configs/mx1ads_defconfig1
-rw-r--r--arch/arm/configs/neponset_defconfig1
-rw-r--r--arch/arm/configs/netwinder_defconfig1
-rw-r--r--arch/arm/configs/netx_defconfig1
-rw-r--r--arch/arm/configs/onearm_defconfig1
-rw-r--r--arch/arm/configs/pleb_defconfig1
-rw-r--r--arch/arm/configs/pnx4008_defconfig1
-rw-r--r--arch/arm/configs/pxa255-idp_defconfig1
-rw-r--r--arch/arm/configs/realview-smp_defconfig1
-rw-r--r--arch/arm/configs/realview_defconfig1
-rw-r--r--arch/arm/configs/rpc_defconfig1
-rw-r--r--arch/arm/configs/s3c2410_defconfig1
-rw-r--r--arch/arm/configs/shark_defconfig1
-rw-r--r--arch/arm/configs/simpad_defconfig1
-rw-r--r--arch/arm/configs/spitz_defconfig1
-rw-r--r--arch/arm/configs/versatile_defconfig1
-rw-r--r--arch/arm/kernel/Makefile4
-rw-r--r--arch/arm/kernel/apm.c187
-rw-r--r--arch/arm/kernel/asm-offsets.c1
-rw-r--r--arch/arm/kernel/ecard.c10
-rw-r--r--arch/arm/kernel/entry-armv.S9
-rw-r--r--arch/arm/kernel/head-nommu.S1
-rw-r--r--arch/arm/kernel/head.S1
-rw-r--r--arch/arm/kernel/irq.c8
-rw-r--r--arch/arm/kernel/iwmmxt-notifier.c63
-rw-r--r--arch/arm/kernel/process.c61
-rw-r--r--arch/arm/kernel/setup.c14
-rw-r--r--arch/arm/kernel/signal.c1
-rw-r--r--arch/arm/kernel/traps.c7
-rw-r--r--arch/arm/kernel/xscale-cp0.c179
-rw-r--r--arch/arm/mach-aaec2000/core.c4
-rw-r--r--arch/arm/mach-at91rm9200/Kconfig36
-rw-r--r--arch/arm/mach-at91rm9200/Makefile12
-rw-r--r--arch/arm/mach-at91rm9200/at91rm9200.c42
-rw-r--r--arch/arm/mach-at91rm9200/at91rm9200_devices.c (renamed from arch/arm/mach-at91rm9200/devices.c)160
-rw-r--r--arch/arm/mach-at91rm9200/at91rm9200_time.c5
-rw-r--r--arch/arm/mach-at91rm9200/at91sam9260.c294
-rw-r--r--arch/arm/mach-at91rm9200/at91sam9260_devices.c866
-rw-r--r--arch/arm/mach-at91rm9200/at91sam9261.c289
-rw-r--r--arch/arm/mach-at91rm9200/at91sam9261_devices.c741
-rw-r--r--arch/arm/mach-at91rm9200/at91sam926x_time.c114
-rw-r--r--arch/arm/mach-at91rm9200/board-carmeva.c32
-rw-r--r--arch/arm/mach-at91rm9200/board-csb337.c2
-rw-r--r--arch/arm/mach-at91rm9200/board-dk.c30
-rw-r--r--arch/arm/mach-at91rm9200/board-eb9200.c2
-rw-r--r--arch/arm/mach-at91rm9200/board-ek.c30
-rw-r--r--arch/arm/mach-at91rm9200/board-kb9202.c2
-rw-r--r--arch/arm/mach-at91rm9200/board-sam9260ek.c201
-rw-r--r--arch/arm/mach-at91rm9200/board-sam9261ek.c259
-rw-r--r--arch/arm/mach-at91rm9200/clock.c27
-rw-r--r--arch/arm/mach-at91rm9200/clock.h1
-rw-r--r--arch/arm/mach-at91rm9200/generic.h8
-rw-r--r--arch/arm/mach-at91rm9200/gpio.c10
-rw-r--r--arch/arm/mach-at91rm9200/irq.c16
-rw-r--r--arch/arm/mach-at91rm9200/pm.c24
-rw-r--r--arch/arm/mach-clps711x/irq.c8
-rw-r--r--arch/arm/mach-clps7500/core.c28
-rw-r--r--arch/arm/mach-ebsa110/core.c4
-rw-r--r--arch/arm/mach-ep93xx/Kconfig12
-rw-r--r--arch/arm/mach-ep93xx/Makefile2
-rw-r--r--arch/arm/mach-ep93xx/adssphere.c91
-rw-r--r--arch/arm/mach-ep93xx/core.c6
-rw-r--r--arch/arm/mach-ep93xx/edb9302a.c91
-rw-r--r--arch/arm/mach-footbridge/common.c4
-rw-r--r--arch/arm/mach-footbridge/isa-irq.c10
-rw-r--r--arch/arm/mach-h720x/common.c22
-rw-r--r--arch/arm/mach-h720x/cpu-h7202.c6
-rw-r--r--arch/arm/mach-imx/generic.c9
-rw-r--r--arch/arm/mach-imx/irq.c14
-rw-r--r--arch/arm/mach-imx/time.c86
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c2
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c8
-rw-r--r--arch/arm/mach-integrator/platsmp.c1
-rw-r--r--arch/arm/mach-iop13xx/Kconfig20
-rw-r--r--arch/arm/mach-iop13xx/Makefile12
-rw-r--r--arch/arm/mach-iop13xx/Makefile.boot3
-rw-r--r--arch/arm/mach-iop13xx/io.c93
-rw-r--r--arch/arm/mach-iop13xx/iq81340mc.c98
-rw-r--r--arch/arm/mach-iop13xx/iq81340sc.c100
-rw-r--r--arch/arm/mach-iop13xx/irq.c286
-rw-r--r--arch/arm/mach-iop13xx/pci.c1113
-rw-r--r--arch/arm/mach-iop13xx/setup.c406
-rw-r--r--arch/arm/mach-iop13xx/time.c102
-rw-r--r--arch/arm/mach-iop32x/irq.c2
-rw-r--r--arch/arm/mach-iop33x/irq.c2
-rw-r--r--arch/arm/mach-ixp2000/core.c20
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x00.c8
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c8
-rw-r--r--arch/arm/mach-ixp2000/pci.c2
-rw-r--r--arch/arm/mach-ixp23xx/core.c16
-rw-r--r--arch/arm/mach-ixp23xx/ixdp2351.c16
-rw-r--r--arch/arm/mach-ixp23xx/pci.c2
-rw-r--r--arch/arm/mach-ixp4xx/common.c51
-rw-r--r--arch/arm/mach-l7200/core.c4
-rw-r--r--arch/arm/mach-lh7a40x/arch-kev7a400.c4
-rw-r--r--arch/arm/mach-lh7a40x/arch-lpd7a40x.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-kev7a400.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-lh7a400.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-lh7a404.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-lpd7a40x.c4
-rw-r--r--arch/arm/mach-netx/generic.c6
-rw-r--r--arch/arm/mach-omap1/fpga.c6
-rw-r--r--arch/arm/mach-omap1/irq.c2
-rw-r--r--arch/arm/mach-omap2/irq.c2
-rw-r--r--arch/arm/mach-pnx4008/irq.c10
-rw-r--r--arch/arm/mach-pxa/Kconfig8
-rw-r--r--arch/arm/mach-pxa/irq.c10
-rw-r--r--arch/arm/mach-pxa/lpd270.c4
-rw-r--r--arch/arm/mach-pxa/lubbock.c4
-rw-r--r--arch/arm/mach-pxa/mainstone.c4
-rw-r--r--arch/arm/mach-pxa/pm.c3
-rw-r--r--arch/arm/mach-pxa/time.c7
-rw-r--r--arch/arm/mach-rpc/irq.c14
-rw-r--r--arch/arm/mach-s3c2410/Kconfig8
-rw-r--r--arch/arm/mach-s3c2410/Makefile1
-rw-r--r--arch/arm/mach-s3c2410/bast-irq.c8
-rw-r--r--arch/arm/mach-s3c2410/irq.c63
-rw-r--r--arch/arm/mach-s3c2410/irq.h2
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c8
-rw-r--r--arch/arm/mach-s3c2410/mach-osiris.c9
-rw-r--r--arch/arm/mach-s3c2410/mach-rx3715.c3
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c50
-rw-r--r--arch/arm/mach-s3c2410/pm-h1940.S33
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-pm.c30
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-irq.c4
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-irq.c10
-rw-r--r--arch/arm/mach-s3c2410/s3c244x-irq.c12
-rw-r--r--arch/arm/mach-sa1100/h3600.c6
-rw-r--r--arch/arm/mach-sa1100/irq.c8
-rw-r--r--arch/arm/mach-sa1100/neponset.c8
-rw-r--r--arch/arm/mach-sa1100/time.c7
-rw-r--r--arch/arm/mach-shark/irq.c2
-rw-r--r--arch/arm/mach-versatile/core.c4
-rw-r--r--arch/arm/mach-versatile/versatile_pb.c18
-rw-r--r--arch/arm/mm/Kconfig4
-rw-r--r--arch/arm/mm/mm.h5
-rw-r--r--arch/arm/mm/mmu.c9
-rw-r--r--arch/arm/mm/nommu.c4
-rw-r--r--arch/arm/mm/proc-arm1020.S2
-rw-r--r--arch/arm/mm/proc-arm1020e.S2
-rw-r--r--arch/arm/mm/proc-arm1022.S2
-rw-r--r--arch/arm/mm/proc-arm1026.S2
-rw-r--r--arch/arm/mm/proc-arm6_7.S2
-rw-r--r--arch/arm/mm/proc-arm720.S2
-rw-r--r--arch/arm/mm/proc-arm740.S2
-rw-r--r--arch/arm/mm/proc-arm7tdmi.S2
-rw-r--r--arch/arm/mm/proc-arm920.S2
-rw-r--r--arch/arm/mm/proc-arm922.S2
-rw-r--r--arch/arm/mm/proc-arm925.S2
-rw-r--r--arch/arm/mm/proc-arm926.S2
-rw-r--r--arch/arm/mm/proc-arm940.S2
-rw-r--r--arch/arm/mm/proc-arm946.S2
-rw-r--r--arch/arm/mm/proc-arm9tdmi.S2
-rw-r--r--arch/arm/mm/proc-sa110.S2
-rw-r--r--arch/arm/mm/proc-sa1100.S2
-rw-r--r--arch/arm/mm/proc-v6.S2
-rw-r--r--arch/arm/mm/proc-xsc3.S13
-rw-r--r--arch/arm/mm/proc-xscale.S11
-rw-r--r--arch/arm/plat-omap/gpio.c8
-rw-r--r--arch/arm/tools/mach-types58
-rw-r--r--drivers/amba/bus.c113
-rw-r--r--drivers/char/watchdog/at91rm9200_wdt.c1
-rw-r--r--drivers/i2c/busses/Kconfig6
-rw-r--r--drivers/i2c/busses/i2c-pxa.c131
-rw-r--r--drivers/mmc/Kconfig8
-rw-r--r--drivers/mmc/Makefile2
-rw-r--r--drivers/mmc/at91_mci.c4
-rw-r--r--drivers/pcmcia/at91_cf.c2
-rw-r--r--drivers/serial/atmel_serial.c10
-rw-r--r--drivers/serial/atmel_serial.h11
-rw-r--r--drivers/usb/Kconfig2
-rw-r--r--drivers/usb/gadget/Kconfig2
-rw-r--r--drivers/usb/host/ohci-hcd.c5
-rw-r--r--include/asm-arm/arch-aaec2000/memory.h40
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_aic.h53
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_dbgu.h45
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_ecc.h38
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_lcdc.h148
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_mci.h (renamed from include/asm-arm/arch-at91rm9200/at91rm9200_mci.h)24
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_pdc.h (renamed from include/asm-avr32/arch-at32ap/at91rm9200_pdc.h)6
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_pio.h49
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_pit.h29
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_pmc.h92
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_rstc.h39
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_rtc.h75
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_rtt.h32
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_shdwc.h33
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_spi.h (renamed from include/asm-arm/arch-at91rm9200/at91rm9200_spi.h)8
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_ssc.h (renamed from include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h)16
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_st.h49
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_tc.h (renamed from include/asm-arm/arch-at91rm9200/at91rm9200_tc.h)6
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_twi.h (renamed from include/asm-arm/arch-at91rm9200/at91rm9200_twi.h)10
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_wdt.h34
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200.h16
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_mc.h160
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_sys.h438
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_udp.h77
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam9260.h125
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h78
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam9261.h292
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h62
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam926x_mc.h134
-rw-r--r--include/asm-arm/arch-at91rm9200/board.h6
-rw-r--r--include/asm-arm/arch-at91rm9200/cpu.h49
-rw-r--r--include/asm-arm/arch-at91rm9200/debug-macro.S1
-rw-r--r--include/asm-arm/arch-at91rm9200/entry-macro.S1
-rw-r--r--include/asm-arm/arch-at91rm9200/hardware.h40
-rw-r--r--include/asm-arm/arch-at91rm9200/irqs.h2
-rw-r--r--include/asm-arm/arch-at91rm9200/system.h20
-rw-r--r--include/asm-arm/arch-at91rm9200/timex.h9
-rw-r--r--include/asm-arm/arch-at91rm9200/uncompress.h4
-rw-r--r--include/asm-arm/arch-at91rm9200/vmalloc.h2
-rw-r--r--include/asm-arm/arch-clps711x/memory.h53
-rw-r--r--include/asm-arm/arch-imx/timex.h3
-rw-r--r--include/asm-arm/arch-iop13xx/debug-macro.S26
-rw-r--r--include/asm-arm/arch-iop13xx/dma.h3
-rw-r--r--include/asm-arm/arch-iop13xx/entry-macro.S39
-rw-r--r--include/asm-arm/arch-iop13xx/hardware.h28
-rw-r--r--include/asm-arm/arch-iop13xx/io.h41
-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h492
-rw-r--r--include/asm-arm/arch-iop13xx/iq81340.h31
-rw-r--r--include/asm-arm/arch-iop13xx/irqs.h207
-rw-r--r--include/asm-arm/arch-iop13xx/memory.h64
-rw-r--r--include/asm-arm/arch-iop13xx/pci.h57
-rw-r--r--include/asm-arm/arch-iop13xx/system.h59
-rw-r--r--include/asm-arm/arch-iop13xx/timex.h3
-rw-r--r--include/asm-arm/arch-iop13xx/uncompress.h24
-rw-r--r--include/asm-arm/arch-iop13xx/vmalloc.h4
-rw-r--r--include/asm-arm/arch-ixp4xx/nslu2.h5
-rw-r--r--include/asm-arm/arch-ixp4xx/udc.h8
-rw-r--r--include/asm-arm/arch-l7200/io.h56
-rw-r--r--include/asm-arm/arch-lh7a40x/memory.h12
-rw-r--r--include/asm-arm/arch-pxa/memory.h36
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h13
-rw-r--r--include/asm-arm/arch-s3c2410/h1940.h21
-rw-r--r--include/asm-arm/arch-s3c2410/system.h2
-rw-r--r--include/asm-arm/arch-sa1100/jornada720.h42
-rw-r--r--include/asm-arm/arch-sa1100/memory.h34
-rw-r--r--include/asm-arm/bug.h4
-rw-r--r--include/asm-arm/elf.h150
-rw-r--r--include/asm-arm/io.h8
-rw-r--r--include/asm-arm/mach/irq.h12
-rw-r--r--include/asm-arm/memory.h39
-rw-r--r--include/asm-arm/pgtable-nommu.h1
-rw-r--r--include/asm-arm/pgtable.h3
-rw-r--r--include/asm-arm/processor.h1
-rw-r--r--include/asm-arm/procinfo.h21
-rw-r--r--include/asm-arm/thread_info.h14
-rw-r--r--include/asm-avr32/arch-at32ap/at91_pdc.h (renamed from include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h)6
-rw-r--r--include/linux/i2c-pxa.h31
286 files changed, 12799 insertions, 1973 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index e182992ff799..deae37416eec 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -348,6 +348,13 @@ P: Ian Molton
348M: spyro@f2s.com 348M: spyro@f2s.com
349S: Maintained 349S: Maintained
350 350
351ARM/ATMEL AT91RM9200 ARM ARCHITECTURE
352P: Andrew Victor
353M: andrew@sanpeople.com
354L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
355W: http://maxim.org.za/at91_26.html
356S: Maintained
357
351ARM/CORGI MACHINE SUPPORT 358ARM/CORGI MACHINE SUPPORT
352P: Richard Purdie 359P: Richard Purdie
353M: rpurdie@rpsys.net 360M: rpurdie@rpsys.net
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ce00c570459d..8c05d4321ae9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -223,6 +223,12 @@ config ARCH_IOP33X
223 help 223 help
224 Support for Intel's IOP33X (XScale) family of processors. 224 Support for Intel's IOP33X (XScale) family of processors.
225 225
226config ARCH_IOP13XX
227 bool "IOP13xx-based"
228 select PCI
229 help
230 Support for Intel's IOP13XX (XScale) family of processors.
231
226config ARCH_IXP4XX 232config ARCH_IXP4XX
227 bool "IXP4xx-based" 233 bool "IXP4xx-based"
228 depends on MMU 234 depends on MMU
@@ -331,6 +337,8 @@ source "arch/arm/mach-iop32x/Kconfig"
331 337
332source "arch/arm/mach-iop33x/Kconfig" 338source "arch/arm/mach-iop33x/Kconfig"
333 339
340source "arch/arm/mach-iop13xx/Kconfig"
341
334source "arch/arm/mach-ixp4xx/Kconfig" 342source "arch/arm/mach-ixp4xx/Kconfig"
335 343
336source "arch/arm/mach-ixp2000/Kconfig" 344source "arch/arm/mach-ixp2000/Kconfig"
@@ -374,6 +382,14 @@ config PLAT_IOP
374 382
375source arch/arm/mm/Kconfig 383source arch/arm/mm/Kconfig
376 384
385config IWMMXT
386 bool "Enable iWMMXt support"
387 depends CPU_XSCALE || CPU_XSC3
388 default y if PXA27x
389 help
390 Enable support for iWMMXt context switching at run time if
391 running on a CPU that supports it.
392
377# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER 393# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
378config XSCALE_PMU 394config XSCALE_PMU
379 bool 395 bool
@@ -583,7 +599,7 @@ config LEDS
583 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 599 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
584 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 600 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
585 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 601 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
586 ARCH_AT91RM9200 || MACH_TRIZEPS4 602 ARCH_AT91 || MACH_TRIZEPS4
587 help 603 help
588 If you say Y here, the LEDs on your machine will be used 604 If you say Y here, the LEDs on your machine will be used
589 to provide useful information about your current system status. 605 to provide useful information about your current system status.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index d22f38b957db..40c5eb1f55c7 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -32,10 +32,6 @@ config DEBUG_USER
32 8 - SIGSEGV faults 32 8 - SIGSEGV faults
33 16 - SIGBUS faults 33 16 - SIGBUS faults
34 34
35config DEBUG_WAITQ
36 bool "Wait queue debugging"
37 depends on DEBUG_KERNEL
38
39config DEBUG_ERRORS 35config DEBUG_ERRORS
40 bool "Verbose kernel error messages" 36 bool "Verbose kernel error messages"
41 depends on DEBUG_KERNEL 37 depends on DEBUG_KERNEL
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6f4f8bf36071..000f1100b553 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -15,6 +15,8 @@ CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
15OBJCOPYFLAGS :=-O binary -R .note -R .comment -S 15OBJCOPYFLAGS :=-O binary -R .note -R .comment -S
16GZFLAGS :=-9 16GZFLAGS :=-9
17#CFLAGS +=-pipe 17#CFLAGS +=-pipe
18# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
19CFLAGS +=$(call cc-option,-marm,)
18 20
19# Do not use arch/arm/defconfig - it's always outdated. 21# Do not use arch/arm/defconfig - it's always outdated.
20# Select a platform tht is kept up-to-date 22# Select a platform tht is kept up-to-date
@@ -108,6 +110,7 @@ endif
108 machine-$(CONFIG_ARCH_CLPS711X) := clps711x 110 machine-$(CONFIG_ARCH_CLPS711X) := clps711x
109 machine-$(CONFIG_ARCH_IOP32X) := iop32x 111 machine-$(CONFIG_ARCH_IOP32X) := iop32x
110 machine-$(CONFIG_ARCH_IOP33X) := iop33x 112 machine-$(CONFIG_ARCH_IOP33X) := iop33x
113 machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
111 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx 114 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
112 machine-$(CONFIG_ARCH_IXP2000) := ixp2000 115 machine-$(CONFIG_ARCH_IXP2000) := ixp2000
113 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx 116 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index f3e020f2227f..09b9d1b6844c 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -160,7 +160,7 @@ void __init gic_dist_init(void __iomem *base)
160 */ 160 */
161 for (i = 29; i < max_irq; i++) { 161 for (i = 29; i < max_irq; i++) {
162 set_irq_chip(i, &gic_chip); 162 set_irq_chip(i, &gic_chip);
163 set_irq_handler(i, do_level_IRQ); 163 set_irq_handler(i, handle_level_irq);
164 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 164 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
165 } 165 }
166 166
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 80a72c75214f..cfe6f4650bc9 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -163,11 +163,11 @@ static struct locomo_dev_info locomo_devices[] = {
163#define LOCOMO_IRQ_LT_START (IRQ_LOCOMO_LT) 163#define LOCOMO_IRQ_LT_START (IRQ_LOCOMO_LT)
164#define LOCOMO_IRQ_SPI_START (IRQ_LOCOMO_SPI_RFR) 164#define LOCOMO_IRQ_SPI_START (IRQ_LOCOMO_SPI_RFR)
165 165
166static void locomo_handler(unsigned int irq, struct irqdesc *desc) 166static void locomo_handler(unsigned int irq, struct irq_desc *desc)
167{ 167{
168 int req, i; 168 int req, i;
169 struct irqdesc *d; 169 struct irq_desc *d;
170 void __iomem *mapbase = get_irq_chipdata(irq); 170 void __iomem *mapbase = get_irq_chip_data(irq);
171 171
172 /* Acknowledge the parent IRQ */ 172 /* Acknowledge the parent IRQ */
173 desc->chip->ack(irq); 173 desc->chip->ack(irq);
@@ -194,7 +194,7 @@ static void locomo_ack_irq(unsigned int irq)
194 194
195static void locomo_mask_irq(unsigned int irq) 195static void locomo_mask_irq(unsigned int irq)
196{ 196{
197 void __iomem *mapbase = get_irq_chipdata(irq); 197 void __iomem *mapbase = get_irq_chip_data(irq);
198 unsigned int r; 198 unsigned int r;
199 r = locomo_readl(mapbase + LOCOMO_ICR); 199 r = locomo_readl(mapbase + LOCOMO_ICR);
200 r &= ~(0x0010 << (irq - LOCOMO_IRQ_START)); 200 r &= ~(0x0010 << (irq - LOCOMO_IRQ_START));
@@ -203,7 +203,7 @@ static void locomo_mask_irq(unsigned int irq)
203 203
204static void locomo_unmask_irq(unsigned int irq) 204static void locomo_unmask_irq(unsigned int irq)
205{ 205{
206 void __iomem *mapbase = get_irq_chipdata(irq); 206 void __iomem *mapbase = get_irq_chip_data(irq);
207 unsigned int r; 207 unsigned int r;
208 r = locomo_readl(mapbase + LOCOMO_ICR); 208 r = locomo_readl(mapbase + LOCOMO_ICR);
209 r |= (0x0010 << (irq - LOCOMO_IRQ_START)); 209 r |= (0x0010 << (irq - LOCOMO_IRQ_START));
@@ -217,10 +217,10 @@ static struct irq_chip locomo_chip = {
217 .unmask = locomo_unmask_irq, 217 .unmask = locomo_unmask_irq,
218}; 218};
219 219
220static void locomo_key_handler(unsigned int irq, struct irqdesc *desc) 220static void locomo_key_handler(unsigned int irq, struct irq_desc *desc)
221{ 221{
222 struct irqdesc *d; 222 struct irq_desc *d;
223 void __iomem *mapbase = get_irq_chipdata(irq); 223 void __iomem *mapbase = get_irq_chip_data(irq);
224 224
225 if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) { 225 if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) {
226 d = irq_desc + LOCOMO_IRQ_KEY_START; 226 d = irq_desc + LOCOMO_IRQ_KEY_START;
@@ -230,7 +230,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc)
230 230
231static void locomo_key_ack_irq(unsigned int irq) 231static void locomo_key_ack_irq(unsigned int irq)
232{ 232{
233 void __iomem *mapbase = get_irq_chipdata(irq); 233 void __iomem *mapbase = get_irq_chip_data(irq);
234 unsigned int r; 234 unsigned int r;
235 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); 235 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
236 r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START)); 236 r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START));
@@ -239,7 +239,7 @@ static void locomo_key_ack_irq(unsigned int irq)
239 239
240static void locomo_key_mask_irq(unsigned int irq) 240static void locomo_key_mask_irq(unsigned int irq)
241{ 241{
242 void __iomem *mapbase = get_irq_chipdata(irq); 242 void __iomem *mapbase = get_irq_chip_data(irq);
243 unsigned int r; 243 unsigned int r;
244 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); 244 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
245 r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START)); 245 r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@@ -248,7 +248,7 @@ static void locomo_key_mask_irq(unsigned int irq)
248 248
249static void locomo_key_unmask_irq(unsigned int irq) 249static void locomo_key_unmask_irq(unsigned int irq)
250{ 250{
251 void __iomem *mapbase = get_irq_chipdata(irq); 251 void __iomem *mapbase = get_irq_chip_data(irq);
252 unsigned int r; 252 unsigned int r;
253 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); 253 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
254 r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START)); 254 r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@@ -262,11 +262,11 @@ static struct irq_chip locomo_key_chip = {
262 .unmask = locomo_key_unmask_irq, 262 .unmask = locomo_key_unmask_irq,
263}; 263};
264 264
265static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc) 265static void locomo_gpio_handler(unsigned int irq, struct irq_desc *desc)
266{ 266{
267 int req, i; 267 int req, i;
268 struct irqdesc *d; 268 struct irq_desc *d;
269 void __iomem *mapbase = get_irq_chipdata(irq); 269 void __iomem *mapbase = get_irq_chip_data(irq);
270 270
271 req = locomo_readl(mapbase + LOCOMO_GIR) & 271 req = locomo_readl(mapbase + LOCOMO_GIR) &
272 locomo_readl(mapbase + LOCOMO_GPD) & 272 locomo_readl(mapbase + LOCOMO_GPD) &
@@ -285,7 +285,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc)
285 285
286static void locomo_gpio_ack_irq(unsigned int irq) 286static void locomo_gpio_ack_irq(unsigned int irq)
287{ 287{
288 void __iomem *mapbase = get_irq_chipdata(irq); 288 void __iomem *mapbase = get_irq_chip_data(irq);
289 unsigned int r; 289 unsigned int r;
290 r = locomo_readl(mapbase + LOCOMO_GWE); 290 r = locomo_readl(mapbase + LOCOMO_GWE);
291 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); 291 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -302,7 +302,7 @@ static void locomo_gpio_ack_irq(unsigned int irq)
302 302
303static void locomo_gpio_mask_irq(unsigned int irq) 303static void locomo_gpio_mask_irq(unsigned int irq)
304{ 304{
305 void __iomem *mapbase = get_irq_chipdata(irq); 305 void __iomem *mapbase = get_irq_chip_data(irq);
306 unsigned int r; 306 unsigned int r;
307 r = locomo_readl(mapbase + LOCOMO_GIE); 307 r = locomo_readl(mapbase + LOCOMO_GIE);
308 r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); 308 r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -311,7 +311,7 @@ static void locomo_gpio_mask_irq(unsigned int irq)
311 311
312static void locomo_gpio_unmask_irq(unsigned int irq) 312static void locomo_gpio_unmask_irq(unsigned int irq)
313{ 313{
314 void __iomem *mapbase = get_irq_chipdata(irq); 314 void __iomem *mapbase = get_irq_chip_data(irq);
315 unsigned int r; 315 unsigned int r;
316 r = locomo_readl(mapbase + LOCOMO_GIE); 316 r = locomo_readl(mapbase + LOCOMO_GIE);
317 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); 317 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -325,10 +325,10 @@ static struct irq_chip locomo_gpio_chip = {
325 .unmask = locomo_gpio_unmask_irq, 325 .unmask = locomo_gpio_unmask_irq,
326}; 326};
327 327
328static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc) 328static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc)
329{ 329{
330 struct irqdesc *d; 330 struct irq_desc *d;
331 void __iomem *mapbase = get_irq_chipdata(irq); 331 void __iomem *mapbase = get_irq_chip_data(irq);
332 332
333 if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) { 333 if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) {
334 d = irq_desc + LOCOMO_IRQ_LT_START; 334 d = irq_desc + LOCOMO_IRQ_LT_START;
@@ -338,7 +338,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc)
338 338
339static void locomo_lt_ack_irq(unsigned int irq) 339static void locomo_lt_ack_irq(unsigned int irq)
340{ 340{
341 void __iomem *mapbase = get_irq_chipdata(irq); 341 void __iomem *mapbase = get_irq_chip_data(irq);
342 unsigned int r; 342 unsigned int r;
343 r = locomo_readl(mapbase + LOCOMO_LTINT); 343 r = locomo_readl(mapbase + LOCOMO_LTINT);
344 r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START)); 344 r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START));
@@ -347,7 +347,7 @@ static void locomo_lt_ack_irq(unsigned int irq)
347 347
348static void locomo_lt_mask_irq(unsigned int irq) 348static void locomo_lt_mask_irq(unsigned int irq)
349{ 349{
350 void __iomem *mapbase = get_irq_chipdata(irq); 350 void __iomem *mapbase = get_irq_chip_data(irq);
351 unsigned int r; 351 unsigned int r;
352 r = locomo_readl(mapbase + LOCOMO_LTINT); 352 r = locomo_readl(mapbase + LOCOMO_LTINT);
353 r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START)); 353 r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START));
@@ -356,7 +356,7 @@ static void locomo_lt_mask_irq(unsigned int irq)
356 356
357static void locomo_lt_unmask_irq(unsigned int irq) 357static void locomo_lt_unmask_irq(unsigned int irq)
358{ 358{
359 void __iomem *mapbase = get_irq_chipdata(irq); 359 void __iomem *mapbase = get_irq_chip_data(irq);
360 unsigned int r; 360 unsigned int r;
361 r = locomo_readl(mapbase + LOCOMO_LTINT); 361 r = locomo_readl(mapbase + LOCOMO_LTINT);
362 r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START)); 362 r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START));
@@ -370,11 +370,11 @@ static struct irq_chip locomo_lt_chip = {
370 .unmask = locomo_lt_unmask_irq, 370 .unmask = locomo_lt_unmask_irq,
371}; 371};
372 372
373static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc) 373static void locomo_spi_handler(unsigned int irq, struct irq_desc *desc)
374{ 374{
375 int req, i; 375 int req, i;
376 struct irqdesc *d; 376 struct irq_desc *d;
377 void __iomem *mapbase = get_irq_chipdata(irq); 377 void __iomem *mapbase = get_irq_chip_data(irq);
378 378
379 req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F; 379 req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F;
380 if (req) { 380 if (req) {
@@ -391,7 +391,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc)
391 391
392static void locomo_spi_ack_irq(unsigned int irq) 392static void locomo_spi_ack_irq(unsigned int irq)
393{ 393{
394 void __iomem *mapbase = get_irq_chipdata(irq); 394 void __iomem *mapbase = get_irq_chip_data(irq);
395 unsigned int r; 395 unsigned int r;
396 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE); 396 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE);
397 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 397 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -408,7 +408,7 @@ static void locomo_spi_ack_irq(unsigned int irq)
408 408
409static void locomo_spi_mask_irq(unsigned int irq) 409static void locomo_spi_mask_irq(unsigned int irq)
410{ 410{
411 void __iomem *mapbase = get_irq_chipdata(irq); 411 void __iomem *mapbase = get_irq_chip_data(irq);
412 unsigned int r; 412 unsigned int r;
413 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE); 413 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
414 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 414 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -417,7 +417,7 @@ static void locomo_spi_mask_irq(unsigned int irq)
417 417
418static void locomo_spi_unmask_irq(unsigned int irq) 418static void locomo_spi_unmask_irq(unsigned int irq)
419{ 419{
420 void __iomem *mapbase = get_irq_chipdata(irq); 420 void __iomem *mapbase = get_irq_chip_data(irq);
421 unsigned int r; 421 unsigned int r;
422 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE); 422 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
423 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 423 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -440,55 +440,55 @@ static void locomo_setup_irq(struct locomo *lchip)
440 * Install handler for IRQ_LOCOMO_HW. 440 * Install handler for IRQ_LOCOMO_HW.
441 */ 441 */
442 set_irq_type(lchip->irq, IRQT_FALLING); 442 set_irq_type(lchip->irq, IRQT_FALLING);
443 set_irq_chipdata(lchip->irq, irqbase); 443 set_irq_chip_data(lchip->irq, irqbase);
444 set_irq_chained_handler(lchip->irq, locomo_handler); 444 set_irq_chained_handler(lchip->irq, locomo_handler);
445 445
446 /* Install handlers for IRQ_LOCOMO_*_BASE */ 446 /* Install handlers for IRQ_LOCOMO_*_BASE */
447 set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip); 447 set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip);
448 set_irq_chipdata(IRQ_LOCOMO_KEY_BASE, irqbase); 448 set_irq_chip_data(IRQ_LOCOMO_KEY_BASE, irqbase);
449 set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler); 449 set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler);
450 set_irq_flags(IRQ_LOCOMO_KEY_BASE, IRQF_VALID | IRQF_PROBE); 450 set_irq_flags(IRQ_LOCOMO_KEY_BASE, IRQF_VALID | IRQF_PROBE);
451 451
452 set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip); 452 set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip);
453 set_irq_chipdata(IRQ_LOCOMO_GPIO_BASE, irqbase); 453 set_irq_chip_data(IRQ_LOCOMO_GPIO_BASE, irqbase);
454 set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler); 454 set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler);
455 set_irq_flags(IRQ_LOCOMO_GPIO_BASE, IRQF_VALID | IRQF_PROBE); 455 set_irq_flags(IRQ_LOCOMO_GPIO_BASE, IRQF_VALID | IRQF_PROBE);
456 456
457 set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip); 457 set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip);
458 set_irq_chipdata(IRQ_LOCOMO_LT_BASE, irqbase); 458 set_irq_chip_data(IRQ_LOCOMO_LT_BASE, irqbase);
459 set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler); 459 set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler);
460 set_irq_flags(IRQ_LOCOMO_LT_BASE, IRQF_VALID | IRQF_PROBE); 460 set_irq_flags(IRQ_LOCOMO_LT_BASE, IRQF_VALID | IRQF_PROBE);
461 461
462 set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip); 462 set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip);
463 set_irq_chipdata(IRQ_LOCOMO_SPI_BASE, irqbase); 463 set_irq_chip_data(IRQ_LOCOMO_SPI_BASE, irqbase);
464 set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler); 464 set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler);
465 set_irq_flags(IRQ_LOCOMO_SPI_BASE, IRQF_VALID | IRQF_PROBE); 465 set_irq_flags(IRQ_LOCOMO_SPI_BASE, IRQF_VALID | IRQF_PROBE);
466 466
467 /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */ 467 /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */
468 set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip); 468 set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip);
469 set_irq_chipdata(LOCOMO_IRQ_KEY_START, irqbase); 469 set_irq_chip_data(LOCOMO_IRQ_KEY_START, irqbase);
470 set_irq_handler(LOCOMO_IRQ_KEY_START, do_edge_IRQ); 470 set_irq_handler(LOCOMO_IRQ_KEY_START, handle_edge_irq);
471 set_irq_flags(LOCOMO_IRQ_KEY_START, IRQF_VALID | IRQF_PROBE); 471 set_irq_flags(LOCOMO_IRQ_KEY_START, IRQF_VALID | IRQF_PROBE);
472 472
473 /* install handlers for IRQ_LOCOMO_GPIO_BASE generated interrupts */ 473 /* install handlers for IRQ_LOCOMO_GPIO_BASE generated interrupts */
474 for (irq = LOCOMO_IRQ_GPIO_START; irq < LOCOMO_IRQ_GPIO_START + 16; irq++) { 474 for (irq = LOCOMO_IRQ_GPIO_START; irq < LOCOMO_IRQ_GPIO_START + 16; irq++) {
475 set_irq_chip(irq, &locomo_gpio_chip); 475 set_irq_chip(irq, &locomo_gpio_chip);
476 set_irq_chipdata(irq, irqbase); 476 set_irq_chip_data(irq, irqbase);
477 set_irq_handler(irq, do_edge_IRQ); 477 set_irq_handler(irq, handle_edge_irq);
478 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 478 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
479 } 479 }
480 480
481 /* install handlers for IRQ_LOCOMO_LT_BASE generated interrupts */ 481 /* install handlers for IRQ_LOCOMO_LT_BASE generated interrupts */
482 set_irq_chip(LOCOMO_IRQ_LT_START, &locomo_lt_chip); 482 set_irq_chip(LOCOMO_IRQ_LT_START, &locomo_lt_chip);
483 set_irq_chipdata(LOCOMO_IRQ_LT_START, irqbase); 483 set_irq_chip_data(LOCOMO_IRQ_LT_START, irqbase);
484 set_irq_handler(LOCOMO_IRQ_LT_START, do_edge_IRQ); 484 set_irq_handler(LOCOMO_IRQ_LT_START, handle_edge_irq);
485 set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE); 485 set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE);
486 486
487 /* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */ 487 /* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */
488 for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 3; irq++) { 488 for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 3; irq++) {
489 set_irq_chip(irq, &locomo_spi_chip); 489 set_irq_chip(irq, &locomo_spi_chip);
490 set_irq_chipdata(irq, irqbase); 490 set_irq_chip_data(irq, irqbase);
491 set_irq_handler(irq, do_edge_IRQ); 491 set_irq_handler(irq, handle_edge_irq);
492 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 492 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
493 } 493 }
494} 494}
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index d5f72010a6f3..fe3f05901a23 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -147,7 +147,7 @@ void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *ho
147 * will call us again if there are more interrupts to process. 147 * will call us again if there are more interrupts to process.
148 */ 148 */
149static void 149static void
150sa1111_irq_handler(unsigned int irq, struct irqdesc *desc) 150sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
151{ 151{
152 unsigned int stat0, stat1, i; 152 unsigned int stat0, stat1, i;
153 void __iomem *base = get_irq_data(irq); 153 void __iomem *base = get_irq_data(irq);
@@ -187,7 +187,7 @@ static void sa1111_ack_irq(unsigned int irq)
187 187
188static void sa1111_mask_lowirq(unsigned int irq) 188static void sa1111_mask_lowirq(unsigned int irq)
189{ 189{
190 void __iomem *mapbase = get_irq_chipdata(irq); 190 void __iomem *mapbase = get_irq_chip_data(irq);
191 unsigned long ie0; 191 unsigned long ie0;
192 192
193 ie0 = sa1111_readl(mapbase + SA1111_INTEN0); 193 ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
@@ -197,7 +197,7 @@ static void sa1111_mask_lowirq(unsigned int irq)
197 197
198static void sa1111_unmask_lowirq(unsigned int irq) 198static void sa1111_unmask_lowirq(unsigned int irq)
199{ 199{
200 void __iomem *mapbase = get_irq_chipdata(irq); 200 void __iomem *mapbase = get_irq_chip_data(irq);
201 unsigned long ie0; 201 unsigned long ie0;
202 202
203 ie0 = sa1111_readl(mapbase + SA1111_INTEN0); 203 ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
@@ -215,7 +215,7 @@ static void sa1111_unmask_lowirq(unsigned int irq)
215static int sa1111_retrigger_lowirq(unsigned int irq) 215static int sa1111_retrigger_lowirq(unsigned int irq)
216{ 216{
217 unsigned int mask = SA1111_IRQMASK_LO(irq); 217 unsigned int mask = SA1111_IRQMASK_LO(irq);
218 void __iomem *mapbase = get_irq_chipdata(irq); 218 void __iomem *mapbase = get_irq_chip_data(irq);
219 unsigned long ip0; 219 unsigned long ip0;
220 int i; 220 int i;
221 221
@@ -236,7 +236,7 @@ static int sa1111_retrigger_lowirq(unsigned int irq)
236static int sa1111_type_lowirq(unsigned int irq, unsigned int flags) 236static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
237{ 237{
238 unsigned int mask = SA1111_IRQMASK_LO(irq); 238 unsigned int mask = SA1111_IRQMASK_LO(irq);
239 void __iomem *mapbase = get_irq_chipdata(irq); 239 void __iomem *mapbase = get_irq_chip_data(irq);
240 unsigned long ip0; 240 unsigned long ip0;
241 241
242 if (flags == IRQT_PROBE) 242 if (flags == IRQT_PROBE)
@@ -259,7 +259,7 @@ static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
259static int sa1111_wake_lowirq(unsigned int irq, unsigned int on) 259static int sa1111_wake_lowirq(unsigned int irq, unsigned int on)
260{ 260{
261 unsigned int mask = SA1111_IRQMASK_LO(irq); 261 unsigned int mask = SA1111_IRQMASK_LO(irq);
262 void __iomem *mapbase = get_irq_chipdata(irq); 262 void __iomem *mapbase = get_irq_chip_data(irq);
263 unsigned long we0; 263 unsigned long we0;
264 264
265 we0 = sa1111_readl(mapbase + SA1111_WAKEEN0); 265 we0 = sa1111_readl(mapbase + SA1111_WAKEEN0);
@@ -284,7 +284,7 @@ static struct irq_chip sa1111_low_chip = {
284 284
285static void sa1111_mask_highirq(unsigned int irq) 285static void sa1111_mask_highirq(unsigned int irq)
286{ 286{
287 void __iomem *mapbase = get_irq_chipdata(irq); 287 void __iomem *mapbase = get_irq_chip_data(irq);
288 unsigned long ie1; 288 unsigned long ie1;
289 289
290 ie1 = sa1111_readl(mapbase + SA1111_INTEN1); 290 ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
@@ -294,7 +294,7 @@ static void sa1111_mask_highirq(unsigned int irq)
294 294
295static void sa1111_unmask_highirq(unsigned int irq) 295static void sa1111_unmask_highirq(unsigned int irq)
296{ 296{
297 void __iomem *mapbase = get_irq_chipdata(irq); 297 void __iomem *mapbase = get_irq_chip_data(irq);
298 unsigned long ie1; 298 unsigned long ie1;
299 299
300 ie1 = sa1111_readl(mapbase + SA1111_INTEN1); 300 ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
@@ -312,7 +312,7 @@ static void sa1111_unmask_highirq(unsigned int irq)
312static int sa1111_retrigger_highirq(unsigned int irq) 312static int sa1111_retrigger_highirq(unsigned int irq)
313{ 313{
314 unsigned int mask = SA1111_IRQMASK_HI(irq); 314 unsigned int mask = SA1111_IRQMASK_HI(irq);
315 void __iomem *mapbase = get_irq_chipdata(irq); 315 void __iomem *mapbase = get_irq_chip_data(irq);
316 unsigned long ip1; 316 unsigned long ip1;
317 int i; 317 int i;
318 318
@@ -333,7 +333,7 @@ static int sa1111_retrigger_highirq(unsigned int irq)
333static int sa1111_type_highirq(unsigned int irq, unsigned int flags) 333static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
334{ 334{
335 unsigned int mask = SA1111_IRQMASK_HI(irq); 335 unsigned int mask = SA1111_IRQMASK_HI(irq);
336 void __iomem *mapbase = get_irq_chipdata(irq); 336 void __iomem *mapbase = get_irq_chip_data(irq);
337 unsigned long ip1; 337 unsigned long ip1;
338 338
339 if (flags == IRQT_PROBE) 339 if (flags == IRQT_PROBE)
@@ -356,7 +356,7 @@ static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
356static int sa1111_wake_highirq(unsigned int irq, unsigned int on) 356static int sa1111_wake_highirq(unsigned int irq, unsigned int on)
357{ 357{
358 unsigned int mask = SA1111_IRQMASK_HI(irq); 358 unsigned int mask = SA1111_IRQMASK_HI(irq);
359 void __iomem *mapbase = get_irq_chipdata(irq); 359 void __iomem *mapbase = get_irq_chip_data(irq);
360 unsigned long we1; 360 unsigned long we1;
361 361
362 we1 = sa1111_readl(mapbase + SA1111_WAKEEN1); 362 we1 = sa1111_readl(mapbase + SA1111_WAKEEN1);
@@ -410,15 +410,15 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
410 410
411 for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { 411 for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
412 set_irq_chip(irq, &sa1111_low_chip); 412 set_irq_chip(irq, &sa1111_low_chip);
413 set_irq_chipdata(irq, irqbase); 413 set_irq_chip_data(irq, irqbase);
414 set_irq_handler(irq, do_edge_IRQ); 414 set_irq_handler(irq, handle_edge_irq);
415 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 415 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
416 } 416 }
417 417
418 for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { 418 for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
419 set_irq_chip(irq, &sa1111_high_chip); 419 set_irq_chip(irq, &sa1111_high_chip);
420 set_irq_chipdata(irq, irqbase); 420 set_irq_chip_data(irq, irqbase);
421 set_irq_handler(irq, do_edge_IRQ); 421 set_irq_handler(irq, handle_edge_irq);
422 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 422 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
423 } 423 }
424 424
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 43d278134521..c026fa2214a3 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -27,14 +27,14 @@
27 27
28static void vic_mask_irq(unsigned int irq) 28static void vic_mask_irq(unsigned int irq)
29{ 29{
30 void __iomem *base = get_irq_chipdata(irq); 30 void __iomem *base = get_irq_chip_data(irq);
31 irq &= 31; 31 irq &= 31;
32 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); 32 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
33} 33}
34 34
35static void vic_unmask_irq(unsigned int irq) 35static void vic_unmask_irq(unsigned int irq)
36{ 36{
37 void __iomem *base = get_irq_chipdata(irq); 37 void __iomem *base = get_irq_chip_data(irq);
38 irq &= 31; 38 irq &= 31;
39 writel(1 << irq, base + VIC_INT_ENABLE); 39 writel(1 << irq, base + VIC_INT_ENABLE);
40} 40}
@@ -88,10 +88,10 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
88 unsigned int irq = irq_start + i; 88 unsigned int irq = irq_start + i;
89 89
90 set_irq_chip(irq, &vic_chip); 90 set_irq_chip(irq, &vic_chip);
91 set_irq_chipdata(irq, base); 91 set_irq_chip_data(irq, base);
92 92
93 if (vic_sources & (1 << i)) { 93 if (vic_sources & (1 << i)) {
94 set_irq_handler(irq, do_level_IRQ); 94 set_irq_handler(irq, handle_level_irq);
95 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 95 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
96 } 96 }
97 } 97 }
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
index b43041476e02..e10d003566d6 100644
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ b/arch/arm/configs/at91rm9200dk_defconfig
@@ -357,9 +357,9 @@ CONFIG_MTD_CFI_UTIL=y
357# 357#
358# CONFIG_MTD_COMPLEX_MAPPINGS is not set 358# CONFIG_MTD_COMPLEX_MAPPINGS is not set
359CONFIG_MTD_PHYSMAP=y 359CONFIG_MTD_PHYSMAP=y
360CONFIG_MTD_PHYSMAP_START=0x10000000 360CONFIG_MTD_PHYSMAP_START=0
361CONFIG_MTD_PHYSMAP_LEN=0x200000 361CONFIG_MTD_PHYSMAP_LEN=0
362CONFIG_MTD_PHYSMAP_BANKWIDTH=2 362CONFIG_MTD_PHYSMAP_BANKWIDTH=0
363# CONFIG_MTD_ARM_INTEGRATOR is not set 363# CONFIG_MTD_ARM_INTEGRATOR is not set
364# CONFIG_MTD_IMPA7 is not set 364# CONFIG_MTD_IMPA7 is not set
365# CONFIG_MTD_PLATRAM is not set 365# CONFIG_MTD_PLATRAM is not set
@@ -585,7 +585,9 @@ CONFIG_AT91RM9200_WATCHDOG=y
585# CONFIG_USBPCWATCHDOG is not set 585# CONFIG_USBPCWATCHDOG is not set
586# CONFIG_NVRAM is not set 586# CONFIG_NVRAM is not set
587# CONFIG_RTC is not set 587# CONFIG_RTC is not set
588CONFIG_AT91_RTC=y 588CONFIG_RTC_LIB=y
589CONFIG_RTC_CLASS=y
590CONFIG_RTC_DRV_AT91RM9200=y
589# CONFIG_DTLK is not set 591# CONFIG_DTLK is not set
590# CONFIG_R3964 is not set 592# CONFIG_R3964 is not set
591 593
@@ -979,7 +981,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
979CONFIG_FRAME_POINTER=y 981CONFIG_FRAME_POINTER=y
980# CONFIG_RCU_TORTURE_TEST is not set 982# CONFIG_RCU_TORTURE_TEST is not set
981CONFIG_DEBUG_USER=y 983CONFIG_DEBUG_USER=y
982# CONFIG_DEBUG_WAITQ is not set
983# CONFIG_DEBUG_ERRORS is not set 984# CONFIG_DEBUG_ERRORS is not set
984CONFIG_DEBUG_LL=y 985CONFIG_DEBUG_LL=y
985# CONFIG_DEBUG_ICEDCC is not set 986# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index d96fc8386e2f..834dddb51314 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -348,9 +348,9 @@ CONFIG_MTD_CFI_UTIL=y
348# 348#
349# CONFIG_MTD_COMPLEX_MAPPINGS is not set 349# CONFIG_MTD_COMPLEX_MAPPINGS is not set
350CONFIG_MTD_PHYSMAP=y 350CONFIG_MTD_PHYSMAP=y
351CONFIG_MTD_PHYSMAP_START=0x10000000 351CONFIG_MTD_PHYSMAP_START=0
352CONFIG_MTD_PHYSMAP_LEN=0x800000 352CONFIG_MTD_PHYSMAP_LEN=0
353CONFIG_MTD_PHYSMAP_BANKWIDTH=2 353CONFIG_MTD_PHYSMAP_BANKWIDTH=0
354# CONFIG_MTD_ARM_INTEGRATOR is not set 354# CONFIG_MTD_ARM_INTEGRATOR is not set
355# CONFIG_MTD_IMPA7 is not set 355# CONFIG_MTD_IMPA7 is not set
356# CONFIG_MTD_PLATRAM is not set 356# CONFIG_MTD_PLATRAM is not set
@@ -566,7 +566,9 @@ CONFIG_AT91RM9200_WATCHDOG=y
566# CONFIG_USBPCWATCHDOG is not set 566# CONFIG_USBPCWATCHDOG is not set
567# CONFIG_NVRAM is not set 567# CONFIG_NVRAM is not set
568# CONFIG_RTC is not set 568# CONFIG_RTC is not set
569CONFIG_AT91_RTC=y 569CONFIG_RTC_LIB=y
570CONFIG_RTC_CLASS=y
571CONFIG_RTC_DRV_AT91RM9200=y
570# CONFIG_DTLK is not set 572# CONFIG_DTLK is not set
571# CONFIG_R3964 is not set 573# CONFIG_R3964 is not set
572 574
@@ -968,7 +970,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
968CONFIG_FRAME_POINTER=y 970CONFIG_FRAME_POINTER=y
969# CONFIG_RCU_TORTURE_TEST is not set 971# CONFIG_RCU_TORTURE_TEST is not set
970CONFIG_DEBUG_USER=y 972CONFIG_DEBUG_USER=y
971# CONFIG_DEBUG_WAITQ is not set
972# CONFIG_DEBUG_ERRORS is not set 973# CONFIG_DEBUG_ERRORS is not set
973CONFIG_DEBUG_LL=y 974CONFIG_DEBUG_LL=y
974# CONFIG_DEBUG_ICEDCC is not set 975# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig
new file mode 100644
index 000000000000..79049206dfa5
--- /dev/null
+++ b/arch/arm/configs/at91sam9260ek_defconfig
@@ -0,0 +1,950 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.19-rc6
4# Fri Nov 17 18:42:21 2006
5#
6CONFIG_ARM=y
7# CONFIG_GENERIC_TIME is not set
8CONFIG_MMU=y
9CONFIG_GENERIC_HARDIRQS=y
10CONFIG_TRACE_IRQFLAGS_SUPPORT=y
11CONFIG_HARDIRQS_SW_RESEND=y
12CONFIG_GENERIC_IRQ_PROBE=y
13CONFIG_RWSEM_GENERIC_SPINLOCK=y
14CONFIG_GENERIC_HWEIGHT=y
15CONFIG_GENERIC_CALIBRATE_DELAY=y
16CONFIG_VECTORS_BASE=0xffff0000
17CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
18
19#
20# Code maturity level options
21#
22CONFIG_EXPERIMENTAL=y
23CONFIG_BROKEN_ON_SMP=y
24CONFIG_INIT_ENV_ARG_LIMIT=32
25
26#
27# General setup
28#
29CONFIG_LOCALVERSION=""
30# CONFIG_LOCALVERSION_AUTO is not set
31# CONFIG_SWAP is not set
32CONFIG_SYSVIPC=y
33# CONFIG_IPC_NS is not set
34# CONFIG_POSIX_MQUEUE is not set
35# CONFIG_BSD_PROCESS_ACCT is not set
36# CONFIG_TASKSTATS is not set
37# CONFIG_UTS_NS is not set
38# CONFIG_AUDIT is not set
39# CONFIG_IKCONFIG is not set
40# CONFIG_RELAY is not set
41CONFIG_INITRAMFS_SOURCE=""
42CONFIG_CC_OPTIMIZE_FOR_SIZE=y
43CONFIG_SYSCTL=y
44# CONFIG_EMBEDDED is not set
45CONFIG_UID16=y
46CONFIG_SYSCTL_SYSCALL=y
47CONFIG_KALLSYMS=y
48# CONFIG_KALLSYMS_ALL is not set
49# CONFIG_KALLSYMS_EXTRA_PASS is not set
50CONFIG_HOTPLUG=y
51CONFIG_PRINTK=y
52CONFIG_BUG=y
53CONFIG_ELF_CORE=y
54CONFIG_BASE_FULL=y
55CONFIG_FUTEX=y
56CONFIG_EPOLL=y
57CONFIG_SHMEM=y
58CONFIG_SLAB=y
59CONFIG_VM_EVENT_COUNTERS=y
60CONFIG_RT_MUTEXES=y
61# CONFIG_TINY_SHMEM is not set
62CONFIG_BASE_SMALL=0
63# CONFIG_SLOB is not set
64
65#
66# Loadable module support
67#
68CONFIG_MODULES=y
69CONFIG_MODULE_UNLOAD=y
70# CONFIG_MODULE_FORCE_UNLOAD is not set
71# CONFIG_MODVERSIONS is not set
72# CONFIG_MODULE_SRCVERSION_ALL is not set
73CONFIG_KMOD=y
74
75#
76# Block layer
77#
78CONFIG_BLOCK=y
79# CONFIG_BLK_DEV_IO_TRACE is not set
80
81#
82# IO Schedulers
83#
84CONFIG_IOSCHED_NOOP=y
85CONFIG_IOSCHED_AS=y
86# CONFIG_IOSCHED_DEADLINE is not set
87# CONFIG_IOSCHED_CFQ is not set
88CONFIG_DEFAULT_AS=y
89# CONFIG_DEFAULT_DEADLINE is not set
90# CONFIG_DEFAULT_CFQ is not set
91# CONFIG_DEFAULT_NOOP is not set
92CONFIG_DEFAULT_IOSCHED="anticipatory"
93
94#
95# System Type
96#
97# CONFIG_ARCH_AAEC2000 is not set
98# CONFIG_ARCH_INTEGRATOR is not set
99# CONFIG_ARCH_REALVIEW is not set
100# CONFIG_ARCH_VERSATILE is not set
101CONFIG_ARCH_AT91=y
102# CONFIG_ARCH_CLPS7500 is not set
103# CONFIG_ARCH_CLPS711X is not set
104# CONFIG_ARCH_CO285 is not set
105# CONFIG_ARCH_EBSA110 is not set
106# CONFIG_ARCH_EP93XX is not set
107# CONFIG_ARCH_FOOTBRIDGE is not set
108# CONFIG_ARCH_NETX is not set
109# CONFIG_ARCH_H720X is not set
110# CONFIG_ARCH_IMX is not set
111# CONFIG_ARCH_IOP32X is not set
112# CONFIG_ARCH_IOP33X is not set
113# CONFIG_ARCH_IXP4XX is not set
114# CONFIG_ARCH_IXP2000 is not set
115# CONFIG_ARCH_IXP23XX is not set
116# CONFIG_ARCH_L7200 is not set
117# CONFIG_ARCH_PNX4008 is not set
118# CONFIG_ARCH_PXA is not set
119# CONFIG_ARCH_RPC is not set
120# CONFIG_ARCH_SA1100 is not set
121# CONFIG_ARCH_S3C2410 is not set
122# CONFIG_ARCH_SHARK is not set
123# CONFIG_ARCH_LH7A40X is not set
124# CONFIG_ARCH_OMAP is not set
125
126#
127# Atmel AT91 System-on-Chip
128#
129# CONFIG_ARCH_AT91RM9200 is not set
130CONFIG_ARCH_AT91SAM9260=y
131# CONFIG_ARCH_AT91SAM9261 is not set
132
133#
134# AT91SAM9260 Board Type
135#
136CONFIG_MACH_AT91SAM9260EK=y
137
138#
139# AT91 Board Options
140#
141# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
142
143#
144# AT91 Feature Selections
145#
146# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
147
148#
149# Processor Type
150#
151CONFIG_CPU_32=y
152CONFIG_CPU_ARM926T=y
153CONFIG_CPU_32v5=y
154CONFIG_CPU_ABRT_EV5TJ=y
155CONFIG_CPU_CACHE_VIVT=y
156CONFIG_CPU_COPY_V4WB=y
157CONFIG_CPU_TLB_V4WBI=y
158CONFIG_CPU_CP15=y
159CONFIG_CPU_CP15_MMU=y
160
161#
162# Processor Features
163#
164# CONFIG_ARM_THUMB is not set
165# CONFIG_CPU_ICACHE_DISABLE is not set
166# CONFIG_CPU_DCACHE_DISABLE is not set
167# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
168# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
169
170#
171# Bus support
172#
173
174#
175# PCCARD (PCMCIA/CardBus) support
176#
177# CONFIG_PCCARD is not set
178
179#
180# Kernel Features
181#
182# CONFIG_PREEMPT is not set
183# CONFIG_NO_IDLE_HZ is not set
184CONFIG_HZ=100
185# CONFIG_AEABI is not set
186# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
187CONFIG_SELECT_MEMORY_MODEL=y
188CONFIG_FLATMEM_MANUAL=y
189# CONFIG_DISCONTIGMEM_MANUAL is not set
190# CONFIG_SPARSEMEM_MANUAL is not set
191CONFIG_FLATMEM=y
192CONFIG_FLAT_NODE_MEM_MAP=y
193# CONFIG_SPARSEMEM_STATIC is not set
194CONFIG_SPLIT_PTLOCK_CPUS=4096
195# CONFIG_RESOURCES_64BIT is not set
196# CONFIG_LEDS is not set
197CONFIG_ALIGNMENT_TRAP=y
198
199#
200# Boot options
201#
202CONFIG_ZBOOT_ROM_TEXT=0x0
203CONFIG_ZBOOT_ROM_BSS=0x0
204CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
205# CONFIG_XIP_KERNEL is not set
206
207#
208# Floating point emulation
209#
210
211#
212# At least one emulation must be selected
213#
214CONFIG_FPE_NWFPE=y
215# CONFIG_FPE_NWFPE_XP is not set
216# CONFIG_FPE_FASTFPE is not set
217# CONFIG_VFP is not set
218
219#
220# Userspace binary formats
221#
222CONFIG_BINFMT_ELF=y
223# CONFIG_BINFMT_AOUT is not set
224# CONFIG_BINFMT_MISC is not set
225# CONFIG_ARTHUR is not set
226
227#
228# Power management options
229#
230# CONFIG_PM is not set
231# CONFIG_APM is not set
232
233#
234# Networking
235#
236CONFIG_NET=y
237
238#
239# Networking options
240#
241# CONFIG_NETDEBUG is not set
242CONFIG_PACKET=y
243# CONFIG_PACKET_MMAP is not set
244CONFIG_UNIX=y
245CONFIG_XFRM=y
246# CONFIG_XFRM_USER is not set
247# CONFIG_XFRM_SUB_POLICY is not set
248# CONFIG_NET_KEY is not set
249CONFIG_INET=y
250# CONFIG_IP_MULTICAST is not set
251# CONFIG_IP_ADVANCED_ROUTER is not set
252CONFIG_IP_FIB_HASH=y
253CONFIG_IP_PNP=y
254# CONFIG_IP_PNP_DHCP is not set
255CONFIG_IP_PNP_BOOTP=y
256# CONFIG_IP_PNP_RARP is not set
257# CONFIG_NET_IPIP is not set
258# CONFIG_NET_IPGRE is not set
259# CONFIG_ARPD is not set
260# CONFIG_SYN_COOKIES is not set
261# CONFIG_INET_AH is not set
262# CONFIG_INET_ESP is not set
263# CONFIG_INET_IPCOMP is not set
264# CONFIG_INET_XFRM_TUNNEL is not set
265# CONFIG_INET_TUNNEL is not set
266CONFIG_INET_XFRM_MODE_TRANSPORT=y
267CONFIG_INET_XFRM_MODE_TUNNEL=y
268CONFIG_INET_XFRM_MODE_BEET=y
269CONFIG_INET_DIAG=y
270CONFIG_INET_TCP_DIAG=y
271# CONFIG_TCP_CONG_ADVANCED is not set
272CONFIG_TCP_CONG_CUBIC=y
273CONFIG_DEFAULT_TCP_CONG="cubic"
274# CONFIG_IPV6 is not set
275# CONFIG_INET6_XFRM_TUNNEL is not set
276# CONFIG_INET6_TUNNEL is not set
277# CONFIG_NETWORK_SECMARK is not set
278# CONFIG_NETFILTER is not set
279
280#
281# DCCP Configuration (EXPERIMENTAL)
282#
283# CONFIG_IP_DCCP is not set
284
285#
286# SCTP Configuration (EXPERIMENTAL)
287#
288# CONFIG_IP_SCTP is not set
289
290#
291# TIPC Configuration (EXPERIMENTAL)
292#
293# CONFIG_TIPC is not set
294# CONFIG_ATM is not set
295# CONFIG_BRIDGE is not set
296# CONFIG_VLAN_8021Q is not set
297# CONFIG_DECNET is not set
298# CONFIG_LLC2 is not set
299# CONFIG_IPX is not set
300# CONFIG_ATALK is not set
301# CONFIG_X25 is not set
302# CONFIG_LAPB is not set
303# CONFIG_ECONET is not set
304# CONFIG_WAN_ROUTER is not set
305
306#
307# QoS and/or fair queueing
308#
309# CONFIG_NET_SCHED is not set
310
311#
312# Network testing
313#
314# CONFIG_NET_PKTGEN is not set
315# CONFIG_HAMRADIO is not set
316# CONFIG_IRDA is not set
317# CONFIG_BT is not set
318# CONFIG_IEEE80211 is not set
319
320#
321# Device Drivers
322#
323
324#
325# Generic Driver Options
326#
327CONFIG_STANDALONE=y
328CONFIG_PREVENT_FIRMWARE_BUILD=y
329# CONFIG_FW_LOADER is not set
330# CONFIG_DEBUG_DRIVER is not set
331# CONFIG_SYS_HYPERVISOR is not set
332
333#
334# Connector - unified userspace <-> kernelspace linker
335#
336# CONFIG_CONNECTOR is not set
337
338#
339# Memory Technology Devices (MTD)
340#
341# CONFIG_MTD is not set
342
343#
344# Parallel port support
345#
346# CONFIG_PARPORT is not set
347
348#
349# Plug and Play support
350#
351
352#
353# Block devices
354#
355# CONFIG_BLK_DEV_COW_COMMON is not set
356# CONFIG_BLK_DEV_LOOP is not set
357# CONFIG_BLK_DEV_NBD is not set
358# CONFIG_BLK_DEV_UB is not set
359CONFIG_BLK_DEV_RAM=y
360CONFIG_BLK_DEV_RAM_COUNT=16
361CONFIG_BLK_DEV_RAM_SIZE=8192
362CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
363CONFIG_BLK_DEV_INITRD=y
364# CONFIG_CDROM_PKTCDVD is not set
365# CONFIG_ATA_OVER_ETH is not set
366
367#
368# SCSI device support
369#
370# CONFIG_RAID_ATTRS is not set
371CONFIG_SCSI=y
372# CONFIG_SCSI_NETLINK is not set
373CONFIG_SCSI_PROC_FS=y
374
375#
376# SCSI support type (disk, tape, CD-ROM)
377#
378CONFIG_BLK_DEV_SD=y
379# CONFIG_CHR_DEV_ST is not set
380# CONFIG_CHR_DEV_OSST is not set
381# CONFIG_BLK_DEV_SR is not set
382# CONFIG_CHR_DEV_SG is not set
383# CONFIG_CHR_DEV_SCH is not set
384
385#
386# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
387#
388CONFIG_SCSI_MULTI_LUN=y
389# CONFIG_SCSI_CONSTANTS is not set
390# CONFIG_SCSI_LOGGING is not set
391
392#
393# SCSI Transports
394#
395# CONFIG_SCSI_SPI_ATTRS is not set
396# CONFIG_SCSI_FC_ATTRS is not set
397# CONFIG_SCSI_ISCSI_ATTRS is not set
398# CONFIG_SCSI_SAS_ATTRS is not set
399# CONFIG_SCSI_SAS_LIBSAS is not set
400
401#
402# SCSI low-level drivers
403#
404# CONFIG_ISCSI_TCP is not set
405# CONFIG_SCSI_DEBUG is not set
406
407#
408# Multi-device support (RAID and LVM)
409#
410# CONFIG_MD is not set
411
412#
413# Fusion MPT device support
414#
415# CONFIG_FUSION is not set
416
417#
418# IEEE 1394 (FireWire) support
419#
420
421#
422# I2O device support
423#
424
425#
426# Network device support
427#
428# CONFIG_NETDEVICES is not set
429# CONFIG_NETPOLL is not set
430# CONFIG_NET_POLL_CONTROLLER is not set
431
432#
433# ISDN subsystem
434#
435# CONFIG_ISDN is not set
436
437#
438# Input device support
439#
440CONFIG_INPUT=y
441# CONFIG_INPUT_FF_MEMLESS is not set
442
443#
444# Userland interfaces
445#
446CONFIG_INPUT_MOUSEDEV=y
447# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
448CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
449CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
450# CONFIG_INPUT_JOYDEV is not set
451# CONFIG_INPUT_TSDEV is not set
452# CONFIG_INPUT_EVDEV is not set
453# CONFIG_INPUT_EVBUG is not set
454
455#
456# Input Device Drivers
457#
458# CONFIG_INPUT_KEYBOARD is not set
459# CONFIG_INPUT_MOUSE is not set
460# CONFIG_INPUT_JOYSTICK is not set
461# CONFIG_INPUT_TOUCHSCREEN is not set
462# CONFIG_INPUT_MISC is not set
463
464#
465# Hardware I/O ports
466#
467# CONFIG_SERIO is not set
468# CONFIG_GAMEPORT is not set
469
470#
471# Character devices
472#
473CONFIG_VT=y
474CONFIG_VT_CONSOLE=y
475CONFIG_HW_CONSOLE=y
476# CONFIG_VT_HW_CONSOLE_BINDING is not set
477# CONFIG_SERIAL_NONSTANDARD is not set
478
479#
480# Serial drivers
481#
482# CONFIG_SERIAL_8250 is not set
483
484#
485# Non-8250 serial port support
486#
487CONFIG_SERIAL_ATMEL=y
488CONFIG_SERIAL_ATMEL_CONSOLE=y
489# CONFIG_SERIAL_ATMEL_TTYAT is not set
490CONFIG_SERIAL_CORE=y
491CONFIG_SERIAL_CORE_CONSOLE=y
492CONFIG_UNIX98_PTYS=y
493CONFIG_LEGACY_PTYS=y
494CONFIG_LEGACY_PTY_COUNT=256
495
496#
497# IPMI
498#
499# CONFIG_IPMI_HANDLER is not set
500
501#
502# Watchdog Cards
503#
504CONFIG_WATCHDOG=y
505CONFIG_WATCHDOG_NOWAYOUT=y
506
507#
508# Watchdog Device Drivers
509#
510# CONFIG_SOFT_WATCHDOG is not set
511
512#
513# USB-based Watchdog Cards
514#
515# CONFIG_USBPCWATCHDOG is not set
516CONFIG_HW_RANDOM=y
517# CONFIG_NVRAM is not set
518# CONFIG_DTLK is not set
519# CONFIG_R3964 is not set
520
521#
522# Ftape, the floppy tape device driver
523#
524# CONFIG_RAW_DRIVER is not set
525
526#
527# TPM devices
528#
529# CONFIG_TCG_TPM is not set
530
531#
532# I2C support
533#
534# CONFIG_I2C is not set
535
536#
537# SPI support
538#
539# CONFIG_SPI is not set
540# CONFIG_SPI_MASTER is not set
541
542#
543# Dallas's 1-wire bus
544#
545# CONFIG_W1 is not set
546
547#
548# Hardware Monitoring support
549#
550# CONFIG_HWMON is not set
551# CONFIG_HWMON_VID is not set
552
553#
554# Misc devices
555#
556# CONFIG_TIFM_CORE is not set
557
558#
559# LED devices
560#
561# CONFIG_NEW_LEDS is not set
562
563#
564# LED drivers
565#
566
567#
568# LED Triggers
569#
570
571#
572# Multimedia devices
573#
574# CONFIG_VIDEO_DEV is not set
575
576#
577# Digital Video Broadcasting Devices
578#
579# CONFIG_DVB is not set
580# CONFIG_USB_DABUSB is not set
581
582#
583# Graphics support
584#
585# CONFIG_FIRMWARE_EDID is not set
586# CONFIG_FB is not set
587
588#
589# Console display driver support
590#
591# CONFIG_VGA_CONSOLE is not set
592CONFIG_DUMMY_CONSOLE=y
593# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
594
595#
596# Sound
597#
598# CONFIG_SOUND is not set
599
600#
601# USB support
602#
603CONFIG_USB_ARCH_HAS_HCD=y
604CONFIG_USB_ARCH_HAS_OHCI=y
605# CONFIG_USB_ARCH_HAS_EHCI is not set
606CONFIG_USB=y
607# CONFIG_USB_DEBUG is not set
608
609#
610# Miscellaneous USB options
611#
612CONFIG_USB_DEVICEFS=y
613# CONFIG_USB_BANDWIDTH is not set
614# CONFIG_USB_DYNAMIC_MINORS is not set
615# CONFIG_USB_OTG is not set
616
617#
618# USB Host Controller Drivers
619#
620# CONFIG_USB_ISP116X_HCD is not set
621CONFIG_USB_OHCI_HCD=y
622# CONFIG_USB_OHCI_BIG_ENDIAN is not set
623CONFIG_USB_OHCI_LITTLE_ENDIAN=y
624# CONFIG_USB_SL811_HCD is not set
625
626#
627# USB Device Class drivers
628#
629# CONFIG_USB_ACM is not set
630# CONFIG_USB_PRINTER is not set
631
632#
633# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
634#
635
636#
637# may also be needed; see USB_STORAGE Help for more information
638#
639CONFIG_USB_STORAGE=y
640CONFIG_USB_STORAGE_DEBUG=y
641# CONFIG_USB_STORAGE_DATAFAB is not set
642# CONFIG_USB_STORAGE_FREECOM is not set
643# CONFIG_USB_STORAGE_DPCM is not set
644# CONFIG_USB_STORAGE_USBAT is not set
645# CONFIG_USB_STORAGE_SDDR09 is not set
646# CONFIG_USB_STORAGE_SDDR55 is not set
647# CONFIG_USB_STORAGE_JUMPSHOT is not set
648# CONFIG_USB_STORAGE_ALAUDA is not set
649# CONFIG_USB_STORAGE_KARMA is not set
650# CONFIG_USB_LIBUSUAL is not set
651
652#
653# USB Input Devices
654#
655# CONFIG_USB_HID is not set
656
657#
658# USB HID Boot Protocol drivers
659#
660# CONFIG_USB_KBD is not set
661# CONFIG_USB_MOUSE is not set
662# CONFIG_USB_AIPTEK is not set
663# CONFIG_USB_WACOM is not set
664# CONFIG_USB_ACECAD is not set
665# CONFIG_USB_KBTAB is not set
666# CONFIG_USB_POWERMATE is not set
667# CONFIG_USB_TOUCHSCREEN is not set
668# CONFIG_USB_YEALINK is not set
669# CONFIG_USB_XPAD is not set
670# CONFIG_USB_ATI_REMOTE is not set
671# CONFIG_USB_ATI_REMOTE2 is not set
672# CONFIG_USB_KEYSPAN_REMOTE is not set
673# CONFIG_USB_APPLETOUCH is not set
674
675#
676# USB Imaging devices
677#
678# CONFIG_USB_MDC800 is not set
679# CONFIG_USB_MICROTEK is not set
680
681#
682# USB Network Adapters
683#
684# CONFIG_USB_CATC is not set
685# CONFIG_USB_KAWETH is not set
686# CONFIG_USB_PEGASUS is not set
687# CONFIG_USB_RTL8150 is not set
688# CONFIG_USB_USBNET_MII is not set
689# CONFIG_USB_USBNET is not set
690CONFIG_USB_MON=y
691
692#
693# USB port drivers
694#
695
696#
697# USB Serial Converter support
698#
699# CONFIG_USB_SERIAL is not set
700
701#
702# USB Miscellaneous drivers
703#
704# CONFIG_USB_EMI62 is not set
705# CONFIG_USB_EMI26 is not set
706# CONFIG_USB_ADUTUX is not set
707# CONFIG_USB_AUERSWALD is not set
708# CONFIG_USB_RIO500 is not set
709# CONFIG_USB_LEGOTOWER is not set
710# CONFIG_USB_LCD is not set
711# CONFIG_USB_LED is not set
712# CONFIG_USB_CYPRESS_CY7C63 is not set
713# CONFIG_USB_CYTHERM is not set
714# CONFIG_USB_PHIDGET is not set
715# CONFIG_USB_IDMOUSE is not set
716# CONFIG_USB_FTDI_ELAN is not set
717# CONFIG_USB_APPLEDISPLAY is not set
718# CONFIG_USB_LD is not set
719# CONFIG_USB_TRANCEVIBRATOR is not set
720# CONFIG_USB_TEST is not set
721
722#
723# USB DSL modem support
724#
725
726#
727# USB Gadget Support
728#
729CONFIG_USB_GADGET=y
730# CONFIG_USB_GADGET_DEBUG_FILES is not set
731CONFIG_USB_GADGET_SELECTED=y
732# CONFIG_USB_GADGET_NET2280 is not set
733# CONFIG_USB_GADGET_PXA2XX is not set
734# CONFIG_USB_GADGET_GOKU is not set
735# CONFIG_USB_GADGET_LH7A40X is not set
736# CONFIG_USB_GADGET_OMAP is not set
737CONFIG_USB_GADGET_AT91=y
738CONFIG_USB_AT91=y
739# CONFIG_USB_GADGET_DUMMY_HCD is not set
740# CONFIG_USB_GADGET_DUALSPEED is not set
741CONFIG_USB_ZERO=m
742# CONFIG_USB_ETH is not set
743CONFIG_USB_GADGETFS=m
744CONFIG_USB_FILE_STORAGE=m
745# CONFIG_USB_FILE_STORAGE_TEST is not set
746CONFIG_USB_G_SERIAL=m
747# CONFIG_USB_MIDI_GADGET is not set
748
749#
750# MMC/SD Card support
751#
752# CONFIG_MMC is not set
753
754#
755# Real Time Clock
756#
757CONFIG_RTC_LIB=y
758# CONFIG_RTC_CLASS is not set
759
760#
761# File systems
762#
763CONFIG_EXT2_FS=y
764# CONFIG_EXT2_FS_XATTR is not set
765# CONFIG_EXT2_FS_XIP is not set
766# CONFIG_EXT3_FS is not set
767# CONFIG_EXT4DEV_FS is not set
768# CONFIG_REISERFS_FS is not set
769# CONFIG_JFS_FS is not set
770# CONFIG_FS_POSIX_ACL is not set
771# CONFIG_XFS_FS is not set
772# CONFIG_GFS2_FS is not set
773# CONFIG_OCFS2_FS is not set
774# CONFIG_MINIX_FS is not set
775# CONFIG_ROMFS_FS is not set
776CONFIG_INOTIFY=y
777CONFIG_INOTIFY_USER=y
778# CONFIG_QUOTA is not set
779CONFIG_DNOTIFY=y
780# CONFIG_AUTOFS_FS is not set
781# CONFIG_AUTOFS4_FS is not set
782# CONFIG_FUSE_FS is not set
783
784#
785# CD-ROM/DVD Filesystems
786#
787# CONFIG_ISO9660_FS is not set
788# CONFIG_UDF_FS is not set
789
790#
791# DOS/FAT/NT Filesystems
792#
793CONFIG_FAT_FS=y
794# CONFIG_MSDOS_FS is not set
795CONFIG_VFAT_FS=y
796CONFIG_FAT_DEFAULT_CODEPAGE=437
797CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
798# CONFIG_NTFS_FS is not set
799
800#
801# Pseudo filesystems
802#
803CONFIG_PROC_FS=y
804CONFIG_PROC_SYSCTL=y
805CONFIG_SYSFS=y
806CONFIG_TMPFS=y
807# CONFIG_TMPFS_POSIX_ACL is not set
808# CONFIG_HUGETLB_PAGE is not set
809CONFIG_RAMFS=y
810# CONFIG_CONFIGFS_FS is not set
811
812#
813# Miscellaneous filesystems
814#
815# CONFIG_ADFS_FS is not set
816# CONFIG_AFFS_FS is not set
817# CONFIG_HFS_FS is not set
818# CONFIG_HFSPLUS_FS is not set
819# CONFIG_BEFS_FS is not set
820# CONFIG_BFS_FS is not set
821# CONFIG_EFS_FS is not set
822CONFIG_CRAMFS=y
823# CONFIG_VXFS_FS is not set
824# CONFIG_HPFS_FS is not set
825# CONFIG_QNX4FS_FS is not set
826# CONFIG_SYSV_FS is not set
827# CONFIG_UFS_FS is not set
828
829#
830# Network File Systems
831#
832# CONFIG_NFS_FS is not set
833# CONFIG_NFSD is not set
834# CONFIG_SMB_FS is not set
835# CONFIG_CIFS is not set
836# CONFIG_NCP_FS is not set
837# CONFIG_CODA_FS is not set
838# CONFIG_AFS_FS is not set
839# CONFIG_9P_FS is not set
840
841#
842# Partition Types
843#
844# CONFIG_PARTITION_ADVANCED is not set
845CONFIG_MSDOS_PARTITION=y
846
847#
848# Native Language Support
849#
850CONFIG_NLS=y
851CONFIG_NLS_DEFAULT="iso8859-1"
852CONFIG_NLS_CODEPAGE_437=y
853# CONFIG_NLS_CODEPAGE_737 is not set
854# CONFIG_NLS_CODEPAGE_775 is not set
855CONFIG_NLS_CODEPAGE_850=y
856# CONFIG_NLS_CODEPAGE_852 is not set
857# CONFIG_NLS_CODEPAGE_855 is not set
858# CONFIG_NLS_CODEPAGE_857 is not set
859# CONFIG_NLS_CODEPAGE_860 is not set
860# CONFIG_NLS_CODEPAGE_861 is not set
861# CONFIG_NLS_CODEPAGE_862 is not set
862# CONFIG_NLS_CODEPAGE_863 is not set
863# CONFIG_NLS_CODEPAGE_864 is not set
864# CONFIG_NLS_CODEPAGE_865 is not set
865# CONFIG_NLS_CODEPAGE_866 is not set
866# CONFIG_NLS_CODEPAGE_869 is not set
867# CONFIG_NLS_CODEPAGE_936 is not set
868# CONFIG_NLS_CODEPAGE_950 is not set
869# CONFIG_NLS_CODEPAGE_932 is not set
870# CONFIG_NLS_CODEPAGE_949 is not set
871# CONFIG_NLS_CODEPAGE_874 is not set
872# CONFIG_NLS_ISO8859_8 is not set
873# CONFIG_NLS_CODEPAGE_1250 is not set
874# CONFIG_NLS_CODEPAGE_1251 is not set
875# CONFIG_NLS_ASCII is not set
876CONFIG_NLS_ISO8859_1=y
877# CONFIG_NLS_ISO8859_2 is not set
878# CONFIG_NLS_ISO8859_3 is not set
879# CONFIG_NLS_ISO8859_4 is not set
880# CONFIG_NLS_ISO8859_5 is not set
881# CONFIG_NLS_ISO8859_6 is not set
882# CONFIG_NLS_ISO8859_7 is not set
883# CONFIG_NLS_ISO8859_9 is not set
884# CONFIG_NLS_ISO8859_13 is not set
885# CONFIG_NLS_ISO8859_14 is not set
886# CONFIG_NLS_ISO8859_15 is not set
887# CONFIG_NLS_KOI8_R is not set
888# CONFIG_NLS_KOI8_U is not set
889# CONFIG_NLS_UTF8 is not set
890
891#
892# Profiling support
893#
894# CONFIG_PROFILING is not set
895
896#
897# Kernel hacking
898#
899# CONFIG_PRINTK_TIME is not set
900CONFIG_ENABLE_MUST_CHECK=y
901# CONFIG_MAGIC_SYSRQ is not set
902# CONFIG_UNUSED_SYMBOLS is not set
903CONFIG_DEBUG_KERNEL=y
904CONFIG_LOG_BUF_SHIFT=14
905CONFIG_DETECT_SOFTLOCKUP=y
906# CONFIG_SCHEDSTATS is not set
907# CONFIG_DEBUG_SLAB is not set
908# CONFIG_DEBUG_RT_MUTEXES is not set
909# CONFIG_RT_MUTEX_TESTER is not set
910# CONFIG_DEBUG_SPINLOCK is not set
911# CONFIG_DEBUG_MUTEXES is not set
912# CONFIG_DEBUG_RWSEMS is not set
913# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
914# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
915# CONFIG_DEBUG_KOBJECT is not set
916CONFIG_DEBUG_BUGVERBOSE=y
917# CONFIG_DEBUG_INFO is not set
918# CONFIG_DEBUG_FS is not set
919# CONFIG_DEBUG_VM is not set
920# CONFIG_DEBUG_LIST is not set
921CONFIG_FRAME_POINTER=y
922CONFIG_FORCED_INLINING=y
923# CONFIG_HEADERS_CHECK is not set
924# CONFIG_RCU_TORTURE_TEST is not set
925CONFIG_DEBUG_USER=y
926# CONFIG_DEBUG_WAITQ is not set
927# CONFIG_DEBUG_ERRORS is not set
928CONFIG_DEBUG_LL=y
929# CONFIG_DEBUG_ICEDCC is not set
930
931#
932# Security options
933#
934# CONFIG_KEYS is not set
935# CONFIG_SECURITY is not set
936
937#
938# Cryptographic options
939#
940# CONFIG_CRYPTO is not set
941
942#
943# Library routines
944#
945# CONFIG_CRC_CCITT is not set
946# CONFIG_CRC16 is not set
947CONFIG_CRC32=y
948# CONFIG_LIBCRC32C is not set
949CONFIG_ZLIB_INFLATE=y
950CONFIG_PLIST=y
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig
new file mode 100644
index 000000000000..784ad7c0186d
--- /dev/null
+++ b/arch/arm/configs/at91sam9261ek_defconfig
@@ -0,0 +1,1106 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.19-rc6
4# Fri Nov 17 18:00:38 2006
5#
6CONFIG_ARM=y
7# CONFIG_GENERIC_TIME is not set
8CONFIG_MMU=y
9CONFIG_GENERIC_HARDIRQS=y
10CONFIG_TRACE_IRQFLAGS_SUPPORT=y
11CONFIG_HARDIRQS_SW_RESEND=y
12CONFIG_GENERIC_IRQ_PROBE=y
13CONFIG_RWSEM_GENERIC_SPINLOCK=y
14CONFIG_GENERIC_HWEIGHT=y
15CONFIG_GENERIC_CALIBRATE_DELAY=y
16CONFIG_VECTORS_BASE=0xffff0000
17CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
18
19#
20# Code maturity level options
21#
22CONFIG_EXPERIMENTAL=y
23CONFIG_BROKEN_ON_SMP=y
24CONFIG_INIT_ENV_ARG_LIMIT=32
25
26#
27# General setup
28#
29CONFIG_LOCALVERSION=""
30# CONFIG_LOCALVERSION_AUTO is not set
31# CONFIG_SWAP is not set
32CONFIG_SYSVIPC=y
33# CONFIG_IPC_NS is not set
34# CONFIG_POSIX_MQUEUE is not set
35# CONFIG_BSD_PROCESS_ACCT is not set
36# CONFIG_TASKSTATS is not set
37# CONFIG_UTS_NS is not set
38# CONFIG_AUDIT is not set
39# CONFIG_IKCONFIG is not set
40# CONFIG_RELAY is not set
41CONFIG_INITRAMFS_SOURCE=""
42CONFIG_CC_OPTIMIZE_FOR_SIZE=y
43CONFIG_SYSCTL=y
44# CONFIG_EMBEDDED is not set
45CONFIG_UID16=y
46CONFIG_SYSCTL_SYSCALL=y
47CONFIG_KALLSYMS=y
48# CONFIG_KALLSYMS_ALL is not set
49# CONFIG_KALLSYMS_EXTRA_PASS is not set
50CONFIG_HOTPLUG=y
51CONFIG_PRINTK=y
52CONFIG_BUG=y
53CONFIG_ELF_CORE=y
54CONFIG_BASE_FULL=y
55CONFIG_FUTEX=y
56CONFIG_EPOLL=y
57CONFIG_SHMEM=y
58CONFIG_SLAB=y
59CONFIG_VM_EVENT_COUNTERS=y
60CONFIG_RT_MUTEXES=y
61# CONFIG_TINY_SHMEM is not set
62CONFIG_BASE_SMALL=0
63# CONFIG_SLOB is not set
64
65#
66# Loadable module support
67#
68CONFIG_MODULES=y
69CONFIG_MODULE_UNLOAD=y
70# CONFIG_MODULE_FORCE_UNLOAD is not set
71# CONFIG_MODVERSIONS is not set
72# CONFIG_MODULE_SRCVERSION_ALL is not set
73CONFIG_KMOD=y
74
75#
76# Block layer
77#
78CONFIG_BLOCK=y
79# CONFIG_BLK_DEV_IO_TRACE is not set
80
81#
82# IO Schedulers
83#
84CONFIG_IOSCHED_NOOP=y
85CONFIG_IOSCHED_AS=y
86# CONFIG_IOSCHED_DEADLINE is not set
87# CONFIG_IOSCHED_CFQ is not set
88CONFIG_DEFAULT_AS=y
89# CONFIG_DEFAULT_DEADLINE is not set
90# CONFIG_DEFAULT_CFQ is not set
91# CONFIG_DEFAULT_NOOP is not set
92CONFIG_DEFAULT_IOSCHED="anticipatory"
93
94#
95# System Type
96#
97# CONFIG_ARCH_AAEC2000 is not set
98# CONFIG_ARCH_INTEGRATOR is not set
99# CONFIG_ARCH_REALVIEW is not set
100# CONFIG_ARCH_VERSATILE is not set
101CONFIG_ARCH_AT91=y
102# CONFIG_ARCH_CLPS7500 is not set
103# CONFIG_ARCH_CLPS711X is not set
104# CONFIG_ARCH_CO285 is not set
105# CONFIG_ARCH_EBSA110 is not set
106# CONFIG_ARCH_EP93XX is not set
107# CONFIG_ARCH_FOOTBRIDGE is not set
108# CONFIG_ARCH_NETX is not set
109# CONFIG_ARCH_H720X is not set
110# CONFIG_ARCH_IMX is not set
111# CONFIG_ARCH_IOP32X is not set
112# CONFIG_ARCH_IOP33X is not set
113# CONFIG_ARCH_IXP4XX is not set
114# CONFIG_ARCH_IXP2000 is not set
115# CONFIG_ARCH_IXP23XX is not set
116# CONFIG_ARCH_L7200 is not set
117# CONFIG_ARCH_PNX4008 is not set
118# CONFIG_ARCH_PXA is not set
119# CONFIG_ARCH_RPC is not set
120# CONFIG_ARCH_SA1100 is not set
121# CONFIG_ARCH_S3C2410 is not set
122# CONFIG_ARCH_SHARK is not set
123# CONFIG_ARCH_LH7A40X is not set
124# CONFIG_ARCH_OMAP is not set
125
126#
127# Atmel AT91 System-on-Chip
128#
129# CONFIG_ARCH_AT91RM9200 is not set
130# CONFIG_ARCH_AT91SAM9260 is not set
131CONFIG_ARCH_AT91SAM9261=y
132
133#
134# AT91SAM9261 Board Type
135#
136CONFIG_MACH_AT91SAM9261EK=y
137
138#
139# AT91 Board Options
140#
141# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
142
143#
144# AT91 Feature Selections
145#
146# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
147
148#
149# Processor Type
150#
151CONFIG_CPU_32=y
152CONFIG_CPU_ARM926T=y
153CONFIG_CPU_32v5=y
154CONFIG_CPU_ABRT_EV5TJ=y
155CONFIG_CPU_CACHE_VIVT=y
156CONFIG_CPU_COPY_V4WB=y
157CONFIG_CPU_TLB_V4WBI=y
158CONFIG_CPU_CP15=y
159CONFIG_CPU_CP15_MMU=y
160
161#
162# Processor Features
163#
164# CONFIG_ARM_THUMB is not set
165# CONFIG_CPU_ICACHE_DISABLE is not set
166# CONFIG_CPU_DCACHE_DISABLE is not set
167# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
168# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
169
170#
171# Bus support
172#
173
174#
175# PCCARD (PCMCIA/CardBus) support
176#
177# CONFIG_PCCARD is not set
178
179#
180# Kernel Features
181#
182# CONFIG_PREEMPT is not set
183# CONFIG_NO_IDLE_HZ is not set
184CONFIG_HZ=100
185# CONFIG_AEABI is not set
186# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
187CONFIG_SELECT_MEMORY_MODEL=y
188CONFIG_FLATMEM_MANUAL=y
189# CONFIG_DISCONTIGMEM_MANUAL is not set
190# CONFIG_SPARSEMEM_MANUAL is not set
191CONFIG_FLATMEM=y
192CONFIG_FLAT_NODE_MEM_MAP=y
193# CONFIG_SPARSEMEM_STATIC is not set
194CONFIG_SPLIT_PTLOCK_CPUS=4096
195# CONFIG_RESOURCES_64BIT is not set
196# CONFIG_LEDS is not set
197CONFIG_ALIGNMENT_TRAP=y
198
199#
200# Boot options
201#
202CONFIG_ZBOOT_ROM_TEXT=0x0
203CONFIG_ZBOOT_ROM_BSS=0x0
204CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
205# CONFIG_XIP_KERNEL is not set
206
207#
208# Floating point emulation
209#
210
211#
212# At least one emulation must be selected
213#
214CONFIG_FPE_NWFPE=y
215# CONFIG_FPE_NWFPE_XP is not set
216# CONFIG_FPE_FASTFPE is not set
217# CONFIG_VFP is not set
218
219#
220# Userspace binary formats
221#
222CONFIG_BINFMT_ELF=y
223# CONFIG_BINFMT_AOUT is not set
224# CONFIG_BINFMT_MISC is not set
225# CONFIG_ARTHUR is not set
226
227#
228# Power management options
229#
230# CONFIG_PM is not set
231# CONFIG_APM is not set
232
233#
234# Networking
235#
236CONFIG_NET=y
237
238#
239# Networking options
240#
241# CONFIG_NETDEBUG is not set
242CONFIG_PACKET=y
243# CONFIG_PACKET_MMAP is not set
244CONFIG_UNIX=y
245CONFIG_XFRM=y
246# CONFIG_XFRM_USER is not set
247# CONFIG_XFRM_SUB_POLICY is not set
248# CONFIG_NET_KEY is not set
249CONFIG_INET=y
250# CONFIG_IP_MULTICAST is not set
251# CONFIG_IP_ADVANCED_ROUTER is not set
252CONFIG_IP_FIB_HASH=y
253CONFIG_IP_PNP=y
254# CONFIG_IP_PNP_DHCP is not set
255CONFIG_IP_PNP_BOOTP=y
256# CONFIG_IP_PNP_RARP is not set
257# CONFIG_NET_IPIP is not set
258# CONFIG_NET_IPGRE is not set
259# CONFIG_ARPD is not set
260# CONFIG_SYN_COOKIES is not set
261# CONFIG_INET_AH is not set
262# CONFIG_INET_ESP is not set
263# CONFIG_INET_IPCOMP is not set
264# CONFIG_INET_XFRM_TUNNEL is not set
265# CONFIG_INET_TUNNEL is not set
266CONFIG_INET_XFRM_MODE_TRANSPORT=y
267CONFIG_INET_XFRM_MODE_TUNNEL=y
268CONFIG_INET_XFRM_MODE_BEET=y
269CONFIG_INET_DIAG=y
270CONFIG_INET_TCP_DIAG=y
271# CONFIG_TCP_CONG_ADVANCED is not set
272CONFIG_TCP_CONG_CUBIC=y
273CONFIG_DEFAULT_TCP_CONG="cubic"
274# CONFIG_IPV6 is not set
275# CONFIG_INET6_XFRM_TUNNEL is not set
276# CONFIG_INET6_TUNNEL is not set
277# CONFIG_NETWORK_SECMARK is not set
278# CONFIG_NETFILTER is not set
279
280#
281# DCCP Configuration (EXPERIMENTAL)
282#
283# CONFIG_IP_DCCP is not set
284
285#
286# SCTP Configuration (EXPERIMENTAL)
287#
288# CONFIG_IP_SCTP is not set
289
290#
291# TIPC Configuration (EXPERIMENTAL)
292#
293# CONFIG_TIPC is not set
294# CONFIG_ATM is not set
295# CONFIG_BRIDGE is not set
296# CONFIG_VLAN_8021Q is not set
297# CONFIG_DECNET is not set
298# CONFIG_LLC2 is not set
299# CONFIG_IPX is not set
300# CONFIG_ATALK is not set
301# CONFIG_X25 is not set
302# CONFIG_LAPB is not set
303# CONFIG_ECONET is not set
304# CONFIG_WAN_ROUTER is not set
305
306#
307# QoS and/or fair queueing
308#
309# CONFIG_NET_SCHED is not set
310
311#
312# Network testing
313#
314# CONFIG_NET_PKTGEN is not set
315# CONFIG_HAMRADIO is not set
316# CONFIG_IRDA is not set
317# CONFIG_BT is not set
318# CONFIG_IEEE80211 is not set
319
320#
321# Device Drivers
322#
323
324#
325# Generic Driver Options
326#
327CONFIG_STANDALONE=y
328CONFIG_PREVENT_FIRMWARE_BUILD=y
329# CONFIG_FW_LOADER is not set
330# CONFIG_DEBUG_DRIVER is not set
331# CONFIG_SYS_HYPERVISOR is not set
332
333#
334# Connector - unified userspace <-> kernelspace linker
335#
336# CONFIG_CONNECTOR is not set
337
338#
339# Memory Technology Devices (MTD)
340#
341CONFIG_MTD=y
342# CONFIG_MTD_DEBUG is not set
343# CONFIG_MTD_CONCAT is not set
344CONFIG_MTD_PARTITIONS=y
345# CONFIG_MTD_REDBOOT_PARTS is not set
346CONFIG_MTD_CMDLINE_PARTS=y
347# CONFIG_MTD_AFS_PARTS is not set
348
349#
350# User Modules And Translation Layers
351#
352# CONFIG_MTD_CHAR is not set
353CONFIG_MTD_BLOCK=y
354# CONFIG_FTL is not set
355# CONFIG_NFTL is not set
356# CONFIG_INFTL is not set
357# CONFIG_RFD_FTL is not set
358# CONFIG_SSFDC is not set
359
360#
361# RAM/ROM/Flash chip drivers
362#
363# CONFIG_MTD_CFI is not set
364# CONFIG_MTD_JEDECPROBE is not set
365CONFIG_MTD_MAP_BANK_WIDTH_1=y
366CONFIG_MTD_MAP_BANK_WIDTH_2=y
367CONFIG_MTD_MAP_BANK_WIDTH_4=y
368# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
369# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
370# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
371CONFIG_MTD_CFI_I1=y
372CONFIG_MTD_CFI_I2=y
373# CONFIG_MTD_CFI_I4 is not set
374# CONFIG_MTD_CFI_I8 is not set
375# CONFIG_MTD_RAM is not set
376# CONFIG_MTD_ROM is not set
377# CONFIG_MTD_ABSENT is not set
378# CONFIG_MTD_OBSOLETE_CHIPS is not set
379
380#
381# Mapping drivers for chip access
382#
383# CONFIG_MTD_COMPLEX_MAPPINGS is not set
384# CONFIG_MTD_PLATRAM is not set
385
386#
387# Self-contained MTD device drivers
388#
389# CONFIG_MTD_SLRAM is not set
390# CONFIG_MTD_PHRAM is not set
391# CONFIG_MTD_MTDRAM is not set
392# CONFIG_MTD_BLOCK2MTD is not set
393
394#
395# Disk-On-Chip Device Drivers
396#
397# CONFIG_MTD_DOC2000 is not set
398# CONFIG_MTD_DOC2001 is not set
399# CONFIG_MTD_DOC2001PLUS is not set
400
401#
402# NAND Flash Device Drivers
403#
404CONFIG_MTD_NAND=y
405# CONFIG_MTD_NAND_VERIFY_WRITE is not set
406# CONFIG_MTD_NAND_ECC_SMC is not set
407CONFIG_MTD_NAND_IDS=y
408# CONFIG_MTD_NAND_DISKONCHIP is not set
409CONFIG_MTD_NAND_AT91=y
410# CONFIG_MTD_NAND_NANDSIM is not set
411
412#
413# OneNAND Flash Device Drivers
414#
415# CONFIG_MTD_ONENAND is not set
416
417#
418# Parallel port support
419#
420# CONFIG_PARPORT is not set
421
422#
423# Plug and Play support
424#
425
426#
427# Block devices
428#
429# CONFIG_BLK_DEV_COW_COMMON is not set
430# CONFIG_BLK_DEV_LOOP is not set
431# CONFIG_BLK_DEV_NBD is not set
432# CONFIG_BLK_DEV_UB is not set
433CONFIG_BLK_DEV_RAM=y
434CONFIG_BLK_DEV_RAM_COUNT=16
435CONFIG_BLK_DEV_RAM_SIZE=8192
436CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
437CONFIG_BLK_DEV_INITRD=y
438# CONFIG_CDROM_PKTCDVD is not set
439# CONFIG_ATA_OVER_ETH is not set
440
441#
442# SCSI device support
443#
444# CONFIG_RAID_ATTRS is not set
445CONFIG_SCSI=y
446# CONFIG_SCSI_NETLINK is not set
447CONFIG_SCSI_PROC_FS=y
448
449#
450# SCSI support type (disk, tape, CD-ROM)
451#
452CONFIG_BLK_DEV_SD=y
453# CONFIG_CHR_DEV_ST is not set
454# CONFIG_CHR_DEV_OSST is not set
455# CONFIG_BLK_DEV_SR is not set
456# CONFIG_CHR_DEV_SG is not set
457# CONFIG_CHR_DEV_SCH is not set
458
459#
460# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
461#
462CONFIG_SCSI_MULTI_LUN=y
463# CONFIG_SCSI_CONSTANTS is not set
464# CONFIG_SCSI_LOGGING is not set
465
466#
467# SCSI Transports
468#
469# CONFIG_SCSI_SPI_ATTRS is not set
470# CONFIG_SCSI_FC_ATTRS is not set
471# CONFIG_SCSI_ISCSI_ATTRS is not set
472# CONFIG_SCSI_SAS_ATTRS is not set
473# CONFIG_SCSI_SAS_LIBSAS is not set
474
475#
476# SCSI low-level drivers
477#
478# CONFIG_ISCSI_TCP is not set
479# CONFIG_SCSI_DEBUG is not set
480
481#
482# Multi-device support (RAID and LVM)
483#
484# CONFIG_MD is not set
485
486#
487# Fusion MPT device support
488#
489# CONFIG_FUSION is not set
490
491#
492# IEEE 1394 (FireWire) support
493#
494
495#
496# I2O device support
497#
498
499#
500# Network device support
501#
502CONFIG_NETDEVICES=y
503# CONFIG_DUMMY is not set
504# CONFIG_BONDING is not set
505# CONFIG_EQUALIZER is not set
506# CONFIG_TUN is not set
507
508#
509# PHY device support
510#
511# CONFIG_PHYLIB is not set
512
513#
514# Ethernet (10 or 100Mbit)
515#
516CONFIG_NET_ETHERNET=y
517CONFIG_MII=y
518# CONFIG_SMC91X is not set
519CONFIG_DM9000=y
520
521#
522# Ethernet (1000 Mbit)
523#
524
525#
526# Ethernet (10000 Mbit)
527#
528
529#
530# Token Ring devices
531#
532
533#
534# Wireless LAN (non-hamradio)
535#
536# CONFIG_NET_RADIO is not set
537
538#
539# Wan interfaces
540#
541# CONFIG_WAN is not set
542# CONFIG_PPP is not set
543# CONFIG_SLIP is not set
544# CONFIG_SHAPER is not set
545# CONFIG_NETCONSOLE is not set
546# CONFIG_NETPOLL is not set
547# CONFIG_NET_POLL_CONTROLLER is not set
548
549#
550# ISDN subsystem
551#
552# CONFIG_ISDN is not set
553
554#
555# Input device support
556#
557CONFIG_INPUT=y
558# CONFIG_INPUT_FF_MEMLESS is not set
559
560#
561# Userland interfaces
562#
563CONFIG_INPUT_MOUSEDEV=y
564# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
565CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
566CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
567# CONFIG_INPUT_JOYDEV is not set
568# CONFIG_INPUT_TSDEV is not set
569# CONFIG_INPUT_EVDEV is not set
570# CONFIG_INPUT_EVBUG is not set
571
572#
573# Input Device Drivers
574#
575# CONFIG_INPUT_KEYBOARD is not set
576# CONFIG_INPUT_MOUSE is not set
577# CONFIG_INPUT_JOYSTICK is not set
578# CONFIG_INPUT_TOUCHSCREEN is not set
579# CONFIG_INPUT_MISC is not set
580
581#
582# Hardware I/O ports
583#
584# CONFIG_SERIO is not set
585# CONFIG_GAMEPORT is not set
586
587#
588# Character devices
589#
590CONFIG_VT=y
591CONFIG_VT_CONSOLE=y
592CONFIG_HW_CONSOLE=y
593# CONFIG_VT_HW_CONSOLE_BINDING is not set
594# CONFIG_SERIAL_NONSTANDARD is not set
595
596#
597# Serial drivers
598#
599# CONFIG_SERIAL_8250 is not set
600
601#
602# Non-8250 serial port support
603#
604CONFIG_SERIAL_ATMEL=y
605CONFIG_SERIAL_ATMEL_CONSOLE=y
606# CONFIG_SERIAL_ATMEL_TTYAT is not set
607CONFIG_SERIAL_CORE=y
608CONFIG_SERIAL_CORE_CONSOLE=y
609CONFIG_UNIX98_PTYS=y
610CONFIG_LEGACY_PTYS=y
611CONFIG_LEGACY_PTY_COUNT=256
612
613#
614# IPMI
615#
616# CONFIG_IPMI_HANDLER is not set
617
618#
619# Watchdog Cards
620#
621CONFIG_WATCHDOG=y
622CONFIG_WATCHDOG_NOWAYOUT=y
623
624#
625# Watchdog Device Drivers
626#
627# CONFIG_SOFT_WATCHDOG is not set
628
629#
630# USB-based Watchdog Cards
631#
632# CONFIG_USBPCWATCHDOG is not set
633CONFIG_HW_RANDOM=y
634# CONFIG_NVRAM is not set
635# CONFIG_DTLK is not set
636# CONFIG_R3964 is not set
637
638#
639# Ftape, the floppy tape device driver
640#
641# CONFIG_RAW_DRIVER is not set
642
643#
644# TPM devices
645#
646# CONFIG_TCG_TPM is not set
647
648#
649# I2C support
650#
651CONFIG_I2C=y
652CONFIG_I2C_CHARDEV=y
653
654#
655# I2C Algorithms
656#
657# CONFIG_I2C_ALGOBIT is not set
658# CONFIG_I2C_ALGOPCF is not set
659# CONFIG_I2C_ALGOPCA is not set
660
661#
662# I2C Hardware Bus support
663#
664CONFIG_I2C_AT91=y
665# CONFIG_I2C_OCORES is not set
666# CONFIG_I2C_PARPORT_LIGHT is not set
667# CONFIG_I2C_STUB is not set
668# CONFIG_I2C_PCA is not set
669# CONFIG_I2C_PCA_ISA is not set
670
671#
672# Miscellaneous I2C Chip support
673#
674# CONFIG_SENSORS_DS1337 is not set
675# CONFIG_SENSORS_DS1374 is not set
676# CONFIG_SENSORS_EEPROM is not set
677# CONFIG_SENSORS_PCF8574 is not set
678# CONFIG_SENSORS_PCA9539 is not set
679# CONFIG_SENSORS_PCF8591 is not set
680# CONFIG_SENSORS_MAX6875 is not set
681# CONFIG_I2C_DEBUG_CORE is not set
682# CONFIG_I2C_DEBUG_ALGO is not set
683# CONFIG_I2C_DEBUG_BUS is not set
684# CONFIG_I2C_DEBUG_CHIP is not set
685
686#
687# SPI support
688#
689# CONFIG_SPI is not set
690# CONFIG_SPI_MASTER is not set
691
692#
693# Dallas's 1-wire bus
694#
695# CONFIG_W1 is not set
696
697#
698# Hardware Monitoring support
699#
700# CONFIG_HWMON is not set
701# CONFIG_HWMON_VID is not set
702
703#
704# Misc devices
705#
706# CONFIG_TIFM_CORE is not set
707
708#
709# LED devices
710#
711# CONFIG_NEW_LEDS is not set
712
713#
714# LED drivers
715#
716
717#
718# LED Triggers
719#
720
721#
722# Multimedia devices
723#
724# CONFIG_VIDEO_DEV is not set
725
726#
727# Digital Video Broadcasting Devices
728#
729# CONFIG_DVB is not set
730# CONFIG_USB_DABUSB is not set
731
732#
733# Graphics support
734#
735# CONFIG_FIRMWARE_EDID is not set
736# CONFIG_FB is not set
737
738#
739# Console display driver support
740#
741# CONFIG_VGA_CONSOLE is not set
742CONFIG_DUMMY_CONSOLE=y
743# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
744
745#
746# Sound
747#
748# CONFIG_SOUND is not set
749
750#
751# USB support
752#
753CONFIG_USB_ARCH_HAS_HCD=y
754CONFIG_USB_ARCH_HAS_OHCI=y
755# CONFIG_USB_ARCH_HAS_EHCI is not set
756CONFIG_USB=y
757# CONFIG_USB_DEBUG is not set
758
759#
760# Miscellaneous USB options
761#
762CONFIG_USB_DEVICEFS=y
763# CONFIG_USB_BANDWIDTH is not set
764# CONFIG_USB_DYNAMIC_MINORS is not set
765# CONFIG_USB_OTG is not set
766
767#
768# USB Host Controller Drivers
769#
770# CONFIG_USB_ISP116X_HCD is not set
771CONFIG_USB_OHCI_HCD=y
772# CONFIG_USB_OHCI_BIG_ENDIAN is not set
773CONFIG_USB_OHCI_LITTLE_ENDIAN=y
774# CONFIG_USB_SL811_HCD is not set
775
776#
777# USB Device Class drivers
778#
779# CONFIG_USB_ACM is not set
780# CONFIG_USB_PRINTER is not set
781
782#
783# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
784#
785
786#
787# may also be needed; see USB_STORAGE Help for more information
788#
789CONFIG_USB_STORAGE=y
790CONFIG_USB_STORAGE_DEBUG=y
791# CONFIG_USB_STORAGE_DATAFAB is not set
792# CONFIG_USB_STORAGE_FREECOM is not set
793# CONFIG_USB_STORAGE_DPCM is not set
794# CONFIG_USB_STORAGE_USBAT is not set
795# CONFIG_USB_STORAGE_SDDR09 is not set
796# CONFIG_USB_STORAGE_SDDR55 is not set
797# CONFIG_USB_STORAGE_JUMPSHOT is not set
798# CONFIG_USB_STORAGE_ALAUDA is not set
799# CONFIG_USB_STORAGE_KARMA is not set
800# CONFIG_USB_LIBUSUAL is not set
801
802#
803# USB Input Devices
804#
805# CONFIG_USB_HID is not set
806
807#
808# USB HID Boot Protocol drivers
809#
810# CONFIG_USB_KBD is not set
811# CONFIG_USB_MOUSE is not set
812# CONFIG_USB_AIPTEK is not set
813# CONFIG_USB_WACOM is not set
814# CONFIG_USB_ACECAD is not set
815# CONFIG_USB_KBTAB is not set
816# CONFIG_USB_POWERMATE is not set
817# CONFIG_USB_TOUCHSCREEN is not set
818# CONFIG_USB_YEALINK is not set
819# CONFIG_USB_XPAD is not set
820# CONFIG_USB_ATI_REMOTE is not set
821# CONFIG_USB_ATI_REMOTE2 is not set
822# CONFIG_USB_KEYSPAN_REMOTE is not set
823# CONFIG_USB_APPLETOUCH is not set
824
825#
826# USB Imaging devices
827#
828# CONFIG_USB_MDC800 is not set
829# CONFIG_USB_MICROTEK is not set
830
831#
832# USB Network Adapters
833#
834# CONFIG_USB_CATC is not set
835# CONFIG_USB_KAWETH is not set
836# CONFIG_USB_PEGASUS is not set
837# CONFIG_USB_RTL8150 is not set
838# CONFIG_USB_USBNET_MII is not set
839# CONFIG_USB_USBNET is not set
840CONFIG_USB_MON=y
841
842#
843# USB port drivers
844#
845
846#
847# USB Serial Converter support
848#
849# CONFIG_USB_SERIAL is not set
850
851#
852# USB Miscellaneous drivers
853#
854# CONFIG_USB_EMI62 is not set
855# CONFIG_USB_EMI26 is not set
856# CONFIG_USB_ADUTUX is not set
857# CONFIG_USB_AUERSWALD is not set
858# CONFIG_USB_RIO500 is not set
859# CONFIG_USB_LEGOTOWER is not set
860# CONFIG_USB_LCD is not set
861# CONFIG_USB_LED is not set
862# CONFIG_USB_CYPRESS_CY7C63 is not set
863# CONFIG_USB_CYTHERM is not set
864# CONFIG_USB_PHIDGET is not set
865# CONFIG_USB_IDMOUSE is not set
866# CONFIG_USB_FTDI_ELAN is not set
867# CONFIG_USB_APPLEDISPLAY is not set
868# CONFIG_USB_LD is not set
869# CONFIG_USB_TRANCEVIBRATOR is not set
870# CONFIG_USB_TEST is not set
871
872#
873# USB DSL modem support
874#
875
876#
877# USB Gadget Support
878#
879CONFIG_USB_GADGET=y
880# CONFIG_USB_GADGET_DEBUG_FILES is not set
881CONFIG_USB_GADGET_SELECTED=y
882# CONFIG_USB_GADGET_NET2280 is not set
883# CONFIG_USB_GADGET_PXA2XX is not set
884# CONFIG_USB_GADGET_GOKU is not set
885# CONFIG_USB_GADGET_LH7A40X is not set
886# CONFIG_USB_GADGET_OMAP is not set
887CONFIG_USB_GADGET_AT91=y
888CONFIG_USB_AT91=y
889# CONFIG_USB_GADGET_DUMMY_HCD is not set
890# CONFIG_USB_GADGET_DUALSPEED is not set
891CONFIG_USB_ZERO=m
892# CONFIG_USB_ETH is not set
893CONFIG_USB_GADGETFS=m
894CONFIG_USB_FILE_STORAGE=m
895# CONFIG_USB_FILE_STORAGE_TEST is not set
896CONFIG_USB_G_SERIAL=m
897# CONFIG_USB_MIDI_GADGET is not set
898
899#
900# MMC/SD Card support
901#
902CONFIG_MMC=y
903# CONFIG_MMC_DEBUG is not set
904CONFIG_MMC_BLOCK=y
905CONFIG_MMC_AT91=m
906# CONFIG_MMC_TIFM_SD is not set
907
908#
909# Real Time Clock
910#
911CONFIG_RTC_LIB=y
912# CONFIG_RTC_CLASS is not set
913
914#
915# File systems
916#
917CONFIG_EXT2_FS=y
918# CONFIG_EXT2_FS_XATTR is not set
919# CONFIG_EXT2_FS_XIP is not set
920# CONFIG_EXT3_FS is not set
921# CONFIG_EXT4DEV_FS is not set
922# CONFIG_REISERFS_FS is not set
923# CONFIG_JFS_FS is not set
924# CONFIG_FS_POSIX_ACL is not set
925# CONFIG_XFS_FS is not set
926# CONFIG_GFS2_FS is not set
927# CONFIG_OCFS2_FS is not set
928# CONFIG_MINIX_FS is not set
929# CONFIG_ROMFS_FS is not set
930CONFIG_INOTIFY=y
931CONFIG_INOTIFY_USER=y
932# CONFIG_QUOTA is not set
933CONFIG_DNOTIFY=y
934# CONFIG_AUTOFS_FS is not set
935# CONFIG_AUTOFS4_FS is not set
936# CONFIG_FUSE_FS is not set
937
938#
939# CD-ROM/DVD Filesystems
940#
941# CONFIG_ISO9660_FS is not set
942# CONFIG_UDF_FS is not set
943
944#
945# DOS/FAT/NT Filesystems
946#
947CONFIG_FAT_FS=y
948# CONFIG_MSDOS_FS is not set
949CONFIG_VFAT_FS=y
950CONFIG_FAT_DEFAULT_CODEPAGE=437
951CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
952# CONFIG_NTFS_FS is not set
953
954#
955# Pseudo filesystems
956#
957CONFIG_PROC_FS=y
958CONFIG_PROC_SYSCTL=y
959CONFIG_SYSFS=y
960CONFIG_TMPFS=y
961# CONFIG_TMPFS_POSIX_ACL is not set
962# CONFIG_HUGETLB_PAGE is not set
963CONFIG_RAMFS=y
964# CONFIG_CONFIGFS_FS is not set
965
966#
967# Miscellaneous filesystems
968#
969# CONFIG_ADFS_FS is not set
970# CONFIG_AFFS_FS is not set
971# CONFIG_HFS_FS is not set
972# CONFIG_HFSPLUS_FS is not set
973# CONFIG_BEFS_FS is not set
974# CONFIG_BFS_FS is not set
975# CONFIG_EFS_FS is not set
976# CONFIG_JFFS_FS is not set
977# CONFIG_JFFS2_FS is not set
978CONFIG_CRAMFS=y
979# CONFIG_VXFS_FS is not set
980# CONFIG_HPFS_FS is not set
981# CONFIG_QNX4FS_FS is not set
982# CONFIG_SYSV_FS is not set
983# CONFIG_UFS_FS is not set
984
985#
986# Network File Systems
987#
988# CONFIG_NFS_FS is not set
989# CONFIG_NFSD is not set
990# CONFIG_SMB_FS is not set
991# CONFIG_CIFS is not set
992# CONFIG_NCP_FS is not set
993# CONFIG_CODA_FS is not set
994# CONFIG_AFS_FS is not set
995# CONFIG_9P_FS is not set
996
997#
998# Partition Types
999#
1000# CONFIG_PARTITION_ADVANCED is not set
1001CONFIG_MSDOS_PARTITION=y
1002
1003#
1004# Native Language Support
1005#
1006CONFIG_NLS=y
1007CONFIG_NLS_DEFAULT="iso8859-1"
1008CONFIG_NLS_CODEPAGE_437=y
1009# CONFIG_NLS_CODEPAGE_737 is not set
1010# CONFIG_NLS_CODEPAGE_775 is not set
1011CONFIG_NLS_CODEPAGE_850=y
1012# CONFIG_NLS_CODEPAGE_852 is not set
1013# CONFIG_NLS_CODEPAGE_855 is not set
1014# CONFIG_NLS_CODEPAGE_857 is not set
1015# CONFIG_NLS_CODEPAGE_860 is not set
1016# CONFIG_NLS_CODEPAGE_861 is not set
1017# CONFIG_NLS_CODEPAGE_862 is not set
1018# CONFIG_NLS_CODEPAGE_863 is not set
1019# CONFIG_NLS_CODEPAGE_864 is not set
1020# CONFIG_NLS_CODEPAGE_865 is not set
1021# CONFIG_NLS_CODEPAGE_866 is not set
1022# CONFIG_NLS_CODEPAGE_869 is not set
1023# CONFIG_NLS_CODEPAGE_936 is not set
1024# CONFIG_NLS_CODEPAGE_950 is not set
1025# CONFIG_NLS_CODEPAGE_932 is not set
1026# CONFIG_NLS_CODEPAGE_949 is not set
1027# CONFIG_NLS_CODEPAGE_874 is not set
1028# CONFIG_NLS_ISO8859_8 is not set
1029# CONFIG_NLS_CODEPAGE_1250 is not set
1030# CONFIG_NLS_CODEPAGE_1251 is not set
1031# CONFIG_NLS_ASCII is not set
1032CONFIG_NLS_ISO8859_1=y
1033# CONFIG_NLS_ISO8859_2 is not set
1034# CONFIG_NLS_ISO8859_3 is not set
1035# CONFIG_NLS_ISO8859_4 is not set
1036# CONFIG_NLS_ISO8859_5 is not set
1037# CONFIG_NLS_ISO8859_6 is not set
1038# CONFIG_NLS_ISO8859_7 is not set
1039# CONFIG_NLS_ISO8859_9 is not set
1040# CONFIG_NLS_ISO8859_13 is not set
1041# CONFIG_NLS_ISO8859_14 is not set
1042# CONFIG_NLS_ISO8859_15 is not set
1043# CONFIG_NLS_KOI8_R is not set
1044# CONFIG_NLS_KOI8_U is not set
1045# CONFIG_NLS_UTF8 is not set
1046
1047#
1048# Profiling support
1049#
1050# CONFIG_PROFILING is not set
1051
1052#
1053# Kernel hacking
1054#
1055# CONFIG_PRINTK_TIME is not set
1056CONFIG_ENABLE_MUST_CHECK=y
1057# CONFIG_MAGIC_SYSRQ is not set
1058# CONFIG_UNUSED_SYMBOLS is not set
1059CONFIG_DEBUG_KERNEL=y
1060CONFIG_LOG_BUF_SHIFT=14
1061CONFIG_DETECT_SOFTLOCKUP=y
1062# CONFIG_SCHEDSTATS is not set
1063# CONFIG_DEBUG_SLAB is not set
1064# CONFIG_DEBUG_RT_MUTEXES is not set
1065# CONFIG_RT_MUTEX_TESTER is not set
1066# CONFIG_DEBUG_SPINLOCK is not set
1067# CONFIG_DEBUG_MUTEXES is not set
1068# CONFIG_DEBUG_RWSEMS is not set
1069# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1070# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1071# CONFIG_DEBUG_KOBJECT is not set
1072CONFIG_DEBUG_BUGVERBOSE=y
1073# CONFIG_DEBUG_INFO is not set
1074# CONFIG_DEBUG_FS is not set
1075# CONFIG_DEBUG_VM is not set
1076# CONFIG_DEBUG_LIST is not set
1077CONFIG_FRAME_POINTER=y
1078CONFIG_FORCED_INLINING=y
1079# CONFIG_HEADERS_CHECK is not set
1080# CONFIG_RCU_TORTURE_TEST is not set
1081CONFIG_DEBUG_USER=y
1082# CONFIG_DEBUG_WAITQ is not set
1083# CONFIG_DEBUG_ERRORS is not set
1084CONFIG_DEBUG_LL=y
1085# CONFIG_DEBUG_ICEDCC is not set
1086
1087#
1088# Security options
1089#
1090# CONFIG_KEYS is not set
1091# CONFIG_SECURITY is not set
1092
1093#
1094# Cryptographic options
1095#
1096# CONFIG_CRYPTO is not set
1097
1098#
1099# Library routines
1100#
1101# CONFIG_CRC_CCITT is not set
1102# CONFIG_CRC16 is not set
1103CONFIG_CRC32=y
1104# CONFIG_LIBCRC32C is not set
1105CONFIG_ZLIB_INFLATE=y
1106CONFIG_PLIST=y
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig
index cfe6bd8e81cd..821865f75605 100644
--- a/arch/arm/configs/badge4_defconfig
+++ b/arch/arm/configs/badge4_defconfig
@@ -1216,7 +1216,6 @@ CONFIG_DEBUG_INFO=y
1216# CONFIG_DEBUG_FS is not set 1216# CONFIG_DEBUG_FS is not set
1217CONFIG_FRAME_POINTER=y 1217CONFIG_FRAME_POINTER=y
1218CONFIG_DEBUG_USER=y 1218CONFIG_DEBUG_USER=y
1219# CONFIG_DEBUG_WAITQ is not set
1220CONFIG_DEBUG_ERRORS=y 1219CONFIG_DEBUG_ERRORS=y
1221CONFIG_DEBUG_LL=y 1220CONFIG_DEBUG_LL=y
1222# CONFIG_DEBUG_ICEDCC is not set 1221# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/carmeva_defconfig b/arch/arm/configs/carmeva_defconfig
index d24ae8777c35..d392833b31fb 100644
--- a/arch/arm/configs/carmeva_defconfig
+++ b/arch/arm/configs/carmeva_defconfig
@@ -474,7 +474,7 @@ CONFIG_LEGACY_PTY_COUNT=256
474# CONFIG_WATCHDOG is not set 474# CONFIG_WATCHDOG is not set
475# CONFIG_NVRAM is not set 475# CONFIG_NVRAM is not set
476# CONFIG_RTC is not set 476# CONFIG_RTC is not set
477# CONFIG_AT91_RTC is not set 477# CONFIG_AT91RM9200_RTC is not set
478# CONFIG_DTLK is not set 478# CONFIG_DTLK is not set
479# CONFIG_R3964 is not set 479# CONFIG_R3964 is not set
480 480
diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig
index 09b7acd7f647..ee130b528bd4 100644
--- a/arch/arm/configs/cerfcube_defconfig
+++ b/arch/arm/configs/cerfcube_defconfig
@@ -851,7 +851,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
851# CONFIG_DEBUG_FS is not set 851# CONFIG_DEBUG_FS is not set
852CONFIG_FRAME_POINTER=y 852CONFIG_FRAME_POINTER=y
853CONFIG_DEBUG_USER=y 853CONFIG_DEBUG_USER=y
854# CONFIG_DEBUG_WAITQ is not set
855CONFIG_DEBUG_ERRORS=y 854CONFIG_DEBUG_ERRORS=y
856CONFIG_DEBUG_LL=y 855CONFIG_DEBUG_LL=y
857# CONFIG_DEBUG_ICEDCC is not set 856# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
index a3758913c0bb..970c8c772eb7 100644
--- a/arch/arm/configs/collie_defconfig
+++ b/arch/arm/configs/collie_defconfig
@@ -934,7 +934,6 @@ CONFIG_FRAME_POINTER=y
934CONFIG_FORCED_INLINING=y 934CONFIG_FORCED_INLINING=y
935# CONFIG_RCU_TORTURE_TEST is not set 935# CONFIG_RCU_TORTURE_TEST is not set
936# CONFIG_DEBUG_USER is not set 936# CONFIG_DEBUG_USER is not set
937# CONFIG_DEBUG_WAITQ is not set
938CONFIG_DEBUG_ERRORS=y 937CONFIG_DEBUG_ERRORS=y
939# CONFIG_DEBUG_LL is not set 938# CONFIG_DEBUG_LL is not set
940 939
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index c41c04fa5020..e8980a9bb893 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -1513,7 +1513,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1513CONFIG_FRAME_POINTER=y 1513CONFIG_FRAME_POINTER=y
1514# CONFIG_RCU_TORTURE_TEST is not set 1514# CONFIG_RCU_TORTURE_TEST is not set
1515# CONFIG_DEBUG_USER is not set 1515# CONFIG_DEBUG_USER is not set
1516# CONFIG_DEBUG_WAITQ is not set
1517CONFIG_DEBUG_ERRORS=y 1516CONFIG_DEBUG_ERRORS=y
1518CONFIG_DEBUG_LL=y 1517CONFIG_DEBUG_LL=y
1519# CONFIG_DEBUG_ICEDCC is not set 1518# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/csb337_defconfig b/arch/arm/configs/csb337_defconfig
index 20e68250d835..2cadd51506bb 100644
--- a/arch/arm/configs/csb337_defconfig
+++ b/arch/arm/configs/csb337_defconfig
@@ -1113,7 +1113,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1113CONFIG_FRAME_POINTER=y 1113CONFIG_FRAME_POINTER=y
1114# CONFIG_RCU_TORTURE_TEST is not set 1114# CONFIG_RCU_TORTURE_TEST is not set
1115CONFIG_DEBUG_USER=y 1115CONFIG_DEBUG_USER=y
1116# CONFIG_DEBUG_WAITQ is not set
1117# CONFIG_DEBUG_ERRORS is not set 1116# CONFIG_DEBUG_ERRORS is not set
1118CONFIG_DEBUG_LL=y 1117CONFIG_DEBUG_LL=y
1119# CONFIG_DEBUG_ICEDCC is not set 1118# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/csb637_defconfig b/arch/arm/configs/csb637_defconfig
index df8595ac031f..94908c1df4cf 100644
--- a/arch/arm/configs/csb637_defconfig
+++ b/arch/arm/configs/csb637_defconfig
@@ -623,7 +623,7 @@ CONFIG_AT91RM9200_WATCHDOG=y
623# CONFIG_USBPCWATCHDOG is not set 623# CONFIG_USBPCWATCHDOG is not set
624# CONFIG_NVRAM is not set 624# CONFIG_NVRAM is not set
625CONFIG_RTC=y 625CONFIG_RTC=y
626# CONFIG_AT91_RTC is not set 626# CONFIG_AT91RM9200_RTC is not set
627# CONFIG_DTLK is not set 627# CONFIG_DTLK is not set
628# CONFIG_R3964 is not set 628# CONFIG_R3964 is not set
629 629
@@ -1062,7 +1062,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1062CONFIG_FRAME_POINTER=y 1062CONFIG_FRAME_POINTER=y
1063# CONFIG_RCU_TORTURE_TEST is not set 1063# CONFIG_RCU_TORTURE_TEST is not set
1064CONFIG_DEBUG_USER=y 1064CONFIG_DEBUG_USER=y
1065# CONFIG_DEBUG_WAITQ is not set
1066# CONFIG_DEBUG_ERRORS is not set 1065# CONFIG_DEBUG_ERRORS is not set
1067CONFIG_DEBUG_LL=y 1066CONFIG_DEBUG_LL=y
1068# CONFIG_DEBUG_ICEDCC is not set 1067# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 3b4802a849e4..f8a66b72ad5d 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -125,6 +125,7 @@ CONFIG_CRUNCH=y
125# 125#
126# EP93xx Platforms 126# EP93xx Platforms
127# 127#
128CONFIG_MACH_ADSSPHERE=y
128CONFIG_MACH_EDB9302=y 129CONFIG_MACH_EDB9302=y
129CONFIG_MACH_EDB9312=y 130CONFIG_MACH_EDB9312=y
130CONFIG_MACH_EDB9315=y 131CONFIG_MACH_EDB9315=y
@@ -1134,7 +1135,6 @@ CONFIG_FRAME_POINTER=y
1134CONFIG_FORCED_INLINING=y 1135CONFIG_FORCED_INLINING=y
1135# CONFIG_RCU_TORTURE_TEST is not set 1136# CONFIG_RCU_TORTURE_TEST is not set
1136CONFIG_DEBUG_USER=y 1137CONFIG_DEBUG_USER=y
1137CONFIG_DEBUG_WAITQ=y
1138CONFIG_DEBUG_ERRORS=y 1138CONFIG_DEBUG_ERRORS=y
1139CONFIG_DEBUG_LL=y 1139CONFIG_DEBUG_LL=y
1140# CONFIG_DEBUG_ICEDCC is not set 1140# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/h7202_defconfig b/arch/arm/configs/h7202_defconfig
index 9d62ed16bf57..0e739af52713 100644
--- a/arch/arm/configs/h7202_defconfig
+++ b/arch/arm/configs/h7202_defconfig
@@ -702,7 +702,6 @@ CONFIG_DEBUG_INFO=y
702# CONFIG_DEBUG_FS is not set 702# CONFIG_DEBUG_FS is not set
703CONFIG_FRAME_POINTER=y 703CONFIG_FRAME_POINTER=y
704CONFIG_DEBUG_USER=y 704CONFIG_DEBUG_USER=y
705# CONFIG_DEBUG_WAITQ is not set
706# CONFIG_DEBUG_ERRORS is not set 705# CONFIG_DEBUG_ERRORS is not set
707# CONFIG_DEBUG_LL is not set 706# CONFIG_DEBUG_LL is not set
708 707
diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig
index a45b57582b86..1c8fb89a6730 100644
--- a/arch/arm/configs/hackkit_defconfig
+++ b/arch/arm/configs/hackkit_defconfig
@@ -740,7 +740,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
740# CONFIG_DEBUG_FS is not set 740# CONFIG_DEBUG_FS is not set
741CONFIG_FRAME_POINTER=y 741CONFIG_FRAME_POINTER=y
742CONFIG_DEBUG_USER=y 742CONFIG_DEBUG_USER=y
743CONFIG_DEBUG_WAITQ=y
744CONFIG_DEBUG_ERRORS=y 743CONFIG_DEBUG_ERRORS=y
745CONFIG_DEBUG_LL=y 744CONFIG_DEBUG_LL=y
746# CONFIG_DEBUG_ICEDCC is not set 745# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index 692ab57ba1ca..3ce96e60b409 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -835,7 +835,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
835# CONFIG_DEBUG_FS is not set 835# CONFIG_DEBUG_FS is not set
836CONFIG_FRAME_POINTER=y 836CONFIG_FRAME_POINTER=y
837# CONFIG_DEBUG_USER is not set 837# CONFIG_DEBUG_USER is not set
838# CONFIG_DEBUG_WAITQ is not set
839CONFIG_DEBUG_ERRORS=y 838CONFIG_DEBUG_ERRORS=y
840# CONFIG_DEBUG_LL is not set 839# CONFIG_DEBUG_LL is not set
841 840
diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig
new file mode 100644
index 000000000000..f6e46193fd26
--- /dev/null
+++ b/arch/arm/configs/iop13xx_defconfig
@@ -0,0 +1,1134 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.19
4# Fri Dec 1 10:51:01 2006
5#
6CONFIG_ARM=y
7# CONFIG_GENERIC_TIME is not set
8CONFIG_MMU=y
9CONFIG_GENERIC_HARDIRQS=y
10CONFIG_TRACE_IRQFLAGS_SUPPORT=y
11CONFIG_HARDIRQS_SW_RESEND=y
12CONFIG_GENERIC_IRQ_PROBE=y
13CONFIG_RWSEM_GENERIC_SPINLOCK=y
14CONFIG_GENERIC_HWEIGHT=y
15CONFIG_GENERIC_CALIBRATE_DELAY=y
16CONFIG_VECTORS_BASE=0xffff0000
17CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
18
19#
20# Code maturity level options
21#
22CONFIG_EXPERIMENTAL=y
23CONFIG_BROKEN_ON_SMP=y
24CONFIG_INIT_ENV_ARG_LIMIT=32
25
26#
27# General setup
28#
29CONFIG_LOCALVERSION=""
30# CONFIG_LOCALVERSION_AUTO is not set
31CONFIG_SWAP=y
32CONFIG_SYSVIPC=y
33# CONFIG_IPC_NS is not set
34CONFIG_POSIX_MQUEUE=y
35CONFIG_BSD_PROCESS_ACCT=y
36# CONFIG_BSD_PROCESS_ACCT_V3 is not set
37# CONFIG_TASKSTATS is not set
38# CONFIG_UTS_NS is not set
39# CONFIG_AUDIT is not set
40CONFIG_IKCONFIG=y
41CONFIG_IKCONFIG_PROC=y
42# CONFIG_RELAY is not set
43CONFIG_INITRAMFS_SOURCE=""
44# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
45CONFIG_SYSCTL=y
46# CONFIG_EMBEDDED is not set
47CONFIG_UID16=y
48CONFIG_SYSCTL_SYSCALL=y
49CONFIG_KALLSYMS=y
50# CONFIG_KALLSYMS_EXTRA_PASS is not set
51CONFIG_HOTPLUG=y
52CONFIG_PRINTK=y
53CONFIG_BUG=y
54CONFIG_ELF_CORE=y
55CONFIG_BASE_FULL=y
56CONFIG_FUTEX=y
57CONFIG_EPOLL=y
58CONFIG_SHMEM=y
59CONFIG_SLAB=y
60CONFIG_VM_EVENT_COUNTERS=y
61CONFIG_RT_MUTEXES=y
62# CONFIG_TINY_SHMEM is not set
63CONFIG_BASE_SMALL=0
64# CONFIG_SLOB is not set
65
66#
67# Loadable module support
68#
69CONFIG_MODULES=y
70CONFIG_MODULE_UNLOAD=y
71# CONFIG_MODULE_FORCE_UNLOAD is not set
72CONFIG_MODVERSIONS=y
73# CONFIG_MODULE_SRCVERSION_ALL is not set
74CONFIG_KMOD=y
75
76#
77# Block layer
78#
79CONFIG_BLOCK=y
80# CONFIG_BLK_DEV_IO_TRACE is not set
81
82#
83# IO Schedulers
84#
85CONFIG_IOSCHED_NOOP=y
86# CONFIG_IOSCHED_AS is not set
87CONFIG_IOSCHED_DEADLINE=y
88# CONFIG_IOSCHED_CFQ is not set
89# CONFIG_DEFAULT_AS is not set
90CONFIG_DEFAULT_DEADLINE=y
91# CONFIG_DEFAULT_CFQ is not set
92# CONFIG_DEFAULT_NOOP is not set
93CONFIG_DEFAULT_IOSCHED="deadline"
94
95#
96# System Type
97#
98# CONFIG_ARCH_AAEC2000 is not set
99# CONFIG_ARCH_INTEGRATOR is not set
100# CONFIG_ARCH_REALVIEW is not set
101# CONFIG_ARCH_VERSATILE is not set
102# CONFIG_ARCH_AT91 is not set
103# CONFIG_ARCH_CLPS7500 is not set
104# CONFIG_ARCH_CLPS711X is not set
105# CONFIG_ARCH_CO285 is not set
106# CONFIG_ARCH_EBSA110 is not set
107# CONFIG_ARCH_EP93XX is not set
108# CONFIG_ARCH_FOOTBRIDGE is not set
109# CONFIG_ARCH_NETX is not set
110# CONFIG_ARCH_H720X is not set
111# CONFIG_ARCH_IMX is not set
112# CONFIG_ARCH_IOP32X is not set
113# CONFIG_ARCH_IOP33X is not set
114CONFIG_ARCH_IOP13XX=y
115# CONFIG_ARCH_IXP4XX is not set
116# CONFIG_ARCH_IXP2000 is not set
117# CONFIG_ARCH_IXP23XX is not set
118# CONFIG_ARCH_L7200 is not set
119# CONFIG_ARCH_PNX4008 is not set
120# CONFIG_ARCH_PXA is not set
121# CONFIG_ARCH_RPC is not set
122# CONFIG_ARCH_SA1100 is not set
123# CONFIG_ARCH_S3C2410 is not set
124# CONFIG_ARCH_SHARK is not set
125# CONFIG_ARCH_LH7A40X is not set
126# CONFIG_ARCH_OMAP is not set
127
128#
129# IOP13XX Implementation Options
130#
131
132#
133# IOP13XX Platform Support
134#
135CONFIG_MACH_IQ81340SC=y
136CONFIG_MACH_IQ81340MC=y
137
138#
139# Processor Type
140#
141CONFIG_CPU_32=y
142CONFIG_CPU_XSC3=y
143CONFIG_CPU_32v5=y
144CONFIG_CPU_ABRT_EV5T=y
145CONFIG_CPU_CACHE_VIVT=y
146CONFIG_CPU_TLB_V4WBI=y
147CONFIG_CPU_CP15=y
148CONFIG_CPU_CP15_MMU=y
149CONFIG_IO_36=y
150
151#
152# Processor Features
153#
154CONFIG_ARM_THUMB=y
155# CONFIG_CPU_DCACHE_DISABLE is not set
156# CONFIG_CPU_BPREDICT_DISABLE is not set
157
158#
159# Bus support
160#
161CONFIG_PCI=y
162
163#
164# PCCARD (PCMCIA/CardBus) support
165#
166# CONFIG_PCCARD is not set
167
168#
169# Kernel Features
170#
171# CONFIG_PREEMPT is not set
172# CONFIG_NO_IDLE_HZ is not set
173CONFIG_HZ=100
174# CONFIG_AEABI is not set
175# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
176CONFIG_SELECT_MEMORY_MODEL=y
177CONFIG_FLATMEM_MANUAL=y
178# CONFIG_DISCONTIGMEM_MANUAL is not set
179# CONFIG_SPARSEMEM_MANUAL is not set
180CONFIG_FLATMEM=y
181CONFIG_FLAT_NODE_MEM_MAP=y
182# CONFIG_SPARSEMEM_STATIC is not set
183CONFIG_SPLIT_PTLOCK_CPUS=4096
184# CONFIG_RESOURCES_64BIT is not set
185CONFIG_ALIGNMENT_TRAP=y
186
187#
188# Boot options
189#
190CONFIG_ZBOOT_ROM_TEXT=0x0
191CONFIG_ZBOOT_ROM_BSS=0x0
192CONFIG_CMDLINE="ip=bootp root=nfs console=ttyS0,115200 nfsroot=,tcp,v3,wsize=8192,rsize=8192"
193# CONFIG_XIP_KERNEL is not set
194
195#
196# Floating point emulation
197#
198
199#
200# At least one emulation must be selected
201#
202CONFIG_FPE_NWFPE=y
203# CONFIG_FPE_NWFPE_XP is not set
204# CONFIG_FPE_FASTFPE is not set
205
206#
207# Userspace binary formats
208#
209CONFIG_BINFMT_ELF=y
210CONFIG_BINFMT_AOUT=y
211# CONFIG_BINFMT_MISC is not set
212# CONFIG_ARTHUR is not set
213
214#
215# Power management options
216#
217# CONFIG_PM is not set
218# CONFIG_APM is not set
219
220#
221# Networking
222#
223CONFIG_NET=y
224
225#
226# Networking options
227#
228# CONFIG_NETDEBUG is not set
229CONFIG_PACKET=y
230CONFIG_PACKET_MMAP=y
231CONFIG_UNIX=y
232CONFIG_XFRM=y
233# CONFIG_XFRM_USER is not set
234# CONFIG_XFRM_SUB_POLICY is not set
235CONFIG_NET_KEY=y
236CONFIG_INET=y
237CONFIG_IP_MULTICAST=y
238# CONFIG_IP_ADVANCED_ROUTER is not set
239CONFIG_IP_FIB_HASH=y
240CONFIG_IP_PNP=y
241# CONFIG_IP_PNP_DHCP is not set
242CONFIG_IP_PNP_BOOTP=y
243# CONFIG_IP_PNP_RARP is not set
244# CONFIG_NET_IPIP is not set
245# CONFIG_NET_IPGRE is not set
246# CONFIG_IP_MROUTE is not set
247# CONFIG_ARPD is not set
248# CONFIG_SYN_COOKIES is not set
249# CONFIG_INET_AH is not set
250# CONFIG_INET_ESP is not set
251# CONFIG_INET_IPCOMP is not set
252# CONFIG_INET_XFRM_TUNNEL is not set
253# CONFIG_INET_TUNNEL is not set
254CONFIG_INET_XFRM_MODE_TRANSPORT=y
255CONFIG_INET_XFRM_MODE_TUNNEL=y
256CONFIG_INET_XFRM_MODE_BEET=y
257CONFIG_INET_DIAG=y
258CONFIG_INET_TCP_DIAG=y
259# CONFIG_TCP_CONG_ADVANCED is not set
260CONFIG_TCP_CONG_CUBIC=y
261CONFIG_DEFAULT_TCP_CONG="cubic"
262# CONFIG_IPV6 is not set
263# CONFIG_INET6_XFRM_TUNNEL is not set
264# CONFIG_INET6_TUNNEL is not set
265# CONFIG_NETWORK_SECMARK is not set
266# CONFIG_NETFILTER is not set
267
268#
269# DCCP Configuration (EXPERIMENTAL)
270#
271# CONFIG_IP_DCCP is not set
272
273#
274# SCTP Configuration (EXPERIMENTAL)
275#
276# CONFIG_IP_SCTP is not set
277
278#
279# TIPC Configuration (EXPERIMENTAL)
280#
281# CONFIG_TIPC is not set
282# CONFIG_ATM is not set
283# CONFIG_BRIDGE is not set
284# CONFIG_VLAN_8021Q is not set
285# CONFIG_DECNET is not set
286# CONFIG_LLC2 is not set
287# CONFIG_IPX is not set
288# CONFIG_ATALK is not set
289# CONFIG_X25 is not set
290# CONFIG_LAPB is not set
291# CONFIG_ECONET is not set
292# CONFIG_WAN_ROUTER is not set
293
294#
295# QoS and/or fair queueing
296#
297# CONFIG_NET_SCHED is not set
298
299#
300# Network testing
301#
302# CONFIG_NET_PKTGEN is not set
303# CONFIG_HAMRADIO is not set
304# CONFIG_IRDA is not set
305# CONFIG_BT is not set
306# CONFIG_IEEE80211 is not set
307
308#
309# Device Drivers
310#
311
312#
313# Generic Driver Options
314#
315CONFIG_STANDALONE=y
316CONFIG_PREVENT_FIRMWARE_BUILD=y
317# CONFIG_FW_LOADER is not set
318# CONFIG_SYS_HYPERVISOR is not set
319
320#
321# Connector - unified userspace <-> kernelspace linker
322#
323# CONFIG_CONNECTOR is not set
324
325#
326# Memory Technology Devices (MTD)
327#
328CONFIG_MTD=y
329# CONFIG_MTD_DEBUG is not set
330# CONFIG_MTD_CONCAT is not set
331CONFIG_MTD_PARTITIONS=y
332CONFIG_MTD_REDBOOT_PARTS=y
333CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
334CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
335CONFIG_MTD_REDBOOT_PARTS_READONLY=y
336# CONFIG_MTD_CMDLINE_PARTS is not set
337# CONFIG_MTD_AFS_PARTS is not set
338
339#
340# User Modules And Translation Layers
341#
342# CONFIG_MTD_CHAR is not set
343CONFIG_MTD_BLOCK=y
344# CONFIG_FTL is not set
345# CONFIG_NFTL is not set
346# CONFIG_INFTL is not set
347# CONFIG_RFD_FTL is not set
348# CONFIG_SSFDC is not set
349
350#
351# RAM/ROM/Flash chip drivers
352#
353CONFIG_MTD_CFI=y
354# CONFIG_MTD_JEDECPROBE is not set
355CONFIG_MTD_GEN_PROBE=y
356CONFIG_MTD_CFI_ADV_OPTIONS=y
357CONFIG_MTD_CFI_NOSWAP=y
358# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
359# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
360# CONFIG_MTD_CFI_GEOMETRY is not set
361CONFIG_MTD_MAP_BANK_WIDTH_1=y
362CONFIG_MTD_MAP_BANK_WIDTH_2=y
363CONFIG_MTD_MAP_BANK_WIDTH_4=y
364# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
365# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
366# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
367CONFIG_MTD_CFI_I1=y
368CONFIG_MTD_CFI_I2=y
369# CONFIG_MTD_CFI_I4 is not set
370# CONFIG_MTD_CFI_I8 is not set
371# CONFIG_MTD_OTP is not set
372CONFIG_MTD_CFI_INTELEXT=y
373# CONFIG_MTD_CFI_AMDSTD is not set
374# CONFIG_MTD_CFI_STAA is not set
375CONFIG_MTD_CFI_UTIL=y
376# CONFIG_MTD_RAM is not set
377# CONFIG_MTD_ROM is not set
378# CONFIG_MTD_ABSENT is not set
379# CONFIG_MTD_OBSOLETE_CHIPS is not set
380
381#
382# Mapping drivers for chip access
383#
384# CONFIG_MTD_COMPLEX_MAPPINGS is not set
385CONFIG_MTD_PHYSMAP=y
386CONFIG_MTD_PHYSMAP_START=0xfa000000
387CONFIG_MTD_PHYSMAP_LEN=0x0
388CONFIG_MTD_PHYSMAP_BANKWIDTH=2
389# CONFIG_MTD_ARM_INTEGRATOR is not set
390# CONFIG_MTD_PLATRAM is not set
391
392#
393# Self-contained MTD device drivers
394#
395# CONFIG_MTD_PMC551 is not set
396# CONFIG_MTD_SLRAM is not set
397# CONFIG_MTD_PHRAM is not set
398# CONFIG_MTD_MTDRAM is not set
399# CONFIG_MTD_BLOCK2MTD is not set
400
401#
402# Disk-On-Chip Device Drivers
403#
404# CONFIG_MTD_DOC2000 is not set
405# CONFIG_MTD_DOC2001 is not set
406# CONFIG_MTD_DOC2001PLUS is not set
407
408#
409# NAND Flash Device Drivers
410#
411# CONFIG_MTD_NAND is not set
412
413#
414# OneNAND Flash Device Drivers
415#
416# CONFIG_MTD_ONENAND is not set
417
418#
419# Parallel port support
420#
421# CONFIG_PARPORT is not set
422
423#
424# Plug and Play support
425#
426
427#
428# Block devices
429#
430# CONFIG_BLK_CPQ_DA is not set
431# CONFIG_BLK_CPQ_CISS_DA is not set
432# CONFIG_BLK_DEV_DAC960 is not set
433# CONFIG_BLK_DEV_UMEM is not set
434# CONFIG_BLK_DEV_COW_COMMON is not set
435# CONFIG_BLK_DEV_LOOP is not set
436# CONFIG_BLK_DEV_NBD is not set
437# CONFIG_BLK_DEV_SX8 is not set
438CONFIG_BLK_DEV_RAM=y
439CONFIG_BLK_DEV_RAM_COUNT=2
440CONFIG_BLK_DEV_RAM_SIZE=8192
441CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
442CONFIG_BLK_DEV_INITRD=y
443# CONFIG_CDROM_PKTCDVD is not set
444# CONFIG_ATA_OVER_ETH is not set
445
446#
447# SCSI device support
448#
449# CONFIG_RAID_ATTRS is not set
450CONFIG_SCSI=y
451# CONFIG_SCSI_NETLINK is not set
452CONFIG_SCSI_PROC_FS=y
453
454#
455# SCSI support type (disk, tape, CD-ROM)
456#
457CONFIG_BLK_DEV_SD=y
458# CONFIG_CHR_DEV_ST is not set
459# CONFIG_CHR_DEV_OSST is not set
460# CONFIG_BLK_DEV_SR is not set
461CONFIG_CHR_DEV_SG=y
462# CONFIG_CHR_DEV_SCH is not set
463
464#
465# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
466#
467# CONFIG_SCSI_MULTI_LUN is not set
468CONFIG_SCSI_CONSTANTS=y
469# CONFIG_SCSI_LOGGING is not set
470
471#
472# SCSI Transports
473#
474# CONFIG_SCSI_SPI_ATTRS is not set
475# CONFIG_SCSI_FC_ATTRS is not set
476CONFIG_SCSI_ISCSI_ATTRS=y
477CONFIG_SCSI_SAS_ATTRS=y
478# CONFIG_SCSI_SAS_LIBSAS is not set
479
480#
481# SCSI low-level drivers
482#
483# CONFIG_ISCSI_TCP is not set
484# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
485# CONFIG_SCSI_3W_9XXX is not set
486# CONFIG_SCSI_ACARD is not set
487# CONFIG_SCSI_AACRAID is not set
488# CONFIG_SCSI_AIC7XXX is not set
489# CONFIG_SCSI_AIC7XXX_OLD is not set
490# CONFIG_SCSI_AIC79XX is not set
491# CONFIG_SCSI_AIC94XX is not set
492# CONFIG_SCSI_DPT_I2O is not set
493# CONFIG_SCSI_ARCMSR is not set
494# CONFIG_MEGARAID_NEWGEN is not set
495# CONFIG_MEGARAID_LEGACY is not set
496# CONFIG_MEGARAID_SAS is not set
497# CONFIG_SCSI_HPTIOP is not set
498# CONFIG_SCSI_DMX3191D is not set
499# CONFIG_SCSI_FUTURE_DOMAIN is not set
500# CONFIG_SCSI_IPS is not set
501# CONFIG_SCSI_INITIO is not set
502# CONFIG_SCSI_INIA100 is not set
503# CONFIG_SCSI_STEX is not set
504# CONFIG_SCSI_SYM53C8XX_2 is not set
505# CONFIG_SCSI_QLOGIC_1280 is not set
506# CONFIG_SCSI_QLA_FC is not set
507# CONFIG_SCSI_QLA_ISCSI is not set
508# CONFIG_SCSI_LPFC is not set
509# CONFIG_SCSI_DC395x is not set
510# CONFIG_SCSI_DC390T is not set
511# CONFIG_SCSI_NSP32 is not set
512# CONFIG_SCSI_DEBUG is not set
513
514#
515# Serial ATA (prod) and Parallel ATA (experimental) drivers
516#
517# CONFIG_ATA is not set
518
519#
520# Multi-device support (RAID and LVM)
521#
522CONFIG_MD=y
523CONFIG_BLK_DEV_MD=y
524# CONFIG_MD_LINEAR is not set
525CONFIG_MD_RAID0=y
526CONFIG_MD_RAID1=y
527CONFIG_MD_RAID10=y
528CONFIG_MD_RAID456=y
529# CONFIG_MD_RAID5_RESHAPE is not set
530# CONFIG_MD_MULTIPATH is not set
531# CONFIG_MD_FAULTY is not set
532CONFIG_BLK_DEV_DM=y
533# CONFIG_DM_DEBUG is not set
534# CONFIG_DM_CRYPT is not set
535# CONFIG_DM_SNAPSHOT is not set
536# CONFIG_DM_MIRROR is not set
537# CONFIG_DM_ZERO is not set
538# CONFIG_DM_MULTIPATH is not set
539
540#
541# Fusion MPT device support
542#
543# CONFIG_FUSION is not set
544# CONFIG_FUSION_SPI is not set
545# CONFIG_FUSION_FC is not set
546# CONFIG_FUSION_SAS is not set
547
548#
549# IEEE 1394 (FireWire) support
550#
551# CONFIG_IEEE1394 is not set
552
553#
554# I2O device support
555#
556# CONFIG_I2O is not set
557
558#
559# Network device support
560#
561CONFIG_NETDEVICES=y
562# CONFIG_DUMMY is not set
563# CONFIG_BONDING is not set
564# CONFIG_EQUALIZER is not set
565# CONFIG_TUN is not set
566
567#
568# ARCnet devices
569#
570# CONFIG_ARCNET is not set
571
572#
573# PHY device support
574#
575
576#
577# Ethernet (10 or 100Mbit)
578#
579# CONFIG_NET_ETHERNET is not set
580
581#
582# Ethernet (1000 Mbit)
583#
584# CONFIG_ACENIC is not set
585# CONFIG_DL2K is not set
586CONFIG_E1000=y
587CONFIG_E1000_NAPI=y
588# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
589# CONFIG_NS83820 is not set
590# CONFIG_HAMACHI is not set
591# CONFIG_YELLOWFIN is not set
592# CONFIG_R8169 is not set
593# CONFIG_SIS190 is not set
594# CONFIG_SKGE is not set
595# CONFIG_SKY2 is not set
596# CONFIG_SK98LIN is not set
597# CONFIG_TIGON3 is not set
598# CONFIG_BNX2 is not set
599# CONFIG_QLA3XXX is not set
600
601#
602# Ethernet (10000 Mbit)
603#
604# CONFIG_CHELSIO_T1 is not set
605# CONFIG_IXGB is not set
606# CONFIG_S2IO is not set
607# CONFIG_MYRI10GE is not set
608
609#
610# Token Ring devices
611#
612# CONFIG_TR is not set
613
614#
615# Wireless LAN (non-hamradio)
616#
617# CONFIG_NET_RADIO is not set
618
619#
620# Wan interfaces
621#
622# CONFIG_WAN is not set
623# CONFIG_FDDI is not set
624# CONFIG_HIPPI is not set
625# CONFIG_PPP is not set
626# CONFIG_SLIP is not set
627# CONFIG_NET_FC is not set
628# CONFIG_SHAPER is not set
629# CONFIG_NETCONSOLE is not set
630# CONFIG_NETPOLL is not set
631# CONFIG_NET_POLL_CONTROLLER is not set
632
633#
634# ISDN subsystem
635#
636# CONFIG_ISDN is not set
637
638#
639# Input device support
640#
641CONFIG_INPUT=y
642# CONFIG_INPUT_FF_MEMLESS is not set
643
644#
645# Userland interfaces
646#
647CONFIG_INPUT_MOUSEDEV=y
648# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
649CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
650CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
651# CONFIG_INPUT_JOYDEV is not set
652# CONFIG_INPUT_TSDEV is not set
653# CONFIG_INPUT_EVDEV is not set
654# CONFIG_INPUT_EVBUG is not set
655
656#
657# Input Device Drivers
658#
659# CONFIG_INPUT_KEYBOARD is not set
660# CONFIG_INPUT_MOUSE is not set
661# CONFIG_INPUT_JOYSTICK is not set
662# CONFIG_INPUT_TOUCHSCREEN is not set
663# CONFIG_INPUT_MISC is not set
664
665#
666# Hardware I/O ports
667#
668# CONFIG_SERIO is not set
669# CONFIG_GAMEPORT is not set
670
671#
672# Character devices
673#
674CONFIG_VT=y
675CONFIG_VT_CONSOLE=y
676CONFIG_HW_CONSOLE=y
677# CONFIG_VT_HW_CONSOLE_BINDING is not set
678# CONFIG_SERIAL_NONSTANDARD is not set
679
680#
681# Serial drivers
682#
683CONFIG_SERIAL_8250=y
684CONFIG_SERIAL_8250_CONSOLE=y
685CONFIG_SERIAL_8250_PCI=y
686CONFIG_SERIAL_8250_NR_UARTS=2
687CONFIG_SERIAL_8250_RUNTIME_UARTS=2
688# CONFIG_SERIAL_8250_EXTENDED is not set
689
690#
691# Non-8250 serial port support
692#
693CONFIG_SERIAL_CORE=y
694CONFIG_SERIAL_CORE_CONSOLE=y
695# CONFIG_SERIAL_JSM is not set
696CONFIG_UNIX98_PTYS=y
697CONFIG_LEGACY_PTYS=y
698CONFIG_LEGACY_PTY_COUNT=256
699
700#
701# IPMI
702#
703# CONFIG_IPMI_HANDLER is not set
704
705#
706# Watchdog Cards
707#
708# CONFIG_WATCHDOG is not set
709CONFIG_HW_RANDOM=y
710# CONFIG_NVRAM is not set
711# CONFIG_DTLK is not set
712# CONFIG_R3964 is not set
713# CONFIG_APPLICOM is not set
714
715#
716# Ftape, the floppy tape device driver
717#
718# CONFIG_DRM is not set
719# CONFIG_RAW_DRIVER is not set
720
721#
722# TPM devices
723#
724# CONFIG_TCG_TPM is not set
725
726#
727# I2C support
728#
729CONFIG_I2C=y
730# CONFIG_I2C_CHARDEV is not set
731
732#
733# I2C Algorithms
734#
735CONFIG_I2C_ALGOBIT=m
736CONFIG_I2C_ALGOPCF=m
737CONFIG_I2C_ALGOPCA=m
738
739#
740# I2C Hardware Bus support
741#
742# CONFIG_I2C_ALI1535 is not set
743# CONFIG_I2C_ALI1563 is not set
744# CONFIG_I2C_ALI15X3 is not set
745# CONFIG_I2C_AMD756 is not set
746# CONFIG_I2C_AMD8111 is not set
747# CONFIG_I2C_I801 is not set
748# CONFIG_I2C_I810 is not set
749# CONFIG_I2C_PIIX4 is not set
750CONFIG_I2C_IOP3XX=y
751# CONFIG_I2C_NFORCE2 is not set
752# CONFIG_I2C_OCORES is not set
753# CONFIG_I2C_PARPORT_LIGHT is not set
754# CONFIG_I2C_PROSAVAGE is not set
755# CONFIG_I2C_SAVAGE4 is not set
756# CONFIG_I2C_SIS5595 is not set
757# CONFIG_I2C_SIS630 is not set
758# CONFIG_I2C_SIS96X is not set
759# CONFIG_I2C_STUB is not set
760# CONFIG_I2C_VIA is not set
761# CONFIG_I2C_VIAPRO is not set
762# CONFIG_I2C_VOODOO3 is not set
763# CONFIG_I2C_PCA_ISA is not set
764
765#
766# Miscellaneous I2C Chip support
767#
768# CONFIG_SENSORS_DS1337 is not set
769# CONFIG_SENSORS_DS1374 is not set
770# CONFIG_SENSORS_EEPROM is not set
771# CONFIG_SENSORS_PCF8574 is not set
772# CONFIG_SENSORS_PCA9539 is not set
773# CONFIG_SENSORS_PCF8591 is not set
774# CONFIG_SENSORS_MAX6875 is not set
775# CONFIG_I2C_DEBUG_CORE is not set
776# CONFIG_I2C_DEBUG_ALGO is not set
777# CONFIG_I2C_DEBUG_BUS is not set
778# CONFIG_I2C_DEBUG_CHIP is not set
779
780#
781# SPI support
782#
783# CONFIG_SPI is not set
784# CONFIG_SPI_MASTER is not set
785
786#
787# Dallas's 1-wire bus
788#
789# CONFIG_W1 is not set
790
791#
792# Hardware Monitoring support
793#
794CONFIG_HWMON=y
795# CONFIG_HWMON_VID is not set
796# CONFIG_SENSORS_ABITUGURU is not set
797# CONFIG_SENSORS_ADM1021 is not set
798# CONFIG_SENSORS_ADM1025 is not set
799# CONFIG_SENSORS_ADM1026 is not set
800# CONFIG_SENSORS_ADM1031 is not set
801# CONFIG_SENSORS_ADM9240 is not set
802# CONFIG_SENSORS_ASB100 is not set
803# CONFIG_SENSORS_ATXP1 is not set
804# CONFIG_SENSORS_DS1621 is not set
805# CONFIG_SENSORS_F71805F is not set
806# CONFIG_SENSORS_FSCHER is not set
807# CONFIG_SENSORS_FSCPOS is not set
808# CONFIG_SENSORS_GL518SM is not set
809# CONFIG_SENSORS_GL520SM is not set
810# CONFIG_SENSORS_IT87 is not set
811# CONFIG_SENSORS_LM63 is not set
812# CONFIG_SENSORS_LM75 is not set
813# CONFIG_SENSORS_LM77 is not set
814# CONFIG_SENSORS_LM78 is not set
815# CONFIG_SENSORS_LM80 is not set
816# CONFIG_SENSORS_LM83 is not set
817# CONFIG_SENSORS_LM85 is not set
818# CONFIG_SENSORS_LM87 is not set
819# CONFIG_SENSORS_LM90 is not set
820# CONFIG_SENSORS_LM92 is not set
821# CONFIG_SENSORS_MAX1619 is not set
822# CONFIG_SENSORS_PC87360 is not set
823# CONFIG_SENSORS_SIS5595 is not set
824# CONFIG_SENSORS_SMSC47M1 is not set
825# CONFIG_SENSORS_SMSC47M192 is not set
826# CONFIG_SENSORS_SMSC47B397 is not set
827# CONFIG_SENSORS_VIA686A is not set
828# CONFIG_SENSORS_VT1211 is not set
829# CONFIG_SENSORS_VT8231 is not set
830# CONFIG_SENSORS_W83781D is not set
831# CONFIG_SENSORS_W83791D is not set
832# CONFIG_SENSORS_W83792D is not set
833# CONFIG_SENSORS_W83L785TS is not set
834# CONFIG_SENSORS_W83627HF is not set
835# CONFIG_SENSORS_W83627EHF is not set
836# CONFIG_HWMON_DEBUG_CHIP is not set
837
838#
839# Misc devices
840#
841# CONFIG_SGI_IOC4 is not set
842# CONFIG_TIFM_CORE is not set
843
844#
845# LED devices
846#
847# CONFIG_NEW_LEDS is not set
848
849#
850# LED drivers
851#
852
853#
854# LED Triggers
855#
856
857#
858# Multimedia devices
859#
860# CONFIG_VIDEO_DEV is not set
861
862#
863# Digital Video Broadcasting Devices
864#
865# CONFIG_DVB is not set
866
867#
868# Graphics support
869#
870CONFIG_FIRMWARE_EDID=y
871# CONFIG_FB is not set
872
873#
874# Console display driver support
875#
876# CONFIG_VGA_CONSOLE is not set
877CONFIG_DUMMY_CONSOLE=y
878# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
879
880#
881# Sound
882#
883# CONFIG_SOUND is not set
884
885#
886# USB support
887#
888CONFIG_USB_ARCH_HAS_HCD=y
889CONFIG_USB_ARCH_HAS_OHCI=y
890CONFIG_USB_ARCH_HAS_EHCI=y
891# CONFIG_USB is not set
892
893#
894# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
895#
896
897#
898# USB Gadget Support
899#
900# CONFIG_USB_GADGET is not set
901
902#
903# MMC/SD Card support
904#
905# CONFIG_MMC is not set
906
907#
908# Real Time Clock
909#
910CONFIG_RTC_LIB=y
911# CONFIG_RTC_CLASS is not set
912
913#
914# File systems
915#
916CONFIG_EXT2_FS=y
917# CONFIG_EXT2_FS_XATTR is not set
918# CONFIG_EXT2_FS_XIP is not set
919CONFIG_EXT3_FS=y
920CONFIG_EXT3_FS_XATTR=y
921# CONFIG_EXT3_FS_POSIX_ACL is not set
922# CONFIG_EXT3_FS_SECURITY is not set
923# CONFIG_EXT4DEV_FS is not set
924CONFIG_JBD=y
925# CONFIG_JBD_DEBUG is not set
926CONFIG_FS_MBCACHE=y
927# CONFIG_REISERFS_FS is not set
928# CONFIG_JFS_FS is not set
929# CONFIG_FS_POSIX_ACL is not set
930# CONFIG_XFS_FS is not set
931# CONFIG_GFS2_FS is not set
932# CONFIG_OCFS2_FS is not set
933# CONFIG_MINIX_FS is not set
934# CONFIG_ROMFS_FS is not set
935CONFIG_INOTIFY=y
936CONFIG_INOTIFY_USER=y
937# CONFIG_QUOTA is not set
938CONFIG_DNOTIFY=y
939# CONFIG_AUTOFS_FS is not set
940# CONFIG_AUTOFS4_FS is not set
941# CONFIG_FUSE_FS is not set
942
943#
944# CD-ROM/DVD Filesystems
945#
946# CONFIG_ISO9660_FS is not set
947# CONFIG_UDF_FS is not set
948
949#
950# DOS/FAT/NT Filesystems
951#
952# CONFIG_MSDOS_FS is not set
953# CONFIG_VFAT_FS is not set
954# CONFIG_NTFS_FS is not set
955
956#
957# Pseudo filesystems
958#
959CONFIG_PROC_FS=y
960CONFIG_PROC_SYSCTL=y
961CONFIG_SYSFS=y
962CONFIG_TMPFS=y
963# CONFIG_TMPFS_POSIX_ACL is not set
964# CONFIG_HUGETLB_PAGE is not set
965CONFIG_RAMFS=y
966# CONFIG_CONFIGFS_FS is not set
967
968#
969# Miscellaneous filesystems
970#
971# CONFIG_ADFS_FS is not set
972# CONFIG_AFFS_FS is not set
973# CONFIG_HFS_FS is not set
974# CONFIG_HFSPLUS_FS is not set
975# CONFIG_BEFS_FS is not set
976# CONFIG_BFS_FS is not set
977# CONFIG_EFS_FS is not set
978# CONFIG_JFFS_FS is not set
979CONFIG_JFFS2_FS=y
980CONFIG_JFFS2_FS_DEBUG=0
981CONFIG_JFFS2_FS_WRITEBUFFER=y
982# CONFIG_JFFS2_SUMMARY is not set
983# CONFIG_JFFS2_FS_XATTR is not set
984# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
985CONFIG_JFFS2_ZLIB=y
986CONFIG_JFFS2_RTIME=y
987# CONFIG_JFFS2_RUBIN is not set
988# CONFIG_CRAMFS is not set
989# CONFIG_VXFS_FS is not set
990# CONFIG_HPFS_FS is not set
991# CONFIG_QNX4FS_FS is not set
992# CONFIG_SYSV_FS is not set
993# CONFIG_UFS_FS is not set
994
995#
996# Network File Systems
997#
998CONFIG_NFS_FS=y
999CONFIG_NFS_V3=y
1000# CONFIG_NFS_V3_ACL is not set
1001# CONFIG_NFS_V4 is not set
1002# CONFIG_NFS_DIRECTIO is not set
1003CONFIG_NFSD=y
1004CONFIG_NFSD_V3=y
1005# CONFIG_NFSD_V3_ACL is not set
1006# CONFIG_NFSD_V4 is not set
1007CONFIG_NFSD_TCP=y
1008CONFIG_ROOT_NFS=y
1009CONFIG_LOCKD=y
1010CONFIG_LOCKD_V4=y
1011CONFIG_EXPORTFS=y
1012CONFIG_NFS_COMMON=y
1013CONFIG_SUNRPC=y
1014# CONFIG_RPCSEC_GSS_KRB5 is not set
1015# CONFIG_RPCSEC_GSS_SPKM3 is not set
1016CONFIG_SMB_FS=m
1017# CONFIG_SMB_NLS_DEFAULT is not set
1018CONFIG_CIFS=m
1019# CONFIG_CIFS_STATS is not set
1020# CONFIG_CIFS_WEAK_PW_HASH is not set
1021# CONFIG_CIFS_XATTR is not set
1022# CONFIG_CIFS_DEBUG2 is not set
1023# CONFIG_CIFS_EXPERIMENTAL is not set
1024# CONFIG_NCP_FS is not set
1025# CONFIG_CODA_FS is not set
1026# CONFIG_AFS_FS is not set
1027# CONFIG_9P_FS is not set
1028
1029#
1030# Partition Types
1031#
1032CONFIG_PARTITION_ADVANCED=y
1033# CONFIG_ACORN_PARTITION is not set
1034# CONFIG_OSF_PARTITION is not set
1035# CONFIG_AMIGA_PARTITION is not set
1036# CONFIG_ATARI_PARTITION is not set
1037# CONFIG_MAC_PARTITION is not set
1038CONFIG_MSDOS_PARTITION=y
1039# CONFIG_BSD_DISKLABEL is not set
1040# CONFIG_MINIX_SUBPARTITION is not set
1041# CONFIG_SOLARIS_X86_PARTITION is not set
1042# CONFIG_UNIXWARE_DISKLABEL is not set
1043# CONFIG_LDM_PARTITION is not set
1044# CONFIG_SGI_PARTITION is not set
1045# CONFIG_ULTRIX_PARTITION is not set
1046# CONFIG_SUN_PARTITION is not set
1047# CONFIG_KARMA_PARTITION is not set
1048# CONFIG_EFI_PARTITION is not set
1049
1050#
1051# Native Language Support
1052#
1053CONFIG_NLS=y
1054CONFIG_NLS_DEFAULT="iso8859-1"
1055# CONFIG_NLS_CODEPAGE_437 is not set
1056# CONFIG_NLS_CODEPAGE_737 is not set
1057# CONFIG_NLS_CODEPAGE_775 is not set
1058# CONFIG_NLS_CODEPAGE_850 is not set
1059# CONFIG_NLS_CODEPAGE_852 is not set
1060# CONFIG_NLS_CODEPAGE_855 is not set
1061# CONFIG_NLS_CODEPAGE_857 is not set
1062# CONFIG_NLS_CODEPAGE_860 is not set
1063# CONFIG_NLS_CODEPAGE_861 is not set
1064# CONFIG_NLS_CODEPAGE_862 is not set
1065# CONFIG_NLS_CODEPAGE_863 is not set
1066# CONFIG_NLS_CODEPAGE_864 is not set
1067# CONFIG_NLS_CODEPAGE_865 is not set
1068# CONFIG_NLS_CODEPAGE_866 is not set
1069# CONFIG_NLS_CODEPAGE_869 is not set
1070# CONFIG_NLS_CODEPAGE_936 is not set
1071# CONFIG_NLS_CODEPAGE_950 is not set
1072# CONFIG_NLS_CODEPAGE_932 is not set
1073# CONFIG_NLS_CODEPAGE_949 is not set
1074# CONFIG_NLS_CODEPAGE_874 is not set
1075# CONFIG_NLS_ISO8859_8 is not set
1076# CONFIG_NLS_CODEPAGE_1250 is not set
1077# CONFIG_NLS_CODEPAGE_1251 is not set
1078# CONFIG_NLS_ASCII is not set
1079# CONFIG_NLS_ISO8859_1 is not set
1080# CONFIG_NLS_ISO8859_2 is not set
1081# CONFIG_NLS_ISO8859_3 is not set
1082# CONFIG_NLS_ISO8859_4 is not set
1083# CONFIG_NLS_ISO8859_5 is not set
1084# CONFIG_NLS_ISO8859_6 is not set
1085# CONFIG_NLS_ISO8859_7 is not set
1086# CONFIG_NLS_ISO8859_9 is not set
1087# CONFIG_NLS_ISO8859_13 is not set
1088# CONFIG_NLS_ISO8859_14 is not set
1089# CONFIG_NLS_ISO8859_15 is not set
1090# CONFIG_NLS_KOI8_R is not set
1091# CONFIG_NLS_KOI8_U is not set
1092# CONFIG_NLS_UTF8 is not set
1093
1094#
1095# Profiling support
1096#
1097# CONFIG_PROFILING is not set
1098
1099#
1100# Kernel hacking
1101#
1102# CONFIG_PRINTK_TIME is not set
1103CONFIG_ENABLE_MUST_CHECK=y
1104# CONFIG_MAGIC_SYSRQ is not set
1105# CONFIG_UNUSED_SYMBOLS is not set
1106# CONFIG_DEBUG_KERNEL is not set
1107CONFIG_LOG_BUF_SHIFT=14
1108CONFIG_DEBUG_BUGVERBOSE=y
1109# CONFIG_DEBUG_FS is not set
1110CONFIG_FRAME_POINTER=y
1111# CONFIG_HEADERS_CHECK is not set
1112CONFIG_DEBUG_USER=y
1113
1114#
1115# Security options
1116#
1117# CONFIG_KEYS is not set
1118# CONFIG_SECURITY is not set
1119
1120#
1121# Cryptographic options
1122#
1123# CONFIG_CRYPTO is not set
1124
1125#
1126# Library routines
1127#
1128CONFIG_CRC_CCITT=y
1129# CONFIG_CRC16 is not set
1130CONFIG_CRC32=y
1131CONFIG_LIBCRC32C=y
1132CONFIG_ZLIB_INFLATE=y
1133CONFIG_ZLIB_DEFLATE=y
1134CONFIG_PLIST=y
diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig
index 0d67f66e78c2..b275c53728ec 100644
--- a/arch/arm/configs/iop32x_defconfig
+++ b/arch/arm/configs/iop32x_defconfig
@@ -1204,7 +1204,6 @@ CONFIG_FRAME_POINTER=y
1204# CONFIG_FORCED_INLINING is not set 1204# CONFIG_FORCED_INLINING is not set
1205# CONFIG_RCU_TORTURE_TEST is not set 1205# CONFIG_RCU_TORTURE_TEST is not set
1206CONFIG_DEBUG_USER=y 1206CONFIG_DEBUG_USER=y
1207# CONFIG_DEBUG_WAITQ is not set
1208# CONFIG_DEBUG_ERRORS is not set 1207# CONFIG_DEBUG_ERRORS is not set
1209CONFIG_DEBUG_LL=y 1208CONFIG_DEBUG_LL=y
1210# CONFIG_DEBUG_ICEDCC is not set 1209# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig
index 2a8fc153969d..848e3ace9069 100644
--- a/arch/arm/configs/iop33x_defconfig
+++ b/arch/arm/configs/iop33x_defconfig
@@ -1051,7 +1051,6 @@ CONFIG_FRAME_POINTER=y
1051# CONFIG_FORCED_INLINING is not set 1051# CONFIG_FORCED_INLINING is not set
1052# CONFIG_RCU_TORTURE_TEST is not set 1052# CONFIG_RCU_TORTURE_TEST is not set
1053CONFIG_DEBUG_USER=y 1053CONFIG_DEBUG_USER=y
1054# CONFIG_DEBUG_WAITQ is not set
1055# CONFIG_DEBUG_ERRORS is not set 1054# CONFIG_DEBUG_ERRORS is not set
1056CONFIG_DEBUG_LL=y 1055CONFIG_DEBUG_LL=y
1057# CONFIG_DEBUG_ICEDCC is not set 1056# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ixp2000_defconfig b/arch/arm/configs/ixp2000_defconfig
index 27b3e31a8ad8..bbd2dcf91e52 100644
--- a/arch/arm/configs/ixp2000_defconfig
+++ b/arch/arm/configs/ixp2000_defconfig
@@ -1026,7 +1026,6 @@ CONFIG_FRAME_POINTER=y
1026CONFIG_FORCED_INLINING=y 1026CONFIG_FORCED_INLINING=y
1027# CONFIG_RCU_TORTURE_TEST is not set 1027# CONFIG_RCU_TORTURE_TEST is not set
1028CONFIG_DEBUG_USER=y 1028CONFIG_DEBUG_USER=y
1029# CONFIG_DEBUG_WAITQ is not set
1030CONFIG_DEBUG_ERRORS=y 1029CONFIG_DEBUG_ERRORS=y
1031CONFIG_DEBUG_LL=y 1030CONFIG_DEBUG_LL=y
1032# CONFIG_DEBUG_ICEDCC is not set 1031# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig
index 7b18997083ce..06deefaec1d2 100644
--- a/arch/arm/configs/ixp23xx_defconfig
+++ b/arch/arm/configs/ixp23xx_defconfig
@@ -1305,7 +1305,6 @@ CONFIG_FRAME_POINTER=y
1305CONFIG_FORCED_INLINING=y 1305CONFIG_FORCED_INLINING=y
1306# CONFIG_RCU_TORTURE_TEST is not set 1306# CONFIG_RCU_TORTURE_TEST is not set
1307CONFIG_DEBUG_USER=y 1307CONFIG_DEBUG_USER=y
1308# CONFIG_DEBUG_WAITQ is not set
1309CONFIG_DEBUG_ERRORS=y 1308CONFIG_DEBUG_ERRORS=y
1310CONFIG_DEBUG_LL=y 1309CONFIG_DEBUG_LL=y
1311# CONFIG_DEBUG_ICEDCC is not set 1310# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index fac7c3b240c0..fabf74c51a88 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -1243,7 +1243,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1243CONFIG_FRAME_POINTER=y 1243CONFIG_FRAME_POINTER=y
1244# CONFIG_RCU_TORTURE_TEST is not set 1244# CONFIG_RCU_TORTURE_TEST is not set
1245# CONFIG_DEBUG_USER is not set 1245# CONFIG_DEBUG_USER is not set
1246# CONFIG_DEBUG_WAITQ is not set
1247CONFIG_DEBUG_ERRORS=y 1246CONFIG_DEBUG_ERRORS=y
1248CONFIG_DEBUG_LL=y 1247CONFIG_DEBUG_LL=y
1249# CONFIG_DEBUG_ICEDCC is not set 1248# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
index 80a6fd97eb32..0c556289a3f4 100644
--- a/arch/arm/configs/jornada720_defconfig
+++ b/arch/arm/configs/jornada720_defconfig
@@ -889,7 +889,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
889# CONFIG_DEBUG_FS is not set 889# CONFIG_DEBUG_FS is not set
890CONFIG_FRAME_POINTER=y 890CONFIG_FRAME_POINTER=y
891# CONFIG_DEBUG_USER is not set 891# CONFIG_DEBUG_USER is not set
892# CONFIG_DEBUG_WAITQ is not set
893CONFIG_DEBUG_ERRORS=y 892CONFIG_DEBUG_ERRORS=y
894CONFIG_DEBUG_LL=y 893CONFIG_DEBUG_LL=y
895# CONFIG_DEBUG_ICEDCC is not set 894# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/kb9202_defconfig b/arch/arm/configs/kb9202_defconfig
index b4cd4b414836..c16537d9d67a 100644
--- a/arch/arm/configs/kb9202_defconfig
+++ b/arch/arm/configs/kb9202_defconfig
@@ -437,7 +437,7 @@ CONFIG_LEGACY_PTY_COUNT=256
437# CONFIG_WATCHDOG is not set 437# CONFIG_WATCHDOG is not set
438# CONFIG_NVRAM is not set 438# CONFIG_NVRAM is not set
439# CONFIG_RTC is not set 439# CONFIG_RTC is not set
440# CONFIG_AT91_RTC is not set 440# CONFIG_AT91RM9200_RTC is not set
441# CONFIG_DTLK is not set 441# CONFIG_DTLK is not set
442# CONFIG_R3964 is not set 442# CONFIG_R3964 is not set
443 443
@@ -753,7 +753,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
753# CONFIG_DEBUG_FS is not set 753# CONFIG_DEBUG_FS is not set
754CONFIG_FRAME_POINTER=y 754CONFIG_FRAME_POINTER=y
755CONFIG_DEBUG_USER=y 755CONFIG_DEBUG_USER=y
756# CONFIG_DEBUG_WAITQ is not set
757CONFIG_DEBUG_ERRORS=y 756CONFIG_DEBUG_ERRORS=y
758CONFIG_DEBUG_LL=y 757CONFIG_DEBUG_LL=y
759# CONFIG_DEBUG_ICEDCC is not set 758# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig
index 4b29e099640d..e146189ab54f 100644
--- a/arch/arm/configs/lpd270_defconfig
+++ b/arch/arm/configs/lpd270_defconfig
@@ -949,7 +949,6 @@ CONFIG_FRAME_POINTER=y
949CONFIG_FORCED_INLINING=y 949CONFIG_FORCED_INLINING=y
950# CONFIG_RCU_TORTURE_TEST is not set 950# CONFIG_RCU_TORTURE_TEST is not set
951CONFIG_DEBUG_USER=y 951CONFIG_DEBUG_USER=y
952# CONFIG_DEBUG_WAITQ is not set
953CONFIG_DEBUG_ERRORS=y 952CONFIG_DEBUG_ERRORS=y
954CONFIG_DEBUG_LL=y 953CONFIG_DEBUG_LL=y
955# CONFIG_DEBUG_ICEDCC is not set 954# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/lpd7a400_defconfig b/arch/arm/configs/lpd7a400_defconfig
index bf9cf9c6d2df..f8ac29d5c654 100644
--- a/arch/arm/configs/lpd7a400_defconfig
+++ b/arch/arm/configs/lpd7a400_defconfig
@@ -850,7 +850,6 @@ CONFIG_DEBUG_INFO=y
850# CONFIG_DEBUG_FS is not set 850# CONFIG_DEBUG_FS is not set
851CONFIG_FRAME_POINTER=y 851CONFIG_FRAME_POINTER=y
852CONFIG_DEBUG_USER=y 852CONFIG_DEBUG_USER=y
853# CONFIG_DEBUG_WAITQ is not set
854CONFIG_DEBUG_ERRORS=y 853CONFIG_DEBUG_ERRORS=y
855# CONFIG_DEBUG_LL is not set 854# CONFIG_DEBUG_LL is not set
856 855
diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig
index 3a57be32e849..46a0f7fe1fa5 100644
--- a/arch/arm/configs/lpd7a404_defconfig
+++ b/arch/arm/configs/lpd7a404_defconfig
@@ -1100,7 +1100,6 @@ CONFIG_FRAME_POINTER=y
1100CONFIG_FORCED_INLINING=y 1100CONFIG_FORCED_INLINING=y
1101# CONFIG_RCU_TORTURE_TEST is not set 1101# CONFIG_RCU_TORTURE_TEST is not set
1102CONFIG_DEBUG_USER=y 1102CONFIG_DEBUG_USER=y
1103# CONFIG_DEBUG_WAITQ is not set
1104CONFIG_DEBUG_ERRORS=y 1103CONFIG_DEBUG_ERRORS=y
1105# CONFIG_DEBUG_LL is not set 1104# CONFIG_DEBUG_LL is not set
1106 1105
diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig
index 81daadcbe0ba..e544bfbbde5d 100644
--- a/arch/arm/configs/lubbock_defconfig
+++ b/arch/arm/configs/lubbock_defconfig
@@ -772,7 +772,6 @@ CONFIG_DEBUG_INFO=y
772# CONFIG_DEBUG_FS is not set 772# CONFIG_DEBUG_FS is not set
773CONFIG_FRAME_POINTER=y 773CONFIG_FRAME_POINTER=y
774CONFIG_DEBUG_USER=y 774CONFIG_DEBUG_USER=y
775# CONFIG_DEBUG_WAITQ is not set
776CONFIG_DEBUG_ERRORS=y 775CONFIG_DEBUG_ERRORS=y
777CONFIG_DEBUG_LL=y 776CONFIG_DEBUG_LL=y
778# CONFIG_DEBUG_ICEDCC is not set 777# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig
index b112bd75bda2..cc8c95b99292 100644
--- a/arch/arm/configs/mainstone_defconfig
+++ b/arch/arm/configs/mainstone_defconfig
@@ -766,7 +766,6 @@ CONFIG_DEBUG_INFO=y
766# CONFIG_DEBUG_FS is not set 766# CONFIG_DEBUG_FS is not set
767CONFIG_FRAME_POINTER=y 767CONFIG_FRAME_POINTER=y
768CONFIG_DEBUG_USER=y 768CONFIG_DEBUG_USER=y
769# CONFIG_DEBUG_WAITQ is not set
770CONFIG_DEBUG_ERRORS=y 769CONFIG_DEBUG_ERRORS=y
771CONFIG_DEBUG_LL=y 770CONFIG_DEBUG_LL=y
772# CONFIG_DEBUG_ICEDCC is not set 771# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/mx1ads_defconfig b/arch/arm/configs/mx1ads_defconfig
index d16f6cd6e039..577d7e1b5d42 100644
--- a/arch/arm/configs/mx1ads_defconfig
+++ b/arch/arm/configs/mx1ads_defconfig
@@ -691,7 +691,6 @@ CONFIG_DEBUG_INFO=y
691# CONFIG_DEBUG_FS is not set 691# CONFIG_DEBUG_FS is not set
692CONFIG_FRAME_POINTER=y 692CONFIG_FRAME_POINTER=y
693CONFIG_DEBUG_USER=y 693CONFIG_DEBUG_USER=y
694# CONFIG_DEBUG_WAITQ is not set
695CONFIG_DEBUG_ERRORS=y 694CONFIG_DEBUG_ERRORS=y
696# CONFIG_DEBUG_LL is not set 695# CONFIG_DEBUG_LL is not set
697 696
diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig
index df8168e57b7c..e86794a10fc0 100644
--- a/arch/arm/configs/neponset_defconfig
+++ b/arch/arm/configs/neponset_defconfig
@@ -1115,7 +1115,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1115# CONFIG_DEBUG_FS is not set 1115# CONFIG_DEBUG_FS is not set
1116CONFIG_FRAME_POINTER=y 1116CONFIG_FRAME_POINTER=y
1117CONFIG_DEBUG_USER=y 1117CONFIG_DEBUG_USER=y
1118# CONFIG_DEBUG_WAITQ is not set
1119CONFIG_DEBUG_ERRORS=y 1118CONFIG_DEBUG_ERRORS=y
1120CONFIG_DEBUG_LL=y 1119CONFIG_DEBUG_LL=y
1121# CONFIG_DEBUG_ICEDCC is not set 1120# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/netwinder_defconfig b/arch/arm/configs/netwinder_defconfig
index 2cae1ead9f9b..c1a63a35c58d 100644
--- a/arch/arm/configs/netwinder_defconfig
+++ b/arch/arm/configs/netwinder_defconfig
@@ -994,7 +994,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
994# CONFIG_DEBUG_FS is not set 994# CONFIG_DEBUG_FS is not set
995CONFIG_FRAME_POINTER=y 995CONFIG_FRAME_POINTER=y
996CONFIG_DEBUG_USER=y 996CONFIG_DEBUG_USER=y
997# CONFIG_DEBUG_WAITQ is not set
998# CONFIG_DEBUG_ERRORS is not set 997# CONFIG_DEBUG_ERRORS is not set
999# CONFIG_DEBUG_LL is not set 998# CONFIG_DEBUG_LL is not set
1000 999
diff --git a/arch/arm/configs/netx_defconfig b/arch/arm/configs/netx_defconfig
index 61115a773382..57f32f39d0ff 100644
--- a/arch/arm/configs/netx_defconfig
+++ b/arch/arm/configs/netx_defconfig
@@ -872,7 +872,6 @@ CONFIG_FRAME_POINTER=y
872CONFIG_FORCED_INLINING=y 872CONFIG_FORCED_INLINING=y
873# CONFIG_RCU_TORTURE_TEST is not set 873# CONFIG_RCU_TORTURE_TEST is not set
874# CONFIG_DEBUG_USER is not set 874# CONFIG_DEBUG_USER is not set
875# CONFIG_DEBUG_WAITQ is not set
876CONFIG_DEBUG_ERRORS=y 875CONFIG_DEBUG_ERRORS=y
877# CONFIG_DEBUG_LL is not set 876# CONFIG_DEBUG_LL is not set
878 877
diff --git a/arch/arm/configs/onearm_defconfig b/arch/arm/configs/onearm_defconfig
index 9b9f2155af35..0498ebd7d5de 100644
--- a/arch/arm/configs/onearm_defconfig
+++ b/arch/arm/configs/onearm_defconfig
@@ -1045,7 +1045,6 @@ CONFIG_FRAME_POINTER=y
1045CONFIG_FORCED_INLINING=y 1045CONFIG_FORCED_INLINING=y
1046# CONFIG_RCU_TORTURE_TEST is not set 1046# CONFIG_RCU_TORTURE_TEST is not set
1047CONFIG_DEBUG_USER=y 1047CONFIG_DEBUG_USER=y
1048# CONFIG_DEBUG_WAITQ is not set
1049# CONFIG_DEBUG_ERRORS is not set 1048# CONFIG_DEBUG_ERRORS is not set
1050CONFIG_DEBUG_LL=y 1049CONFIG_DEBUG_LL=y
1051# CONFIG_DEBUG_ICEDCC is not set 1050# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig
index 24e8bdd4cb91..a6b47ea8e465 100644
--- a/arch/arm/configs/pleb_defconfig
+++ b/arch/arm/configs/pleb_defconfig
@@ -721,7 +721,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
721# CONFIG_DEBUG_FS is not set 721# CONFIG_DEBUG_FS is not set
722CONFIG_FRAME_POINTER=y 722CONFIG_FRAME_POINTER=y
723# CONFIG_DEBUG_USER is not set 723# CONFIG_DEBUG_USER is not set
724# CONFIG_DEBUG_WAITQ is not set
725# CONFIG_DEBUG_ERRORS is not set 724# CONFIG_DEBUG_ERRORS is not set
726# CONFIG_DEBUG_LL is not set 725# CONFIG_DEBUG_LL is not set
727 726
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
index a4989f44baaa..b5e11aa2e290 100644
--- a/arch/arm/configs/pnx4008_defconfig
+++ b/arch/arm/configs/pnx4008_defconfig
@@ -1604,7 +1604,6 @@ CONFIG_FRAME_POINTER=y
1604CONFIG_FORCED_INLINING=y 1604CONFIG_FORCED_INLINING=y
1605# CONFIG_RCU_TORTURE_TEST is not set 1605# CONFIG_RCU_TORTURE_TEST is not set
1606# CONFIG_DEBUG_USER is not set 1606# CONFIG_DEBUG_USER is not set
1607# CONFIG_DEBUG_WAITQ is not set
1608# CONFIG_DEBUG_ERRORS is not set 1607# CONFIG_DEBUG_ERRORS is not set
1609# CONFIG_DEBUG_LL is not set 1608# CONFIG_DEBUG_LL is not set
1610 1609
diff --git a/arch/arm/configs/pxa255-idp_defconfig b/arch/arm/configs/pxa255-idp_defconfig
index b71d31a4bb56..46e5089df0ae 100644
--- a/arch/arm/configs/pxa255-idp_defconfig
+++ b/arch/arm/configs/pxa255-idp_defconfig
@@ -768,7 +768,6 @@ CONFIG_DEBUG_INFO=y
768# CONFIG_DEBUG_FS is not set 768# CONFIG_DEBUG_FS is not set
769CONFIG_FRAME_POINTER=y 769CONFIG_FRAME_POINTER=y
770CONFIG_DEBUG_USER=y 770CONFIG_DEBUG_USER=y
771# CONFIG_DEBUG_WAITQ is not set
772CONFIG_DEBUG_ERRORS=y 771CONFIG_DEBUG_ERRORS=y
773CONFIG_DEBUG_LL=y 772CONFIG_DEBUG_LL=y
774# CONFIG_DEBUG_ICEDCC is not set 773# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index ffd905ff19f1..fc39ba1a89f3 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -967,7 +967,6 @@ CONFIG_FORCED_INLINING=y
967# CONFIG_HEADERS_CHECK is not set 967# CONFIG_HEADERS_CHECK is not set
968# CONFIG_RCU_TORTURE_TEST is not set 968# CONFIG_RCU_TORTURE_TEST is not set
969CONFIG_DEBUG_USER=y 969CONFIG_DEBUG_USER=y
970# CONFIG_DEBUG_WAITQ is not set
971CONFIG_DEBUG_ERRORS=y 970CONFIG_DEBUG_ERRORS=y
972CONFIG_DEBUG_LL=y 971CONFIG_DEBUG_LL=y
973# CONFIG_DEBUG_ICEDCC is not set 972# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index 3f1ec4e304f7..accbf529ce5b 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -759,7 +759,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
759# CONFIG_DEBUG_FS is not set 759# CONFIG_DEBUG_FS is not set
760CONFIG_FRAME_POINTER=y 760CONFIG_FRAME_POINTER=y
761CONFIG_DEBUG_USER=y 761CONFIG_DEBUG_USER=y
762# CONFIG_DEBUG_WAITQ is not set
763CONFIG_DEBUG_ERRORS=y 762CONFIG_DEBUG_ERRORS=y
764# CONFIG_DEBUG_LL is not set 763# CONFIG_DEBUG_LL is not set
765 764
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index b498afdc03b6..bc091264d354 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -910,7 +910,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
910# CONFIG_DEBUG_FS is not set 910# CONFIG_DEBUG_FS is not set
911CONFIG_FRAME_POINTER=y 911CONFIG_FRAME_POINTER=y
912CONFIG_DEBUG_USER=y 912CONFIG_DEBUG_USER=y
913# CONFIG_DEBUG_WAITQ is not set
914CONFIG_DEBUG_ERRORS=y 913CONFIG_DEBUG_ERRORS=y
915CONFIG_DEBUG_LL=y 914CONFIG_DEBUG_LL=y
916# CONFIG_DEBUG_ICEDCC is not set 915# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index c0152393e494..3b31a33d0080 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -1319,7 +1319,6 @@ CONFIG_FORCED_INLINING=y
1319# CONFIG_HEADERS_CHECK is not set 1319# CONFIG_HEADERS_CHECK is not set
1320# CONFIG_RCU_TORTURE_TEST is not set 1320# CONFIG_RCU_TORTURE_TEST is not set
1321CONFIG_DEBUG_USER=y 1321CONFIG_DEBUG_USER=y
1322# CONFIG_DEBUG_WAITQ is not set
1323# CONFIG_DEBUG_ERRORS is not set 1322# CONFIG_DEBUG_ERRORS is not set
1324CONFIG_DEBUG_LL=y 1323CONFIG_DEBUG_LL=y
1325# CONFIG_DEBUG_ICEDCC is not set 1324# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig
index c48d17062262..9b6561d119af 100644
--- a/arch/arm/configs/shark_defconfig
+++ b/arch/arm/configs/shark_defconfig
@@ -965,7 +965,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
965# CONFIG_DEBUG_FS is not set 965# CONFIG_DEBUG_FS is not set
966CONFIG_FRAME_POINTER=y 966CONFIG_FRAME_POINTER=y
967CONFIG_DEBUG_USER=y 967CONFIG_DEBUG_USER=y
968# CONFIG_DEBUG_WAITQ is not set
969# CONFIG_DEBUG_ERRORS is not set 968# CONFIG_DEBUG_ERRORS is not set
970# CONFIG_DEBUG_LL is not set 969# CONFIG_DEBUG_LL is not set
971 970
diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig
index 140056a3507f..03f783e696b3 100644
--- a/arch/arm/configs/simpad_defconfig
+++ b/arch/arm/configs/simpad_defconfig
@@ -934,7 +934,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
934# CONFIG_DEBUG_FS is not set 934# CONFIG_DEBUG_FS is not set
935CONFIG_FRAME_POINTER=y 935CONFIG_FRAME_POINTER=y
936CONFIG_DEBUG_USER=y 936CONFIG_DEBUG_USER=y
937# CONFIG_DEBUG_WAITQ is not set
938CONFIG_DEBUG_ERRORS=y 937CONFIG_DEBUG_ERRORS=y
939CONFIG_DEBUG_LL=y 938CONFIG_DEBUG_LL=y
940# CONFIG_DEBUG_ICEDCC is not set 939# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index bd03238968c1..aa7a01179500 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -1406,7 +1406,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1406CONFIG_FRAME_POINTER=y 1406CONFIG_FRAME_POINTER=y
1407# CONFIG_RCU_TORTURE_TEST is not set 1407# CONFIG_RCU_TORTURE_TEST is not set
1408# CONFIG_DEBUG_USER is not set 1408# CONFIG_DEBUG_USER is not set
1409# CONFIG_DEBUG_WAITQ is not set
1410CONFIG_DEBUG_ERRORS=y 1409CONFIG_DEBUG_ERRORS=y
1411CONFIG_DEBUG_LL=y 1410CONFIG_DEBUG_LL=y
1412# CONFIG_DEBUG_ICEDCC is not set 1411# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index f7bf6ef27d19..48dca69addae 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -972,7 +972,6 @@ CONFIG_FRAME_POINTER=y
972CONFIG_FORCED_INLINING=y 972CONFIG_FORCED_INLINING=y
973# CONFIG_RCU_TORTURE_TEST is not set 973# CONFIG_RCU_TORTURE_TEST is not set
974CONFIG_DEBUG_USER=y 974CONFIG_DEBUG_USER=y
975# CONFIG_DEBUG_WAITQ is not set
976CONFIG_DEBUG_ERRORS=y 975CONFIG_DEBUG_ERRORS=y
977CONFIG_DEBUG_LL=y 976CONFIG_DEBUG_LL=y
978# CONFIG_DEBUG_ICEDCC is not set 977# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 1320a0efca73..ab06a86e85d5 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -24,7 +24,9 @@ obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o
24obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o 24obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
25AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 25AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
26 26
27obj-$(CONFIG_IWMMXT) += iwmmxt.o iwmmxt-notifier.o 27obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
28obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
29obj-$(CONFIG_IWMMXT) += iwmmxt.o
28AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt 30AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
29 31
30ifneq ($(CONFIG_ARCH_EBSA110),y) 32ifneq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/kernel/apm.c b/arch/arm/kernel/apm.c
index ecf4f9472d94..a11fb9a40c04 100644
--- a/arch/arm/kernel/apm.c
+++ b/arch/arm/kernel/apm.c
@@ -12,7 +12,6 @@
12 */ 12 */
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/poll.h> 14#include <linux/poll.h>
15#include <linux/timer.h>
16#include <linux/slab.h> 15#include <linux/slab.h>
17#include <linux/proc_fs.h> 16#include <linux/proc_fs.h>
18#include <linux/miscdevice.h> 17#include <linux/miscdevice.h>
@@ -26,6 +25,7 @@
26#include <linux/init.h> 25#include <linux/init.h>
27#include <linux/completion.h> 26#include <linux/completion.h>
28#include <linux/kthread.h> 27#include <linux/kthread.h>
28#include <linux/delay.h>
29 29
30#include <asm/apm.h> /* apm_power_info */ 30#include <asm/apm.h> /* apm_power_info */
31#include <asm/system.h> 31#include <asm/system.h>
@@ -71,7 +71,8 @@ struct apm_user {
71#define SUSPEND_PENDING 1 /* suspend pending read */ 71#define SUSPEND_PENDING 1 /* suspend pending read */
72#define SUSPEND_READ 2 /* suspend read, pending ack */ 72#define SUSPEND_READ 2 /* suspend read, pending ack */
73#define SUSPEND_ACKED 3 /* suspend acked */ 73#define SUSPEND_ACKED 3 /* suspend acked */
74#define SUSPEND_DONE 4 /* suspend completed */ 74#define SUSPEND_WAIT 4 /* waiting for suspend */
75#define SUSPEND_DONE 5 /* suspend completed */
75 76
76 struct apm_queue queue; 77 struct apm_queue queue;
77}; 78};
@@ -101,6 +102,7 @@ static DECLARE_WAIT_QUEUE_HEAD(kapmd_wait);
101static DEFINE_SPINLOCK(kapmd_queue_lock); 102static DEFINE_SPINLOCK(kapmd_queue_lock);
102static struct apm_queue kapmd_queue; 103static struct apm_queue kapmd_queue;
103 104
105static DEFINE_MUTEX(state_lock);
104 106
105static const char driver_version[] = "1.13"; /* no spaces */ 107static const char driver_version[] = "1.13"; /* no spaces */
106 108
@@ -148,38 +150,60 @@ static void queue_add_event(struct apm_queue *q, apm_event_t event)
148 q->events[q->event_head] = event; 150 q->events[q->event_head] = event;
149} 151}
150 152
151static void queue_event_one_user(struct apm_user *as, apm_event_t event) 153static void queue_event(apm_event_t event)
152{ 154{
153 if (as->suser && as->writer) { 155 struct apm_user *as;
154 switch (event) {
155 case APM_SYS_SUSPEND:
156 case APM_USER_SUSPEND:
157 /*
158 * If this user already has a suspend pending,
159 * don't queue another one.
160 */
161 if (as->suspend_state != SUSPEND_NONE)
162 return;
163 156
164 as->suspend_state = SUSPEND_PENDING; 157 down_read(&user_list_lock);
165 suspends_pending++; 158 list_for_each_entry(as, &apm_user_list, list) {
166 break; 159 if (as->reader)
167 } 160 queue_add_event(&as->queue, event);
168 } 161 }
169 queue_add_event(&as->queue, event); 162 up_read(&user_list_lock);
163 wake_up_interruptible(&apm_waitqueue);
170} 164}
171 165
172static void queue_event(apm_event_t event, struct apm_user *sender) 166/*
167 * queue_suspend_event - queue an APM suspend event.
168 *
169 * Check that we're in a state where we can suspend. If not,
170 * return -EBUSY. Otherwise, queue an event to all "writer"
171 * users. If there are no "writer" users, return '1' to
172 * indicate that we can immediately suspend.
173 */
174static int queue_suspend_event(apm_event_t event, struct apm_user *sender)
173{ 175{
174 struct apm_user *as; 176 struct apm_user *as;
177 int ret = 1;
175 178
179 mutex_lock(&state_lock);
176 down_read(&user_list_lock); 180 down_read(&user_list_lock);
181
182 /*
183 * If a thread is still processing, we can't suspend, so reject
184 * the request.
185 */
177 list_for_each_entry(as, &apm_user_list, list) { 186 list_for_each_entry(as, &apm_user_list, list) {
178 if (as != sender && as->reader) 187 if (as != sender && as->reader && as->writer && as->suser &&
179 queue_event_one_user(as, event); 188 as->suspend_state != SUSPEND_NONE) {
189 ret = -EBUSY;
190 goto out;
191 }
180 } 192 }
193
194 list_for_each_entry(as, &apm_user_list, list) {
195 if (as != sender && as->reader && as->writer && as->suser) {
196 as->suspend_state = SUSPEND_PENDING;
197 suspends_pending++;
198 queue_add_event(&as->queue, event);
199 ret = 0;
200 }
201 }
202 out:
181 up_read(&user_list_lock); 203 up_read(&user_list_lock);
204 mutex_unlock(&state_lock);
182 wake_up_interruptible(&apm_waitqueue); 205 wake_up_interruptible(&apm_waitqueue);
206 return ret;
183} 207}
184 208
185static void apm_suspend(void) 209static void apm_suspend(void)
@@ -191,17 +215,22 @@ static void apm_suspend(void)
191 * Anyone on the APM queues will think we're still suspended. 215 * Anyone on the APM queues will think we're still suspended.
192 * Send a message so everyone knows we're now awake again. 216 * Send a message so everyone knows we're now awake again.
193 */ 217 */
194 queue_event(APM_NORMAL_RESUME, NULL); 218 queue_event(APM_NORMAL_RESUME);
195 219
196 /* 220 /*
197 * Finally, wake up anyone who is sleeping on the suspend. 221 * Finally, wake up anyone who is sleeping on the suspend.
198 */ 222 */
223 mutex_lock(&state_lock);
199 down_read(&user_list_lock); 224 down_read(&user_list_lock);
200 list_for_each_entry(as, &apm_user_list, list) { 225 list_for_each_entry(as, &apm_user_list, list) {
201 as->suspend_result = err; 226 if (as->suspend_state == SUSPEND_WAIT ||
202 as->suspend_state = SUSPEND_DONE; 227 as->suspend_state == SUSPEND_ACKED) {
228 as->suspend_result = err;
229 as->suspend_state = SUSPEND_DONE;
230 }
203 } 231 }
204 up_read(&user_list_lock); 232 up_read(&user_list_lock);
233 mutex_unlock(&state_lock);
205 234
206 wake_up(&apm_suspend_waitqueue); 235 wake_up(&apm_suspend_waitqueue);
207} 236}
@@ -227,8 +256,11 @@ static ssize_t apm_read(struct file *fp, char __user *buf, size_t count, loff_t
227 if (copy_to_user(buf, &event, sizeof(event))) 256 if (copy_to_user(buf, &event, sizeof(event)))
228 break; 257 break;
229 258
230 if (event == APM_SYS_SUSPEND || event == APM_USER_SUSPEND) 259 mutex_lock(&state_lock);
260 if (as->suspend_state == SUSPEND_PENDING &&
261 (event == APM_SYS_SUSPEND || event == APM_USER_SUSPEND))
231 as->suspend_state = SUSPEND_READ; 262 as->suspend_state = SUSPEND_READ;
263 mutex_unlock(&state_lock);
232 264
233 buf += sizeof(event); 265 buf += sizeof(event);
234 i -= sizeof(event); 266 i -= sizeof(event);
@@ -270,9 +302,13 @@ apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
270 302
271 switch (cmd) { 303 switch (cmd) {
272 case APM_IOC_SUSPEND: 304 case APM_IOC_SUSPEND:
305 mutex_lock(&state_lock);
306
273 as->suspend_result = -EINTR; 307 as->suspend_result = -EINTR;
274 308
275 if (as->suspend_state == SUSPEND_READ) { 309 if (as->suspend_state == SUSPEND_READ) {
310 int pending;
311
276 /* 312 /*
277 * If we read a suspend command from /dev/apm_bios, 313 * If we read a suspend command from /dev/apm_bios,
278 * then the corresponding APM_IOC_SUSPEND ioctl is 314 * then the corresponding APM_IOC_SUSPEND ioctl is
@@ -280,47 +316,73 @@ apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
280 */ 316 */
281 as->suspend_state = SUSPEND_ACKED; 317 as->suspend_state = SUSPEND_ACKED;
282 suspends_pending--; 318 suspends_pending--;
319 pending = suspends_pending == 0;
320 mutex_unlock(&state_lock);
321
322 /*
323 * If there are no further acknowledges required,
324 * suspend the system.
325 */
326 if (pending)
327 apm_suspend();
328
329 /*
330 * Wait for the suspend/resume to complete. If there
331 * are pending acknowledges, we wait here for them.
332 *
333 * Note: we need to ensure that the PM subsystem does
334 * not kick us out of the wait when it suspends the
335 * threads.
336 */
337 flags = current->flags;
338 current->flags |= PF_NOFREEZE;
339
340 wait_event(apm_suspend_waitqueue,
341 as->suspend_state == SUSPEND_DONE);
283 } else { 342 } else {
343 as->suspend_state = SUSPEND_WAIT;
344 mutex_unlock(&state_lock);
345
284 /* 346 /*
285 * Otherwise it is a request to suspend the system. 347 * Otherwise it is a request to suspend the system.
286 * Queue an event for all readers, and expect an 348 * Queue an event for all readers, and expect an
287 * acknowledge from all writers who haven't already 349 * acknowledge from all writers who haven't already
288 * acknowledged. 350 * acknowledged.
289 */ 351 */
290 queue_event(APM_USER_SUSPEND, as); 352 err = queue_suspend_event(APM_USER_SUSPEND, as);
291 } 353 if (err < 0) {
292 354 /*
293 /* 355 * Avoid taking the lock here - this
294 * If there are no further acknowledges required, suspend 356 * should be fine.
295 * the system. 357 */
296 */ 358 as->suspend_state = SUSPEND_NONE;
297 if (suspends_pending == 0) 359 break;
298 apm_suspend(); 360 }
361
362 if (err > 0)
363 apm_suspend();
299 364
300 /* 365 /*
301 * Wait for the suspend/resume to complete. If there are 366 * Wait for the suspend/resume to complete. If there
302 * pending acknowledges, we wait here for them. 367 * are pending acknowledges, we wait here for them.
303 * 368 *
304 * Note that we need to ensure that the PM subsystem does 369 * Note: we need to ensure that the PM subsystem does
305 * not kick us out of the wait when it suspends the threads. 370 * not kick us out of the wait when it suspends the
306 */ 371 * threads.
307 flags = current->flags; 372 */
308 current->flags |= PF_NOFREEZE; 373 flags = current->flags;
374 current->flags |= PF_NOFREEZE;
309 375
310 /*
311 * Note: do not allow a thread which is acking the suspend
312 * to escape until the resume is complete.
313 */
314 if (as->suspend_state == SUSPEND_ACKED)
315 wait_event(apm_suspend_waitqueue,
316 as->suspend_state == SUSPEND_DONE);
317 else
318 wait_event_interruptible(apm_suspend_waitqueue, 376 wait_event_interruptible(apm_suspend_waitqueue,
319 as->suspend_state == SUSPEND_DONE); 377 as->suspend_state == SUSPEND_DONE);
378 }
320 379
321 current->flags = flags; 380 current->flags = flags;
381
382 mutex_lock(&state_lock);
322 err = as->suspend_result; 383 err = as->suspend_result;
323 as->suspend_state = SUSPEND_NONE; 384 as->suspend_state = SUSPEND_NONE;
385 mutex_unlock(&state_lock);
324 break; 386 break;
325 } 387 }
326 388
@@ -330,6 +392,8 @@ apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
330static int apm_release(struct inode * inode, struct file * filp) 392static int apm_release(struct inode * inode, struct file * filp)
331{ 393{
332 struct apm_user *as = filp->private_data; 394 struct apm_user *as = filp->private_data;
395 int pending = 0;
396
333 filp->private_data = NULL; 397 filp->private_data = NULL;
334 398
335 down_write(&user_list_lock); 399 down_write(&user_list_lock);
@@ -342,11 +406,14 @@ static int apm_release(struct inode * inode, struct file * filp)
342 * need to balance suspends_pending, which means the 406 * need to balance suspends_pending, which means the
343 * possibility of sleeping. 407 * possibility of sleeping.
344 */ 408 */
409 mutex_lock(&state_lock);
345 if (as->suspend_state != SUSPEND_NONE) { 410 if (as->suspend_state != SUSPEND_NONE) {
346 suspends_pending -= 1; 411 suspends_pending -= 1;
347 if (suspends_pending == 0) 412 pending = suspends_pending == 0;
348 apm_suspend();
349 } 413 }
414 mutex_unlock(&state_lock);
415 if (pending)
416 apm_suspend();
350 417
351 kfree(as); 418 kfree(as);
352 return 0; 419 return 0;
@@ -470,6 +537,7 @@ static int kapmd(void *arg)
470{ 537{
471 do { 538 do {
472 apm_event_t event; 539 apm_event_t event;
540 int ret;
473 541
474 wait_event_interruptible(kapmd_wait, 542 wait_event_interruptible(kapmd_wait,
475 !queue_empty(&kapmd_queue) || kthread_should_stop()); 543 !queue_empty(&kapmd_queue) || kthread_should_stop());
@@ -489,13 +557,20 @@ static int kapmd(void *arg)
489 557
490 case APM_LOW_BATTERY: 558 case APM_LOW_BATTERY:
491 case APM_POWER_STATUS_CHANGE: 559 case APM_POWER_STATUS_CHANGE:
492 queue_event(event, NULL); 560 queue_event(event);
493 break; 561 break;
494 562
495 case APM_USER_SUSPEND: 563 case APM_USER_SUSPEND:
496 case APM_SYS_SUSPEND: 564 case APM_SYS_SUSPEND:
497 queue_event(event, NULL); 565 ret = queue_suspend_event(event, NULL);
498 if (suspends_pending == 0) 566 if (ret < 0) {
567 /*
568 * We were busy. Try again in 50ms.
569 */
570 queue_add_event(&kapmd_queue, event);
571 msleep(50);
572 }
573 if (ret > 0)
499 apm_suspend(); 574 apm_suspend();
500 break; 575 break;
501 576
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index cc2d58d028e1..3c078e346753 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -15,6 +15,7 @@
15#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
16#include <asm/thread_info.h> 16#include <asm/thread_info.h>
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <asm/procinfo.h>
18 19
19/* 20/*
20 * Make sure that the compiler and target are compatible. 21 * Make sure that the compiler and target are compatible.
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index b27513a0f11e..a786f769035d 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -529,7 +529,7 @@ static void ecard_dump_irq_state(void)
529 } 529 }
530} 530}
531 531
532static void ecard_check_lockup(struct irqdesc *desc) 532static void ecard_check_lockup(struct irq_desc *desc)
533{ 533{
534 static unsigned long last; 534 static unsigned long last;
535 static int lockup; 535 static int lockup;
@@ -567,7 +567,7 @@ static void ecard_check_lockup(struct irqdesc *desc)
567} 567}
568 568
569static void 569static void
570ecard_irq_handler(unsigned int irq, struct irqdesc *desc) 570ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
571{ 571{
572 ecard_t *ec; 572 ecard_t *ec;
573 int called = 0; 573 int called = 0;
@@ -585,7 +585,7 @@ ecard_irq_handler(unsigned int irq, struct irqdesc *desc)
585 pending = ecard_default_ops.irqpending(ec); 585 pending = ecard_default_ops.irqpending(ec);
586 586
587 if (pending) { 587 if (pending) {
588 struct irqdesc *d = irq_desc + ec->irq; 588 struct irq_desc *d = irq_desc + ec->irq;
589 desc_handle_irq(ec->irq, d); 589 desc_handle_irq(ec->irq, d);
590 called ++; 590 called ++;
591 } 591 }
@@ -609,7 +609,7 @@ static unsigned char first_set[] =
609}; 609};
610 610
611static void 611static void
612ecard_irqexp_handler(unsigned int irq, struct irqdesc *desc) 612ecard_irqexp_handler(unsigned int irq, struct irq_desc *desc)
613{ 613{
614 const unsigned int statusmask = 15; 614 const unsigned int statusmask = 15;
615 unsigned int status; 615 unsigned int status;
@@ -1022,7 +1022,7 @@ ecard_probe(int slot, card_type_t type)
1022 if (slot < 8) { 1022 if (slot < 8) {
1023 ec->irq = 32 + slot; 1023 ec->irq = 32 + slot;
1024 set_irq_chip(ec->irq, &ecard_chip); 1024 set_irq_chip(ec->irq, &ecard_chip);
1025 set_irq_handler(ec->irq, do_level_IRQ); 1025 set_irq_handler(ec->irq, handle_level_irq);
1026 set_irq_flags(ec->irq, IRQF_VALID); 1026 set_irq_flags(ec->irq, IRQF_VALID);
1027 } 1027 }
1028 1028
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bd623b73445f..2db42b18f53f 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -589,10 +589,6 @@ ENTRY(__switch_to)
589 strex r5, r4, [ip] @ Clear exclusive monitor 589 strex r5, r4, [ip] @ Clear exclusive monitor
590#endif 590#endif
591#endif 591#endif
592#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
593 mra r4, r5, acc0
594 stmia ip, {r4, r5}
595#endif
596#if defined(CONFIG_HAS_TLS_REG) 592#if defined(CONFIG_HAS_TLS_REG)
597 mcr p15, 0, r3, c13, c0, 3 @ set TLS register 593 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
598#elif !defined(CONFIG_TLS_REG_EMUL) 594#elif !defined(CONFIG_TLS_REG_EMUL)
@@ -602,11 +598,6 @@ ENTRY(__switch_to)
602#ifdef CONFIG_MMU 598#ifdef CONFIG_MMU
603 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 599 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
604#endif 600#endif
605#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
606 add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra
607 ldmib r4, {r4, r5}
608 mar acc0, r4, r5
609#endif
610 mov r5, r0 601 mov r5, r0
611 add r4, r2, #TI_CPU_SAVE 602 add r4, r2, #TI_CPU_SAVE
612 ldr r0, =thread_notify_head 603 ldr r0, =thread_notify_head
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index f359a189dcf2..0119c0d5f978 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -16,7 +16,6 @@
16 16
17#include <asm/assembler.h> 17#include <asm/assembler.h>
18#include <asm/mach-types.h> 18#include <asm/mach-types.h>
19#include <asm/procinfo.h>
20#include <asm/ptrace.h> 19#include <asm/ptrace.h>
21#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
22#include <asm/thread_info.h> 21#include <asm/thread_info.h>
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index ebc3e74a7947..bda0748ffb00 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -16,7 +16,6 @@
16 16
17#include <asm/assembler.h> 17#include <asm/assembler.h>
18#include <asm/domain.h> 18#include <asm/domain.h>
19#include <asm/procinfo.h>
20#include <asm/ptrace.h> 19#include <asm/ptrace.h>
21#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
22#include <asm/memory.h> 21#include <asm/memory.h>
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 2c4ff1cbe334..ec01f08f5642 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -112,7 +112,7 @@ static struct irq_desc bad_irq_desc = {
112asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) 112asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
113{ 113{
114 struct pt_regs *old_regs = set_irq_regs(regs); 114 struct pt_regs *old_regs = set_irq_regs(regs);
115 struct irqdesc *desc = irq_desc + irq; 115 struct irq_desc *desc = irq_desc + irq;
116 116
117 /* 117 /*
118 * Some hardware gives randomly wrong interrupts. Rather 118 * Some hardware gives randomly wrong interrupts. Rather
@@ -134,7 +134,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
134 134
135void set_irq_flags(unsigned int irq, unsigned int iflags) 135void set_irq_flags(unsigned int irq, unsigned int iflags)
136{ 136{
137 struct irqdesc *desc; 137 struct irq_desc *desc;
138 unsigned long flags; 138 unsigned long flags;
139 139
140 if (irq >= NR_IRQS) { 140 if (irq >= NR_IRQS) {
@@ -171,7 +171,7 @@ void __init init_IRQ(void)
171 171
172#ifdef CONFIG_HOTPLUG_CPU 172#ifdef CONFIG_HOTPLUG_CPU
173 173
174static void route_irq(struct irqdesc *desc, unsigned int irq, unsigned int cpu) 174static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
175{ 175{
176 pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu); 176 pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu);
177 177
@@ -190,7 +190,7 @@ void migrate_irqs(void)
190 unsigned int i, cpu = smp_processor_id(); 190 unsigned int i, cpu = smp_processor_id();
191 191
192 for (i = 0; i < NR_IRQS; i++) { 192 for (i = 0; i < NR_IRQS; i++) {
193 struct irqdesc *desc = irq_desc + i; 193 struct irq_desc *desc = irq_desc + i;
194 194
195 if (desc->cpu == cpu) { 195 if (desc->cpu == cpu) {
196 unsigned int newcpu = any_online_cpu(desc->affinity); 196 unsigned int newcpu = any_online_cpu(desc->affinity);
diff --git a/arch/arm/kernel/iwmmxt-notifier.c b/arch/arm/kernel/iwmmxt-notifier.c
deleted file mode 100644
index 0d1a1db40062..000000000000
--- a/arch/arm/kernel/iwmmxt-notifier.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * linux/arch/arm/kernel/iwmmxt-notifier.c
3 *
4 * XScale iWMMXt (Concan) context switching and handling
5 *
6 * Initial code:
7 * Copyright (c) 2003, Intel Corporation
8 *
9 * Full lazy switching support, optimizations and more, by Nicolas Pitre
10 * Copyright (c) 2003-2004, MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/module.h>
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/signal.h>
21#include <linux/sched.h>
22#include <linux/init.h>
23#include <asm/thread_notify.h>
24#include <asm/io.h>
25
26static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
27{
28 struct thread_info *thread = t;
29
30 switch (cmd) {
31 case THREAD_NOTIFY_FLUSH:
32 /*
33 * flush_thread() zeroes thread->fpstate, so no need
34 * to do anything here.
35 *
36 * FALLTHROUGH: Ensure we don't try to overwrite our newly
37 * initialised state information on the first fault.
38 */
39
40 case THREAD_NOTIFY_RELEASE:
41 iwmmxt_task_release(thread);
42 break;
43
44 case THREAD_NOTIFY_SWITCH:
45 iwmmxt_task_switch(thread);
46 break;
47 }
48
49 return NOTIFY_DONE;
50}
51
52static struct notifier_block iwmmxt_notifier_block = {
53 .notifier_call = iwmmxt_do,
54};
55
56static int __init iwmmxt_init(void)
57{
58 thread_register_notifier(&iwmmxt_notifier_block);
59
60 return 0;
61}
62
63late_initcall(iwmmxt_init);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index bf35c178a877..a9e8f7e55fd6 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -281,67 +281,6 @@ void show_fpregs(struct user_fp *regs)
281} 281}
282 282
283/* 283/*
284 * Task structure and kernel stack allocation.
285 */
286struct thread_info_list {
287 unsigned long *head;
288 unsigned int nr;
289};
290
291static DEFINE_PER_CPU(struct thread_info_list, thread_info_list) = { NULL, 0 };
292
293#define EXTRA_TASK_STRUCT 4
294
295struct thread_info *alloc_thread_info(struct task_struct *task)
296{
297 struct thread_info *thread = NULL;
298
299 if (EXTRA_TASK_STRUCT) {
300 struct thread_info_list *th = &get_cpu_var(thread_info_list);
301 unsigned long *p = th->head;
302
303 if (p) {
304 th->head = (unsigned long *)p[0];
305 th->nr -= 1;
306 }
307 put_cpu_var(thread_info_list);
308
309 thread = (struct thread_info *)p;
310 }
311
312 if (!thread)
313 thread = (struct thread_info *)
314 __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER);
315
316#ifdef CONFIG_DEBUG_STACK_USAGE
317 /*
318 * The stack must be cleared if you want SYSRQ-T to
319 * give sensible stack usage information
320 */
321 if (thread)
322 memzero(thread, THREAD_SIZE);
323#endif
324 return thread;
325}
326
327void free_thread_info(struct thread_info *thread)
328{
329 if (EXTRA_TASK_STRUCT) {
330 struct thread_info_list *th = &get_cpu_var(thread_info_list);
331 if (th->nr < EXTRA_TASK_STRUCT) {
332 unsigned long *p = (unsigned long *)thread;
333 p[0] = (unsigned long)th->head;
334 th->head = p;
335 th->nr += 1;
336 put_cpu_var(thread_info_list);
337 return;
338 }
339 put_cpu_var(thread_info_list);
340 }
341 free_pages((unsigned long)thread, THREAD_SIZE_ORDER);
342}
343
344/*
345 * Free current thread data structures etc.. 284 * Free current thread data structures etc..
346 */ 285 */
347void exit_thread(void) 286void exit_thread(void)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 29efc9f82057..238dd9b6db84 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -357,9 +357,6 @@ static void __init setup_processor(void)
357#ifndef CONFIG_VFP 357#ifndef CONFIG_VFP
358 elf_hwcap &= ~HWCAP_VFP; 358 elf_hwcap &= ~HWCAP_VFP;
359#endif 359#endif
360#ifndef CONFIG_IWMMXT
361 elf_hwcap &= ~HWCAP_IWMMXT;
362#endif
363 360
364 cpu_proc_init(); 361 cpu_proc_init();
365} 362}
@@ -441,16 +438,19 @@ __early_param("initrd=", early_initrd);
441 438
442static void __init arm_add_memory(unsigned long start, unsigned long size) 439static void __init arm_add_memory(unsigned long start, unsigned long size)
443{ 440{
441 struct membank *bank;
442
444 /* 443 /*
445 * Ensure that start/size are aligned to a page boundary. 444 * Ensure that start/size are aligned to a page boundary.
446 * Size is appropriately rounded down, start is rounded up. 445 * Size is appropriately rounded down, start is rounded up.
447 */ 446 */
448 size -= start & ~PAGE_MASK; 447 size -= start & ~PAGE_MASK;
449 448
450 meminfo.bank[meminfo.nr_banks].start = PAGE_ALIGN(start); 449 bank = &meminfo.bank[meminfo.nr_banks++];
451 meminfo.bank[meminfo.nr_banks].size = size & PAGE_MASK; 450
452 meminfo.bank[meminfo.nr_banks].node = PHYS_TO_NID(start); 451 bank->start = PAGE_ALIGN(start);
453 meminfo.nr_banks += 1; 452 bank->size = size & PAGE_MASK;
453 bank->node = PHYS_TO_NID(start);
454} 454}
455 455
456/* 456/*
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 48cf7fffddf2..f2b1d61fbc0e 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -12,6 +12,7 @@
12#include <linux/ptrace.h> 12#include <linux/ptrace.h>
13#include <linux/personality.h> 13#include <linux/personality.h>
14 14
15#include <asm/elf.h>
15#include <asm/cacheflush.h> 16#include <asm/cacheflush.h>
16#include <asm/ucontext.h> 17#include <asm/ucontext.h>
17#include <asm/uaccess.h> 18#include <asm/uaccess.h>
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index bede380c07a9..042a12982e98 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -631,12 +631,9 @@ baddataabort(int code, unsigned long instr, struct pt_regs *regs)
631 notify_die("unknown data abort code", regs, &info, instr, 0); 631 notify_die("unknown data abort code", regs, &info, instr, 0);
632} 632}
633 633
634void __attribute__((noreturn)) __bug(const char *file, int line, void *data) 634void __attribute__((noreturn)) __bug(const char *file, int line)
635{ 635{
636 printk(KERN_CRIT"kernel BUG at %s:%d!", file, line); 636 printk(KERN_CRIT"kernel BUG at %s:%d!\n", file, line);
637 if (data)
638 printk(" - extra data = %p", data);
639 printk("\n");
640 *(int *)0 = 0; 637 *(int *)0 = 0;
641 638
642 /* Avoid "noreturn function does return" */ 639 /* Avoid "noreturn function does return" */
diff --git a/arch/arm/kernel/xscale-cp0.c b/arch/arm/kernel/xscale-cp0.c
new file mode 100644
index 000000000000..180000bfdc8f
--- /dev/null
+++ b/arch/arm/kernel/xscale-cp0.c
@@ -0,0 +1,179 @@
1/*
2 * linux/arch/arm/kernel/xscale-cp0.c
3 *
4 * XScale DSP and iWMMXt coprocessor context switching and handling
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/types.h>
13#include <linux/kernel.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/init.h>
17#include <asm/thread_notify.h>
18#include <asm/io.h>
19
20static inline void dsp_save_state(u32 *state)
21{
22 __asm__ __volatile__ (
23 "mrrc p0, 0, %0, %1, c0\n"
24 : "=r" (state[0]), "=r" (state[1]));
25}
26
27static inline void dsp_load_state(u32 *state)
28{
29 __asm__ __volatile__ (
30 "mcrr p0, 0, %0, %1, c0\n"
31 : : "r" (state[0]), "r" (state[1]));
32}
33
34static int dsp_do(struct notifier_block *self, unsigned long cmd, void *t)
35{
36 struct thread_info *thread = t;
37
38 switch (cmd) {
39 case THREAD_NOTIFY_FLUSH:
40 thread->cpu_context.extra[0] = 0;
41 thread->cpu_context.extra[1] = 0;
42 break;
43
44 case THREAD_NOTIFY_SWITCH:
45 dsp_save_state(current_thread_info()->cpu_context.extra);
46 dsp_load_state(thread->cpu_context.extra);
47 break;
48 }
49
50 return NOTIFY_DONE;
51}
52
53static struct notifier_block dsp_notifier_block = {
54 .notifier_call = dsp_do,
55};
56
57
58#ifdef CONFIG_IWMMXT
59static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
60{
61 struct thread_info *thread = t;
62
63 switch (cmd) {
64 case THREAD_NOTIFY_FLUSH:
65 /*
66 * flush_thread() zeroes thread->fpstate, so no need
67 * to do anything here.
68 *
69 * FALLTHROUGH: Ensure we don't try to overwrite our newly
70 * initialised state information on the first fault.
71 */
72
73 case THREAD_NOTIFY_RELEASE:
74 iwmmxt_task_release(thread);
75 break;
76
77 case THREAD_NOTIFY_SWITCH:
78 iwmmxt_task_switch(thread);
79 break;
80 }
81
82 return NOTIFY_DONE;
83}
84
85static struct notifier_block iwmmxt_notifier_block = {
86 .notifier_call = iwmmxt_do,
87};
88#endif
89
90
91static u32 __init xscale_cp_access_read(void)
92{
93 u32 value;
94
95 __asm__ __volatile__ (
96 "mrc p15, 0, %0, c15, c1, 0\n\t"
97 : "=r" (value));
98
99 return value;
100}
101
102static void __init xscale_cp_access_write(u32 value)
103{
104 u32 temp;
105
106 __asm__ __volatile__ (
107 "mcr p15, 0, %1, c15, c1, 0\n\t"
108 "mrc p15, 0, %0, c15, c1, 0\n\t"
109 "mov %0, %0\n\t"
110 "sub pc, pc, #4\n\t"
111 : "=r" (temp) : "r" (value));
112}
113
114/*
115 * Detect whether we have a MAC coprocessor (40 bit register) or an
116 * iWMMXt coprocessor (64 bit registers) by loading 00000100:00000000
117 * into a coprocessor register and reading it back, and checking
118 * whether the upper word survived intact.
119 */
120static int __init cpu_has_iwmmxt(void)
121{
122 u32 lo;
123 u32 hi;
124
125 /*
126 * This sequence is interpreted by the DSP coprocessor as:
127 * mar acc0, %2, %3
128 * mra %0, %1, acc0
129 *
130 * And by the iWMMXt coprocessor as:
131 * tmcrr wR0, %2, %3
132 * tmrrc %0, %1, wR0
133 */
134 __asm__ __volatile__ (
135 "mcrr p0, 0, %2, %3, c0\n"
136 "mrrc p0, 0, %0, %1, c0\n"
137 : "=r" (lo), "=r" (hi)
138 : "r" (0), "r" (0x100));
139
140 return !!hi;
141}
142
143
144/*
145 * If we detect that the CPU has iWMMXt (and CONFIG_IWMMXT=y), we
146 * disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
147 * switch code handle iWMMXt context switching. If on the other
148 * hand the CPU has a DSP coprocessor, we keep access to CP0 enabled
149 * all the time, and save/restore acc0 on context switch in non-lazy
150 * fashion.
151 */
152static int __init xscale_cp0_init(void)
153{
154 u32 cp_access;
155
156 cp_access = xscale_cp_access_read() & ~3;
157 xscale_cp_access_write(cp_access | 1);
158
159 if (cpu_has_iwmmxt()) {
160#ifndef CONFIG_IWMMXT
161 printk(KERN_WARNING "CAUTION: XScale iWMMXt coprocessor "
162 "detected, but kernel support is missing.\n");
163#else
164 printk(KERN_INFO "XScale iWMMXt coprocessor detected.\n");
165 elf_hwcap |= HWCAP_IWMMXT;
166 thread_register_notifier(&iwmmxt_notifier_block);
167#endif
168 } else {
169 printk(KERN_INFO "XScale DSP coprocessor detected.\n");
170 thread_register_notifier(&dsp_notifier_block);
171 cp_access |= 1;
172 }
173
174 xscale_cp_access_write(cp_access);
175
176 return 0;
177}
178
179late_initcall(xscale_cp0_init);
diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c
index fe3d297d682d..a950160fcfb6 100644
--- a/arch/arm/mach-aaec2000/core.c
+++ b/arch/arm/mach-aaec2000/core.c
@@ -82,7 +82,7 @@ static void aaec2000_int_unmask(unsigned int irq)
82 IRQ_INTENS |= (1 << irq); 82 IRQ_INTENS |= (1 << irq);
83} 83}
84 84
85static struct irqchip aaec2000_irq_chip = { 85static struct irq_chip aaec2000_irq_chip = {
86 .ack = aaec2000_int_ack, 86 .ack = aaec2000_int_ack,
87 .mask = aaec2000_int_mask, 87 .mask = aaec2000_int_mask,
88 .unmask = aaec2000_int_unmask, 88 .unmask = aaec2000_int_unmask,
@@ -93,7 +93,7 @@ void __init aaec2000_init_irq(void)
93 unsigned int i; 93 unsigned int i;
94 94
95 for (i = 0; i < NR_IRQS; i++) { 95 for (i = 0; i < NR_IRQS; i++) {
96 set_irq_handler(i, do_level_IRQ); 96 set_irq_handler(i, handle_level_irq);
97 set_irq_chip(i, &aaec2000_irq_chip); 97 set_irq_chip(i, &aaec2000_irq_chip);
98 set_irq_flags(i, IRQF_VALID); 98 set_irq_flags(i, IRQF_VALID);
99 } 99 }
diff --git a/arch/arm/mach-at91rm9200/Kconfig b/arch/arm/mach-at91rm9200/Kconfig
index 2f85e8693b1b..9f11db8af233 100644
--- a/arch/arm/mach-at91rm9200/Kconfig
+++ b/arch/arm/mach-at91rm9200/Kconfig
@@ -2,7 +2,8 @@ if ARCH_AT91
2 2
3menu "Atmel AT91 System-on-Chip" 3menu "Atmel AT91 System-on-Chip"
4 4
5comment "Atmel AT91 Processors" 5choice
6 prompt "Atmel AT91 Processor"
6 7
7config ARCH_AT91RM9200 8config ARCH_AT91RM9200
8 bool "AT91RM9200" 9 bool "AT91RM9200"
@@ -13,6 +14,8 @@ config ARCH_AT91SAM9260
13config ARCH_AT91SAM9261 14config ARCH_AT91SAM9261
14 bool "AT91SAM9261" 15 bool "AT91SAM9261"
15 16
17endchoice
18
16# ---------------------------------------------------------- 19# ----------------------------------------------------------
17 20
18if ARCH_AT91RM9200 21if ARCH_AT91RM9200
@@ -33,7 +36,6 @@ config ARCH_AT91RM9200DK
33 Select this if you are using Atmel's AT91RM9200-DK Development board. 36 Select this if you are using Atmel's AT91RM9200-DK Development board.
34 (Discontinued) 37 (Discontinued)
35 38
36
37config MACH_AT91RM9200EK 39config MACH_AT91RM9200EK
38 bool "Atmel AT91RM9200-EK Evaluation Kit" 40 bool "Atmel AT91RM9200-EK Evaluation Kit"
39 depends on ARCH_AT91RM9200 41 depends on ARCH_AT91RM9200
@@ -90,6 +92,13 @@ if ARCH_AT91SAM9260
90 92
91comment "AT91SAM9260 Board Type" 93comment "AT91SAM9260 Board Type"
92 94
95config MACH_AT91SAM9260EK
96 bool "Atmel AT91SAM9260-EK Evaluation Kit"
97 depends on ARCH_AT91SAM9260
98 help
99 Select this if you are using Atmel's AT91SAM9260-EK Evaluation Kit.
100 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
101
93endif 102endif
94 103
95# ---------------------------------------------------------- 104# ----------------------------------------------------------
@@ -98,8 +107,31 @@ if ARCH_AT91SAM9261
98 107
99comment "AT91SAM9261 Board Type" 108comment "AT91SAM9261 Board Type"
100 109
110config MACH_AT91SAM9261EK
111 bool "Atmel AT91SAM9261-EK Evaluation Kit"
112 depends on ARCH_AT91SAM9261
113 help
114 Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
115 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
116
101endif 117endif
102 118
119# ----------------------------------------------------------
120
121comment "AT91 Board Options"
122
123config MTD_AT91_DATAFLASH_CARD
124 bool "Enable DataFlash Card support"
125 depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK)
126 help
127 Enable support for the DataFlash card.
128
129config MTD_NAND_AT91_BUSWIDTH_16
130 bool "Enable 16-bit data bus interface to NAND flash"
131 depends on (MACH_AT91SAM9261EK || MACH_AT91SAM9260EK)
132 help
133 On AT91SAM926x boards both types of NAND flash can be present
134 (8 and 16 bit data bus width).
103 135
104# ---------------------------------------------------------- 136# ----------------------------------------------------------
105 137
diff --git a/arch/arm/mach-at91rm9200/Makefile b/arch/arm/mach-at91rm9200/Makefile
index c174805c24e5..cf777007847a 100644
--- a/arch/arm/mach-at91rm9200/Makefile
+++ b/arch/arm/mach-at91rm9200/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := clock.o irq.o gpio.o devices.o 5obj-y := clock.o irq.o gpio.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
@@ -10,11 +10,11 @@ obj- :=
10obj-$(CONFIG_PM) += pm.o 10obj-$(CONFIG_PM) += pm.o
11 11
12# CPU-specific support 12# CPU-specific support
13obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o 13obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
14obj-$(CONFIG_ARCH_AT91SAM9260) += 14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
15obj-$(CONFIG_ARCH_AT91SAM9261) += 15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
16 16
17# AT91RM9200 Board-specific support 17# AT91RM9200 board-specific support
18obj-$(CONFIG_MACH_ONEARM) += board-1arm.o 18obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
19obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o 19obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o
20obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o 20obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o
@@ -26,8 +26,10 @@ obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o
26obj-$(CONFIG_MACH_KAFA) += board-kafa.o 26obj-$(CONFIG_MACH_KAFA) += board-kafa.o
27 27
28# AT91SAM9260 board-specific support 28# AT91SAM9260 board-specific support
29obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
29 30
30# AT91SAM9261 board-specific support 31# AT91SAM9261 board-specific support
32obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
31 33
32# LEDs support 34# LEDs support
33led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o 35led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o
diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c
index dcf6136fedf9..a92e9a495b07 100644
--- a/arch/arm/mach-at91rm9200/at91rm9200.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200.c
@@ -14,8 +14,10 @@
14 14
15#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
16#include <asm/mach/map.h> 16#include <asm/mach/map.h>
17#include <asm/arch/at91rm9200.h>
18#include <asm/arch/at91_pmc.h>
19#include <asm/arch/at91_st.h>
17 20
18#include <asm/hardware.h>
19#include "generic.h" 21#include "generic.h"
20#include "clock.h" 22#include "clock.h"
21 23
@@ -26,32 +28,12 @@ static struct map_desc at91rm9200_io_desc[] __initdata = {
26 .length = SZ_4K, 28 .length = SZ_4K,
27 .type = MT_DEVICE, 29 .type = MT_DEVICE,
28 }, { 30 }, {
29 .virtual = AT91_VA_BASE_SPI,
30 .pfn = __phys_to_pfn(AT91RM9200_BASE_SPI),
31 .length = SZ_16K,
32 .type = MT_DEVICE,
33 }, {
34 .virtual = AT91_VA_BASE_EMAC, 31 .virtual = AT91_VA_BASE_EMAC,
35 .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), 32 .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC),
36 .length = SZ_16K, 33 .length = SZ_16K,
37 .type = MT_DEVICE, 34 .type = MT_DEVICE,
38 }, { 35 }, {
39 .virtual = AT91_VA_BASE_TWI, 36 .virtual = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE,
40 .pfn = __phys_to_pfn(AT91RM9200_BASE_TWI),
41 .length = SZ_16K,
42 .type = MT_DEVICE,
43 }, {
44 .virtual = AT91_VA_BASE_MCI,
45 .pfn = __phys_to_pfn(AT91RM9200_BASE_MCI),
46 .length = SZ_16K,
47 .type = MT_DEVICE,
48 }, {
49 .virtual = AT91_VA_BASE_UDP,
50 .pfn = __phys_to_pfn(AT91RM9200_BASE_UDP),
51 .length = SZ_16K,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = AT91_SRAM_VIRT_BASE,
55 .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE), 37 .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE),
56 .length = AT91RM9200_SRAM_SIZE, 38 .length = AT91RM9200_SRAM_SIZE,
57 .type = MT_DEVICE, 39 .type = MT_DEVICE,
@@ -222,6 +204,16 @@ static struct at91_gpio_bank at91rm9200_gpio[] = {
222 } 204 }
223}; 205};
224 206
207static void at91rm9200_reset(void)
208{
209 /*
210 * Perform a hardware reset with the use of the Watchdog timer.
211 */
212 at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
213 at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
214}
215
216
225/* -------------------------------------------------------------------- 217/* --------------------------------------------------------------------
226 * AT91RM9200 processor initialization 218 * AT91RM9200 processor initialization
227 * -------------------------------------------------------------------- */ 219 * -------------------------------------------------------------------- */
@@ -230,6 +222,12 @@ void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks
230 /* Map peripherals */ 222 /* Map peripherals */
231 iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); 223 iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
232 224
225 at91_arch_reset = at91rm9200_reset;
226 at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
227 | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
228 | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
229 | (1 << AT91RM9200_ID_IRQ6);
230
233 /* Init clock subsystem */ 231 /* Init clock subsystem */
234 at91_clock_init(main_clock); 232 at91_clock_init(main_clock);
235 233
diff --git a/arch/arm/mach-at91rm9200/devices.c b/arch/arm/mach-at91rm9200/at91rm9200_devices.c
index 059824376629..4641b99db0ee 100644
--- a/arch/arm/mach-at91rm9200/devices.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200_devices.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-at91rm9200/devices.c 2 * arch/arm/mach-at91rm9200/at91rm9200_devices.c
3 * 3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org> 4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell 5 * Copyright (C) 2005 David Brownell
@@ -15,9 +15,10 @@
15 15
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17 17
18#include <asm/hardware.h>
19#include <asm/arch/board.h> 18#include <asm/arch/board.h>
20#include <asm/arch/gpio.h> 19#include <asm/arch/gpio.h>
20#include <asm/arch/at91rm9200.h>
21#include <asm/arch/at91rm9200_mc.h>
21 22
22#include "generic.h" 23#include "generic.h"
23 24
@@ -33,7 +34,7 @@
33static u64 ohci_dmamask = 0xffffffffUL; 34static u64 ohci_dmamask = 0xffffffffUL;
34static struct at91_usbh_data usbh_data; 35static struct at91_usbh_data usbh_data;
35 36
36static struct resource at91_usbh_resources[] = { 37static struct resource usbh_resources[] = {
37 [0] = { 38 [0] = {
38 .start = AT91RM9200_UHP_BASE, 39 .start = AT91RM9200_UHP_BASE,
39 .end = AT91RM9200_UHP_BASE + SZ_1M - 1, 40 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
@@ -54,8 +55,8 @@ static struct platform_device at91rm9200_usbh_device = {
54 .coherent_dma_mask = 0xffffffff, 55 .coherent_dma_mask = 0xffffffff,
55 .platform_data = &usbh_data, 56 .platform_data = &usbh_data,
56 }, 57 },
57 .resource = at91_usbh_resources, 58 .resource = usbh_resources,
58 .num_resources = ARRAY_SIZE(at91_usbh_resources), 59 .num_resources = ARRAY_SIZE(usbh_resources),
59}; 60};
60 61
61void __init at91_add_device_usbh(struct at91_usbh_data *data) 62void __init at91_add_device_usbh(struct at91_usbh_data *data)
@@ -78,7 +79,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
78#ifdef CONFIG_USB_GADGET_AT91 79#ifdef CONFIG_USB_GADGET_AT91
79static struct at91_udc_data udc_data; 80static struct at91_udc_data udc_data;
80 81
81static struct resource at91_udc_resources[] = { 82static struct resource udc_resources[] = {
82 [0] = { 83 [0] = {
83 .start = AT91RM9200_BASE_UDP, 84 .start = AT91RM9200_BASE_UDP,
84 .end = AT91RM9200_BASE_UDP + SZ_16K - 1, 85 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
@@ -97,8 +98,8 @@ static struct platform_device at91rm9200_udc_device = {
97 .dev = { 98 .dev = {
98 .platform_data = &udc_data, 99 .platform_data = &udc_data,
99 }, 100 },
100 .resource = at91_udc_resources, 101 .resource = udc_resources,
101 .num_resources = ARRAY_SIZE(at91_udc_resources), 102 .num_resources = ARRAY_SIZE(udc_resources),
102}; 103};
103 104
104void __init at91_add_device_udc(struct at91_udc_data *data) 105void __init at91_add_device_udc(struct at91_udc_data *data)
@@ -129,7 +130,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {}
129static u64 eth_dmamask = 0xffffffffUL; 130static u64 eth_dmamask = 0xffffffffUL;
130static struct at91_eth_data eth_data; 131static struct at91_eth_data eth_data;
131 132
132static struct resource at91_eth_resources[] = { 133static struct resource eth_resources[] = {
133 [0] = { 134 [0] = {
134 .start = AT91_VA_BASE_EMAC, 135 .start = AT91_VA_BASE_EMAC,
135 .end = AT91_VA_BASE_EMAC + SZ_16K - 1, 136 .end = AT91_VA_BASE_EMAC + SZ_16K - 1,
@@ -150,8 +151,8 @@ static struct platform_device at91rm9200_eth_device = {
150 .coherent_dma_mask = 0xffffffff, 151 .coherent_dma_mask = 0xffffffff,
151 .platform_data = &eth_data, 152 .platform_data = &eth_data,
152 }, 153 },
153 .resource = at91_eth_resources, 154 .resource = eth_resources,
154 .num_resources = ARRAY_SIZE(at91_eth_resources), 155 .num_resources = ARRAY_SIZE(eth_resources),
155}; 156};
156 157
157void __init at91_add_device_eth(struct at91_eth_data *data) 158void __init at91_add_device_eth(struct at91_eth_data *data)
@@ -202,11 +203,13 @@ void __init at91_add_device_eth(struct at91_eth_data *data) {}
202#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) 203#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
203static struct at91_cf_data cf_data; 204static struct at91_cf_data cf_data;
204 205
205static struct resource at91_cf_resources[] = { 206#define CF_BASE AT91_CHIPSELECT_4
207
208static struct resource cf_resources[] = {
206 [0] = { 209 [0] = {
207 .start = AT91_CF_BASE, 210 .start = CF_BASE,
208 /* ties up CS4, CS5 and CS6 */ 211 /* ties up CS4, CS5 and CS6 */
209 .end = AT91_CF_BASE + (0x30000000 - 1), 212 .end = CF_BASE + (0x30000000 - 1),
210 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT, 213 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
211 }, 214 },
212}; 215};
@@ -217,15 +220,38 @@ static struct platform_device at91rm9200_cf_device = {
217 .dev = { 220 .dev = {
218 .platform_data = &cf_data, 221 .platform_data = &cf_data,
219 }, 222 },
220 .resource = at91_cf_resources, 223 .resource = cf_resources,
221 .num_resources = ARRAY_SIZE(at91_cf_resources), 224 .num_resources = ARRAY_SIZE(cf_resources),
222}; 225};
223 226
224void __init at91_add_device_cf(struct at91_cf_data *data) 227void __init at91_add_device_cf(struct at91_cf_data *data)
225{ 228{
229 unsigned int csa;
230
226 if (!data) 231 if (!data)
227 return; 232 return;
228 233
234 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
235
236 /* CF takes over CS4, CS5, CS6 */
237 csa = at91_sys_read(AT91_EBI_CSA);
238 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
239
240 /*
241 * Static memory controller timing adjustments.
242 * REVISIT: these timings are in terms of MCK cycles, so
243 * when MCK changes (cpufreq etc) so must these values...
244 */
245 at91_sys_write(AT91_SMC_CSR(4),
246 AT91_SMC_ACSS_STD
247 | AT91_SMC_DBW_16
248 | AT91_SMC_BAT
249 | AT91_SMC_WSEN
250 | AT91_SMC_NWS_(32) /* wait states */
251 | AT91_SMC_RWSETUP_(6) /* setup time */
252 | AT91_SMC_RWHOLD_(4) /* hold time */
253 );
254
229 /* input/irq */ 255 /* input/irq */
230 if (data->irq_pin) { 256 if (data->irq_pin) {
231 at91_set_gpio_input(data->irq_pin, 1); 257 at91_set_gpio_input(data->irq_pin, 1);
@@ -245,6 +271,9 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
245 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */ 271 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
246 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */ 272 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
247 273
274 /* nWAIT is _not_ a default setting */
275 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
276
248 cf_data = *data; 277 cf_data = *data;
249 platform_device_register(&at91rm9200_cf_device); 278 platform_device_register(&at91rm9200_cf_device);
250} 279}
@@ -257,11 +286,11 @@ void __init at91_add_device_cf(struct at91_cf_data *data) {}
257 * MMC / SD 286 * MMC / SD
258 * -------------------------------------------------------------------- */ 287 * -------------------------------------------------------------------- */
259 288
260#if defined(CONFIG_MMC_AT91RM9200) || defined(CONFIG_MMC_AT91RM9200_MODULE) 289#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
261static u64 mmc_dmamask = 0xffffffffUL; 290static u64 mmc_dmamask = 0xffffffffUL;
262static struct at91_mmc_data mmc_data; 291static struct at91_mmc_data mmc_data;
263 292
264static struct resource at91_mmc_resources[] = { 293static struct resource mmc_resources[] = {
265 [0] = { 294 [0] = {
266 .start = AT91RM9200_BASE_MCI, 295 .start = AT91RM9200_BASE_MCI,
267 .end = AT91RM9200_BASE_MCI + SZ_16K - 1, 296 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
@@ -282,8 +311,8 @@ static struct platform_device at91rm9200_mmc_device = {
282 .coherent_dma_mask = 0xffffffff, 311 .coherent_dma_mask = 0xffffffff,
283 .platform_data = &mmc_data, 312 .platform_data = &mmc_data,
284 }, 313 },
285 .resource = at91_mmc_resources, 314 .resource = mmc_resources,
286 .num_resources = ARRAY_SIZE(at91_mmc_resources), 315 .num_resources = ARRAY_SIZE(mmc_resources),
287}; 316};
288 317
289void __init at91_add_device_mmc(struct at91_mmc_data *data) 318void __init at91_add_device_mmc(struct at91_mmc_data *data)
@@ -298,31 +327,33 @@ void __init at91_add_device_mmc(struct at91_mmc_data *data)
298 } 327 }
299 if (data->wp_pin) 328 if (data->wp_pin)
300 at91_set_gpio_input(data->wp_pin, 1); 329 at91_set_gpio_input(data->wp_pin, 1);
330 if (data->vcc_pin)
331 at91_set_gpio_output(data->vcc_pin, 0);
301 332
302 /* CLK */ 333 /* CLK */
303 at91_set_A_periph(AT91_PIN_PA27, 0); 334 at91_set_A_periph(AT91_PIN_PA27, 0);
304 335
305 if (data->is_b) { 336 if (data->slot_b) {
306 /* CMD */ 337 /* CMD */
307 at91_set_B_periph(AT91_PIN_PA8, 0); 338 at91_set_B_periph(AT91_PIN_PA8, 1);
308 339
309 /* DAT0, maybe DAT1..DAT3 */ 340 /* DAT0, maybe DAT1..DAT3 */
310 at91_set_B_periph(AT91_PIN_PA9, 0); 341 at91_set_B_periph(AT91_PIN_PA9, 1);
311 if (data->wire4) { 342 if (data->wire4) {
312 at91_set_B_periph(AT91_PIN_PA10, 0); 343 at91_set_B_periph(AT91_PIN_PA10, 1);
313 at91_set_B_periph(AT91_PIN_PA11, 0); 344 at91_set_B_periph(AT91_PIN_PA11, 1);
314 at91_set_B_periph(AT91_PIN_PA12, 0); 345 at91_set_B_periph(AT91_PIN_PA12, 1);
315 } 346 }
316 } else { 347 } else {
317 /* CMD */ 348 /* CMD */
318 at91_set_A_periph(AT91_PIN_PA28, 0); 349 at91_set_A_periph(AT91_PIN_PA28, 1);
319 350
320 /* DAT0, maybe DAT1..DAT3 */ 351 /* DAT0, maybe DAT1..DAT3 */
321 at91_set_A_periph(AT91_PIN_PA29, 0); 352 at91_set_A_periph(AT91_PIN_PA29, 1);
322 if (data->wire4) { 353 if (data->wire4) {
323 at91_set_B_periph(AT91_PIN_PB3, 0); 354 at91_set_B_periph(AT91_PIN_PB3, 1);
324 at91_set_B_periph(AT91_PIN_PB4, 0); 355 at91_set_B_periph(AT91_PIN_PB4, 1);
325 at91_set_B_periph(AT91_PIN_PB5, 0); 356 at91_set_B_periph(AT91_PIN_PB5, 1);
326 } 357 }
327 } 358 }
328 359
@@ -341,29 +372,45 @@ void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
341#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) 372#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
342static struct at91_nand_data nand_data; 373static struct at91_nand_data nand_data;
343 374
344static struct resource at91_nand_resources[] = { 375#define NAND_BASE AT91_CHIPSELECT_3
376
377static struct resource nand_resources[] = {
345 { 378 {
346 .start = AT91_SMARTMEDIA_BASE, 379 .start = NAND_BASE,
347 .end = AT91_SMARTMEDIA_BASE + SZ_8M - 1, 380 .end = NAND_BASE + SZ_8M - 1,
348 .flags = IORESOURCE_MEM, 381 .flags = IORESOURCE_MEM,
349 } 382 }
350}; 383};
351 384
352static struct platform_device at91_nand_device = { 385static struct platform_device at91rm9200_nand_device = {
353 .name = "at91_nand", 386 .name = "at91_nand",
354 .id = -1, 387 .id = -1,
355 .dev = { 388 .dev = {
356 .platform_data = &nand_data, 389 .platform_data = &nand_data,
357 }, 390 },
358 .resource = at91_nand_resources, 391 .resource = nand_resources,
359 .num_resources = ARRAY_SIZE(at91_nand_resources), 392 .num_resources = ARRAY_SIZE(nand_resources),
360}; 393};
361 394
362void __init at91_add_device_nand(struct at91_nand_data *data) 395void __init at91_add_device_nand(struct at91_nand_data *data)
363{ 396{
397 unsigned int csa;
398
364 if (!data) 399 if (!data)
365 return; 400 return;
366 401
402 /* enable the address range of CS3 */
403 csa = at91_sys_read(AT91_EBI_CSA);
404 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
405
406 /* set the bus interface characteristics */
407 at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
408 | AT91_SMC_NWS_(5)
409 | AT91_SMC_TDF_(1)
410 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
411 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
412 );
413
367 /* enable pin */ 414 /* enable pin */
368 if (data->enable_pin) 415 if (data->enable_pin)
369 at91_set_gpio_output(data->enable_pin, 1); 416 at91_set_gpio_output(data->enable_pin, 1);
@@ -380,7 +427,7 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
380 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */ 427 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
381 428
382 nand_data = *data; 429 nand_data = *data;
383 platform_device_register(&at91_nand_device); 430 platform_device_register(&at91rm9200_nand_device);
384} 431}
385#else 432#else
386void __init at91_add_device_nand(struct at91_nand_data *data) {} 433void __init at91_add_device_nand(struct at91_nand_data *data) {}
@@ -392,10 +439,25 @@ void __init at91_add_device_nand(struct at91_nand_data *data) {}
392 * -------------------------------------------------------------------- */ 439 * -------------------------------------------------------------------- */
393 440
394#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) 441#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
442
443static struct resource twi_resources[] = {
444 [0] = {
445 .start = AT91RM9200_BASE_TWI,
446 .end = AT91RM9200_BASE_TWI + SZ_16K - 1,
447 .flags = IORESOURCE_MEM,
448 },
449 [1] = {
450 .start = AT91RM9200_ID_TWI,
451 .end = AT91RM9200_ID_TWI,
452 .flags = IORESOURCE_IRQ,
453 },
454};
455
395static struct platform_device at91rm9200_twi_device = { 456static struct platform_device at91rm9200_twi_device = {
396 .name = "at91_i2c", 457 .name = "at91_i2c",
397 .id = -1, 458 .id = -1,
398 .num_resources = 0, 459 .resource = twi_resources,
460 .num_resources = ARRAY_SIZE(twi_resources),
399}; 461};
400 462
401void __init at91_add_device_i2c(void) 463void __init at91_add_device_i2c(void)
@@ -421,7 +483,7 @@ void __init at91_add_device_i2c(void) {}
421#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) 483#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
422static u64 spi_dmamask = 0xffffffffUL; 484static u64 spi_dmamask = 0xffffffffUL;
423 485
424static struct resource at91_spi_resources[] = { 486static struct resource spi_resources[] = {
425 [0] = { 487 [0] = {
426 .start = AT91RM9200_BASE_SPI, 488 .start = AT91RM9200_BASE_SPI,
427 .end = AT91RM9200_BASE_SPI + SZ_16K - 1, 489 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
@@ -438,14 +500,14 @@ static struct platform_device at91rm9200_spi_device = {
438 .name = "at91_spi", 500 .name = "at91_spi",
439 .id = 0, 501 .id = 0,
440 .dev = { 502 .dev = {
441 .dma_mask = &spi_dmamask, 503 .dma_mask = &spi_dmamask,
442 .coherent_dma_mask = 0xffffffff, 504 .coherent_dma_mask = 0xffffffff,
443 }, 505 },
444 .resource = at91_spi_resources, 506 .resource = spi_resources,
445 .num_resources = ARRAY_SIZE(at91_spi_resources), 507 .num_resources = ARRAY_SIZE(spi_resources),
446}; 508};
447 509
448static const unsigned at91_spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 }; 510static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
449 511
450void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) 512void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
451{ 513{
@@ -461,7 +523,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
461 if (devices[i].controller_data) 523 if (devices[i].controller_data)
462 cs_pin = (unsigned long) devices[i].controller_data; 524 cs_pin = (unsigned long) devices[i].controller_data;
463 else 525 else
464 cs_pin = at91_spi_standard_cs[devices[i].chip_select]; 526 cs_pin = spi_standard_cs[devices[i].chip_select];
465 527
466#ifdef CONFIG_SPI_AT91_MANUAL_CS 528#ifdef CONFIG_SPI_AT91_MANUAL_CS
467 at91_set_gpio_output(cs_pin, 1); 529 at91_set_gpio_output(cs_pin, 1);
@@ -474,7 +536,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
474 } 536 }
475 537
476 spi_register_board_info(devices, nr_devices); 538 spi_register_board_info(devices, nr_devices);
477 at91_clock_associate("spi0_clk", &at91rm9200_spi_device.dev, "spi"); 539 at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi");
478 platform_device_register(&at91rm9200_spi_device); 540 platform_device_register(&at91rm9200_spi_device);
479} 541}
480#else 542#else
@@ -486,7 +548,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
486 * RTC 548 * RTC
487 * -------------------------------------------------------------------- */ 549 * -------------------------------------------------------------------- */
488 550
489#if defined(CONFIG_RTC_DRV_AT91) || defined(CONFIG_RTC_DRV_AT91_MODULE) 551#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
490static struct platform_device at91rm9200_rtc_device = { 552static struct platform_device at91rm9200_rtc_device = {
491 .name = "at91_rtc", 553 .name = "at91_rtc",
492 .id = -1, 554 .id = -1,
@@ -506,7 +568,7 @@ static void __init at91_add_device_rtc(void) {}
506 * Watchdog 568 * Watchdog
507 * -------------------------------------------------------------------- */ 569 * -------------------------------------------------------------------- */
508 570
509#if defined(CONFIG_AT91_WATCHDOG) || defined(CONFIG_AT91_WATCHDOG_MODULE) 571#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
510static struct platform_device at91rm9200_wdt_device = { 572static struct platform_device at91rm9200_wdt_device = {
511 .name = "at91_wdt", 573 .name = "at91_wdt",
512 .id = -1, 574 .id = -1,
diff --git a/arch/arm/mach-at91rm9200/at91rm9200_time.c b/arch/arm/mach-at91rm9200/at91rm9200_time.c
index 07c9cea8961d..b999e192a7e9 100644
--- a/arch/arm/mach-at91rm9200/at91rm9200_time.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200_time.c
@@ -30,6 +30,8 @@
30#include <asm/io.h> 30#include <asm/io.h>
31#include <asm/mach/time.h> 31#include <asm/mach/time.h>
32 32
33#include <asm/arch/at91_st.h>
34
33static unsigned long last_crtr; 35static unsigned long last_crtr;
34 36
35/* 37/*
@@ -99,6 +101,9 @@ void at91rm9200_timer_reset(void)
99 /* Set Period Interval timer */ 101 /* Set Period Interval timer */
100 at91_sys_write(AT91_ST_PIMR, LATCH); 102 at91_sys_write(AT91_ST_PIMR, LATCH);
101 103
104 /* Clear any pending interrupts */
105 (void) at91_sys_read(AT91_ST_SR);
106
102 /* Enable Period Interval Timer interrupt */ 107 /* Enable Period Interval Timer interrupt */
103 at91_sys_write(AT91_ST_IER, AT91_ST_PITS); 108 at91_sys_write(AT91_ST_IER, AT91_ST_PITS);
104} 109}
diff --git a/arch/arm/mach-at91rm9200/at91sam9260.c b/arch/arm/mach-at91rm9200/at91sam9260.c
new file mode 100644
index 000000000000..203f073a53e6
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam9260.c
@@ -0,0 +1,294 @@
1/*
2 * arch/arm/mach-at91rm9200/at91sam9260.c
3 *
4 * Copyright (C) 2006 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17#include <asm/arch/at91sam9260.h>
18#include <asm/arch/at91_pmc.h>
19
20#include "generic.h"
21#include "clock.h"
22
23static struct map_desc at91sam9260_io_desc[] __initdata = {
24 {
25 .virtual = AT91_VA_BASE_SYS,
26 .pfn = __phys_to_pfn(AT91_BASE_SYS),
27 .length = SZ_16K,
28 .type = MT_DEVICE,
29 }, {
30 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
31 .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
32 .length = AT91SAM9260_SRAM0_SIZE,
33 .type = MT_DEVICE,
34 }, {
35 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
36 .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
37 .length = AT91SAM9260_SRAM1_SIZE,
38 .type = MT_DEVICE,
39 },
40};
41
42/* --------------------------------------------------------------------
43 * Clocks
44 * -------------------------------------------------------------------- */
45
46/*
47 * The peripheral clocks.
48 */
49static struct clk pioA_clk = {
50 .name = "pioA_clk",
51 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
52 .type = CLK_TYPE_PERIPHERAL,
53};
54static struct clk pioB_clk = {
55 .name = "pioB_clk",
56 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
57 .type = CLK_TYPE_PERIPHERAL,
58};
59static struct clk pioC_clk = {
60 .name = "pioC_clk",
61 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
62 .type = CLK_TYPE_PERIPHERAL,
63};
64static struct clk adc_clk = {
65 .name = "adc_clk",
66 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
67 .type = CLK_TYPE_PERIPHERAL,
68};
69static struct clk usart0_clk = {
70 .name = "usart0_clk",
71 .pmc_mask = 1 << AT91SAM9260_ID_US0,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk usart1_clk = {
75 .name = "usart1_clk",
76 .pmc_mask = 1 << AT91SAM9260_ID_US1,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk usart2_clk = {
80 .name = "usart2_clk",
81 .pmc_mask = 1 << AT91SAM9260_ID_US2,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk mmc_clk = {
85 .name = "mci_clk",
86 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk udc_clk = {
90 .name = "udc_clk",
91 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk twi_clk = {
95 .name = "twi_clk",
96 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk spi0_clk = {
100 .name = "spi0_clk",
101 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk spi1_clk = {
105 .name = "spi1_clk",
106 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109static struct clk ohci_clk = {
110 .name = "ohci_clk",
111 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
112 .type = CLK_TYPE_PERIPHERAL,
113};
114static struct clk ether_clk = {
115 .name = "ether_clk",
116 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
117 .type = CLK_TYPE_PERIPHERAL,
118};
119static struct clk isi_clk = {
120 .name = "isi_clk",
121 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
122 .type = CLK_TYPE_PERIPHERAL,
123};
124static struct clk usart3_clk = {
125 .name = "usart3_clk",
126 .pmc_mask = 1 << AT91SAM9260_ID_US3,
127 .type = CLK_TYPE_PERIPHERAL,
128};
129static struct clk usart4_clk = {
130 .name = "usart4_clk",
131 .pmc_mask = 1 << AT91SAM9260_ID_US4,
132 .type = CLK_TYPE_PERIPHERAL,
133};
134static struct clk usart5_clk = {
135 .name = "usart5_clk",
136 .pmc_mask = 1 << AT91SAM9260_ID_US5,
137 .type = CLK_TYPE_PERIPHERAL,
138};
139
140static struct clk *periph_clocks[] __initdata = {
141 &pioA_clk,
142 &pioB_clk,
143 &pioC_clk,
144 &adc_clk,
145 &usart0_clk,
146 &usart1_clk,
147 &usart2_clk,
148 &mmc_clk,
149 &udc_clk,
150 &twi_clk,
151 &spi0_clk,
152 &spi1_clk,
153 // ssc
154 // tc0 .. tc2
155 &ohci_clk,
156 &ether_clk,
157 &isi_clk,
158 &usart3_clk,
159 &usart4_clk,
160 &usart5_clk,
161 // tc3 .. tc5
162 // irq0 .. irq2
163};
164
165/*
166 * The two programmable clocks.
167 * You must configure pin multiplexing to bring these signals out.
168 */
169static struct clk pck0 = {
170 .name = "pck0",
171 .pmc_mask = AT91_PMC_PCK0,
172 .type = CLK_TYPE_PROGRAMMABLE,
173 .id = 0,
174};
175static struct clk pck1 = {
176 .name = "pck1",
177 .pmc_mask = AT91_PMC_PCK1,
178 .type = CLK_TYPE_PROGRAMMABLE,
179 .id = 1,
180};
181
182static void __init at91sam9260_register_clocks(void)
183{
184 int i;
185
186 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
187 clk_register(periph_clocks[i]);
188
189 clk_register(&pck0);
190 clk_register(&pck1);
191}
192
193/* --------------------------------------------------------------------
194 * GPIO
195 * -------------------------------------------------------------------- */
196
197static struct at91_gpio_bank at91sam9260_gpio[] = {
198 {
199 .id = AT91SAM9260_ID_PIOA,
200 .offset = AT91_PIOA,
201 .clock = &pioA_clk,
202 }, {
203 .id = AT91SAM9260_ID_PIOB,
204 .offset = AT91_PIOB,
205 .clock = &pioB_clk,
206 }, {
207 .id = AT91SAM9260_ID_PIOC,
208 .offset = AT91_PIOC,
209 .clock = &pioC_clk,
210 }
211};
212
213static void at91sam9260_reset(void)
214{
215#warning "Implement CPU reset"
216}
217
218
219/* --------------------------------------------------------------------
220 * AT91SAM9260 processor initialization
221 * -------------------------------------------------------------------- */
222
223void __init at91sam9260_initialize(unsigned long main_clock)
224{
225 /* Map peripherals */
226 iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
227
228 at91_arch_reset = at91sam9260_reset;
229 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
230 | (1 << AT91SAM9260_ID_IRQ2);
231
232 /* Init clock subsystem */
233 at91_clock_init(main_clock);
234
235 /* Register the processor-specific clocks */
236 at91sam9260_register_clocks();
237
238 /* Register GPIO subsystem */
239 at91_gpio_init(at91sam9260_gpio, 3);
240}
241
242/* --------------------------------------------------------------------
243 * Interrupt initialization
244 * -------------------------------------------------------------------- */
245
246/*
247 * The default interrupt priority levels (0 = lowest, 7 = highest).
248 */
249static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
250 7, /* Advanced Interrupt Controller */
251 7, /* System Peripherals */
252 0, /* Parallel IO Controller A */
253 0, /* Parallel IO Controller B */
254 0, /* Parallel IO Controller C */
255 0, /* Analog-to-Digital Converter */
256 6, /* USART 0 */
257 6, /* USART 1 */
258 6, /* USART 2 */
259 0, /* Multimedia Card Interface */
260 4, /* USB Device Port */
261 0, /* Two-Wire Interface */
262 6, /* Serial Peripheral Interface 0 */
263 6, /* Serial Peripheral Interface 1 */
264 5, /* Serial Synchronous Controller */
265 0,
266 0,
267 0, /* Timer Counter 0 */
268 0, /* Timer Counter 1 */
269 0, /* Timer Counter 2 */
270 3, /* USB Host port */
271 3, /* Ethernet */
272 0, /* Image Sensor Interface */
273 6, /* USART 3 */
274 6, /* USART 4 */
275 6, /* USART 5 */
276 0, /* Timer Counter 3 */
277 0, /* Timer Counter 4 */
278 0, /* Timer Counter 5 */
279 0, /* Advanced Interrupt Controller */
280 0, /* Advanced Interrupt Controller */
281 0, /* Advanced Interrupt Controller */
282};
283
284void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
285{
286 if (!priority)
287 priority = at91sam9260_default_irq_priority;
288
289 /* Initialize the AIC interrupt controller */
290 at91_aic_init(priority);
291
292 /* Enable GPIO interrupts */
293 at91_gpio_irq_setup();
294}
diff --git a/arch/arm/mach-at91rm9200/at91sam9260_devices.c b/arch/arm/mach-at91rm9200/at91sam9260_devices.c
new file mode 100644
index 000000000000..a6c596dc4516
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam9260_devices.c
@@ -0,0 +1,866 @@
1/*
2 * arch/arm/mach-at91rm9200/at91sam9260_devices.c
3 *
4 * Copyright (C) 2006 Atmel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/platform_device.h>
16
17#include <asm/arch/board.h>
18#include <asm/arch/gpio.h>
19#include <asm/arch/at91sam9260.h>
20#include <asm/arch/at91sam926x_mc.h>
21
22#include "generic.h"
23
24#define SZ_512 0x00000200
25#define SZ_256 0x00000100
26#define SZ_16 0x00000010
27
28/* --------------------------------------------------------------------
29 * USB Host
30 * -------------------------------------------------------------------- */
31
32#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
33static u64 ohci_dmamask = 0xffffffffUL;
34static struct at91_usbh_data usbh_data;
35
36static struct resource usbh_resources[] = {
37 [0] = {
38 .start = AT91SAM9260_UHP_BASE,
39 .end = AT91SAM9260_UHP_BASE + SZ_1M - 1,
40 .flags = IORESOURCE_MEM,
41 },
42 [1] = {
43 .start = AT91SAM9260_ID_UHP,
44 .end = AT91SAM9260_ID_UHP,
45 .flags = IORESOURCE_IRQ,
46 },
47};
48
49static struct platform_device at91_usbh_device = {
50 .name = "at91_ohci",
51 .id = -1,
52 .dev = {
53 .dma_mask = &ohci_dmamask,
54 .coherent_dma_mask = 0xffffffff,
55 .platform_data = &usbh_data,
56 },
57 .resource = usbh_resources,
58 .num_resources = ARRAY_SIZE(usbh_resources),
59};
60
61void __init at91_add_device_usbh(struct at91_usbh_data *data)
62{
63 if (!data)
64 return;
65
66 usbh_data = *data;
67 platform_device_register(&at91_usbh_device);
68}
69#else
70void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
71#endif
72
73
74/* --------------------------------------------------------------------
75 * USB Device (Gadget)
76 * -------------------------------------------------------------------- */
77
78#ifdef CONFIG_USB_GADGET_AT91
79static struct at91_udc_data udc_data;
80
81static struct resource udc_resources[] = {
82 [0] = {
83 .start = AT91SAM9260_BASE_UDP,
84 .end = AT91SAM9260_BASE_UDP + SZ_16K - 1,
85 .flags = IORESOURCE_MEM,
86 },
87 [1] = {
88 .start = AT91SAM9260_ID_UDP,
89 .end = AT91SAM9260_ID_UDP,
90 .flags = IORESOURCE_IRQ,
91 },
92};
93
94static struct platform_device at91_udc_device = {
95 .name = "at91_udc",
96 .id = -1,
97 .dev = {
98 .platform_data = &udc_data,
99 },
100 .resource = udc_resources,
101 .num_resources = ARRAY_SIZE(udc_resources),
102};
103
104void __init at91_add_device_udc(struct at91_udc_data *data)
105{
106 if (!data)
107 return;
108
109 if (data->vbus_pin) {
110 at91_set_gpio_input(data->vbus_pin, 0);
111 at91_set_deglitch(data->vbus_pin, 1);
112 }
113
114 /* Pullup pin is handled internally by USB device peripheral */
115
116 udc_data = *data;
117 platform_device_register(&at91_udc_device);
118}
119#else
120void __init at91_add_device_udc(struct at91_udc_data *data) {}
121#endif
122
123
124/* --------------------------------------------------------------------
125 * Ethernet
126 * -------------------------------------------------------------------- */
127
128#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
129static u64 eth_dmamask = 0xffffffffUL;
130static struct eth_platform_data eth_data;
131
132static struct resource eth_resources[] = {
133 [0] = {
134 .start = AT91SAM9260_BASE_EMAC,
135 .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
136 .flags = IORESOURCE_MEM,
137 },
138 [1] = {
139 .start = AT91SAM9260_ID_EMAC,
140 .end = AT91SAM9260_ID_EMAC,
141 .flags = IORESOURCE_IRQ,
142 },
143};
144
145static struct platform_device at91sam9260_eth_device = {
146 .name = "macb",
147 .id = -1,
148 .dev = {
149 .dma_mask = &eth_dmamask,
150 .coherent_dma_mask = 0xffffffff,
151 .platform_data = &eth_data,
152 },
153 .resource = eth_resources,
154 .num_resources = ARRAY_SIZE(eth_resources),
155};
156
157void __init at91_add_device_eth(struct eth_platform_data *data)
158{
159 if (!data)
160 return;
161
162 if (data->phy_irq_pin) {
163 at91_set_gpio_input(data->phy_irq_pin, 0);
164 at91_set_deglitch(data->phy_irq_pin, 1);
165 }
166
167 /* Pins used for MII and RMII */
168 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
169 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
170 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
171 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
172 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
173 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
174 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
175 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
176 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
177 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
178
179 if (!data->is_rmii) {
180 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
181 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
182 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
183 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
184 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
185 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
186 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
187 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
188 }
189
190 eth_data = *data;
191 platform_device_register(&at91sam9260_eth_device);
192}
193#else
194void __init at91_add_device_eth(struct eth_platform_data *data) {}
195#endif
196
197
198/* --------------------------------------------------------------------
199 * MMC / SD
200 * -------------------------------------------------------------------- */
201
202#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
203static u64 mmc_dmamask = 0xffffffffUL;
204static struct at91_mmc_data mmc_data;
205
206static struct resource mmc_resources[] = {
207 [0] = {
208 .start = AT91SAM9260_BASE_MCI,
209 .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = AT91SAM9260_ID_MCI,
214 .end = AT91SAM9260_ID_MCI,
215 .flags = IORESOURCE_IRQ,
216 },
217};
218
219static struct platform_device at91sam9260_mmc_device = {
220 .name = "at91_mci",
221 .id = -1,
222 .dev = {
223 .dma_mask = &mmc_dmamask,
224 .coherent_dma_mask = 0xffffffff,
225 .platform_data = &mmc_data,
226 },
227 .resource = mmc_resources,
228 .num_resources = ARRAY_SIZE(mmc_resources),
229};
230
231void __init at91_add_device_mmc(struct at91_mmc_data *data)
232{
233 if (!data)
234 return;
235
236 /* input/irq */
237 if (data->det_pin) {
238 at91_set_gpio_input(data->det_pin, 1);
239 at91_set_deglitch(data->det_pin, 1);
240 }
241 if (data->wp_pin)
242 at91_set_gpio_input(data->wp_pin, 1);
243 if (data->vcc_pin)
244 at91_set_gpio_output(data->vcc_pin, 0);
245
246 /* CLK */
247 at91_set_A_periph(AT91_PIN_PA8, 0);
248
249 if (data->slot_b) {
250 /* CMD */
251 at91_set_B_periph(AT91_PIN_PA1, 1);
252
253 /* DAT0, maybe DAT1..DAT3 */
254 at91_set_B_periph(AT91_PIN_PA0, 1);
255 if (data->wire4) {
256 at91_set_B_periph(AT91_PIN_PA5, 1);
257 at91_set_B_periph(AT91_PIN_PA4, 1);
258 at91_set_B_periph(AT91_PIN_PA3, 1);
259 }
260 } else {
261 /* CMD */
262 at91_set_A_periph(AT91_PIN_PA7, 1);
263
264 /* DAT0, maybe DAT1..DAT3 */
265 at91_set_A_periph(AT91_PIN_PA6, 1);
266 if (data->wire4) {
267 at91_set_A_periph(AT91_PIN_PA9, 1);
268 at91_set_A_periph(AT91_PIN_PA10, 1);
269 at91_set_A_periph(AT91_PIN_PA11, 1);
270 }
271 }
272
273 mmc_data = *data;
274 platform_device_register(&at91sam9260_mmc_device);
275}
276#else
277void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
278#endif
279
280
281/* --------------------------------------------------------------------
282 * NAND / SmartMedia
283 * -------------------------------------------------------------------- */
284
285#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
286static struct at91_nand_data nand_data;
287
288#define NAND_BASE AT91_CHIPSELECT_3
289
290static struct resource nand_resources[] = {
291 {
292 .start = NAND_BASE,
293 .end = NAND_BASE + SZ_8M - 1,
294 .flags = IORESOURCE_MEM,
295 }
296};
297
298static struct platform_device at91sam9260_nand_device = {
299 .name = "at91_nand",
300 .id = -1,
301 .dev = {
302 .platform_data = &nand_data,
303 },
304 .resource = nand_resources,
305 .num_resources = ARRAY_SIZE(nand_resources),
306};
307
308void __init at91_add_device_nand(struct at91_nand_data *data)
309{
310 unsigned long csa, mode;
311
312 if (!data)
313 return;
314
315 csa = at91_sys_read(AT91_MATRIX_EBICSA);
316 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC);
317
318 /* set the bus interface characteristics */
319 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
320 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
321
322 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
323 | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
324
325 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
326
327 if (data->bus_width_16)
328 mode = AT91_SMC_DBW_16;
329 else
330 mode = AT91_SMC_DBW_8;
331 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
332
333 /* enable pin */
334 if (data->enable_pin)
335 at91_set_gpio_output(data->enable_pin, 1);
336
337 /* ready/busy pin */
338 if (data->rdy_pin)
339 at91_set_gpio_input(data->rdy_pin, 1);
340
341 /* card detect pin */
342 if (data->det_pin)
343 at91_set_gpio_input(data->det_pin, 1);
344
345 nand_data = *data;
346 platform_device_register(&at91sam9260_nand_device);
347}
348#else
349void __init at91_add_device_nand(struct at91_nand_data *data) {}
350#endif
351
352
353/* --------------------------------------------------------------------
354 * TWI (i2c)
355 * -------------------------------------------------------------------- */
356
357#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
358
359static struct resource twi_resources[] = {
360 [0] = {
361 .start = AT91SAM9260_BASE_TWI,
362 .end = AT91SAM9260_BASE_TWI + SZ_16K - 1,
363 .flags = IORESOURCE_MEM,
364 },
365 [1] = {
366 .start = AT91SAM9260_ID_TWI,
367 .end = AT91SAM9260_ID_TWI,
368 .flags = IORESOURCE_IRQ,
369 },
370};
371
372static struct platform_device at91sam9260_twi_device = {
373 .name = "at91_i2c",
374 .id = -1,
375 .resource = twi_resources,
376 .num_resources = ARRAY_SIZE(twi_resources),
377};
378
379void __init at91_add_device_i2c(void)
380{
381 /* pins used for TWI interface */
382 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
383 at91_set_multi_drive(AT91_PIN_PA23, 1);
384
385 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
386 at91_set_multi_drive(AT91_PIN_PA24, 1);
387
388 platform_device_register(&at91sam9260_twi_device);
389}
390#else
391void __init at91_add_device_i2c(void) {}
392#endif
393
394
395/* --------------------------------------------------------------------
396 * SPI
397 * -------------------------------------------------------------------- */
398
399#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
400static u64 spi_dmamask = 0xffffffffUL;
401
402static struct resource spi0_resources[] = {
403 [0] = {
404 .start = AT91SAM9260_BASE_SPI0,
405 .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = AT91SAM9260_ID_SPI0,
410 .end = AT91SAM9260_ID_SPI0,
411 .flags = IORESOURCE_IRQ,
412 },
413};
414
415static struct platform_device at91sam9260_spi0_device = {
416 .name = "atmel_spi",
417 .id = 0,
418 .dev = {
419 .dma_mask = &spi_dmamask,
420 .coherent_dma_mask = 0xffffffff,
421 },
422 .resource = spi0_resources,
423 .num_resources = ARRAY_SIZE(spi0_resources),
424};
425
426static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
427
428static struct resource spi1_resources[] = {
429 [0] = {
430 .start = AT91SAM9260_BASE_SPI1,
431 .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
432 .flags = IORESOURCE_MEM,
433 },
434 [1] = {
435 .start = AT91SAM9260_ID_SPI1,
436 .end = AT91SAM9260_ID_SPI1,
437 .flags = IORESOURCE_IRQ,
438 },
439};
440
441static struct platform_device at91sam9260_spi1_device = {
442 .name = "atmel_spi",
443 .id = 1,
444 .dev = {
445 .dma_mask = &spi_dmamask,
446 .coherent_dma_mask = 0xffffffff,
447 },
448 .resource = spi1_resources,
449 .num_resources = ARRAY_SIZE(spi1_resources),
450};
451
452static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
453
454void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
455{
456 int i;
457 unsigned long cs_pin;
458 short enable_spi0 = 0;
459 short enable_spi1 = 0;
460
461 /* Choose SPI chip-selects */
462 for (i = 0; i < nr_devices; i++) {
463 if (devices[i].controller_data)
464 cs_pin = (unsigned long) devices[i].controller_data;
465 else if (devices[i].bus_num == 0)
466 cs_pin = spi0_standard_cs[devices[i].chip_select];
467 else
468 cs_pin = spi1_standard_cs[devices[i].chip_select];
469
470 if (devices[i].bus_num == 0)
471 enable_spi0 = 1;
472 else
473 enable_spi1 = 1;
474
475 /* enable chip-select pin */
476 at91_set_gpio_output(cs_pin, 1);
477
478 /* pass chip-select pin to driver */
479 devices[i].controller_data = (void *) cs_pin;
480 }
481
482 spi_register_board_info(devices, nr_devices);
483
484 /* Configure SPI bus(es) */
485 if (enable_spi0) {
486 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
487 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
488 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
489
490 at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk");
491 platform_device_register(&at91sam9260_spi0_device);
492 }
493 if (enable_spi1) {
494 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
495 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
496 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
497
498 at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk");
499 platform_device_register(&at91sam9260_spi1_device);
500 }
501}
502#else
503void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
504#endif
505
506
507/* --------------------------------------------------------------------
508 * LEDs
509 * -------------------------------------------------------------------- */
510
511#if defined(CONFIG_LEDS)
512u8 at91_leds_cpu;
513u8 at91_leds_timer;
514
515void __init at91_init_leds(u8 cpu_led, u8 timer_led)
516{
517 at91_leds_cpu = cpu_led;
518 at91_leds_timer = timer_led;
519}
520#else
521void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
522#endif
523
524
525/* --------------------------------------------------------------------
526 * UART
527 * -------------------------------------------------------------------- */
528#if defined(CONFIG_SERIAL_ATMEL)
529static struct resource dbgu_resources[] = {
530 [0] = {
531 .start = AT91_VA_BASE_SYS + AT91_DBGU,
532 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
533 .flags = IORESOURCE_MEM,
534 },
535 [1] = {
536 .start = AT91_ID_SYS,
537 .end = AT91_ID_SYS,
538 .flags = IORESOURCE_IRQ,
539 },
540};
541
542static struct atmel_uart_data dbgu_data = {
543 .use_dma_tx = 0,
544 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
545 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
546};
547
548static struct platform_device at91sam9260_dbgu_device = {
549 .name = "atmel_usart",
550 .id = 0,
551 .dev = {
552 .platform_data = &dbgu_data,
553 .coherent_dma_mask = 0xffffffff,
554 },
555 .resource = dbgu_resources,
556 .num_resources = ARRAY_SIZE(dbgu_resources),
557};
558
559static inline void configure_dbgu_pins(void)
560{
561 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
562 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
563}
564
565static struct resource uart0_resources[] = {
566 [0] = {
567 .start = AT91SAM9260_BASE_US0,
568 .end = AT91SAM9260_BASE_US0 + SZ_16K - 1,
569 .flags = IORESOURCE_MEM,
570 },
571 [1] = {
572 .start = AT91SAM9260_ID_US0,
573 .end = AT91SAM9260_ID_US0,
574 .flags = IORESOURCE_IRQ,
575 },
576};
577
578static struct atmel_uart_data uart0_data = {
579 .use_dma_tx = 1,
580 .use_dma_rx = 1,
581};
582
583static struct platform_device at91sam9260_uart0_device = {
584 .name = "atmel_usart",
585 .id = 1,
586 .dev = {
587 .platform_data = &uart0_data,
588 .coherent_dma_mask = 0xffffffff,
589 },
590 .resource = uart0_resources,
591 .num_resources = ARRAY_SIZE(uart0_resources),
592};
593
594static inline void configure_usart0_pins(void)
595{
596 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
597 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
598 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */
599 at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */
600 at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */
601 at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */
602 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */
603 at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
604}
605
606static struct resource uart1_resources[] = {
607 [0] = {
608 .start = AT91SAM9260_BASE_US1,
609 .end = AT91SAM9260_BASE_US1 + SZ_16K - 1,
610 .flags = IORESOURCE_MEM,
611 },
612 [1] = {
613 .start = AT91SAM9260_ID_US1,
614 .end = AT91SAM9260_ID_US1,
615 .flags = IORESOURCE_IRQ,
616 },
617};
618
619static struct atmel_uart_data uart1_data = {
620 .use_dma_tx = 1,
621 .use_dma_rx = 1,
622};
623
624static struct platform_device at91sam9260_uart1_device = {
625 .name = "atmel_usart",
626 .id = 2,
627 .dev = {
628 .platform_data = &uart1_data,
629 .coherent_dma_mask = 0xffffffff,
630 },
631 .resource = uart1_resources,
632 .num_resources = ARRAY_SIZE(uart1_resources),
633};
634
635static inline void configure_usart1_pins(void)
636{
637 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
638 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
639 at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */
640 at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
641}
642
643static struct resource uart2_resources[] = {
644 [0] = {
645 .start = AT91SAM9260_BASE_US2,
646 .end = AT91SAM9260_BASE_US2 + SZ_16K - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 [1] = {
650 .start = AT91SAM9260_ID_US2,
651 .end = AT91SAM9260_ID_US2,
652 .flags = IORESOURCE_IRQ,
653 },
654};
655
656static struct atmel_uart_data uart2_data = {
657 .use_dma_tx = 1,
658 .use_dma_rx = 1,
659};
660
661static struct platform_device at91sam9260_uart2_device = {
662 .name = "atmel_usart",
663 .id = 3,
664 .dev = {
665 .platform_data = &uart2_data,
666 .coherent_dma_mask = 0xffffffff,
667 },
668 .resource = uart2_resources,
669 .num_resources = ARRAY_SIZE(uart2_resources),
670};
671
672static inline void configure_usart2_pins(void)
673{
674 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
675 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
676}
677
678static struct resource uart3_resources[] = {
679 [0] = {
680 .start = AT91SAM9260_BASE_US3,
681 .end = AT91SAM9260_BASE_US3 + SZ_16K - 1,
682 .flags = IORESOURCE_MEM,
683 },
684 [1] = {
685 .start = AT91SAM9260_ID_US3,
686 .end = AT91SAM9260_ID_US3,
687 .flags = IORESOURCE_IRQ,
688 },
689};
690
691static struct atmel_uart_data uart3_data = {
692 .use_dma_tx = 1,
693 .use_dma_rx = 1,
694};
695
696static struct platform_device at91sam9260_uart3_device = {
697 .name = "atmel_usart",
698 .id = 4,
699 .dev = {
700 .platform_data = &uart3_data,
701 .coherent_dma_mask = 0xffffffff,
702 },
703 .resource = uart3_resources,
704 .num_resources = ARRAY_SIZE(uart3_resources),
705};
706
707static inline void configure_usart3_pins(void)
708{
709 at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
710 at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */
711}
712
713static struct resource uart4_resources[] = {
714 [0] = {
715 .start = AT91SAM9260_BASE_US4,
716 .end = AT91SAM9260_BASE_US4 + SZ_16K - 1,
717 .flags = IORESOURCE_MEM,
718 },
719 [1] = {
720 .start = AT91SAM9260_ID_US4,
721 .end = AT91SAM9260_ID_US4,
722 .flags = IORESOURCE_IRQ,
723 },
724};
725
726static struct atmel_uart_data uart4_data = {
727 .use_dma_tx = 1,
728 .use_dma_rx = 1,
729};
730
731static struct platform_device at91sam9260_uart4_device = {
732 .name = "atmel_usart",
733 .id = 5,
734 .dev = {
735 .platform_data = &uart4_data,
736 .coherent_dma_mask = 0xffffffff,
737 },
738 .resource = uart4_resources,
739 .num_resources = ARRAY_SIZE(uart4_resources),
740};
741
742static inline void configure_usart4_pins(void)
743{
744 at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
745 at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
746}
747
748static struct resource uart5_resources[] = {
749 [0] = {
750 .start = AT91SAM9260_BASE_US5,
751 .end = AT91SAM9260_BASE_US5 + SZ_16K - 1,
752 .flags = IORESOURCE_MEM,
753 },
754 [1] = {
755 .start = AT91SAM9260_ID_US5,
756 .end = AT91SAM9260_ID_US5,
757 .flags = IORESOURCE_IRQ,
758 },
759};
760
761static struct atmel_uart_data uart5_data = {
762 .use_dma_tx = 1,
763 .use_dma_rx = 1,
764};
765
766static struct platform_device at91sam9260_uart5_device = {
767 .name = "atmel_usart",
768 .id = 6,
769 .dev = {
770 .platform_data = &uart5_data,
771 .coherent_dma_mask = 0xffffffff,
772 },
773 .resource = uart5_resources,
774 .num_resources = ARRAY_SIZE(uart5_resources),
775};
776
777static inline void configure_usart5_pins(void)
778{
779 at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
780 at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
781}
782
783struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
784struct platform_device *atmel_default_console_device; /* the serial console device */
785
786void __init at91_init_serial(struct at91_uart_config *config)
787{
788 int i;
789
790 /* Fill in list of supported UARTs */
791 for (i = 0; i < config->nr_tty; i++) {
792 switch (config->tty_map[i]) {
793 case 0:
794 configure_usart0_pins();
795 at91_uarts[i] = &at91sam9260_uart0_device;
796 at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
797 break;
798 case 1:
799 configure_usart1_pins();
800 at91_uarts[i] = &at91sam9260_uart1_device;
801 at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
802 break;
803 case 2:
804 configure_usart2_pins();
805 at91_uarts[i] = &at91sam9260_uart2_device;
806 at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
807 break;
808 case 3:
809 configure_usart3_pins();
810 at91_uarts[i] = &at91sam9260_uart3_device;
811 at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
812 break;
813 case 4:
814 configure_usart4_pins();
815 at91_uarts[i] = &at91sam9260_uart4_device;
816 at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
817 break;
818 case 5:
819 configure_usart5_pins();
820 at91_uarts[i] = &at91sam9260_uart5_device;
821 at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
822 break;
823 case 6:
824 configure_dbgu_pins();
825 at91_uarts[i] = &at91sam9260_dbgu_device;
826 at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
827 break;
828 default:
829 continue;
830 }
831 at91_uarts[i]->id = i; /* update ID number to mapped ID */
832 }
833
834 /* Set serial console device */
835 if (config->console_tty < ATMEL_MAX_UART)
836 atmel_default_console_device = at91_uarts[config->console_tty];
837 if (!atmel_default_console_device)
838 printk(KERN_INFO "AT91: No default serial console defined.\n");
839}
840
841void __init at91_add_device_serial(void)
842{
843 int i;
844
845 for (i = 0; i < ATMEL_MAX_UART; i++) {
846 if (at91_uarts[i])
847 platform_device_register(at91_uarts[i]);
848 }
849}
850#else
851void __init at91_init_serial(struct at91_uart_config *config) {}
852void __init at91_add_device_serial(void) {}
853#endif
854
855
856/* -------------------------------------------------------------------- */
857/*
858 * These devices are always present and don't need any board-specific
859 * setup.
860 */
861static int __init at91_add_standard_devices(void)
862{
863 return 0;
864}
865
866arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91rm9200/at91sam9261.c b/arch/arm/mach-at91rm9200/at91sam9261.c
new file mode 100644
index 000000000000..5a82f35da2e9
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam9261.c
@@ -0,0 +1,289 @@
1/*
2 * arch/arm/mach-at91rm9200/at91sam9261.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17#include <asm/arch/at91sam9261.h>
18#include <asm/arch/at91_pmc.h>
19
20#include "generic.h"
21#include "clock.h"
22
23static struct map_desc at91sam9261_io_desc[] __initdata = {
24 {
25 .virtual = AT91_VA_BASE_SYS,
26 .pfn = __phys_to_pfn(AT91_BASE_SYS),
27 .length = SZ_16K,
28 .type = MT_DEVICE,
29 }, {
30 .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
31 .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
32 .length = AT91SAM9261_SRAM_SIZE,
33 .type = MT_DEVICE,
34 },
35};
36
37/* --------------------------------------------------------------------
38 * Clocks
39 * -------------------------------------------------------------------- */
40
41/*
42 * The peripheral clocks.
43 */
44static struct clk pioA_clk = {
45 .name = "pioA_clk",
46 .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
47 .type = CLK_TYPE_PERIPHERAL,
48};
49static struct clk pioB_clk = {
50 .name = "pioB_clk",
51 .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
52 .type = CLK_TYPE_PERIPHERAL,
53};
54static struct clk pioC_clk = {
55 .name = "pioC_clk",
56 .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
57 .type = CLK_TYPE_PERIPHERAL,
58};
59static struct clk usart0_clk = {
60 .name = "usart0_clk",
61 .pmc_mask = 1 << AT91SAM9261_ID_US0,
62 .type = CLK_TYPE_PERIPHERAL,
63};
64static struct clk usart1_clk = {
65 .name = "usart1_clk",
66 .pmc_mask = 1 << AT91SAM9261_ID_US1,
67 .type = CLK_TYPE_PERIPHERAL,
68};
69static struct clk usart2_clk = {
70 .name = "usart2_clk",
71 .pmc_mask = 1 << AT91SAM9261_ID_US2,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk mmc_clk = {
75 .name = "mci_clk",
76 .pmc_mask = 1 << AT91SAM9261_ID_MCI,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk udc_clk = {
80 .name = "udc_clk",
81 .pmc_mask = 1 << AT91SAM9261_ID_UDP,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk twi_clk = {
85 .name = "twi_clk",
86 .pmc_mask = 1 << AT91SAM9261_ID_TWI,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk spi0_clk = {
90 .name = "spi0_clk",
91 .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk spi1_clk = {
95 .name = "spi1_clk",
96 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk ohci_clk = {
100 .name = "ohci_clk",
101 .pmc_mask = 1 << AT91SAM9261_ID_UHP,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk lcdc_clk = {
105 .name = "lcdc_clk",
106 .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109
110static struct clk *periph_clocks[] __initdata = {
111 &pioA_clk,
112 &pioB_clk,
113 &pioC_clk,
114 &usart0_clk,
115 &usart1_clk,
116 &usart2_clk,
117 &mmc_clk,
118 &udc_clk,
119 &twi_clk,
120 &spi0_clk,
121 &spi1_clk,
122 // ssc 0 .. ssc2
123 // tc0 .. tc2
124 &ohci_clk,
125 &lcdc_clk,
126 // irq0 .. irq2
127};
128
129/*
130 * The four programmable clocks.
131 * You must configure pin multiplexing to bring these signals out.
132 */
133static struct clk pck0 = {
134 .name = "pck0",
135 .pmc_mask = AT91_PMC_PCK0,
136 .type = CLK_TYPE_PROGRAMMABLE,
137 .id = 0,
138};
139static struct clk pck1 = {
140 .name = "pck1",
141 .pmc_mask = AT91_PMC_PCK1,
142 .type = CLK_TYPE_PROGRAMMABLE,
143 .id = 1,
144};
145static struct clk pck2 = {
146 .name = "pck2",
147 .pmc_mask = AT91_PMC_PCK2,
148 .type = CLK_TYPE_PROGRAMMABLE,
149 .id = 2,
150};
151static struct clk pck3 = {
152 .name = "pck3",
153 .pmc_mask = AT91_PMC_PCK3,
154 .type = CLK_TYPE_PROGRAMMABLE,
155 .id = 3,
156};
157
158/* HClocks */
159static struct clk hck0 = {
160 .name = "hck0",
161 .pmc_mask = AT91_PMC_HCK0,
162 .type = CLK_TYPE_SYSTEM,
163 .id = 0,
164};
165static struct clk hck1 = {
166 .name = "hck1",
167 .pmc_mask = AT91_PMC_HCK1,
168 .type = CLK_TYPE_SYSTEM,
169 .id = 1,
170};
171
172static void __init at91sam9261_register_clocks(void)
173{
174 int i;
175
176 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
177 clk_register(periph_clocks[i]);
178
179 clk_register(&pck0);
180 clk_register(&pck1);
181 clk_register(&pck2);
182 clk_register(&pck3);
183
184 clk_register(&hck0);
185 clk_register(&hck1);
186}
187
188/* --------------------------------------------------------------------
189 * GPIO
190 * -------------------------------------------------------------------- */
191
192static struct at91_gpio_bank at91sam9261_gpio[] = {
193 {
194 .id = AT91SAM9261_ID_PIOA,
195 .offset = AT91_PIOA,
196 .clock = &pioA_clk,
197 }, {
198 .id = AT91SAM9261_ID_PIOB,
199 .offset = AT91_PIOB,
200 .clock = &pioB_clk,
201 }, {
202 .id = AT91SAM9261_ID_PIOC,
203 .offset = AT91_PIOC,
204 .clock = &pioC_clk,
205 }
206};
207
208static void at91sam9261_reset(void)
209{
210#warning "Implement CPU reset"
211}
212
213
214/* --------------------------------------------------------------------
215 * AT91SAM9261 processor initialization
216 * -------------------------------------------------------------------- */
217
218void __init at91sam9261_initialize(unsigned long main_clock)
219{
220 /* Map peripherals */
221 iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
222
223 at91_arch_reset = at91sam9261_reset;
224 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
225 | (1 << AT91SAM9261_ID_IRQ2);
226
227 /* Init clock subsystem */
228 at91_clock_init(main_clock);
229
230 /* Register the processor-specific clocks */
231 at91sam9261_register_clocks();
232
233 /* Register GPIO subsystem */
234 at91_gpio_init(at91sam9261_gpio, 3);
235}
236
237/* --------------------------------------------------------------------
238 * Interrupt initialization
239 * -------------------------------------------------------------------- */
240
241/*
242 * The default interrupt priority levels (0 = lowest, 7 = highest).
243 */
244static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
245 7, /* Advanced Interrupt Controller */
246 7, /* System Peripherals */
247 0, /* Parallel IO Controller A */
248 0, /* Parallel IO Controller B */
249 0, /* Parallel IO Controller C */
250 0,
251 6, /* USART 0 */
252 6, /* USART 1 */
253 6, /* USART 2 */
254 0, /* Multimedia Card Interface */
255 4, /* USB Device Port */
256 0, /* Two-Wire Interface */
257 6, /* Serial Peripheral Interface 0 */
258 6, /* Serial Peripheral Interface 1 */
259 5, /* Serial Synchronous Controller 0 */
260 5, /* Serial Synchronous Controller 1 */
261 5, /* Serial Synchronous Controller 2 */
262 0, /* Timer Counter 0 */
263 0, /* Timer Counter 1 */
264 0, /* Timer Counter 2 */
265 3, /* USB Host port */
266 3, /* LCD Controller */
267 0,
268 0,
269 0,
270 0,
271 0,
272 0,
273 0,
274 0, /* Advanced Interrupt Controller */
275 0, /* Advanced Interrupt Controller */
276 0, /* Advanced Interrupt Controller */
277};
278
279void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])
280{
281 if (!priority)
282 priority = at91sam9261_default_irq_priority;
283
284 /* Initialize the AIC interrupt controller */
285 at91_aic_init(priority);
286
287 /* Enable GPIO interrupts */
288 at91_gpio_irq_setup();
289}
diff --git a/arch/arm/mach-at91rm9200/at91sam9261_devices.c b/arch/arm/mach-at91rm9200/at91sam9261_devices.c
new file mode 100644
index 000000000000..ed1d79081b35
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam9261_devices.c
@@ -0,0 +1,741 @@
1/*
2 * arch/arm/mach-at91rm9200/at91sam9261_devices.c
3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
16#include <linux/platform_device.h>
17
18#include <asm/arch/board.h>
19#include <asm/arch/gpio.h>
20#include <asm/arch/at91sam9261.h>
21#include <asm/arch/at91sam9261_matrix.h>
22#include <asm/arch/at91sam926x_mc.h>
23
24#include "generic.h"
25
26#define SZ_512 0x00000200
27#define SZ_256 0x00000100
28#define SZ_16 0x00000010
29
30/* --------------------------------------------------------------------
31 * USB Host
32 * -------------------------------------------------------------------- */
33
34#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
35static u64 ohci_dmamask = 0xffffffffUL;
36static struct at91_usbh_data usbh_data;
37
38static struct resource usbh_resources[] = {
39 [0] = {
40 .start = AT91SAM9261_UHP_BASE,
41 .end = AT91SAM9261_UHP_BASE + SZ_1M - 1,
42 .flags = IORESOURCE_MEM,
43 },
44 [1] = {
45 .start = AT91SAM9261_ID_UHP,
46 .end = AT91SAM9261_ID_UHP,
47 .flags = IORESOURCE_IRQ,
48 },
49};
50
51static struct platform_device at91sam9261_usbh_device = {
52 .name = "at91_ohci",
53 .id = -1,
54 .dev = {
55 .dma_mask = &ohci_dmamask,
56 .coherent_dma_mask = 0xffffffff,
57 .platform_data = &usbh_data,
58 },
59 .resource = usbh_resources,
60 .num_resources = ARRAY_SIZE(usbh_resources),
61};
62
63void __init at91_add_device_usbh(struct at91_usbh_data *data)
64{
65 if (!data)
66 return;
67
68 usbh_data = *data;
69 platform_device_register(&at91sam9261_usbh_device);
70}
71#else
72void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
73#endif
74
75
76/* --------------------------------------------------------------------
77 * USB Device (Gadget)
78 * -------------------------------------------------------------------- */
79
80#ifdef CONFIG_USB_GADGET_AT91
81static struct at91_udc_data udc_data;
82
83static struct resource udc_resources[] = {
84 [0] = {
85 .start = AT91SAM9261_BASE_UDP,
86 .end = AT91SAM9261_BASE_UDP + SZ_16K - 1,
87 .flags = IORESOURCE_MEM,
88 },
89 [1] = {
90 .start = AT91SAM9261_ID_UDP,
91 .end = AT91SAM9261_ID_UDP,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static struct platform_device at91sam9261_udc_device = {
97 .name = "at91_udc",
98 .id = -1,
99 .dev = {
100 .platform_data = &udc_data,
101 },
102 .resource = udc_resources,
103 .num_resources = ARRAY_SIZE(udc_resources),
104};
105
106void __init at91_add_device_udc(struct at91_udc_data *data)
107{
108 unsigned long x;
109
110 if (!data)
111 return;
112
113 if (data->vbus_pin) {
114 at91_set_gpio_input(data->vbus_pin, 0);
115 at91_set_deglitch(data->vbus_pin, 1);
116 }
117
118 /* Pullup pin is handled internally */
119 x = at91_sys_read(AT91_MATRIX_USBPUCR);
120 at91_sys_write(AT91_MATRIX_USBPUCR, x | AT91_MATRIX_USBPUCR_PUON);
121
122 udc_data = *data;
123 platform_device_register(&at91sam9261_udc_device);
124}
125#else
126void __init at91_add_device_udc(struct at91_udc_data *data) {}
127#endif
128
129/* --------------------------------------------------------------------
130 * MMC / SD
131 * -------------------------------------------------------------------- */
132
133#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
134static u64 mmc_dmamask = 0xffffffffUL;
135static struct at91_mmc_data mmc_data;
136
137static struct resource mmc_resources[] = {
138 [0] = {
139 .start = AT91SAM9261_BASE_MCI,
140 .end = AT91SAM9261_BASE_MCI + SZ_16K - 1,
141 .flags = IORESOURCE_MEM,
142 },
143 [1] = {
144 .start = AT91SAM9261_ID_MCI,
145 .end = AT91SAM9261_ID_MCI,
146 .flags = IORESOURCE_IRQ,
147 },
148};
149
150static struct platform_device at91sam9261_mmc_device = {
151 .name = "at91_mci",
152 .id = -1,
153 .dev = {
154 .dma_mask = &mmc_dmamask,
155 .coherent_dma_mask = 0xffffffff,
156 .platform_data = &mmc_data,
157 },
158 .resource = mmc_resources,
159 .num_resources = ARRAY_SIZE(mmc_resources),
160};
161
162void __init at91_add_device_mmc(struct at91_mmc_data *data)
163{
164 if (!data)
165 return;
166
167 /* input/irq */
168 if (data->det_pin) {
169 at91_set_gpio_input(data->det_pin, 1);
170 at91_set_deglitch(data->det_pin, 1);
171 }
172 if (data->wp_pin)
173 at91_set_gpio_input(data->wp_pin, 1);
174 if (data->vcc_pin)
175 at91_set_gpio_output(data->vcc_pin, 0);
176
177 /* CLK */
178 at91_set_B_periph(AT91_PIN_PA2, 0);
179
180 /* CMD */
181 at91_set_B_periph(AT91_PIN_PA1, 1);
182
183 /* DAT0, maybe DAT1..DAT3 */
184 at91_set_B_periph(AT91_PIN_PA0, 1);
185 if (data->wire4) {
186 at91_set_B_periph(AT91_PIN_PA4, 1);
187 at91_set_B_periph(AT91_PIN_PA5, 1);
188 at91_set_B_periph(AT91_PIN_PA6, 1);
189 }
190
191 mmc_data = *data;
192 platform_device_register(&at91sam9261_mmc_device);
193}
194#else
195void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
196#endif
197
198
199/* --------------------------------------------------------------------
200 * NAND / SmartMedia
201 * -------------------------------------------------------------------- */
202
203#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
204static struct at91_nand_data nand_data;
205
206#define NAND_BASE AT91_CHIPSELECT_3
207
208static struct resource nand_resources[] = {
209 {
210 .start = NAND_BASE,
211 .end = NAND_BASE + SZ_256M - 1,
212 .flags = IORESOURCE_MEM,
213 }
214};
215
216static struct platform_device at91_nand_device = {
217 .name = "at91_nand",
218 .id = -1,
219 .dev = {
220 .platform_data = &nand_data,
221 },
222 .resource = nand_resources,
223 .num_resources = ARRAY_SIZE(nand_resources),
224};
225
226void __init at91_add_device_nand(struct at91_nand_data *data)
227{
228 unsigned long csa, mode;
229
230 if (!data)
231 return;
232
233 csa = at91_sys_read(AT91_MATRIX_EBICSA);
234 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC);
235
236 /* set the bus interface characteristics */
237 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
238 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
239
240 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
241 | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
242
243 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
244
245 if (data->bus_width_16)
246 mode = AT91_SMC_DBW_16;
247 else
248 mode = AT91_SMC_DBW_8;
249 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
250
251 /* enable pin */
252 if (data->enable_pin)
253 at91_set_gpio_output(data->enable_pin, 1);
254
255 /* ready/busy pin */
256 if (data->rdy_pin)
257 at91_set_gpio_input(data->rdy_pin, 1);
258
259 /* card detect pin */
260 if (data->det_pin)
261 at91_set_gpio_input(data->det_pin, 1);
262
263 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
264 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
265
266 nand_data = *data;
267 platform_device_register(&at91_nand_device);
268}
269
270#else
271void __init at91_add_device_nand(struct at91_nand_data *data) {}
272#endif
273
274
275/* --------------------------------------------------------------------
276 * TWI (i2c)
277 * -------------------------------------------------------------------- */
278
279#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
280
281static struct resource twi_resources[] = {
282 [0] = {
283 .start = AT91SAM9261_BASE_TWI,
284 .end = AT91SAM9261_BASE_TWI + SZ_16K - 1,
285 .flags = IORESOURCE_MEM,
286 },
287 [1] = {
288 .start = AT91SAM9261_ID_TWI,
289 .end = AT91SAM9261_ID_TWI,
290 .flags = IORESOURCE_IRQ,
291 },
292};
293
294static struct platform_device at91sam9261_twi_device = {
295 .name = "at91_i2c",
296 .id = -1,
297 .resource = twi_resources,
298 .num_resources = ARRAY_SIZE(twi_resources),
299};
300
301void __init at91_add_device_i2c(void)
302{
303 /* pins used for TWI interface */
304 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
305 at91_set_multi_drive(AT91_PIN_PA7, 1);
306
307 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
308 at91_set_multi_drive(AT91_PIN_PA8, 1);
309
310 platform_device_register(&at91sam9261_twi_device);
311}
312#else
313void __init at91_add_device_i2c(void) {}
314#endif
315
316
317/* --------------------------------------------------------------------
318 * SPI
319 * -------------------------------------------------------------------- */
320
321#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
322static u64 spi_dmamask = 0xffffffffUL;
323
324static struct resource spi0_resources[] = {
325 [0] = {
326 .start = AT91SAM9261_BASE_SPI0,
327 .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
328 .flags = IORESOURCE_MEM,
329 },
330 [1] = {
331 .start = AT91SAM9261_ID_SPI0,
332 .end = AT91SAM9261_ID_SPI0,
333 .flags = IORESOURCE_IRQ,
334 },
335};
336
337static struct platform_device at91sam9261_spi0_device = {
338 .name = "atmel_spi",
339 .id = 0,
340 .dev = {
341 .dma_mask = &spi_dmamask,
342 .coherent_dma_mask = 0xffffffff,
343 },
344 .resource = spi0_resources,
345 .num_resources = ARRAY_SIZE(spi0_resources),
346};
347
348static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
349
350static struct resource spi1_resources[] = {
351 [0] = {
352 .start = AT91SAM9261_BASE_SPI1,
353 .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
354 .flags = IORESOURCE_MEM,
355 },
356 [1] = {
357 .start = AT91SAM9261_ID_SPI1,
358 .end = AT91SAM9261_ID_SPI1,
359 .flags = IORESOURCE_IRQ,
360 },
361};
362
363static struct platform_device at91sam9261_spi1_device = {
364 .name = "atmel_spi",
365 .id = 1,
366 .dev = {
367 .dma_mask = &spi_dmamask,
368 .coherent_dma_mask = 0xffffffff,
369 },
370 .resource = spi1_resources,
371 .num_resources = ARRAY_SIZE(spi1_resources),
372};
373
374static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
375
376void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
377{
378 int i;
379 unsigned long cs_pin;
380 short enable_spi0 = 0;
381 short enable_spi1 = 0;
382
383 /* Choose SPI chip-selects */
384 for (i = 0; i < nr_devices; i++) {
385 if (devices[i].controller_data)
386 cs_pin = (unsigned long) devices[i].controller_data;
387 else if (devices[i].bus_num == 0)
388 cs_pin = spi0_standard_cs[devices[i].chip_select];
389 else
390 cs_pin = spi1_standard_cs[devices[i].chip_select];
391
392 if (devices[i].bus_num == 0)
393 enable_spi0 = 1;
394 else
395 enable_spi1 = 1;
396
397 /* enable chip-select pin */
398 at91_set_gpio_output(cs_pin, 1);
399
400 /* pass chip-select pin to driver */
401 devices[i].controller_data = (void *) cs_pin;
402 }
403
404 spi_register_board_info(devices, nr_devices);
405
406 /* Configure SPI bus(es) */
407 if (enable_spi0) {
408 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
409 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
410 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
411
412 at91_clock_associate("spi0_clk", &at91sam9261_spi0_device.dev, "spi_clk");
413 platform_device_register(&at91sam9261_spi0_device);
414 }
415 if (enable_spi1) {
416 at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
417 at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
418 at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
419
420 at91_clock_associate("spi1_clk", &at91sam9261_spi1_device.dev, "spi_clk");
421 platform_device_register(&at91sam9261_spi1_device);
422 }
423}
424#else
425void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
426#endif
427
428
429/* --------------------------------------------------------------------
430 * LCD Controller
431 * -------------------------------------------------------------------- */
432
433#if defined(CONFIG_FB_AT91) || defined(CONFIG_FB_AT91_MODULE)
434static u64 lcdc_dmamask = 0xffffffffUL;
435static struct at91fb_info lcdc_data;
436
437static struct resource lcdc_resources[] = {
438 [0] = {
439 .start = AT91SAM9261_LCDC_BASE,
440 .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
441 .flags = IORESOURCE_MEM,
442 },
443 [1] = {
444 .start = AT91SAM9261_ID_LCDC,
445 .end = AT91SAM9261_ID_LCDC,
446 .flags = IORESOURCE_IRQ,
447 },
448#if defined(CONFIG_FB_INTSRAM)
449 [2] = {
450 .start = AT91SAM9261_SRAM_BASE,
451 .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
452 .flags = IORESOURCE_MEM,
453 },
454#endif
455};
456
457static struct platform_device at91_lcdc_device = {
458 .name = "at91-fb",
459 .id = 0,
460 .dev = {
461 .dma_mask = &lcdc_dmamask,
462 .coherent_dma_mask = 0xffffffff,
463 .platform_data = &lcdc_data,
464 },
465 .resource = lcdc_resources,
466 .num_resources = ARRAY_SIZE(lcdc_resources),
467};
468
469void __init at91_add_device_lcdc(struct at91fb_info *data)
470{
471 if (!data) {
472 return;
473 }
474
475 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
476 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
477 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
478 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
479 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
480 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
481 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
482 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
483 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
484 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
485 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
486 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
487 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
488 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
489 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
490 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
491 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
492 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
493 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
494 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
495 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
496 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
497
498 lcdc_data = *data;
499 platform_device_register(&at91_lcdc_device);
500}
501#else
502void __init at91_add_device_lcdc(struct at91fb_info *data) {}
503#endif
504
505
506/* --------------------------------------------------------------------
507 * LEDs
508 * -------------------------------------------------------------------- */
509
510#if defined(CONFIG_LEDS)
511u8 at91_leds_cpu;
512u8 at91_leds_timer;
513
514void __init at91_init_leds(u8 cpu_led, u8 timer_led)
515{
516 at91_leds_cpu = cpu_led;
517 at91_leds_timer = timer_led;
518}
519#else
520void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
521#endif
522
523
524/* --------------------------------------------------------------------
525 * UART
526 * -------------------------------------------------------------------- */
527
528#if defined(CONFIG_SERIAL_ATMEL)
529static struct resource dbgu_resources[] = {
530 [0] = {
531 .start = AT91_VA_BASE_SYS + AT91_DBGU,
532 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
533 .flags = IORESOURCE_MEM,
534 },
535 [1] = {
536 .start = AT91_ID_SYS,
537 .end = AT91_ID_SYS,
538 .flags = IORESOURCE_IRQ,
539 },
540};
541
542static struct atmel_uart_data dbgu_data = {
543 .use_dma_tx = 0,
544 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
545 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
546};
547
548static struct platform_device at91sam9261_dbgu_device = {
549 .name = "atmel_usart",
550 .id = 0,
551 .dev = {
552 .platform_data = &dbgu_data,
553 .coherent_dma_mask = 0xffffffff,
554 },
555 .resource = dbgu_resources,
556 .num_resources = ARRAY_SIZE(dbgu_resources),
557};
558
559static inline void configure_dbgu_pins(void)
560{
561 at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
562 at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
563}
564
565static struct resource uart0_resources[] = {
566 [0] = {
567 .start = AT91SAM9261_BASE_US0,
568 .end = AT91SAM9261_BASE_US0 + SZ_16K - 1,
569 .flags = IORESOURCE_MEM,
570 },
571 [1] = {
572 .start = AT91SAM9261_ID_US0,
573 .end = AT91SAM9261_ID_US0,
574 .flags = IORESOURCE_IRQ,
575 },
576};
577
578static struct atmel_uart_data uart0_data = {
579 .use_dma_tx = 1,
580 .use_dma_rx = 1,
581};
582
583static struct platform_device at91sam9261_uart0_device = {
584 .name = "atmel_usart",
585 .id = 1,
586 .dev = {
587 .platform_data = &uart0_data,
588 .coherent_dma_mask = 0xffffffff,
589 },
590 .resource = uart0_resources,
591 .num_resources = ARRAY_SIZE(uart0_resources),
592};
593
594static inline void configure_usart0_pins(void)
595{
596 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
597 at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
598 at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
599 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
600}
601
602static struct resource uart1_resources[] = {
603 [0] = {
604 .start = AT91SAM9261_BASE_US1,
605 .end = AT91SAM9261_BASE_US1 + SZ_16K - 1,
606 .flags = IORESOURCE_MEM,
607 },
608 [1] = {
609 .start = AT91SAM9261_ID_US1,
610 .end = AT91SAM9261_ID_US1,
611 .flags = IORESOURCE_IRQ,
612 },
613};
614
615static struct atmel_uart_data uart1_data = {
616 .use_dma_tx = 1,
617 .use_dma_rx = 1,
618};
619
620static struct platform_device at91sam9261_uart1_device = {
621 .name = "atmel_usart",
622 .id = 2,
623 .dev = {
624 .platform_data = &uart1_data,
625 .coherent_dma_mask = 0xffffffff,
626 },
627 .resource = uart1_resources,
628 .num_resources = ARRAY_SIZE(uart1_resources),
629};
630
631static inline void configure_usart1_pins(void)
632{
633 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
634 at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
635}
636
637static struct resource uart2_resources[] = {
638 [0] = {
639 .start = AT91SAM9261_BASE_US2,
640 .end = AT91SAM9261_BASE_US2 + SZ_16K - 1,
641 .flags = IORESOURCE_MEM,
642 },
643 [1] = {
644 .start = AT91SAM9261_ID_US2,
645 .end = AT91SAM9261_ID_US2,
646 .flags = IORESOURCE_IRQ,
647 },
648};
649
650static struct atmel_uart_data uart2_data = {
651 .use_dma_tx = 1,
652 .use_dma_rx = 1,
653};
654
655static struct platform_device at91sam9261_uart2_device = {
656 .name = "atmel_usart",
657 .id = 3,
658 .dev = {
659 .platform_data = &uart2_data,
660 .coherent_dma_mask = 0xffffffff,
661 },
662 .resource = uart2_resources,
663 .num_resources = ARRAY_SIZE(uart2_resources),
664};
665
666static inline void configure_usart2_pins(void)
667{
668 at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
669 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
670}
671
672struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
673struct platform_device *atmel_default_console_device; /* the serial console device */
674
675void __init at91_init_serial(struct at91_uart_config *config)
676{
677 int i;
678
679 /* Fill in list of supported UARTs */
680 for (i = 0; i < config->nr_tty; i++) {
681 switch (config->tty_map[i]) {
682 case 0:
683 configure_usart0_pins();
684 at91_uarts[i] = &at91sam9261_uart0_device;
685 at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart");
686 break;
687 case 1:
688 configure_usart1_pins();
689 at91_uarts[i] = &at91sam9261_uart1_device;
690 at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart");
691 break;
692 case 2:
693 configure_usart2_pins();
694 at91_uarts[i] = &at91sam9261_uart2_device;
695 at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart");
696 break;
697 case 3:
698 configure_dbgu_pins();
699 at91_uarts[i] = &at91sam9261_dbgu_device;
700 at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart");
701 break;
702 default:
703 continue;
704 }
705 at91_uarts[i]->id = i; /* update ID number to mapped ID */
706 }
707
708 /* Set serial console device */
709 if (config->console_tty < ATMEL_MAX_UART)
710 atmel_default_console_device = at91_uarts[config->console_tty];
711 if (!atmel_default_console_device)
712 printk(KERN_INFO "AT91: No default serial console defined.\n");
713}
714
715void __init at91_add_device_serial(void)
716{
717 int i;
718
719 for (i = 0; i < ATMEL_MAX_UART; i++) {
720 if (at91_uarts[i])
721 platform_device_register(at91_uarts[i]);
722 }
723}
724#else
725void __init at91_init_serial(struct at91_uart_config *config) {}
726void __init at91_add_device_serial(void) {}
727#endif
728
729
730/* -------------------------------------------------------------------- */
731
732/*
733 * These devices are always present and don't need any board-specific
734 * setup.
735 */
736static int __init at91_add_standard_devices(void)
737{
738 return 0;
739}
740
741arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91rm9200/at91sam926x_time.c b/arch/arm/mach-at91rm9200/at91sam926x_time.c
new file mode 100644
index 000000000000..99df5f6ee42e
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam926x_time.c
@@ -0,0 +1,114 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/at91sam926x_time.c
3 *
4 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5 * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/time.h>
18
19#include <asm/hardware.h>
20#include <asm/io.h>
21#include <asm/mach/time.h>
22
23#include <asm/arch/at91_pit.h>
24
25
26#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
27#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
28
29/*
30 * Returns number of microseconds since last timer interrupt. Note that interrupts
31 * will have been disabled by do_gettimeofday()
32 * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
33 * 'tick' is usecs per jiffy (linux/timex.h).
34 */
35static unsigned long at91sam926x_gettimeoffset(void)
36{
37 unsigned long elapsed;
38 unsigned long t = at91_sys_read(AT91_PIT_PIIR);
39
40 elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t); /* hardware clock cycles */
41
42 return (unsigned long)(elapsed * 1000000) / LATCH;
43}
44
45/*
46 * IRQ handler for the timer.
47 */
48static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
49{
50 volatile long nr_ticks;
51
52 if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */
53 write_seqlock(&xtime_lock);
54
55 /* Get number to ticks performed before interrupt and clear PIT interrupt */
56 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
57 do {
58 timer_tick();
59 nr_ticks--;
60 } while (nr_ticks);
61
62 write_sequnlock(&xtime_lock);
63 return IRQ_HANDLED;
64 } else
65 return IRQ_NONE; /* not handled */
66}
67
68static struct irqaction at91sam926x_timer_irq = {
69 .name = "at91_tick",
70 .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER,
71 .handler = at91sam926x_timer_interrupt
72};
73
74void at91sam926x_timer_reset(void)
75{
76 /* Disable timer */
77 at91_sys_write(AT91_PIT_MR, 0);
78
79 /* Clear any pending interrupts */
80 (void) at91_sys_read(AT91_PIT_PIVR);
81
82 /* Set Period Interval timer and enable its interrupt */
83 at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN);
84}
85
86/*
87 * Set up timer interrupt.
88 */
89void __init at91sam926x_timer_init(void)
90{
91 /* Initialize and enable the timer */
92 at91sam926x_timer_reset();
93
94 /* Make IRQs happen for the system timer. */
95 setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
96}
97
98#ifdef CONFIG_PM
99static void at91sam926x_timer_suspend(void)
100{
101 /* Disable timer */
102 at91_sys_write(AT91_PIT_MR, 0);
103}
104#else
105#define at91sam926x_timer_suspend NULL
106#endif
107
108struct sys_timer at91sam926x_timer = {
109 .init = at91sam926x_timer_init,
110 .offset = at91sam926x_gettimeoffset,
111 .suspend = at91sam926x_timer_suspend,
112 .resume = at91sam926x_timer_reset,
113};
114
diff --git a/arch/arm/mach-at91rm9200/board-carmeva.c b/arch/arm/mach-at91rm9200/board-carmeva.c
index 98208740e7c5..654f0379550a 100644
--- a/arch/arm/mach-at91rm9200/board-carmeva.c
+++ b/arch/arm/mach-at91rm9200/board-carmeva.c
@@ -65,7 +65,6 @@ static void __init carmeva_init_irq(void)
65 at91rm9200_init_interrupts(NULL); 65 at91rm9200_init_interrupts(NULL);
66} 66}
67 67
68
69static struct at91_eth_data __initdata carmeva_eth_data = { 68static struct at91_eth_data __initdata carmeva_eth_data = {
70 .phy_irq_pin = AT91_PIN_PC4, 69 .phy_irq_pin = AT91_PIN_PC4,
71 .is_rmii = 1, 70 .is_rmii = 1,
@@ -89,8 +88,33 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
89// }; 88// };
90 89
91static struct at91_mmc_data __initdata carmeva_mmc_data = { 90static struct at91_mmc_data __initdata carmeva_mmc_data = {
92 .is_b = 0, 91 .slot_b = 0,
93 .wire4 = 1, 92 .wire4 = 1,
93 .det_pin = AT91_PIN_PB10,
94 .wp_pin = AT91_PIN_PC14,
95};
96
97static struct spi_board_info carmeva_spi_devices[] = {
98 { /* DataFlash chip */
99 .modalias = "mtd_dataflash",
100 .chip_select = 0,
101 .max_speed_hz = 10 * 1000 * 1000,
102 },
103 { /* User accessable spi - cs1 (250KHz) */
104 .modalias = "spi-cs1",
105 .chip_select = 1,
106 .max_speed_hz = 250 * 1000,
107 },
108 { /* User accessable spi - cs2 (1MHz) */
109 .modalias = "spi-cs2",
110 .chip_select = 2,
111 .max_speed_hz = 1 * 1000 * 1000,
112 },
113 { /* User accessable spi - cs3 (10MHz) */
114 .modalias = "spi-cs3",
115 .chip_select = 3,
116 .max_speed_hz = 10 * 1000 * 1000,
117 },
94}; 118};
95 119
96static void __init carmeva_board_init(void) 120static void __init carmeva_board_init(void)
@@ -105,10 +129,10 @@ static void __init carmeva_board_init(void)
105 at91_add_device_udc(&carmeva_udc_data); 129 at91_add_device_udc(&carmeva_udc_data);
106 /* I2C */ 130 /* I2C */
107 at91_add_device_i2c(); 131 at91_add_device_i2c();
132 /* SPI */
133 at91_add_device_spi(carmeva_spi_devices, ARRAY_SIZE(carmeva_spi_devices));
108 /* Compact Flash */ 134 /* Compact Flash */
109// at91_add_device_cf(&carmeva_cf_data); 135// at91_add_device_cf(&carmeva_cf_data);
110 /* SPI */
111// at91_add_device_spi(NULL, 0);
112 /* MMC */ 136 /* MMC */
113 at91_add_device_mmc(&carmeva_mmc_data); 137 at91_add_device_mmc(&carmeva_mmc_data);
114} 138}
diff --git a/arch/arm/mach-at91rm9200/board-csb337.c b/arch/arm/mach-at91rm9200/board-csb337.c
index 8eeae491ce71..b8bb8052607a 100644
--- a/arch/arm/mach-at91rm9200/board-csb337.c
+++ b/arch/arm/mach-at91rm9200/board-csb337.c
@@ -99,7 +99,7 @@ static struct at91_cf_data __initdata csb337_cf_data = {
99 99
100static struct at91_mmc_data __initdata csb337_mmc_data = { 100static struct at91_mmc_data __initdata csb337_mmc_data = {
101 .det_pin = AT91_PIN_PD5, 101 .det_pin = AT91_PIN_PD5,
102 .is_b = 0, 102 .slot_b = 0,
103 .wire4 = 1, 103 .wire4 = 1,
104 .wp_pin = AT91_PIN_PD6, 104 .wp_pin = AT91_PIN_PD6,
105}; 105};
diff --git a/arch/arm/mach-at91rm9200/board-dk.c b/arch/arm/mach-at91rm9200/board-dk.c
index c699f3984d4b..7522bf91bce8 100644
--- a/arch/arm/mach-at91rm9200/board-dk.c
+++ b/arch/arm/mach-at91rm9200/board-dk.c
@@ -27,6 +27,7 @@
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/spi/spi.h> 29#include <linux/spi/spi.h>
30#include <linux/mtd/physmap.h>
30 31
31#include <asm/hardware.h> 32#include <asm/hardware.h>
32#include <asm/setup.h> 33#include <asm/setup.h>
@@ -39,6 +40,7 @@
39 40
40#include <asm/arch/board.h> 41#include <asm/arch/board.h>
41#include <asm/arch/gpio.h> 42#include <asm/arch/gpio.h>
43#include <asm/arch/at91rm9200_mc.h>
42 44
43#include "generic.h" 45#include "generic.h"
44 46
@@ -93,7 +95,7 @@ static struct at91_cf_data __initdata dk_cf_data = {
93}; 95};
94 96
95static struct at91_mmc_data __initdata dk_mmc_data = { 97static struct at91_mmc_data __initdata dk_mmc_data = {
96 .is_b = 0, 98 .slot_b = 0,
97 .wire4 = 1, 99 .wire4 = 1,
98}; 100};
99 101
@@ -145,6 +147,30 @@ static struct at91_nand_data __initdata dk_nand_data = {
145 .partition_info = nand_partitions, 147 .partition_info = nand_partitions,
146}; 148};
147 149
150#define DK_FLASH_BASE AT91_CHIPSELECT_0
151#define DK_FLASH_SIZE 0x200000
152
153static struct physmap_flash_data dk_flash_data = {
154 .width = 2,
155};
156
157static struct resource dk_flash_resource = {
158 .start = DK_FLASH_BASE,
159 .end = DK_FLASH_BASE + DK_FLASH_SIZE - 1,
160 .flags = IORESOURCE_MEM,
161};
162
163static struct platform_device dk_flash = {
164 .name = "physmap-flash",
165 .id = 0,
166 .dev = {
167 .platform_data = &dk_flash_data,
168 },
169 .resource = &dk_flash_resource,
170 .num_resources = 1,
171};
172
173
148static void __init dk_board_init(void) 174static void __init dk_board_init(void)
149{ 175{
150 /* Serial */ 176 /* Serial */
@@ -172,6 +198,8 @@ static void __init dk_board_init(void)
172#endif 198#endif
173 /* NAND */ 199 /* NAND */
174 at91_add_device_nand(&dk_nand_data); 200 at91_add_device_nand(&dk_nand_data);
201 /* NOR Flash */
202 platform_device_register(&dk_flash);
175 /* VGA */ 203 /* VGA */
176// dk_add_device_video(); 204// dk_add_device_video();
177} 205}
diff --git a/arch/arm/mach-at91rm9200/board-eb9200.c b/arch/arm/mach-at91rm9200/board-eb9200.c
index 65e867ba2df3..80b72cf7264c 100644
--- a/arch/arm/mach-at91rm9200/board-eb9200.c
+++ b/arch/arm/mach-at91rm9200/board-eb9200.c
@@ -87,7 +87,7 @@ static struct at91_cf_data __initdata eb9200_cf_data = {
87}; 87};
88 88
89static struct at91_mmc_data __initdata eb9200_mmc_data = { 89static struct at91_mmc_data __initdata eb9200_mmc_data = {
90 .is_b = 0, 90 .slot_b = 0,
91 .wire4 = 1, 91 .wire4 = 1,
92}; 92};
93 93
diff --git a/arch/arm/mach-at91rm9200/board-ek.c b/arch/arm/mach-at91rm9200/board-ek.c
index 830eb7932178..c4fdb415f20e 100644
--- a/arch/arm/mach-at91rm9200/board-ek.c
+++ b/arch/arm/mach-at91rm9200/board-ek.c
@@ -27,6 +27,7 @@
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/spi/spi.h> 29#include <linux/spi/spi.h>
30#include <linux/mtd/physmap.h>
30 31
31#include <asm/hardware.h> 32#include <asm/hardware.h>
32#include <asm/setup.h> 33#include <asm/setup.h>
@@ -39,6 +40,7 @@
39 40
40#include <asm/arch/board.h> 41#include <asm/arch/board.h>
41#include <asm/arch/gpio.h> 42#include <asm/arch/gpio.h>
43#include <asm/arch/at91rm9200_mc.h>
42 44
43#include "generic.h" 45#include "generic.h"
44 46
@@ -87,7 +89,7 @@ static struct at91_udc_data __initdata ek_udc_data = {
87 89
88static struct at91_mmc_data __initdata ek_mmc_data = { 90static struct at91_mmc_data __initdata ek_mmc_data = {
89 .det_pin = AT91_PIN_PB27, 91 .det_pin = AT91_PIN_PB27,
90 .is_b = 0, 92 .slot_b = 0,
91 .wire4 = 1, 93 .wire4 = 1,
92 .wp_pin = AT91_PIN_PA17, 94 .wp_pin = AT91_PIN_PA17,
93}; 95};
@@ -107,6 +109,30 @@ static struct spi_board_info ek_spi_devices[] = {
107#endif 109#endif
108}; 110};
109 111
112#define EK_FLASH_BASE AT91_CHIPSELECT_0
113#define EK_FLASH_SIZE 0x200000
114
115static struct physmap_flash_data ek_flash_data = {
116 .width = 2,
117};
118
119static struct resource ek_flash_resource = {
120 .start = EK_FLASH_BASE,
121 .end = EK_FLASH_BASE + EK_FLASH_SIZE - 1,
122 .flags = IORESOURCE_MEM,
123};
124
125static struct platform_device ek_flash = {
126 .name = "physmap-flash",
127 .id = 0,
128 .dev = {
129 .platform_data = &ek_flash_data,
130 },
131 .resource = &ek_flash_resource,
132 .num_resources = 1,
133};
134
135
110static void __init ek_board_init(void) 136static void __init ek_board_init(void)
111{ 137{
112 /* Serial */ 138 /* Serial */
@@ -130,6 +156,8 @@ static void __init ek_board_init(void)
130 at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */ 156 at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
131 at91_add_device_mmc(&ek_mmc_data); 157 at91_add_device_mmc(&ek_mmc_data);
132#endif 158#endif
159 /* NOR Flash */
160 platform_device_register(&ek_flash);
133 /* VGA */ 161 /* VGA */
134// ek_add_device_video(); 162// ek_add_device_video();
135} 163}
diff --git a/arch/arm/mach-at91rm9200/board-kb9202.c b/arch/arm/mach-at91rm9200/board-kb9202.c
index 35a954a44b1b..759d8191854f 100644
--- a/arch/arm/mach-at91rm9200/board-kb9202.c
+++ b/arch/arm/mach-at91rm9200/board-kb9202.c
@@ -84,7 +84,7 @@ static struct at91_udc_data __initdata kb9202_udc_data = {
84 84
85static struct at91_mmc_data __initdata kb9202_mmc_data = { 85static struct at91_mmc_data __initdata kb9202_mmc_data = {
86 .det_pin = AT91_PIN_PB2, 86 .det_pin = AT91_PIN_PB2,
87 .is_b = 0, 87 .slot_b = 0,
88 .wire4 = 1, 88 .wire4 = 1,
89}; 89};
90 90
diff --git a/arch/arm/mach-at91rm9200/board-sam9260ek.c b/arch/arm/mach-at91rm9200/board-sam9260ek.c
new file mode 100644
index 000000000000..ffca9bdec37b
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/board-sam9260ek.c
@@ -0,0 +1,201 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/board-ek.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/spi/spi.h>
28
29#include <asm/hardware.h>
30#include <asm/setup.h>
31#include <asm/mach-types.h>
32#include <asm/irq.h>
33
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
37
38#include <asm/arch/board.h>
39#include <asm/arch/gpio.h>
40#include <asm/arch/at91sam926x_mc.h>
41
42#include "generic.h"
43
44
45/*
46 * Serial port configuration.
47 * 0 .. 5 = USART0 .. USART5
48 * 6 = DBGU
49 */
50static struct at91_uart_config __initdata ek_uart_config = {
51 .console_tty = 0, /* ttyS0 */
52 .nr_tty = 3,
53 .tty_map = { 6, 0, 1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */
54};
55
56static void __init ek_map_io(void)
57{
58 /* Initialize processor: 18.432 MHz crystal */
59 at91sam9260_initialize(18432000);
60
61 /* Setup the serial ports and console */
62 at91_init_serial(&ek_uart_config);
63}
64
65static void __init ek_init_irq(void)
66{
67 at91sam9260_init_interrupts(NULL);
68}
69
70
71/*
72 * USB Host port
73 */
74static struct at91_usbh_data __initdata ek_usbh_data = {
75 .ports = 2,
76};
77
78/*
79 * USB Device port
80 */
81static struct at91_udc_data __initdata ek_udc_data = {
82 .vbus_pin = AT91_PIN_PC5,
83 .pullup_pin = 0, /* pull-up driven by UDC */
84};
85
86
87/*
88 * SPI devices.
89 */
90static struct spi_board_info ek_spi_devices[] = {
91#if !defined(CONFIG_MMC_AT91)
92 { /* DataFlash chip */
93 .modalias = "mtd_dataflash",
94 .chip_select = 1,
95 .max_speed_hz = 15 * 1000 * 1000,
96 .bus_num = 0,
97 },
98#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
99 { /* DataFlash card */
100 .modalias = "mtd_dataflash",
101 .chip_select = 0,
102 .max_speed_hz = 15 * 1000 * 1000,
103 .bus_num = 0,
104 },
105#endif
106#endif
107#if defined(CONFIG_SND_AT73C213)
108 { /* AT73C213 DAC */
109 .modalias = "snd_at73c213",
110 .chip_select = 0,
111 .max_speed_hz = 10 * 1000 * 1000,
112 .bus_num = 1,
113 },
114#endif
115};
116
117
118/*
119 * MACB Ethernet device
120 */
121static struct __initdata eth_platform_data ek_macb_data = {
122 .is_rmii = 1,
123};
124
125
126/*
127 * NAND flash
128 */
129static struct mtd_partition __initdata ek_nand_partition[] = {
130 {
131 .name = "Partition 1",
132 .offset = 0,
133 .size = 256 * 1024,
134 },
135 {
136 .name = "Partition 2",
137 .offset = 256 * 1024,
138 .size = MTDPART_SIZ_FULL,
139 },
140};
141
142static struct mtd_partition *nand_partitions(int size, int *num_partitions)
143{
144 *num_partitions = ARRAY_SIZE(ek_nand_partition);
145 return ek_nand_partition;
146}
147
148static struct at91_nand_data __initdata ek_nand_data = {
149 .ale = 21,
150 .cle = 22,
151// .det_pin = ... not connected
152 .rdy_pin = AT91_PIN_PC13,
153 .enable_pin = AT91_PIN_PC14,
154 .partition_info = nand_partitions,
155#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
156 .bus_width_16 = 1,
157#else
158 .bus_width_16 = 0,
159#endif
160};
161
162
163/*
164 * MCI (SD/MMC)
165 */
166static struct at91_mmc_data __initdata ek_mmc_data = {
167 .slot_b = 1,
168 .wire4 = 1,
169// .det_pin = ... not connected
170// .wp_pin = ... not connected
171// .vcc_pin = ... not connected
172};
173
174static void __init ek_board_init(void)
175{
176 /* Serial */
177 at91_add_device_serial();
178 /* USB Host */
179 at91_add_device_usbh(&ek_usbh_data);
180 /* USB Device */
181 at91_add_device_udc(&ek_udc_data);
182 /* SPI */
183 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
184 /* NAND */
185 at91_add_device_nand(&ek_nand_data);
186 /* Ethernet */
187 at91_add_device_eth(&ek_macb_data);
188 /* MMC */
189 at91_add_device_mmc(&ek_mmc_data);
190}
191
192MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
193 /* Maintainer: Atmel */
194 .phys_io = AT91_BASE_SYS,
195 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
196 .boot_params = AT91_SDRAM_BASE + 0x100,
197 .timer = &at91sam926x_timer,
198 .map_io = ek_map_io,
199 .init_irq = ek_init_irq,
200 .init_machine = ek_board_init,
201MACHINE_END
diff --git a/arch/arm/mach-at91rm9200/board-sam9261ek.c b/arch/arm/mach-at91rm9200/board-sam9261ek.c
new file mode 100644
index 000000000000..30b490d8886b
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/board-sam9261ek.c
@@ -0,0 +1,259 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/board-ek.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/spi/spi.h>
28#include <linux/dm9000.h>
29
30#include <asm/hardware.h>
31#include <asm/setup.h>
32#include <asm/mach-types.h>
33#include <asm/irq.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38
39#include <asm/arch/board.h>
40#include <asm/arch/gpio.h>
41#include <asm/arch/at91sam926x_mc.h>
42
43#include "generic.h"
44
45
46/*
47 * Serial port configuration.
48 * 0 .. 2 = USART0 .. USART2
49 * 3 = DBGU
50 */
51static struct at91_uart_config __initdata ek_uart_config = {
52 .console_tty = 0, /* ttyS0 */
53 .nr_tty = 1,
54 .tty_map = { 3, -1, -1, -1 } /* ttyS0, ..., ttyS3 */
55};
56
57static void __init ek_map_io(void)
58{
59 /* Initialize processor: 18.432 MHz crystal */
60 at91sam9261_initialize(18432000);
61
62 /* Setup the serial ports and console */
63 at91_init_serial(&ek_uart_config);
64}
65
66static void __init ek_init_irq(void)
67{
68 at91sam9261_init_interrupts(NULL);
69}
70
71
72/*
73 * DM9000 ethernet device
74 */
75#if defined(CONFIG_DM9000)
76static struct resource at91sam9261_dm9000_resource[] = {
77 [0] = {
78 .start = AT91_CHIPSELECT_2,
79 .end = AT91_CHIPSELECT_2 + 3,
80 .flags = IORESOURCE_MEM
81 },
82 [1] = {
83 .start = AT91_CHIPSELECT_2 + 0x44,
84 .end = AT91_CHIPSELECT_2 + 0xFF,
85 .flags = IORESOURCE_MEM
86 },
87 [2] = {
88 .start = AT91_PIN_PC11,
89 .end = AT91_PIN_PC11,
90 .flags = IORESOURCE_IRQ
91 }
92};
93
94static struct dm9000_plat_data dm9000_platdata = {
95 .flags = DM9000_PLATF_16BITONLY,
96};
97
98static struct platform_device at91sam9261_dm9000_device = {
99 .name = "dm9000",
100 .id = 0,
101 .num_resources = ARRAY_SIZE(at91sam9261_dm9000_resource),
102 .resource = at91sam9261_dm9000_resource,
103 .dev = {
104 .platform_data = &dm9000_platdata,
105 }
106};
107
108static void __init ek_add_device_dm9000(void)
109{
110 /*
111 * Configure Chip-Select 2 on SMC for the DM9000.
112 * Note: These timings were calculated for MASTER_CLOCK = 100000000
113 * according to the DM9000 timings.
114 */
115 at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
116 at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
117 at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
118 at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
119
120 /* Configure Reset signal as output */
121 at91_set_gpio_output(AT91_PIN_PC10, 0);
122
123 /* Configure Interrupt pin as input, no pull-up */
124 at91_set_gpio_input(AT91_PIN_PC11, 0);
125
126 platform_device_register(&at91sam9261_dm9000_device);
127}
128#else
129static void __init ek_add_device_dm9000(void) {}
130#endif /* CONFIG_DM9000 */
131
132
133/*
134 * USB Host Port
135 */
136static struct at91_usbh_data __initdata ek_usbh_data = {
137 .ports = 2,
138};
139
140
141/*
142 * USB Device Port
143 */
144static struct at91_udc_data __initdata ek_udc_data = {
145 .vbus_pin = AT91_PIN_PB29,
146 .pullup_pin = 0, /* pull-up driven by UDC */
147};
148
149
150/*
151 * MCI (SD/MMC)
152 */
153static struct at91_mmc_data __initdata ek_mmc_data = {
154 .wire4 = 1,
155// .det_pin = ... not connected
156// .wp_pin = ... not connected
157// .vcc_pin = ... not connected
158};
159
160
161/*
162 * NAND flash
163 */
164static struct mtd_partition __initdata ek_nand_partition[] = {
165 {
166 .name = "Partition 1",
167 .offset = 0,
168 .size = 256 * 1024,
169 },
170 {
171 .name = "Partition 2",
172 .offset = 256 * 1024 ,
173 .size = MTDPART_SIZ_FULL,
174 },
175};
176
177static struct mtd_partition *nand_partitions(int size, int *num_partitions)
178{
179 *num_partitions = ARRAY_SIZE(ek_nand_partition);
180 return ek_nand_partition;
181}
182
183static struct at91_nand_data __initdata ek_nand_data = {
184 .ale = 22,
185 .cle = 21,
186// .det_pin = ... not connected
187 .rdy_pin = AT91_PIN_PC15,
188 .enable_pin = AT91_PIN_PC14,
189 .partition_info = nand_partitions,
190#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
191 .bus_width_16 = 1,
192#else
193 .bus_width_16 = 0,
194#endif
195};
196
197/*
198 * SPI devices
199 */
200static struct spi_board_info ek_spi_devices[] = {
201 { /* DataFlash chip */
202 .modalias = "mtd_dataflash",
203 .chip_select = 0,
204 .max_speed_hz = 15 * 1000 * 1000,
205 .bus_num = 0,
206 },
207#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
208 { /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */
209 .modalias = "mtd_dataflash",
210 .chip_select = 3,
211 .max_speed_hz = 15 * 1000 * 1000,
212 .bus_num = 0,
213 },
214#elif defined(CONFIG_SND_AT73C213)
215 { /* AT73C213 DAC */
216 .modalias = "snd_at73c213",
217 .chip_select = 3,
218 .max_speed_hz = 10 * 1000 * 1000,
219 .bus_num = 0,
220 },
221#endif
222};
223
224
225static void __init ek_board_init(void)
226{
227 /* Serial */
228 at91_add_device_serial();
229 /* USB Host */
230 at91_add_device_usbh(&ek_usbh_data);
231 /* USB Device */
232 at91_add_device_udc(&ek_udc_data);
233 /* I2C */
234 at91_add_device_i2c();
235 /* NAND */
236 at91_add_device_nand(&ek_nand_data);
237 /* DM9000 ethernet */
238 ek_add_device_dm9000();
239
240 /* spi0 and mmc/sd share the same PIO pins */
241#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
242 /* SPI */
243 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
244#else
245 /* MMC */
246 at91_add_device_mmc(&ek_mmc_data);
247#endif
248}
249
250MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
251 /* Maintainer: Atmel */
252 .phys_io = AT91_BASE_SYS,
253 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
254 .boot_params = AT91_SDRAM_BASE + 0x100,
255 .timer = &at91sam926x_timer,
256 .map_io = ek_map_io,
257 .init_irq = ek_init_irq,
258 .init_machine = ek_board_init,
259MACHINE_END
diff --git a/arch/arm/mach-at91rm9200/clock.c b/arch/arm/mach-at91rm9200/clock.c
index a43b061a7c85..4dee21fefe5a 100644
--- a/arch/arm/mach-at91rm9200/clock.c
+++ b/arch/arm/mach-at91rm9200/clock.c
@@ -28,6 +28,8 @@
28#include <asm/mach-types.h> 28#include <asm/mach-types.h>
29 29
30#include <asm/hardware.h> 30#include <asm/hardware.h>
31#include <asm/arch/at91_pmc.h>
32#include <asm/arch/cpu.h>
31 33
32#include "clock.h" 34#include "clock.h"
33 35
@@ -41,6 +43,7 @@
41#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) 43#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
42#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) 44#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
43#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL) 45#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
46#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
44 47
45 48
46static LIST_HEAD(clocks); 49static LIST_HEAD(clocks);
@@ -114,13 +117,11 @@ static void pmc_sys_mode(struct clk *clk, int is_on)
114static struct clk udpck = { 117static struct clk udpck = {
115 .name = "udpck", 118 .name = "udpck",
116 .parent = &pllb, 119 .parent = &pllb,
117 .pmc_mask = AT91_PMC_UDP,
118 .mode = pmc_sys_mode, 120 .mode = pmc_sys_mode,
119}; 121};
120static struct clk uhpck = { 122static struct clk uhpck = {
121 .name = "uhpck", 123 .name = "uhpck",
122 .parent = &pllb, 124 .parent = &pllb,
123 .pmc_mask = AT91_PMC_UHP,
124 .mode = pmc_sys_mode, 125 .mode = pmc_sys_mode,
125}; 126};
126 127
@@ -434,6 +435,12 @@ int __init clk_register(struct clk *clk)
434 clk->mode = pmc_periph_mode; 435 clk->mode = pmc_periph_mode;
435 list_add_tail(&clk->node, &clocks); 436 list_add_tail(&clk->node, &clocks);
436 } 437 }
438 else if (clk_is_sys(clk)) {
439 clk->parent = &mck;
440 clk->mode = pmc_sys_mode;
441
442 list_add_tail(&clk->node, &clocks);
443 }
437#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS 444#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
438 else if (clk_is_programmable(clk)) { 445 else if (clk_is_programmable(clk)) {
439 clk->mode = pmc_sys_mode; 446 clk->mode = pmc_sys_mode;
@@ -586,9 +593,21 @@ int __init at91_clock_init(unsigned long main_clock)
586 */ 593 */
587 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; 594 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
588 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); 595 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
589 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP); 596 if (cpu_is_at91rm9200()) {
597 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
598 udpck.pmc_mask = AT91RM9200_PMC_UDP;
599 at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP);
600 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
601 } else if (cpu_is_at91sam9260()) {
602 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
603 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
604 at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP);
605 } else if (cpu_is_at91sam9261()) {
606 uhpck.pmc_mask = (AT91SAM926x_PMC_UHP | AT91_PMC_HCK0);
607 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
608 at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91_PMC_HCK0 | AT91SAM926x_PMC_UDP);
609 }
590 at91_sys_write(AT91_CKGR_PLLBR, 0); 610 at91_sys_write(AT91_CKGR_PLLBR, 0);
591 at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);
592 611
593 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); 612 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
594 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); 613 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
diff --git a/arch/arm/mach-at91rm9200/clock.h b/arch/arm/mach-at91rm9200/clock.h
index 0592e662ab37..b5c7a2eb2d1d 100644
--- a/arch/arm/mach-at91rm9200/clock.h
+++ b/arch/arm/mach-at91rm9200/clock.h
@@ -10,6 +10,7 @@
10#define CLK_TYPE_PLL 0x2 10#define CLK_TYPE_PLL 0x2
11#define CLK_TYPE_PROGRAMMABLE 0x4 11#define CLK_TYPE_PROGRAMMABLE 0x4
12#define CLK_TYPE_PERIPHERAL 0x8 12#define CLK_TYPE_PERIPHERAL 0x8
13#define CLK_TYPE_SYSTEM 0x10
13 14
14 15
15struct clk { 16struct clk {
diff --git a/arch/arm/mach-at91rm9200/generic.h b/arch/arm/mach-at91rm9200/generic.h
index 694e411e285f..8c4d5a77d485 100644
--- a/arch/arm/mach-at91rm9200/generic.h
+++ b/arch/arm/mach-at91rm9200/generic.h
@@ -10,14 +10,19 @@
10 10
11 /* Processors */ 11 /* Processors */
12extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks); 12extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks);
13extern void __init at91sam9260_initialize(unsigned long main_clock);
14extern void __init at91sam9261_initialize(unsigned long main_clock);
13 15
14 /* Interrupts */ 16 /* Interrupts */
15extern void __init at91rm9200_init_interrupts(unsigned int priority[]); 17extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
18extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
19extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
16extern void __init at91_aic_init(unsigned int priority[]); 20extern void __init at91_aic_init(unsigned int priority[]);
17 21
18 /* Timer */ 22 /* Timer */
19struct sys_timer; 23struct sys_timer;
20extern struct sys_timer at91rm9200_timer; 24extern struct sys_timer at91rm9200_timer;
25extern struct sys_timer at91sam926x_timer;
21 26
22 /* Clocks */ 27 /* Clocks */
23extern int __init at91_clock_init(unsigned long main_clock); 28extern int __init at91_clock_init(unsigned long main_clock);
@@ -39,3 +44,6 @@ struct at91_gpio_bank {
39}; 44};
40extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks); 45extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
41extern void __init at91_gpio_irq_setup(void); 46extern void __init at91_gpio_irq_setup(void);
47
48extern void (*at91_arch_reset)(void);
49extern int at91_extern_irq;
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
index 7467d644f0a3..3f188508c391 100644
--- a/arch/arm/mach-at91rm9200/gpio.c
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -19,6 +19,8 @@
19 19
20#include <asm/io.h> 20#include <asm/io.h>
21#include <asm/hardware.h> 21#include <asm/hardware.h>
22#include <asm/arch/at91_pio.h>
23#include <asm/arch/at91_pmc.h>
22#include <asm/arch/gpio.h> 24#include <asm/arch/gpio.h>
23 25
24#include "generic.h" 26#include "generic.h"
@@ -332,10 +334,10 @@ static struct irq_chip gpio_irqchip = {
332 .set_wake = gpio_irq_set_wake, 334 .set_wake = gpio_irq_set_wake,
333}; 335};
334 336
335static void gpio_irq_handler(unsigned irq, struct irqdesc *desc) 337static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
336{ 338{
337 unsigned pin; 339 unsigned pin;
338 struct irqdesc *gpio; 340 struct irq_desc *gpio;
339 void __iomem *pio; 341 void __iomem *pio;
340 u32 isr; 342 u32 isr;
341 343
@@ -396,7 +398,7 @@ void __init at91_gpio_irq_setup(void)
396 __raw_writel(~0, controller + PIO_IDR); 398 __raw_writel(~0, controller + PIO_IDR);
397 399
398 set_irq_data(id, (void *) pin); 400 set_irq_data(id, (void *) pin);
399 set_irq_chipdata(id, controller); 401 set_irq_chip_data(id, controller);
400 402
401 for (i = 0; i < 32; i++, pin++) { 403 for (i = 0; i < 32; i++, pin++) {
402 /* 404 /*
@@ -404,7 +406,7 @@ void __init at91_gpio_irq_setup(void)
404 * shorter, and the AIC handles interupts sanely. 406 * shorter, and the AIC handles interupts sanely.
405 */ 407 */
406 set_irq_chip(pin, &gpio_irqchip); 408 set_irq_chip(pin, &gpio_irqchip);
407 set_irq_handler(pin, do_simple_IRQ); 409 set_irq_handler(pin, handle_simple_irq);
408 set_irq_flags(pin, IRQF_VALID); 410 set_irq_flags(pin, IRQF_VALID);
409 } 411 }
410 412
diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c
index 3e488117ca91..2148daafd29c 100644
--- a/arch/arm/mach-at91rm9200/irq.c
+++ b/arch/arm/mach-at91rm9200/irq.c
@@ -47,6 +47,10 @@ static void at91_aic_unmask_irq(unsigned int irq)
47 at91_sys_write(AT91_AIC_IECR, 1 << irq); 47 at91_sys_write(AT91_AIC_IECR, 1 << irq);
48} 48}
49 49
50unsigned int at91_extern_irq;
51
52#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
53
50static int at91_aic_set_type(unsigned irq, unsigned type) 54static int at91_aic_set_type(unsigned irq, unsigned type)
51{ 55{
52 unsigned int smr, srctype; 56 unsigned int smr, srctype;
@@ -59,14 +63,16 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
59 srctype = AT91_AIC_SRCTYPE_RISING; 63 srctype = AT91_AIC_SRCTYPE_RISING;
60 break; 64 break;
61 case IRQT_LOW: 65 case IRQT_LOW:
62 if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0)) /* only supported on external interrupts */ 66 if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
67 srctype = AT91_AIC_SRCTYPE_LOW;
68 else
63 return -EINVAL; 69 return -EINVAL;
64 srctype = AT91_AIC_SRCTYPE_LOW;
65 break; 70 break;
66 case IRQT_FALLING: 71 case IRQT_FALLING:
67 if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0)) /* only supported on external interrupts */ 72 if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
73 srctype = AT91_AIC_SRCTYPE_FALLING;
74 else
68 return -EINVAL; 75 return -EINVAL;
69 srctype = AT91_AIC_SRCTYPE_FALLING;
70 break; 76 break;
71 default: 77 default:
72 return -EINVAL; 78 return -EINVAL;
@@ -139,7 +145,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
139 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); 145 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
140 146
141 set_irq_chip(i, &at91_aic_chip); 147 set_irq_chip(i, &at91_aic_chip);
142 set_irq_handler(i, do_level_IRQ); 148 set_irq_handler(i, handle_level_irq);
143 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 149 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
144 150
145 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ 151 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
diff --git a/arch/arm/mach-at91rm9200/pm.c b/arch/arm/mach-at91rm9200/pm.c
index 32c95d8eaacf..67aa5572a3ea 100644
--- a/arch/arm/mach-at91rm9200/pm.c
+++ b/arch/arm/mach-at91rm9200/pm.c
@@ -26,7 +26,10 @@
26#include <asm/mach/irq.h> 26#include <asm/mach/irq.h>
27#include <asm/mach-types.h> 27#include <asm/mach-types.h>
28 28
29#include <asm/arch/at91_pmc.h>
30#include <asm/arch/at91rm9200_mc.h>
29#include <asm/arch/gpio.h> 31#include <asm/arch/gpio.h>
32#include <asm/arch/cpu.h>
30 33
31#include "generic.h" 34#include "generic.h"
32 35
@@ -68,9 +71,15 @@ static int at91_pm_verify_clocks(void)
68 scsr = at91_sys_read(AT91_PMC_SCSR); 71 scsr = at91_sys_read(AT91_PMC_SCSR);
69 72
70 /* USB must not be using PLLB */ 73 /* USB must not be using PLLB */
71 if ((scsr & (AT91_PMC_UHP | AT91_PMC_UDP)) != 0) { 74 if (cpu_is_at91rm9200()) {
72 pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n"); 75 if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) {
73 return 0; 76 pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
77 return 0;
78 }
79 } else if (cpu_is_at91sam9260()) {
80#warning "Check SAM9260 USB clocks"
81 } else if (cpu_is_at91sam9261()) {
82#warning "Check SAM9261 USB clocks"
74 } 83 }
75 84
76#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS 85#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
@@ -112,7 +121,6 @@ EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
112static void (*slow_clock)(void); 121static void (*slow_clock)(void);
113 122
114 123
115
116static int at91_pm_enter(suspend_state_t state) 124static int at91_pm_enter(suspend_state_t state)
117{ 125{
118 at91_gpio_suspend(); 126 at91_gpio_suspend();
@@ -123,13 +131,7 @@ static int at91_pm_enter(suspend_state_t state)
123 (at91_sys_read(AT91_PMC_PCSR) 131 (at91_sys_read(AT91_PMC_PCSR)
124 | (1 << AT91_ID_FIQ) 132 | (1 << AT91_ID_FIQ)
125 | (1 << AT91_ID_SYS) 133 | (1 << AT91_ID_SYS)
126 | (1 << AT91RM9200_ID_IRQ0) 134 | (at91_extern_irq))
127 | (1 << AT91RM9200_ID_IRQ1)
128 | (1 << AT91RM9200_ID_IRQ2)
129 | (1 << AT91RM9200_ID_IRQ3)
130 | (1 << AT91RM9200_ID_IRQ4)
131 | (1 << AT91RM9200_ID_IRQ5)
132 | (1 << AT91RM9200_ID_IRQ6))
133 & at91_sys_read(AT91_AIC_IMR), 135 & at91_sys_read(AT91_AIC_IMR),
134 state); 136 state);
135 137
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
index 7ee926e5bad2..ca102960f528 100644
--- a/arch/arm/mach-clps711x/irq.c
+++ b/arch/arm/mach-clps711x/irq.c
@@ -63,7 +63,7 @@ static void int1_unmask(unsigned int irq)
63 clps_writel(intmr1, INTMR1); 63 clps_writel(intmr1, INTMR1);
64} 64}
65 65
66static struct irqchip int1_chip = { 66static struct irq_chip int1_chip = {
67 .ack = int1_ack, 67 .ack = int1_ack,
68 .mask = int1_mask, 68 .mask = int1_mask,
69 .unmask = int1_unmask, 69 .unmask = int1_unmask,
@@ -100,7 +100,7 @@ static void int2_unmask(unsigned int irq)
100 clps_writel(intmr2, INTMR2); 100 clps_writel(intmr2, INTMR2);
101} 101}
102 102
103static struct irqchip int2_chip = { 103static struct irq_chip int2_chip = {
104 .ack = int2_ack, 104 .ack = int2_ack,
105 .mask = int2_mask, 105 .mask = int2_mask,
106 .unmask = int2_unmask, 106 .unmask = int2_unmask,
@@ -112,12 +112,12 @@ void __init clps711x_init_irq(void)
112 112
113 for (i = 0; i < NR_IRQS; i++) { 113 for (i = 0; i < NR_IRQS; i++) {
114 if (INT1_IRQS & (1 << i)) { 114 if (INT1_IRQS & (1 << i)) {
115 set_irq_handler(i, do_level_IRQ); 115 set_irq_handler(i, handle_level_irq);
116 set_irq_chip(i, &int1_chip); 116 set_irq_chip(i, &int1_chip);
117 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 117 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
118 } 118 }
119 if (INT2_IRQS & (1 << i)) { 119 if (INT2_IRQS & (1 << i)) {
120 set_irq_handler(i, do_level_IRQ); 120 set_irq_handler(i, handle_level_irq);
121 set_irq_chip(i, &int2_chip); 121 set_irq_chip(i, &int2_chip);
122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
123 } 123 }
diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c
index fb10cf252588..231b90004736 100644
--- a/arch/arm/mach-clps7500/core.c
+++ b/arch/arm/mach-clps7500/core.c
@@ -57,7 +57,7 @@ static void cl7500_unmask_irq_a(unsigned int irq)
57 iomd_writeb(val | mask, IOMD_IRQMASKA); 57 iomd_writeb(val | mask, IOMD_IRQMASKA);
58} 58}
59 59
60static struct irqchip clps7500_a_chip = { 60static struct irq_chip clps7500_a_chip = {
61 .ack = cl7500_ack_irq_a, 61 .ack = cl7500_ack_irq_a,
62 .mask = cl7500_mask_irq_a, 62 .mask = cl7500_mask_irq_a,
63 .unmask = cl7500_unmask_irq_a, 63 .unmask = cl7500_unmask_irq_a,
@@ -81,7 +81,7 @@ static void cl7500_unmask_irq_b(unsigned int irq)
81 iomd_writeb(val | mask, IOMD_IRQMASKB); 81 iomd_writeb(val | mask, IOMD_IRQMASKB);
82} 82}
83 83
84static struct irqchip clps7500_b_chip = { 84static struct irq_chip clps7500_b_chip = {
85 .ack = cl7500_mask_irq_b, 85 .ack = cl7500_mask_irq_b,
86 .mask = cl7500_mask_irq_b, 86 .mask = cl7500_mask_irq_b,
87 .unmask = cl7500_unmask_irq_b, 87 .unmask = cl7500_unmask_irq_b,
@@ -105,7 +105,7 @@ static void cl7500_unmask_irq_c(unsigned int irq)
105 iomd_writeb(val | mask, IOMD_IRQMASKC); 105 iomd_writeb(val | mask, IOMD_IRQMASKC);
106} 106}
107 107
108static struct irqchip clps7500_c_chip = { 108static struct irq_chip clps7500_c_chip = {
109 .ack = cl7500_mask_irq_c, 109 .ack = cl7500_mask_irq_c,
110 .mask = cl7500_mask_irq_c, 110 .mask = cl7500_mask_irq_c,
111 .unmask = cl7500_unmask_irq_c, 111 .unmask = cl7500_unmask_irq_c,
@@ -129,7 +129,7 @@ static void cl7500_unmask_irq_d(unsigned int irq)
129 iomd_writeb(val | mask, IOMD_IRQMASKD); 129 iomd_writeb(val | mask, IOMD_IRQMASKD);
130} 130}
131 131
132static struct irqchip clps7500_d_chip = { 132static struct irq_chip clps7500_d_chip = {
133 .ack = cl7500_mask_irq_d, 133 .ack = cl7500_mask_irq_d,
134 .mask = cl7500_mask_irq_d, 134 .mask = cl7500_mask_irq_d,
135 .unmask = cl7500_unmask_irq_d, 135 .unmask = cl7500_unmask_irq_d,
@@ -153,7 +153,7 @@ static void cl7500_unmask_irq_dma(unsigned int irq)
153 iomd_writeb(val | mask, IOMD_DMAMASK); 153 iomd_writeb(val | mask, IOMD_DMAMASK);
154} 154}
155 155
156static struct irqchip clps7500_dma_chip = { 156static struct irq_chip clps7500_dma_chip = {
157 .ack = cl7500_mask_irq_dma, 157 .ack = cl7500_mask_irq_dma,
158 .mask = cl7500_mask_irq_dma, 158 .mask = cl7500_mask_irq_dma,
159 .unmask = cl7500_unmask_irq_dma, 159 .unmask = cl7500_unmask_irq_dma,
@@ -177,7 +177,7 @@ static void cl7500_unmask_irq_fiq(unsigned int irq)
177 iomd_writeb(val | mask, IOMD_FIQMASK); 177 iomd_writeb(val | mask, IOMD_FIQMASK);
178} 178}
179 179
180static struct irqchip clps7500_fiq_chip = { 180static struct irq_chip clps7500_fiq_chip = {
181 .ack = cl7500_mask_irq_fiq, 181 .ack = cl7500_mask_irq_fiq,
182 .mask = cl7500_mask_irq_fiq, 182 .mask = cl7500_mask_irq_fiq,
183 .unmask = cl7500_unmask_irq_fiq, 183 .unmask = cl7500_unmask_irq_fiq,
@@ -187,7 +187,7 @@ static void cl7500_no_action(unsigned int irq)
187{ 187{
188} 188}
189 189
190static struct irqchip clps7500_no_chip = { 190static struct irq_chip clps7500_no_chip = {
191 .ack = cl7500_no_action, 191 .ack = cl7500_no_action,
192 .mask = cl7500_no_action, 192 .mask = cl7500_no_action,
193 .unmask = cl7500_no_action, 193 .unmask = cl7500_no_action,
@@ -214,43 +214,43 @@ static void __init clps7500_init_irq(void)
214 switch (irq) { 214 switch (irq) {
215 case 0 ... 7: 215 case 0 ... 7:
216 set_irq_chip(irq, &clps7500_a_chip); 216 set_irq_chip(irq, &clps7500_a_chip);
217 set_irq_handler(irq, do_level_IRQ); 217 set_irq_handler(irq, handle_level_irq);
218 set_irq_flags(irq, flags); 218 set_irq_flags(irq, flags);
219 break; 219 break;
220 220
221 case 8 ... 15: 221 case 8 ... 15:
222 set_irq_chip(irq, &clps7500_b_chip); 222 set_irq_chip(irq, &clps7500_b_chip);
223 set_irq_handler(irq, do_level_IRQ); 223 set_irq_handler(irq, handle_level_irq);
224 set_irq_flags(irq, flags); 224 set_irq_flags(irq, flags);
225 break; 225 break;
226 226
227 case 16 ... 22: 227 case 16 ... 22:
228 set_irq_chip(irq, &clps7500_dma_chip); 228 set_irq_chip(irq, &clps7500_dma_chip);
229 set_irq_handler(irq, do_level_IRQ); 229 set_irq_handler(irq, handle_level_irq);
230 set_irq_flags(irq, flags); 230 set_irq_flags(irq, flags);
231 break; 231 break;
232 232
233 case 24 ... 31: 233 case 24 ... 31:
234 set_irq_chip(irq, &clps7500_c_chip); 234 set_irq_chip(irq, &clps7500_c_chip);
235 set_irq_handler(irq, do_level_IRQ); 235 set_irq_handler(irq, handle_level_irq);
236 set_irq_flags(irq, flags); 236 set_irq_flags(irq, flags);
237 break; 237 break;
238 238
239 case 40 ... 47: 239 case 40 ... 47:
240 set_irq_chip(irq, &clps7500_d_chip); 240 set_irq_chip(irq, &clps7500_d_chip);
241 set_irq_handler(irq, do_level_IRQ); 241 set_irq_handler(irq, handle_level_irq);
242 set_irq_flags(irq, flags); 242 set_irq_flags(irq, flags);
243 break; 243 break;
244 244
245 case 48 ... 55: 245 case 48 ... 55:
246 set_irq_chip(irq, &clps7500_no_chip); 246 set_irq_chip(irq, &clps7500_no_chip);
247 set_irq_handler(irq, do_level_IRQ); 247 set_irq_handler(irq, handle_level_irq);
248 set_irq_flags(irq, flags); 248 set_irq_flags(irq, flags);
249 break; 249 break;
250 250
251 case 64 ... 72: 251 case 64 ... 72:
252 set_irq_chip(irq, &clps7500_fiq_chip); 252 set_irq_chip(irq, &clps7500_fiq_chip);
253 set_irq_handler(irq, do_level_IRQ); 253 set_irq_handler(irq, handle_level_irq);
254 set_irq_flags(irq, flags); 254 set_irq_flags(irq, flags);
255 break; 255 break;
256 } 256 }
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 90103ab373a6..8459431cfd71 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -45,7 +45,7 @@ static void ebsa110_unmask_irq(unsigned int irq)
45 __raw_writeb(1 << irq, IRQ_MSET); 45 __raw_writeb(1 << irq, IRQ_MSET);
46} 46}
47 47
48static struct irqchip ebsa110_irq_chip = { 48static struct irq_chip ebsa110_irq_chip = {
49 .ack = ebsa110_mask_irq, 49 .ack = ebsa110_mask_irq,
50 .mask = ebsa110_mask_irq, 50 .mask = ebsa110_mask_irq,
51 .unmask = ebsa110_unmask_irq, 51 .unmask = ebsa110_unmask_irq,
@@ -67,7 +67,7 @@ static void __init ebsa110_init_irq(void)
67 67
68 for (irq = 0; irq < NR_IRQS; irq++) { 68 for (irq = 0; irq < NR_IRQS; irq++) {
69 set_irq_chip(irq, &ebsa110_irq_chip); 69 set_irq_chip(irq, &ebsa110_irq_chip);
70 set_irq_handler(irq, do_level_IRQ); 70 set_irq_handler(irq, handle_level_irq);
71 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 71 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
72 } 72 }
73} 73}
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index e346b03cd921..af7904b3d0a8 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -9,12 +9,24 @@ config CRUNCH
9 9
10comment "EP93xx Platforms" 10comment "EP93xx Platforms"
11 11
12config MACH_ADSSPHERE
13 bool "Support ADS Sphere"
14 help
15 Say 'Y' here if you want your kernel to support the ADS
16 Sphere board.
17
12config MACH_EDB9302 18config MACH_EDB9302
13 bool "Support Cirrus Logic EDB9302" 19 bool "Support Cirrus Logic EDB9302"
14 help 20 help
15 Say 'Y' here if you want your kernel to support the Cirrus 21 Say 'Y' here if you want your kernel to support the Cirrus
16 Logic EDB9302 Evaluation Board. 22 Logic EDB9302 Evaluation Board.
17 23
24config MACH_EDB9302A
25 bool "Support Cirrus Logic EDB9302A"
26 help
27 Say 'Y' here if you want your kernel to support the Cirrus
28 Logic EDB9302A Evaluation Board.
29
18config MACH_EDB9312 30config MACH_EDB9312
19 bool "Support Cirrus Logic EDB9312" 31 bool "Support Cirrus Logic EDB9312"
20 help 32 help
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index c2eb18b530c2..b06641dd450d 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -6,7 +6,9 @@ obj-m :=
6obj-n := 6obj-n :=
7obj- := 7obj- :=
8 8
9obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o
9obj-$(CONFIG_MACH_EDB9302) += edb9302.o 10obj-$(CONFIG_MACH_EDB9302) += edb9302.o
11obj-$(CONFIG_MACH_EDB9302A) += edb9302a.o
10obj-$(CONFIG_MACH_EDB9312) += edb9312.o 12obj-$(CONFIG_MACH_EDB9312) += edb9312.o
11obj-$(CONFIG_MACH_EDB9315) += edb9315.o 13obj-$(CONFIG_MACH_EDB9315) += edb9315.o
12obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o 14obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
new file mode 100644
index 000000000000..ac5d5818eb7b
--- /dev/null
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -0,0 +1,91 @@
1/*
2 * arch/arm/mach-ep93xx/adssphere.c
3 * ADS Sphere support.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/mm.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/mtd/physmap.h>
20#include <linux/platform_device.h>
21#include <asm/io.h>
22#include <asm/hardware.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25
26static struct physmap_flash_data adssphere_flash_data = {
27 .width = 4,
28};
29
30static struct resource adssphere_flash_resource = {
31 .start = 0x60000000,
32 .end = 0x61ffffff,
33 .flags = IORESOURCE_MEM,
34};
35
36static struct platform_device adssphere_flash = {
37 .name = "physmap-flash",
38 .id = 0,
39 .dev = {
40 .platform_data = &adssphere_flash_data,
41 },
42 .num_resources = 1,
43 .resource = &adssphere_flash_resource,
44};
45
46static struct ep93xx_eth_data adssphere_eth_data = {
47 .phy_id = 1,
48};
49
50static struct resource adssphere_eth_resource[] = {
51 {
52 .start = EP93XX_ETHERNET_PHYS_BASE,
53 .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
54 .flags = IORESOURCE_MEM,
55 }, {
56 .start = IRQ_EP93XX_ETHERNET,
57 .end = IRQ_EP93XX_ETHERNET,
58 .flags = IORESOURCE_IRQ,
59 }
60};
61
62static struct platform_device adssphere_eth_device = {
63 .name = "ep93xx-eth",
64 .id = -1,
65 .dev = {
66 .platform_data = &adssphere_eth_data,
67 },
68 .num_resources = 2,
69 .resource = adssphere_eth_resource,
70};
71
72static void __init adssphere_init_machine(void)
73{
74 ep93xx_init_devices();
75 platform_device_register(&adssphere_flash);
76
77 memcpy(adssphere_eth_data.dev_addr,
78 (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
79 platform_device_register(&adssphere_eth_device);
80}
81
82MACHINE_START(ADSSPHERE, "ADS Sphere board")
83 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
84 .phys_io = EP93XX_APB_PHYS_BASE,
85 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
86 .boot_params = 0x00000100,
87 .map_io = ep93xx_map_io,
88 .init_irq = ep93xx_init_irq,
89 .timer = &ep93xx_timer,
90 .init_machine = adssphere_init_machine,
91MACHINE_END
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index e3fd1ab6adcc..d649b39711d4 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -245,7 +245,7 @@ EXPORT_SYMBOL(gpio_line_set);
245 * EP93xx IRQ handling 245 * EP93xx IRQ handling
246 *************************************************************************/ 246 *************************************************************************/
247static void ep93xx_gpio_ab_irq_handler(unsigned int irq, 247static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
248 struct irqdesc *desc) 248 struct irq_desc *desc)
249{ 249{
250 unsigned char status; 250 unsigned char status;
251 int i; 251 int i;
@@ -335,7 +335,7 @@ static int ep93xx_gpio_ab_irq_type(unsigned int irq, unsigned int type)
335 return 0; 335 return 0;
336} 336}
337 337
338static struct irqchip ep93xx_gpio_ab_irq_chip = { 338static struct irq_chip ep93xx_gpio_ab_irq_chip = {
339 .ack = ep93xx_gpio_ab_irq_mask_ack, 339 .ack = ep93xx_gpio_ab_irq_mask_ack,
340 .mask = ep93xx_gpio_ab_irq_mask, 340 .mask = ep93xx_gpio_ab_irq_mask,
341 .unmask = ep93xx_gpio_ab_irq_unmask, 341 .unmask = ep93xx_gpio_ab_irq_unmask,
@@ -352,7 +352,7 @@ void __init ep93xx_init_irq(void)
352 352
353 for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) { 353 for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) {
354 set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip); 354 set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip);
355 set_irq_handler(irq, do_level_IRQ); 355 set_irq_handler(irq, handle_level_irq);
356 set_irq_flags(irq, IRQF_VALID); 356 set_irq_flags(irq, IRQF_VALID);
357 } 357 }
358 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); 358 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
diff --git a/arch/arm/mach-ep93xx/edb9302a.c b/arch/arm/mach-ep93xx/edb9302a.c
new file mode 100644
index 000000000000..62e064bab1d2
--- /dev/null
+++ b/arch/arm/mach-ep93xx/edb9302a.c
@@ -0,0 +1,91 @@
1/*
2 * arch/arm/mach-ep93xx/edb9302a.c
3 * Cirrus Logic EDB9302A support.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/mm.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/mtd/physmap.h>
20#include <linux/platform_device.h>
21#include <asm/io.h>
22#include <asm/hardware.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25
26static struct physmap_flash_data edb9302a_flash_data = {
27 .width = 2,
28};
29
30static struct resource edb9302a_flash_resource = {
31 .start = 0x60000000,
32 .end = 0x60ffffff,
33 .flags = IORESOURCE_MEM,
34};
35
36static struct platform_device edb9302a_flash = {
37 .name = "physmap-flash",
38 .id = 0,
39 .dev = {
40 .platform_data = &edb9302a_flash_data,
41 },
42 .num_resources = 1,
43 .resource = &edb9302a_flash_resource,
44};
45
46static struct ep93xx_eth_data edb9302a_eth_data = {
47 .phy_id = 1,
48};
49
50static struct resource edb9302a_eth_resource[] = {
51 {
52 .start = EP93XX_ETHERNET_PHYS_BASE,
53 .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
54 .flags = IORESOURCE_MEM,
55 }, {
56 .start = IRQ_EP93XX_ETHERNET,
57 .end = IRQ_EP93XX_ETHERNET,
58 .flags = IORESOURCE_IRQ,
59 }
60};
61
62static struct platform_device edb9302a_eth_device = {
63 .name = "ep93xx-eth",
64 .id = -1,
65 .dev = {
66 .platform_data = &edb9302a_eth_data,
67 },
68 .num_resources = 2,
69 .resource = edb9302a_eth_resource,
70};
71
72static void __init edb9302a_init_machine(void)
73{
74 ep93xx_init_devices();
75 platform_device_register(&edb9302a_flash);
76
77 memcpy(edb9302a_eth_data.dev_addr,
78 (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
79 platform_device_register(&edb9302a_eth_device);
80}
81
82MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
83 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
84 .phys_io = EP93XX_APB_PHYS_BASE,
85 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
86 .boot_params = 0xc0000100,
87 .map_io = ep93xx_map_io,
88 .init_irq = ep93xx_init_irq,
89 .timer = &ep93xx_timer,
90 .init_machine = edb9302a_init_machine,
91MACHINE_END
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index af900f4755a4..ef29fc34ce65 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -78,7 +78,7 @@ static void fb_unmask_irq(unsigned int irq)
78 *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)]; 78 *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)];
79} 79}
80 80
81static struct irqchip fb_chip = { 81static struct irq_chip fb_chip = {
82 .ack = fb_mask_irq, 82 .ack = fb_mask_irq,
83 .mask = fb_mask_irq, 83 .mask = fb_mask_irq,
84 .unmask = fb_unmask_irq, 84 .unmask = fb_unmask_irq,
@@ -96,7 +96,7 @@ static void __init __fb_init_irq(void)
96 96
97 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { 97 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
98 set_irq_chip(irq, &fb_chip); 98 set_irq_chip(irq, &fb_chip);
99 set_irq_handler(irq, do_level_IRQ); 99 set_irq_handler(irq, handle_level_irq);
100 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 100 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
101 } 101 }
102} 102}
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index 888dedd501b9..79443ffc8916 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -49,7 +49,7 @@ static void isa_unmask_pic_lo_irq(unsigned int irq)
49 outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO); 49 outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO);
50} 50}
51 51
52static struct irqchip isa_lo_chip = { 52static struct irq_chip isa_lo_chip = {
53 .ack = isa_ack_pic_lo_irq, 53 .ack = isa_ack_pic_lo_irq,
54 .mask = isa_mask_pic_lo_irq, 54 .mask = isa_mask_pic_lo_irq,
55 .unmask = isa_unmask_pic_lo_irq, 55 .unmask = isa_unmask_pic_lo_irq,
@@ -78,14 +78,14 @@ static void isa_unmask_pic_hi_irq(unsigned int irq)
78 outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI); 78 outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI);
79} 79}
80 80
81static struct irqchip isa_hi_chip = { 81static struct irq_chip isa_hi_chip = {
82 .ack = isa_ack_pic_hi_irq, 82 .ack = isa_ack_pic_hi_irq,
83 .mask = isa_mask_pic_hi_irq, 83 .mask = isa_mask_pic_hi_irq,
84 .unmask = isa_unmask_pic_hi_irq, 84 .unmask = isa_unmask_pic_hi_irq,
85}; 85};
86 86
87static void 87static void
88isa_irq_handler(unsigned int irq, struct irqdesc *desc) 88isa_irq_handler(unsigned int irq, struct irq_desc *desc)
89{ 89{
90 unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE; 90 unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
91 91
@@ -150,13 +150,13 @@ void __init isa_init_irq(unsigned int host_irq)
150 if (host_irq != (unsigned int)-1) { 150 if (host_irq != (unsigned int)-1) {
151 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { 151 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
152 set_irq_chip(irq, &isa_lo_chip); 152 set_irq_chip(irq, &isa_lo_chip);
153 set_irq_handler(irq, do_level_IRQ); 153 set_irq_handler(irq, handle_level_irq);
154 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 154 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
155 } 155 }
156 156
157 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { 157 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
158 set_irq_chip(irq, &isa_hi_chip); 158 set_irq_chip(irq, &isa_hi_chip);
159 set_irq_handler(irq, do_level_IRQ); 159 set_irq_handler(irq, handle_level_irq);
160 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 160 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
161 } 161 }
162 162
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index 4719229a1a78..7f31816896ad 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -101,7 +101,7 @@ static void inline unmask_gpio_irq(u32 irq)
101 101
102static void 102static void
103h720x_gpio_handler(unsigned int mask, unsigned int irq, 103h720x_gpio_handler(unsigned int mask, unsigned int irq,
104 struct irqdesc *desc) 104 struct irq_desc *desc)
105{ 105{
106 IRQDBG("%s irq: %d\n",__FUNCTION__,irq); 106 IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
107 desc = irq_desc + irq; 107 desc = irq_desc + irq;
@@ -117,7 +117,7 @@ h720x_gpio_handler(unsigned int mask, unsigned int irq,
117} 117}
118 118
119static void 119static void
120h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 120h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
121{ 121{
122 unsigned int mask, irq; 122 unsigned int mask, irq;
123 123
@@ -128,7 +128,7 @@ h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
128} 128}
129 129
130static void 130static void
131h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 131h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
132{ 132{
133 unsigned int mask, irq; 133 unsigned int mask, irq;
134 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); 134 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
@@ -138,7 +138,7 @@ h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
138} 138}
139 139
140static void 140static void
141h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 141h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
142{ 142{
143 unsigned int mask, irq; 143 unsigned int mask, irq;
144 144
@@ -149,7 +149,7 @@ h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
149} 149}
150 150
151static void 151static void
152h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 152h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
153{ 153{
154 unsigned int mask, irq; 154 unsigned int mask, irq;
155 155
@@ -161,7 +161,7 @@ h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
161 161
162#ifdef CONFIG_CPU_H7202 162#ifdef CONFIG_CPU_H7202
163static void 163static void
164h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 164h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
165{ 165{
166 unsigned int mask, irq; 166 unsigned int mask, irq;
167 167
@@ -172,13 +172,13 @@ h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
172} 172}
173#endif 173#endif
174 174
175static struct irqchip h720x_global_chip = { 175static struct irq_chip h720x_global_chip = {
176 .ack = mask_global_irq, 176 .ack = mask_global_irq,
177 .mask = mask_global_irq, 177 .mask = mask_global_irq,
178 .unmask = unmask_global_irq, 178 .unmask = unmask_global_irq,
179}; 179};
180 180
181static struct irqchip h720x_gpio_chip = { 181static struct irq_chip h720x_gpio_chip = {
182 .ack = ack_gpio_irq, 182 .ack = ack_gpio_irq,
183 .mask = mask_gpio_irq, 183 .mask = mask_gpio_irq,
184 .unmask = unmask_gpio_irq, 184 .unmask = unmask_gpio_irq,
@@ -203,14 +203,14 @@ void __init h720x_init_irq (void)
203 /* Initialize global IRQ's, fast path */ 203 /* Initialize global IRQ's, fast path */
204 for (irq = 0; irq < NR_GLBL_IRQS; irq++) { 204 for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
205 set_irq_chip(irq, &h720x_global_chip); 205 set_irq_chip(irq, &h720x_global_chip);
206 set_irq_handler(irq, do_level_IRQ); 206 set_irq_handler(irq, handle_level_irq);
207 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 207 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
208 } 208 }
209 209
210 /* Initialize multiplexed IRQ's, slow path */ 210 /* Initialize multiplexed IRQ's, slow path */
211 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { 211 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
212 set_irq_chip(irq, &h720x_gpio_chip); 212 set_irq_chip(irq, &h720x_gpio_chip);
213 set_irq_handler(irq, do_edge_IRQ); 213 set_irq_handler(irq, handle_edge_irq);
214 set_irq_flags(irq, IRQF_VALID ); 214 set_irq_flags(irq, IRQF_VALID );
215 } 215 }
216 set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); 216 set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
@@ -221,7 +221,7 @@ void __init h720x_init_irq (void)
221#ifdef CONFIG_CPU_H7202 221#ifdef CONFIG_CPU_H7202
222 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { 222 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
223 set_irq_chip(irq, &h720x_gpio_chip); 223 set_irq_chip(irq, &h720x_gpio_chip);
224 set_irq_handler(irq, do_edge_IRQ); 224 set_irq_handler(irq, handle_edge_irq);
225 set_irq_flags(irq, IRQF_VALID ); 225 set_irq_flags(irq, IRQF_VALID );
226 } 226 }
227 set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); 227 set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index 06fecaefd8dc..703870f30adf 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -106,7 +106,7 @@ static struct platform_device *devices[] __initdata = {
106 * we have to handle all timer interrupts in one place. 106 * we have to handle all timer interrupts in one place.
107 */ 107 */
108static void 108static void
109h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 109h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
110{ 110{
111 unsigned int mask, irq; 111 unsigned int mask, irq;
112 112
@@ -162,7 +162,7 @@ static void inline unmask_timerx_irq (u32 irq)
162 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit; 162 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
163} 163}
164 164
165static struct irqchip h7202_timerx_chip = { 165static struct irq_chip h7202_timerx_chip = {
166 .ack = mask_timerx_irq, 166 .ack = mask_timerx_irq,
167 .mask = mask_timerx_irq, 167 .mask = mask_timerx_irq,
168 .unmask = unmask_timerx_irq, 168 .unmask = unmask_timerx_irq,
@@ -202,7 +202,7 @@ void __init h7202_init_irq (void)
202 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { 202 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
203 mask_timerx_irq(irq); 203 mask_timerx_irq(irq);
204 set_irq_chip(irq, &h7202_timerx_chip); 204 set_irq_chip(irq, &h7202_timerx_chip);
205 set_irq_handler(irq, do_edge_IRQ); 205 set_irq_handler(irq, handle_edge_irq);
206 set_irq_flags(irq, IRQF_VALID ); 206 set_irq_flags(irq, IRQF_VALID );
207 } 207 }
208 set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); 208 set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c
index 12ea58a3b84f..b5aa49d00ca3 100644
--- a/arch/arm/mach-imx/generic.c
+++ b/arch/arm/mach-imx/generic.c
@@ -104,6 +104,9 @@ EXPORT_SYMBOL(imx_gpio_mode);
104 */ 104 */
105static unsigned int imx_decode_pll(unsigned int pll) 105static unsigned int imx_decode_pll(unsigned int pll)
106{ 106{
107 unsigned long long ll;
108 unsigned long quot;
109
107 u32 mfi = (pll >> 10) & 0xf; 110 u32 mfi = (pll >> 10) & 0xf;
108 u32 mfn = pll & 0x3ff; 111 u32 mfn = pll & 0x3ff;
109 u32 mfd = (pll >> 16) & 0x3ff; 112 u32 mfd = (pll >> 16) & 0x3ff;
@@ -112,7 +115,11 @@ static unsigned int imx_decode_pll(unsigned int pll)
112 115
113 mfi = mfi <= 5 ? 5 : mfi; 116 mfi = mfi <= 5 ? 5 : mfi;
114 117
115 return (2 * (f_ref>>10) * ( (mfi<<10) + (mfn<<10) / (mfd+1) )) / (pd+1); 118 ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
119 quot = (pd+1) * (1<<16);
120 ll += quot / 2;
121 do_div(ll, quot);
122 return (unsigned int) ll;
116} 123}
117 124
118unsigned int imx_get_system_clk(void) 125unsigned int imx_get_system_clk(void)
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c
index 368b13b058ab..0791b56caecc 100644
--- a/arch/arm/mach-imx/irq.c
+++ b/arch/arm/mach-imx/irq.c
@@ -146,7 +146,7 @@ imx_gpio_unmask_irq(unsigned int irq)
146 146
147static void 147static void
148imx_gpio_handler(unsigned int mask, unsigned int irq, 148imx_gpio_handler(unsigned int mask, unsigned int irq,
149 struct irqdesc *desc) 149 struct irq_desc *desc)
150{ 150{
151 desc = irq_desc + irq; 151 desc = irq_desc + irq;
152 while (mask) { 152 while (mask) {
@@ -161,7 +161,7 @@ imx_gpio_handler(unsigned int mask, unsigned int irq,
161} 161}
162 162
163static void 163static void
164imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 164imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
165{ 165{
166 unsigned int mask, irq; 166 unsigned int mask, irq;
167 167
@@ -171,7 +171,7 @@ imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
171} 171}
172 172
173static void 173static void
174imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 174imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
175{ 175{
176 unsigned int mask, irq; 176 unsigned int mask, irq;
177 177
@@ -181,7 +181,7 @@ imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
181} 181}
182 182
183static void 183static void
184imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 184imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
185{ 185{
186 unsigned int mask, irq; 186 unsigned int mask, irq;
187 187
@@ -191,7 +191,7 @@ imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
191} 191}
192 192
193static void 193static void
194imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 194imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
195{ 195{
196 unsigned int mask, irq; 196 unsigned int mask, irq;
197 197
@@ -230,13 +230,13 @@ imx_init_irq(void)
230 230
231 for (irq = 0; irq < IMX_IRQS; irq++) { 231 for (irq = 0; irq < IMX_IRQS; irq++) {
232 set_irq_chip(irq, &imx_internal_chip); 232 set_irq_chip(irq, &imx_internal_chip);
233 set_irq_handler(irq, do_level_IRQ); 233 set_irq_handler(irq, handle_level_irq);
234 set_irq_flags(irq, IRQF_VALID); 234 set_irq_flags(irq, IRQF_VALID);
235 } 235 }
236 236
237 for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) { 237 for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
238 set_irq_chip(irq, &imx_gpio_chip); 238 set_irq_chip(irq, &imx_gpio_chip);
239 set_irq_handler(irq, do_edge_IRQ); 239 set_irq_handler(irq, handle_edge_irq);
240 set_irq_flags(irq, IRQF_VALID); 240 set_irq_flags(irq, IRQF_VALID);
241 } 241 }
242 242
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 8ae4a2c5066f..40039b2a90b3 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -14,6 +14,7 @@
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/time.h> 16#include <linux/time.h>
17#include <linux/clocksource.h>
17 18
18#include <asm/hardware.h> 19#include <asm/hardware.h>
19#include <asm/io.h> 20#include <asm/io.h>
@@ -24,33 +25,7 @@
24/* Use timer 1 as system timer */ 25/* Use timer 1 as system timer */
25#define TIMER_BASE IMX_TIM1_BASE 26#define TIMER_BASE IMX_TIM1_BASE
26 27
27/* 28static unsigned long evt_diff;
28 * Returns number of us since last clock interrupt. Note that interrupts
29 * will have been disabled by do_gettimeoffset()
30 */
31static unsigned long imx_gettimeoffset(void)
32{
33 unsigned long ticks;
34
35 /*
36 * Get the current number of ticks. Note that there is a race
37 * condition between us reading the timer and checking for
38 * an interrupt. We get around this by ensuring that the
39 * counter has not reloaded between our two reads.
40 */
41 ticks = IMX_TCN(TIMER_BASE);
42
43 /*
44 * Interrupt pending? If so, we've reloaded once already.
45 */
46 if (IMX_TSTAT(TIMER_BASE) & TSTAT_COMP)
47 ticks += LATCH;
48
49 /*
50 * Convert the ticks to usecs
51 */
52 return (1000000 / CLK32) * ticks;
53}
54 29
55/* 30/*
56 * IRQ handler for the timer 31 * IRQ handler for the timer
@@ -58,14 +33,23 @@ static unsigned long imx_gettimeoffset(void)
58static irqreturn_t 33static irqreturn_t
59imx_timer_interrupt(int irq, void *dev_id) 34imx_timer_interrupt(int irq, void *dev_id)
60{ 35{
61 write_seqlock(&xtime_lock); 36 uint32_t tstat;
62 37
63 /* clear the interrupt */ 38 /* clear the interrupt */
64 if (IMX_TSTAT(TIMER_BASE)) 39 tstat = IMX_TSTAT(TIMER_BASE);
65 IMX_TSTAT(TIMER_BASE) = 0; 40 IMX_TSTAT(TIMER_BASE) = 0;
41
42 if (tstat & TSTAT_COMP) {
43 do {
44
45 write_seqlock(&xtime_lock);
46 timer_tick();
47 write_sequnlock(&xtime_lock);
48 IMX_TCMP(TIMER_BASE) += evt_diff;
66 49
67 timer_tick(); 50 } while (unlikely((int32_t)(IMX_TCMP(TIMER_BASE)
68 write_sequnlock(&xtime_lock); 51 - IMX_TCN(TIMER_BASE)) < 0));
52 }
69 53
70 return IRQ_HANDLED; 54 return IRQ_HANDLED;
71} 55}
@@ -77,9 +61,9 @@ static struct irqaction imx_timer_irq = {
77}; 61};
78 62
79/* 63/*
80 * Set up timer interrupt, and return the current time in seconds. 64 * Set up timer hardware into expected mode and state.
81 */ 65 */
82static void __init imx_timer_init(void) 66static void __init imx_timer_hardware_init(void)
83{ 67{
84 /* 68 /*
85 * Initialise to a known state (all timers off, and timing reset) 69 * Initialise to a known state (all timers off, and timing reset)
@@ -87,7 +71,38 @@ static void __init imx_timer_init(void)
87 IMX_TCTL(TIMER_BASE) = 0; 71 IMX_TCTL(TIMER_BASE) = 0;
88 IMX_TPRER(TIMER_BASE) = 0; 72 IMX_TPRER(TIMER_BASE) = 0;
89 IMX_TCMP(TIMER_BASE) = LATCH - 1; 73 IMX_TCMP(TIMER_BASE) = LATCH - 1;
90 IMX_TCTL(TIMER_BASE) = TCTL_CLK_32 | TCTL_IRQEN | TCTL_TEN; 74
75 IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_IRQEN | TCTL_TEN;
76 evt_diff = LATCH;
77}
78
79cycle_t imx_get_cycles(void)
80{
81 return IMX_TCN(TIMER_BASE);
82}
83
84static struct clocksource clocksource_imx = {
85 .name = "imx_timer1",
86 .rating = 200,
87 .read = imx_get_cycles,
88 .mask = 0xFFFFFFFF,
89 .shift = 20,
90 .is_continuous = 1,
91};
92
93static int __init imx_clocksource_init(void)
94{
95 clocksource_imx.mult =
96 clocksource_hz2mult(imx_get_perclk1(), clocksource_imx.shift);
97 clocksource_register(&clocksource_imx);
98
99 return 0;
100}
101
102static void __init imx_timer_init(void)
103{
104 imx_timer_hardware_init();
105 imx_clocksource_init();
91 106
92 /* 107 /*
93 * Make irqs happen for the system timer 108 * Make irqs happen for the system timer
@@ -97,5 +112,4 @@ static void __init imx_timer_init(void)
97 112
98struct sys_timer imx_timer = { 113struct sys_timer imx_timer = {
99 .init = imx_timer_init, 114 .init = imx_timer_init,
100 .offset = imx_gettimeoffset,
101}; 115};
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 191c57a3b997..72280754354d 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -183,7 +183,7 @@ static void __init ap_init_irq(void)
183 for (i = 0; i < NR_IRQS; i++) { 183 for (i = 0; i < NR_IRQS; i++) {
184 if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) { 184 if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) {
185 set_irq_chip(i, &sc_chip); 185 set_irq_chip(i, &sc_chip);
186 set_irq_handler(i, do_level_IRQ); 186 set_irq_handler(i, handle_level_irq);
187 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 187 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
188 } 188 }
189 } 189 }
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 771b65bffe69..913f64b22405 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -202,7 +202,7 @@ static struct irq_chip sic_chip = {
202}; 202};
203 203
204static void 204static void
205sic_handle_irq(unsigned int irq, struct irqdesc *desc) 205sic_handle_irq(unsigned int irq, struct irq_desc *desc)
206{ 206{
207 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS); 207 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
208 208
@@ -238,7 +238,7 @@ static void __init intcp_init_irq(void)
238 if (i == 29) 238 if (i == 29)
239 break; 239 break;
240 set_irq_chip(i, &pic_chip); 240 set_irq_chip(i, &pic_chip);
241 set_irq_handler(i, do_level_IRQ); 241 set_irq_handler(i, handle_level_irq);
242 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 242 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
243 } 243 }
244 244
@@ -247,7 +247,7 @@ static void __init intcp_init_irq(void)
247 247
248 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) { 248 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
249 set_irq_chip(i, &cic_chip); 249 set_irq_chip(i, &cic_chip);
250 set_irq_handler(i, do_level_IRQ); 250 set_irq_handler(i, handle_level_irq);
251 set_irq_flags(i, IRQF_VALID); 251 set_irq_flags(i, IRQF_VALID);
252 } 252 }
253 253
@@ -256,7 +256,7 @@ static void __init intcp_init_irq(void)
256 256
257 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { 257 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
258 set_irq_chip(i, &sic_chip); 258 set_irq_chip(i, &sic_chip);
259 set_irq_handler(i, do_level_IRQ); 259 set_irq_handler(i, handle_level_irq);
260 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 260 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
261 } 261 }
262 262
diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c
index 1bc8534ef0c6..613b841a10f3 100644
--- a/arch/arm/mach-integrator/platsmp.c
+++ b/arch/arm/mach-integrator/platsmp.c
@@ -18,7 +18,6 @@
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/delay.h> 19#include <asm/delay.h>
20#include <asm/mmu_context.h> 20#include <asm/mmu_context.h>
21#include <asm/procinfo.h>
22#include <asm/ptrace.h> 21#include <asm/ptrace.h>
23#include <asm/smp.h> 22#include <asm/smp.h>
24 23
diff --git a/arch/arm/mach-iop13xx/Kconfig b/arch/arm/mach-iop13xx/Kconfig
new file mode 100644
index 000000000000..40c2d689f2eb
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Kconfig
@@ -0,0 +1,20 @@
1if ARCH_IOP13XX
2
3menu "IOP13XX Implementation Options"
4
5comment "IOP13XX Platform Support"
6
7config MACH_IQ81340SC
8 bool "Enable IQ81340SC Hardware Support"
9 help
10 Say Y here if you want to support running on the Intel IQ81340SC
11 evaluation kit.
12
13config MACH_IQ81340MC
14 bool "Enable IQ81340MC Hardware Support"
15 help
16 Say Y here if you want to support running on the Intel IQ81340MC
17 evaluation kit.
18
19endmenu
20endif
diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile
new file mode 100644
index 000000000000..c3d6c08f2d4c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Makefile
@@ -0,0 +1,12 @@
1obj-y :=
2obj-m :=
3obj-n :=
4obj- :=
5
6obj-$(CONFIG_ARCH_IOP13XX) += setup.o
7obj-$(CONFIG_ARCH_IOP13XX) += irq.o
8obj-$(CONFIG_ARCH_IOP13XX) += time.o
9obj-$(CONFIG_ARCH_IOP13XX) += pci.o
10obj-$(CONFIG_ARCH_IOP13XX) += io.o
11obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
12obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o
diff --git a/arch/arm/mach-iop13xx/Makefile.boot b/arch/arm/mach-iop13xx/Makefile.boot
new file mode 100644
index 000000000000..0b0e19fdfe6c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
new file mode 100644
index 000000000000..fbf9f88e46ea
--- /dev/null
+++ b/arch/arm/mach-iop13xx/io.c
@@ -0,0 +1,93 @@
1/*
2 * iop13xx custom ioremap implementation
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <asm/hardware.h>
22#include <asm/io.h>
23
24void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
25 unsigned long flags)
26{
27 void __iomem * retval;
28
29 switch (cookie) {
30 case IOP13XX_PCIX_LOWER_MEM_RA ... IOP13XX_PCIX_UPPER_MEM_RA:
31 if (unlikely(!iop13xx_atux_mem_base))
32 retval = NULL;
33 else
34 retval = (void *)(iop13xx_atux_mem_base +
35 (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
36 break;
37 case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
38 if (unlikely(!iop13xx_atue_mem_base))
39 retval = NULL;
40 else
41 retval = (void *)(iop13xx_atue_mem_base +
42 (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
43 break;
44 case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
45 retval = __ioremap(IOP13XX_PBI_LOWER_MEM_PA +
46 (cookie - IOP13XX_PBI_LOWER_MEM_RA),
47 size, flags);
48 break;
49 case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
50 retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
51 break;
52 case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
53 retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
54 break;
55 case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
56 retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
57 break;
58 default:
59 retval = __ioremap(cookie, size, flags);
60 }
61
62 return retval;
63}
64EXPORT_SYMBOL(__iop13xx_ioremap);
65
66void __iop13xx_iounmap(void __iomem *addr)
67{
68 extern void __iounmap(volatile void __iomem *addr);
69
70 if (iop13xx_atue_mem_base)
71 if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
72 addr < (void __iomem *) (iop13xx_atue_mem_base +
73 iop13xx_atue_mem_size))
74 goto skip;
75
76 if (iop13xx_atux_mem_base)
77 if (addr >= (void __iomem *) iop13xx_atux_mem_base &&
78 addr < (void __iomem *) (iop13xx_atux_mem_base +
79 iop13xx_atux_mem_size))
80 goto skip;
81
82 switch ((u32) addr) {
83 case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
84 case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
85 case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
86 goto skip;
87 }
88 __iounmap(addr);
89
90skip:
91 return;
92}
93EXPORT_SYMBOL(__iop13xx_iounmap);
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
new file mode 100644
index 000000000000..ee595786cd22
--- /dev/null
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -0,0 +1,98 @@
1/*
2 * iq81340mc board support
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/pci.h>
20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23#include <asm/mach/pci.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/arch/pci.h>
27#include <asm/mach/time.h>
28
29extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
30
31static int __init
32iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
33{
34 switch (idsel) {
35 case 1:
36 switch (pin) {
37 case 1: return ATUX_INTB;
38 case 2: return ATUX_INTC;
39 case 3: return ATUX_INTD;
40 case 4: return ATUX_INTA;
41 default: return -1;
42 }
43 case 2:
44 switch (pin) {
45 case 1: return ATUX_INTC;
46 case 2: return ATUX_INTD;
47 case 3: return ATUX_INTC;
48 case 4: return ATUX_INTD;
49 default: return -1;
50 }
51 default: return -1;
52 }
53}
54
55static struct hw_pci iq81340mc_pci __initdata = {
56 .swizzle = pci_std_swizzle,
57 .nr_controllers = 0,
58 .setup = iop13xx_pci_setup,
59 .map_irq = iq81340mc_pcix_map_irq,
60 .scan = iop13xx_scan_bus,
61 .preinit = iop13xx_pci_init,
62};
63
64static int __init iq81340mc_pci_init(void)
65{
66 iop13xx_atu_select(&iq81340mc_pci);
67 pci_common_init(&iq81340mc_pci);
68 iop13xx_map_pci_memory();
69
70 return 0;
71}
72
73static void __init iq81340mc_init(void)
74{
75 iop13xx_platform_init();
76 iq81340mc_pci_init();
77}
78
79static void __init iq81340mc_timer_init(void)
80{
81 iop13xx_init_time(400000000);
82}
83
84static struct sys_timer iq81340mc_timer = {
85 .init = iq81340mc_timer_init,
86 .offset = iop13xx_gettimeoffset,
87};
88
89MACHINE_START(IQ81340MC, "Intel IQ81340MC")
90 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
91 .phys_io = PHYS_IO,
92 .io_pg_offst = IO_PG_OFFSET,
93 .map_io = iop13xx_map_io,
94 .init_irq = iop13xx_init_irq,
95 .timer = &iq81340mc_timer,
96 .boot_params = BOOT_PARAM_OFFSET,
97 .init_machine = iq81340mc_init,
98MACHINE_END
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
new file mode 100644
index 000000000000..6677e14b61bf
--- /dev/null
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -0,0 +1,100 @@
1/*
2 * iq81340sc board support
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/pci.h>
20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23#include <asm/mach/pci.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/arch/pci.h>
27#include <asm/mach/time.h>
28
29extern int init_atu;
30
31static int __init
32iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
33{
34 WARN_ON(idsel < 1 || idsel > 2);
35
36 switch (idsel) {
37 case 1:
38 switch (pin) {
39 case 1: return ATUX_INTB;
40 case 2: return ATUX_INTC;
41 case 3: return ATUX_INTD;
42 case 4: return ATUX_INTA;
43 default: return -1;
44 }
45 case 2:
46 switch (pin) {
47 case 1: return ATUX_INTC;
48 case 2: return ATUX_INTC;
49 case 3: return ATUX_INTC;
50 case 4: return ATUX_INTC;
51 default: return -1;
52 }
53 default: return -1;
54 }
55}
56
57static struct hw_pci iq81340sc_pci __initdata = {
58 .swizzle = pci_std_swizzle,
59 .nr_controllers = 0,
60 .setup = iop13xx_pci_setup,
61 .scan = iop13xx_scan_bus,
62 .map_irq = iq81340sc_atux_map_irq,
63 .preinit = iop13xx_pci_init
64};
65
66static int __init iq81340sc_pci_init(void)
67{
68 iop13xx_atu_select(&iq81340sc_pci);
69 pci_common_init(&iq81340sc_pci);
70 iop13xx_map_pci_memory();
71
72 return 0;
73}
74
75static void __init iq81340sc_init(void)
76{
77 iop13xx_platform_init();
78 iq81340sc_pci_init();
79}
80
81static void __init iq81340sc_timer_init(void)
82{
83 iop13xx_init_time(400000000);
84}
85
86static struct sys_timer iq81340sc_timer = {
87 .init = iq81340sc_timer_init,
88 .offset = iop13xx_gettimeoffset,
89};
90
91MACHINE_START(IQ81340SC, "Intel IQ81340SC")
92 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
93 .phys_io = PHYS_IO,
94 .io_pg_offst = IO_PG_OFFSET,
95 .map_io = iop13xx_map_io,
96 .init_irq = iop13xx_init_irq,
97 .timer = &iq81340sc_timer,
98 .boot_params = BOOT_PARAM_OFFSET,
99 .init_machine = iq81340sc_init,
100MACHINE_END
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
new file mode 100644
index 000000000000..c4d9c8c5579c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -0,0 +1,286 @@
1/*
2 * iop13xx IRQ handling / support functions
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/sysctl.h>
23#include <asm/uaccess.h>
24#include <asm/mach/irq.h>
25#include <asm/irq.h>
26#include <asm/hardware.h>
27#include <asm/mach-types.h>
28#include <asm/arch/irqs.h>
29
30/* INTCTL0 CP6 R0 Page 4
31 */
32static inline u32 read_intctl_0(void)
33{
34 u32 val;
35 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
36 return val;
37}
38static inline void write_intctl_0(u32 val)
39{
40 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
41}
42
43/* INTCTL1 CP6 R1 Page 4
44 */
45static inline u32 read_intctl_1(void)
46{
47 u32 val;
48 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
49 return val;
50}
51static inline void write_intctl_1(u32 val)
52{
53 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
54}
55
56/* INTCTL2 CP6 R2 Page 4
57 */
58static inline u32 read_intctl_2(void)
59{
60 u32 val;
61 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
62 return val;
63}
64static inline void write_intctl_2(u32 val)
65{
66 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
67}
68
69/* INTCTL3 CP6 R3 Page 4
70 */
71static inline u32 read_intctl_3(void)
72{
73 u32 val;
74 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
75 return val;
76}
77static inline void write_intctl_3(u32 val)
78{
79 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
80}
81
82/* INTSTR0 CP6 R0 Page 5
83 */
84static inline u32 read_intstr_0(void)
85{
86 u32 val;
87 asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
88 return val;
89}
90static inline void write_intstr_0(u32 val)
91{
92 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
93}
94
95/* INTSTR1 CP6 R1 Page 5
96 */
97static inline u32 read_intstr_1(void)
98{
99 u32 val;
100 asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
101 return val;
102}
103static void write_intstr_1(u32 val)
104{
105 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
106}
107
108/* INTSTR2 CP6 R2 Page 5
109 */
110static inline u32 read_intstr_2(void)
111{
112 u32 val;
113 asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
114 return val;
115}
116static void write_intstr_2(u32 val)
117{
118 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
119}
120
121/* INTSTR3 CP6 R3 Page 5
122 */
123static inline u32 read_intstr_3(void)
124{
125 u32 val;
126 asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
127 return val;
128}
129static void write_intstr_3(u32 val)
130{
131 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
132}
133
134/* INTBASE CP6 R0 Page 2
135 */
136static inline u32 read_intbase(void)
137{
138 u32 val;
139 asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
140 return val;
141}
142static void write_intbase(u32 val)
143{
144 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
145}
146
147/* INTSIZE CP6 R2 Page 2
148 */
149static inline u32 read_intsize(void)
150{
151 u32 val;
152 asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
153 return val;
154}
155static void write_intsize(u32 val)
156{
157 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
158}
159
160/* 0 = Interrupt Masked and 1 = Interrupt not masked */
161static void
162iop13xx_irq_mask0 (unsigned int irq)
163{
164 u32 cp_flags = iop13xx_cp6_save();
165 write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
166 iop13xx_cp6_restore(cp_flags);
167}
168
169static void
170iop13xx_irq_mask1 (unsigned int irq)
171{
172 u32 cp_flags = iop13xx_cp6_save();
173 write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
174 iop13xx_cp6_restore(cp_flags);
175}
176
177static void
178iop13xx_irq_mask2 (unsigned int irq)
179{
180 u32 cp_flags = iop13xx_cp6_save();
181 write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
182 iop13xx_cp6_restore(cp_flags);
183}
184
185static void
186iop13xx_irq_mask3 (unsigned int irq)
187{
188 u32 cp_flags = iop13xx_cp6_save();
189 write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
190 iop13xx_cp6_restore(cp_flags);
191}
192
193static void
194iop13xx_irq_unmask0(unsigned int irq)
195{
196 u32 cp_flags = iop13xx_cp6_save();
197 write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
198 iop13xx_cp6_restore(cp_flags);
199}
200
201static void
202iop13xx_irq_unmask1(unsigned int irq)
203{
204 u32 cp_flags = iop13xx_cp6_save();
205 write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
206 iop13xx_cp6_restore(cp_flags);
207}
208
209static void
210iop13xx_irq_unmask2(unsigned int irq)
211{
212 u32 cp_flags = iop13xx_cp6_save();
213 write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
214 iop13xx_cp6_restore(cp_flags);
215}
216
217static void
218iop13xx_irq_unmask3(unsigned int irq)
219{
220 u32 cp_flags = iop13xx_cp6_save();
221 write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
222 iop13xx_cp6_restore(cp_flags);
223}
224
225static struct irqchip iop13xx_irqchip0 = {
226 .ack = iop13xx_irq_mask0,
227 .mask = iop13xx_irq_mask0,
228 .unmask = iop13xx_irq_unmask0,
229};
230
231static struct irqchip iop13xx_irqchip1 = {
232 .ack = iop13xx_irq_mask1,
233 .mask = iop13xx_irq_mask1,
234 .unmask = iop13xx_irq_unmask1,
235};
236
237static struct irqchip iop13xx_irqchip2 = {
238 .ack = iop13xx_irq_mask2,
239 .mask = iop13xx_irq_mask2,
240 .unmask = iop13xx_irq_unmask2,
241};
242
243static struct irqchip iop13xx_irqchip3 = {
244 .ack = iop13xx_irq_mask3,
245 .mask = iop13xx_irq_mask3,
246 .unmask = iop13xx_irq_unmask3,
247};
248
249void __init iop13xx_init_irq(void)
250{
251 unsigned int i;
252
253 u32 cp_flags = iop13xx_cp6_save();
254
255 /* disable all interrupts */
256 write_intctl_0(0);
257 write_intctl_1(0);
258 write_intctl_2(0);
259 write_intctl_3(0);
260
261 /* treat all as IRQ */
262 write_intstr_0(0);
263 write_intstr_1(0);
264 write_intstr_2(0);
265 write_intstr_3(0);
266
267 /* initialize the interrupt vector generator */
268 write_intbase(INTBASE);
269 write_intsize(INTSIZE_4);
270
271 for(i = 0; i < NR_IOP13XX_IRQS; i++) {
272 if (i < 32)
273 set_irq_chip(i, &iop13xx_irqchip0);
274 else if (i < 64)
275 set_irq_chip(i, &iop13xx_irqchip1);
276 else if (i < 96)
277 set_irq_chip(i, &iop13xx_irqchip2);
278 else
279 set_irq_chip(i, &iop13xx_irqchip3);
280
281 set_irq_handler(i, do_level_IRQ);
282 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
283 }
284
285 iop13xx_cp6_restore(cp_flags);
286}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
new file mode 100644
index 000000000000..89ec70ea3187
--- /dev/null
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -0,0 +1,1113 @@
1/*
2 * iop13xx PCI support
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19
20#include <linux/pci.h>
21#include <linux/delay.h>
22
23#include <asm/irq.h>
24#include <asm/hardware.h>
25#include <asm/sizes.h>
26#include <asm/mach/pci.h>
27#include <asm/arch/pci.h>
28
29#define IOP13XX_PCI_DEBUG 0
30#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
31
32u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
33u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
34static struct pci_bus *pci_bus_atux = 0;
35static struct pci_bus *pci_bus_atue = 0;
36u32 iop13xx_atue_mem_base;
37u32 iop13xx_atux_mem_base;
38size_t iop13xx_atue_mem_size;
39size_t iop13xx_atux_mem_size;
40unsigned long iop13xx_pcibios_min_io = 0;
41unsigned long iop13xx_pcibios_min_mem = 0;
42
43EXPORT_SYMBOL(iop13xx_atue_mem_base);
44EXPORT_SYMBOL(iop13xx_atux_mem_base);
45EXPORT_SYMBOL(iop13xx_atue_mem_size);
46EXPORT_SYMBOL(iop13xx_atux_mem_size);
47
48int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
49static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
50 access */
51
52/* Scan the initialized busses and ioremap the requested memory range
53 */
54void iop13xx_map_pci_memory(void)
55{
56 int atu;
57 struct pci_bus *bus;
58 struct pci_dev *dev;
59 resource_size_t end = 0;
60
61 for (atu = 0; atu < 2; atu++) {
62 bus = atu ? pci_bus_atue : pci_bus_atux;
63 if (bus) {
64 list_for_each_entry(dev, &bus->devices, bus_list) {
65 int i;
66 int max = 7;
67
68 if (dev->subordinate)
69 max = DEVICE_COUNT_RESOURCE;
70
71 for (i = 0; i < max; i++) {
72 struct resource *res = &dev->resource[i];
73 if (res->flags & IORESOURCE_MEM)
74 end = max(res->end, end);
75 }
76 }
77
78 switch(atu) {
79 case 0:
80 iop13xx_atux_mem_size =
81 (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
82
83 /* 16MB align the request */
84 if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
85 iop13xx_atux_mem_size &= ~(SZ_16M - 1);
86 iop13xx_atux_mem_size += SZ_16M;
87 }
88
89 if (end) {
90 iop13xx_atux_mem_base =
91 (u32) __ioremap_pfn(
92 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
93 , 0, iop13xx_atux_mem_size, 0);
94 if (!iop13xx_atux_mem_base) {
95 printk("%s: atux allocation "
96 "failed\n", __FUNCTION__);
97 BUG();
98 }
99 } else
100 iop13xx_atux_mem_size = 0;
101 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
102 __FUNCTION__, atu, iop13xx_atux_mem_size,
103 iop13xx_atux_mem_base);
104 break;
105 case 1:
106 iop13xx_atue_mem_size =
107 (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
108
109 /* 16MB align the request */
110 if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
111 iop13xx_atue_mem_size &= ~(SZ_16M - 1);
112 iop13xx_atue_mem_size += SZ_16M;
113 }
114
115 if (end) {
116 iop13xx_atue_mem_base =
117 (u32) __ioremap_pfn(
118 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
119 , 0, iop13xx_atue_mem_size, 0);
120 if (!iop13xx_atue_mem_base) {
121 printk("%s: atue allocation "
122 "failed\n", __FUNCTION__);
123 BUG();
124 }
125 } else
126 iop13xx_atue_mem_size = 0;
127 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
128 __FUNCTION__, atu, iop13xx_atue_mem_size,
129 iop13xx_atue_mem_base);
130 break;
131 }
132
133 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
134 atu ? "ATUE" : "ATUX",
135 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
136 SZ_1M,
137 atu ? IOP13XX_PCIE_LOWER_MEM_RA :
138 IOP13XX_PCIX_LOWER_MEM_RA,
139 atu ? iop13xx_atue_mem_base :
140 iop13xx_atux_mem_base);
141 end = 0;
142 }
143
144 }
145}
146
147static inline int iop13xx_atu_function(int atu)
148{
149 int func = 0;
150 /* the function number depends on the value of the
151 * IOP13XX_INTERFACE_SEL_PCIX reset strap
152 * see C-Spec section 3.17
153 */
154 switch(atu) {
155 case IOP13XX_INIT_ATU_ATUX:
156 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
157 func = 5;
158 else
159 func = 0;
160 break;
161 case IOP13XX_INIT_ATU_ATUE:
162 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
163 func = 0;
164 else
165 func = 5;
166 break;
167 default:
168 BUG();
169 }
170
171 return func;
172}
173
174/* iop13xx_atux_cfg_address - format a configuration address for atux
175 * @bus: Target bus to access
176 * @devfn: Combined device number and function number
177 * @where: Desired register's address offset
178 *
179 * Convert the parameters to a configuration address formatted
180 * according the PCI-X 2.0 specification
181 */
182static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
183{
184 struct pci_sys_data *sys = bus->sysdata;
185 u32 addr;
186
187 if (sys->busnr == bus->number)
188 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
189 else
190 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
191
192 addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
193 addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
194
195 return addr;
196}
197
198/* iop13xx_atue_cfg_address - format a configuration address for atue
199 * @bus: Target bus to access
200 * @devfn: Combined device number and function number
201 * @where: Desired register's address offset
202 *
203 * Convert the parameters to an address usable by the ATUE_OCCAR
204 */
205static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
206{
207 struct pci_sys_data *sys = bus->sysdata;
208 u32 addr;
209
210 PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
211 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
212 addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM |
213 ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
214 ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
215 (where & ~0x3);
216
217 if (sys->busnr != bus->number)
218 addr |= 1; /* type 1 access */
219
220 return addr;
221}
222
223/* This routine checks the status of the last configuration cycle. If an error
224 * was detected it returns >0, else it returns a 0. The errors being checked
225 * are parity, master abort, target abort (master and target). These types of
226 * errors occure during a config cycle where there is no device, like during
227 * the discovery stage.
228 */
229static int iop13xx_atux_pci_status(int clear)
230{
231 unsigned int status;
232 int err = 0;
233
234 /*
235 * Check the status registers.
236 */
237 status = __raw_readw(IOP13XX_ATUX_ATUSR);
238 if (status & IOP_PCI_STATUS_ERROR)
239 {
240 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
241 if(clear)
242 __raw_writew(status & IOP_PCI_STATUS_ERROR,
243 IOP13XX_ATUX_ATUSR);
244 err = 1;
245 }
246 status = __raw_readl(IOP13XX_ATUX_ATUISR);
247 if (status & IOP13XX_ATUX_ATUISR_ERROR)
248 {
249 PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status);
250 if(clear)
251 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
252 IOP13XX_ATUX_ATUISR);
253 err = 1;
254 }
255 return err;
256}
257
258/* Simply write the address register and read the configuration
259 * data. Note that the data dependency on %0 encourages an abort
260 * to be detected before we return.
261 */
262static inline u32 iop13xx_atux_read(unsigned long addr)
263{
264 u32 val;
265
266 __asm__ __volatile__(
267 "str %1, [%2]\n\t"
268 "ldr %0, [%3]\n\t"
269 "mov %0, %0\n\t"
270 : "=r" (val)
271 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
272
273 return val;
274}
275
276/* The read routines must check the error status of the last configuration
277 * cycle. If there was an error, the routine returns all hex f's.
278 */
279static int
280iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
281 int size, u32 *value)
282{
283 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
284 u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
285
286 if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
287 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
288 IOP13XX_XBG_BECSR);
289 val = 0xffffffff;
290 }
291
292 *value = val;
293
294 return PCIBIOS_SUCCESSFUL;
295}
296
297static int
298iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
299 int size, u32 value)
300{
301 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
302 u32 val;
303
304 if (size != 4) {
305 val = iop13xx_atux_read(addr);
306 if (!iop13xx_atux_pci_status(1) == 0)
307 return PCIBIOS_SUCCESSFUL;
308
309 where = (where & 3) * 8;
310
311 if (size == 1)
312 val &= ~(0xff << where);
313 else
314 val &= ~(0xffff << where);
315
316 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
317 } else {
318 __raw_writel(addr, IOP13XX_ATUX_OCCAR);
319 __raw_writel(value, IOP13XX_ATUX_OCCDR);
320 }
321
322 return PCIBIOS_SUCCESSFUL;
323}
324
325static struct pci_ops iop13xx_atux_ops = {
326 .read = iop13xx_atux_read_config,
327 .write = iop13xx_atux_write_config,
328};
329
330/* This routine checks the status of the last configuration cycle. If an error
331 * was detected it returns >0, else it returns a 0. The errors being checked
332 * are parity, master abort, target abort (master and target). These types of
333 * errors occure during a config cycle where there is no device, like during
334 * the discovery stage.
335 */
336static int iop13xx_atue_pci_status(int clear)
337{
338 unsigned int status;
339 int err = 0;
340
341 /*
342 * Check the status registers.
343 */
344
345 /* standard pci status register */
346 status = __raw_readw(IOP13XX_ATUE_ATUSR);
347 if (status & IOP_PCI_STATUS_ERROR) {
348 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
349 if(clear)
350 __raw_writew(status & IOP_PCI_STATUS_ERROR,
351 IOP13XX_ATUE_ATUSR);
352 err++;
353 }
354
355 /* check the normal status bits in the ATUISR */
356 status = __raw_readl(IOP13XX_ATUE_ATUISR);
357 if (status & IOP13XX_ATUE_ATUISR_ERROR) {
358 PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
359 if (clear)
360 __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
361 IOP13XX_ATUE_ATUISR);
362 err++;
363
364 /* check the PCI-E status if the ATUISR reports an interface error */
365 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
366 /* get the unmasked errors */
367 status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
368 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
369
370 if (status) {
371 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
372 __raw_readl(IOP13XX_ATUE_PIE_STS));
373 err++;
374 } else {
375 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
376 __raw_readl(IOP13XX_ATUE_PIE_STS));
377 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
378 __raw_readl(IOP13XX_ATUE_PIE_MSK));
379 BUG();
380 }
381
382 if(clear)
383 __raw_writel(status, IOP13XX_ATUE_PIE_STS);
384 }
385 }
386
387 return err;
388}
389
390static inline int __init
391iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
392{
393 WARN_ON(idsel != 0);
394
395 switch (pin) {
396 case 1: return ATUE_INTA;
397 case 2: return ATUE_INTB;
398 case 3: return ATUE_INTC;
399 case 4: return ATUE_INTD;
400 default: return -1;
401 }
402}
403
404static inline u32 iop13xx_atue_read(unsigned long addr)
405{
406 u32 val;
407
408 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
409 val = __raw_readl(IOP13XX_ATUE_OCCDR);
410
411 rmb();
412
413 return val;
414}
415
416/* The read routines must check the error status of the last configuration
417 * cycle. If there was an error, the routine returns all hex f's.
418 */
419static int
420iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
421 int size, u32 *value)
422{
423 u32 val;
424 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
425
426 /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
427 if (!PCI_SLOT(devfn) || (addr & 1)) {
428 val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
429 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
430 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
431 IOP13XX_XBG_BECSR);
432 val = 0xffffffff;
433 }
434
435 PRINTK("addr=%#0lx, val=%#010x", addr, val);
436 } else
437 val = 0xffffffff;
438
439 *value = val;
440
441 return PCIBIOS_SUCCESSFUL;
442}
443
444static int
445iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
446 int size, u32 value)
447{
448 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
449 u32 val;
450
451 if (size != 4) {
452 val = iop13xx_atue_read(addr);
453 if (!iop13xx_atue_pci_status(1) == 0)
454 return PCIBIOS_SUCCESSFUL;
455
456 where = (where & 3) * 8;
457
458 if (size == 1)
459 val &= ~(0xff << where);
460 else
461 val &= ~(0xffff << where);
462
463 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
464 } else {
465 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
466 __raw_writel(value, IOP13XX_ATUE_OCCDR);
467 }
468
469 return PCIBIOS_SUCCESSFUL;
470}
471
472static struct pci_ops iop13xx_atue_ops = {
473 .read = iop13xx_atue_read_config,
474 .write = iop13xx_atue_write_config,
475};
476
477/* When a PCI device does not exist during config cycles, the XScale gets a
478 * bus error instead of returning 0xffffffff. We can't rely on the ATU status
479 * bits to tell us that it was indeed a configuration cycle that caused this
480 * error especially in the case when the ATUE link is down. Instead we rely
481 * on data from the south XSI bridge to validate the abort
482 */
483int
484iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
485{
486 PRINTK("Data abort: address = 0x%08lx "
487 "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
488 addr, fsr, regs->ARM_pc, regs->ARM_lr);
489
490 PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
491 PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
492 PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
493
494 /* If it was an imprecise abort, then we need to correct the
495 * return address to be _after_ the instruction.
496 */
497 if (fsr & (1 << 10))
498 regs->ARM_pc += 4;
499
500 if (is_atue_occdr_error() || is_atux_occdr_error())
501 return 0;
502 else
503 return 1;
504}
505
506/* Scan an IOP13XX PCI bus. nr selects which ATU we use.
507 */
508struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
509{
510 int which_atu;
511 struct pci_bus *bus = NULL;
512
513 switch (init_atu) {
514 case IOP13XX_INIT_ATU_ATUX:
515 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
516 break;
517 case IOP13XX_INIT_ATU_ATUE:
518 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
519 break;
520 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
521 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
522 break;
523 default:
524 which_atu = 0;
525 }
526
527 if (!which_atu) {
528 BUG();
529 return NULL;
530 }
531
532 switch (which_atu) {
533 case IOP13XX_INIT_ATU_ATUX:
534 if (time_after_eq(jiffies + msecs_to_jiffies(1000),
535 atux_trhfa_timeout)) /* ensure not wrap */
536 while(time_before(jiffies, atux_trhfa_timeout))
537 udelay(100);
538
539 bus = pci_bus_atux = pci_scan_bus(sys->busnr,
540 &iop13xx_atux_ops,
541 sys);
542 break;
543 case IOP13XX_INIT_ATU_ATUE:
544 bus = pci_bus_atue = pci_scan_bus(sys->busnr,
545 &iop13xx_atue_ops,
546 sys);
547 break;
548 }
549
550 return bus;
551}
552
553/* This function is called from iop13xx_pci_init() after assigning valid
554 * values to iop13xx_atue_pmmr_offset. This is the location for common
555 * setup of ATUE for all IOP13XX implementations.
556 */
557void __init iop13xx_atue_setup(void)
558{
559 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
560 u32 reg_val;
561
562 /* BAR 1 (1:1 mapping with Physical RAM) */
563 /* Set limit and enable */
564 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
565 IOP13XX_ATUE_IALR1);
566 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
567
568 /* Set base at the top of the reserved address space */
569 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
570 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
571
572 /* 1:1 mapping with physical ram
573 * (leave big endian byte swap disabled)
574 */
575 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
576 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
577
578 /* Outbound window 1 (PCIX/PCIE memory window) */
579 /* 32 bit Address Space */
580 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
581 /* PA[35:32] */
582 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
583 (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
584 IOP13XX_ATUE_OUMBAR1);
585
586 /* Setup the I/O Bar
587 * A[35-16] in 31-12
588 */
589 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
590 IOP13XX_ATUE_OIOBAR);
591 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
592
593 /* clear startup errors */
594 iop13xx_atue_pci_status(1);
595
596 /* OIOBAR function number
597 */
598 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
599 reg_val &= ~0x7;
600 reg_val |= func;
601 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
602
603 /* OUMBAR function numbers
604 */
605 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
606 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
607 IOP13XX_ATU_OUMBAR_FUNC_NUM);
608 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
609 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
610
611 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
612 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
613 IOP13XX_ATU_OUMBAR_FUNC_NUM);
614 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
615 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
616
617 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
618 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
619 IOP13XX_ATU_OUMBAR_FUNC_NUM);
620 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
621 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
622
623 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
624 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
625 IOP13XX_ATU_OUMBAR_FUNC_NUM);
626 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
627 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
628
629 /* Enable inbound and outbound cycles
630 */
631 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
632 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
633 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
634 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
635
636 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
637 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
638 IOP13XX_ATUE_ATUCR_IVM;
639 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
640}
641
642void __init iop13xx_atue_disable(void)
643{
644 u32 reg_val;
645
646 __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
647 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
648
649 /* wait for cycles to quiesce */
650 while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
651 IOP13XX_ATUE_PCSR_IN_Q_BUSY |
652 IOP13XX_ATUE_PCSR_LLRB_BUSY))
653 cpu_relax();
654
655 /* BAR 0 ( Disabled ) */
656 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
657 __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
658 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
659 __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
660 __raw_writel(0x0, IOP13XX_ATUE_IALR0);
661 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
662 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
663 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
664
665 /* BAR 1 ( Disabled ) */
666 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
667 __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
668 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
669 __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
670 __raw_writel(0x0, IOP13XX_ATUE_IALR1);
671 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
672 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
673 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
674
675 /* BAR 2 ( Disabled ) */
676 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
677 __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
678 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
679 __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
680 __raw_writel(0x0, IOP13XX_ATUE_IALR2);
681 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
682 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
683 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
684
685 /* BAR 3 ( Disabled ) */
686 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
687 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
688 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
689
690 /* Setup the I/O Bar
691 * A[35-16] in 31-12
692 */
693 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
694 IOP13XX_ATUE_OIOBAR);
695 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
696}
697
698/* This function is called from iop13xx_pci_init() after assigning valid
699 * values to iop13xx_atux_pmmr_offset. This is the location for common
700 * setup of ATUX for all IOP13XX implementations.
701 */
702void __init iop13xx_atux_setup(void)
703{
704 u32 reg_val;
705 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
706
707 /* Take PCI-X bus out of reset if bootloader hasn't already.
708 * According to spec, we should wait for 2^25 PCI clocks to meet
709 * the PCI timing parameter Trhfa (RST# high to first access).
710 * This is rarely necessary and often ignored.
711 */
712 reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
713 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
714 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
715 msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
716 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
717 IOP13XX_ATUX_PCSR);
718 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
719 }
720 else
721 atux_trhfa_timeout = jiffies;
722
723 /* BAR 1 (1:1 mapping with Physical RAM) */
724 /* Set limit and enable */
725 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
726 IOP13XX_ATUX_IALR1);
727 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
728
729 /* Set base at the top of the reserved address space */
730 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
731 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
732
733 /* 1:1 mapping with physical ram
734 * (leave big endian byte swap disabled)
735 */
736 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
737 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
738
739 /* Outbound window 1 (PCIX/PCIE memory window) */
740 /* 32 bit Address Space */
741 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
742 /* PA[35:32] */
743 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
744 IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
745 IOP13XX_ATUX_OUMBAR1);
746
747 /* Setup the I/O Bar
748 * A[35-16] in 31-12
749 */
750 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
751 IOP13XX_ATUX_OIOBAR);
752 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
753
754 /* clear startup errors */
755 iop13xx_atux_pci_status(1);
756
757 /* OIOBAR function number
758 */
759 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
760 reg_val &= ~0x7;
761 reg_val |= func;
762 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
763
764 /* OUMBAR function numbers
765 */
766 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
767 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
768 IOP13XX_ATU_OUMBAR_FUNC_NUM);
769 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
770 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
771
772 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
773 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
774 IOP13XX_ATU_OUMBAR_FUNC_NUM);
775 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
776 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
777
778 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
779 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
780 IOP13XX_ATU_OUMBAR_FUNC_NUM);
781 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
782 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
783
784 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
785 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
786 IOP13XX_ATU_OUMBAR_FUNC_NUM);
787 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
788 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
789
790 /* Enable inbound and outbound cycles
791 */
792 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
793 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
794 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
795 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
796
797 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
798 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
799 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
800}
801
802void __init iop13xx_atux_disable(void)
803{
804 u32 reg_val;
805
806 __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
807 __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
808
809 /* wait for cycles to quiesce */
810 while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
811 IOP13XX_ATUX_PCSR_IN_Q_BUSY))
812 cpu_relax();
813
814 /* BAR 0 ( Disabled ) */
815 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
816 __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
817 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
818 __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
819 __raw_writel(0x0, IOP13XX_ATUX_IALR0);
820 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
821 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
822 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
823
824 /* BAR 1 ( Disabled ) */
825 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
826 __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
827 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
828 __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
829 __raw_writel(0x0, IOP13XX_ATUX_IALR1);
830 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
831 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
832 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
833
834 /* BAR 2 ( Disabled ) */
835 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
836 __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
837 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
838 __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
839 __raw_writel(0x0, IOP13XX_ATUX_IALR2);
840 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
841 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
842 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
843
844 /* BAR 3 ( Disabled ) */
845 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
846 __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
847 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
848 __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
849 __raw_writel(0x0, IOP13XX_ATUX_IALR3);
850 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
851 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
852 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
853
854 /* Setup the I/O Bar
855 * A[35-16] in 31-12
856 */
857 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
858 IOP13XX_ATUX_OIOBAR);
859 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
860}
861
862void __init iop13xx_set_atu_mmr_bases(void)
863{
864 /* Based on ESSR0, determine the ATU X/E offsets */
865 switch(__raw_readl(IOP13XX_ESSR0) &
866 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
867 /* both asserted */
868 case 0:
869 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
870 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
871 break;
872 /* IOP13XX_CONTROLLER_ONLY = deasserted
873 * IOP13XX_INTERFACE_SEL_PCIX = asserted
874 */
875 case IOP13XX_CONTROLLER_ONLY:
876 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
877 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
878 break;
879 /* IOP13XX_CONTROLLER_ONLY = asserted
880 * IOP13XX_INTERFACE_SEL_PCIX = deasserted
881 */
882 case IOP13XX_INTERFACE_SEL_PCIX:
883 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
884 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
885 break;
886 /* both deasserted */
887 case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
888 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
889 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
890 break;
891 default:
892 BUG();
893 }
894}
895
896void __init iop13xx_atu_select(struct hw_pci *plat_pci)
897{
898 int i;
899
900 /* set system defaults
901 * note: if "iop13xx_init_atu=" is specified this autodetect
902 * sequence will be bypassed
903 */
904 if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
905 /* check for single/dual interface */
906 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
907 /* ATUE must be present check the device id
908 * to see if ATUX is present.
909 */
910 init_atu |= IOP13XX_INIT_ATU_ATUE;
911 switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
912 case 0x70:
913 case 0x80:
914 case 0xc0:
915 init_atu |= IOP13XX_INIT_ATU_ATUX;
916 break;
917 }
918 } else {
919 /* ATUX must be present check the device id
920 * to see if ATUE is present.
921 */
922 init_atu |= IOP13XX_INIT_ATU_ATUX;
923 switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
924 case 0x70:
925 case 0x80:
926 case 0xc0:
927 init_atu |= IOP13XX_INIT_ATU_ATUE;
928 break;
929 }
930 }
931
932 /* check central resource and root complex capability */
933 if (init_atu & IOP13XX_INIT_ATU_ATUX)
934 if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
935 IOP13XX_ATUX_PCSR_CENTRAL_RES))
936 init_atu &= ~IOP13XX_INIT_ATU_ATUX;
937
938 if (init_atu & IOP13XX_INIT_ATU_ATUE)
939 if (__raw_readl(IOP13XX_ATUE_PCSR) &
940 IOP13XX_ATUE_PCSR_END_POINT)
941 init_atu &= ~IOP13XX_INIT_ATU_ATUE;
942 }
943
944 for (i = 0; i < 2; i++) {
945 if((init_atu & (1 << i)) == (1 << i))
946 plat_pci->nr_controllers++;
947 }
948}
949
950void __init iop13xx_pci_init(void)
951{
952 /* clear pre-existing south bridge errors */
953 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
954
955 /* Setup the Min Address for PCI memory... */
956 iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
957
958 /* if Linux is given control of an ATU
959 * clear out its prior configuration,
960 * otherwise do not touch the registers
961 */
962 if (init_atu & IOP13XX_INIT_ATU_ATUE) {
963 iop13xx_atue_disable();
964 iop13xx_atue_setup();
965 }
966
967 if (init_atu & IOP13XX_INIT_ATU_ATUX) {
968 iop13xx_atux_disable();
969 iop13xx_atux_setup();
970 }
971
972 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS,
973 "imprecise external abort");
974}
975
976/* intialize the pci memory space. handle any combination of
977 * atue and atux enabled/disabled
978 */
979int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
980{
981 struct resource *res;
982 int which_atu;
983 u32 pcixsr, pcsr;
984
985 if (nr > 1)
986 return 0;
987
988 res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
989 if (!res)
990 panic("PCI: unable to alloc resources");
991
992 memset(res, 0, sizeof(struct resource) * 2);
993
994 /* 'nr' assumptions:
995 * ATUX is always 0
996 * ATUE is 1 when ATUX is also enabled
997 * ATUE is 0 when ATUX is disabled
998 */
999 switch(init_atu) {
1000 case IOP13XX_INIT_ATU_ATUX:
1001 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
1002 break;
1003 case IOP13XX_INIT_ATU_ATUE:
1004 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
1005 break;
1006 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
1007 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
1008 break;
1009 default:
1010 which_atu = 0;
1011 }
1012
1013 if (!which_atu)
1014 return 0;
1015
1016 switch(which_atu) {
1017 case IOP13XX_INIT_ATU_ATUX:
1018 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
1019 pcixsr &= ~0xffff;
1020 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
1021 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
1022 iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
1023 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1024 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1025
1026 res[0].start = IOP13XX_PCIX_LOWER_IO_PA;
1027 res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
1028 res[0].name = "IQ81340 ATUX PCI I/O Space";
1029 res[0].flags = IORESOURCE_IO;
1030
1031 res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
1032 res[1].end = IOP13XX_PCIX_UPPER_MEM_RA;
1033 res[1].name = "IQ81340 ATUX PCI Memory Space";
1034 res[1].flags = IORESOURCE_MEM;
1035 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1036 sys->io_offset = IOP13XX_PCIX_IO_OFFSET;
1037 break;
1038 case IOP13XX_INIT_ATU_ATUE:
1039 /* Note: the function number field in the PCSR is ro */
1040 pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
1041 pcsr &= ~(0xfff8 << 16);
1042 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
1043 0 << IOP13XX_ATUE_PCSR_DEV_NUM;
1044
1045 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1046
1047 res[0].start = IOP13XX_PCIE_LOWER_IO_PA;
1048 res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
1049 res[0].name = "IQ81340 ATUE PCI I/O Space";
1050 res[0].flags = IORESOURCE_IO;
1051
1052 res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
1053 res[1].end = IOP13XX_PCIE_UPPER_MEM_RA;
1054 res[1].name = "IQ81340 ATUE PCI Memory Space";
1055 res[1].flags = IORESOURCE_MEM;
1056 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1057 sys->io_offset = IOP13XX_PCIE_IO_OFFSET;
1058 sys->map_irq = iop13xx_pcie_map_irq;
1059 break;
1060 default:
1061 return 0;
1062 }
1063
1064 request_resource(&ioport_resource, &res[0]);
1065 request_resource(&iomem_resource, &res[1]);
1066
1067 sys->resource[0] = &res[0];
1068 sys->resource[1] = &res[1];
1069 sys->resource[2] = NULL;
1070
1071 return 1;
1072}
1073
1074u16 iop13xx_dev_id(void)
1075{
1076 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
1077 return __raw_readw(IOP13XX_ATUE_DID);
1078 else
1079 return __raw_readw(IOP13XX_ATUX_DID);
1080}
1081
1082static int __init iop13xx_init_atu_setup(char *str)
1083{
1084 init_atu = IOP13XX_INIT_ATU_NONE;
1085 if (str) {
1086 while (*str != '\0') {
1087 switch (*str) {
1088 case 'x':
1089 case 'X':
1090 init_atu |= IOP13XX_INIT_ATU_ATUX;
1091 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1092 break;
1093 case 'e':
1094 case 'E':
1095 init_atu |= IOP13XX_INIT_ATU_ATUE;
1096 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1097 break;
1098 case ',':
1099 case '=':
1100 break;
1101 default:
1102 PRINTK("\"iop13xx_init_atu\" malformed at "
1103 "character: \'%c\'", *str);
1104 *(str + 1) = '\0';
1105 init_atu = IOP13XX_INIT_ATU_DEFAULT;
1106 }
1107 str++;
1108 }
1109 }
1110 return 1;
1111}
1112
1113__setup("iop13xx_init_atu", iop13xx_init_atu_setup);
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
new file mode 100644
index 000000000000..3756d2ccb1a7
--- /dev/null
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -0,0 +1,406 @@
1/*
2 * iop13xx platform Initialization
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19
20#include <linux/serial_8250.h>
21#ifdef CONFIG_MTD_PHYSMAP
22#include <linux/mtd/physmap.h>
23#endif
24#include <asm/mach/map.h>
25#include <asm/hardware.h>
26#include <asm/irq.h>
27
28#define IOP13XX_UART_XTAL 33334000
29#define IOP13XX_SETUP_DEBUG 0
30#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
31
32/* Standard IO mapping for all IOP13XX based systems
33 */
34static struct map_desc iop13xx_std_desc[] __initdata = {
35 { /* mem mapped registers */
36 .virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
37 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
38 .length = IOP13XX_PMMR_SIZE,
39 .type = MT_DEVICE,
40 }, { /* PCIE IO space */
41 .virtual = IOP13XX_PCIE_LOWER_IO_VA,
42 .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
43 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
44 .type = MT_DEVICE,
45 }, { /* PCIX IO space */
46 .virtual = IOP13XX_PCIX_LOWER_IO_VA,
47 .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
48 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
49 .type = MT_DEVICE,
50 },
51};
52
53static struct resource iop13xx_uart0_resources[] = {
54 [0] = {
55 .start = IOP13XX_UART0_PHYS,
56 .end = IOP13XX_UART0_PHYS + 0x3f,
57 .flags = IORESOURCE_MEM,
58 },
59 [1] = {
60 .start = IRQ_IOP13XX_UART0,
61 .end = IRQ_IOP13XX_UART0,
62 .flags = IORESOURCE_IRQ
63 }
64};
65
66static struct resource iop13xx_uart1_resources[] = {
67 [0] = {
68 .start = IOP13XX_UART1_PHYS,
69 .end = IOP13XX_UART1_PHYS + 0x3f,
70 .flags = IORESOURCE_MEM,
71 },
72 [1] = {
73 .start = IRQ_IOP13XX_UART1,
74 .end = IRQ_IOP13XX_UART1,
75 .flags = IORESOURCE_IRQ
76 }
77};
78
79static struct plat_serial8250_port iop13xx_uart0_data[] = {
80 {
81 .membase = (char*)(IOP13XX_UART0_VIRT),
82 .mapbase = (IOP13XX_UART0_PHYS),
83 .irq = IRQ_IOP13XX_UART0,
84 .uartclk = IOP13XX_UART_XTAL,
85 .regshift = 2,
86 .iotype = UPIO_MEM,
87 .flags = UPF_SKIP_TEST,
88 },
89 { },
90};
91
92static struct plat_serial8250_port iop13xx_uart1_data[] = {
93 {
94 .membase = (char*)(IOP13XX_UART1_VIRT),
95 .mapbase = (IOP13XX_UART1_PHYS),
96 .irq = IRQ_IOP13XX_UART1,
97 .uartclk = IOP13XX_UART_XTAL,
98 .regshift = 2,
99 .iotype = UPIO_MEM,
100 .flags = UPF_SKIP_TEST,
101 },
102 { },
103};
104
105/* The ids are fixed up later in iop13xx_platform_init */
106static struct platform_device iop13xx_uart0 = {
107 .name = "serial8250",
108 .id = 0,
109 .dev.platform_data = iop13xx_uart0_data,
110 .num_resources = 2,
111 .resource = iop13xx_uart0_resources,
112};
113
114static struct platform_device iop13xx_uart1 = {
115 .name = "serial8250",
116 .id = 0,
117 .dev.platform_data = iop13xx_uart1_data,
118 .num_resources = 2,
119 .resource = iop13xx_uart1_resources
120};
121
122static struct resource iop13xx_i2c_0_resources[] = {
123 [0] = {
124 .start = IOP13XX_I2C0_PHYS,
125 .end = IOP13XX_I2C0_PHYS + 0x18,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = IRQ_IOP13XX_I2C_0,
130 .end = IRQ_IOP13XX_I2C_0,
131 .flags = IORESOURCE_IRQ
132 }
133};
134
135static struct resource iop13xx_i2c_1_resources[] = {
136 [0] = {
137 .start = IOP13XX_I2C1_PHYS,
138 .end = IOP13XX_I2C1_PHYS + 0x18,
139 .flags = IORESOURCE_MEM,
140 },
141 [1] = {
142 .start = IRQ_IOP13XX_I2C_1,
143 .end = IRQ_IOP13XX_I2C_1,
144 .flags = IORESOURCE_IRQ
145 }
146};
147
148static struct resource iop13xx_i2c_2_resources[] = {
149 [0] = {
150 .start = IOP13XX_I2C2_PHYS,
151 .end = IOP13XX_I2C2_PHYS + 0x18,
152 .flags = IORESOURCE_MEM,
153 },
154 [1] = {
155 .start = IRQ_IOP13XX_I2C_2,
156 .end = IRQ_IOP13XX_I2C_2,
157 .flags = IORESOURCE_IRQ
158 }
159};
160
161/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
162 * we just use the same device name.
163 */
164
165/* The ids are fixed up later in iop13xx_platform_init */
166static struct platform_device iop13xx_i2c_0_controller = {
167 .name = "IOP3xx-I2C",
168 .id = 0,
169 .num_resources = 2,
170 .resource = iop13xx_i2c_0_resources
171};
172
173static struct platform_device iop13xx_i2c_1_controller = {
174 .name = "IOP3xx-I2C",
175 .id = 0,
176 .num_resources = 2,
177 .resource = iop13xx_i2c_1_resources
178};
179
180static struct platform_device iop13xx_i2c_2_controller = {
181 .name = "IOP3xx-I2C",
182 .id = 0,
183 .num_resources = 2,
184 .resource = iop13xx_i2c_2_resources
185};
186
187#ifdef CONFIG_MTD_PHYSMAP
188/* PBI Flash Device
189 */
190static struct physmap_flash_data iq8134x_flash_data = {
191 .width = 2,
192};
193
194static struct resource iq8134x_flash_resource = {
195 .start = IQ81340_FLASHBASE,
196 .end = 0,
197 .flags = IORESOURCE_MEM,
198};
199
200static struct platform_device iq8134x_flash = {
201 .name = "physmap-flash",
202 .id = 0,
203 .dev = { .platform_data = &iq8134x_flash_data, },
204 .num_resources = 1,
205 .resource = &iq8134x_flash_resource,
206};
207
208static unsigned long iq8134x_probe_flash_size(void)
209{
210 uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
211 int i;
212 char query[3];
213 unsigned long size = 0;
214 int width = iq8134x_flash_data.width;
215
216 if (flash_addr) {
217 /* send CFI 'query' command */
218 writew(0x98, flash_addr);
219
220 /* check for CFI compliance */
221 for (i = 0; i < 3 * width; i += width)
222 query[i / width] = readb(flash_addr + (0x10 * width) + i);
223
224 /* read the size */
225 if (memcmp(query, "QRY", 3) == 0)
226 size = 1 << readb(flash_addr + (0x27 * width));
227
228 /* send CFI 'read array' command */
229 writew(0xff, flash_addr);
230
231 iounmap(flash_addr);
232 }
233
234 return size;
235}
236#endif
237
238void __init iop13xx_map_io(void)
239{
240 /* Initialize the Static Page Table maps */
241 iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
242}
243
244static int init_uart = 0;
245static int init_i2c = 0;
246
247void __init iop13xx_platform_init(void)
248{
249 int i;
250 u32 uart_idx, i2c_idx, plat_idx;
251 struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
252
253 /* set the bases so we can read the device id */
254 iop13xx_set_atu_mmr_bases();
255
256 memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
257
258 if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
259 switch (iop13xx_dev_id()) {
260 /* enable both uarts on iop341 and iop342 */
261 case 0x3380:
262 case 0x3384:
263 case 0x3388:
264 case 0x338c:
265 case 0x3382:
266 case 0x3386:
267 case 0x338a:
268 case 0x338e:
269 init_uart |= IOP13XX_INIT_UART_0;
270 init_uart |= IOP13XX_INIT_UART_1;
271 break;
272 /* only enable uart 1 */
273 default:
274 init_uart |= IOP13XX_INIT_UART_1;
275 }
276 }
277
278 if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
279 switch (iop13xx_dev_id()) {
280 /* enable all i2c units on iop341 and iop342 */
281 case 0x3380:
282 case 0x3384:
283 case 0x3388:
284 case 0x338c:
285 case 0x3382:
286 case 0x3386:
287 case 0x338a:
288 case 0x338e:
289 init_i2c |= IOP13XX_INIT_I2C_0;
290 init_i2c |= IOP13XX_INIT_I2C_1;
291 init_i2c |= IOP13XX_INIT_I2C_2;
292 break;
293 /* only enable i2c 1 and 2 */
294 default:
295 init_i2c |= IOP13XX_INIT_I2C_1;
296 init_i2c |= IOP13XX_INIT_I2C_2;
297 }
298 }
299
300 plat_idx = 0;
301 uart_idx = 0;
302 i2c_idx = 0;
303
304 /* uart 1 (if enabled) is ttyS0 */
305 if (init_uart & IOP13XX_INIT_UART_1) {
306 PRINTK("Adding uart1 to platform device list\n");
307 iop13xx_uart1.id = uart_idx++;
308 iop13xx_devices[plat_idx++] = &iop13xx_uart1;
309 }
310 if (init_uart & IOP13XX_INIT_UART_0) {
311 PRINTK("Adding uart0 to platform device list\n");
312 iop13xx_uart0.id = uart_idx++;
313 iop13xx_devices[plat_idx++] = &iop13xx_uart0;
314 }
315
316 for(i = 0; i < IQ81340_NUM_I2C; i++) {
317 if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
318 printk("Adding i2c%d to platform device list\n", i);
319 switch(init_i2c & (1 << i)) {
320 case IOP13XX_INIT_I2C_0:
321 iop13xx_i2c_0_controller.id = i2c_idx++;
322 iop13xx_devices[plat_idx++] =
323 &iop13xx_i2c_0_controller;
324 break;
325 case IOP13XX_INIT_I2C_1:
326 iop13xx_i2c_1_controller.id = i2c_idx++;
327 iop13xx_devices[plat_idx++] =
328 &iop13xx_i2c_1_controller;
329 break;
330 case IOP13XX_INIT_I2C_2:
331 iop13xx_i2c_2_controller.id = i2c_idx++;
332 iop13xx_devices[plat_idx++] =
333 &iop13xx_i2c_2_controller;
334 break;
335 }
336 }
337
338#ifdef CONFIG_MTD_PHYSMAP
339 iq8134x_flash_resource.end = iq8134x_flash_resource.start +
340 iq8134x_probe_flash_size();
341 if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
342 iop13xx_devices[plat_idx++] = &iq8134x_flash;
343 else
344 printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
345#endif
346
347 platform_add_devices(iop13xx_devices, plat_idx);
348}
349
350static int __init iop13xx_init_uart_setup(char *str)
351{
352 if (str) {
353 while (*str != '\0') {
354 switch(*str) {
355 case '0':
356 init_uart |= IOP13XX_INIT_UART_0;
357 break;
358 case '1':
359 init_uart |= IOP13XX_INIT_UART_1;
360 break;
361 case ',':
362 case '=':
363 break;
364 default:
365 PRINTK("\"iop13xx_init_uart\" malformed"
366 " at character: \'%c\'", *str);
367 *(str + 1) = '\0';
368 init_uart = IOP13XX_INIT_UART_DEFAULT;
369 }
370 str++;
371 }
372 }
373 return 1;
374}
375
376static int __init iop13xx_init_i2c_setup(char *str)
377{
378 if (str) {
379 while (*str != '\0') {
380 switch(*str) {
381 case '0':
382 init_i2c |= IOP13XX_INIT_I2C_0;
383 break;
384 case '1':
385 init_i2c |= IOP13XX_INIT_I2C_1;
386 break;
387 case '2':
388 init_i2c |= IOP13XX_INIT_I2C_2;
389 break;
390 case ',':
391 case '=':
392 break;
393 default:
394 PRINTK("\"iop13xx_init_i2c\" malformed"
395 " at character: \'%c\'", *str);
396 *(str + 1) = '\0';
397 init_i2c = IOP13XX_INIT_I2C_DEFAULT;
398 }
399 str++;
400 }
401 }
402 return 1;
403}
404
405__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
406__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
diff --git a/arch/arm/mach-iop13xx/time.c b/arch/arm/mach-iop13xx/time.c
new file mode 100644
index 000000000000..8b21365f653f
--- /dev/null
+++ b/arch/arm/mach-iop13xx/time.c
@@ -0,0 +1,102 @@
1/*
2 * arch/arm/mach-iop13xx/time.c
3 *
4 * Timer code for IOP13xx (copied from IOP32x/IOP33x implementation)
5 *
6 * Author: Deepak Saxena <dsaxena@mvista.com>
7 *
8 * Copyright 2002-2003 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/time.h>
19#include <linux/init.h>
20#include <linux/timex.h>
21#include <asm/io.h>
22#include <asm/irq.h>
23#include <asm/uaccess.h>
24#include <asm/mach/irq.h>
25#include <asm/mach/time.h>
26
27static unsigned long ticks_per_jiffy;
28static unsigned long ticks_per_usec;
29static unsigned long next_jiffy_time;
30
31static inline u32 read_tcr1(void)
32{
33 u32 val;
34 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
35 return val;
36}
37
38unsigned long iop13xx_gettimeoffset(void)
39{
40 unsigned long offset;
41 u32 cp_flags;
42
43 cp_flags = iop13xx_cp6_save();
44 offset = next_jiffy_time - read_tcr1();
45 iop13xx_cp6_restore(cp_flags);
46
47 return offset / ticks_per_usec;
48}
49
50static irqreturn_t
51iop13xx_timer_interrupt(int irq, void *dev_id)
52{
53 u32 cp_flags = iop13xx_cp6_save();
54
55 write_seqlock(&xtime_lock);
56
57 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1));
58
59 while ((signed long)(next_jiffy_time - read_tcr1())
60 >= ticks_per_jiffy) {
61 timer_tick();
62 next_jiffy_time -= ticks_per_jiffy;
63 }
64
65 write_sequnlock(&xtime_lock);
66
67 iop13xx_cp6_restore(cp_flags);
68
69 return IRQ_HANDLED;
70}
71
72static struct irqaction iop13xx_timer_irq = {
73 .name = "IOP13XX Timer Tick",
74 .handler = iop13xx_timer_interrupt,
75 .flags = IRQF_DISABLED | IRQF_TIMER,
76};
77
78void __init iop13xx_init_time(unsigned long tick_rate)
79{
80 u32 timer_ctl;
81 u32 cp_flags;
82
83 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
84 ticks_per_usec = tick_rate / 1000000;
85 next_jiffy_time = 0xffffffff;
86
87 timer_ctl = IOP13XX_TMR_EN | IOP13XX_TMR_PRIVILEGED |
88 IOP13XX_TMR_RELOAD | IOP13XX_TMR_RATIO_1_1;
89
90 /*
91 * We use timer 0 for our timer interrupt, and timer 1 as
92 * monotonic counter for tracking missed jiffies.
93 */
94 cp_flags = iop13xx_cp6_save();
95 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1));
96 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl));
97 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff));
98 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl));
99 iop13xx_cp6_restore(cp_flags);
100
101 setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq);
102}
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index 69d6302f40cf..3ec1cd5c4f99 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -70,7 +70,7 @@ void __init iop32x_init_irq(void)
70 70
71 for (i = 0; i < NR_IRQS; i++) { 71 for (i = 0; i < NR_IRQS; i++) {
72 set_irq_chip(i, &ext_chip); 72 set_irq_chip(i, &ext_chip);
73 set_irq_handler(i, do_level_IRQ); 73 set_irq_handler(i, handle_level_irq);
74 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 74 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
75 } 75 }
76} 76}
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 63304b3d0d76..00b37f32d72e 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -121,7 +121,7 @@ void __init iop33x_init_irq(void)
121 121
122 for (i = 0; i < NR_IRQS; i++) { 122 for (i = 0; i < NR_IRQS; i++) {
123 set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); 123 set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
124 set_irq_handler(i, do_level_IRQ); 124 set_irq_handler(i, handle_level_irq);
125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
126 } 126 }
127} 127}
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 22c98e9dad28..27b7480f4afe 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -308,7 +308,7 @@ EXPORT_SYMBOL(gpio_line_config);
308/************************************************************************* 308/*************************************************************************
309 * IRQ handling IXP2000 309 * IRQ handling IXP2000
310 *************************************************************************/ 310 *************************************************************************/
311static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc) 311static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
312{ 312{
313 int i; 313 int i;
314 unsigned long status = *IXP2000_GPIO_INST; 314 unsigned long status = *IXP2000_GPIO_INST;
@@ -373,7 +373,7 @@ static void ixp2000_GPIO_irq_unmask(unsigned int irq)
373 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0))); 373 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
374} 374}
375 375
376static struct irqchip ixp2000_GPIO_irq_chip = { 376static struct irq_chip ixp2000_GPIO_irq_chip = {
377 .ack = ixp2000_GPIO_irq_mask_ack, 377 .ack = ixp2000_GPIO_irq_mask_ack,
378 .mask = ixp2000_GPIO_irq_mask, 378 .mask = ixp2000_GPIO_irq_mask,
379 .unmask = ixp2000_GPIO_irq_unmask, 379 .unmask = ixp2000_GPIO_irq_unmask,
@@ -401,7 +401,7 @@ static void ixp2000_pci_irq_unmask(unsigned int irq)
401/* 401/*
402 * Error interrupts. These are used extensively by the microengine drivers 402 * Error interrupts. These are used extensively by the microengine drivers
403 */ 403 */
404static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc) 404static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
405{ 405{
406 int i; 406 int i;
407 unsigned long status = *IXP2000_IRQ_ERR_STATUS; 407 unsigned long status = *IXP2000_IRQ_ERR_STATUS;
@@ -426,13 +426,13 @@ static void ixp2000_err_irq_unmask(unsigned int irq)
426 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))); 426 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
427} 427}
428 428
429static struct irqchip ixp2000_err_irq_chip = { 429static struct irq_chip ixp2000_err_irq_chip = {
430 .ack = ixp2000_err_irq_mask, 430 .ack = ixp2000_err_irq_mask,
431 .mask = ixp2000_err_irq_mask, 431 .mask = ixp2000_err_irq_mask,
432 .unmask = ixp2000_err_irq_unmask 432 .unmask = ixp2000_err_irq_unmask
433}; 433};
434 434
435static struct irqchip ixp2000_pci_irq_chip = { 435static struct irq_chip ixp2000_pci_irq_chip = {
436 .ack = ixp2000_pci_irq_mask, 436 .ack = ixp2000_pci_irq_mask,
437 .mask = ixp2000_pci_irq_mask, 437 .mask = ixp2000_pci_irq_mask,
438 .unmask = ixp2000_pci_irq_unmask 438 .unmask = ixp2000_pci_irq_unmask
@@ -448,7 +448,7 @@ static void ixp2000_irq_unmask(unsigned int irq)
448 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq)); 448 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
449} 449}
450 450
451static struct irqchip ixp2000_irq_chip = { 451static struct irq_chip ixp2000_irq_chip = {
452 .ack = ixp2000_irq_mask, 452 .ack = ixp2000_irq_mask,
453 .mask = ixp2000_irq_mask, 453 .mask = ixp2000_irq_mask,
454 .unmask = ixp2000_irq_unmask 454 .unmask = ixp2000_irq_unmask
@@ -484,7 +484,7 @@ void __init ixp2000_init_irq(void)
484 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { 484 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
485 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { 485 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
486 set_irq_chip(irq, &ixp2000_irq_chip); 486 set_irq_chip(irq, &ixp2000_irq_chip);
487 set_irq_handler(irq, do_level_IRQ); 487 set_irq_handler(irq, handle_level_irq);
488 set_irq_flags(irq, IRQF_VALID); 488 set_irq_flags(irq, IRQF_VALID);
489 } else set_irq_flags(irq, 0); 489 } else set_irq_flags(irq, 0);
490 } 490 }
@@ -493,7 +493,7 @@ void __init ixp2000_init_irq(void)
493 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & 493 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
494 IXP2000_VALID_ERR_IRQ_MASK) { 494 IXP2000_VALID_ERR_IRQ_MASK) {
495 set_irq_chip(irq, &ixp2000_err_irq_chip); 495 set_irq_chip(irq, &ixp2000_err_irq_chip);
496 set_irq_handler(irq, do_level_IRQ); 496 set_irq_handler(irq, handle_level_irq);
497 set_irq_flags(irq, IRQF_VALID); 497 set_irq_flags(irq, IRQF_VALID);
498 } 498 }
499 else 499 else
@@ -503,7 +503,7 @@ void __init ixp2000_init_irq(void)
503 503
504 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { 504 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
505 set_irq_chip(irq, &ixp2000_GPIO_irq_chip); 505 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
506 set_irq_handler(irq, do_level_IRQ); 506 set_irq_handler(irq, handle_level_irq);
507 set_irq_flags(irq, IRQF_VALID); 507 set_irq_flags(irq, IRQF_VALID);
508 } 508 }
509 set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); 509 set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
@@ -516,7 +516,7 @@ void __init ixp2000_init_irq(void)
516 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); 516 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
517 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { 517 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
518 set_irq_chip(irq, &ixp2000_pci_irq_chip); 518 set_irq_chip(irq, &ixp2000_pci_irq_chip);
519 set_irq_handler(irq, do_level_IRQ); 519 set_irq_handler(irq, handle_level_irq);
520 set_irq_flags(irq, IRQF_VALID); 520 set_irq_flags(irq, IRQF_VALID);
521 } 521 }
522} 522}
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index aa2655092d2d..52b368b34346 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -106,7 +106,7 @@ static void ixdp2x00_irq_unmask(unsigned int irq)
106 ixp2000_release_slowport(&old_cfg); 106 ixp2000_release_slowport(&old_cfg);
107} 107}
108 108
109static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc) 109static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
110{ 110{
111 volatile u32 ex_interrupt = 0; 111 volatile u32 ex_interrupt = 0;
112 static struct slowport_cfg old_cfg; 112 static struct slowport_cfg old_cfg;
@@ -129,7 +129,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
129 129
130 for(i = 0; i < board_irq_count; i++) { 130 for(i = 0; i < board_irq_count; i++) {
131 if(ex_interrupt & (1 << i)) { 131 if(ex_interrupt & (1 << i)) {
132 struct irqdesc *cpld_desc; 132 struct irq_desc *cpld_desc;
133 int cpld_irq = IXP2000_BOARD_IRQ(0) + i; 133 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
134 cpld_desc = irq_desc + cpld_irq; 134 cpld_desc = irq_desc + cpld_irq;
135 desc_handle_irq(cpld_irq, cpld_desc); 135 desc_handle_irq(cpld_irq, cpld_desc);
@@ -139,7 +139,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
139 desc->chip->unmask(irq); 139 desc->chip->unmask(irq);
140} 140}
141 141
142static struct irqchip ixdp2x00_cpld_irq_chip = { 142static struct irq_chip ixdp2x00_cpld_irq_chip = {
143 .ack = ixdp2x00_irq_mask, 143 .ack = ixdp2x00_irq_mask,
144 .mask = ixdp2x00_irq_mask, 144 .mask = ixdp2x00_irq_mask,
145 .unmask = ixdp2x00_irq_unmask 145 .unmask = ixdp2x00_irq_unmask
@@ -162,7 +162,7 @@ void ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long
162 162
163 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { 163 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
164 set_irq_chip(irq, &ixdp2x00_cpld_irq_chip); 164 set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
165 set_irq_handler(irq, do_level_IRQ); 165 set_irq_handler(irq, handle_level_irq);
166 set_irq_flags(irq, IRQF_VALID); 166 set_irq_flags(irq, IRQF_VALID);
167 } 167 }
168 168
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 9ccae9e63f70..3084a5fa751c 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -63,7 +63,7 @@ static void ixdp2x01_irq_unmask(unsigned int irq)
63 63
64static u32 valid_irq_mask; 64static u32 valid_irq_mask;
65 65
66static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc) 66static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
67{ 67{
68 u32 ex_interrupt; 68 u32 ex_interrupt;
69 int i; 69 int i;
@@ -79,7 +79,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
79 79
80 for (i = 0; i < IXP2000_BOARD_IRQS; i++) { 80 for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
81 if (ex_interrupt & (1 << i)) { 81 if (ex_interrupt & (1 << i)) {
82 struct irqdesc *cpld_desc; 82 struct irq_desc *cpld_desc;
83 int cpld_irq = IXP2000_BOARD_IRQ(0) + i; 83 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
84 cpld_desc = irq_desc + cpld_irq; 84 cpld_desc = irq_desc + cpld_irq;
85 desc_handle_irq(cpld_irq, cpld_desc); 85 desc_handle_irq(cpld_irq, cpld_desc);
@@ -89,7 +89,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
89 desc->chip->unmask(irq); 89 desc->chip->unmask(irq);
90} 90}
91 91
92static struct irqchip ixdp2x01_irq_chip = { 92static struct irq_chip ixdp2x01_irq_chip = {
93 .mask = ixdp2x01_irq_mask, 93 .mask = ixdp2x01_irq_mask,
94 .ack = ixdp2x01_irq_mask, 94 .ack = ixdp2x01_irq_mask,
95 .unmask = ixdp2x01_irq_unmask 95 .unmask = ixdp2x01_irq_unmask
@@ -119,7 +119,7 @@ void __init ixdp2x01_init_irq(void)
119 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { 119 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
120 if (irq & valid_irq_mask) { 120 if (irq & valid_irq_mask) {
121 set_irq_chip(irq, &ixdp2x01_irq_chip); 121 set_irq_chip(irq, &ixdp2x01_irq_chip);
122 set_irq_handler(irq, do_level_IRQ); 122 set_irq_handler(irq, handle_level_irq);
123 set_irq_flags(irq, IRQF_VALID); 123 set_irq_flags(irq, IRQF_VALID);
124 } else { 124 } else {
125 set_irq_flags(irq, 0); 125 set_irq_flags(irq, 0);
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index d4bf1e1c0031..5a09a90c08fb 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -32,7 +32,7 @@
32 32
33#include <asm/mach/pci.h> 33#include <asm/mach/pci.h>
34 34
35static int pci_master_aborts = 0; 35static volatile int pci_master_aborts = 0;
36 36
37static int clear_master_aborts(void); 37static int clear_master_aborts(void);
38 38
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index a704a1820048..ce6ad635a00c 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -224,14 +224,14 @@ static void ixp23xx_irq_edge_unmask(unsigned int irq)
224 *intr_reg |= (1 << (irq % 32)); 224 *intr_reg |= (1 << (irq % 32));
225} 225}
226 226
227static struct irqchip ixp23xx_irq_level_chip = { 227static struct irq_chip ixp23xx_irq_level_chip = {
228 .ack = ixp23xx_irq_mask, 228 .ack = ixp23xx_irq_mask,
229 .mask = ixp23xx_irq_mask, 229 .mask = ixp23xx_irq_mask,
230 .unmask = ixp23xx_irq_level_unmask, 230 .unmask = ixp23xx_irq_level_unmask,
231 .set_type = ixp23xx_irq_set_type 231 .set_type = ixp23xx_irq_set_type
232}; 232};
233 233
234static struct irqchip ixp23xx_irq_edge_chip = { 234static struct irq_chip ixp23xx_irq_edge_chip = {
235 .ack = ixp23xx_irq_ack, 235 .ack = ixp23xx_irq_ack,
236 .mask = ixp23xx_irq_mask, 236 .mask = ixp23xx_irq_mask,
237 .unmask = ixp23xx_irq_edge_unmask, 237 .unmask = ixp23xx_irq_edge_unmask,
@@ -251,11 +251,11 @@ static void ixp23xx_pci_irq_unmask(unsigned int irq)
251/* 251/*
252 * TODO: Should this just be done at ASM level? 252 * TODO: Should this just be done at ASM level?
253 */ 253 */
254static void pci_handler(unsigned int irq, struct irqdesc *desc) 254static void pci_handler(unsigned int irq, struct irq_desc *desc)
255{ 255{
256 u32 pci_interrupt; 256 u32 pci_interrupt;
257 unsigned int irqno; 257 unsigned int irqno;
258 struct irqdesc *int_desc; 258 struct irq_desc *int_desc;
259 259
260 pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS; 260 pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
261 261
@@ -276,7 +276,7 @@ static void pci_handler(unsigned int irq, struct irqdesc *desc)
276 desc->chip->unmask(irq); 276 desc->chip->unmask(irq);
277} 277}
278 278
279static struct irqchip ixp23xx_pci_irq_chip = { 279static struct irq_chip ixp23xx_pci_irq_chip = {
280 .ack = ixp23xx_pci_irq_mask, 280 .ack = ixp23xx_pci_irq_mask,
281 .mask = ixp23xx_pci_irq_mask, 281 .mask = ixp23xx_pci_irq_mask,
282 .unmask = ixp23xx_pci_irq_unmask 282 .unmask = ixp23xx_pci_irq_unmask
@@ -287,11 +287,11 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
287 switch (type) { 287 switch (type) {
288 case IXP23XX_IRQ_LEVEL: 288 case IXP23XX_IRQ_LEVEL:
289 set_irq_chip(irq, &ixp23xx_irq_level_chip); 289 set_irq_chip(irq, &ixp23xx_irq_level_chip);
290 set_irq_handler(irq, do_level_IRQ); 290 set_irq_handler(irq, handle_level_irq);
291 break; 291 break;
292 case IXP23XX_IRQ_EDGE: 292 case IXP23XX_IRQ_EDGE:
293 set_irq_chip(irq, &ixp23xx_irq_edge_chip); 293 set_irq_chip(irq, &ixp23xx_irq_edge_chip);
294 set_irq_handler(irq, do_edge_IRQ); 294 set_irq_handler(irq, handle_edge_irq);
295 break; 295 break;
296 } 296 }
297 set_irq_flags(irq, IRQF_VALID); 297 set_irq_flags(irq, IRQF_VALID);
@@ -322,7 +322,7 @@ void __init ixp23xx_init_irq(void)
322 322
323 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { 323 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
324 set_irq_chip(irq, &ixp23xx_pci_irq_chip); 324 set_irq_chip(irq, &ixp23xx_pci_irq_chip);
325 set_irq_handler(irq, do_level_IRQ); 325 set_irq_handler(irq, handle_level_irq);
326 set_irq_flags(irq, IRQF_VALID); 326 set_irq_flags(irq, IRQF_VALID);
327 } 327 }
328 328
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index b6ab0e8bb5e8..7a86a2516eaa 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -60,7 +60,7 @@ static void ixdp2351_inta_unmask(unsigned int irq)
60 *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq); 60 *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
61} 61}
62 62
63static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc) 63static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
64{ 64{
65 u16 ex_interrupt = 65 u16 ex_interrupt =
66 *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID; 66 *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
@@ -70,7 +70,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
70 70
71 for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) { 71 for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
72 if (ex_interrupt & (1 << i)) { 72 if (ex_interrupt & (1 << i)) {
73 struct irqdesc *cpld_desc; 73 struct irq_desc *cpld_desc;
74 int cpld_irq = 74 int cpld_irq =
75 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i); 75 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
76 cpld_desc = irq_desc + cpld_irq; 76 cpld_desc = irq_desc + cpld_irq;
@@ -81,7 +81,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
81 desc->chip->unmask(irq); 81 desc->chip->unmask(irq);
82} 82}
83 83
84static struct irqchip ixdp2351_inta_chip = { 84static struct irq_chip ixdp2351_inta_chip = {
85 .ack = ixdp2351_inta_mask, 85 .ack = ixdp2351_inta_mask,
86 .mask = ixdp2351_inta_mask, 86 .mask = ixdp2351_inta_mask,
87 .unmask = ixdp2351_inta_unmask 87 .unmask = ixdp2351_inta_unmask
@@ -97,7 +97,7 @@ static void ixdp2351_intb_unmask(unsigned int irq)
97 *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq); 97 *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
98} 98}
99 99
100static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc) 100static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
101{ 101{
102 u16 ex_interrupt = 102 u16 ex_interrupt =
103 *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID; 103 *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
@@ -107,7 +107,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
107 107
108 for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) { 108 for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
109 if (ex_interrupt & (1 << i)) { 109 if (ex_interrupt & (1 << i)) {
110 struct irqdesc *cpld_desc; 110 struct irq_desc *cpld_desc;
111 int cpld_irq = 111 int cpld_irq =
112 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i); 112 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
113 cpld_desc = irq_desc + cpld_irq; 113 cpld_desc = irq_desc + cpld_irq;
@@ -118,7 +118,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
118 desc->chip->unmask(irq); 118 desc->chip->unmask(irq);
119} 119}
120 120
121static struct irqchip ixdp2351_intb_chip = { 121static struct irq_chip ixdp2351_intb_chip = {
122 .ack = ixdp2351_intb_mask, 122 .ack = ixdp2351_intb_mask,
123 .mask = ixdp2351_intb_mask, 123 .mask = ixdp2351_intb_mask,
124 .unmask = ixdp2351_intb_unmask 124 .unmask = ixdp2351_intb_unmask
@@ -142,7 +142,7 @@ void ixdp2351_init_irq(void)
142 irq++) { 142 irq++) {
143 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { 143 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
144 set_irq_flags(irq, IRQF_VALID); 144 set_irq_flags(irq, IRQF_VALID);
145 set_irq_handler(irq, do_level_IRQ); 145 set_irq_handler(irq, handle_level_irq);
146 set_irq_chip(irq, &ixdp2351_inta_chip); 146 set_irq_chip(irq, &ixdp2351_inta_chip);
147 } 147 }
148 } 148 }
@@ -153,7 +153,7 @@ void ixdp2351_init_irq(void)
153 irq++) { 153 irq++) {
154 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { 154 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
155 set_irq_flags(irq, IRQF_VALID); 155 set_irq_flags(irq, IRQF_VALID);
156 set_irq_handler(irq, do_level_IRQ); 156 set_irq_handler(irq, handle_level_irq);
157 set_irq_chip(irq, &ixdp2351_intb_chip); 157 set_irq_chip(irq, &ixdp2351_intb_chip);
158 } 158 }
159 } 159 }
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 3b34fa35e36b..ac7d43d23c28 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -36,7 +36,7 @@
36 36
37extern int (*external_fault) (unsigned long, struct pt_regs *); 37extern int (*external_fault) (unsigned long, struct pt_regs *);
38 38
39static int pci_master_aborts = 0; 39static volatile int pci_master_aborts = 0;
40 40
41#ifdef DEBUG 41#ifdef DEBUG
42#define DBG(x...) printk(x) 42#define DBG(x...) printk(x)
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index fbe288a8da65..2ec9a9e9a04d 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -28,6 +28,7 @@
28#include <linux/timex.h> 28#include <linux/timex.h>
29#include <linux/clocksource.h> 29#include <linux/clocksource.h>
30 30
31#include <asm/arch/udc.h>
31#include <asm/hardware.h> 32#include <asm/hardware.h>
32#include <asm/uaccess.h> 33#include <asm/uaccess.h>
33#include <asm/io.h> 34#include <asm/io.h>
@@ -39,6 +40,8 @@
39#include <asm/mach/irq.h> 40#include <asm/mach/irq.h>
40#include <asm/mach/time.h> 41#include <asm/mach/time.h>
41 42
43static int __init ixp4xx_clocksource_init(void);
44
42/************************************************************************* 45/*************************************************************************
43 * IXP4xx chipset I/O mapping 46 * IXP4xx chipset I/O mapping
44 *************************************************************************/ 47 *************************************************************************/
@@ -195,7 +198,7 @@ static void ixp4xx_irq_unmask(unsigned int irq)
195 *IXP4XX_ICMR |= (1 << irq); 198 *IXP4XX_ICMR |= (1 << irq);
196} 199}
197 200
198static struct irqchip ixp4xx_irq_chip = { 201static struct irq_chip ixp4xx_irq_chip = {
199 .name = "IXP4xx", 202 .name = "IXP4xx",
200 .ack = ixp4xx_irq_ack, 203 .ack = ixp4xx_irq_ack,
201 .mask = ixp4xx_irq_mask, 204 .mask = ixp4xx_irq_mask,
@@ -224,7 +227,7 @@ void __init ixp4xx_init_irq(void)
224 /* Default to all level triggered */ 227 /* Default to all level triggered */
225 for(i = 0; i < NR_IRQS; i++) { 228 for(i = 0; i < NR_IRQS; i++) {
226 set_irq_chip(i, &ixp4xx_irq_chip); 229 set_irq_chip(i, &ixp4xx_irq_chip);
227 set_irq_handler(i, do_level_IRQ); 230 set_irq_handler(i, handle_level_irq);
228 set_irq_flags(i, IRQF_VALID); 231 set_irq_flags(i, IRQF_VALID);
229 } 232 }
230} 233}
@@ -280,12 +283,52 @@ static void __init ixp4xx_timer_init(void)
280 283
281 /* Connect the interrupt handler and enable the interrupt */ 284 /* Connect the interrupt handler and enable the interrupt */
282 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq); 285 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
286
287 ixp4xx_clocksource_init();
283} 288}
284 289
285struct sys_timer ixp4xx_timer = { 290struct sys_timer ixp4xx_timer = {
286 .init = ixp4xx_timer_init, 291 .init = ixp4xx_timer_init,
287}; 292};
288 293
294static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
295
296void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
297{
298 memcpy(&ixp4xx_udc_info, info, sizeof *info);
299}
300
301static struct resource ixp4xx_udc_resources[] = {
302 [0] = {
303 .start = 0xc800b000,
304 .end = 0xc800bfff,
305 .flags = IORESOURCE_MEM,
306 },
307 [1] = {
308 .start = IRQ_IXP4XX_USB,
309 .end = IRQ_IXP4XX_USB,
310 .flags = IORESOURCE_IRQ,
311 },
312};
313
314/*
315 * USB device controller. The IXP4xx uses the same controller as PXA2XX,
316 * so we just use the same device.
317 */
318static struct platform_device ixp4xx_udc_device = {
319 .name = "pxa2xx-udc",
320 .id = -1,
321 .num_resources = 2,
322 .resource = ixp4xx_udc_resources,
323 .dev = {
324 .platform_data = &ixp4xx_udc_info,
325 },
326};
327
328static struct platform_device *ixp4xx_devices[] __initdata = {
329 &ixp4xx_udc_device,
330};
331
289static struct resource ixp46x_i2c_resources[] = { 332static struct resource ixp46x_i2c_resources[] = {
290 [0] = { 333 [0] = {
291 .start = 0xc8011000, 334 .start = 0xc8011000,
@@ -321,6 +364,8 @@ void __init ixp4xx_sys_init(void)
321{ 364{
322 ixp4xx_exp_bus_size = SZ_16M; 365 ixp4xx_exp_bus_size = SZ_16M;
323 366
367 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
368
324 if (cpu_is_ixp46x()) { 369 if (cpu_is_ixp46x()) {
325 int region; 370 int region;
326 371
@@ -363,5 +408,3 @@ static int __init ixp4xx_clocksource_init(void)
363 408
364 return 0; 409 return 0;
365} 410}
366
367device_initcall(ixp4xx_clocksource_init);
diff --git a/arch/arm/mach-l7200/core.c b/arch/arm/mach-l7200/core.c
index b7af5640ea7b..561a0fe7095d 100644
--- a/arch/arm/mach-l7200/core.c
+++ b/arch/arm/mach-l7200/core.c
@@ -55,7 +55,7 @@ static void l7200_unmask_irq(unsigned int irq)
55 IRQ_ENABLE = 1 << irq; 55 IRQ_ENABLE = 1 << irq;
56} 56}
57 57
58static struct irqchip l7200_irq_chip = { 58static struct irq_chip l7200_irq_chip = {
59 .ack = l7200_mask_irq, 59 .ack = l7200_mask_irq,
60 .mask = l7200_mask_irq, 60 .mask = l7200_mask_irq,
61 .unmask = l7200_unmask_irq 61 .unmask = l7200_unmask_irq
@@ -71,7 +71,7 @@ static void __init l7200_init_irq(void)
71 for (irq = 0; irq < NR_IRQS; irq++) { 71 for (irq = 0; irq < NR_IRQS; irq++) {
72 set_irq_chip(irq, &l7200_irq_chip); 72 set_irq_chip(irq, &l7200_irq_chip);
73 set_irq_flags(irq, IRQF_VALID); 73 set_irq_flags(irq, IRQF_VALID);
74 set_irq_handler(irq, do_level_IRQ); 74 set_irq_handler(irq, handle_level_irq);
75 } 75 }
76 76
77 init_FIQ(); 77 init_FIQ();
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c
index 15fbcc911fe7..6d26661d99f6 100644
--- a/arch/arm/mach-lh7a40x/arch-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c
@@ -71,7 +71,7 @@ static struct irq_chip kev7a400_cpld_chip = {
71}; 71};
72 72
73 73
74static void kev7a400_cpld_handler (unsigned int irq, struct irqdesc *desc) 74static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
75{ 75{
76 u32 mask = CPLD_LATCHED_INTS; 76 u32 mask = CPLD_LATCHED_INTS;
77 irq = IRQ_KEV7A400_CPLD; 77 irq = IRQ_KEV7A400_CPLD;
@@ -88,7 +88,7 @@ void __init lh7a40x_init_board_irq (void)
88 for (irq = IRQ_KEV7A400_CPLD; 88 for (irq = IRQ_KEV7A400_CPLD;
89 irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) { 89 irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) {
90 set_irq_chip (irq, &kev7a400_cpld_chip); 90 set_irq_chip (irq, &kev7a400_cpld_chip);
91 set_irq_handler (irq, do_edge_IRQ); 91 set_irq_handler (irq, handle_edge_irq);
92 set_irq_flags (irq, IRQF_VALID); 92 set_irq_flags (irq, IRQF_VALID);
93 } 93 }
94 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler); 94 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
index 8441e0a156cb..fe64946f9e18 100644
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
@@ -207,7 +207,7 @@ static struct irq_chip lpd7a40x_cpld_chip = {
207 .unmask = lh7a40x_unmask_cpld_irq, 207 .unmask = lh7a40x_unmask_cpld_irq,
208}; 208};
209 209
210static void lpd7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc) 210static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
211{ 211{
212 unsigned int mask = CPLD_INTERRUPTS; 212 unsigned int mask = CPLD_INTERRUPTS;
213 213
@@ -279,7 +279,7 @@ void __init lh7a40x_init_board_irq (void)
279 for (irq = IRQ_BOARD_START; 279 for (irq = IRQ_BOARD_START;
280 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { 280 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
281 set_irq_chip (irq, &lpd7a40x_cpld_chip); 281 set_irq_chip (irq, &lpd7a40x_cpld_chip);
282 set_irq_handler (irq, do_level_IRQ); 282 set_irq_handler (irq, handle_level_irq);
283 set_irq_flags (irq, IRQF_VALID); 283 set_irq_flags (irq, IRQF_VALID);
284 } 284 }
285 285
diff --git a/arch/arm/mach-lh7a40x/irq-kev7a400.c b/arch/arm/mach-lh7a40x/irq-kev7a400.c
index 646071334b8f..c7433b3c5812 100644
--- a/arch/arm/mach-lh7a40x/irq-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/irq-kev7a400.c
@@ -51,7 +51,7 @@ irq_chip lh7a400_cpld_chip = {
51}; 51};
52 52
53static void 53static void
54lh7a400_cpld_handler (unsigned int irq, struct irqdesc *desc) 54lh7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
55{ 55{
56 u32 mask = CPLD_LATCHED_INTS; 56 u32 mask = CPLD_LATCHED_INTS;
57 irq = IRQ_KEV_7A400_CPLD; 57 irq = IRQ_KEV_7A400_CPLD;
@@ -71,7 +71,7 @@ lh7a400_init_board_irq (void)
71 for (irq = IRQ_KEV7A400_CPLD; 71 for (irq = IRQ_KEV7A400_CPLD;
72 irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) { 72 irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) {
73 set_irq_chip (irq, &lh7a400_cpld_chip); 73 set_irq_chip (irq, &lh7a400_cpld_chip);
74 set_irq_handler (irq, do_edge_IRQ); 74 set_irq_handler (irq, handle_edge_irq);
75 set_irq_flags (irq, IRQF_VALID); 75 set_irq_flags (irq, IRQF_VALID);
76 } 76 }
77 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler); 77 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c
index 091b2dc58d25..0b938e8b4d98 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a400.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c
@@ -74,11 +74,11 @@ void __init lh7a400_init_irq (void)
74 case IRQ_GPIO6INTR: 74 case IRQ_GPIO6INTR:
75 case IRQ_GPIO7INTR: 75 case IRQ_GPIO7INTR:
76 set_irq_chip (irq, &lh7a400_gpio_chip); 76 set_irq_chip (irq, &lh7a400_gpio_chip);
77 set_irq_handler (irq, do_level_IRQ); /* OK default */ 77 set_irq_handler (irq, handle_level_irq); /* OK default */
78 break; 78 break;
79 default: 79 default:
80 set_irq_chip (irq, &lh7a400_internal_chip); 80 set_irq_chip (irq, &lh7a400_internal_chip);
81 set_irq_handler (irq, do_level_IRQ); 81 set_irq_handler (irq, handle_level_irq);
82 } 82 }
83 set_irq_flags (irq, IRQF_VALID); 83 set_irq_flags (irq, IRQF_VALID);
84 } 84 }
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c
index 7059b983724f..5760f8c53e89 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a404.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c
@@ -161,13 +161,13 @@ void __init lh7a404_init_irq (void)
161 set_irq_chip (irq, irq < 32 161 set_irq_chip (irq, irq < 32
162 ? &lh7a404_gpio_vic1_chip 162 ? &lh7a404_gpio_vic1_chip
163 : &lh7a404_gpio_vic2_chip); 163 : &lh7a404_gpio_vic2_chip);
164 set_irq_handler (irq, do_level_IRQ); /* OK default */ 164 set_irq_handler (irq, handle_level_irq); /* OK default */
165 break; 165 break;
166 default: 166 default:
167 set_irq_chip (irq, irq < 32 167 set_irq_chip (irq, irq < 32
168 ? &lh7a404_vic1_chip 168 ? &lh7a404_vic1_chip
169 : &lh7a404_vic2_chip); 169 : &lh7a404_vic2_chip);
170 set_irq_handler (irq, do_level_IRQ); 170 set_irq_handler (irq, handle_level_irq);
171 } 171 }
172 set_irq_flags (irq, IRQF_VALID); 172 set_irq_flags (irq, IRQF_VALID);
173 } 173 }
diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
index b20376804bbb..15b9577023c9 100644
--- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
@@ -57,7 +57,7 @@ static struct irq_chip lh7a40x_cpld_chip = {
57 .unmask = lh7a40x_unmask_cpld_irq, 57 .unmask = lh7a40x_unmask_cpld_irq,
58}; 58};
59 59
60static void lh7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc) 60static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
61{ 61{
62 unsigned int mask = CPLD_INTERRUPTS; 62 unsigned int mask = CPLD_INTERRUPTS;
63 63
@@ -118,7 +118,7 @@ void __init lh7a40x_init_board_irq (void)
118 for (irq = IRQ_BOARD_START; 118 for (irq = IRQ_BOARD_START;
119 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { 119 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
120 set_irq_chip (irq, &lh7a40x_cpld_chip); 120 set_irq_chip (irq, &lh7a40x_cpld_chip);
121 set_irq_handler (irq, do_edge_IRQ); 121 set_irq_handler (irq, handle_edge_irq);
122 set_irq_flags (irq, IRQF_VALID); 122 set_irq_flags (irq, IRQF_VALID);
123 } 123 }
124 124
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index edbbbdc3b06b..b9ca8f98265d 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -69,7 +69,7 @@ static struct platform_device *devices[] __initdata = {
69#endif 69#endif
70 70
71static void 71static void
72netx_hif_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 72netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
73{ 73{
74 unsigned int irq = NETX_IRQ_HIF_CHAINED(0); 74 unsigned int irq = NETX_IRQ_HIF_CHAINED(0);
75 unsigned int stat; 75 unsigned int stat;
@@ -160,7 +160,7 @@ netx_hif_unmask_irq(unsigned int _irq)
160 DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq); 160 DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq);
161} 161}
162 162
163static struct irqchip netx_hif_chip = { 163static struct irq_chip netx_hif_chip = {
164 .ack = netx_hif_ack_irq, 164 .ack = netx_hif_ack_irq,
165 .mask = netx_hif_mask_irq, 165 .mask = netx_hif_mask_irq,
166 .unmask = netx_hif_unmask_irq, 166 .unmask = netx_hif_unmask_irq,
@@ -175,7 +175,7 @@ void __init netx_init_irq(void)
175 175
176 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { 176 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
177 set_irq_chip(irq, &netx_hif_chip); 177 set_irq_chip(irq, &netx_hif_chip);
178 set_irq_handler(irq, do_level_IRQ); 178 set_irq_handler(irq, handle_level_irq);
179 set_irq_flags(irq, IRQF_VALID); 179 set_irq_flags(irq, IRQF_VALID);
180 } 180 }
181 181
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 8e40208b10bb..30e188109046 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -84,9 +84,9 @@ static void fpga_mask_ack_irq(unsigned int irq)
84 fpga_ack_irq(irq); 84 fpga_ack_irq(irq);
85} 85}
86 86
87void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc) 87void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
88{ 88{
89 struct irqdesc *d; 89 struct irq_desc *d;
90 u32 stat; 90 u32 stat;
91 int fpga_irq; 91 int fpga_irq;
92 92
@@ -168,7 +168,7 @@ void omap1510_fpga_init_irq(void)
168 set_irq_chip(i, &omap_fpga_irq); 168 set_irq_chip(i, &omap_fpga_irq);
169 } 169 }
170 170
171 set_irq_handler(i, do_edge_IRQ); 171 set_irq_handler(i, handle_edge_irq);
172 set_irq_flags(i, IRQF_VALID); 172 set_irq_flags(i, IRQF_VALID);
173 } 173 }
174 174
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 3ea140bb9eba..6383a12ad970 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -229,7 +229,7 @@ void __init omap_init_irq(void)
229 omap_irq_set_cfg(j, 0, 0, irq_trigger); 229 omap_irq_set_cfg(j, 0, 0, irq_trigger);
230 230
231 set_irq_chip(j, &omap_irq_chip); 231 set_irq_chip(j, &omap_irq_chip);
232 set_irq_handler(j, do_level_IRQ); 232 set_irq_handler(j, handle_level_irq);
233 set_irq_flags(j, IRQF_VALID); 233 set_irq_flags(j, IRQF_VALID);
234 } 234 }
235 } 235 }
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 11870093d7a1..a39d30680300 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -130,7 +130,7 @@ void __init omap_init_irq(void)
130 130
131 for (i = 0; i < nr_irqs; i++) { 131 for (i = 0; i < nr_irqs; i++) {
132 set_irq_chip(i, &omap_irq_chip); 132 set_irq_chip(i, &omap_irq_chip);
133 set_irq_handler(i, do_level_IRQ); 133 set_irq_handler(i, handle_level_irq);
134 set_irq_flags(i, IRQF_VALID); 134 set_irq_flags(i, IRQF_VALID);
135 } 135 }
136} 136}
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 3a4bcf3d91fa..968d0b027597 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -59,22 +59,22 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
59 case IRQT_RISING: 59 case IRQT_RISING:
60 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ 60 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
61 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */ 61 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
62 set_irq_handler(irq, do_edge_IRQ); 62 set_irq_handler(irq, handle_edge_irq);
63 break; 63 break;
64 case IRQT_FALLING: 64 case IRQT_FALLING:
65 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ 65 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
66 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */ 66 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
67 set_irq_handler(irq, do_edge_IRQ); 67 set_irq_handler(irq, handle_edge_irq);
68 break; 68 break;
69 case IRQT_LOW: 69 case IRQT_LOW:
70 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ 70 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
71 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */ 71 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
72 set_irq_handler(irq, do_level_IRQ); 72 set_irq_handler(irq, handle_level_irq);
73 break; 73 break;
74 case IRQT_HIGH: 74 case IRQT_HIGH:
75 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ 75 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
76 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */ 76 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
77 set_irq_handler(irq, do_level_IRQ); 77 set_irq_handler(irq, handle_level_irq);
78 break; 78 break;
79 79
80 /* IRQT_BOTHEDGE is not supported */ 80 /* IRQT_BOTHEDGE is not supported */
@@ -85,7 +85,7 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
85 return 0; 85 return 0;
86} 86}
87 87
88static struct irqchip pnx4008_irq_chip = { 88static struct irq_chip pnx4008_irq_chip = {
89 .ack = pnx4008_mask_ack_irq, 89 .ack = pnx4008_mask_ack_irq,
90 .mask = pnx4008_mask_irq, 90 .mask = pnx4008_mask_irq,
91 .unmask = pnx4008_unmask_irq, 91 .unmask = pnx4008_unmask_irq,
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 03d07cae26c8..9e3d0bdcba07 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -13,12 +13,10 @@ config ARCH_LUBBOCK
13config MACH_LOGICPD_PXA270 13config MACH_LOGICPD_PXA270
14 bool "LogicPD PXA270 Card Engine Development Platform" 14 bool "LogicPD PXA270 Card Engine Development Platform"
15 select PXA27x 15 select PXA27x
16 select IWMMXT
17 16
18config MACH_MAINSTONE 17config MACH_MAINSTONE
19 bool "Intel HCDDBBVA0 Development Platform" 18 bool "Intel HCDDBBVA0 Development Platform"
20 select PXA27x 19 select PXA27x
21 select IWMMXT
22 20
23config ARCH_PXA_IDP 21config ARCH_PXA_IDP
24 bool "Accelent Xscale IDP" 22 bool "Accelent Xscale IDP"
@@ -53,7 +51,6 @@ config PXA_SHARPSL_25x
53config PXA_SHARPSL_27x 51config PXA_SHARPSL_27x
54 bool "Sharp PXA270 models (SL-Cxx00)" 52 bool "Sharp PXA270 models (SL-Cxx00)"
55 select PXA27x 53 select PXA27x
56 select IWMMXT
57 54
58endchoice 55endchoice
59 56
@@ -129,11 +126,6 @@ config PXA27x
129 help 126 help
130 Select code specific to PXA27x variants 127 Select code specific to PXA27x variants
131 128
132config IWMMXT
133 bool
134 help
135 Enable support for iWMMXt
136
137config PXA_SHARP_C7xx 129config PXA_SHARP_C7xx
138 bool 130 bool
139 select PXA_SSP 131 select PXA_SSP
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index ab1a16025d51..f815678a9d63 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -143,7 +143,7 @@ static struct irq_chip pxa_low_gpio_chip = {
143 * Demux handler for GPIO>=2 edge detect interrupts 143 * Demux handler for GPIO>=2 edge detect interrupts
144 */ 144 */
145 145
146static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc) 146static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
147{ 147{
148 unsigned int mask; 148 unsigned int mask;
149 int loop; 149 int loop;
@@ -286,27 +286,27 @@ void __init pxa_init_irq(void)
286 286
287 for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) { 287 for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
288 set_irq_chip(irq, &pxa_internal_chip_low); 288 set_irq_chip(irq, &pxa_internal_chip_low);
289 set_irq_handler(irq, do_level_IRQ); 289 set_irq_handler(irq, handle_level_irq);
290 set_irq_flags(irq, IRQF_VALID); 290 set_irq_flags(irq, IRQF_VALID);
291 } 291 }
292 292
293#if PXA_INTERNAL_IRQS > 32 293#if PXA_INTERNAL_IRQS > 32
294 for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) { 294 for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
295 set_irq_chip(irq, &pxa_internal_chip_high); 295 set_irq_chip(irq, &pxa_internal_chip_high);
296 set_irq_handler(irq, do_level_IRQ); 296 set_irq_handler(irq, handle_level_irq);
297 set_irq_flags(irq, IRQF_VALID); 297 set_irq_flags(irq, IRQF_VALID);
298 } 298 }
299#endif 299#endif
300 300
301 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 301 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
302 set_irq_chip(irq, &pxa_low_gpio_chip); 302 set_irq_chip(irq, &pxa_low_gpio_chip);
303 set_irq_handler(irq, do_edge_IRQ); 303 set_irq_handler(irq, handle_edge_irq);
304 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 304 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
305 } 305 }
306 306
307 for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { 307 for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
308 set_irq_chip(irq, &pxa_muxed_gpio_chip); 308 set_irq_chip(irq, &pxa_muxed_gpio_chip);
309 set_irq_handler(irq, do_edge_IRQ); 309 set_irq_handler(irq, handle_edge_irq);
310 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 310 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
311 } 311 }
312 312
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 5749f6b72e12..8e27a64fa9f4 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -75,7 +75,7 @@ static struct irq_chip lpd270_irq_chip = {
75 .unmask = lpd270_unmask_irq, 75 .unmask = lpd270_unmask_irq,
76}; 76};
77 77
78static void lpd270_irq_handler(unsigned int irq, struct irqdesc *desc) 78static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
79{ 79{
80 unsigned long pending; 80 unsigned long pending;
81 81
@@ -105,7 +105,7 @@ static void __init lpd270_init_irq(void)
105 /* setup extra LogicPD PXA270 irqs */ 105 /* setup extra LogicPD PXA270 irqs */
106 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { 106 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
107 set_irq_chip(irq, &lpd270_irq_chip); 107 set_irq_chip(irq, &lpd270_irq_chip);
108 set_irq_handler(irq, do_level_IRQ); 108 set_irq_handler(irq, handle_level_irq);
109 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 109 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
110 } 110 }
111 set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); 111 set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 142c33c3dff5..055de7f4f00a 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -85,7 +85,7 @@ static struct irq_chip lubbock_irq_chip = {
85 .unmask = lubbock_unmask_irq, 85 .unmask = lubbock_unmask_irq,
86}; 86};
87 87
88static void lubbock_irq_handler(unsigned int irq, struct irqdesc *desc) 88static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
89{ 89{
90 unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled; 90 unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
91 do { 91 do {
@@ -108,7 +108,7 @@ static void __init lubbock_init_irq(void)
108 /* setup extra lubbock irqs */ 108 /* setup extra lubbock irqs */
109 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { 109 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
110 set_irq_chip(irq, &lubbock_irq_chip); 110 set_irq_chip(irq, &lubbock_irq_chip);
111 set_irq_handler(irq, do_level_IRQ); 111 set_irq_handler(irq, handle_level_irq);
112 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 112 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
113 } 113 }
114 114
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 49c34d94a9fe..56d94d88d5ca 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -71,7 +71,7 @@ static struct irq_chip mainstone_irq_chip = {
71 .unmask = mainstone_unmask_irq, 71 .unmask = mainstone_unmask_irq,
72}; 72};
73 73
74static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc) 74static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
75{ 75{
76 unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled; 76 unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
77 do { 77 do {
@@ -94,7 +94,7 @@ static void __init mainstone_init_irq(void)
94 /* setup extra Mainstone irqs */ 94 /* setup extra Mainstone irqs */
95 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { 95 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
96 set_irq_chip(irq, &mainstone_irq_chip); 96 set_irq_chip(irq, &mainstone_irq_chip);
97 set_irq_handler(irq, do_level_IRQ); 97 set_irq_handler(irq, handle_level_irq);
98 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) 98 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
99 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); 99 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
100 else 100 else
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 2112c414f0e2..b4d8276d6050 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -83,7 +83,8 @@ int pxa_pm_enter(suspend_state_t state)
83 83
84#ifdef CONFIG_IWMMXT 84#ifdef CONFIG_IWMMXT
85 /* force any iWMMXt context to ram **/ 85 /* force any iWMMXt context to ram **/
86 iwmmxt_task_disable(NULL); 86 if (elf_hwcap & HWCAP_IWMMXT)
87 iwmmxt_task_disable(NULL);
87#endif 88#endif
88 89
89 /* preserve current time */ 90 /* preserve current time */
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 3ac268fa419b..b91466861029 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -124,6 +124,7 @@ static struct irqaction pxa_timer_irq = {
124static void __init pxa_timer_init(void) 124static void __init pxa_timer_init(void)
125{ 125{
126 struct timespec tv; 126 struct timespec tv;
127 unsigned long flags;
127 128
128 set_rtc = pxa_set_rtc; 129 set_rtc = pxa_set_rtc;
129 130
@@ -132,12 +133,12 @@ static void __init pxa_timer_init(void)
132 do_settimeofday(&tv); 133 do_settimeofday(&tv);
133 134
134 OIER = 0; /* disable any timer interrupts */ 135 OIER = 0; /* disable any timer interrupts */
135 OSCR = LATCH*2; /* push OSCR out of the way */
136 OSMR0 = LATCH; /* set initial match */
137 OSSR = 0xf; /* clear status on all timers */ 136 OSSR = 0xf; /* clear status on all timers */
138 setup_irq(IRQ_OST0, &pxa_timer_irq); 137 setup_irq(IRQ_OST0, &pxa_timer_irq);
138 local_irq_save(flags);
139 OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */ 139 OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */
140 OSCR = 0; /* initialize free-running timer */ 140 OSMR0 = OSCR + LATCH; /* set initial match */
141 local_irq_restore(flags);
141} 142}
142 143
143#ifdef CONFIG_NO_IDLE_HZ 144#ifdef CONFIG_NO_IDLE_HZ
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 56b2716f8cf5..7a029621db43 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -34,7 +34,7 @@ static void iomd_unmask_irq_a(unsigned int irq)
34 iomd_writeb(val | mask, IOMD_IRQMASKA); 34 iomd_writeb(val | mask, IOMD_IRQMASKA);
35} 35}
36 36
37static struct irqchip iomd_a_chip = { 37static struct irq_chip iomd_a_chip = {
38 .ack = iomd_ack_irq_a, 38 .ack = iomd_ack_irq_a,
39 .mask = iomd_mask_irq_a, 39 .mask = iomd_mask_irq_a,
40 .unmask = iomd_unmask_irq_a, 40 .unmask = iomd_unmask_irq_a,
@@ -58,7 +58,7 @@ static void iomd_unmask_irq_b(unsigned int irq)
58 iomd_writeb(val | mask, IOMD_IRQMASKB); 58 iomd_writeb(val | mask, IOMD_IRQMASKB);
59} 59}
60 60
61static struct irqchip iomd_b_chip = { 61static struct irq_chip iomd_b_chip = {
62 .ack = iomd_mask_irq_b, 62 .ack = iomd_mask_irq_b,
63 .mask = iomd_mask_irq_b, 63 .mask = iomd_mask_irq_b,
64 .unmask = iomd_unmask_irq_b, 64 .unmask = iomd_unmask_irq_b,
@@ -82,7 +82,7 @@ static void iomd_unmask_irq_dma(unsigned int irq)
82 iomd_writeb(val | mask, IOMD_DMAMASK); 82 iomd_writeb(val | mask, IOMD_DMAMASK);
83} 83}
84 84
85static struct irqchip iomd_dma_chip = { 85static struct irq_chip iomd_dma_chip = {
86 .ack = iomd_mask_irq_dma, 86 .ack = iomd_mask_irq_dma,
87 .mask = iomd_mask_irq_dma, 87 .mask = iomd_mask_irq_dma,
88 .unmask = iomd_unmask_irq_dma, 88 .unmask = iomd_unmask_irq_dma,
@@ -106,7 +106,7 @@ static void iomd_unmask_irq_fiq(unsigned int irq)
106 iomd_writeb(val | mask, IOMD_FIQMASK); 106 iomd_writeb(val | mask, IOMD_FIQMASK);
107} 107}
108 108
109static struct irqchip iomd_fiq_chip = { 109static struct irq_chip iomd_fiq_chip = {
110 .ack = iomd_mask_irq_fiq, 110 .ack = iomd_mask_irq_fiq,
111 .mask = iomd_mask_irq_fiq, 111 .mask = iomd_mask_irq_fiq,
112 .unmask = iomd_unmask_irq_fiq, 112 .unmask = iomd_unmask_irq_fiq,
@@ -134,19 +134,19 @@ void __init rpc_init_irq(void)
134 switch (irq) { 134 switch (irq) {
135 case 0 ... 7: 135 case 0 ... 7:
136 set_irq_chip(irq, &iomd_a_chip); 136 set_irq_chip(irq, &iomd_a_chip);
137 set_irq_handler(irq, do_level_IRQ); 137 set_irq_handler(irq, handle_level_irq);
138 set_irq_flags(irq, flags); 138 set_irq_flags(irq, flags);
139 break; 139 break;
140 140
141 case 8 ... 15: 141 case 8 ... 15:
142 set_irq_chip(irq, &iomd_b_chip); 142 set_irq_chip(irq, &iomd_b_chip);
143 set_irq_handler(irq, do_level_IRQ); 143 set_irq_handler(irq, handle_level_irq);
144 set_irq_flags(irq, flags); 144 set_irq_flags(irq, flags);
145 break; 145 break;
146 146
147 case 16 ... 21: 147 case 16 ... 21:
148 set_irq_chip(irq, &iomd_dma_chip); 148 set_irq_chip(irq, &iomd_dma_chip);
149 set_irq_handler(irq, do_level_IRQ); 149 set_irq_handler(irq, handle_level_irq);
150 set_irq_flags(irq, flags); 150 set_irq_flags(irq, flags);
151 break; 151 break;
152 152
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 63965c78de8c..08b2f300eb79 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -41,9 +41,16 @@ config BAST_PC104_IRQ
41 Say Y here to enable the PC104 IRQ routing on the 41 Say Y here to enable the PC104 IRQ routing on the
42 Simtec BAST (EB2410ITX) 42 Simtec BAST (EB2410ITX)
43 43
44config PM_H1940
45 bool
46 depends on PM
47 help
48 Internal node for H1940 and related PM
49
44config ARCH_H1940 50config ARCH_H1940
45 bool "IPAQ H1940" 51 bool "IPAQ H1940"
46 select CPU_S3C2410 52 select CPU_S3C2410
53 select PM_H1940
47 help 54 help
48 Say Y here if you are using the HP IPAQ H1940 55 Say Y here if you are using the HP IPAQ H1940
49 56
@@ -115,6 +122,7 @@ config MACH_VR1000
115config MACH_RX3715 122config MACH_RX3715
116 bool "HP iPAQ rx3715" 123 bool "HP iPAQ rx3715"
117 select CPU_S3C2440 124 select CPU_S3C2440
125 select PM_H1940
118 help 126 help
119 Say Y here if you are using the HP iPAQ rx3715. 127 Say Y here if you are using the HP iPAQ rx3715.
120 128
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index d66013365b6b..27663e28cc88 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += s3c2410-dma.o
31 31
32obj-$(CONFIG_PM) += pm.o sleep.o 32obj-$(CONFIG_PM) += pm.o sleep.o
33obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o 33obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
34obj-$(CONFIG_PM_H1940) += pm-h1940.o
34 35
35# S3C2412 support 36# S3C2412 support
36obj-$(CONFIG_CPU_S3C2412) += s3c2412.o 37obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 23d5beea5568..379efe70778c 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -88,7 +88,7 @@ bast_pc104_mask(unsigned int irqno)
88static void 88static void
89bast_pc104_maskack(unsigned int irqno) 89bast_pc104_maskack(unsigned int irqno)
90{ 90{
91 struct irqdesc *desc = irq_desc + IRQ_ISA; 91 struct irq_desc *desc = irq_desc + IRQ_ISA;
92 92
93 bast_pc104_mask(irqno); 93 bast_pc104_mask(irqno);
94 desc->chip->ack(IRQ_ISA); 94 desc->chip->ack(IRQ_ISA);
@@ -104,7 +104,7 @@ bast_pc104_unmask(unsigned int irqno)
104 __raw_writeb(temp, BAST_VA_PC104_IRQMASK); 104 __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
105} 105}
106 106
107static struct irqchip bast_pc104_chip = { 107static struct irq_chip bast_pc104_chip = {
108 .mask = bast_pc104_mask, 108 .mask = bast_pc104_mask,
109 .unmask = bast_pc104_unmask, 109 .unmask = bast_pc104_unmask,
110 .ack = bast_pc104_maskack 110 .ack = bast_pc104_maskack
@@ -112,7 +112,7 @@ static struct irqchip bast_pc104_chip = {
112 112
113static void 113static void
114bast_irq_pc104_demux(unsigned int irq, 114bast_irq_pc104_demux(unsigned int irq,
115 struct irqdesc *desc) 115 struct irq_desc *desc)
116{ 116{
117 unsigned int stat; 117 unsigned int stat;
118 unsigned int irqno; 118 unsigned int irqno;
@@ -157,7 +157,7 @@ static __init int bast_irq_init(void)
157 unsigned int irqno = bast_pc104_irqs[i]; 157 unsigned int irqno = bast_pc104_irqs[i];
158 158
159 set_irq_chip(irqno, &bast_pc104_chip); 159 set_irq_chip(irqno, &bast_pc104_chip);
160 set_irq_handler(irqno, do_level_IRQ); 160 set_irq_handler(irqno, handle_level_irq);
161 set_irq_flags(irqno, IRQF_VALID); 161 set_irq_flags(irqno, IRQF_VALID);
162 } 162 }
163 } 163 }
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 683b3491ba3c..3c0ed7871c55 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -180,7 +180,7 @@ s3c_irq_unmask(unsigned int irqno)
180 __raw_writel(mask, S3C2410_INTMSK); 180 __raw_writel(mask, S3C2410_INTMSK);
181} 181}
182 182
183struct irqchip s3c_irq_level_chip = { 183struct irq_chip s3c_irq_level_chip = {
184 .name = "s3c-level", 184 .name = "s3c-level",
185 .ack = s3c_irq_maskack, 185 .ack = s3c_irq_maskack,
186 .mask = s3c_irq_mask, 186 .mask = s3c_irq_mask,
@@ -188,7 +188,7 @@ struct irqchip s3c_irq_level_chip = {
188 .set_wake = s3c_irq_wake 188 .set_wake = s3c_irq_wake
189}; 189};
190 190
191static struct irqchip s3c_irq_chip = { 191static struct irq_chip s3c_irq_chip = {
192 .name = "s3c", 192 .name = "s3c",
193 .ack = s3c_irq_ack, 193 .ack = s3c_irq_ack,
194 .mask = s3c_irq_mask, 194 .mask = s3c_irq_mask,
@@ -206,18 +206,6 @@ s3c_irqext_mask(unsigned int irqno)
206 mask = __raw_readl(S3C24XX_EINTMASK); 206 mask = __raw_readl(S3C24XX_EINTMASK);
207 mask |= ( 1UL << irqno); 207 mask |= ( 1UL << irqno);
208 __raw_writel(mask, S3C24XX_EINTMASK); 208 __raw_writel(mask, S3C24XX_EINTMASK);
209
210 if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
211 /* check to see if all need masking */
212
213 if ((mask & (0xf << 4)) == (0xf << 4)) {
214 /* all masked, mask the parent */
215 s3c_irq_mask(IRQ_EINT4t7);
216 }
217 } else {
218 /* todo: the same check as above for the rest of the irq regs...*/
219
220 }
221} 209}
222 210
223static void 211static void
@@ -229,7 +217,6 @@ s3c_irqext_ack(unsigned int irqno)
229 217
230 bit = 1UL << (irqno - EXTINT_OFF); 218 bit = 1UL << (irqno - EXTINT_OFF);
231 219
232
233 mask = __raw_readl(S3C24XX_EINTMASK); 220 mask = __raw_readl(S3C24XX_EINTMASK);
234 221
235 __raw_writel(bit, S3C24XX_EINTPEND); 222 __raw_writel(bit, S3C24XX_EINTPEND);
@@ -258,8 +245,6 @@ s3c_irqext_unmask(unsigned int irqno)
258 mask = __raw_readl(S3C24XX_EINTMASK); 245 mask = __raw_readl(S3C24XX_EINTMASK);
259 mask &= ~( 1UL << irqno); 246 mask &= ~( 1UL << irqno);
260 __raw_writel(mask, S3C24XX_EINTMASK); 247 __raw_writel(mask, S3C24XX_EINTMASK);
261
262 s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
263} 248}
264 249
265int 250int
@@ -344,7 +329,7 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
344 return 0; 329 return 0;
345} 330}
346 331
347static struct irqchip s3c_irqext_chip = { 332static struct irq_chip s3c_irqext_chip = {
348 .name = "s3c-ext", 333 .name = "s3c-ext",
349 .mask = s3c_irqext_mask, 334 .mask = s3c_irqext_mask,
350 .unmask = s3c_irqext_unmask, 335 .unmask = s3c_irqext_unmask,
@@ -353,7 +338,7 @@ static struct irqchip s3c_irqext_chip = {
353 .set_wake = s3c_irqext_wake 338 .set_wake = s3c_irqext_wake
354}; 339};
355 340
356static struct irqchip s3c_irq_eint0t4 = { 341static struct irq_chip s3c_irq_eint0t4 = {
357 .name = "s3c-ext0", 342 .name = "s3c-ext0",
358 .ack = s3c_irq_ack, 343 .ack = s3c_irq_ack,
359 .mask = s3c_irq_mask, 344 .mask = s3c_irq_mask,
@@ -390,7 +375,7 @@ s3c_irq_uart0_ack(unsigned int irqno)
390 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); 375 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
391} 376}
392 377
393static struct irqchip s3c_irq_uart0 = { 378static struct irq_chip s3c_irq_uart0 = {
394 .name = "s3c-uart0", 379 .name = "s3c-uart0",
395 .mask = s3c_irq_uart0_mask, 380 .mask = s3c_irq_uart0_mask,
396 .unmask = s3c_irq_uart0_unmask, 381 .unmask = s3c_irq_uart0_unmask,
@@ -417,7 +402,7 @@ s3c_irq_uart1_ack(unsigned int irqno)
417 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); 402 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
418} 403}
419 404
420static struct irqchip s3c_irq_uart1 = { 405static struct irq_chip s3c_irq_uart1 = {
421 .name = "s3c-uart1", 406 .name = "s3c-uart1",
422 .mask = s3c_irq_uart1_mask, 407 .mask = s3c_irq_uart1_mask,
423 .unmask = s3c_irq_uart1_unmask, 408 .unmask = s3c_irq_uart1_unmask,
@@ -444,7 +429,7 @@ s3c_irq_uart2_ack(unsigned int irqno)
444 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); 429 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
445} 430}
446 431
447static struct irqchip s3c_irq_uart2 = { 432static struct irq_chip s3c_irq_uart2 = {
448 .name = "s3c-uart2", 433 .name = "s3c-uart2",
449 .mask = s3c_irq_uart2_mask, 434 .mask = s3c_irq_uart2_mask,
450 .unmask = s3c_irq_uart2_unmask, 435 .unmask = s3c_irq_uart2_unmask,
@@ -471,7 +456,7 @@ s3c_irq_adc_ack(unsigned int irqno)
471 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); 456 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
472} 457}
473 458
474static struct irqchip s3c_irq_adc = { 459static struct irq_chip s3c_irq_adc = {
475 .name = "s3c-adc", 460 .name = "s3c-adc",
476 .mask = s3c_irq_adc_mask, 461 .mask = s3c_irq_adc_mask,
477 .unmask = s3c_irq_adc_unmask, 462 .unmask = s3c_irq_adc_unmask,
@@ -480,11 +465,11 @@ static struct irqchip s3c_irq_adc = {
480 465
481/* irq demux for adc */ 466/* irq demux for adc */
482static void s3c_irq_demux_adc(unsigned int irq, 467static void s3c_irq_demux_adc(unsigned int irq,
483 struct irqdesc *desc) 468 struct irq_desc *desc)
484{ 469{
485 unsigned int subsrc, submsk; 470 unsigned int subsrc, submsk;
486 unsigned int offset = 9; 471 unsigned int offset = 9;
487 struct irqdesc *mydesc; 472 struct irq_desc *mydesc;
488 473
489 /* read the current pending interrupts, and the mask 474 /* read the current pending interrupts, and the mask
490 * for what it is available */ 475 * for what it is available */
@@ -512,7 +497,7 @@ static void s3c_irq_demux_uart(unsigned int start)
512{ 497{
513 unsigned int subsrc, submsk; 498 unsigned int subsrc, submsk;
514 unsigned int offset = start - IRQ_S3CUART_RX0; 499 unsigned int offset = start - IRQ_S3CUART_RX0;
515 struct irqdesc *desc; 500 struct irq_desc *desc;
516 501
517 /* read the current pending interrupts, and the mask 502 /* read the current pending interrupts, and the mask
518 * for what it is available */ 503 * for what it is available */
@@ -549,7 +534,7 @@ static void s3c_irq_demux_uart(unsigned int start)
549 534
550static void 535static void
551s3c_irq_demux_uart0(unsigned int irq, 536s3c_irq_demux_uart0(unsigned int irq,
552 struct irqdesc *desc) 537 struct irq_desc *desc)
553{ 538{
554 irq = irq; 539 irq = irq;
555 s3c_irq_demux_uart(IRQ_S3CUART_RX0); 540 s3c_irq_demux_uart(IRQ_S3CUART_RX0);
@@ -557,7 +542,7 @@ s3c_irq_demux_uart0(unsigned int irq,
557 542
558static void 543static void
559s3c_irq_demux_uart1(unsigned int irq, 544s3c_irq_demux_uart1(unsigned int irq,
560 struct irqdesc *desc) 545 struct irq_desc *desc)
561{ 546{
562 irq = irq; 547 irq = irq;
563 s3c_irq_demux_uart(IRQ_S3CUART_RX1); 548 s3c_irq_demux_uart(IRQ_S3CUART_RX1);
@@ -565,7 +550,7 @@ s3c_irq_demux_uart1(unsigned int irq,
565 550
566static void 551static void
567s3c_irq_demux_uart2(unsigned int irq, 552s3c_irq_demux_uart2(unsigned int irq,
568 struct irqdesc *desc) 553 struct irq_desc *desc)
569{ 554{
570 irq = irq; 555 irq = irq;
571 s3c_irq_demux_uart(IRQ_S3CUART_RX2); 556 s3c_irq_demux_uart(IRQ_S3CUART_RX2);
@@ -573,7 +558,7 @@ s3c_irq_demux_uart2(unsigned int irq,
573 558
574static void 559static void
575s3c_irq_demux_extint8(unsigned int irq, 560s3c_irq_demux_extint8(unsigned int irq,
576 struct irqdesc *desc) 561 struct irq_desc *desc)
577{ 562{
578 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 563 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
579 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 564 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -595,7 +580,7 @@ s3c_irq_demux_extint8(unsigned int irq,
595 580
596static void 581static void
597s3c_irq_demux_extint4t7(unsigned int irq, 582s3c_irq_demux_extint4t7(unsigned int irq,
598 struct irqdesc *desc) 583 struct irq_desc *desc)
599{ 584{
600 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 585 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
601 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 586 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -738,7 +723,7 @@ void __init s3c24xx_init_irq(void)
738 case IRQ_UART2: 723 case IRQ_UART2:
739 case IRQ_ADCPARENT: 724 case IRQ_ADCPARENT:
740 set_irq_chip(irqno, &s3c_irq_level_chip); 725 set_irq_chip(irqno, &s3c_irq_level_chip);
741 set_irq_handler(irqno, do_level_IRQ); 726 set_irq_handler(irqno, handle_level_irq);
742 break; 727 break;
743 728
744 case IRQ_RESERVED6: 729 case IRQ_RESERVED6:
@@ -749,7 +734,7 @@ void __init s3c24xx_init_irq(void)
749 default: 734 default:
750 //irqdbf("registering irq %d (s3c irq)\n", irqno); 735 //irqdbf("registering irq %d (s3c irq)\n", irqno);
751 set_irq_chip(irqno, &s3c_irq_chip); 736 set_irq_chip(irqno, &s3c_irq_chip);
752 set_irq_handler(irqno, do_edge_IRQ); 737 set_irq_handler(irqno, handle_edge_irq);
753 set_irq_flags(irqno, IRQF_VALID); 738 set_irq_flags(irqno, IRQF_VALID);
754 } 739 }
755 } 740 }
@@ -769,14 +754,14 @@ void __init s3c24xx_init_irq(void)
769 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 754 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
770 irqdbf("registering irq %d (ext int)\n", irqno); 755 irqdbf("registering irq %d (ext int)\n", irqno);
771 set_irq_chip(irqno, &s3c_irq_eint0t4); 756 set_irq_chip(irqno, &s3c_irq_eint0t4);
772 set_irq_handler(irqno, do_edge_IRQ); 757 set_irq_handler(irqno, handle_edge_irq);
773 set_irq_flags(irqno, IRQF_VALID); 758 set_irq_flags(irqno, IRQF_VALID);
774 } 759 }
775 760
776 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { 761 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
777 irqdbf("registering irq %d (extended s3c irq)\n", irqno); 762 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
778 set_irq_chip(irqno, &s3c_irqext_chip); 763 set_irq_chip(irqno, &s3c_irqext_chip);
779 set_irq_handler(irqno, do_edge_IRQ); 764 set_irq_handler(irqno, handle_edge_irq);
780 set_irq_flags(irqno, IRQF_VALID); 765 set_irq_flags(irqno, IRQF_VALID);
781 } 766 }
782 767
@@ -787,28 +772,28 @@ void __init s3c24xx_init_irq(void)
787 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { 772 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
788 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); 773 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
789 set_irq_chip(irqno, &s3c_irq_uart0); 774 set_irq_chip(irqno, &s3c_irq_uart0);
790 set_irq_handler(irqno, do_level_IRQ); 775 set_irq_handler(irqno, handle_level_irq);
791 set_irq_flags(irqno, IRQF_VALID); 776 set_irq_flags(irqno, IRQF_VALID);
792 } 777 }
793 778
794 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { 779 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
795 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); 780 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
796 set_irq_chip(irqno, &s3c_irq_uart1); 781 set_irq_chip(irqno, &s3c_irq_uart1);
797 set_irq_handler(irqno, do_level_IRQ); 782 set_irq_handler(irqno, handle_level_irq);
798 set_irq_flags(irqno, IRQF_VALID); 783 set_irq_flags(irqno, IRQF_VALID);
799 } 784 }
800 785
801 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { 786 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
802 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); 787 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
803 set_irq_chip(irqno, &s3c_irq_uart2); 788 set_irq_chip(irqno, &s3c_irq_uart2);
804 set_irq_handler(irqno, do_level_IRQ); 789 set_irq_handler(irqno, handle_level_irq);
805 set_irq_flags(irqno, IRQF_VALID); 790 set_irq_flags(irqno, IRQF_VALID);
806 } 791 }
807 792
808 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { 793 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
809 irqdbf("registering irq %d (s3c adc irq)\n", irqno); 794 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
810 set_irq_chip(irqno, &s3c_irq_adc); 795 set_irq_chip(irqno, &s3c_irq_adc);
811 set_irq_handler(irqno, do_edge_IRQ); 796 set_irq_handler(irqno, handle_edge_irq);
812 set_irq_flags(irqno, IRQF_VALID); 797 set_irq_flags(irqno, IRQF_VALID);
813 } 798 }
814 799
diff --git a/arch/arm/mach-s3c2410/irq.h b/arch/arm/mach-s3c2410/irq.h
index 842a9f42c97b..3686a0082245 100644
--- a/arch/arm/mach-s3c2410/irq.h
+++ b/arch/arm/mach-s3c2410/irq.h
@@ -17,7 +17,7 @@
17 17
18#define EXTINT_OFF (IRQ_EINT4 - 4) 18#define EXTINT_OFF (IRQ_EINT4 - 4)
19 19
20extern struct irqchip s3c_irq_level_chip; 20extern struct irq_chip s3c_irq_level_chip;
21 21
22static inline void 22static inline void
23s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, 23s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 8c895c077d22..f5b98099a5d9 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -33,6 +33,7 @@
33#include <asm/arch/regs-serial.h> 33#include <asm/arch/regs-serial.h>
34#include <asm/arch/regs-lcd.h> 34#include <asm/arch/regs-lcd.h>
35 35
36#include <asm/arch/h1940.h>
36#include <asm/arch/h1940-latch.h> 37#include <asm/arch/h1940-latch.h>
37#include <asm/arch/fb.h> 38#include <asm/arch/fb.h>
38 39
@@ -41,6 +42,7 @@
41#include "clock.h" 42#include "clock.h"
42#include "devs.h" 43#include "devs.h"
43#include "cpu.h" 44#include "cpu.h"
45#include "pm.h"
44 46
45static struct map_desc h1940_iodesc[] __initdata = { 47static struct map_desc h1940_iodesc[] __initdata = {
46 [0] = { 48 [0] = {
@@ -164,12 +166,16 @@ static void __init h1940_map_io(void)
164 s3c24xx_init_clocks(0); 166 s3c24xx_init_clocks(0);
165 s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs)); 167 s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
166 s3c24xx_set_board(&h1940_board); 168 s3c24xx_set_board(&h1940_board);
169
170 /* setup PM */
171
172 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
173 s3c2410_pm_init();
167} 174}
168 175
169static void __init h1940_init_irq(void) 176static void __init h1940_init_irq(void)
170{ 177{
171 s3c24xx_init_irq(); 178 s3c24xx_init_irq();
172
173} 179}
174 180
175static void __init h1940_init(void) 181static void __init h1940_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-osiris.c b/arch/arm/mach-s3c2410/mach-osiris.c
index e193ba69e652..a4ab144e7292 100644
--- a/arch/arm/mach-s3c2410/mach-osiris.c
+++ b/arch/arm/mach-s3c2410/mach-osiris.c
@@ -114,6 +114,15 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
114 .clocks = osiris_serial_clocks, 114 .clocks = osiris_serial_clocks,
115 .clocks_size = ARRAY_SIZE(osiris_serial_clocks), 115 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
116 }, 116 },
117 [2] = {
118 .hwport = 2,
119 .flags = 0,
120 .ucon = UCON,
121 .ulcon = ULCON,
122 .ufcon = UFCON,
123 .clocks = osiris_serial_clocks,
124 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
125 }
117}; 126};
118 127
119/* NAND Flash on Osiris board */ 128/* NAND Flash on Osiris board */
diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c
index 23d7c052013c..ecbcdf79d739 100644
--- a/arch/arm/mach-s3c2410/mach-rx3715.c
+++ b/arch/arm/mach-s3c2410/mach-rx3715.c
@@ -42,6 +42,7 @@
42#include <asm/arch/regs-gpio.h> 42#include <asm/arch/regs-gpio.h>
43#include <asm/arch/regs-lcd.h> 43#include <asm/arch/regs-lcd.h>
44 44
45#include <asm/arch/h1940.h>
45#include <asm/arch/nand.h> 46#include <asm/arch/nand.h>
46#include <asm/arch/fb.h> 47#include <asm/arch/fb.h>
47 48
@@ -224,7 +225,9 @@ static void __init rx3715_init_irq(void)
224 225
225static void __init rx3715_init_machine(void) 226static void __init rx3715_init_machine(void)
226{ 227{
228 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
227 s3c2410_pm_init(); 229 s3c2410_pm_init();
230
228 s3c24xx_fb_set_platdata(&rx3715_lcdcfg); 231 s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
229} 232}
230 233
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index a0d7692cdb2b..e2eda3937ab0 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -41,6 +41,7 @@
41 41
42#include <asm/arch/regs-serial.h> 42#include <asm/arch/regs-serial.h>
43#include <asm/arch/regs-gpio.h> 43#include <asm/arch/regs-gpio.h>
44#include <asm/arch/leds-gpio.h>
44 45
45#include "clock.h" 46#include "clock.h"
46#include "devs.h" 47#include "devs.h"
@@ -313,6 +314,50 @@ static struct platform_device vr1000_dm9k1 = {
313 } 314 }
314}; 315};
315 316
317/* LEDS */
318
319static struct s3c24xx_led_platdata vr1000_led1_pdata = {
320 .name = "led1",
321 .gpio = S3C2410_GPB0,
322 .def_trigger = "",
323};
324
325static struct s3c24xx_led_platdata vr1000_led2_pdata = {
326 .name = "led2",
327 .gpio = S3C2410_GPB1,
328 .def_trigger = "",
329};
330
331static struct s3c24xx_led_platdata vr1000_led3_pdata = {
332 .name = "led3",
333 .gpio = S3C2410_GPB2,
334 .def_trigger = "",
335};
336
337static struct platform_device vr1000_led1 = {
338 .name = "s3c24xx_led",
339 .id = 1,
340 .dev = {
341 .platform_data = &vr1000_led1_pdata,
342 },
343};
344
345static struct platform_device vr1000_led2 = {
346 .name = "s3c24xx_led",
347 .id = 2,
348 .dev = {
349 .platform_data = &vr1000_led2_pdata,
350 },
351};
352
353static struct platform_device vr1000_led3 = {
354 .name = "s3c24xx_led",
355 .id = 1,
356 .dev = {
357 .platform_data = &vr1000_led3_pdata,
358 },
359};
360
316/* devices for this board */ 361/* devices for this board */
317 362
318static struct platform_device *vr1000_devices[] __initdata = { 363static struct platform_device *vr1000_devices[] __initdata = {
@@ -325,7 +370,10 @@ static struct platform_device *vr1000_devices[] __initdata = {
325 &serial_device, 370 &serial_device,
326 &vr1000_nor, 371 &vr1000_nor,
327 &vr1000_dm9k0, 372 &vr1000_dm9k0,
328 &vr1000_dm9k1 373 &vr1000_dm9k1,
374 &vr1000_led1,
375 &vr1000_led2,
376 &vr1000_led3,
329}; 377};
330 378
331static struct clk *vr1000_clocks[] = { 379static struct clk *vr1000_clocks[] = {
diff --git a/arch/arm/mach-s3c2410/pm-h1940.S b/arch/arm/mach-s3c2410/pm-h1940.S
new file mode 100644
index 000000000000..7d66de7ff7db
--- /dev/null
+++ b/arch/arm/mach-s3c2410/pm-h1940.S
@@ -0,0 +1,33 @@
1/* linux/arch/arm/mach-s3c2410/pm-h1940.S
2 *
3 * Copyright (c) 2006 Ben Dooks <ben-linux@fluff.org>
4 *
5 * H1940 Suspend to RAM
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19*/
20
21#include <linux/linkage.h>
22#include <asm/assembler.h>
23#include <asm/hardware.h>
24#include <asm/arch/map.h>
25
26#include <asm/arch/regs-gpio.h>
27
28 .text
29 .global h1940_pm_return
30
31h1940_pm_return:
32 mov r0, #S3C2410_PA_GPIO
33 ldr pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ]
diff --git a/arch/arm/mach-s3c2410/s3c2410-pm.c b/arch/arm/mach-s3c2410/s3c2410-pm.c
index e51d76669512..77c6814c0f05 100644
--- a/arch/arm/mach-s3c2410/s3c2410-pm.c
+++ b/arch/arm/mach-s3c2410/s3c2410-pm.c
@@ -32,6 +32,7 @@
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33 33
34#include <asm/arch/regs-gpio.h> 34#include <asm/arch/regs-gpio.h>
35#include <asm/arch/h1940.h>
35 36
36#include "cpu.h" 37#include "cpu.h"
37#include "pm.h" 38#include "pm.h"
@@ -52,6 +53,35 @@ static void s3c2410_pm_prepare(void)
52 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); 53 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
53 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); 54 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
54 55
56 if (machine_is_h1940()) {
57 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
58 unsigned long ptr;
59 unsigned long calc = 0;
60
61 /* generate check for the bootloader to check on resume */
62
63 for (ptr = 0; ptr < 0x40000; ptr += 0x400)
64 calc += __raw_readl(base+ptr);
65
66 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
67 }
68
69 /* the RX3715 uses similar code and the same H1940 and the
70 * same offsets for resume and checksum pointers */
71
72 if (machine_is_rx3715()) {
73 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
74 unsigned long ptr;
75 unsigned long calc = 0;
76
77 /* generate check for the bootloader to check on resume */
78
79 for (ptr = 0; ptr < 0x40000; ptr += 0x4)
80 calc += __raw_readl(base+ptr);
81
82 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
83 }
84
55 if ( machine_is_aml_m5900() ) 85 if ( machine_is_aml_m5900() )
56 s3c2410_gpio_setpin(S3C2410_GPF2, 1); 86 s3c2410_gpio_setpin(S3C2410_GPF2, 1);
57 87
diff --git a/arch/arm/mach-s3c2410/s3c2412-irq.c b/arch/arm/mach-s3c2410/s3c2412-irq.c
index 7f741547658f..ffcc30b23a80 100644
--- a/arch/arm/mach-s3c2410/s3c2412-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2412-irq.c
@@ -98,7 +98,7 @@ s3c2412_irq_unmask(unsigned int irqno)
98 __raw_writel(mask & ~bitval, S3C2410_INTMSK); 98 __raw_writel(mask & ~bitval, S3C2410_INTMSK);
99} 99}
100 100
101static struct irqchip s3c2412_irq_eint0t4 = { 101static struct irq_chip s3c2412_irq_eint0t4 = {
102 .ack = s3c2412_irq_ack, 102 .ack = s3c2412_irq_ack,
103 .mask = s3c2412_irq_mask, 103 .mask = s3c2412_irq_mask,
104 .unmask = s3c2412_irq_unmask, 104 .unmask = s3c2412_irq_unmask,
@@ -112,7 +112,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
112 112
113 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 113 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
114 set_irq_chip(irqno, &s3c2412_irq_eint0t4); 114 set_irq_chip(irqno, &s3c2412_irq_eint0t4);
115 set_irq_handler(irqno, do_edge_IRQ); 115 set_irq_handler(irqno, handle_edge_irq);
116 set_irq_flags(irqno, IRQF_VALID); 116 set_irq_flags(irqno, IRQF_VALID);
117 } 117 }
118 118
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c
index 39db0752d53b..1ba19b27ab05 100644
--- a/arch/arm/mach-s3c2410/s3c2440-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2440-irq.c
@@ -42,10 +42,10 @@
42/* WDT/AC97 */ 42/* WDT/AC97 */
43 43
44static void s3c_irq_demux_wdtac97(unsigned int irq, 44static void s3c_irq_demux_wdtac97(unsigned int irq,
45 struct irqdesc *desc) 45 struct irq_desc *desc)
46{ 46{
47 unsigned int subsrc, submsk; 47 unsigned int subsrc, submsk;
48 struct irqdesc *mydesc; 48 struct irq_desc *mydesc;
49 49
50 /* read the current pending interrupts, and the mask 50 /* read the current pending interrupts, and the mask
51 * for what it is available */ 51 * for what it is available */
@@ -90,7 +90,7 @@ s3c_irq_wdtac97_ack(unsigned int irqno)
90 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13); 90 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
91} 91}
92 92
93static struct irqchip s3c_irq_wdtac97 = { 93static struct irq_chip s3c_irq_wdtac97 = {
94 .mask = s3c_irq_wdtac97_mask, 94 .mask = s3c_irq_wdtac97_mask,
95 .unmask = s3c_irq_wdtac97_unmask, 95 .unmask = s3c_irq_wdtac97_unmask,
96 .ack = s3c_irq_wdtac97_ack, 96 .ack = s3c_irq_wdtac97_ack,
@@ -105,12 +105,12 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
105 /* add new chained handler for wdt, ac7 */ 105 /* add new chained handler for wdt, ac7 */
106 106
107 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); 107 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
108 set_irq_handler(IRQ_WDT, do_level_IRQ); 108 set_irq_handler(IRQ_WDT, handle_level_irq);
109 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); 109 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
110 110
111 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { 111 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
112 set_irq_chip(irqno, &s3c_irq_wdtac97); 112 set_irq_chip(irqno, &s3c_irq_wdtac97);
113 set_irq_handler(irqno, do_level_IRQ); 113 set_irq_handler(irqno, handle_level_irq);
114 set_irq_flags(irqno, IRQF_VALID); 114 set_irq_flags(irqno, IRQF_VALID);
115 } 115 }
116 116
diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c
index 146f2109dd90..ede94636a72a 100644
--- a/arch/arm/mach-s3c2410/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2410/s3c244x-irq.c
@@ -42,10 +42,10 @@
42/* camera irq */ 42/* camera irq */
43 43
44static void s3c_irq_demux_cam(unsigned int irq, 44static void s3c_irq_demux_cam(unsigned int irq,
45 struct irqdesc *desc) 45 struct irq_desc *desc)
46{ 46{
47 unsigned int subsrc, submsk; 47 unsigned int subsrc, submsk;
48 struct irqdesc *mydesc; 48 struct irq_desc *mydesc;
49 49
50 /* read the current pending interrupts, and the mask 50 /* read the current pending interrupts, and the mask
51 * for what it is available */ 51 * for what it is available */
@@ -89,7 +89,7 @@ s3c_irq_cam_ack(unsigned int irqno)
89 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11); 89 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
90} 90}
91 91
92static struct irqchip s3c_irq_cam = { 92static struct irq_chip s3c_irq_cam = {
93 .mask = s3c_irq_cam_mask, 93 .mask = s3c_irq_cam_mask,
94 .unmask = s3c_irq_cam_unmask, 94 .unmask = s3c_irq_cam_unmask,
95 .ack = s3c_irq_cam_ack, 95 .ack = s3c_irq_cam_ack,
@@ -100,18 +100,18 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
100 unsigned int irqno; 100 unsigned int irqno;
101 101
102 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); 102 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
103 set_irq_handler(IRQ_NFCON, do_level_IRQ); 103 set_irq_handler(IRQ_NFCON, handle_level_irq);
104 set_irq_flags(IRQ_NFCON, IRQF_VALID); 104 set_irq_flags(IRQ_NFCON, IRQF_VALID);
105 105
106 /* add chained handler for camera */ 106 /* add chained handler for camera */
107 107
108 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); 108 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
109 set_irq_handler(IRQ_CAM, do_level_IRQ); 109 set_irq_handler(IRQ_CAM, handle_level_irq);
110 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); 110 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
111 111
112 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { 112 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
113 set_irq_chip(irqno, &s3c_irq_cam); 113 set_irq_chip(irqno, &s3c_irq_cam);
114 set_irq_handler(irqno, do_level_IRQ); 114 set_irq_handler(irqno, handle_level_irq);
115 set_irq_flags(irqno, IRQF_VALID); 115 set_irq_flags(irqno, IRQF_VALID);
116 } 116 }
117 117
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index fa6dc71bd6ad..b034ad69a324 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -702,7 +702,7 @@ static u32 gpio_irq_mask[] = {
702 GPIO2_SD_CON_SLT, 702 GPIO2_SD_CON_SLT,
703}; 703};
704 704
705static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc) 705static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc)
706{ 706{
707 int i; 707 int i;
708 708
@@ -719,14 +719,14 @@ static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc)
719 if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq); 719 if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq);
720 for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++) 720 for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++)
721 if (irq & kpio_irq_mask[j]) 721 if (irq & kpio_irq_mask[j])
722 do_edge_IRQ(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j); 722 handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j);
723 723
724 /* GPIO2 */ 724 /* GPIO2 */
725 irq = H3800_ASIC2_GPIINTFLAG; 725 irq = H3800_ASIC2_GPIINTFLAG;
726 if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq); 726 if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq);
727 for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++) 727 for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++)
728 if (irq & gpio_irq_mask[j]) 728 if (irq & gpio_irq_mask[j])
729 do_edge_IRQ(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j); 729 handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j);
730 } 730 }
731 731
732 if (i >= MAX_ASIC_ISR_LOOPS) 732 if (i >= MAX_ASIC_ISR_LOOPS)
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index f4c6322ca33e..5642aeca079e 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -110,7 +110,7 @@ static struct irq_chip sa1100_low_gpio_chip = {
110 * and call the handler. 110 * and call the handler.
111 */ 111 */
112static void 112static void
113sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc) 113sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
114{ 114{
115 unsigned int mask; 115 unsigned int mask;
116 116
@@ -327,19 +327,19 @@ void __init sa1100_init_irq(void)
327 327
328 for (irq = 0; irq <= 10; irq++) { 328 for (irq = 0; irq <= 10; irq++) {
329 set_irq_chip(irq, &sa1100_low_gpio_chip); 329 set_irq_chip(irq, &sa1100_low_gpio_chip);
330 set_irq_handler(irq, do_edge_IRQ); 330 set_irq_handler(irq, handle_edge_irq);
331 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 331 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
332 } 332 }
333 333
334 for (irq = 12; irq <= 31; irq++) { 334 for (irq = 12; irq <= 31; irq++) {
335 set_irq_chip(irq, &sa1100_normal_chip); 335 set_irq_chip(irq, &sa1100_normal_chip);
336 set_irq_handler(irq, do_level_IRQ); 336 set_irq_handler(irq, handle_level_irq);
337 set_irq_flags(irq, IRQF_VALID); 337 set_irq_flags(irq, IRQF_VALID);
338 } 338 }
339 339
340 for (irq = 32; irq <= 48; irq++) { 340 for (irq = 32; irq <= 48; irq++) {
341 set_irq_chip(irq, &sa1100_high_gpio_chip); 341 set_irq_chip(irq, &sa1100_high_gpio_chip);
342 set_irq_handler(irq, do_edge_IRQ); 342 set_irq_handler(irq, handle_edge_irq);
343 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 343 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
344 } 344 }
345 345
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 354d5e91da59..075d4d1d63be 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -29,12 +29,12 @@
29 * is rather unfortunate. 29 * is rather unfortunate.
30 */ 30 */
31static void 31static void
32neponset_irq_handler(unsigned int irq, struct irqdesc *desc) 32neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
33{ 33{
34 unsigned int irr; 34 unsigned int irr;
35 35
36 while (1) { 36 while (1) {
37 struct irqdesc *d; 37 struct irq_desc *d;
38 38
39 /* 39 /*
40 * Acknowledge the parent IRQ. 40 * Acknowledge the parent IRQ.
@@ -168,9 +168,9 @@ static int neponset_probe(struct platform_device *dev)
168 * Setup other Neponset IRQs. SA1111 will be done by the 168 * Setup other Neponset IRQs. SA1111 will be done by the
169 * generic SA1111 code. 169 * generic SA1111 code.
170 */ 170 */
171 set_irq_handler(IRQ_NEPONSET_SMC9196, do_simple_IRQ); 171 set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
172 set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); 172 set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
173 set_irq_handler(IRQ_NEPONSET_USAR, do_simple_IRQ); 173 set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
174 set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); 174 set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
175 175
176 /* 176 /*
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 4284bd6f7a1f..29c89f9eb2ce 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -118,6 +118,7 @@ static struct irqaction sa1100_timer_irq = {
118static void __init sa1100_timer_init(void) 118static void __init sa1100_timer_init(void)
119{ 119{
120 struct timespec tv; 120 struct timespec tv;
121 unsigned long flags;
121 122
122 set_rtc = sa1100_set_rtc; 123 set_rtc = sa1100_set_rtc;
123 124
@@ -126,12 +127,12 @@ static void __init sa1100_timer_init(void)
126 do_settimeofday(&tv); 127 do_settimeofday(&tv);
127 128
128 OIER = 0; /* disable any timer interrupts */ 129 OIER = 0; /* disable any timer interrupts */
129 OSCR = LATCH*2; /* push OSCR out of the way */
130 OSMR0 = LATCH; /* set initial match */
131 OSSR = 0xf; /* clear status on all timers */ 130 OSSR = 0xf; /* clear status on all timers */
132 setup_irq(IRQ_OST0, &sa1100_timer_irq); 131 setup_irq(IRQ_OST0, &sa1100_timer_irq);
132 local_irq_save(flags);
133 OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */ 133 OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */
134 OSCR = 0; /* initialize free-running timer */ 134 OSMR0 = OSCR + LATCH; /* set initial match */
135 local_irq_restore(flags);
135} 136}
136 137
137#ifdef CONFIG_NO_IDLE_HZ 138#ifdef CONFIG_NO_IDLE_HZ
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c
index 297ecf130650..00a6c1466867 100644
--- a/arch/arm/mach-shark/irq.c
+++ b/arch/arm/mach-shark/irq.c
@@ -82,7 +82,7 @@ void __init shark_init_irq(void)
82 82
83 for (irq = 0; irq < NR_IRQS; irq++) { 83 for (irq = 0; irq < NR_IRQS; irq++) {
84 set_irq_chip(irq, &fb_chip); 84 set_irq_chip(irq, &fb_chip);
85 set_irq_handler(irq, do_edge_IRQ); 85 set_irq_handler(irq, handle_edge_irq);
86 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 86 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
87 } 87 }
88 88
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 998b398df30e..57196947559f 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -78,7 +78,7 @@ static struct irq_chip sic_chip = {
78}; 78};
79 79
80static void 80static void
81sic_handle_irq(unsigned int irq, struct irqdesc *desc) 81sic_handle_irq(unsigned int irq, struct irq_desc *desc)
82{ 82{
83 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS); 83 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
84 84
@@ -124,7 +124,7 @@ void __init versatile_init_irq(void)
124 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { 124 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
125 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) { 125 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
126 set_irq_chip(i, &sic_chip); 126 set_irq_chip(i, &sic_chip);
127 set_irq_handler(i, do_level_IRQ); 127 set_irq_handler(i, handle_level_irq);
128 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 128 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
129 } 129 }
130 } 130 }
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 503725b166fc..be439bb9d450 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -81,22 +81,18 @@ static struct amba_device *amba_devs[] __initdata = {
81 &mmc1_device, 81 &mmc1_device,
82}; 82};
83 83
84static int __init versatile_pb_init(void) 84static void __init versatile_pb_init(void)
85{ 85{
86 int i; 86 int i;
87 87
88 if (machine_is_versatile_pb()) { 88 versatile_init();
89 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
90 struct amba_device *d = amba_devs[i];
91 amba_device_register(d, &iomem_resource);
92 }
93 }
94 89
95 return 0; 90 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
91 struct amba_device *d = amba_devs[i];
92 amba_device_register(d, &iomem_resource);
93 }
96} 94}
97 95
98arch_initcall(versatile_pb_init);
99
100MACHINE_START(VERSATILE_PB, "ARM-Versatile PB") 96MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
101 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 97 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
102 .phys_io = 0x101f1000, 98 .phys_io = 0x101f1000,
@@ -105,5 +101,5 @@ MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
105 .map_io = versatile_map_io, 101 .map_io = versatile_map_io,
106 .init_irq = versatile_init_irq, 102 .init_irq = versatile_init_irq,
107 .timer = &versatile_timer, 103 .timer = &versatile_timer,
108 .init_machine = versatile_init, 104 .init_machine = versatile_pb_init,
109MACHINE_END 105MACHINE_END
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c0bfb8212b77..125cb3ff5589 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -333,7 +333,7 @@ config CPU_XSCALE
333# XScale Core Version 3 333# XScale Core Version 3
334config CPU_XSC3 334config CPU_XSC3
335 bool 335 bool
336 depends on ARCH_IXP23XX 336 depends on ARCH_IXP23XX || ARCH_IOP13XX
337 default y 337 default y
338 select CPU_32v5 338 select CPU_32v5
339 select CPU_ABRT_EV5T 339 select CPU_ABRT_EV5T
@@ -580,7 +580,7 @@ config CPU_CACHE_ROUND_ROBIN
580 580
581config CPU_BPREDICT_DISABLE 581config CPU_BPREDICT_DISABLE
582 bool "Disable branch prediction" 582 bool "Disable branch prediction"
583 depends on CPU_ARM1020 || CPU_V6 583 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3
584 help 584 help
585 Say Y here to disable branch prediction. If unsure, say N. 585 Say Y here to disable branch prediction. If unsure, say N.
586 586
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index bb2bc9ab6bd3..a44e30970635 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -1,4 +1,7 @@
1/* the upper-most page table pointer */ 1/* the upper-most page table pointer */
2
3#ifdef CONFIG_MMU
4
2extern pmd_t *top_pmd; 5extern pmd_t *top_pmd;
3 6
4#define TOP_PTE(x) pte_offset_kernel(top_pmd, x) 7#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
@@ -13,6 +16,8 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
13 return pmd_off(pgd_offset_k(virt), virt); 16 return pmd_off(pgd_offset_k(virt), virt);
14} 17}
15 18
19#endif
20
16struct map_desc; 21struct map_desc;
17struct meminfo; 22struct meminfo;
18struct pglist_data; 23struct pglist_data;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index f866bf6b97d4..b7f194af20b4 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -265,7 +265,7 @@ static void __init build_mem_type_table(void)
265 if (arch_is_coherent()) { 265 if (arch_is_coherent()) {
266 if (cpu_is_xsc3()) { 266 if (cpu_is_xsc3()) {
267 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 267 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
268 mem_types[MT_MEMORY].prot_pte |= L_PTE_COHERENT; 268 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
269 } 269 }
270 } 270 }
271 271
@@ -619,6 +619,13 @@ void __init reserve_node_zero(pg_data_t *pgdat)
619 if (machine_is_p720t()) 619 if (machine_is_p720t())
620 res_size = 0x00014000; 620 res_size = 0x00014000;
621 621
622 /* H1940 and RX3715 need to reserve this for suspend */
623
624 if (machine_is_h1940() || machine_is_rx3715()) {
625 reserve_bootmem_node(pgdat, 0x30003000, 0x1000);
626 reserve_bootmem_node(pgdat, 0x30081000, 0x1000);
627 }
628
622#ifdef CONFIG_SA1111 629#ifdef CONFIG_SA1111
623 /* 630 /*
624 * Because of the SA1111 DMA bug, we want to preserve our 631 * Because of the SA1111 DMA bug, we want to preserve our
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index d0e66424a597..05818fc0c705 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -6,10 +6,12 @@
6#include <linux/module.h> 6#include <linux/module.h>
7#include <linux/mm.h> 7#include <linux/mm.h>
8#include <linux/pagemap.h> 8#include <linux/pagemap.h>
9#include <linux/bootmem.h>
9 10
10#include <asm/cacheflush.h> 11#include <asm/cacheflush.h>
11#include <asm/io.h> 12#include <asm/io.h>
12#include <asm/page.h> 13#include <asm/page.h>
14#include <asm/mach/arch.h>
13 15
14#include "mm.h" 16#include "mm.h"
15 17
@@ -76,7 +78,7 @@ void __iomem *__ioremap(unsigned long phys_addr, size_t size,
76} 78}
77EXPORT_SYMBOL(__ioremap); 79EXPORT_SYMBOL(__ioremap);
78 80
79void __iounmap(void __iomem *addr) 81void __iounmap(volatile void __iomem *addr)
80{ 82{
81} 83}
82EXPORT_SYMBOL(__iounmap); 84EXPORT_SYMBOL(__iounmap);
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 1d8316f3cecf..289b8e6f504d 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -29,9 +29,9 @@
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/elf.h>
32#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
33#include <asm/pgtable.h> 34#include <asm/pgtable.h>
34#include <asm/procinfo.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
36 36
37#include "proc-macros.S" 37#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 89b1d6d3d7c0..bed9db6ba582 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -29,9 +29,9 @@
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/elf.h>
32#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
33#include <asm/pgtable.h> 34#include <asm/pgtable.h>
34#include <asm/procinfo.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
36 36
37#include "proc-macros.S" 37#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index a089528e6bce..d2a7c1b9cab9 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -18,9 +18,9 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/elf.h>
21#include <asm/pgtable-hwdef.h> 22#include <asm/pgtable-hwdef.h>
22#include <asm/pgtable.h> 23#include <asm/pgtable.h>
23#include <asm/procinfo.h>
24#include <asm/ptrace.h> 24#include <asm/ptrace.h>
25 25
26#include "proc-macros.S" 26#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index d6d84d92c7c7..3247ce5c0177 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -18,9 +18,9 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/elf.h>
21#include <asm/pgtable-hwdef.h> 22#include <asm/pgtable-hwdef.h>
22#include <asm/pgtable.h> 23#include <asm/pgtable.h>
23#include <asm/procinfo.h>
24#include <asm/ptrace.h> 24#include <asm/ptrace.h>
25 25
26#include "proc-macros.S" 26#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 0432e4806888..ce4f9eef763c 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -15,9 +15,9 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <asm/assembler.h> 16#include <asm/assembler.h>
17#include <asm/asm-offsets.h> 17#include <asm/asm-offsets.h>
18#include <asm/elf.h>
18#include <asm/pgtable-hwdef.h> 19#include <asm/pgtable-hwdef.h>
19#include <asm/pgtable.h> 20#include <asm/pgtable.h>
20#include <asm/procinfo.h>
21#include <asm/ptrace.h> 21#include <asm/ptrace.h>
22 22
23ENTRY(cpu_arm6_dcache_clean_area) 23ENTRY(cpu_arm6_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index c2f0705bfd49..c04c194da785 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -36,9 +36,9 @@
36#include <linux/init.h> 36#include <linux/init.h>
37#include <asm/assembler.h> 37#include <asm/assembler.h>
38#include <asm/asm-offsets.h> 38#include <asm/asm-offsets.h>
39#include <asm/elf.h>
39#include <asm/pgtable-hwdef.h> 40#include <asm/pgtable-hwdef.h>
40#include <asm/pgtable.h> 41#include <asm/pgtable.h>
41#include <asm/procinfo.h>
42#include <asm/ptrace.h> 42#include <asm/ptrace.h>
43 43
44#include "proc-macros.S" 44#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 40713818a87b..7069f495cf9b 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -12,9 +12,9 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/elf.h>
15#include <asm/pgtable-hwdef.h> 16#include <asm/pgtable-hwdef.h>
16#include <asm/pgtable.h> 17#include <asm/pgtable.h>
17#include <asm/procinfo.h>
18#include <asm/ptrace.h> 18#include <asm/ptrace.h>
19 19
20 .text 20 .text
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 22d7e3100ea6..d091c2571823 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -12,9 +12,9 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/elf.h>
15#include <asm/pgtable-hwdef.h> 16#include <asm/pgtable-hwdef.h>
16#include <asm/pgtable.h> 17#include <asm/pgtable.h>
17#include <asm/procinfo.h>
18#include <asm/ptrace.h> 18#include <asm/ptrace.h>
19 19
20 .text 20 .text
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 4adb46b3a4e0..65cbb2851bff 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -28,9 +28,9 @@
28#include <linux/linkage.h> 28#include <linux/linkage.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/elf.h>
31#include <asm/pgtable-hwdef.h> 32#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/procinfo.h>
34#include <asm/page.h> 34#include <asm/page.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
36#include "proc-macros.S" 36#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 571f082f0247..52761b70d735 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -29,9 +29,9 @@
29#include <linux/linkage.h> 29#include <linux/linkage.h>
30#include <linux/init.h> 30#include <linux/init.h>
31#include <asm/assembler.h> 31#include <asm/assembler.h>
32#include <asm/elf.h>
32#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
33#include <asm/pgtable.h> 34#include <asm/pgtable.h>
34#include <asm/procinfo.h>
35#include <asm/page.h> 35#include <asm/page.h>
36#include <asm/ptrace.h> 36#include <asm/ptrace.h>
37#include "proc-macros.S" 37#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 8d9a9f93b011..5b74339d1588 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -52,9 +52,9 @@
52#include <linux/linkage.h> 52#include <linux/linkage.h>
53#include <linux/init.h> 53#include <linux/init.h>
54#include <asm/assembler.h> 54#include <asm/assembler.h>
55#include <asm/elf.h>
55#include <asm/pgtable-hwdef.h> 56#include <asm/pgtable-hwdef.h>
56#include <asm/pgtable.h> 57#include <asm/pgtable.h>
57#include <asm/procinfo.h>
58#include <asm/page.h> 58#include <asm/page.h>
59#include <asm/ptrace.h> 59#include <asm/ptrace.h>
60#include "proc-macros.S" 60#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 44a7a652d625..8628ed29a955 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -28,9 +28,9 @@
28#include <linux/linkage.h> 28#include <linux/linkage.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/elf.h>
31#include <asm/pgtable-hwdef.h> 32#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/procinfo.h>
34#include <asm/page.h> 34#include <asm/page.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
36#include "proc-macros.S" 36#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 2397f4b6e151..786c593778f0 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -11,9 +11,9 @@
11#include <linux/linkage.h> 11#include <linux/linkage.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/elf.h>
14#include <asm/pgtable-hwdef.h> 15#include <asm/pgtable-hwdef.h>
15#include <asm/pgtable.h> 16#include <asm/pgtable.h>
16#include <asm/procinfo.h>
17#include <asm/ptrace.h> 17#include <asm/ptrace.h>
18 18
19/* ARM940T has a 4KB DCache comprising 256 lines of 4 words */ 19/* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index e18617564421..a60c1421d450 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -13,9 +13,9 @@
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <asm/assembler.h> 15#include <asm/assembler.h>
16#include <asm/elf.h>
16#include <asm/pgtable-hwdef.h> 17#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h> 18#include <asm/pgtable.h>
18#include <asm/procinfo.h>
19#include <asm/ptrace.h> 19#include <asm/ptrace.h>
20 20
21/* 21/*
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 918ebf65d4f6..4848eeac86b6 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -12,9 +12,9 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/elf.h>
15#include <asm/pgtable-hwdef.h> 16#include <asm/pgtable-hwdef.h>
16#include <asm/pgtable.h> 17#include <asm/pgtable.h>
17#include <asm/procinfo.h>
18#include <asm/ptrace.h> 18#include <asm/ptrace.h>
19 19
20 .text 20 .text
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index c878064e9b88..cd7d865c9d19 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -17,7 +17,7 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <asm/assembler.h> 18#include <asm/assembler.h>
19#include <asm/asm-offsets.h> 19#include <asm/asm-offsets.h>
20#include <asm/procinfo.h> 20#include <asm/elf.h>
21#include <asm/hardware.h> 21#include <asm/hardware.h>
22#include <asm/pgtable-hwdef.h> 22#include <asm/pgtable-hwdef.h>
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index b23b66a6155a..b776653cc31c 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -22,7 +22,7 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <asm/assembler.h> 23#include <asm/assembler.h>
24#include <asm/asm-offsets.h> 24#include <asm/asm-offsets.h>
25#include <asm/procinfo.h> 25#include <asm/elf.h>
26#include <asm/hardware.h> 26#include <asm/hardware.h>
27#include <asm/pgtable-hwdef.h> 27#include <asm/pgtable-hwdef.h>
28#include <asm/pgtable.h> 28#include <asm/pgtable.h>
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 6f72549f8843..b440c8a1d345 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -13,8 +13,8 @@
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <asm/assembler.h> 14#include <asm/assembler.h>
15#include <asm/asm-offsets.h> 15#include <asm/asm-offsets.h>
16#include <asm/elf.h>
16#include <asm/hardware/arm_scu.h> 17#include <asm/hardware/arm_scu.h>
17#include <asm/procinfo.h>
18#include <asm/pgtable-hwdef.h> 18#include <asm/pgtable-hwdef.h>
19#include <asm/pgtable.h> 19#include <asm/pgtable.h>
20 20
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 4ace2d8090c7..1ef564d0957f 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -27,7 +27,7 @@
27#include <linux/linkage.h> 27#include <linux/linkage.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <asm/assembler.h> 29#include <asm/assembler.h>
30#include <asm/procinfo.h> 30#include <asm/elf.h>
31#include <asm/hardware.h> 31#include <asm/hardware.h>
32#include <asm/pgtable.h> 32#include <asm/pgtable.h>
33#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
@@ -57,11 +57,6 @@
57#define L2_CACHE_ENABLE 1 57#define L2_CACHE_ENABLE 1
58 58
59/* 59/*
60 * Enable the Branch Target Buffer (can cause crashes, see erratum #42.)
61 */
62#define BTB_ENABLE 0
63
64/*
65 * This macro is used to wait for a CP15 write and is needed 60 * This macro is used to wait for a CP15 write and is needed
66 * when we have to ensure that the last operation to the co-pro 61 * when we have to ensure that the last operation to the co-pro
67 * was completed before continuing with operation. 62 * was completed before continuing with operation.
@@ -371,8 +366,10 @@ ENTRY(cpu_xsc3_switch_mm)
371ENTRY(cpu_xsc3_set_pte) 366ENTRY(cpu_xsc3_set_pte)
372 str r1, [r0], #-2048 @ linux version 367 str r1, [r0], #-2048 @ linux version
373 368
374 bic r2, r1, #0xdf0 @ Keep C, B, coherency bits 369 bic r2, r1, #0xff0 @ Keep C, B bits
375 orr r2, r2, #PTE_TYPE_EXT @ extended page 370 orr r2, r2, #PTE_TYPE_EXT @ extended page
371 tst r1, #L_PTE_SHARED @ Shared?
372 orrne r2, r2, #0x200
376 373
377 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 374 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
378 375
@@ -432,9 +429,7 @@ __xsc3_setup:
432 mrc p15, 0, r0, c1, c0, 0 @ get control register 429 mrc p15, 0, r0, c1, c0, 0 @ get control register
433 bic r0, r0, r5 @ .... .... .... ..A. 430 bic r0, r0, r5 @ .... .... .... ..A.
434 orr r0, r0, r6 @ .... .... .... .C.M 431 orr r0, r0, r6 @ .... .... .... .C.M
435#if BTB_ENABLE
436 orr r0, r0, #0x00000800 @ ..VI Z..S .... .... 432 orr r0, r0, #0x00000800 @ ..VI Z..S .... ....
437#endif
438#if L2_CACHE_ENABLE 433#if L2_CACHE_ENABLE
439 orr r0, r0, #0x04000000 @ L2 enable 434 orr r0, r0, #0x04000000 @ L2 enable
440#endif 435#endif
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 2749c1f88d7d..cc1004b3e511 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -23,7 +23,7 @@
23#include <linux/linkage.h> 23#include <linux/linkage.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <asm/assembler.h> 25#include <asm/assembler.h>
26#include <asm/procinfo.h> 26#include <asm/elf.h>
27#include <asm/pgtable.h> 27#include <asm/pgtable.h>
28#include <asm/pgtable-hwdef.h> 28#include <asm/pgtable-hwdef.h>
29#include <asm/page.h> 29#include <asm/page.h>
@@ -491,12 +491,7 @@ __xscale_setup:
491 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB 491 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
492 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 492 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
493 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs 493 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
494#ifdef CONFIG_IWMMXT 494 mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
495 mov r0, #0 @ initially disallow access to CP0/CP1
496#else
497 mov r0, #1 @ Allow access to CP0
498#endif
499 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
500 orr r0, r0, #1 << 13 @ Its undefined whether this 495 orr r0, r0, #1 << 13 @ Its undefined whether this
501 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 496 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
502 497
@@ -909,7 +904,7 @@ __pxa270_proc_info:
909 b __xscale_setup 904 b __xscale_setup
910 .long cpu_arch_name 905 .long cpu_arch_name
911 .long cpu_elf_name 906 .long cpu_elf_name
912 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_IWMMXT 907 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
913 .long cpu_pxa270_name 908 .long cpu_pxa270_name
914 .long xscale_processor_functions 909 .long xscale_processor_functions
915 .long v4wbi_tlb_fns 910 .long v4wbi_tlb_fns
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 8162eed8b500..4f2fd5591337 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -410,7 +410,7 @@ static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int tr
410 trigger & __IRQT_RISEDGE); 410 trigger & __IRQT_RISEDGE);
411 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 411 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
412 trigger & __IRQT_FALEDGE); 412 trigger & __IRQT_FALEDGE);
413 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level 413 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
414 * triggering requested. */ 414 * triggering requested. */
415} 415}
416 416
@@ -783,7 +783,7 @@ void omap_free_gpio(int gpio)
783 * line's interrupt handler has been run, we may miss some nested 783 * line's interrupt handler has been run, we may miss some nested
784 * interrupts. 784 * interrupts.
785 */ 785 */
786static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc) 786static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
787{ 787{
788 void __iomem *isr_reg = NULL; 788 void __iomem *isr_reg = NULL;
789 u32 isr; 789 u32 isr;
@@ -853,7 +853,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
853 853
854 gpio_irq = bank->virtual_irq_start; 854 gpio_irq = bank->virtual_irq_start;
855 for (; isr != 0; isr >>= 1, gpio_irq++) { 855 for (; isr != 0; isr >>= 1, gpio_irq++) {
856 struct irqdesc *d; 856 struct irq_desc *d;
857 int irq_mask; 857 int irq_mask;
858 if (!(isr & 1)) 858 if (!(isr & 1))
859 continue; 859 continue;
@@ -1092,7 +1092,7 @@ static int __init _omap_gpio_init(void)
1092 set_irq_chip(j, &mpuio_irq_chip); 1092 set_irq_chip(j, &mpuio_irq_chip);
1093 else 1093 else
1094 set_irq_chip(j, &gpio_irq_chip); 1094 set_irq_chip(j, &gpio_irq_chip);
1095 set_irq_handler(j, do_simple_IRQ); 1095 set_irq_handler(j, handle_simple_irq);
1096 set_irq_flags(j, IRQF_VALID); 1096 set_irq_flags(j, IRQF_VALID);
1097 } 1097 }
1098 set_irq_chained_handler(bank->irq, gpio_irq_handler); 1098 set_irq_chained_handler(bank->irq, gpio_irq_handler);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 579c69ae9ff7..8bcb838e5444 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
12# 12#
13# http://www.arm.linux.org.uk/developer/machines/?action=new 13# http://www.arm.linux.org.uk/developer/machines/?action=new
14# 14#
15# Last update: Mon Oct 16 21:13:36 2006 15# Last update: Thu Dec 7 17:19:20 2006
16# 16#
17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
18# 18#
@@ -79,7 +79,7 @@ psionw ARCH_PSIONW PSIONW 60
79aln SA1100_ALN ALN 61 79aln SA1100_ALN ALN 61
80epxa ARCH_CAMELOT CAMELOT 62 80epxa ARCH_CAMELOT CAMELOT 62
81gds2200 SA1100_GDS2200 GDS2200 63 81gds2200 SA1100_GDS2200 GDS2200 63
82psion_series7 SA1100_PSION_SERIES7 PSION_SERIES7 64 82netbook SA1100_PSION_SERIES7 PSION_SERIES7 64
83xfile SA1100_XFILE XFILE 65 83xfile SA1100_XFILE XFILE 65
84accelent_ep9312 ARCH_ACCELENT_EP9312 ACCELENT_EP9312 66 84accelent_ep9312 ARCH_ACCELENT_EP9312 ACCELENT_EP9312 66
85ic200 ARCH_IC200 IC200 67 85ic200 ARCH_IC200 IC200 67
@@ -810,9 +810,9 @@ sb3010 MACH_SB3010 SB3010 795
810rm9200 MACH_RM9200 RM9200 796 810rm9200 MACH_RM9200 RM9200 796
811dma03 MACH_DMA03 DMA03 797 811dma03 MACH_DMA03 DMA03 797
812road_s101 MACH_ROAD_S101 ROAD_S101 798 812road_s101 MACH_ROAD_S101 ROAD_S101 798
813iq_nextgen_a MACH_IQ_NEXTGEN_A IQ_NEXTGEN_A 799 813iq81340sc MACH_IQ81340SC IQ81340SC 799
814iq_nextgen_b MACH_IQ_NEXTGEN_B IQ_NEXTGEN_B 800 814iq_nextgen_b MACH_IQ_NEXTGEN_B IQ_NEXTGEN_B 800
815iq_nextgen_c MACH_IQ_NEXTGEN_C IQ_NEXTGEN_C 801 815iq81340mc MACH_IQ81340MC IQ81340MC 801
816iq_nextgen_d MACH_IQ_NEXTGEN_D IQ_NEXTGEN_D 802 816iq_nextgen_d MACH_IQ_NEXTGEN_D IQ_NEXTGEN_D 802
817iq_nextgen_e MACH_IQ_NEXTGEN_E IQ_NEXTGEN_E 803 817iq_nextgen_e MACH_IQ_NEXTGEN_E IQ_NEXTGEN_E 803
818mallow_at91 MACH_MALLOW_AT91 MALLOW_AT91 804 818mallow_at91 MACH_MALLOW_AT91 MALLOW_AT91 804
@@ -1165,9 +1165,57 @@ pnx4010 MACH_PNX4010 PNX4010 1151
1165oxnas MACH_OXNAS OXNAS 1152 1165oxnas MACH_OXNAS OXNAS 1152
1166fiori MACH_FIORI FIORI 1153 1166fiori MACH_FIORI FIORI 1153
1167ml1200 MACH_ML1200 ML1200 1154 1167ml1200 MACH_ML1200 ML1200 1154
1168cactus MACH_CACTUS CACTUS 1155 1168pecos MACH_PECOS PECOS 1155
1169nb2xxx MACH_NB2XXX NB2XXX 1156 1169nb2xxx MACH_NB2XXX NB2XXX 1156
1170hw6900 MACH_HW6900 HW6900 1157 1170hw6900 MACH_HW6900 HW6900 1157
1171cdcs_quoll MACH_CDCS_QUOLL CDCS_QUOLL 1158 1171cdcs_quoll MACH_CDCS_QUOLL CDCS_QUOLL 1158
1172quicksilver MACH_QUICKSILVER QUICKSILVER 1159 1172quicksilver MACH_QUICKSILVER QUICKSILVER 1159
1173uplat926 MACH_UPLAT926 UPLAT926 1160 1173uplat926 MACH_UPLAT926 UPLAT926 1160
1174dep2410_dep2410 MACH_DEP2410_THOMAS DEP2410_THOMAS 1161
1175dtk2410 MACH_DTK2410 DTK2410 1162
1176chili MACH_CHILI CHILI 1163
1177demeter MACH_DEMETER DEMETER 1164
1178dionysus MACH_DIONYSUS DIONYSUS 1165
1179as352x MACH_AS352X AS352X 1166
1180service MACH_SERVICE SERVICE 1167
1181cs_e9301 MACH_CS_E9301 CS_E9301 1168
1182micro9m MACH_MICRO9M MICRO9M 1169
1183ia_mospck MACH_IA_MOSPCK IA_MOSPCK 1170
1184ql201b MACH_QL201B QL201B 1171
1185bbm MACH_BBM BBM 1174
1186exxx MACH_EXXX EXXX 1175
1187wma11b MACH_WMA11B WMA11B 1176
1188pelco_atlas MACH_PELCO_ATLAS PELCO_ATLAS 1177
1189g500 MACH_G500 G500 1178
1190bug MACH_BUG BUG 1179
1191mx33ads MACH_MX33ADS MX33ADS 1180
1192chub MACH_CHUB CHUB 1181
1193gta01 MACH_GTA01 GTA01 1182
1194w90n740 MACH_W90N740 W90N740 1183
1195medallion_sa2410 MACH_MEDALLION_SA2410 MEDALLION_SA2410 1184
1196ia_cpu_9200_2 MACH_IA_CPU_9200_2 IA_CPU_9200_2 1185
1197dimmrm9200 MACH_DIMMRM9200 DIMMRM9200 1186
1198pm9261 MACH_PM9261 PM9261 1187
1199mx21 MACH_MX21 MX21 1188
1200ml7304 MACH_ML7304 ML7304 1189
1201ucp250 MACH_UCP250 UCP250 1190
1202intboard MACH_INTBOARD INTBOARD 1191
1203gulfstream MACH_GULFSTREAM GULFSTREAM 1192
1204labquest MACH_LABQUEST LABQUEST 1193
1205vcmx313 MACH_VCMX313 VCMX313 1194
1206urg200 MACH_URG200 URG200 1195
1207cpux255lcdnet MACH_CPUX255LCDNET CPUX255LCDNET 1196
1208netdcu9 MACH_NETDCU9 NETDCU9 1197
1209netdcu10 MACH_NETDCU10 NETDCU10 1198
1210dspg_dga MACH_DSPG_DGA DSPG_DGA 1199
1211dspg_dvw MACH_DSPG_DVW DSPG_DVW 1200
1212solos MACH_SOLOS SOLOS 1201
1213at91sam9263ek MACH_AT91SAM9263EK AT91SAM9263EK 1202
1214osstbox MACH_OSSTBOX OSSTBOX 1203
1215kbat9261 MACH_KBAT9261 KBAT9261 1204
1216ct1100 MACH_CT1100 CT1100 1205
1217akcppxa MACH_AKCPPXA AKCPPXA 1206
1218zevio_1020 MACH_ZEVIO_1020 ZEVIO_1020 1207
1219hitrack MACH_HITRACK HITRACK 1208
1220syme1 MACH_SYME1 SYME1 1209
1221syhl1 MACH_SYHL1 SYHL1 1210
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 9e3e2a69c03a..fd5475071acc 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -80,12 +80,38 @@ static int amba_resume(struct device *dev)
80 return ret; 80 return ret;
81} 81}
82 82
83#define amba_attr_func(name,fmt,arg...) \
84static ssize_t name##_show(struct device *_dev, \
85 struct device_attribute *attr, char *buf) \
86{ \
87 struct amba_device *dev = to_amba_device(_dev); \
88 return sprintf(buf, fmt, arg); \
89}
90
91#define amba_attr(name,fmt,arg...) \
92amba_attr_func(name,fmt,arg) \
93static DEVICE_ATTR(name, S_IRUGO, name##_show, NULL)
94
95amba_attr_func(id, "%08x\n", dev->periphid);
96amba_attr(irq0, "%u\n", dev->irq[0]);
97amba_attr(irq1, "%u\n", dev->irq[1]);
98amba_attr_func(resource, "\t%016llx\t%016llx\t%016lx\n",
99 (unsigned long long)dev->res.start, (unsigned long long)dev->res.end,
100 dev->res.flags);
101
102static struct device_attribute amba_dev_attrs[] = {
103 __ATTR_RO(id),
104 __ATTR_RO(resource),
105 __ATTR_NULL,
106};
107
83/* 108/*
84 * Primecells are part of the Advanced Microcontroller Bus Architecture, 109 * Primecells are part of the Advanced Microcontroller Bus Architecture,
85 * so we call the bus "amba". 110 * so we call the bus "amba".
86 */ 111 */
87static struct bus_type amba_bustype = { 112static struct bus_type amba_bustype = {
88 .name = "amba", 113 .name = "amba",
114 .dev_attrs = amba_dev_attrs,
89 .match = amba_match, 115 .match = amba_match,
90 .uevent = amba_uevent, 116 .uevent = amba_uevent,
91 .suspend = amba_suspend, 117 .suspend = amba_suspend,
@@ -169,21 +195,6 @@ static void amba_device_release(struct device *dev)
169 kfree(d); 195 kfree(d);
170} 196}
171 197
172#define amba_attr(name,fmt,arg...) \
173static ssize_t show_##name(struct device *_dev, struct device_attribute *attr, char *buf) \
174{ \
175 struct amba_device *dev = to_amba_device(_dev); \
176 return sprintf(buf, fmt, arg); \
177} \
178static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
179
180amba_attr(id, "%08x\n", dev->periphid);
181amba_attr(irq0, "%u\n", dev->irq[0]);
182amba_attr(irq1, "%u\n", dev->irq[1]);
183amba_attr(resource, "\t%016llx\t%016llx\t%016lx\n",
184 (unsigned long long)dev->res.start, (unsigned long long)dev->res.end,
185 dev->res.flags);
186
187/** 198/**
188 * amba_device_register - register an AMBA device 199 * amba_device_register - register an AMBA device
189 * @dev: AMBA device to register 200 * @dev: AMBA device to register
@@ -208,40 +219,46 @@ int amba_device_register(struct amba_device *dev, struct resource *parent)
208 dev_warn(&dev->dev, "coherent dma mask is unset\n"); 219 dev_warn(&dev->dev, "coherent dma mask is unset\n");
209 220
210 ret = request_resource(parent, &dev->res); 221 ret = request_resource(parent, &dev->res);
211 if (ret == 0) { 222 if (ret)
212 tmp = ioremap(dev->res.start, SZ_4K); 223 goto err_out;
213 if (!tmp) { 224
214 ret = -ENOMEM; 225 tmp = ioremap(dev->res.start, SZ_4K);
215 goto out; 226 if (!tmp) {
216 } 227 ret = -ENOMEM;
217 228 goto err_release;
218 for (pid = 0, i = 0; i < 4; i++)
219 pid |= (readl(tmp + 0xfe0 + 4 * i) & 255) << (i * 8);
220 for (cid = 0, i = 0; i < 4; i++)
221 cid |= (readl(tmp + 0xff0 + 4 * i) & 255) << (i * 8);
222
223 iounmap(tmp);
224
225 if (cid == 0xb105f00d)
226 dev->periphid = pid;
227
228 if (dev->periphid)
229 ret = device_register(&dev->dev);
230 else
231 ret = -ENODEV;
232
233 if (ret == 0) {
234 device_create_file(&dev->dev, &dev_attr_id);
235 if (dev->irq[0] != NO_IRQ)
236 device_create_file(&dev->dev, &dev_attr_irq0);
237 if (dev->irq[1] != NO_IRQ)
238 device_create_file(&dev->dev, &dev_attr_irq1);
239 device_create_file(&dev->dev, &dev_attr_resource);
240 } else {
241 out:
242 release_resource(&dev->res);
243 }
244 } 229 }
230
231 for (pid = 0, i = 0; i < 4; i++)
232 pid |= (readl(tmp + 0xfe0 + 4 * i) & 255) << (i * 8);
233 for (cid = 0, i = 0; i < 4; i++)
234 cid |= (readl(tmp + 0xff0 + 4 * i) & 255) << (i * 8);
235
236 iounmap(tmp);
237
238 if (cid == 0xb105f00d)
239 dev->periphid = pid;
240
241 if (!dev->periphid) {
242 ret = -ENODEV;
243 goto err_release;
244 }
245
246 ret = device_register(&dev->dev);
247 if (ret)
248 goto err_release;
249
250 if (dev->irq[0] != NO_IRQ)
251 ret = device_create_file(&dev->dev, &dev_attr_irq0);
252 if (ret == 0 && dev->irq[1] != NO_IRQ)
253 ret = device_create_file(&dev->dev, &dev_attr_irq1);
254 if (ret == 0)
255 return ret;
256
257 device_unregister(&dev->dev);
258
259 err_release:
260 release_resource(&dev->res);
261 err_out:
245 return ret; 262 return ret;
246} 263}
247 264
diff --git a/drivers/char/watchdog/at91rm9200_wdt.c b/drivers/char/watchdog/at91rm9200_wdt.c
index 4e7a1145e78f..cb86967e2c5f 100644
--- a/drivers/char/watchdog/at91rm9200_wdt.c
+++ b/drivers/char/watchdog/at91rm9200_wdt.c
@@ -21,6 +21,7 @@
21#include <linux/watchdog.h> 21#include <linux/watchdog.h>
22#include <asm/bitops.h> 22#include <asm/bitops.h>
23#include <asm/uaccess.h> 23#include <asm/uaccess.h>
24#include <asm/arch/at91_st.h>
24 25
25 26
26#define WDT_DEFAULT_TIME 5 /* seconds */ 27#define WDT_DEFAULT_TIME 5 /* seconds */
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 510816c16da3..5cbf8b9d5141 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -195,11 +195,11 @@ config I2C_IBM_IIC
195 will be called i2c-ibm_iic. 195 will be called i2c-ibm_iic.
196 196
197config I2C_IOP3XX 197config I2C_IOP3XX
198 tristate "Intel IOP3xx and IXP4xx on-chip I2C interface" 198 tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface"
199 depends on (ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX) && I2C 199 depends on (ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX) && I2C
200 help 200 help
201 Say Y here if you want to use the IIC bus controller on 201 Say Y here if you want to use the IIC bus controller on
202 the Intel IOP3xx I/O Processors or IXP4xx Network Processors. 202 the Intel IOPx3xx I/O Processors or IXP4xx Network Processors.
203 203
204 This driver can also be built as a module. If so, the module 204 This driver can also be built as a module. If so, the module
205 will be called i2c-iop3xx. 205 will be called i2c-iop3xx.
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index c95a6c154165..c3b1567c852a 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -358,133 +358,6 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
358 358
359#ifdef CONFIG_I2C_PXA_SLAVE 359#ifdef CONFIG_I2C_PXA_SLAVE
360/* 360/*
361 * I2C EEPROM emulation.
362 */
363static struct i2c_eeprom_emu eeprom = {
364 .size = I2C_EEPROM_EMU_SIZE,
365 .watch = LIST_HEAD_INIT(eeprom.watch),
366};
367
368struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void)
369{
370 return &eeprom;
371}
372
373int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *emu, void *data,
374 unsigned int addr, unsigned int size,
375 struct i2c_eeprom_emu_watcher *watcher)
376{
377 struct i2c_eeprom_emu_watch *watch;
378 unsigned long flags;
379
380 if (addr + size > emu->size)
381 return -EINVAL;
382
383 watch = kmalloc(sizeof(struct i2c_eeprom_emu_watch), GFP_KERNEL);
384 if (watch) {
385 watch->start = addr;
386 watch->end = addr + size - 1;
387 watch->ops = watcher;
388 watch->data = data;
389
390 local_irq_save(flags);
391 list_add(&watch->node, &emu->watch);
392 local_irq_restore(flags);
393 }
394
395 return watch ? 0 : -ENOMEM;
396}
397
398void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *emu, void *data,
399 struct i2c_eeprom_emu_watcher *watcher)
400{
401 struct i2c_eeprom_emu_watch *watch, *n;
402 unsigned long flags;
403
404 list_for_each_entry_safe(watch, n, &emu->watch, node) {
405 if (watch->ops == watcher && watch->data == data) {
406 local_irq_save(flags);
407 list_del(&watch->node);
408 local_irq_restore(flags);
409 kfree(watch);
410 }
411 }
412}
413
414static void i2c_eeprom_emu_event(void *ptr, i2c_slave_event_t event)
415{
416 struct i2c_eeprom_emu *emu = ptr;
417
418 eedbg(3, "i2c_eeprom_emu_event: %d\n", event);
419
420 switch (event) {
421 case I2C_SLAVE_EVENT_START_WRITE:
422 emu->seen_start = 1;
423 eedbg(2, "i2c_eeprom: write initiated\n");
424 break;
425
426 case I2C_SLAVE_EVENT_START_READ:
427 emu->seen_start = 0;
428 eedbg(2, "i2c_eeprom: read initiated\n");
429 break;
430
431 case I2C_SLAVE_EVENT_STOP:
432 emu->seen_start = 0;
433 eedbg(2, "i2c_eeprom: received stop\n");
434 break;
435
436 default:
437 eedbg(0, "i2c_eeprom: unhandled event\n");
438 break;
439 }
440}
441
442static int i2c_eeprom_emu_read(void *ptr)
443{
444 struct i2c_eeprom_emu *emu = ptr;
445 int ret;
446
447 ret = emu->bytes[emu->ptr];
448 emu->ptr = (emu->ptr + 1) % emu->size;
449
450 return ret;
451}
452
453static void i2c_eeprom_emu_write(void *ptr, unsigned int val)
454{
455 struct i2c_eeprom_emu *emu = ptr;
456 struct i2c_eeprom_emu_watch *watch;
457
458 if (emu->seen_start != 0) {
459 eedbg(2, "i2c_eeprom_emu_write: setting ptr %02x\n", val);
460 emu->ptr = val;
461 emu->seen_start = 0;
462 return;
463 }
464
465 emu->bytes[emu->ptr] = val;
466
467 eedbg(1, "i2c_eeprom_emu_write: ptr=0x%02x, val=0x%02x\n",
468 emu->ptr, val);
469
470 list_for_each_entry(watch, &emu->watch, node) {
471 if (!watch->ops || !watch->ops->write)
472 continue;
473 if (watch->start <= emu->ptr && watch->end >= emu->ptr)
474 watch->ops->write(watch->data, emu->ptr, val);
475 }
476
477 emu->ptr = (emu->ptr + 1) % emu->size;
478}
479
480struct i2c_slave_client eeprom_client = {
481 .data = &eeprom,
482 .event = i2c_eeprom_emu_event,
483 .read = i2c_eeprom_emu_read,
484 .write = i2c_eeprom_emu_write
485};
486
487/*
488 * PXA I2C Slave mode 361 * PXA I2C Slave mode
489 */ 362 */
490 363
@@ -963,11 +836,9 @@ static int i2c_pxa_probe(struct platform_device *dev)
963 i2c->slave_addr = I2C_PXA_SLAVE_ADDR; 836 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
964 837
965#ifdef CONFIG_I2C_PXA_SLAVE 838#ifdef CONFIG_I2C_PXA_SLAVE
966 i2c->slave = &eeprom_client;
967 if (plat) { 839 if (plat) {
968 i2c->slave_addr = plat->slave_addr; 840 i2c->slave_addr = plat->slave_addr;
969 if (plat->slave) 841 i2c->slave = plat->slave;
970 i2c->slave = plat->slave;
971 } 842 }
972#endif 843#endif
973 844
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index ea41852ec8cd..fbef8da60043 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -91,11 +91,11 @@ config MMC_AU1X
91 91
92 If unsure, say N. 92 If unsure, say N.
93 93
94config MMC_AT91RM9200 94config MMC_AT91
95 tristate "AT91RM9200 SD/MMC Card Interface support" 95 tristate "AT91 SD/MMC Card Interface support"
96 depends on ARCH_AT91RM9200 && MMC 96 depends on ARCH_AT91 && MMC
97 help 97 help
98 This selects the AT91RM9200 MCI controller. 98 This selects the AT91 MCI controller.
99 99
100 If unsure, say N. 100 If unsure, say N.
101 101
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index acfd4de0aba5..83ffb9326a54 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_MMC_SDHCI) += sdhci.o
22obj-$(CONFIG_MMC_WBSD) += wbsd.o 22obj-$(CONFIG_MMC_WBSD) += wbsd.o
23obj-$(CONFIG_MMC_AU1X) += au1xmmc.o 23obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
24obj-$(CONFIG_MMC_OMAP) += omap.o 24obj-$(CONFIG_MMC_OMAP) += omap.o
25obj-$(CONFIG_MMC_AT91RM9200) += at91_mci.o 25obj-$(CONFIG_MMC_AT91) += at91_mci.o
26obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o 26obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
27 27
28mmc_core-y := mmc.o mmc_sysfs.o 28mmc_core-y := mmc.o mmc_sysfs.o
diff --git a/drivers/mmc/at91_mci.c b/drivers/mmc/at91_mci.c
index 494b23fb0a01..41761f7189a6 100644
--- a/drivers/mmc/at91_mci.c
+++ b/drivers/mmc/at91_mci.c
@@ -73,8 +73,8 @@
73#include <asm/mach/mmc.h> 73#include <asm/mach/mmc.h>
74#include <asm/arch/board.h> 74#include <asm/arch/board.h>
75#include <asm/arch/gpio.h> 75#include <asm/arch/gpio.h>
76#include <asm/arch/at91rm9200_mci.h> 76#include <asm/arch/at91_mci.h>
77#include <asm/arch/at91rm9200_pdc.h> 77#include <asm/arch/at91_pdc.h>
78 78
79#define DRIVER_NAME "at91_mci" 79#define DRIVER_NAME "at91_mci"
80 80
diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c
index 3bcb7dc32995..697966703512 100644
--- a/drivers/pcmcia/at91_cf.c
+++ b/drivers/pcmcia/at91_cf.c
@@ -23,9 +23,9 @@
23#include <asm/io.h> 23#include <asm/io.h>
24#include <asm/sizes.h> 24#include <asm/sizes.h>
25 25
26#include <asm/arch/at91rm9200.h>
27#include <asm/arch/board.h> 26#include <asm/arch/board.h>
28#include <asm/arch/gpio.h> 27#include <asm/arch/gpio.h>
28#include <asm/arch/at91rm9200_mc.h>
29 29
30 30
31/* 31/*
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
index 391a1f4167a4..9217ee6c7865 100644
--- a/drivers/serial/atmel_serial.c
+++ b/drivers/serial/atmel_serial.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/char/at91_serial.c 2 * linux/drivers/char/atmel_serial.c
3 * 3 *
4 * Driver for Atmel AT91 / AT32 Serial ports 4 * Driver for Atmel AT91 / AT32 Serial ports
5 * Copyright (C) 2003 Rick Bronson 5 * Copyright (C) 2003 Rick Bronson
@@ -36,11 +36,11 @@
36 36
37#include <asm/io.h> 37#include <asm/io.h>
38 38
39#include <asm/arch/at91rm9200_pdc.h>
40#include <asm/mach/serial_at91.h> 39#include <asm/mach/serial_at91.h>
41#include <asm/arch/board.h> 40#include <asm/arch/board.h>
41#include <asm/arch/at91_pdc.h>
42#ifdef CONFIG_ARM 42#ifdef CONFIG_ARM
43#include <asm/arch/system.h> 43#include <asm/arch/cpu.h>
44#include <asm/arch/gpio.h> 44#include <asm/arch/gpio.h>
45#endif 45#endif
46 46
@@ -137,8 +137,8 @@ static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
137 unsigned int control = 0; 137 unsigned int control = 0;
138 unsigned int mode; 138 unsigned int mode;
139 139
140#ifdef CONFIG_ARM 140#ifdef CONFIG_ARCH_AT91RM9200
141 if (arch_identify() == ARCH_ID_AT91RM9200) { 141 if (cpu_is_at91rm9200()) {
142 /* 142 /*
143 * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21. 143 * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
144 * We need to drive the pin manually. 144 * We need to drive the pin manually.
diff --git a/drivers/serial/atmel_serial.h b/drivers/serial/atmel_serial.h
index eced2ad1a8d9..fe1763b2a6d5 100644
--- a/drivers/serial/atmel_serial.h
+++ b/drivers/serial/atmel_serial.h
@@ -31,8 +31,8 @@
31#define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */ 31#define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */
32#define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */ 32#define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
33#define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */ 33#define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */
34#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable */ 34#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */
35#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable */ 35#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */
36#define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */ 36#define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */
37#define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */ 37#define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */
38 38
@@ -92,9 +92,9 @@
92#define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */ 92#define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
93#define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */ 93#define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */
94#define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */ 94#define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */
95#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change */ 95#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */
96#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change */ 96#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */
97#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change */ 97#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */
98#define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */ 98#define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */
99#define ATMEL_US_RI (1 << 20) /* RI */ 99#define ATMEL_US_RI (1 << 20) /* RI */
100#define ATMEL_US_DSR (1 << 21) /* DSR */ 100#define ATMEL_US_DSR (1 << 21) /* DSR */
@@ -106,6 +106,7 @@
106#define ATMEL_US_CSR 0x14 /* Channel Status Register */ 106#define ATMEL_US_CSR 0x14 /* Channel Status Register */
107#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */ 107#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
108#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */ 108#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
109#define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [SAM9 only] */
109 110
110#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */ 111#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
111#define ATMEL_US_CD (0xffff << 0) /* Clock Divider */ 112#define ATMEL_US_CD (0xffff << 0) /* Clock Divider */
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index f9b1719b9a37..9980a4ddfed9 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -24,7 +24,7 @@ config USB_ARCH_HAS_OHCI
24 default y if ARCH_S3C2410 24 default y if ARCH_S3C2410
25 default y if PXA27x 25 default y if PXA27x
26 default y if ARCH_EP93XX 26 default y if ARCH_EP93XX
27 default y if (ARCH_AT91RM9200 || ARCH_AT91SAM9261) 27 default y if ARCH_AT91
28 default y if ARCH_PNX4008 28 default y if ARCH_PNX4008
29 # PPC: 29 # PPC:
30 default y if STB03xxx 30 default y if STB03xxx
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index bbbc82a8336a..4097a86c4b5e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -189,7 +189,7 @@ config USB_OTG
189 189
190config USB_GADGET_AT91 190config USB_GADGET_AT91
191 boolean "AT91 USB Device Port" 191 boolean "AT91 USB Device Port"
192 depends on ARCH_AT91RM9200 192 depends on ARCH_AT91
193 select USB_GADGET_SELECTED 193 select USB_GADGET_SELECTED
194 help 194 help
195 Many Atmel AT91 processors (such as the AT91RM2000) have a 195 Many Atmel AT91 processors (such as the AT91RM2000) have a
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index ea4714e557e4..4776b3bdf9c8 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -935,7 +935,7 @@ MODULE_LICENSE ("GPL");
935#include "ohci-ppc-soc.c" 935#include "ohci-ppc-soc.c"
936#endif 936#endif
937 937
938#if defined(CONFIG_ARCH_AT91RM9200) || defined(CONFIG_ARCH_AT91SAM9261) 938#ifdef CONFIG_ARCH_AT91
939#include "ohci-at91.c" 939#include "ohci-at91.c"
940#endif 940#endif
941 941
@@ -952,8 +952,7 @@ MODULE_LICENSE ("GPL");
952 || defined (CONFIG_ARCH_EP93XX) \ 952 || defined (CONFIG_ARCH_EP93XX) \
953 || defined (CONFIG_SOC_AU1X00) \ 953 || defined (CONFIG_SOC_AU1X00) \
954 || defined (CONFIG_USB_OHCI_HCD_PPC_SOC) \ 954 || defined (CONFIG_USB_OHCI_HCD_PPC_SOC) \
955 || defined (CONFIG_ARCH_AT91RM9200) \ 955 || defined (CONFIG_ARCH_AT91) \
956 || defined (CONFIG_ARCH_AT91SAM9261) \
957 || defined (CONFIG_ARCH_PNX4008) \ 956 || defined (CONFIG_ARCH_PNX4008) \
958 ) 957 )
959#error "missing bus glue for ohci-hcd" 958#error "missing bus glue for ohci-hcd"
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
index 24b51cccde8f..9eceb4148922 100644
--- a/include/asm-arm/arch-aaec2000/memory.h
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -17,8 +17,6 @@
17#define __virt_to_bus(x) __virt_to_phys(x) 17#define __virt_to_bus(x) __virt_to_phys(x)
18#define __bus_to_virt(x) __phys_to_virt(x) 18#define __bus_to_virt(x) __phys_to_virt(x)
19 19
20#ifdef CONFIG_DISCONTIGMEM
21
22/* 20/*
23 * The nodes are the followings: 21 * The nodes are the followings:
24 * 22 *
@@ -27,42 +25,6 @@
27 * node 2: 0xf800.0000 - 0xfbff.ffff 25 * node 2: 0xf800.0000 - 0xfbff.ffff
28 * node 3: 0xfc00.0000 - 0xffff.ffff 26 * node 3: 0xfc00.0000 - 0xffff.ffff
29 */ 27 */
30 28#define NODE_MEM_SIZE_BITS 26
31/*
32 * Given a kernel address, find the home node of the underlying memory.
33 */
34#define KVADDR_TO_NID(addr) \
35 (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
36
37/*
38 * Given a page frame number, convert it to a node id.
39 */
40#define PFN_TO_NID(pfn) \
41 (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
42
43/*
44 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
45 * and return the mem_map of that node.
46 */
47#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
48
49/*
50 * Given a page frame number, find the owning node of the memory
51 * and return the mem_map of that node.
52 */
53#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
54
55/*
56 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
57 * and returns the index corresponding to the appropriate page in the
58 * node's mem_map.
59 */
60#define LOCAL_MAP_NR(addr) \
61 (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
62
63#define NODE_MAX_MEM_SHIFT 26
64#define NODE_MAX_MEM_SIZE (1 << NODE_MAX_MEM_SHIFT)
65
66#endif /* CONFIG_DISCONTIGMEM */
67 29
68#endif /* __ASM_ARCH_MEMORY_H */ 30#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/include/asm-arm/arch-at91rm9200/at91_aic.h b/include/asm-arm/arch-at91rm9200/at91_aic.h
new file mode 100644
index 000000000000..267e69812e26
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_aic.h
@@ -0,0 +1,53 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_aic.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Advanced Interrupt Controller (AIC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_AIC_H
17#define AT91_AIC_H
18
19#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
20#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
21#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
22#define AT91_AIC_SRCTYPE_LOW (0 << 5)
23#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
24#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
25#define AT91_AIC_SRCTYPE_RISING (3 << 5)
26
27#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
28#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
29#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
30#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
31#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
32
33#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
34#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
35#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
36#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
37#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
38
39#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
40#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
41#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
42#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
43#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
44#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
45#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
46#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
47#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
48
49#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
50#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
51#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
52
53#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_dbgu.h b/include/asm-arm/arch-at91rm9200/at91_dbgu.h
new file mode 100644
index 000000000000..e4b8b27acfca
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_dbgu.h
@@ -0,0 +1,45 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_dbgu.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Debug Unit (DBGU) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_DBGU_H
17#define AT91_DBGU_H
18
19#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
20#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
21#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
22#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
23#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
24#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
25#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
26#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
27#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
28#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
29#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
30
31#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
32#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
33#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
34#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
35#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
36#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
37#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
38#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
39#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
40#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
41
42#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
43#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
44
45#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_ecc.h b/include/asm-arm/arch-at91rm9200/at91_ecc.h
new file mode 100644
index 000000000000..fddf256a98d3
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_ecc.h
@@ -0,0 +1,38 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_ecc.h
3 *
4 * Error Corrected Code Controller (ECC) - System peripherals regsters.
5 * Based on AT91SAM9260 datasheet revision B.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef AT91_ECC_H
14#define AT91_ECC_H
15
16#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */
17#define AT91_ECC_RST (1 << 0) /* Reset parity */
18
19#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */
20#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
21#define AT91_ECC_PAGESIZE_528 (0)
22#define AT91_ECC_PAGESIZE_1056 (1)
23#define AT91_ECC_PAGESIZE_2112 (2)
24#define AT91_ECC_PAGESIZE_4224 (3)
25
26#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */
27#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
28#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
29#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
30
31#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */
32#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
33#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
34
35#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */
36#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
37
38#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_lcdc.h b/include/asm-arm/arch-at91rm9200/at91_lcdc.h
new file mode 100644
index 000000000000..9cbfcdd3c471
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_lcdc.h
@@ -0,0 +1,148 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_lcdc.h
3 *
4 * LCD Controller (LCDC).
5 * Based on AT91SAM9261 datasheet revision E.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91_LCDC_H
14#define AT91_LCDC_H
15
16#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */
17#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */
18#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */
19#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */
20#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */
21#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */
22
23#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */
24#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */
25#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */
26
27#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */
28#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */
29#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */
30#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */
31
32#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */
33#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */
34#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */
35#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */
36
37#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */
38#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */
39#define AT91_LCDC_DISTYPE_STNMONO (0 << 0)
40#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0)
41#define AT91_LCDC_DISTYPE_TFT (2 << 0)
42#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */
43#define AT91_LCDC_SCANMOD_SINGLE (0 << 2)
44#define AT91_LCDC_SCANMOD_DUAL (1 << 2)
45#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */
46#define AT91_LCDC_IFWIDTH_4 (0 << 3)
47#define AT91_LCDC_IFWIDTH_8 (1 << 3)
48#define AT91_LCDC_IFWIDTH_16 (2 << 3)
49#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */
50#define AT91_LCDC_PIXELSIZE_1 (0 << 5)
51#define AT91_LCDC_PIXELSIZE_2 (1 << 5)
52#define AT91_LCDC_PIXELSIZE_4 (2 << 5)
53#define AT91_LCDC_PIXELSIZE_8 (3 << 5)
54#define AT91_LCDC_PIXELSIZE_16 (4 << 5)
55#define AT91_LCDC_PIXELSIZE_24 (5 << 5)
56#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */
57#define AT91_LCDC_INVVD_NORMAL (0 << 8)
58#define AT91_LCDC_INVVD_INVERTED (1 << 8)
59#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */
60#define AT91_LCDC_INVFRAME_NORMAL (0 << 9)
61#define AT91_LCDC_INVFRAME_INVERTED (1 << 9)
62#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */
63#define AT91_LCDC_INVLINE_NORMAL (0 << 10)
64#define AT91_LCDC_INVLINE_INVERTED (1 << 10)
65#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */
66#define AT91_LCDC_INVCLK_NORMAL (0 << 11)
67#define AT91_LCDC_INVCLK_INVERTED (1 << 11)
68#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */
69#define AT91_LCDC_INVDVAL_NORMAL (0 << 12)
70#define AT91_LCDC_INVDVAL_INVERTED (1 << 12)
71#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */
72#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
73#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
74#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */
75#define AT91_LCDC_MEMOR_BIG (0 << 31)
76#define AT91_LCDC_MEMOR_LITTLE (1 << 31)
77
78#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */
79#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */
80#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */
81#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */
82#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */
83
84#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */
85#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */
86#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */
87#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */
88
89#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */
90#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */
91#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */
92
93#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */
94#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */
95
96#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */
97#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */
98#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */
99#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */
100#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */
101#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */
102#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */
103#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */
104#define AT91_LCDC_DP1_2_VAL (0xff)
105#define AT91_LCDC_DP4_7_VAL (0xfffffff)
106#define AT91_LCDC_DP3_5_VAL (0xfffff)
107#define AT91_LCDC_DP2_3_VAL (0xfff)
108#define AT91_LCDC_DP5_7_VAL (0xfffffff)
109#define AT91_LCDC_DP3_4_VAL (0xffff)
110#define AT91_LCDC_DP4_5_VAL (0xfffff)
111#define AT91_LCDC_DP6_7_VAL (0xfffffff)
112
113#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */
114#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */
115#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */
116#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */
117
118#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */
119#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */
120#define AT91_LCDC_PS_DIV1 (0 << 0)
121#define AT91_LCDC_PS_DIV2 (1 << 0)
122#define AT91_LCDC_PS_DIV4 (2 << 0)
123#define AT91_LCDC_PS_DIV8 (3 << 0)
124#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */
125#define AT91_LCDC_POL_NEGATIVE (0 << 2)
126#define AT91_LCDC_POL_POSITIVE (1 << 2)
127#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */
128#define AT91_LCDC_ENA_PWMDISABLE (0 << 3)
129#define AT91_LCDC_ENA_PWMENABLE (1 << 3)
130
131#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */
132#define AT91_LCDC_CVAL (0xff) /* PWM compare value */
133
134#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */
135#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */
136#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */
137#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */
138#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */
139#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */
140#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */
141#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */
142#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */
143#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */
144#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */
145
146#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */
147
148#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h b/include/asm-arm/arch-at91rm9200/at91_mci.h
index f28636d61e39..9a552cb743c0 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
+++ b/include/asm-arm/arch-at91rm9200/at91_mci.h
@@ -1,11 +1,11 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_mci.h 2 * include/asm-arm/arch-at91rm9200/at91_mci.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
6 * 6 *
7 * MultiMedia Card Interface (MCI) registers. 7 * MultiMedia Card Interface (MCI) registers.
8 * Based on AT91RM9200 datasheet revision E. 8 * Based on AT91RM9200 datasheet revision F.
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 11 * it under the terms of the GNU General Public License as published by
@@ -13,8 +13,8 @@
13 * (at your option) any later version. 13 * (at your option) any later version.
14 */ 14 */
15 15
16#ifndef AT91RM9200_MCI_H 16#ifndef AT91_MCI_H
17#define AT91RM9200_MCI_H 17#define AT91_MCI_H
18 18
19#define AT91_MCI_CR 0x00 /* Control Register */ 19#define AT91_MCI_CR 0x00 /* Control Register */
20#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ 20#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
@@ -25,10 +25,10 @@
25 25
26#define AT91_MCI_MR 0x04 /* Mode Register */ 26#define AT91_MCI_MR 0x04 /* Mode Register */
27#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ 27#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
28#define AT91_MCI_PWSDIV (3 << 8) /* Power Saving Divider */ 28#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
29#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ 29#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
30#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ 30#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
31#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ 31#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
32 32
33#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ 33#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
34#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ 34#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
@@ -43,8 +43,8 @@
43#define AT91_MCI_DTOMUL_1M (7 << 4) 43#define AT91_MCI_DTOMUL_1M (7 << 4)
44 44
45#define AT91_MCI_SDCR 0x0c /* SD Card Register */ 45#define AT91_MCI_SDCR 0x0c /* SD Card Register */
46#define AT91_MCI_SDCSEL (0xf << 0) /* SD Card Selector */ 46#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
47#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ 47#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
48 48
49#define AT91_MCI_ARGR 0x10 /* Argument Register */ 49#define AT91_MCI_ARGR 0x10 /* Argument Register */
50 50
@@ -78,18 +78,20 @@
78 78
79#define AT91_MCI_SR 0x40 /* Status Register */ 79#define AT91_MCI_SR 0x40 /* Status Register */
80#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ 80#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */
81#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ 81#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
82#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ 82#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */
83#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ 83#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */
84#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ 84#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */
85#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ 85#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */
86#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ 86#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
87#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ 87#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
88#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
89#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */
88#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ 90#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
89#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ 91#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
90#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ 92#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
91#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ 93#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
92#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ 94#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
93#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ 95#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
94#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ 96#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */
95#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ 97#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */
diff --git a/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h b/include/asm-arm/arch-at91rm9200/at91_pdc.h
index ce1150d4438d..79d6e02fa45e 100644
--- a/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_pdc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h 2 * include/asm-arm/arch-at91rm9200/at91_pdc.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
@@ -13,8 +13,8 @@
13 * (at your option) any later version. 13 * (at your option) any later version.
14 */ 14 */
15 15
16#ifndef AT91RM9200_PDC_H 16#ifndef AT91_PDC_H
17#define AT91RM9200_PDC_H 17#define AT91_PDC_H
18 18
19#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ 19#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
20#define AT91_PDC_RCR 0x104 /* Receive Counter Register */ 20#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
diff --git a/include/asm-arm/arch-at91rm9200/at91_pio.h b/include/asm-arm/arch-at91rm9200/at91_pio.h
new file mode 100644
index 000000000000..680eaa1f5915
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_pio.h
@@ -0,0 +1,49 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_pio.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Parallel I/O Controller (PIO) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_PIO_H
17#define AT91_PIO_H
18
19#define PIO_PER 0x00 /* Enable Register */
20#define PIO_PDR 0x04 /* Disable Register */
21#define PIO_PSR 0x08 /* Status Register */
22#define PIO_OER 0x10 /* Output Enable Register */
23#define PIO_ODR 0x14 /* Output Disable Register */
24#define PIO_OSR 0x18 /* Output Status Register */
25#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
26#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
27#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
28#define PIO_SODR 0x30 /* Set Output Data Register */
29#define PIO_CODR 0x34 /* Clear Output Data Register */
30#define PIO_ODSR 0x38 /* Output Data Status Register */
31#define PIO_PDSR 0x3c /* Pin Data Status Register */
32#define PIO_IER 0x40 /* Interrupt Enable Register */
33#define PIO_IDR 0x44 /* Interrupt Disable Register */
34#define PIO_IMR 0x48 /* Interrupt Mask Register */
35#define PIO_ISR 0x4c /* Interrupt Status Register */
36#define PIO_MDER 0x50 /* Multi-driver Enable Register */
37#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
38#define PIO_MDSR 0x58 /* Multi-driver Status Register */
39#define PIO_PUDR 0x60 /* Pull-up Disable Register */
40#define PIO_PUER 0x64 /* Pull-up Enable Register */
41#define PIO_PUSR 0x68 /* Pull-up Status Register */
42#define PIO_ASR 0x70 /* Peripheral A Select Register */
43#define PIO_BSR 0x74 /* Peripheral B Select Register */
44#define PIO_ABSR 0x78 /* AB Status Register */
45#define PIO_OWER 0xa0 /* Output Write Enable Register */
46#define PIO_OWDR 0xa4 /* Output Write Disable Register */
47#define PIO_OWSR 0xa8 /* Output Write Status Register */
48
49#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_pit.h b/include/asm-arm/arch-at91rm9200/at91_pit.h
new file mode 100644
index 000000000000..4a30d009c588
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_pit.h
@@ -0,0 +1,29 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_pit.h
3 *
4 * Periodic Interval Timer (PIT) - System peripherals regsters.
5 * Based on AT91SAM9261 datasheet revision D.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91_PIT_H
14#define AT91_PIT_H
15
16#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
17#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
18#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
19#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
20
21#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
22#define AT91_PIT_PITS (1 << 0) /* Timer Status */
23
24#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
25#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
26#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
27#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
28
29#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_pmc.h b/include/asm-arm/arch-at91rm9200/at91_pmc.h
new file mode 100644
index 000000000000..de8c3da74a01
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_pmc.h
@@ -0,0 +1,92 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_pmc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Power Management Controller (PMC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_PMC_H
17#define AT91_PMC_H
18
19#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
20#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
21
22#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
23#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
24#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
25#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
26#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
27#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
28#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
29#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
30#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
31#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
32#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
33#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
34#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
35
36#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
37#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
38#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
39
40#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
41#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
42#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
43#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
44
45#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
46#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
47#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
48
49#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
50#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
51#define AT91_PMC_DIV (0xff << 0) /* Divider */
52#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
53#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
54#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
55#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
56
57#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
58#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
59#define AT91_PMC_CSS_SLOW (0 << 0)
60#define AT91_PMC_CSS_MAIN (1 << 0)
61#define AT91_PMC_CSS_PLLA (2 << 0)
62#define AT91_PMC_CSS_PLLB (3 << 0)
63#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
64#define AT91_PMC_PRES_1 (0 << 2)
65#define AT91_PMC_PRES_2 (1 << 2)
66#define AT91_PMC_PRES_4 (2 << 2)
67#define AT91_PMC_PRES_8 (3 << 2)
68#define AT91_PMC_PRES_16 (4 << 2)
69#define AT91_PMC_PRES_32 (5 << 2)
70#define AT91_PMC_PRES_64 (6 << 2)
71#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
72#define AT91_PMC_MDIV_1 (0 << 8)
73#define AT91_PMC_MDIV_2 (1 << 8)
74#define AT91_PMC_MDIV_3 (2 << 8)
75#define AT91_PMC_MDIV_4 (3 << 8)
76
77#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
78
79#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
80#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
81#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
82#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
83#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
84#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
85#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
86#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
87#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
88#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
89#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
90#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
91
92#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_rstc.h b/include/asm-arm/arch-at91rm9200/at91_rstc.h
new file mode 100644
index 000000000000..ccdc52da973d
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_rstc.h
@@ -0,0 +1,39 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_rstc.h
3 *
4 * Reset Controller (RSTC) - System peripherals regsters.
5 * Based on AT91SAM9261 datasheet revision D.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91_RSTC_H
14#define AT91_RSTC_H
15
16#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
17#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
18#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
19#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
20#define AT01_RSTC_KEY (0xff << 24) /* KEY Password */
21
22#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
23#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
24#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
25#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
26#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
27#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
28#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
29#define AT91_RSTC_RSTTYP_USER (4 << 8)
30#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
31#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
32
33#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
34#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
35#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
36#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
37#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */
38
39#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtc.h b/include/asm-arm/arch-at91rm9200/at91_rtc.h
new file mode 100644
index 000000000000..6e5065d56260
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_rtc.h
@@ -0,0 +1,75 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_rtc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Real Time Clock (RTC) - System peripheral registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_RTC_H
17#define AT91_RTC_H
18
19#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
20#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
21#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
22#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
23#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
24#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
25#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
26#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
27#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
28#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
29#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
30#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
31
32#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
33#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
34
35#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
36#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
37#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
38#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
39#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
40
41#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
42#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
43#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
44#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
45#define AT91_RTC_DAY (7 << 21) /* Current Day */
46#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
47
48#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
49#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
50#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
51#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
52
53#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
54#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
55#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
56
57#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
58#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
59#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
60#define AT91_RTC_SECEV (1 << 2) /* Second Event */
61#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
62#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
63
64#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
65#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
66#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
67#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
68
69#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
70#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
71#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
72#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
73#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
74
75#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtt.h b/include/asm-arm/arch-at91rm9200/at91_rtt.h
new file mode 100644
index 000000000000..c6751ba3cccc
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_rtt.h
@@ -0,0 +1,32 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_rtt.h
3 *
4 * Real-time Timer (RTT) - System peripherals regsters.
5 * Based on AT91SAM9261 datasheet revision D.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91_RTT_H
14#define AT91_RTT_H
15
16#define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */
17#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
18#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
19#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
20#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
21
22#define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */
23#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
24
25#define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */
26#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
27
28#define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */
29#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
30#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
31
32#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_shdwc.h b/include/asm-arm/arch-at91rm9200/at91_shdwc.h
new file mode 100644
index 000000000000..0439250553c9
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_shdwc.h
@@ -0,0 +1,33 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_shdwc.h
3 *
4 * Shutdown Controller (SHDWC) - System peripherals regsters.
5 * Based on AT91SAM9261 datasheet revision D.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91_SHDWC_H
14#define AT91_SHDWC_H
15
16#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
17#define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */
18#define AT91_SHDW_KEY (0xff << 24) /* KEY Password */
19
20#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
21#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
22#define AT91_SHDW_WKMODE0_NONE 0
23#define AT91_SHDW_WKMODE0_HIGH 1
24#define AT91_SHDW_WKMODE0_LOW 2
25#define AT91_SHDW_WKMODE0_ANYLEVEL 3
26#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
27#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
28
29#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
30#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
31#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
32
33#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h b/include/asm-arm/arch-at91rm9200/at91_spi.h
index bff5ea45f604..bec48ca89bba 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
+++ b/include/asm-arm/arch-at91rm9200/at91_spi.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_spi.h 2 * include/asm-arm/arch-at91rm9200/at91_spi.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
@@ -13,8 +13,8 @@
13 * (at your option) any later version. 13 * (at your option) any later version.
14 */ 14 */
15 15
16#ifndef AT91RM9200_SPI_H 16#ifndef AT91_SPI_H
17#define AT91RM9200_SPI_H 17#define AT91_SPI_H
18 18
19#define AT91_SPI_CR 0x00 /* Control Register */ 19#define AT91_SPI_CR 0x00 /* Control Register */
20#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ 20#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
@@ -28,7 +28,7 @@
28#define AT91_SPI_PS_FIXED (0 << 1) 28#define AT91_SPI_PS_FIXED (0 << 1)
29#define AT91_SPI_PS_VARIABLE (1 << 1) 29#define AT91_SPI_PS_VARIABLE (1 << 1)
30#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ 30#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
31#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection */ 31#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
32#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ 32#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
33#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ 33#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
34#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ 34#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h b/include/asm-arm/arch-at91rm9200/at91_ssc.h
index ac880227147f..694bcaa8f7c2 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_ssc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h 2 * include/asm-arm/arch-at91rm9200/at91_ssc.h
3 * 3 *
4 * Copyright (C) SAN People 4 * Copyright (C) SAN People
5 * 5 *
@@ -12,8 +12,8 @@
12 * (at your option) any later version. 12 * (at your option) any later version.
13 */ 13 */
14 14
15#ifndef AT91RM9200_SSC_H 15#ifndef AT91_SSC_H
16#define AT91RM9200_SSC_H 16#define AT91_SSC_H
17 17
18#define AT91_SSC_CR 0x00 /* Control Register */ 18#define AT91_SSC_CR 0x00 /* Control Register */
19#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ 19#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
@@ -36,6 +36,10 @@
36#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ 36#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
37#define AT91_SSC_CKI_FALLING (0 << 5) 37#define AT91_SSC_CKI_FALLING (0 << 5)
38#define AT91_SSC_CK_RISING (1 << 5) 38#define AT91_SSC_CK_RISING (1 << 5)
39#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */
40#define AT91_SSC_CKG_NONE (0 << 6)
41#define AT91_SSC_CKG_RFLOW (1 << 6)
42#define AT91_SSC_CKG_RFHIGH (2 << 6)
39#define AT91_SSC_START (0xf << 8) /* Start Selection */ 43#define AT91_SSC_START (0xf << 8) /* Start Selection */
40#define AT91_SSC_START_CONTINUOUS (0 << 8) 44#define AT91_SSC_START_CONTINUOUS (0 << 8)
41#define AT91_SSC_START_TX_RX (1 << 8) 45#define AT91_SSC_START_TX_RX (1 << 8)
@@ -45,6 +49,7 @@
45#define AT91_SSC_START_RISING_RF (5 << 8) 49#define AT91_SSC_START_RISING_RF (5 << 8)
46#define AT91_SSC_START_LEVEL_RF (6 << 8) 50#define AT91_SSC_START_LEVEL_RF (6 << 8)
47#define AT91_SSC_START_EDGE_RF (7 << 8) 51#define AT91_SSC_START_EDGE_RF (7 << 8)
52#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */
48#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ 53#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
49#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ 54#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
50 55
@@ -75,6 +80,9 @@
75#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ 80#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
76#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ 81#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
77 82
83#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */
84#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */
85
78#define AT91_SSC_SR 0x40 /* Status Register */ 86#define AT91_SSC_SR 0x40 /* Status Register */
79#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ 87#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
80#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ 88#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
@@ -84,6 +92,8 @@
84#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ 92#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
85#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ 93#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
86#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ 94#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
95#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */
96#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */
87#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ 97#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
88#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ 98#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
89#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ 99#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
diff --git a/include/asm-arm/arch-at91rm9200/at91_st.h b/include/asm-arm/arch-at91rm9200/at91_st.h
new file mode 100644
index 000000000000..2432ddfc6c47
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_st.h
@@ -0,0 +1,49 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_st.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * System Timer (ST) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_ST_H
17#define AT91_ST_H
18
19#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
20#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
21
22#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
23#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
24
25#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
26#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
27#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
28#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
29
30#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
31#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
32
33#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
34#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
35#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
36#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
37#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
38
39#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
40#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
41#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
42
43#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
44#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
45
46#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
47#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
48
49#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h b/include/asm-arm/arch-at91rm9200/at91_tc.h
index f4da752bb0c8..8d06eb078e1d 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_tc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_tc.h 2 * include/asm-arm/arch-at91rm9200/at91_tc.h
3 * 3 *
4 * Copyright (C) SAN People 4 * Copyright (C) SAN People
5 * 5 *
@@ -12,8 +12,8 @@
12 * (at your option) any later version. 12 * (at your option) any later version.
13 */ 13 */
14 14
15#ifndef AT91RM9200_TC_H 15#ifndef AT91_TC_H
16#define AT91RM9200_TC_H 16#define AT91_TC_H
17 17
18#define AT91_TC_BCR 0xc0 /* TC Block Control Register */ 18#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
19#define AT91_TC_SYNC (1 << 0) /* Synchro Command */ 19#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h b/include/asm-arm/arch-at91rm9200/at91_twi.h
index 93547d7482bd..cda914f1e740 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
+++ b/include/asm-arm/arch-at91rm9200/at91_twi.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h 2 * include/asm-arm/arch-at91rm9200/at91_twi.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
@@ -13,8 +13,8 @@
13 * (at your option) any later version. 13 * (at your option) any later version.
14 */ 14 */
15 15
16#ifndef AT91RM9200_TWI_H 16#ifndef AT91_TWI_H
17#define AT91RM9200_TWI_H 17#define AT91_TWI_H
18 18
19#define AT91_TWI_CR 0x00 /* Control Register */ 19#define AT91_TWI_CR 0x00 /* Control Register */
20#define AT91_TWI_START (1 << 0) /* Send a Start Condition */ 20#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
@@ -43,8 +43,8 @@
43#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ 43#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
44#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ 44#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
45#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ 45#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
46#define AT91_TWI_OVRE (1 << 6) /* Overrun Error */ 46#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
47#define AT91_TWI_UNRE (1 << 7) /* Underrun Error */ 47#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
48#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ 48#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
49 49
50#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ 50#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
diff --git a/include/asm-arm/arch-at91rm9200/at91_wdt.h b/include/asm-arm/arch-at91rm9200/at91_wdt.h
new file mode 100644
index 000000000000..ac63e775772c
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91_wdt.h
@@ -0,0 +1,34 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91_wdt.h
3 *
4 * Watchdog Timer (WDT) - System peripherals regsters.
5 * Based on AT91SAM9261 datasheet revision D.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91_WDT_H
14#define AT91_WDT_H
15
16#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
17#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
18#define AT91_WDT_KEY (0xff << 24) /* KEY Password */
19
20#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
21#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
22#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
23#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
24#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
25#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
26#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
27#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
28#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
29
30#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
31#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
32#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
33
34#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
index a5a86b1ff886..4d51177efddd 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -80,6 +80,22 @@
80 80
81 81
82/* 82/*
83 * System Peripherals (offset from AT91_BASE_SYS)
84 */
85#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
86#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
87#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */
88#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */
89#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */
90#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */
91#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
92#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
93#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
94#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
95
96#define AT91_MATRIX 0 /* not supported */
97
98/*
83 * Internal Memory. 99 * Internal Memory.
84 */ 100 */
85#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ 101#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
new file mode 100644
index 000000000000..0c0d81480b3a
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
@@ -0,0 +1,160 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_MC_H
17#define AT91RM9200_MC_H
18
19/* Memory Controller */
20#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
21#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
22
23#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
24#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
25#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
26#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
27#define AT91_MC_ABTSZ_BYTE (0 << 8)
28#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
29#define AT91_MC_ABTSZ_WORD (2 << 8)
30#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
31#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
32#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
33#define AT91_MC_ABTTYP_FETCH (2 << 10)
34#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
35#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
36#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
37#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
38#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
39#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
40#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
41#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
42
43#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
44
45#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
46#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
47#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
48#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
49#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
50
51/* External Bus Interface (EBI) registers */
52#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
53#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
54#define AT91_EBI_CS0A_SMC (0 << 0)
55#define AT91_EBI_CS0A_BFC (1 << 0)
56#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
57#define AT91_EBI_CS1A_SMC (0 << 1)
58#define AT91_EBI_CS1A_SDRAMC (1 << 1)
59#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
60#define AT91_EBI_CS3A_SMC (0 << 3)
61#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
62#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
63#define AT91_EBI_CS4A_SMC (0 << 4)
64#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
65#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
66#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
67
68/* Static Memory Controller (SMC) registers */
69#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
70#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
71#define AT91_SMC_NWS_(x) ((x) << 0)
72#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
73#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
74#define AT91_SMC_TDF_(x) ((x) << 8)
75#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
76#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
77#define AT91_SMC_DBW_16 (1 << 13)
78#define AT91_SMC_DBW_8 (2 << 13)
79#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
80#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
81#define AT91_SMC_ACSS_STD (0 << 16)
82#define AT91_SMC_ACSS_1 (1 << 16)
83#define AT91_SMC_ACSS_2 (2 << 16)
84#define AT91_SMC_ACSS_3 (3 << 16)
85#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
86#define AT91_SMC_RWSETUP_(x) ((x) << 24)
87#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
88#define AT91_SMC_RWHOLD_(x) ((x) << 28)
89
90/* SDRAM Controller registers */
91#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
92#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
93#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
94#define AT91_SDRAMC_MODE_NOP (1 << 0)
95#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
96#define AT91_SDRAMC_MODE_LMR (3 << 0)
97#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
98#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
99#define AT91_SDRAMC_DBW_32 (0 << 4)
100#define AT91_SDRAMC_DBW_16 (1 << 4)
101
102#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
103#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
104
105#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
106#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
107#define AT91_SDRAMC_NC_8 (0 << 0)
108#define AT91_SDRAMC_NC_9 (1 << 0)
109#define AT91_SDRAMC_NC_10 (2 << 0)
110#define AT91_SDRAMC_NC_11 (3 << 0)
111#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
112#define AT91_SDRAMC_NR_11 (0 << 2)
113#define AT91_SDRAMC_NR_12 (1 << 2)
114#define AT91_SDRAMC_NR_13 (2 << 2)
115#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
116#define AT91_SDRAMC_NB_2 (0 << 4)
117#define AT91_SDRAMC_NB_4 (1 << 4)
118#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
119#define AT91_SDRAMC_CAS_2 (2 << 5)
120#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
121#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
122#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
123#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
124#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
125#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
126
127#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
128#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
129#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
130#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
131#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
132#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
133
134/* Burst Flash Controller register */
135#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
136#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
137#define AT91_BFC_BFCOM_DISABLED (0 << 0)
138#define AT91_BFC_BFCOM_ASYNC (1 << 0)
139#define AT91_BFC_BFCOM_BURST (2 << 0)
140#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
141#define AT91_BFC_BFCC_MCK (1 << 2)
142#define AT91_BFC_BFCC_DIV2 (2 << 2)
143#define AT91_BFC_BFCC_DIV4 (3 << 2)
144#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
145#define AT91_BFC_PAGES (7 << 8) /* Page Size */
146#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
147#define AT91_BFC_PAGES_16 (1 << 8)
148#define AT91_BFC_PAGES_32 (2 << 8)
149#define AT91_BFC_PAGES_64 (3 << 8)
150#define AT91_BFC_PAGES_128 (4 << 8)
151#define AT91_BFC_PAGES_256 (5 << 8)
152#define AT91_BFC_PAGES_512 (6 << 8)
153#define AT91_BFC_PAGES_1024 (7 << 8)
154#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
155#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
156#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
157#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
158#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
159
160#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
deleted file mode 100644
index 73693fea76a2..000000000000
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ /dev/null
@@ -1,438 +0,0 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_SYS_H
17#define AT91RM9200_SYS_H
18
19/*
20 * Advanced Interrupt Controller.
21 */
22#define AT91_AIC 0x000
23
24#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
25#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
26#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
27#define AT91_AIC_SRCTYPE_LOW (0 << 5)
28#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
29#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
30#define AT91_AIC_SRCTYPE_RISING (3 << 5)
31
32#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
33#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
34#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
35#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
36#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
37
38#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
39#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
40#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
41#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
42#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
43
44#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
45#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
46#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
47#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
48#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
49#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
50#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
51#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
52#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
53
54
55/*
56 * Debug Unit.
57 */
58#define AT91_DBGU 0x200
59
60#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
61#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
62#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
63#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
64#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
65#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
66#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
67#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
68#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
69#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
70#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
71
72#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
73#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
74#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
75#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
76#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
77#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
78#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
79#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
80#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
81#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
82
83#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
84#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
85#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
86
87/*
88 * PIO Controllers.
89 */
90#define AT91_PIOA 0x400
91#define AT91_PIOB 0x600
92#define AT91_PIOC 0x800
93#define AT91_PIOD 0xa00
94
95#define PIO_PER 0x00 /* Enable Register */
96#define PIO_PDR 0x04 /* Disable Register */
97#define PIO_PSR 0x08 /* Status Register */
98#define PIO_OER 0x10 /* Output Enable Register */
99#define PIO_ODR 0x14 /* Output Disable Register */
100#define PIO_OSR 0x18 /* Output Status Register */
101#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
102#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
103#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
104#define PIO_SODR 0x30 /* Set Output Data Register */
105#define PIO_CODR 0x34 /* Clear Output Data Register */
106#define PIO_ODSR 0x38 /* Output Data Status Register */
107#define PIO_PDSR 0x3c /* Pin Data Status Register */
108#define PIO_IER 0x40 /* Interrupt Enable Register */
109#define PIO_IDR 0x44 /* Interrupt Disable Register */
110#define PIO_IMR 0x48 /* Interrupt Mask Register */
111#define PIO_ISR 0x4c /* Interrupt Status Register */
112#define PIO_MDER 0x50 /* Multi-driver Enable Register */
113#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
114#define PIO_MDSR 0x58 /* Multi-driver Status Register */
115#define PIO_PUDR 0x60 /* Pull-up Disable Register */
116#define PIO_PUER 0x64 /* Pull-up Enable Register */
117#define PIO_PUSR 0x68 /* Pull-up Status Register */
118#define PIO_ASR 0x70 /* Peripheral A Select Register */
119#define PIO_BSR 0x74 /* Peripheral B Select Register */
120#define PIO_ABSR 0x78 /* AB Status Register */
121#define PIO_OWER 0xa0 /* Output Write Enable Register */
122#define PIO_OWDR 0xa4 /* Output Write Disable Register */
123#define PIO_OWSR 0xa8 /* Output Write Status Register */
124
125#define AT91_PIO_P(n) (1 << (n))
126
127
128/*
129 * Power Management Controller.
130 */
131#define AT91_PMC 0xc00
132
133#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
134#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
135
136#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
137#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
138#define AT91_PMC_UDP (1 << 1) /* USB Devcice Port Clock */
139#define AT91_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend */
140#define AT91_PMC_UHP (1 << 4) /* USB Host Port Clock */
141#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
142#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
143#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
144#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
145
146#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
147#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
148#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
149
150#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
151#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
152#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
153
154#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
155#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
156#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
157
158#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
159#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
160#define AT91_PMC_DIV (0xff << 0) /* Divider */
161#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
162#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
163#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
164#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
165
166#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
167#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
168#define AT91_PMC_CSS_SLOW (0 << 0)
169#define AT91_PMC_CSS_MAIN (1 << 0)
170#define AT91_PMC_CSS_PLLA (2 << 0)
171#define AT91_PMC_CSS_PLLB (3 << 0)
172#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
173#define AT91_PMC_PRES_1 (0 << 2)
174#define AT91_PMC_PRES_2 (1 << 2)
175#define AT91_PMC_PRES_4 (2 << 2)
176#define AT91_PMC_PRES_8 (3 << 2)
177#define AT91_PMC_PRES_16 (4 << 2)
178#define AT91_PMC_PRES_32 (5 << 2)
179#define AT91_PMC_PRES_64 (6 << 2)
180#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
181#define AT91_PMC_MDIV_1 (0 << 8)
182#define AT91_PMC_MDIV_2 (1 << 8)
183#define AT91_PMC_MDIV_3 (2 << 8)
184#define AT91_PMC_MDIV_4 (3 << 8)
185
186#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
187
188#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
189#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
190#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
191#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
192#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
193#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
194#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
195#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
196#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
197#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
198#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
199#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
200
201
202/*
203 * System Timer.
204 */
205#define AT91_ST 0xd00
206
207#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
208#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
209#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
210#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
211#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
212#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
213#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
214#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
215#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
216#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
217#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
218#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
219#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
220#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
221#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
222#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
223#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
224#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
225#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
226#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
227#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
228#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
229
230
231/*
232 * Real-time Clock.
233 */
234#define AT91_RTC 0xe00
235
236#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
237#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
238#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
239#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
240#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
241#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
242#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
243#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
244#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
245#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
246#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
247#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
248
249#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
250#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
251
252#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
253#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
254#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
255#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
256#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
257
258#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
259#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
260#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
261#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
262#define AT91_RTC_DAY (7 << 21) /* Current Day */
263#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
264
265#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
266#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
267#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
268#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
269
270#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
271#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
272#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
273
274#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
275#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
276#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
277#define AT91_RTC_SECEV (1 << 2) /* Second Event */
278#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
279#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
280
281#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
282#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
283#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
284#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
285
286#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
287#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
288#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
289#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
290#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
291
292
293/*
294 * Memory Controller.
295 */
296#define AT91_MC 0xf00
297
298#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
299#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
300
301#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
302#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
303#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
304#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
305#define AT91_MC_ABTSZ_BYTE (0 << 8)
306#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
307#define AT91_MC_ABTSZ_WORD (2 << 8)
308#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
309#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
310#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
311#define AT91_MC_ABTTYP_FETCH (2 << 10)
312#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
313#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
314#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
315#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
316#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
317#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
318#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
319#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
320
321#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
322
323#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
324#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
325#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
326#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
327#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
328
329/* External Bus Interface (EBI) registers */
330#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
331#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
332#define AT91_EBI_CS0A_SMC (0 << 0)
333#define AT91_EBI_CS0A_BFC (1 << 0)
334#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
335#define AT91_EBI_CS1A_SMC (0 << 1)
336#define AT91_EBI_CS1A_SDRAMC (1 << 1)
337#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
338#define AT91_EBI_CS3A_SMC (0 << 3)
339#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
340#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
341#define AT91_EBI_CS4A_SMC (0 << 4)
342#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
343#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
344#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
345
346/* Static Memory Controller (SMC) registers */
347#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
348#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
349#define AT91_SMC_NWS_(x) ((x) << 0)
350#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
351#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
352#define AT91_SMC_TDF_(x) ((x) << 8)
353#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
354#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
355#define AT91_SMC_DBW_16 (1 << 13)
356#define AT91_SMC_DBW_8 (2 << 13)
357#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
358#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
359#define AT91_SMC_ACSS_STD (0 << 16)
360#define AT91_SMC_ACSS_1 (1 << 16)
361#define AT91_SMC_ACSS_2 (2 << 16)
362#define AT91_SMC_ACSS_3 (3 << 16)
363#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
364#define AT91_SMC_RWSETUP_(x) ((x) << 24)
365#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
366#define AT91_SMC_RWHOLD_(x) ((x) << 28)
367
368/* SDRAM Controller registers */
369#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
370#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
371#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
372#define AT91_SDRAMC_MODE_NOP (1 << 0)
373#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
374#define AT91_SDRAMC_MODE_LMR (3 << 0)
375#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
376#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
377#define AT91_SDRAMC_DBW_32 (0 << 4)
378#define AT91_SDRAMC_DBW_16 (1 << 4)
379
380#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
381#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
382
383#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
384#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
385#define AT91_SDRAMC_NC_8 (0 << 0)
386#define AT91_SDRAMC_NC_9 (1 << 0)
387#define AT91_SDRAMC_NC_10 (2 << 0)
388#define AT91_SDRAMC_NC_11 (3 << 0)
389#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
390#define AT91_SDRAMC_NR_11 (0 << 2)
391#define AT91_SDRAMC_NR_12 (1 << 2)
392#define AT91_SDRAMC_NR_13 (2 << 2)
393#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
394#define AT91_SDRAMC_NB_2 (0 << 4)
395#define AT91_SDRAMC_NB_4 (1 << 4)
396#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
397#define AT91_SDRAMC_CAS_2 (2 << 5)
398#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
399#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
400#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
401#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
402#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
403#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
404
405#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
406#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
407#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
408#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
409#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
410#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
411
412/* Burst Flash Controller register */
413#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
414#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
415#define AT91_BFC_BFCOM_DISABLED (0 << 0)
416#define AT91_BFC_BFCOM_ASYNC (1 << 0)
417#define AT91_BFC_BFCOM_BURST (2 << 0)
418#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
419#define AT91_BFC_BFCC_MCK (1 << 2)
420#define AT91_BFC_BFCC_DIV2 (2 << 2)
421#define AT91_BFC_BFCC_DIV4 (3 << 2)
422#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
423#define AT91_BFC_PAGES (7 << 8) /* Page Size */
424#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
425#define AT91_BFC_PAGES_16 (1 << 8)
426#define AT91_BFC_PAGES_32 (2 << 8)
427#define AT91_BFC_PAGES_64 (3 << 8)
428#define AT91_BFC_PAGES_128 (4 << 8)
429#define AT91_BFC_PAGES_256 (5 << 8)
430#define AT91_BFC_PAGES_512 (6 << 8)
431#define AT91_BFC_PAGES_1024 (7 << 8)
432#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
433#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
434#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
435#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
436#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
437
438#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h b/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
deleted file mode 100644
index 951e3f61cef4..000000000000
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * USB Device Port (UDP) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_UDP_H
17#define AT91RM9200_UDP_H
18
19#define AT91_UDP_FRM_NUM 0x00 /* Frame Number Register */
20#define AT91_UDP_NUM (0x7ff << 0) /* Frame Number */
21#define AT91_UDP_FRM_ERR (1 << 16) /* Frame Error */
22#define AT91_UDP_FRM_OK (1 << 17) /* Frame OK */
23
24#define AT91_UDP_GLB_STAT 0x04 /* Global State Register */
25#define AT91_UDP_FADDEN (1 << 0) /* Function Address Enable */
26#define AT91_UDP_CONFG (1 << 1) /* Configured */
27#define AT91_UDP_ESR (1 << 2) /* Enable Send Resume */
28#define AT91_UDP_RSMINPR (1 << 3) /* Resume has been sent */
29#define AT91_UDP_RMWUPE (1 << 4) /* Remote Wake Up Enable */
30
31#define AT91_UDP_FADDR 0x08 /* Function Address Register */
32#define AT91_UDP_FADD (0x7f << 0) /* Function Address Value */
33#define AT91_UDP_FEN (1 << 8) /* Function Enable */
34
35#define AT91_UDP_IER 0x10 /* Interrupt Enable Register */
36#define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */
37#define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */
38
39#define AT91_UDP_ISR 0x1c /* Interrupt Status Register */
40#define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */
41#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */
42#define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */
43#define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status */
44#define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */
45#define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrpt Status */
46#define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status */
47
48#define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */
49#define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */
50
51#define AT91_UDP_CSR(n) (0x30 + ((n) * 4)) /* Endpoint Control/Status Registers 0-7 */
52#define AT91_UDP_TXCOMP (1 << 0) /* Generates IN packet with data previously written in DPR */
53#define AT91_UDP_RX_DATA_BK0 (1 << 1) /* Receive Data Bank 0 */
54#define AT91_UDP_RXSETUP (1 << 2) /* Send STALL to the host */
55#define AT91_UDP_STALLSENT (1 << 3) /* Stall Sent / Isochronous error (Isochronous endpoints) */
56#define AT91_UDP_TXPKTRDY (1 << 4) /* Transmit Packet Ready */
57#define AT91_UDP_FORCESTALL (1 << 5) /* Force Stall */
58#define AT91_UDP_RX_DATA_BK1 (1 << 6) /* Receive Data Bank 1 */
59#define AT91_UDP_DIR (1 << 7) /* Transfer Direction */
60#define AT91_UDP_EPTYPE (7 << 8) /* Endpoint Type */
61#define AT91_UDP_EPTYPE_CTRL (0 << 8)
62#define AT91_UDP_EPTYPE_ISO_OUT (1 << 8)
63#define AT91_UDP_EPTYPE_BULK_OUT (2 << 8)
64#define AT91_UDP_EPTYPE_INT_OUT (3 << 8)
65#define AT91_UDP_EPTYPE_ISO_IN (5 << 8)
66#define AT91_UDP_EPTYPE_BULK_IN (6 << 8)
67#define AT91_UDP_EPTYPE_INT_IN (7 << 8)
68#define AT91_UDP_DTGLE (1 << 11) /* Data Toggle */
69#define AT91_UDP_EPEDS (1 << 15) /* Endpoint Enable/Disable */
70#define AT91_UDP_RXBYTECNT (0x7ff << 16) /* Number of bytes in FIFO */
71
72#define AT91_UDP_FDR(n) (0x50 + ((n) * 4)) /* Endpoint FIFO Data Registers 0-7 */
73
74#define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */
75#define AT91_UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */
76
77#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260.h b/include/asm-arm/arch-at91rm9200/at91sam9260.h
new file mode 100644
index 000000000000..46f4dd65c035
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9260.h
@@ -0,0 +1,125 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91sam9260.h
3 *
4 * (C) 2006 Andrew Victor
5 *
6 * Common definitions.
7 * Based on AT91SAM9260 datasheet revision A (Preliminary).
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9260_H
16#define AT91SAM9260_H
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
22#define AT91_ID_SYS 1 /* System Peripherals */
23#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
24#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
25#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
26#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
27#define AT91SAM9260_ID_US0 6 /* USART 0 */
28#define AT91SAM9260_ID_US1 7 /* USART 1 */
29#define AT91SAM9260_ID_US2 8 /* USART 2 */
30#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
31#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
32#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
33#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
34#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
35#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
36#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
37#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
38#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
39#define AT91SAM9260_ID_UHP 20 /* USB Host port */
40#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
41#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
42#define AT91SAM9260_ID_US3 23 /* USART 3 */
43#define AT91SAM9260_ID_US4 24 /* USART 4 */
44#define AT91SAM9260_ID_US5 25 /* USART 5 */
45#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
46#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
47#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
48#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
49#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
50#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
51
52
53/*
54 * User Peripheral physical base addresses.
55 */
56#define AT91SAM9260_BASE_TCB0 0xfffa0000
57#define AT91SAM9260_BASE_TC0 0xfffa0000
58#define AT91SAM9260_BASE_TC1 0xfffa0040
59#define AT91SAM9260_BASE_TC2 0xfffa0080
60#define AT91SAM9260_BASE_UDP 0xfffa4000
61#define AT91SAM9260_BASE_MCI 0xfffa8000
62#define AT91SAM9260_BASE_TWI 0xfffac000
63#define AT91SAM9260_BASE_US0 0xfffb0000
64#define AT91SAM9260_BASE_US1 0xfffb4000
65#define AT91SAM9260_BASE_US2 0xfffb8000
66#define AT91SAM9260_BASE_SSC 0xfffbc000
67#define AT91SAM9260_BASE_ISI 0xfffc0000
68#define AT91SAM9260_BASE_EMAC 0xfffc4000
69#define AT91SAM9260_BASE_SPI0 0xfffc8000
70#define AT91SAM9260_BASE_SPI1 0xfffcc000
71#define AT91SAM9260_BASE_US3 0xfffd0000
72#define AT91SAM9260_BASE_US4 0xfffd4000
73#define AT91SAM9260_BASE_US5 0xfffd8000
74#define AT91SAM9260_BASE_TCB1 0xfffdc000
75#define AT91SAM9260_BASE_TC3 0xfffdc000
76#define AT91SAM9260_BASE_TC4 0xfffdc040
77#define AT91SAM9260_BASE_TC5 0xfffdc080
78#define AT91SAM9260_BASE_ADC 0xfffe0000
79#define AT91_BASE_SYS 0xffffe800
80
81/*
82 * System Peripherals (offset from AT91_BASE_SYS)
83 */
84#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
85#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
86#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
87#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
88#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
89#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
90#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
91#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
92#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
93#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
94#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
95#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
96#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
97#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
98#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
99#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
100#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
101
102
103/*
104 * Internal Memory.
105 */
106#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
107#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
108
109#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
110#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
111#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
112#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
113
114#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
115
116#if 0
117/*
118 * PIO pin definitions (peripheral A/B multiplexing).
119 */
120
121// TODO: Add
122
123#endif
124
125#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
new file mode 100644
index 000000000000..746d973705bf
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
@@ -0,0 +1,78 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
3 *
4 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
5 * Based on AT91SAM9260 datasheet revision B.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91SAM9260_MATRIX_H
14#define AT91SAM9260_MATRIX_H
15
16#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
17#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
18#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
19#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
20#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
21#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x04) /* Master Configuration Register 5 */
22#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
23#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
24#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
25#define AT91_MATRIX_ULBT_FOUR (2 << 0)
26#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
27#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
28
29#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
30#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
31#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
32#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
33#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
34#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
35#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
36#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
37#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
38#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
39#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
40#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
41#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
42#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
43
44#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
45#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
46#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
47#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
48#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
49#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
50#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
51#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
52#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
53#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
54#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
55
56#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
57#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
58#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
59
60#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
61#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
62#define AT91_MATRIX_CS1A_SMC (0 << 1)
63#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
64#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
65#define AT91_MATRIX_CS3A_SMC (0 << 3)
66#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
67#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
68#define AT91_MATRIX_CS4A_SMC (0 << 4)
69#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
70#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */
71#define AT91_MATRIX_CS5A_SMC (0 << 5)
72#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
73#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
74#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
75#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
76#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
77
78#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261.h b/include/asm-arm/arch-at91rm9200/at91sam9261.h
new file mode 100644
index 000000000000..8d39672d5b82
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9261.h
@@ -0,0 +1,292 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91sam9261.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Common definitions.
7 * Based on AT91SAM9261 datasheet revision E. (Preliminary)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9261_H
16#define AT91SAM9261_H
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
22#define AT91_ID_SYS 1 /* System Peripherals */
23#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
24#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
25#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
26#define AT91SAM9261_ID_US0 6 /* USART 0 */
27#define AT91SAM9261_ID_US1 7 /* USART 1 */
28#define AT91SAM9261_ID_US2 8 /* USART 2 */
29#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
30#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
31#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
32#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
33#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
34#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
35#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
36#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
37#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
38#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
39#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
40#define AT91SAM9261_ID_UHP 20 /* USB Host port */
41#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
42#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
43#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
44#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
45
46
47/*
48 * User Peripheral physical base addresses.
49 */
50#define AT91SAM9261_BASE_TCB0 0xfffa0000
51#define AT91SAM9261_BASE_TC0 0xfffa0000
52#define AT91SAM9261_BASE_TC1 0xfffa0040
53#define AT91SAM9261_BASE_TC2 0xfffa0080
54#define AT91SAM9261_BASE_UDP 0xfffa4000
55#define AT91SAM9261_BASE_MCI 0xfffa8000
56#define AT91SAM9261_BASE_TWI 0xfffac000
57#define AT91SAM9261_BASE_US0 0xfffb0000
58#define AT91SAM9261_BASE_US1 0xfffb4000
59#define AT91SAM9261_BASE_US2 0xfffb8000
60#define AT91SAM9261_BASE_SSC0 0xfffbc000
61#define AT91SAM9261_BASE_SSC1 0xfffc0000
62#define AT91SAM9261_BASE_SSC2 0xfffc4000
63#define AT91SAM9261_BASE_SPI0 0xfffc8000
64#define AT91SAM9261_BASE_SPI1 0xfffcc000
65#define AT91_BASE_SYS 0xffffea00
66
67
68/*
69 * System Peripherals (offset from AT91_BASE_SYS)
70 */
71#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
72#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
75#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
76#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
77#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
78#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
79#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
80#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
81#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
82#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
83#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
84#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
85#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
86
87
88/*
89 * Internal Memory.
90 */
91#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
92#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
93
94#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
95#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
96
97#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
98#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
99
100
101#if 0
102/*
103 * PIO pin definitions (peripheral A/B multiplexing).
104 */
105#define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */
106#define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */
107#define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */
108#define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */
109#define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */
110#define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */
111#define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */
112#define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */
113#define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */
114#define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */
115#define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */
116#define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */
117#define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */
118#define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */
119#define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */
120#define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */
121#define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */
122#define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */
123#define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */
124#define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */
125#define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */
126#define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */
127#define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */
128#define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */
129#define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */
130#define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */
131#define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */
132#define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */
133#define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */
134#define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */
135#define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */
136#define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */
137#define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */
138#define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */
139#define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */
140#define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */
141#define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */
142#define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */
143#define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */
144#define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */
145#define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */
146#define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */
147#define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */
148#define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */
149#define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */
150#define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */
151#define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */
152#define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */
153#define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */
154#define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */
155#define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */
156#define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */
157#define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */
158#define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */
159#define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */
160#define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */
161#define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */
162#define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */
163#define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */
164#define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */
165#define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */
166#define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */
167#define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */
168
169#define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */
170#define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */
171#define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */
172#define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */
173#define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */
174#define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */
175#define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */
176#define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */
177#define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */
178#define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */
179#define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */
180#define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */
181#define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */
182#define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */
183#define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */
184#define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */
185#define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */
186#define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */
187#define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */
188#define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */
189#define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */
190#define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */
191#define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */
192#define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */
193#define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */
194#define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */
195#define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */
196#define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */
197#define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */
198#define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */
199#define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */
200#define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */
201#define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */
202#define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */
203#define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */
204#define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */
205#define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */
206#define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */
207#define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */
208#define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */
209#define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */
210#define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */
211#define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */
212#define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */
213#define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */
214#define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */
215#define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */
216#define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */
217#define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */
218#define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */
219#define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */
220#define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */
221#define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */
222#define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */
223#define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */
224#define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */
225#define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */
226#define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */
227#define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */
228#define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */
229#define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */
230
231#define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */
232#define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */
233#define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */
234#define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */
235#define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */
236#define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */
237#define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */
238#define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */
239#define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */
240#define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */
241#define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */
242#define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */
243#define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */
244#define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */
245#define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */
246#define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */
247#define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */
248#define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */
249#define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */
250#define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */
251#define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */
252#define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */
253#define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */
254#define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */
255#define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */
256#define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */
257#define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */
258#define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */
259#define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */
260#define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */
261#define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */
262#define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */
263#define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */
264#define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */
265#define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
266#define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */
267#define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
268#define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */
269#define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
270#define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */
271#define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
272#define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */
273#define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
274#define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */
275#define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
276#define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */
277#define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */
278#define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */
279#define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */
280#define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */
281#define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */
282#define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */
283#define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */
284#define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */
285#define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */
286#define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */
287#define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */
288#define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */
289#define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */
290#endif
291
292#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
new file mode 100644
index 000000000000..270a5dcdf1cd
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
@@ -0,0 +1,62 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
3 *
4 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
5 * Based on AT91SAM9261 datasheet revision D.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91SAM9261_MATRIX_H
14#define AT91SAM9261_MATRIX_H
15
16#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
17#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
18#define AT01_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
19
20#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
21#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
22#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
23#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
24#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
25#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
26#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
27#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
28#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
29#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
30#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
31
32#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
33#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
34#define AT91_MATRIX_ITCM_0 (0 << 0)
35#define AT91_MATRIX_ITCM_16 (5 << 0)
36#define AT91_MATRIX_ITCM_32 (6 << 0)
37#define AT91_MATRIX_ITCM_64 (7 << 0)
38#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
39#define AT91_MATRIX_DTCM_0 (0 << 4)
40#define AT91_MATRIX_DTCM_16 (5 << 4)
41#define AT91_MATRIX_DTCM_32 (6 << 4)
42#define AT91_MATRIX_DTCM_64 (7 << 4)
43
44#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
45#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
46#define AT91_MATRIX_CS1A_SMC (0 << 1)
47#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
48#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
49#define AT91_MATRIX_CS3A_SMC (0 << 3)
50#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
51#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
52#define AT91_MATRIX_CS4A_SMC (0 << 4)
53#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
54#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
55#define AT91_MATRIX_CS5A_SMC (0 << 5)
56#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
57#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
58
59#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
60#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
61
62#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
new file mode 100644
index 000000000000..7d94968b5d57
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
@@ -0,0 +1,134 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
3 *
4 * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
5 * Based on AT91SAM9261 datasheet revision D.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91SAM926x_MC_H
14#define AT91SAM926x_MC_H
15
16/* SDRAM Controller (SDRAMC) registers */
17#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
18#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
19#define AT91_SDRAMC_MODE_NORMAL 0
20#define AT91_SDRAMC_MODE_NOP 1
21#define AT91_SDRAMC_MODE_PRECHARGE 2
22#define AT91_SDRAMC_MODE_LMR 3
23#define AT91_SDRAMC_MODE_REFRESH 4
24#define AT91_SDRAMC_MODE_EXT_LMR 5
25#define AT91_SDRAMC_MODE_DEEP 6
26
27#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
28#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
29
30#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
31#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
32#define AT91_SDRAMC_NC_8 (0 << 0)
33#define AT91_SDRAMC_NC_9 (1 << 0)
34#define AT91_SDRAMC_NC_10 (2 << 0)
35#define AT91_SDRAMC_NC_11 (3 << 0)
36#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
37#define AT91_SDRAMC_NR_11 (0 << 2)
38#define AT91_SDRAMC_NR_12 (1 << 2)
39#define AT91_SDRAMC_NR_13 (2 << 2)
40#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
41#define AT91_SDRAMC_NB_2 (0 << 4)
42#define AT91_SDRAMC_NB_4 (1 << 4)
43#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
44#define AT91_SDRAMC_CAS_1 (1 << 5)
45#define AT91_SDRAMC_CAS_2 (2 << 5)
46#define AT91_SDRAMC_CAS_3 (3 << 5)
47#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
48#define AT91_SDRAMC_DBW_32 (0 << 7)
49#define AT91_SDRAMC_DBW_16 (1 << 7)
50#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
51#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
52#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
53#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
54#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
55#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
56
57#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
58#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
59#define AT91_SDRAMC_LPCB_DISABLE 0
60#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
61#define AT91_SDRAMC_LPCB_POWER_DOWN 2
62#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
63#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
64#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
65#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
66#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
67#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
68#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
69#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
70
71#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
72#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
73#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
74#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
75#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
76
77#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
78#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
79#define AT91_SDRAMC_MD_SDRAM 0
80#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
81
82
83/* Static Memory Controller (SMC) registers */
84#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
85#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
86#define AT91_SMC_NWESETUP_(x) ((x) << 0)
87#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
88#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
89#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
90#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
91#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
92#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
93
94#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
95#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
96#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
97#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
98#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
99#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
100#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
101#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
102#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
103
104#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
105#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
106#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
107#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
108#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
109
110#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
111#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
112#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
113#define AT91_SMC_EXNWMODE (3 << 5) /* NWAIT Mode */
114#define AT91_SMC_EXNWMODE_DISABLE (0 << 5)
115#define AT91_SMC_EXNWMODE_FROZEN (2 << 5)
116#define AT91_SMC_EXNWMODE_READY (3 << 5)
117#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
118#define AT91_SMC_BAT_SELECT (0 << 8)
119#define AT91_SMC_BAT_WRITE (1 << 8)
120#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
121#define AT91_SMC_DBW_8 (0 << 12)
122#define AT91_SMC_DBW_16 (1 << 12)
123#define AT91_SMC_DBW_32 (2 << 12)
124#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
125#define AT91_SMC_TDF_(x) ((x) << 16)
126#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
127#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
128#define AT91_SMC_PS (3 << 28) /* Page Size */
129#define AT91_SMC_PS_4 (0 << 28)
130#define AT91_SMC_PS_8 (1 << 28)
131#define AT91_SMC_PS_16 (2 << 28)
132#define AT91_SMC_PS_32 (3 << 28)
133
134#endif
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h
index 3cc9aec80f9d..768e0fc6aa2f 100644
--- a/include/asm-arm/arch-at91rm9200/board.h
+++ b/include/asm-arm/arch-at91rm9200/board.h
@@ -48,13 +48,14 @@ struct at91_cf_data {
48 u8 det_pin; /* Card detect */ 48 u8 det_pin; /* Card detect */
49 u8 vcc_pin; /* power switching */ 49 u8 vcc_pin; /* power switching */
50 u8 rst_pin; /* card reset */ 50 u8 rst_pin; /* card reset */
51 u8 chipselect; /* EBI Chip Select number */
51}; 52};
52extern void __init at91_add_device_cf(struct at91_cf_data *data); 53extern void __init at91_add_device_cf(struct at91_cf_data *data);
53 54
54 /* MMC / SD */ 55 /* MMC / SD */
55struct at91_mmc_data { 56struct at91_mmc_data {
56 u8 det_pin; /* card detect IRQ */ 57 u8 det_pin; /* card detect IRQ */
57 unsigned is_b:1; /* uses B side (vs A) */ 58 unsigned slot_b:1; /* uses Slot B */
58 unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ 59 unsigned wire4:1; /* (SD) supports DAT0..DAT3 */
59 u8 wp_pin; /* (SD) writeprotect detect */ 60 u8 wp_pin; /* (SD) writeprotect detect */
60 u8 vcc_pin; /* power switching (high == on) */ 61 u8 vcc_pin; /* power switching (high == on) */
@@ -81,7 +82,8 @@ struct at91_nand_data {
81 u8 rdy_pin; /* ready/busy */ 82 u8 rdy_pin; /* ready/busy */
82 u8 ale; /* address line number connected to ALE */ 83 u8 ale; /* address line number connected to ALE */
83 u8 cle; /* address line number connected to CLE */ 84 u8 cle; /* address line number connected to CLE */
84 struct mtd_partition* (*partition_info)(int, int*); 85 u8 bus_width_16; /* buswidth is 16 bit */
86 struct mtd_partition* (*partition_info)(int, int*);
85}; 87};
86extern void __init at91_add_device_nand(struct at91_nand_data *data); 88extern void __init at91_add_device_nand(struct at91_nand_data *data);
87 89
diff --git a/include/asm-arm/arch-at91rm9200/cpu.h b/include/asm-arm/arch-at91rm9200/cpu.h
new file mode 100644
index 000000000000..6f8d09b08692
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/cpu.h
@@ -0,0 +1,49 @@
1/*
2 * include/asm-arm/arch-at91rm9200/cpu.h
3 *
4 * Copyright (C) 2006 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#ifndef __ASM_ARCH_CPU_H
14#define __ASM_ARCH_CPU_H
15
16#include <asm/hardware.h>
17#include <asm/arch/at91_dbgu.h>
18
19
20#define ARCH_ID_AT91RM9200 0x09290780
21#define ARCH_ID_AT91SAM9260 0x019803a0
22#define ARCH_ID_AT91SAM9261 0x019703a0
23
24
25static inline unsigned long at91_cpu_identify(void)
26{
27 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
28}
29
30
31#ifdef CONFIG_ARCH_AT91RM9200
32#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
33#else
34#define cpu_is_at91rm9200() (0)
35#endif
36
37#ifdef CONFIG_ARCH_AT91SAM9260
38#define cpu_is_at91sam9260() (at91_cpu_identify() == ARCH_ID_AT91SAM9260)
39#else
40#define cpu_is_at91sam9260() (0)
41#endif
42
43#ifdef CONFIG_ARCH_AT91SAM9261
44#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
45#else
46#define cpu_is_at91sam9261() (0)
47#endif
48
49#endif
diff --git a/include/asm-arm/arch-at91rm9200/debug-macro.S b/include/asm-arm/arch-at91rm9200/debug-macro.S
index f496b54c4c3e..85cdadf26634 100644
--- a/include/asm-arm/arch-at91rm9200/debug-macro.S
+++ b/include/asm-arm/arch-at91rm9200/debug-macro.S
@@ -12,6 +12,7 @@
12*/ 12*/
13 13
14#include <asm/hardware.h> 14#include <asm/hardware.h>
15#include <asm/arch/at91_dbgu.h>
15 16
16 .macro addruart,rx 17 .macro addruart,rx
17 mrc p15, 0, \rx, c1, c0 18 mrc p15, 0, \rx, c1, c0
diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S
index 61a326e94909..57248a796472 100644
--- a/include/asm-arm/arch-at91rm9200/entry-macro.S
+++ b/include/asm-arm/arch-at91rm9200/entry-macro.S
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <asm/hardware.h> 13#include <asm/hardware.h>
14#include <asm/arch/at91_aic.h>
14 15
15 .macro disable_fiq 16 .macro disable_fiq
16 .endm 17 .endm
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 9ca4cc9c0b2e..9ea5bfe06320 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -16,8 +16,16 @@
16 16
17#include <asm/sizes.h> 17#include <asm/sizes.h>
18 18
19#if defined(CONFIG_ARCH_AT91RM9200)
19#include <asm/arch/at91rm9200.h> 20#include <asm/arch/at91rm9200.h>
20#include <asm/arch/at91rm9200_sys.h> 21#elif defined(CONFIG_ARCH_AT91SAM9260)
22#include <asm/arch/at91sam9260.h>
23#elif defined(CONFIG_ARCH_AT91SAM9261)
24#include <asm/arch/at91sam9261.h>
25#else
26#error "Unsupported AT91 processor"
27#endif
28
21 29
22/* 30/*
23 * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF 31 * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
@@ -34,29 +42,27 @@
34 * Virtual to Physical Address mapping for IO devices. 42 * Virtual to Physical Address mapping for IO devices.
35 */ 43 */
36#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) 44#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
37#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI)
38#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) 45#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
39#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI)
40#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI)
41#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP)
42 46
43 /* Internal SRAM is mapped below the IO devices */ 47 /* Internal SRAM is mapped below the IO devices */
44#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE) 48#define AT91_SRAM_MAX SZ_1M
49#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
45 50
46/* Serial ports */ 51/* Serial ports */
47#define ATMEL_MAX_UART 5 /* 4 USART3's and one DBGU port */ 52#define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */
48 53
49/* FLASH */ 54/* External Memory Map */
50#define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */ 55#define AT91_CHIPSELECT_0 0x10000000
56#define AT91_CHIPSELECT_1 0x20000000
57#define AT91_CHIPSELECT_2 0x30000000
58#define AT91_CHIPSELECT_3 0x40000000
59#define AT91_CHIPSELECT_4 0x50000000
60#define AT91_CHIPSELECT_5 0x60000000
61#define AT91_CHIPSELECT_6 0x70000000
62#define AT91_CHIPSELECT_7 0x80000000
51 63
52/* SDRAM */ 64/* SDRAM */
53#define AT91_SDRAM_BASE 0x20000000 /* NCS1: SDRAM physical base address */ 65#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
54
55/* SmartMedia */
56#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3: Smartmedia physical base address */
57
58/* Compact Flash */
59#define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */
60 66
61/* Clocks */ 67/* Clocks */
62#define AT91_SLOW_CLOCK 32768 /* slow clock */ 68#define AT91_SLOW_CLOCK 32768 /* slow clock */
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
index 763cb96c418b..c0679eaefaf2 100644
--- a/include/asm-arm/arch-at91rm9200/irqs.h
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -21,6 +21,8 @@
21#ifndef __ASM_ARCH_IRQS_H 21#ifndef __ASM_ARCH_IRQS_H
22#define __ASM_ARCH_IRQS_H 22#define __ASM_ARCH_IRQS_H
23 23
24#include <asm/arch/at91_aic.h>
25
24#define NR_AIC_IRQS 32 26#define NR_AIC_IRQS 32
25 27
26 28
diff --git a/include/asm-arm/arch-at91rm9200/system.h b/include/asm-arm/arch-at91rm9200/system.h
index 8a2ff472e4cf..9c67130603b2 100644
--- a/include/asm-arm/arch-at91rm9200/system.h
+++ b/include/asm-arm/arch-at91rm9200/system.h
@@ -22,6 +22,8 @@
22#define __ASM_ARCH_SYSTEM_H 22#define __ASM_ARCH_SYSTEM_H
23 23
24#include <asm/hardware.h> 24#include <asm/hardware.h>
25#include <asm/arch/at91_st.h>
26#include <asm/arch/at91_dbgu.h>
25 27
26static inline void arch_idle(void) 28static inline void arch_idle(void)
27{ 29{
@@ -39,21 +41,13 @@ static inline void arch_idle(void)
39 cpu_do_idle(); 41 cpu_do_idle();
40} 42}
41 43
42static inline void arch_reset(char mode) 44void (*at91_arch_reset)(void);
43{
44 /*
45 * Perform a hardware reset with the use of the Watchdog timer.
46 */
47 at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
48 at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
49}
50
51#define ARCH_ID_AT91RM9200 0x09200080
52#define ARCH_ID_AT91SAM9261 0x019000a0
53 45
54static inline unsigned long arch_identify(void) 46static inline void arch_reset(char mode)
55{ 47{
56 return at91_sys_read(AT91_DBGU_CIDR) & (AT91_CIDR_EPROC | AT91_CIDR_ARCH); 48 /* call the CPU-specific reset function */
49 if (at91_arch_reset)
50 (at91_arch_reset)();
57} 51}
58 52
59#endif 53#endif
diff --git a/include/asm-arm/arch-at91rm9200/timex.h b/include/asm-arm/arch-at91rm9200/timex.h
index 88687cefe6eb..faeca45a8d44 100644
--- a/include/asm-arm/arch-at91rm9200/timex.h
+++ b/include/asm-arm/arch-at91rm9200/timex.h
@@ -23,6 +23,15 @@
23 23
24#include <asm/hardware.h> 24#include <asm/hardware.h>
25 25
26#if defined(CONFIG_ARCH_AT91RM9200)
27
26#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) 28#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK)
27 29
30#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
31
32#define AT91SAM9_MASTER_CLOCK 99300000
33#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
34
35#endif
36
28#endif 37#endif
diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h
index ec7811ab0a52..34b4b93fa015 100644
--- a/include/asm-arm/arch-at91rm9200/uncompress.h
+++ b/include/asm-arm/arch-at91rm9200/uncompress.h
@@ -22,11 +22,11 @@
22#define __ASM_ARCH_UNCOMPRESS_H 22#define __ASM_ARCH_UNCOMPRESS_H
23 23
24#include <asm/hardware.h> 24#include <asm/hardware.h>
25#include <asm/arch/at91_dbgu.h>
25 26
26/* 27/*
27 * The following code assumes the serial port has already been 28 * The following code assumes the serial port has already been
28 * initialized by the bootloader. We search for the first enabled 29 * initialized by the bootloader. If you didn't setup a port in
29 * port in the most probable order. If you didn't setup a port in
30 * your bootloader then nothing will appear (which might be desired). 30 * your bootloader then nothing will appear (which might be desired).
31 * 31 *
32 * This does not append a newline 32 * This does not append a newline
diff --git a/include/asm-arm/arch-at91rm9200/vmalloc.h b/include/asm-arm/arch-at91rm9200/vmalloc.h
index 4c367eb57f47..0a23b8c562b9 100644
--- a/include/asm-arm/arch-at91rm9200/vmalloc.h
+++ b/include/asm-arm/arch-at91rm9200/vmalloc.h
@@ -21,6 +21,6 @@
21#ifndef __ASM_ARCH_VMALLOC_H 21#ifndef __ASM_ARCH_VMALLOC_H
22#define __ASM_ARCH_VMALLOC_H 22#define __ASM_ARCH_VMALLOC_H
23 23
24#define VMALLOC_END (AT91_SRAM_VIRT_BASE & PGDIR_MASK) 24#define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK)
25 25
26#endif 26#endif
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
index c6e8dcf674de..42768cc8bfb4 100644
--- a/include/asm-arm/arch-clps711x/memory.h
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -62,7 +62,15 @@
62 * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM. 62 * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM.
63 */ 63 */
64 64
65#ifdef CONFIG_DISCONTIGMEM 65/*
66 * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
67 * uses only one of the two banks (bank #1). However, even within
68 * bank #1, memory is discontiguous.
69 *
70 * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
71 * them, so we use 24 for the node max shift to get 16MB node sizes.
72 */
73
66/* 74/*
67 * Because of the wide memory address space between physical RAM banks on the 75 * Because of the wide memory address space between physical RAM banks on the
68 * SA1100, it's much more convenient to use Linux's NUMA support to implement 76 * SA1100, it's much more convenient to use Linux's NUMA support to implement
@@ -80,48 +88,7 @@
80 * node 2: 0xd0000000 - 0xd7ffffff 88 * node 2: 0xd0000000 - 0xd7ffffff
81 * node 3: 0xd8000000 - 0xdfffffff 89 * node 3: 0xd8000000 - 0xdfffffff
82 */ 90 */
83 91#define NODE_MEM_SIZE_BITS 24
84/*
85 * Given a kernel address, find the home node of the underlying memory.
86 */
87#define KVADDR_TO_NID(addr) \
88 (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
89
90/*
91 * Given a page frame number, convert it to a node id.
92 */
93#define PFN_TO_NID(pfn) \
94 (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
95
96/*
97 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
98 * and returns the mem_map of that node.
99 */
100#define ADDR_TO_MAPBASE(kaddr) \
101 NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
102
103#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
104
105/*
106 * Given a kaddr, LOCAL_MAR_NR finds the owning node of the memory
107 * and returns the index corresponding to the appropriate page in the
108 * node's mem_map.
109 */
110#define LOCAL_MAP_NR(addr) \
111 (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
112
113/*
114 * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
115 * uses only one of the two banks (bank #1). However, even within
116 * bank #1, memory is discontiguous.
117 *
118 * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
119 * them, so we use 24 for the node max shift to get 16MB node sizes.
120 */
121#define NODE_MAX_MEM_SHIFT 24
122#define NODE_MAX_MEM_SIZE (1<<NODE_MAX_MEM_SHIFT)
123
124#endif /* CONFIG_DISCONTIGMEM */
125 92
126#endif 93#endif
127 94
diff --git a/include/asm-arm/arch-imx/timex.h b/include/asm-arm/arch-imx/timex.h
index 8c91674706b1..e22ba789546c 100644
--- a/include/asm-arm/arch-imx/timex.h
+++ b/include/asm-arm/arch-imx/timex.h
@@ -21,7 +21,6 @@
21#ifndef __ASM_ARCH_TIMEX_H 21#ifndef __ASM_ARCH_TIMEX_H
22#define __ASM_ARCH_TIMEX_H 22#define __ASM_ARCH_TIMEX_H
23 23
24#include <asm/hardware.h> 24#define CLOCK_TICK_RATE (16000000)
25#define CLOCK_TICK_RATE (CLK32)
26 25
27#endif 26#endif
diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S
new file mode 100644
index 000000000000..788b4e386c16
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/debug-macro.S
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-iop13xx/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 .macro addruart, rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ mmu enabled?
17 moveq \rx, #0xff000000 @ physical
18 orreq \rx, \rx, #0x00d80000
19 movne \rx, #0xfe000000 @ virtual
20 orrne \rx, \rx, #0x00e80000
21 orr \rx, \rx, #0x00002300
22 orr \rx, \rx, #0x00000040
23 .endm
24
25#define UART_SHIFT 2
26#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
new file mode 100644
index 000000000000..2e15da53ff79
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -0,0 +1,3 @@
1#ifndef _IOP13XX_DMA_H
2#define _IOP13XX_DMA_H_
3#endif
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S
new file mode 100644
index 000000000000..94c50283dc56
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * iop13xx low level irq macros
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 .macro disable_fiq
20 .endm
21
22 /*
23 * Note: a 1-cycle window exists where iintvec will return the value
24 * of iintbase, so we explicitly check for "bad zeros"
25 */
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 mrc p15, 0, \tmp, c15, c1, 0
28 orr \tmp, \tmp, #(1 << 6)
29 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
30
31 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
32 cmp \irqnr, #0
33 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
34 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
35 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
36
37 biceq \tmp, \tmp, #(1 << 6)
38 mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts
39 .endm
diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/include/asm-arm/arch-iop13xx/hardware.h
new file mode 100644
index 000000000000..8e1d56289846
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/hardware.h
@@ -0,0 +1,28 @@
1#ifndef __ASM_ARCH_HARDWARE_H
2#define __ASM_ARCH_HARDWARE_H
3#include <asm/types.h>
4
5#define pcibios_assign_all_busses() 1
6
7#ifndef __ASSEMBLY__
8extern unsigned long iop13xx_pcibios_min_io;
9extern unsigned long iop13xx_pcibios_min_mem;
10extern u16 iop13xx_dev_id(void);
11extern void iop13xx_set_atu_mmr_bases(void);
12#endif
13
14#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io)
15#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem)
16
17/*
18 * Generic chipset bits
19 *
20 */
21#include "iop13xx.h"
22
23/*
24 * Board specific bits
25 */
26#include "iq81340.h"
27
28#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h
new file mode 100644
index 000000000000..db6de2480a24
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/io.h
@@ -0,0 +1,41 @@
1/*
2 * iop13xx custom ioremap implementation
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#ifndef __ASM_ARM_ARCH_IO_H
20#define __ASM_ARM_ARCH_IO_H
21
22#define IO_SPACE_LIMIT 0xffffffff
23
24#define __io(a) (a)
25#define __mem_pci(a) (a)
26#define __mem_isa(a) (a)
27
28extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
29extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
30 unsigned long flags);
31extern void __iop13xx_iounmap(void __iomem *addr);
32
33extern u32 iop13xx_atue_mem_base;
34extern u32 iop13xx_atux_mem_base;
35extern size_t iop13xx_atue_mem_size;
36extern size_t iop13xx_atux_mem_size;
37
38#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
39#define __arch_iounmap(a) __iop13xx_iounmap(a)
40
41#endif
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
new file mode 100644
index 000000000000..a88522a0ff8e
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -0,0 +1,492 @@
1#ifndef _IOP13XX_HW_H_
2#define _IOP13XX_HW_H_
3
4#ifndef __ASSEMBLY__
5/* The ATU offsets can change based on the strapping */
6extern u32 iop13xx_atux_pmmr_offset;
7extern u32 iop13xx_atue_pmmr_offset;
8void iop13xx_init_irq(void);
9void iop13xx_map_io(void);
10void iop13xx_platform_init(void);
11void iop13xx_init_irq(void);
12void iop13xx_init_time(unsigned long tickrate);
13unsigned long iop13xx_gettimeoffset(void);
14
15/* handle cp6 access
16 * to do: handle access in entry-armv5.S and unify with
17 * the iop3xx implementation
18 * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
19 * when interrupts are enabled
20 */
21static inline unsigned long iop13xx_cp6_save(void)
22{
23 u32 temp, cp_flags;
24
25 asm volatile (
26 "mrc p15, 0, %1, c15, c1, 0\n\t"
27 "orr %0, %1, #(1 << 6)\n\t"
28 "mcr p15, 0, %0, c15, c1, 0\n\t"
29 : "=r" (temp), "=r"(cp_flags));
30
31 return cp_flags;
32}
33
34static inline void iop13xx_cp6_restore(unsigned long cp_flags)
35{
36 asm volatile (
37 "mcr p15, 0, %0, c15, c1, 0\n\t"
38 : : "r" (cp_flags) );
39}
40
41/* CPUID CP6 R0 Page 0 */
42static inline int iop13xx_cpu_id(void)
43{
44 int id;
45 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
46 return id;
47}
48
49#endif
50
51/*
52 * IOP13XX I/O and Mem space regions for PCI autoconfiguration
53 */
54#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
55#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
56
57/* PCI MAP
58 * 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM
59 * 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB)
60*/
61#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
62#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
63#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
64#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL
65#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
66 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
67#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
68 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
69#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\
70 IOP13XX_PCIX_LOWER_IO_BA)
71#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
72 (IOP13XX_PCIX_LOWER_IO_PA\
73 - IOP13XX_PCIX_LOWER_IO_VA))
74
75#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
76#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
77#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
78#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
79 IOP13XX_PCIX_LOWER_MEM_BA)
80#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
81 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
82#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
83 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
84
85#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
86#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
87#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
88 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
89#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
90 IOP13XX_PCIX_LOWER_MEM_BA)
91
92/* PCI-E ranges */
93#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
94#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
95#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
96#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL
97#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
98 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
99#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
100 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
101#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
102 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
103#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\
104 IOP13XX_PCIE_LOWER_IO_BA)
105#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
106 (IOP13XX_PCIE_LOWER_IO_PA\
107 - IOP13XX_PCIE_LOWER_IO_VA))
108
109#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
110#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
111#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
112#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
113 IOP13XX_PCIE_LOWER_MEM_BA)
114#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
115 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
116#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
117 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
118
119/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
120#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
121#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
122#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
123 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
124#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
125 IOP13XX_PCIE_LOWER_MEM_BA)
126
127/* PBI Ranges */
128#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
129#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
130#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
131#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
132#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
133 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
134
135/*
136 * IOP13XX chipset registers
137 */
138#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
139#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
140#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
141#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
142 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
143#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
144 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
145#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
146 (IOP13XX_PMMR_PHYS_MEM_BASE\
147 - IOP13XX_PMMR_VIRT_MEM_BASE))
148#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
149 (IOP13XX_PMMR_PHYS_MEM_BASE\
150 - IOP13XX_PMMR_VIRT_MEM_BASE))
151#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
152#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
153#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
154#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
155#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
156#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
157#define IOP13XX_PMMR_SIZE 0x00080000
158
159/*=================== Defines for Platform Devices =====================*/
160#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
161#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
162#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
163#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
164
165#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
166#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
167#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
168#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
169#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
170#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
171
172/* ATU selection flags */
173/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
174#define IOP13XX_INIT_ATU_DEFAULT (0)
175#define IOP13XX_INIT_ATU_ATUX (1 << 0)
176#define IOP13XX_INIT_ATU_ATUE (1 << 1)
177#define IOP13XX_INIT_ATU_NONE (1 << 2)
178
179/* UART selection flags */
180/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
181#define IOP13XX_INIT_UART_DEFAULT (0)
182#define IOP13XX_INIT_UART_0 (1 << 0)
183#define IOP13XX_INIT_UART_1 (1 << 1)
184
185/* I2C selection flags */
186/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
187#define IOP13XX_INIT_I2C_DEFAULT (0)
188#define IOP13XX_INIT_I2C_0 (1 << 0)
189#define IOP13XX_INIT_I2C_1 (1 << 1)
190#define IOP13XX_INIT_I2C_2 (1 << 2)
191
192#define IQ81340_NUM_UART 2
193#define IQ81340_NUM_I2C 3
194#define IQ81340_NUM_PHYS_MAP_FLASH 1
195#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
196 IQ81340_NUM_I2C +\
197 IQ81340_NUM_PHYS_MAP_FLASH)
198
199/*========================== PMMR offsets for key registers ============*/
200#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
201#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
202#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
203#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
204#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
205#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
206#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
207#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
208#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
209
210#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
211#define IOP13XX_CONTROLLER_ONLY (1 << 14)
212#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
213
214#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
215#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
216 IOP13XX_PMON_PMMR_OFFSET)
217#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
218 IOP13XX_PMON_PMMR_OFFSET)
219
220#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
221#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
222#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
223#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
224
225#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
226#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
227#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
228#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
229
230#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
231#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
232#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
233#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
234
235#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
236#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
237
238/*================================ATU===================================*/
239#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
240 iop13xx_atux_pmmr_offset + (ofs))
241
242#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
243 iop13xx_atux_pmmr_offset + 0x2)
244
245#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
246 iop13xx_atux_pmmr_offset + 0x4)
247#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
248 iop13xx_atux_pmmr_offset + 0x6)
249
250#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
251#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
252#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
253#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
254#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
255#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
256#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
257#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
258#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
259#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
260#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
261#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
262#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
263#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
264#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
265#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
266#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
267#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
268#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
269#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
270#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
271#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
272#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
273#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
274
275#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
276#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
277#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
278#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
279#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
280#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
281#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
282#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
283#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
284#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
285#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
286#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
287#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
288#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
289
290#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
291#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
292#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
293#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
294#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
295#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
296
297#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
298#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
299#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
300#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
301#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
302#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
303#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
304#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
305#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
306#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
307#define IOP13XX_ATUX_STAT_BIST (1 << 8 )
308#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
309#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
310#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
311#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
312#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
313#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
314
315#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
316#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
317#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
318
319#define IOP13XX_ATUX_IALR_DISABLE 0x00000001
320#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
321
322#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
323 iop13xx_atue_pmmr_offset + (ofs))
324
325#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
326 iop13xx_atue_pmmr_offset + 0x2)
327#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
328 iop13xx_atue_pmmr_offset + 0x4)
329#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
330 iop13xx_atue_pmmr_offset + 0x6)
331
332#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
333#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
334#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
335#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
336#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
337#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
338#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
339#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
340#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
341#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
342#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
343#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
344#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
345#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
346#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
347#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
348 iop13xx_atue_pmmr_offset + 0xe2)
349#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
350#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
351#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
352#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
353#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
354#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
355#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
356#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
357#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
358
359#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
360#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
361#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
362#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
363#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
364#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
365
366#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
367#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
368
369#define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
370#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
371#define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
372#define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
373#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
374#define IOP13XX_ATUE_OCCAR_EXT_REG (8)
375#define IOP13XX_ATUE_OCCAR_REG (2)
376
377#define IOP13XX_ATUE_PCSR_BUS_NUM (24)
378#define IOP13XX_ATUE_PCSR_DEV_NUM (19)
379#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
380#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
381#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
382#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
383#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
384
385#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
386#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
387#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
388
389#define IOP13XX_ATUE_PCSR_CORE_RESET (8)
390#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
391
392#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
393#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
394#define IOP13XX_ATUE_STAT_PME (1 << 27)
395#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
396#define IOP13XX_ATUE_STAT_IVM (1 << 25)
397#define IOP13XX_ATUE_STAT_BIST (1 << 24)
398#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
399#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
400#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
401#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
402#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
403#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
404#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
405#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
406#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
407#define IOP13XX_ATUE_STAT_CRS (1 << 7 )
408#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
409#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
410#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
411#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
412#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
413#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
414#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
415
416#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
417#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
418#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
419#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
420#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
421#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
422#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
423#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
424#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
425#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
426#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
427#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
428#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
429#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
430#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
431
432#define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
433#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
434#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
435#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
436/*=======================================================================*/
437
438/*==============================ADMA UNITS===============================*/
439#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
440#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
441#define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs))
442
443#define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0)
444#define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4)
445#define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8)
446#define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18)
447#define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c)
448#define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20)
449#define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24)
450#define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28)
451#define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c)
452#define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30)
453#define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34)
454#define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38)
455#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
456#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
457
458/*==============================XSI BRIDGE===============================*/
459#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
460#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
461#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
462#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
463 IOP13XX_PMMR_VIRT_TO_PHYS(\
464 IOP13XX_ATUE_OCCDR))\
465 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
466#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
467 IOP13XX_PMMR_VIRT_TO_PHYS(\
468 IOP13XX_ATUX_OCCDR))\
469 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
470/*=======================================================================*/
471
472#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
473 (ofs))
474
475#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
476#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
477#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
478#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
479#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
480#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
481
482#define IOP13XX_TMR_TC 0x01
483#define IOP13XX_TMR_EN 0x02
484#define IOP13XX_TMR_RELOAD 0x04
485#define IOP13XX_TMR_PRIVILEGED 0x08
486
487#define IOP13XX_TMR_RATIO_1_1 0x00
488#define IOP13XX_TMR_RATIO_4_1 0x10
489#define IOP13XX_TMR_RATIO_8_1 0x20
490#define IOP13XX_TMR_RATIO_16_1 0x30
491
492#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/include/asm-arm/arch-iop13xx/iq81340.h
new file mode 100644
index 000000000000..b98f8f109c22
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iq81340.h
@@ -0,0 +1,31 @@
1#ifndef _IQ81340_H_
2#define _IQ81340_H_
3
4#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA
5#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000)
6
7#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */
8
9#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
10
11#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0)
12#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000)
13#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000)
14#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000)
15#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000)
16#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000)
17#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000)
18#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000)
19#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000)
20#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000)
21#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000)
22#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
23
24#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH)
25#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1)
26
27/* These are the values used in the Machine description */
28#define PHYS_IO 0xfeffff00
29#define IO_PG_OFFSET 0xffffff00
30#define BOOT_PARAM_OFFSET 0x00000100
31#endif /* _IQ81340_H_ */
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h
new file mode 100644
index 000000000000..442e35a40359
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/irqs.h
@@ -0,0 +1,207 @@
1#ifndef _IOP13XX_IRQS_H_
2#define _IOP13XX_IRQS_H_
3
4#ifndef __ASSEMBLER__
5#include <linux/types.h>
6#include <asm/system.h> /* local_irq_save */
7#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
8
9/* INTPND0 CP6 R0 Page 3
10 */
11static inline u32 read_intpnd_0(void)
12{
13 u32 val;
14 asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
15 return val;
16}
17
18/* INTPND1 CP6 R1 Page 3
19 */
20static inline u32 read_intpnd_1(void)
21{
22 u32 val;
23 asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
24 return val;
25}
26
27/* INTPND2 CP6 R2 Page 3
28 */
29static inline u32 read_intpnd_2(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
33 return val;
34}
35
36/* INTPND3 CP6 R3 Page 3
37 */
38static inline u32 read_intpnd_3(void)
39{
40 u32 val;
41 asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
42 return val;
43}
44
45static inline void
46iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
47{
48 local_irq_save(*irq_flags);
49 *cp_flags = iop13xx_cp6_save();
50}
51
52static inline void
53iop13xx_cp6_irq_restore(unsigned long *cp_flags,
54 unsigned long *irq_flags)
55{
56 iop13xx_cp6_restore(*cp_flags);
57 local_irq_restore(*irq_flags);
58}
59#endif
60
61#define INTBASE 0
62#define INTSIZE_4 1
63
64/*
65 * iop34x chipset interrupts
66 */
67#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x))
68
69/*
70 * On IRQ or FIQ register
71 */
72#define IRQ_IOP13XX_ADMA0_EOT (0)
73#define IRQ_IOP13XX_ADMA0_EOC (1)
74#define IRQ_IOP13XX_ADMA1_EOT (2)
75#define IRQ_IOP13XX_ADMA1_EOC (3)
76#define IRQ_IOP13XX_ADMA2_EOT (4)
77#define IRQ_IOP13XX_ADMA2_EOC (5)
78#define IRQ_IOP134_WATCHDOG (6)
79#define IRQ_IOP13XX_RSVD_7 (7)
80#define IRQ_IOP13XX_TIMER0 (8)
81#define IRQ_IOP13XX_TIMER1 (9)
82#define IRQ_IOP13XX_I2C_0 (10)
83#define IRQ_IOP13XX_I2C_1 (11)
84#define IRQ_IOP13XX_MSG (12)
85#define IRQ_IOP13XX_MSGIBQ (13)
86#define IRQ_IOP13XX_ATU_IM (14)
87#define IRQ_IOP13XX_ATU_BIST (15)
88#define IRQ_IOP13XX_PPMU (16)
89#define IRQ_IOP13XX_COREPMU (17)
90#define IRQ_IOP13XX_CORECACHE (18)
91#define IRQ_IOP13XX_RSVD_19 (19)
92#define IRQ_IOP13XX_RSVD_20 (20)
93#define IRQ_IOP13XX_RSVD_21 (21)
94#define IRQ_IOP13XX_RSVD_22 (22)
95#define IRQ_IOP13XX_RSVD_23 (23)
96#define IRQ_IOP13XX_XINT0 (24)
97#define IRQ_IOP13XX_XINT1 (25)
98#define IRQ_IOP13XX_XINT2 (26)
99#define IRQ_IOP13XX_XINT3 (27)
100#define IRQ_IOP13XX_XINT4 (28)
101#define IRQ_IOP13XX_XINT5 (29)
102#define IRQ_IOP13XX_XINT6 (30)
103#define IRQ_IOP13XX_XINT7 (31)
104 /* IINTSRC1 bit */
105#define IRQ_IOP13XX_XINT8 (32) /* 0 */
106#define IRQ_IOP13XX_XINT9 (33) /* 1 */
107#define IRQ_IOP13XX_XINT10 (34) /* 2 */
108#define IRQ_IOP13XX_XINT11 (35) /* 3 */
109#define IRQ_IOP13XX_XINT12 (36) /* 4 */
110#define IRQ_IOP13XX_XINT13 (37) /* 5 */
111#define IRQ_IOP13XX_XINT14 (38) /* 6 */
112#define IRQ_IOP13XX_XINT15 (39) /* 7 */
113#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */
114#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */
115#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */
116#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */
117#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */
118#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */
119#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */
120#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */
121#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */
122#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */
123#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */
124#define IRQ_IOP13XX_UART0 (51) /* 19 */
125#define IRQ_IOP13XX_UART1 (52) /* 20 */
126#define IRQ_IOP13XX_PBIE (53) /* 21 */
127#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */
128#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */
129#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */
130#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */
131#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */
132#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */
133#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */
134#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */
135#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */
136#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */
137 /* IINTSRC2 bit */
138#define IRQ_IOP13XX_INTERPROC (64) /* 0 */
139#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */
140#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */
141#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */
142#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */
143#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */
144#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */
145#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */
146#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */
147#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */
148#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */
149#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */
150#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */
151#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */
152#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */
153#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */
154#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */
155#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */
156#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */
157#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */
158#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */
159#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */
160#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */
161#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */
162#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */
163#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */
164#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */
165#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */
166#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */
167#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */
168#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */
169#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */
170 /* IINTSRC3 bit */
171#define IRQ_IOP13XX_I2C_2 (96) /* 0 */
172#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */
173#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */
174#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */
175#define IRQ_IOP13XX_IMU (100) /* 4 */
176#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */
177#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */
178#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */
179#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */
180#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */
181#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */
182#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */
183#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */
184#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */
185#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */
186#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */
187#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */
188#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */
189#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */
190#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */
191#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */
192#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */
193#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */
194#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */
195#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */
196#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */
197#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */
198#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */
199#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */
200#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */
201#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */
202#define IRQ_IOP13XX_HPI (127) /* 31 */
203
204#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
205#define NR_IRQS NR_IOP13XX_IRQS
206
207#endif /* _IOP13XX_IRQ_H_ */
diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h
new file mode 100644
index 000000000000..031a0fa78eff
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/memory.h
@@ -0,0 +1,64 @@
1#ifndef __ASM_ARCH_MEMORY_H
2#define __ASM_ARCH_MEMORY_H
3
4#include <asm/arch/hardware.h>
5
6/*
7 * Physical DRAM offset.
8 */
9#define PHYS_OFFSET UL(0x00000000)
10#define TASK_SIZE UL(0x3f000000)
11#define PAGE_OFFSET UL(0x40000000)
12#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
13
14#ifndef __ASSEMBLY__
15
16#if defined(CONFIG_ARCH_IOP13XX)
17#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
18#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
19#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
20#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
21
22/*
23 * Virtual view <-> PCI DMA view memory address translations
24 * virt_to_bus: Used to translate the virtual address to an
25 * address suitable to be passed to set_dma_addr
26 * bus_to_virt: Used to convert an address for DMA operations
27 * to an address that the kernel can use.
28 */
29
30/* RAM has 1:1 mapping on the PCIe/x Busses */
31#define __virt_to_bus(x) (__virt_to_phys(x))
32#define __bus_to_virt(x) (__phys_to_virt(x))
33
34#define virt_to_lbus(x) \
35(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \
36((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \
37((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
38((x) - PAGE_OFFSET + PHYS_OFFSET))
39
40#define lbus_to_virt(x) \
41(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
42((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
43((x) - PHYS_OFFSET + PAGE_OFFSET))
44
45/* Device is an lbus device if it is on the platform bus of the IOP13XX */
46#define is_lbus_device(dev) (dev &&\
47 (strncmp(dev->bus->name, "platform", 8) == 0))
48
49#define __arch_page_to_dma(dev, page) \
50({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
51(dma_addr_t)__virt_to_bus(page_address(page));})
52
53#define __arch_dma_to_virt(dev, addr) \
54({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
55
56#define __arch_virt_to_dma(dev, addr) \
57({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
58
59#endif /* CONFIG_ARCH_IOP13XX */
60#endif /* !ASSEMBLY */
61
62#define PFN_TO_NID(addr) (0)
63
64#endif
diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h
new file mode 100644
index 000000000000..4041f30d4cd3
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/pci.h
@@ -0,0 +1,57 @@
1#ifndef _IOP13XX_PCI_H_
2#define _IOP13XX_PCI_H_
3#include <asm/arch/irqs.h>
4#include <asm/io.h>
5
6struct pci_sys_data;
7struct hw_pci;
8int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
9struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
10void iop13xx_atu_select(struct hw_pci *plat_pci);
11void iop13xx_pci_init(void);
12void iop13xx_map_pci_memory(void);
13
14#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \
15 PCI_STATUS_SIG_TARGET_ABORT | \
16 PCI_STATUS_REC_TARGET_ABORT | \
17 PCI_STATUS_REC_TARGET_ABORT | \
18 PCI_STATUS_REC_MASTER_ABORT | \
19 PCI_STATUS_SIG_SYSTEM_ERROR | \
20 PCI_STATUS_DETECTED_PARITY)
21
22#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \
23 IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \
24 IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \
25 IOP13XX_ATUE_STAT_ERR_COR | \
26 IOP13XX_ATUE_STAT_ERR_UNCOR | \
27 IOP13XX_ATUE_STAT_CRS | \
28 IOP13XX_ATUE_STAT_DET_PAR_ERR | \
29 IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
30 IOP13XX_ATUE_STAT_SIG_TABORT | \
31 IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
32 IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
33
34#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \
35 IOP13XX_ATUX_STAT_REC_SCEM | \
36 IOP13XX_ATUX_STAT_TX_SERR | \
37 IOP13XX_ATUX_STAT_DET_PAR_ERR | \
38 IOP13XX_ATUX_STAT_INT_REC_MABORT | \
39 IOP13XX_ATUX_STAT_REC_SERR | \
40 IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
41 IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
42 IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
43 IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
44
45/* PCI interrupts
46 */
47#define ATUX_INTA IRQ_IOP13XX_XINT0
48#define ATUX_INTB IRQ_IOP13XX_XINT1
49#define ATUX_INTC IRQ_IOP13XX_XINT2
50#define ATUX_INTD IRQ_IOP13XX_XINT3
51
52#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
53#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
54#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
55#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
56
57#endif /* _IOP13XX_PCI_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
new file mode 100644
index 000000000000..ee3a62530af2
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -0,0 +1,59 @@
1/*
2 * linux/include/asm-arm/arch-iop13xx/system.h
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <asm/arch/iop13xx.h>
11static inline void arch_idle(void)
12{
13 cpu_do_idle();
14}
15
16/* WDTCR CP6 R7 Page 9 */
17static inline u32 read_wdtcr(void)
18{
19 u32 val;
20 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
21 return val;
22}
23static inline void write_wdtcr(u32 val)
24{
25 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
26}
27
28/* WDTSR CP6 R8 Page 9 */
29static inline u32 read_wdtsr(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
33 return val;
34}
35static inline void write_wdtsr(u32 val)
36{
37 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
38}
39
40#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e
41#define IOP13XX_WDTCR_EN 0xe1e1e1e1
42#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f
43#define IOP13XX_WDTCR_DIS 0xf1f1f1f1
44#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
45#define IOP13XX_WDTCR_IB_RESET (1 << 0)
46static inline void arch_reset(char mode)
47{
48 /*
49 * Reset the internal bus (warning both cores are reset)
50 */
51 u32 cp_flags = iop13xx_cp6_save();
52 write_wdtcr(IOP13XX_WDTCR_EN_ARM);
53 write_wdtcr(IOP13XX_WDTCR_EN);
54 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
55 write_wdtcr(0x1000);
56 iop13xx_cp6_restore(cp_flags);
57
58 for(;;);
59}
diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h
new file mode 100644
index 000000000000..f0c51dd97ed8
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/timex.h
@@ -0,0 +1,3 @@
1#include <asm/hardware.h>
2
3#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
new file mode 100644
index 000000000000..b9525d59b7ad
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/uncompress.h
@@ -0,0 +1,24 @@
1#include <asm/types.h>
2#include <linux/serial_reg.h>
3#include <asm/hardware.h>
4#include <asm/processor.h>
5
6#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
7#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
8
9static inline void putc(char c)
10{
11 while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
12 cpu_relax();
13 UART_BASE[UART_TX] = c;
14}
15
16static inline void flush(void)
17{
18}
19
20/*
21 * nothing to do
22 */
23#define arch_decomp_setup()
24#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/include/asm-arm/arch-iop13xx/vmalloc.h
new file mode 100644
index 000000000000..c53456740345
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/vmalloc.h
@@ -0,0 +1,4 @@
1#ifndef _VMALLOC_H_
2#define _VMALLOC_H_
3#define VMALLOC_END 0xfa000000UL
4#endif
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h
index 4281838873ef..6b437f7c9955 100644
--- a/include/asm-arm/arch-ixp4xx/nslu2.h
+++ b/include/asm-arm/arch-ixp4xx/nslu2.h
@@ -76,6 +76,7 @@
76 76
77#define NSLU2_GPIO_BUZZ 4 77#define NSLU2_GPIO_BUZZ 4
78#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ) 78#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ)
79
79/* LEDs */ 80/* LEDs */
80 81
81#define NSLU2_LED_RED NSLU2_GPIO0 82#define NSLU2_LED_RED NSLU2_GPIO0
@@ -84,8 +85,8 @@
84#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED) 85#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED)
85#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN) 86#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN)
86 87
87#define NSLU2_LED_DISK1 NSLU2_GPIO2 88#define NSLU2_LED_DISK1 NSLU2_GPIO3
88#define NSLU2_LED_DISK2 NSLU2_GPIO3 89#define NSLU2_LED_DISK2 NSLU2_GPIO2
89 90
90#define NSLU2_LED_DISK1_BM (1L << NSLU2_GPIO2) 91#define NSLU2_LED_DISK1_BM (1L << NSLU2_GPIO2)
91#define NSLU2_LED_DISK2_BM (1L << NSLU2_GPIO3) 92#define NSLU2_LED_DISK2_BM (1L << NSLU2_GPIO3)
diff --git a/include/asm-arm/arch-ixp4xx/udc.h b/include/asm-arm/arch-ixp4xx/udc.h
new file mode 100644
index 000000000000..dbdec36ff0d1
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/udc.h
@@ -0,0 +1,8 @@
1/*
2 * linux/include/asm-arm/arch-ixp4xx/udc.h
3 *
4 */
5#include <asm/mach/udc_pxa2xx.h>
6
7extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
8
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index d744d97c18a5..645dbdfb3908 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -17,59 +17,11 @@
17/* 17/*
18 * There are not real ISA nor PCI buses, so we fake it. 18 * There are not real ISA nor PCI buses, so we fake it.
19 */ 19 */
20#define __io_pci(a) ((void __iomem *)(PCIO_BASE + (a))) 20static inline void __iomem *__io(unsigned long addr)
21#define __mem_pci(a) (a)
22
23#define __ioaddr(p) __io_pci(p)
24
25/*
26 * Generic virtual read/write
27 */
28#define __arch_getb(a) (*(volatile unsigned char *)(a))
29#define __arch_getl(a) (*(volatile unsigned int *)(a))
30
31static inline unsigned int __arch_getw(unsigned long a)
32{
33 unsigned int value;
34 __asm__ __volatile__("ldrh %0, [%1, #0] @ getw"
35 : "=&r" (value)
36 : "r" (a) : "cc");
37 return value;
38}
39
40#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
41#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
42
43static inline void __arch_putw(unsigned int value, unsigned long a)
44{ 21{
45 __asm__ __volatile__("strh %0, [%1, #0] @ putw" 22 return (void __iomem *)addr;
46 : : "r" (value), "r" (a) : "cc");
47} 23}
48 24#define __io(a) __io(a)
49/* 25#define __mem_pci(a) (a)
50 * Translated address IO functions
51 *
52 * IO address has already been translated to a virtual address
53 */
54#define outb_t(v,p) (*(volatile unsigned char *)(p) = (v))
55#define inb_t(p) (*(volatile unsigned char *)(p))
56#define outw_t(v,p) (*(volatile unsigned int *)(p) = (v))
57#define inw_t(p) (*(volatile unsigned int *)(p))
58#define outl_t(v,p) (*(volatile unsigned long *)(p) = (v))
59#define inl_t(p) (*(volatile unsigned long *)(p))
60
61/*
62 * FIXME - These are to allow for linking. On all the other
63 * ARM platforms, the entire IO space is contiguous.
64 * The 7200 has three separate IO spaces. The below
65 * macros will eventually become more involved. Use
66 * with caution and don't be surprised by kernel oopses!!!
67 */
68#define inb(p) inb_t(p)
69#define inw(p) inw_t(p)
70#define inl(p) inl_t(p)
71#define outb(v,p) outb_t(v,p)
72#define outw(v,p) outw_t(v,p)
73#define outl(v,p) outl_t(v,p)
74 26
75#endif 27#endif
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
index 9f1a58cbf407..9b0c8012e713 100644
--- a/include/asm-arm/arch-lh7a40x/memory.h
+++ b/include/asm-arm/arch-lh7a40x/memory.h
@@ -58,18 +58,6 @@
58#endif 58#endif
59 59
60/* 60/*
61 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
62 * and return the mem_map of that node.
63 */
64# define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
65
66/*
67 * Given a page frame number, find the owning node of the memory
68 * and return the mem_map of that node.
69 */
70# define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
71
72/*
73 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory 61 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
74 * and returns the index corresponding to the appropriate page in the 62 * and returns the index corresponding to the appropriate page in the
75 * node's mem_map. 63 * node's mem_map.
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index eaf6d43939e9..e17f9881faf0 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -27,7 +27,6 @@
27#define __virt_to_bus(x) __virt_to_phys(x) 27#define __virt_to_bus(x) __virt_to_phys(x)
28#define __bus_to_virt(x) __phys_to_virt(x) 28#define __bus_to_virt(x) __phys_to_virt(x)
29 29
30#ifdef CONFIG_DISCONTIGMEM
31/* 30/*
32 * The nodes are matched with the physical SDRAM banks as follows: 31 * The nodes are matched with the physical SDRAM banks as follows:
33 * 32 *
@@ -35,38 +34,9 @@
35 * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff 34 * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff
36 * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff 35 * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff
37 * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff 36 * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff
37 *
38 * This needs a node mem size of 26 bits.
38 */ 39 */
39 40#define NODE_MEM_SIZE_BITS 26
40/*
41 * Given a kernel address, find the home node of the underlying memory.
42 */
43#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26)
44
45/*
46 * Given a page frame number, convert it to a node id.
47 */
48#define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
49
50/*
51 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
52 * and returns the mem_map of that node.
53 */
54#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
55
56/*
57 * Given a page frame number, find the owning node of the memory
58 * and returns the mem_map of that node.
59 */
60#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
61
62/*
63 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
64 * and returns the index corresponding to the appropriate page in the
65 * node's mem_map.
66 */
67#define LOCAL_MAP_NR(addr) \
68 (((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT)
69
70#endif
71 41
72#endif 42#endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index cff752f35230..083e03c5639f 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -99,7 +99,7 @@
99#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ 99#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
100#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ 100#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
101#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ 101#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
102#define DCSR_ENRINTR (1 << 9) /* The end of Receive */ 102#define DCSR_EORINTR (1 << 9) /* The end of Receive */
103#endif 103#endif
104#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ 104#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
105#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ 105#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
@@ -803,12 +803,11 @@
803#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ 803#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
804#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ 804#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
805#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) 805#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
806#define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */ 806#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
807#define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */ 807#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
808#define UDCISR1_IERU (1 << 29) /* IntEn - Resume */ 808#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
809#define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */ 809#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
810#define UDCISR1_IERS (1 << 27) /* IntEn - Reset */ 810#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
811
812 811
813#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ 812#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
814#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ 813#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
diff --git a/include/asm-arm/arch-s3c2410/h1940.h b/include/asm-arm/arch-s3c2410/h1940.h
new file mode 100644
index 000000000000..6135592e60f2
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/h1940.h
@@ -0,0 +1,21 @@
1/* linux/include/asm-arm/arch-s3c2410/h1940.h
2 *
3 * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
4 *
5 * H1940 definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_H1940_H
13#define __ASM_ARCH_H1940_H
14
15#define H1940_SUSPEND_CHECKSUM (0x30003ff8)
16#define H1940_SUSPEND_RESUMEAT (0x30081000)
17#define H1940_SUSPEND_CHECK (0x30080000)
18
19extern void h1940_pm_return(void);
20
21#endif /* __ASM_ARCH_H1940_H */
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 718246d85952..4f72a853a5cf 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -71,7 +71,7 @@ arch_reset(char mode)
71 71
72 /* set the watchdog to go and reset... */ 72 /* set the watchdog to go and reset... */
73 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | 73 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
74 S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); 74 S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
75 75
76 /* wait for reset to assert... */ 76 /* wait for reset to assert... */
77 mdelay(5000); 77 mdelay(5000);
diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h
deleted file mode 100644
index 3f37ca07806d..000000000000
--- a/include/asm-arm/arch-sa1100/jornada720.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-sa1100/jornada720.h
3 *
4 * Created 2000/11/29 by John Ankcorn <jca@lcs.mit.edu>
5 *
6 * This file contains the hardware specific definitions for HP Jornada 720
7 *
8 */
9
10#ifndef __ASM_ARCH_HARDWARE_H
11#error "include <asm/hardware.h> instead"
12#endif
13
14#define SA1111_BASE (0x40000000)
15
16#define GPIO_JORNADA720_KEYBOARD GPIO_GPIO(0)
17#define GPIO_JORNADA720_MOUSE GPIO_GPIO(9)
18
19#define GPIO_JORNADA720_KEYBOARD_IRQ IRQ_GPIO0
20#define GPIO_JORNADA720_MOUSE_IRQ IRQ_GPIO9
21
22/* MCU COMMANDS */
23#define MCU_GetBatteryData 0xc0
24#define MCU_GetScanKeyCode 0x90
25#define MCU_GetTouchSamples 0xa0
26#define MCU_GetContrast 0xD0
27#define MCU_SetContrast 0xD1
28#define MCU_GetBrightness 0xD2
29#define MCU_SetBrightness 0xD3
30#define MCU_ContrastOff 0xD8
31#define MCU_BrightnessOff 0xD9
32#define MCU_PWMOFF 0xDF
33#define MCU_TxDummy 0x11
34#define MCU_ErrorCode 0x00
35
36#ifndef __ASSEMBLY__
37
38void jornada720_mcu_init(void);
39void jornada_contrast(int arg_contrast);
40void jornada720_battery(void);
41int jornada720_getkey(unsigned char *data, int size);
42#endif
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
index 1ff172dc8e33..0e907fc6d42a 100644
--- a/include/asm-arm/arch-sa1100/memory.h
+++ b/include/asm-arm/arch-sa1100/memory.h
@@ -39,7 +39,6 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
39#define __virt_to_bus(x) __virt_to_phys(x) 39#define __virt_to_bus(x) __virt_to_phys(x)
40#define __bus_to_virt(x) __phys_to_virt(x) 40#define __bus_to_virt(x) __phys_to_virt(x)
41 41
42#ifdef CONFIG_DISCONTIGMEM
43/* 42/*
44 * Because of the wide memory address space between physical RAM banks on the 43 * Because of the wide memory address space between physical RAM banks on the
45 * SA1100, it's much convenient to use Linux's NUMA support to implement our 44 * SA1100, it's much convenient to use Linux's NUMA support to implement our
@@ -57,38 +56,7 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
57 * node 2: 0xd0000000 - 0xd7ffffff 56 * node 2: 0xd0000000 - 0xd7ffffff
58 * node 3: 0xd8000000 - 0xdfffffff 57 * node 3: 0xd8000000 - 0xdfffffff
59 */ 58 */
60 59#define NODE_MEM_SIZE_BITS 27
61/*
62 * Given a kernel address, find the home node of the underlying memory.
63 */
64#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 27)
65
66/*
67 * Given a page frame number, convert it to a node id.
68 */
69#define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (27 - PAGE_SHIFT))
70
71/*
72 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
73 * and return the mem_map of that node.
74 */
75#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
76
77/*
78 * Given a page frame number, find the owning node of the memory
79 * and return the mem_map of that node.
80 */
81#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
82
83/*
84 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
85 * and returns the index corresponding to the appropriate page in the
86 * node's mem_map.
87 */
88#define LOCAL_MAP_NR(addr) \
89 (((unsigned long)(addr) & 0x07ffffff) >> PAGE_SHIFT)
90
91#endif
92 60
93/* 61/*
94 * Cache flushing area - SA1100 zero bank 62 * Cache flushing area - SA1100 zero bank
diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h
index 0e36fd5d87df..7b62351f097d 100644
--- a/include/asm-arm/bug.h
+++ b/include/asm-arm/bug.h
@@ -4,10 +4,10 @@
4 4
5#ifdef CONFIG_BUG 5#ifdef CONFIG_BUG
6#ifdef CONFIG_DEBUG_BUGVERBOSE 6#ifdef CONFIG_DEBUG_BUGVERBOSE
7extern void __bug(const char *file, int line, void *data) __attribute__((noreturn)); 7extern void __bug(const char *file, int line) __attribute__((noreturn));
8 8
9/* give file/line information */ 9/* give file/line information */
10#define BUG() __bug(__FILE__, __LINE__, NULL) 10#define BUG() __bug(__FILE__, __LINE__)
11 11
12#else 12#else
13 13
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index 17f0c656d272..642382d2c9f0 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -1,17 +1,22 @@
1#ifndef __ASMARM_ELF_H 1#ifndef __ASMARM_ELF_H
2#define __ASMARM_ELF_H 2#define __ASMARM_ELF_H
3 3
4 4#ifndef __ASSEMBLY__
5/* 5/*
6 * ELF register definitions.. 6 * ELF register definitions..
7 */ 7 */
8
9#include <asm/ptrace.h> 8#include <asm/ptrace.h>
10#include <asm/user.h> 9#include <asm/user.h>
11 10
12typedef unsigned long elf_greg_t; 11typedef unsigned long elf_greg_t;
13typedef unsigned long elf_freg_t[3]; 12typedef unsigned long elf_freg_t[3];
14 13
14#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
15typedef elf_greg_t elf_gregset_t[ELF_NGREG];
16
17typedef struct user_fp elf_fpregset_t;
18#endif
19
15#define EM_ARM 40 20#define EM_ARM 40
16#define EF_ARM_APCS26 0x08 21#define EF_ARM_APCS26 0x08
17#define EF_ARM_SOFT_FLOAT 0x200 22#define EF_ARM_SOFT_FLOAT 0x200
@@ -23,11 +28,6 @@ typedef unsigned long elf_freg_t[3];
23#define R_ARM_CALL 28 28#define R_ARM_CALL 28
24#define R_ARM_JUMP24 29 29#define R_ARM_JUMP24 29
25 30
26#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
27typedef elf_greg_t elf_gregset_t[ELF_NGREG];
28
29typedef struct user_fp elf_fpregset_t;
30
31/* 31/*
32 * These are used to set parameters in the core dumps. 32 * These are used to set parameters in the core dumps.
33 */ 33 */
@@ -39,97 +39,99 @@ typedef struct user_fp elf_fpregset_t;
39#endif 39#endif
40#define ELF_ARCH EM_ARM 40#define ELF_ARCH EM_ARM
41 41
42#ifdef __KERNEL__
43#include <asm/procinfo.h>
44
45/* 42/*
46 * This is used to ensure we don't load something for the wrong architecture. 43 * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
47 */ 44 */
48#define elf_check_arch(x) ( ((x)->e_machine == EM_ARM) && (ELF_PROC_OK((x))) ) 45#define HWCAP_SWP 1
49 46#define HWCAP_HALF 2
50#define USE_ELF_CORE_DUMP 47#define HWCAP_THUMB 4
51#define ELF_EXEC_PAGESIZE 4096 48#define HWCAP_26BIT 8 /* Play it safe */
52 49#define HWCAP_FAST_MULT 16
53/* This is the location that an ET_DYN program is loaded if exec'ed. Typical 50#define HWCAP_FPA 32
54 use of this is to invoke "./ld.so someprog" to test out a new version of 51#define HWCAP_VFP 64
55 the loader. We need to make sure that it is out of the way of the program 52#define HWCAP_EDSP 128
56 that it will "exec", and that there is sufficient room for the brk. */ 53#define HWCAP_JAVA 256
57 54#define HWCAP_IWMMXT 512
58#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
59
60/* When the program starts, a1 contains a pointer to a function to be
61 registered with atexit, as per the SVR4 ABI. A value of 0 means we
62 have no such handler. */
63#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0
64
65/* This yields a mask that user programs can use to figure out what
66 instruction set this cpu supports. */
67 55
56#ifdef __KERNEL__
57#ifndef __ASSEMBLY__
58/*
59 * This yields a mask that user programs can use to figure out what
60 * instruction set this cpu supports.
61 */
68#define ELF_HWCAP (elf_hwcap) 62#define ELF_HWCAP (elf_hwcap)
63extern unsigned int elf_hwcap;
69 64
70/* This yields a string that ld.so will use to load implementation 65/*
71 specific libraries for optimization. This is more specific in 66 * This yields a string that ld.so will use to load implementation
72 intent than poking at uname or /proc/cpuinfo. */ 67 * specific libraries for optimization. This is more specific in
73 68 * intent than poking at uname or /proc/cpuinfo.
74/* For now we just provide a fairly general string that describes the 69 *
75 processor family. This could be made more specific later if someone 70 * For now we just provide a fairly general string that describes the
76 implemented optimisations that require it. 26-bit CPUs give you 71 * processor family. This could be made more specific later if someone
77 "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't 72 * implemented optimisations that require it. 26-bit CPUs give you
78 supported). 32-bit CPUs give you "v3[lb]" for anything based on an 73 * "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't
79 ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1 74 * supported). 32-bit CPUs give you "v3[lb]" for anything based on an
80 core. */ 75 * ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1
81 76 * core.
77 */
82#define ELF_PLATFORM_SIZE 8 78#define ELF_PLATFORM_SIZE 8
83extern char elf_platform[];
84#define ELF_PLATFORM (elf_platform) 79#define ELF_PLATFORM (elf_platform)
85 80
81extern char elf_platform[];
82#endif
83
84/*
85 * This is used to ensure we don't load something for the wrong architecture.
86 */
87#define elf_check_arch(x) ((x)->e_machine == EM_ARM && ELF_PROC_OK(x))
88
86/* 89/*
87 * 32-bit code is always OK. Some cpus can do 26-bit, some can't. 90 * 32-bit code is always OK. Some cpus can do 26-bit, some can't.
88 */ 91 */
89#define ELF_PROC_OK(x) (ELF_THUMB_OK(x) && ELF_26BIT_OK(x)) 92#define ELF_PROC_OK(x) (ELF_THUMB_OK(x) && ELF_26BIT_OK(x))
90 93
91#define ELF_THUMB_OK(x) \ 94#define ELF_THUMB_OK(x) \
92 (( (elf_hwcap & HWCAP_THUMB) && ((x)->e_entry & 1) == 1) || \ 95 ((elf_hwcap & HWCAP_THUMB && ((x)->e_entry & 1) == 1) || \
93 ((x)->e_entry & 3) == 0) 96 ((x)->e_entry & 3) == 0)
94 97
95#define ELF_26BIT_OK(x) \ 98#define ELF_26BIT_OK(x) \
96 (( (elf_hwcap & HWCAP_26BIT) && (x)->e_flags & EF_ARM_APCS26) || \ 99 ((elf_hwcap & HWCAP_26BIT && (x)->e_flags & EF_ARM_APCS26) || \
97 ((x)->e_flags & EF_ARM_APCS26) == 0) 100 ((x)->e_flags & EF_ARM_APCS26) == 0)
98 101
99#ifndef CONFIG_IWMMXT 102#define USE_ELF_CORE_DUMP
103#define ELF_EXEC_PAGESIZE 4096
100 104
101/* Old NetWinder binaries were compiled in such a way that the iBCS 105/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
102 heuristic always trips on them. Until these binaries become uncommon 106 use of this is to invoke "./ld.so someprog" to test out a new version of
103 enough not to care, don't trust the `ibcs' flag here. In any case 107 the loader. We need to make sure that it is out of the way of the program
104 there is no other ELF system currently supported by iBCS. 108 that it will "exec", and that there is sufficient room for the brk. */
105 @@ Could print a warning message to encourage users to upgrade. */
106#define SET_PERSONALITY(ex,ibcs2) \
107 set_personality(((ex).e_flags&EF_ARM_APCS26 ?PER_LINUX :PER_LINUX_32BIT))
108 109
109#else 110#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
111
112/* When the program starts, a1 contains a pointer to a function to be
113 registered with atexit, as per the SVR4 ABI. A value of 0 means we
114 have no such handler. */
115#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0
110 116
111/* 117/*
112 * All iWMMXt capable CPUs don't support 26-bit mode. Yet they can run 118 * Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0
113 * legacy binaries which used to contain FPA11 floating point instructions 119 * and CP1, we only enable access to the iWMMXt coprocessor if the
114 * that have always been emulated by the kernel. PFA11 and iWMMXt overlap 120 * binary is EABI or softfloat (and thus, guaranteed not to use
115 * on coprocessor 1 space though. We therefore must decide if given task 121 * FPA instructions.)
116 * is allowed to use CP 0 and 1 for iWMMXt, or if they should be blocked
117 * at all times for the prefetch exception handler to catch FPA11 opcodes
118 * and emulate them. The best indication to discriminate those two cases
119 * is the SOFT_FLOAT flag in the ELF header.
120 */ 122 */
121 123#define SET_PERSONALITY(ex, ibcs2) \
122#define SET_PERSONALITY(ex,ibcs2) \ 124 do { \
123do { \ 125 if ((ex).e_flags & EF_ARM_APCS26) { \
124 set_personality(PER_LINUX_32BIT); \ 126 set_personality(PER_LINUX); \
125 if (((ex).e_flags & EF_ARM_EABI_MASK) || \ 127 } else { \
126 ((ex).e_flags & EF_ARM_SOFT_FLOAT)) \ 128 set_personality(PER_LINUX_32BIT); \
127 set_thread_flag(TIF_USING_IWMMXT); \ 129 if (elf_hwcap & HWCAP_IWMMXT && (ex).e_flags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) \
128 else \ 130 set_thread_flag(TIF_USING_IWMMXT); \
129 clear_thread_flag(TIF_USING_IWMMXT); \ 131 else \
130} while (0) 132 clear_thread_flag(TIF_USING_IWMMXT); \
131 133 } \
132#endif 134 } while (0)
133 135
134#endif 136#endif
135 137
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index ae999fd5dc67..288f76b166d0 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -75,14 +75,6 @@ extern void __readwrite_bug(const char *fn);
75 */ 75 */
76#include <asm/arch/io.h> 76#include <asm/arch/io.h>
77 77
78#ifdef __io_pci
79#warning machine class uses buggy __io_pci
80#endif
81#if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \
82 defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl)
83#warning machine class uses old __arch_putw or __arch_getw
84#endif
85
86/* 78/*
87 * IO port access primitives 79 * IO port access primitives
88 * ------------------------- 80 * -------------------------
diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h
index 0e017ecf2096..eb0bfba6570d 100644
--- a/include/asm-arm/mach/irq.h
+++ b/include/asm-arm/mach/irq.h
@@ -22,12 +22,6 @@ extern void init_FIQ(void);
22extern int show_fiq_list(struct seq_file *, void *); 22extern int show_fiq_list(struct seq_file *, void *);
23 23
24/* 24/*
25 * Function wrappers
26 */
27#define set_irq_chipdata(irq, d) set_irq_chip_data(irq, d)
28#define get_irq_chipdata(irq) get_irq_chip_data(irq)
29
30/*
31 * Obsolete inline function for calling irq descriptor handlers. 25 * Obsolete inline function for calling irq descriptor handlers.
32 */ 26 */
33static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc) 27static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc)
@@ -44,12 +38,6 @@ void set_irq_flags(unsigned int irq, unsigned int flags);
44/* 38/*
45 * This is for easy migration, but should be changed in the source 39 * This is for easy migration, but should be changed in the source
46 */ 40 */
47#define do_level_IRQ handle_level_irq
48#define do_edge_IRQ handle_edge_irq
49#define do_simple_IRQ handle_simple_irq
50#define irqdesc irq_desc
51#define irqchip irq_chip
52
53#define do_bad_IRQ(irq,desc) \ 41#define do_bad_IRQ(irq,desc) \
54do { \ 42do { \
55 spin_lock(&desc->lock); \ 43 spin_lock(&desc->lock); \
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index 91d536c215d7..d9bfb39adabf 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -215,6 +215,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
215 * virt_addr_valid(k) indicates whether a virtual address is valid 215 * virt_addr_valid(k) indicates whether a virtual address is valid
216 */ 216 */
217#ifndef CONFIG_DISCONTIGMEM 217#ifndef CONFIG_DISCONTIGMEM
218
218#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET 219#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET
219#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) 220#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
220 221
@@ -230,6 +231,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
230 * around in memory. 231 * around in memory.
231 */ 232 */
232#include <linux/numa.h> 233#include <linux/numa.h>
234
233#define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn) 235#define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn)
234#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT) 236#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
235 237
@@ -256,6 +258,43 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
256 */ 258 */
257#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) 259#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT)
258 260
261/*
262 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
263 * and returns the mem_map of that node.
264 */
265#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
266
267/*
268 * Given a page frame number, find the owning node of the memory
269 * and returns the mem_map of that node.
270 */
271#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
272
273#ifdef NODE_MEM_SIZE_BITS
274#define NODE_MEM_SIZE_MASK ((1 << NODE_MEM_SIZE_BITS) - 1)
275
276/*
277 * Given a kernel address, find the home node of the underlying memory.
278 */
279#define KVADDR_TO_NID(addr) \
280 (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS)
281
282/*
283 * Given a page frame number, convert it to a node id.
284 */
285#define PFN_TO_NID(pfn) \
286 (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT))
287
288/*
289 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
290 * and returns the index corresponding to the appropriate page in the
291 * node's mem_map.
292 */
293#define LOCAL_MAP_NR(addr) \
294 (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT)
295
296#endif /* NODE_MEM_SIZE_BITS */
297
259#endif /* !CONFIG_DISCONTIGMEM */ 298#endif /* !CONFIG_DISCONTIGMEM */
260 299
261/* 300/*
diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h
index c1b264dff287..7b1c9acdf79a 100644
--- a/include/asm-arm/pgtable-nommu.h
+++ b/include/asm-arm/pgtable-nommu.h
@@ -44,7 +44,6 @@
44#define PAGE_READONLY __pgprot(0) 44#define PAGE_READONLY __pgprot(0)
45#define PAGE_KERNEL __pgprot(0) 45#define PAGE_KERNEL __pgprot(0)
46 46
47//extern void paging_init(struct meminfo *, struct machine_desc *);
48#define swapper_pg_dir ((pgd_t *) 0) 47#define swapper_pg_dir ((pgd_t *) 0)
49 48
50#define __swp_type(x) (0) 49#define __swp_type(x) (0)
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index ed8cb5963e99..88cd5c784ef0 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -169,8 +169,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
169#define L_PTE_WRITE (1 << 5) 169#define L_PTE_WRITE (1 << 5)
170#define L_PTE_EXEC (1 << 6) 170#define L_PTE_EXEC (1 << 6)
171#define L_PTE_DIRTY (1 << 7) 171#define L_PTE_DIRTY (1 << 7)
172#define L_PTE_COHERENT (1 << 9) /* I/O coherent (xsc3) */ 172#define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */
173#define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */
174#define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */ 173#define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */
175 174
176#ifndef __ASSEMBLY__ 175#ifndef __ASSEMBLY__
diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h
index 04f4d34c6317..b442e8e2a809 100644
--- a/include/asm-arm/processor.h
+++ b/include/asm-arm/processor.h
@@ -20,7 +20,6 @@
20#ifdef __KERNEL__ 20#ifdef __KERNEL__
21 21
22#include <asm/ptrace.h> 22#include <asm/ptrace.h>
23#include <asm/procinfo.h>
24#include <asm/types.h> 23#include <asm/types.h>
25 24
26union debug_insn { 25union debug_insn {
diff --git a/include/asm-arm/procinfo.h b/include/asm-arm/procinfo.h
index 91a31adfa8a8..4d3c685075e0 100644
--- a/include/asm-arm/procinfo.h
+++ b/include/asm-arm/procinfo.h
@@ -10,7 +10,7 @@
10#ifndef __ASM_PROCINFO_H 10#ifndef __ASM_PROCINFO_H
11#define __ASM_PROCINFO_H 11#define __ASM_PROCINFO_H
12 12
13#ifndef __ASSEMBLY__ 13#ifdef __KERNEL__
14 14
15struct cpu_tlb_fns; 15struct cpu_tlb_fns;
16struct cpu_user_fns; 16struct cpu_user_fns;
@@ -42,19 +42,8 @@ struct proc_info_list {
42 struct cpu_cache_fns *cache; 42 struct cpu_cache_fns *cache;
43}; 43};
44 44
45extern unsigned int elf_hwcap; 45#else /* __KERNEL__ */
46 46#include <asm/elf.h>
47#endif /* __ASSEMBLY__ */ 47#warning "Please include asm/elf.h instead"
48 48#endif /* __KERNEL__ */
49#define HWCAP_SWP 1
50#define HWCAP_HALF 2
51#define HWCAP_THUMB 4
52#define HWCAP_26BIT 8 /* Play it safe */
53#define HWCAP_FAST_MULT 16
54#define HWCAP_FPA 32
55#define HWCAP_VFP 64
56#define HWCAP_EDSP 128
57#define HWCAP_JAVA 256
58#define HWCAP_IWMMXT 512
59
60#endif 49#endif
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index f28b236139ed..d9b8bddc8732 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -94,8 +94,18 @@ static inline struct thread_info *current_thread_info(void)
94 return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); 94 return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
95} 95}
96 96
97extern struct thread_info *alloc_thread_info(struct task_struct *task); 97/* thread information allocation */
98extern void free_thread_info(struct thread_info *); 98#ifdef CONFIG_DEBUG_STACK_USAGE
99#define alloc_thread_info(tsk) \
100 ((struct thread_info *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, \
101 THREAD_SIZE_ORDER))
102#else
103#define alloc_thread_info(tsk) \
104 ((struct thread_info *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER))
105#endif
106
107#define free_thread_info(info) \
108 free_pages((unsigned long)info, THREAD_SIZE_ORDER);
99 109
100#define thread_saved_pc(tsk) \ 110#define thread_saved_pc(tsk) \
101 ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc))) 111 ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc)))
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h b/include/asm-avr32/arch-at32ap/at91_pdc.h
index ce1150d4438d..79d6e02fa45e 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+++ b/include/asm-avr32/arch-at32ap/at91_pdc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h 2 * include/asm-arm/arch-at91rm9200/at91_pdc.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
@@ -13,8 +13,8 @@
13 * (at your option) any later version. 13 * (at your option) any later version.
14 */ 14 */
15 15
16#ifndef AT91RM9200_PDC_H 16#ifndef AT91_PDC_H
17#define AT91RM9200_PDC_H 17#define AT91_PDC_H
18 18
19#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ 19#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
20#define AT91_PDC_RCR 0x104 /* Receive Counter Register */ 20#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
diff --git a/include/linux/i2c-pxa.h b/include/linux/i2c-pxa.h
index 5f3eaf802223..41dcdfe7f625 100644
--- a/include/linux/i2c-pxa.h
+++ b/include/linux/i2c-pxa.h
@@ -1,29 +1,6 @@
1#ifndef _LINUX_I2C_ALGO_PXA_H 1#ifndef _LINUX_I2C_ALGO_PXA_H
2#define _LINUX_I2C_ALGO_PXA_H 2#define _LINUX_I2C_ALGO_PXA_H
3 3
4struct i2c_eeprom_emu_watcher {
5 void (*write)(void *, unsigned int addr, unsigned char newval);
6};
7
8struct i2c_eeprom_emu_watch {
9 struct list_head node;
10 unsigned int start;
11 unsigned int end;
12 struct i2c_eeprom_emu_watcher *ops;
13 void *data;
14};
15
16#define I2C_EEPROM_EMU_SIZE (256)
17
18struct i2c_eeprom_emu {
19 unsigned int size;
20 unsigned int ptr;
21 unsigned int seen_start;
22 struct list_head watch;
23
24 unsigned char bytes[I2C_EEPROM_EMU_SIZE];
25};
26
27typedef enum i2c_slave_event_e { 4typedef enum i2c_slave_event_e {
28 I2C_SLAVE_EVENT_START_READ, 5 I2C_SLAVE_EVENT_START_READ,
29 I2C_SLAVE_EVENT_START_WRITE, 6 I2C_SLAVE_EVENT_START_WRITE,
@@ -37,12 +14,4 @@ struct i2c_slave_client {
37 void (*write)(void *ptr, unsigned int val); 14 void (*write)(void *ptr, unsigned int val);
38}; 15};
39 16
40extern int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *, void *data,
41 unsigned int addr, unsigned int size,
42 struct i2c_eeprom_emu_watcher *);
43
44extern void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *, void *data, struct i2c_eeprom_emu_watcher *watcher);
45
46extern struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void);
47
48#endif /* _LINUX_I2C_ALGO_PXA_H */ 17#endif /* _LINUX_I2C_ALGO_PXA_H */