215 files changed, 6221 insertions, 1259 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 43bd17bfc381..8c05d4321ae9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -223,6 +223,12 @@ config ARCH_IOP33X
        help
          Support for Intel's IOP33X (XScale) family of processors.
+config ARCH_IOP13XX
+        bool "IOP13xx-based"
+        select PCI
+        help
+          Support for Intel's IOP13XX (XScale) family of processors.
 config ARCH_IXP4XX
        bool "IXP4xx-based"
        depends on MMU
@@ -331,6 +337,8 @@ source "arch/arm/mach-iop32x/Kconfig"
 source "arch/arm/mach-iop33x/Kconfig"
+source "arch/arm/mach-iop13xx/Kconfig"
 source "arch/arm/mach-ixp4xx/Kconfig"
 source "arch/arm/mach-ixp2000/Kconfig"
@@ -374,6 +382,14 @@ config PLAT_IOP
 source arch/arm/mm/Kconfig
+config IWMMXT
+        bool "Enable iWMMXt support"
+        depends CPU_XSCALE || CPU_XSC3
+        default y if PXA27x
+        help
+          Enable support for iWMMXt context switching at run time if
+          running on a CPU that supports it.
 #  bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
 config XSCALE_PMU
        bool
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index d22f38b957db..40c5eb1f55c7 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -32,10 +32,6 @@ config DEBUG_USER
              8 - SIGSEGV faults
             16 - SIGBUS faults
-config DEBUG_WAITQ
-        bool "Wait queue debugging"
-        depends on DEBUG_KERNEL
 config DEBUG_ERRORS
        bool "Verbose kernel error messages"
        depends on DEBUG_KERNEL
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6f4f8bf36071..000f1100b553 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -15,6 +15,8 @@ CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
 OBJCOPYFLAGS    :=-O binary -R .note -R .comment -S
 GZFLAGS         :=-9
 #CFLAGS         +=-pipe
+# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
+CFLAGS          +=$(call cc-option,-marm,)
 # Do not use arch/arm/defconfig - it's always outdated.
 # Select a platform tht is kept up-to-date
@@ -108,6 +110,7 @@ endif
 machine-$(CONFIG_ARCH_CLPS711X)   := clps711x
 machine-$(CONFIG_ARCH_IOP32X)     := iop32x
 machine-$(CONFIG_ARCH_IOP33X)     := iop33x
+ machine-$(CONFIG_ARCH_IOP13XX)    := iop13xx
 machine-$(CONFIG_ARCH_IXP4XX)     := ixp4xx
 machine-$(CONFIG_ARCH_IXP2000)    := ixp2000
 machine-$(CONFIG_ARCH_IXP23XX)    := ixp23xx
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index f3e020f2227f..09b9d1b6844c 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -160,7 +160,7 @@ void __init gic_dist_init(void __iomem *base)
         */
        for (i = 29; i < max_irq; i++) {
                set_irq_chip(i, &gic_chip);
-                set_irq_handler(i, do_level_IRQ);
+                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
        }
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 80a72c75214f..cfe6f4650bc9 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -163,11 +163,11 @@ static struct locomo_dev_info locomo_devices[] = {
 #define LOCOMO_IRQ_LT_START     (IRQ_LOCOMO_LT)
 #define LOCOMO_IRQ_SPI_START    (IRQ_LOCOMO_SPI_RFR)
-static void locomo_handler(unsigned int irq, struct irqdesc *desc)
+static void locomo_handler(unsigned int irq, struct irq_desc *desc)
 {
        int req, i;
-        struct irqdesc *d;
+        struct irq_desc *d;
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        /* Acknowledge the parent IRQ */
        desc->chip->ack(irq);
@@ -194,7 +194,7 @@ static void locomo_ack_irq(unsigned int irq)
 static void locomo_mask_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_ICR);
        r &= ~(0x0010 << (irq - LOCOMO_IRQ_START));
@@ -203,7 +203,7 @@ static void locomo_mask_irq(unsigned int irq)
 static void locomo_unmask_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_ICR);
        r |= (0x0010 << (irq - LOCOMO_IRQ_START));
@@ -217,10 +217,10 @@ static struct irq_chip locomo_chip = {
        .unmask = locomo_unmask_irq,
 };
-static void locomo_key_handler(unsigned int irq, struct irqdesc *desc)
+static void locomo_key_handler(unsigned int irq, struct irq_desc *desc)
 {
-        struct irqdesc *d;
+        struct irq_desc *d;
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) {
                d = irq_desc + LOCOMO_IRQ_KEY_START;
@@ -230,7 +230,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc)
 static void locomo_key_ack_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
        r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START));
@@ -239,7 +239,7 @@ static void locomo_key_ack_irq(unsigned int irq)
 static void locomo_key_mask_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
        r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@@ -248,7 +248,7 @@ static void locomo_key_mask_irq(unsigned int irq)
 static void locomo_key_unmask_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
        r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@@ -262,11 +262,11 @@ static struct irq_chip locomo_key_chip = {
        .unmask = locomo_key_unmask_irq,
 };
-static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc)
+static void locomo_gpio_handler(unsigned int irq, struct irq_desc *desc)
 {
        int req, i;
-        struct irqdesc *d;
+        struct irq_desc *d;
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        req =   locomo_readl(mapbase + LOCOMO_GIR) &
                locomo_readl(mapbase + LOCOMO_GPD) &
@@ -285,7 +285,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc)
 static void locomo_gpio_ack_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_GWE);
        r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -302,7 +302,7 @@ static void locomo_gpio_ack_irq(unsigned int irq)
 static void locomo_gpio_mask_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_GIE);
        r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -311,7 +311,7 @@ static void locomo_gpio_mask_irq(unsigned int irq)
 static void locomo_gpio_unmask_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_GIE);
        r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -325,10 +325,10 @@ static struct irq_chip locomo_gpio_chip = {
        .unmask = locomo_gpio_unmask_irq,
 };
-static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc)
+static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc)
 {
-        struct irqdesc *d;
+        struct irq_desc *d;
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) {
                d = irq_desc + LOCOMO_IRQ_LT_START;
@@ -338,7 +338,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc)
 static void locomo_lt_ack_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_LTINT);
        r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START));
@@ -347,7 +347,7 @@ static void locomo_lt_ack_irq(unsigned int irq)
 static void locomo_lt_mask_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_LTINT);
        r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START));
@@ -356,7 +356,7 @@ static void locomo_lt_mask_irq(unsigned int irq)
 static void locomo_lt_unmask_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_LTINT);
        r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START));
@@ -370,11 +370,11 @@ static struct irq_chip locomo_lt_chip = {
        .unmask = locomo_lt_unmask_irq,
 };
-static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc)
+static void locomo_spi_handler(unsigned int irq, struct irq_desc *desc)
 {
        int req, i;
-        struct irqdesc *d;
+        struct irq_desc *d;
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F;
        if (req) {
@@ -391,7 +391,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc)
 static void locomo_spi_ack_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE);
        r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -408,7 +408,7 @@ static void locomo_spi_ack_irq(unsigned int irq)
 static void locomo_spi_mask_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
        r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -417,7 +417,7 @@ static void locomo_spi_mask_irq(unsigned int irq)
 static void locomo_spi_unmask_irq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned int r;
        r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
        r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -440,55 +440,55 @@ static void locomo_setup_irq(struct locomo *lchip)
         * Install handler for IRQ_LOCOMO_HW.
         */
        set_irq_type(lchip->irq, IRQT_FALLING);
-        set_irq_chipdata(lchip->irq, irqbase);
+        set_irq_chip_data(lchip->irq, irqbase);
        set_irq_chained_handler(lchip->irq, locomo_handler);
        /* Install handlers for IRQ_LOCOMO_*_BASE */
        set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip);
-        set_irq_chipdata(IRQ_LOCOMO_KEY_BASE, irqbase);
+        set_irq_chip_data(IRQ_LOCOMO_KEY_BASE, irqbase);
        set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler);
        set_irq_flags(IRQ_LOCOMO_KEY_BASE, IRQF_VALID | IRQF_PROBE);
        set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip);
-        set_irq_chipdata(IRQ_LOCOMO_GPIO_BASE, irqbase);
+        set_irq_chip_data(IRQ_LOCOMO_GPIO_BASE, irqbase);
        set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler);
        set_irq_flags(IRQ_LOCOMO_GPIO_BASE, IRQF_VALID | IRQF_PROBE);
        set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip);
-        set_irq_chipdata(IRQ_LOCOMO_LT_BASE, irqbase);
+        set_irq_chip_data(IRQ_LOCOMO_LT_BASE, irqbase);
        set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler);
        set_irq_flags(IRQ_LOCOMO_LT_BASE, IRQF_VALID | IRQF_PROBE);
        set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip);
-        set_irq_chipdata(IRQ_LOCOMO_SPI_BASE, irqbase);
+        set_irq_chip_data(IRQ_LOCOMO_SPI_BASE, irqbase);
        set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler);
        set_irq_flags(IRQ_LOCOMO_SPI_BASE, IRQF_VALID | IRQF_PROBE);
        /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */
        set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip);
-        set_irq_chipdata(LOCOMO_IRQ_KEY_START, irqbase);
+        set_irq_chip_data(LOCOMO_IRQ_KEY_START, irqbase);
-        set_irq_handler(LOCOMO_IRQ_KEY_START, do_edge_IRQ);
+        set_irq_handler(LOCOMO_IRQ_KEY_START, handle_edge_irq);
        set_irq_flags(LOCOMO_IRQ_KEY_START, IRQF_VALID | IRQF_PROBE);
        /* install handlers for IRQ_LOCOMO_GPIO_BASE generated interrupts */
        for (irq = LOCOMO_IRQ_GPIO_START; irq < LOCOMO_IRQ_GPIO_START + 16; irq++) {
                set_irq_chip(irq, &locomo_gpio_chip);
-                set_irq_chipdata(irq, irqbase);
+                set_irq_chip_data(irq, irqbase);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
        /* install handlers for IRQ_LOCOMO_LT_BASE generated interrupts */
        set_irq_chip(LOCOMO_IRQ_LT_START, &locomo_lt_chip);
-        set_irq_chipdata(LOCOMO_IRQ_LT_START, irqbase);
+        set_irq_chip_data(LOCOMO_IRQ_LT_START, irqbase);
-        set_irq_handler(LOCOMO_IRQ_LT_START, do_edge_IRQ);
+        set_irq_handler(LOCOMO_IRQ_LT_START, handle_edge_irq);
        set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE);
        /* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */
        for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 3; irq++) {
                set_irq_chip(irq, &locomo_spi_chip);
-                set_irq_chipdata(irq, irqbase);
+                set_irq_chip_data(irq, irqbase);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
 }
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index d5f72010a6f3..fe3f05901a23 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -147,7 +147,7 @@ void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *ho
 * will call us again if there are more interrupts to process.
 */
 static void
-sa1111_irq_handler(unsigned int irq, struct irqdesc *desc)
+sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        unsigned int stat0, stat1, i;
        void __iomem *base = get_irq_data(irq);
@@ -187,7 +187,7 @@ static void sa1111_ack_irq(unsigned int irq)
 static void sa1111_mask_lowirq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned long ie0;
        ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
@@ -197,7 +197,7 @@ static void sa1111_mask_lowirq(unsigned int irq)
 static void sa1111_unmask_lowirq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned long ie0;
        ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
@@ -215,7 +215,7 @@ static void sa1111_unmask_lowirq(unsigned int irq)
 static int sa1111_retrigger_lowirq(unsigned int irq)
 {
        unsigned int mask = SA1111_IRQMASK_LO(irq);
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned long ip0;
        int i;
@@ -236,7 +236,7 @@ static int sa1111_retrigger_lowirq(unsigned int irq)
 static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
 {
        unsigned int mask = SA1111_IRQMASK_LO(irq);
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned long ip0;
        if (flags == IRQT_PROBE)
@@ -259,7 +259,7 @@ static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
 static int sa1111_wake_lowirq(unsigned int irq, unsigned int on)
 {
        unsigned int mask = SA1111_IRQMASK_LO(irq);
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned long we0;
        we0 = sa1111_readl(mapbase + SA1111_WAKEEN0);
@@ -284,7 +284,7 @@ static struct irq_chip sa1111_low_chip = {
 static void sa1111_mask_highirq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned long ie1;
        ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
@@ -294,7 +294,7 @@ static void sa1111_mask_highirq(unsigned int irq)
 static void sa1111_unmask_highirq(unsigned int irq)
 {
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned long ie1;
        ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
@@ -312,7 +312,7 @@ static void sa1111_unmask_highirq(unsigned int irq)
 static int sa1111_retrigger_highirq(unsigned int irq)
 {
        unsigned int mask = SA1111_IRQMASK_HI(irq);
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned long ip1;
        int i;
@@ -333,7 +333,7 @@ static int sa1111_retrigger_highirq(unsigned int irq)
 static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
 {
        unsigned int mask = SA1111_IRQMASK_HI(irq);
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned long ip1;
        if (flags == IRQT_PROBE)
@@ -356,7 +356,7 @@ static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
 static int sa1111_wake_highirq(unsigned int irq, unsigned int on)
 {
        unsigned int mask = SA1111_IRQMASK_HI(irq);
-        void __iomem *mapbase = get_irq_chipdata(irq);
+        void __iomem *mapbase = get_irq_chip_data(irq);
        unsigned long we1;
        we1 = sa1111_readl(mapbase + SA1111_WAKEEN1);
@@ -410,15 +410,15 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
        for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
                set_irq_chip(irq, &sa1111_low_chip);
-                set_irq_chipdata(irq, irqbase);
+                set_irq_chip_data(irq, irqbase);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
        for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
                set_irq_chip(irq, &sa1111_high_chip);
-                set_irq_chipdata(irq, irqbase);
+                set_irq_chip_data(irq, irqbase);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 43d278134521..c026fa2214a3 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -27,14 +27,14 @@
 static void vic_mask_irq(unsigned int irq)
 {
-        void __iomem *base = get_irq_chipdata(irq);
+        void __iomem *base = get_irq_chip_data(irq);
        irq &= 31;
        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 }
 static void vic_unmask_irq(unsigned int irq)
 {
-        void __iomem *base = get_irq_chipdata(irq);
+        void __iomem *base = get_irq_chip_data(irq);
        irq &= 31;
        writel(1 << irq, base + VIC_INT_ENABLE);
 }
@@ -88,10 +88,10 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
                unsigned int irq = irq_start + i;
                set_irq_chip(irq, &vic_chip);
-                set_irq_chipdata(irq, base);
+                set_irq_chip_data(irq, base);
                if (vic_sources & (1 << i)) {
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
                }
        }
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
index 1d79360f3eba..e10d003566d6 100644
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ b/arch/arm/configs/at91rm9200dk_defconfig
@@ -981,7 +981,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_FRAME_POINTER=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index 16120bca3cb7..834dddb51314 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -970,7 +970,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_FRAME_POINTER=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig
index cfe6bd8e81cd..821865f75605 100644
--- a/arch/arm/configs/badge4_defconfig
+++ b/arch/arm/configs/badge4_defconfig
@@ -1216,7 +1216,6 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig
index 09b7acd7f647..ee130b528bd4 100644
--- a/arch/arm/configs/cerfcube_defconfig
+++ b/arch/arm/configs/cerfcube_defconfig
@@ -851,7 +851,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
index a3758913c0bb..970c8c772eb7 100644
--- a/arch/arm/configs/collie_defconfig
+++ b/arch/arm/configs/collie_defconfig
@@ -934,7 +934,6 @@ CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index c41c04fa5020..e8980a9bb893 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -1513,7 +1513,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_FRAME_POINTER=y
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/csb337_defconfig b/arch/arm/configs/csb337_defconfig
index 20e68250d835..2cadd51506bb 100644
--- a/arch/arm/configs/csb337_defconfig
+++ b/arch/arm/configs/csb337_defconfig
@@ -1113,7 +1113,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_FRAME_POINTER=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/csb637_defconfig b/arch/arm/configs/csb637_defconfig
index abf33520b709..94908c1df4cf 100644
--- a/arch/arm/configs/csb637_defconfig
+++ b/arch/arm/configs/csb637_defconfig
@@ -1062,7 +1062,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_FRAME_POINTER=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 3b4802a849e4..f8a66b72ad5d 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -125,6 +125,7 @@ CONFIG_CRUNCH=y
 #
 # EP93xx Platforms
 #
+CONFIG_MACH_ADSSPHERE=y
 CONFIG_MACH_EDB9302=y
 CONFIG_MACH_EDB9312=y
 CONFIG_MACH_EDB9315=y
@@ -1134,7 +1135,6 @@ CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_WAITQ=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/h7202_defconfig b/arch/arm/configs/h7202_defconfig
index 9d62ed16bf57..0e739af52713 100644
--- a/arch/arm/configs/h7202_defconfig
+++ b/arch/arm/configs/h7202_defconfig
@@ -702,7 +702,6 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig
index a45b57582b86..1c8fb89a6730 100644
--- a/arch/arm/configs/hackkit_defconfig
+++ b/arch/arm/configs/hackkit_defconfig
@@ -740,7 +740,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_WAITQ=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index 692ab57ba1ca..3ce96e60b409 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -835,7 +835,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig
new file mode 100644
index 000000000000..f6e46193fd26
--- /dev/null
+++ b/arch/arm/configs/iop13xx_defconfig
@@ -0,0 +1,1134 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.19
+# Fri Dec  1 10:51:01 2006
+#
+CONFIG_ARM=y
+# CONFIG_GENERIC_TIME is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_RELAY is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+CONFIG_ARCH_IOP13XX=y
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+#
+# IOP13XX Implementation Options
+#
+#
+# IOP13XX Platform Support
+#
+CONFIG_MACH_IQ81340SC=y
+CONFIG_MACH_IQ81340MC=y
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSC3=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_IO_36=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+#
+# Bus support
+#
+CONFIG_PCI=y
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+# CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="ip=bootp root=nfs console=ttyS0,115200 nfsroot=,tcp,v3,wsize=8192,rsize=8192"
+# CONFIG_XIP_KERNEL is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+# CONFIG_APM is not set
+#
+# Networking
+#
+CONFIG_NET=y
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0xfa000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+#
+# OneNAND Flash Device Drivers
+#
+# CONFIG_MTD_ONENAND is not set
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+#
+# Plug and Play support
+#
+#
+# Block devices
+#
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=y
+# CONFIG_SCSI_SAS_LIBSAS is not set
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+#
+# Serial ATA (prod) and Parallel ATA (experimental) drivers
+#
+# CONFIG_ATA is not set
+#
+# Multi-device support (RAID and LVM)
+#
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+# CONFIG_MD_LINEAR is not set
+CONFIG_MD_RAID0=y
+CONFIG_MD_RAID1=y
+CONFIG_MD_RAID10=y
+CONFIG_MD_RAID456=y
+# CONFIG_MD_RAID5_RESHAPE is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_DEBUG is not set
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
+# CONFIG_FUSION_SAS is not set
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+#
+# PHY device support
+#
+#
+# Ethernet (10 or 100Mbit)
+#
+# CONFIG_NET_ETHERNET is not set
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+CONFIG_E1000_NAPI=y
+# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+#
+# I2C support
+#
+CONFIG_I2C=y
+# CONFIG_I2C_CHARDEV is not set
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_ALGOPCF=m
+CONFIG_I2C_ALGOPCA=m
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_IOP3XX=y
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+#
+# Misc devices
+#
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+#
+# LED drivers
+#
+#
+# LED Triggers
+#
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+#
+# Graphics support
+#
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_NFSD_TCP=y
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_FS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_USER=y
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+#
+# Library routines
+#
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig
index 0d67f66e78c2..b275c53728ec 100644
--- a/arch/arm/configs/iop32x_defconfig
+++ b/arch/arm/configs/iop32x_defconfig
@@ -1204,7 +1204,6 @@ CONFIG_FRAME_POINTER=y
 # CONFIG_FORCED_INLINING is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig
index 2a8fc153969d..848e3ace9069 100644
--- a/arch/arm/configs/iop33x_defconfig
+++ b/arch/arm/configs/iop33x_defconfig
@@ -1051,7 +1051,6 @@ CONFIG_FRAME_POINTER=y
 # CONFIG_FORCED_INLINING is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ixp2000_defconfig b/arch/arm/configs/ixp2000_defconfig
index 27b3e31a8ad8..bbd2dcf91e52 100644
--- a/arch/arm/configs/ixp2000_defconfig
+++ b/arch/arm/configs/ixp2000_defconfig
@@ -1026,7 +1026,6 @@ CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig
index 7b18997083ce..06deefaec1d2 100644
--- a/arch/arm/configs/ixp23xx_defconfig
+++ b/arch/arm/configs/ixp23xx_defconfig
@@ -1305,7 +1305,6 @@ CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index fac7c3b240c0..fabf74c51a88 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -1243,7 +1243,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_FRAME_POINTER=y
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
index 80a6fd97eb32..0c556289a3f4 100644
--- a/arch/arm/configs/jornada720_defconfig
+++ b/arch/arm/configs/jornada720_defconfig
@@ -889,7 +889,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/kb9202_defconfig b/arch/arm/configs/kb9202_defconfig
index 9ab0e0a66fd5..c16537d9d67a 100644
--- a/arch/arm/configs/kb9202_defconfig
+++ b/arch/arm/configs/kb9202_defconfig
@@ -753,7 +753,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig
index 4b29e099640d..e146189ab54f 100644
--- a/arch/arm/configs/lpd270_defconfig
+++ b/arch/arm/configs/lpd270_defconfig
@@ -949,7 +949,6 @@ CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/lpd7a400_defconfig b/arch/arm/configs/lpd7a400_defconfig
index bf9cf9c6d2df..f8ac29d5c654 100644
--- a/arch/arm/configs/lpd7a400_defconfig
+++ b/arch/arm/configs/lpd7a400_defconfig
@@ -850,7 +850,6 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig
index 3a57be32e849..46a0f7fe1fa5 100644
--- a/arch/arm/configs/lpd7a404_defconfig
+++ b/arch/arm/configs/lpd7a404_defconfig
@@ -1100,7 +1100,6 @@ CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig
index 81daadcbe0ba..e544bfbbde5d 100644
--- a/arch/arm/configs/lubbock_defconfig
+++ b/arch/arm/configs/lubbock_defconfig
@@ -772,7 +772,6 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig
index b112bd75bda2..cc8c95b99292 100644
--- a/arch/arm/configs/mainstone_defconfig
+++ b/arch/arm/configs/mainstone_defconfig
@@ -766,7 +766,6 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/mx1ads_defconfig b/arch/arm/configs/mx1ads_defconfig
index d16f6cd6e039..577d7e1b5d42 100644
--- a/arch/arm/configs/mx1ads_defconfig
+++ b/arch/arm/configs/mx1ads_defconfig
@@ -691,7 +691,6 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig
index df8168e57b7c..e86794a10fc0 100644
--- a/arch/arm/configs/neponset_defconfig
+++ b/arch/arm/configs/neponset_defconfig
@@ -1115,7 +1115,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/netwinder_defconfig b/arch/arm/configs/netwinder_defconfig
index 2cae1ead9f9b..c1a63a35c58d 100644
--- a/arch/arm/configs/netwinder_defconfig
+++ b/arch/arm/configs/netwinder_defconfig
@@ -994,7 +994,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/netx_defconfig b/arch/arm/configs/netx_defconfig
index 61115a773382..57f32f39d0ff 100644
--- a/arch/arm/configs/netx_defconfig
+++ b/arch/arm/configs/netx_defconfig
@@ -872,7 +872,6 @@ CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/onearm_defconfig b/arch/arm/configs/onearm_defconfig
index 9b9f2155af35..0498ebd7d5de 100644
--- a/arch/arm/configs/onearm_defconfig
+++ b/arch/arm/configs/onearm_defconfig
@@ -1045,7 +1045,6 @@ CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig
index 24e8bdd4cb91..a6b47ea8e465 100644
--- a/arch/arm/configs/pleb_defconfig
+++ b/arch/arm/configs/pleb_defconfig
@@ -721,7 +721,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
index a4989f44baaa..b5e11aa2e290 100644
--- a/arch/arm/configs/pnx4008_defconfig
+++ b/arch/arm/configs/pnx4008_defconfig
@@ -1604,7 +1604,6 @@ CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/pxa255-idp_defconfig b/arch/arm/configs/pxa255-idp_defconfig
index b71d31a4bb56..46e5089df0ae 100644
--- a/arch/arm/configs/pxa255-idp_defconfig
+++ b/arch/arm/configs/pxa255-idp_defconfig
@@ -768,7 +768,6 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index ffd905ff19f1..fc39ba1a89f3 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -967,7 +967,6 @@ CONFIG_FORCED_INLINING=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index 3f1ec4e304f7..accbf529ce5b 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -759,7 +759,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index b498afdc03b6..bc091264d354 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -910,7 +910,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index c0152393e494..3b31a33d0080 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -1319,7 +1319,6 @@ CONFIG_FORCED_INLINING=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig
index c48d17062262..9b6561d119af 100644
--- a/arch/arm/configs/shark_defconfig
+++ b/arch/arm/configs/shark_defconfig
@@ -965,7 +965,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 # CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_LL is not set
diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig
index 140056a3507f..03f783e696b3 100644
--- a/arch/arm/configs/simpad_defconfig
+++ b/arch/arm/configs/simpad_defconfig
@@ -934,7 +934,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index bd03238968c1..aa7a01179500 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -1406,7 +1406,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_FRAME_POINTER=y
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index f7bf6ef27d19..48dca69addae 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -972,7 +972,6 @@ CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 1320a0efca73..ab06a86e85d5 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -24,7 +24,9 @@ obj-$(CONFIG_OABI_COMPAT)	+= sys_oabi-compat.o
 obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
 AFLAGS_crunch-bits.o            := -Wa,-mcpu=ep9312
-obj-$(CONFIG_IWMMXT)            += iwmmxt.o iwmmxt-notifier.o
+obj-$(CONFIG_CPU_XSCALE)        += xscale-cp0.o
+obj-$(CONFIG_CPU_XSC3)          += xscale-cp0.o
+obj-$(CONFIG_IWMMXT)            += iwmmxt.o
 AFLAGS_iwmmxt.o                 := -Wa,-mcpu=iwmmxt
 ifneq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/kernel/apm.c b/arch/arm/kernel/apm.c
index ecf4f9472d94..a11fb9a40c04 100644
--- a/arch/arm/kernel/apm.c
+++ b/arch/arm/kernel/apm.c
@@ -12,7 +12,6 @@
 */
 #include <linux/module.h>
 #include <linux/poll.h>
-#include <linux/timer.h>
 #include <linux/slab.h>
 #include <linux/proc_fs.h>
 #include <linux/miscdevice.h>
@@ -26,6 +25,7 @@
 #include <linux/init.h>
 #include <linux/completion.h>
 #include <linux/kthread.h>
+#include <linux/delay.h>
 #include <asm/apm.h> /* apm_power_info */
 #include <asm/system.h>
@@ -71,7 +71,8 @@ struct apm_user {
 #define SUSPEND_PENDING 1               /* suspend pending read */
 #define SUSPEND_READ    2               /* suspend read, pending ack */
 #define SUSPEND_ACKED   3               /* suspend acked */
-#define SUSPEND_DONE    4               /* suspend completed */
+#define SUSPEND_WAIT    4               /* waiting for suspend */
+#define SUSPEND_DONE    5               /* suspend completed */
        struct apm_queue        queue;
 };
@@ -101,6 +102,7 @@ static DECLARE_WAIT_QUEUE_HEAD(kapmd_wait);
 static DEFINE_SPINLOCK(kapmd_queue_lock);
 static struct apm_queue kapmd_queue;
+static DEFINE_MUTEX(state_lock);
 static const char driver_version[] = "1.13";    /* no spaces */
@@ -148,38 +150,60 @@ static void queue_add_event(struct apm_queue *q, apm_event_t event)
        q->events[q->event_head] = event;
 }
-static void queue_event_one_user(struct apm_user *as, apm_event_t event)
+static void queue_event(apm_event_t event)
 {
-        if (as->suser && as->writer) {
+        struct apm_user *as;
-                switch (event) {
-                case APM_SYS_SUSPEND:
-                case APM_USER_SUSPEND:
-                        /*
-                         * If this user already has a suspend pending,
-                         * don't queue another one.
-                         */
-                        if (as->suspend_state != SUSPEND_NONE)
-                                return;
-                        as->suspend_state = SUSPEND_PENDING;
+        down_read(&user_list_lock);
-                        suspends_pending++;
+        list_for_each_entry(as, &apm_user_list, list) {
-                        break;
+                if (as->reader)
-                }
+                        queue_add_event(&as->queue, event);
        }
-        queue_add_event(&as->queue, event);
+        up_read(&user_list_lock);
+        wake_up_interruptible(&apm_waitqueue);
 }
-static void queue_event(apm_event_t event, struct apm_user *sender)
+/*
+ * queue_suspend_event - queue an APM suspend event.
+ *
+ * Check that we're in a state where we can suspend.  If not,
+ * return -EBUSY.  Otherwise, queue an event to all "writer"
+ * users.  If there are no "writer" users, return '1' to
+ * indicate that we can immediately suspend.
+ */
+static int queue_suspend_event(apm_event_t event, struct apm_user *sender)
 {
        struct apm_user *as;
+        int ret = 1;
+        mutex_lock(&state_lock);
        down_read(&user_list_lock);
+        /*
+         * If a thread is still processing, we can't suspend, so reject
+         * the request.
+         */
        list_for_each_entry(as, &apm_user_list, list) {
-                if (as != sender && as->reader)
+                if (as != sender && as->reader && as->writer && as->suser &&
-                        queue_event_one_user(as, event);
+                    as->suspend_state != SUSPEND_NONE) {
+                        ret = -EBUSY;
+                        goto out;
+                }
        }
+        list_for_each_entry(as, &apm_user_list, list) {
+                if (as != sender && as->reader && as->writer && as->suser) {
+                        as->suspend_state = SUSPEND_PENDING;
+                        suspends_pending++;
+                        queue_add_event(&as->queue, event);
+                        ret = 0;
+                }
+        }
+ out:
        up_read(&user_list_lock);
+        mutex_unlock(&state_lock);
        wake_up_interruptible(&apm_waitqueue);
+        return ret;
 }
 static void apm_suspend(void)
@@ -191,17 +215,22 @@ static void apm_suspend(void)
         * Anyone on the APM queues will think we're still suspended.
         * Send a message so everyone knows we're now awake again.
         */
-        queue_event(APM_NORMAL_RESUME, NULL);
+        queue_event(APM_NORMAL_RESUME);
        /*
         * Finally, wake up anyone who is sleeping on the suspend.
         */
+        mutex_lock(&state_lock);
        down_read(&user_list_lock);
        list_for_each_entry(as, &apm_user_list, list) {
-                as->suspend_result = err;
+                if (as->suspend_state == SUSPEND_WAIT ||
-                as->suspend_state = SUSPEND_DONE;
+                    as->suspend_state == SUSPEND_ACKED) {
+                        as->suspend_result = err;
+                        as->suspend_state = SUSPEND_DONE;
+                }
        }
        up_read(&user_list_lock);
+        mutex_unlock(&state_lock);
        wake_up(&apm_suspend_waitqueue);
 }
@@ -227,8 +256,11 @@ static ssize_t apm_read(struct file *fp, char __user *buf, size_t count, loff_t
                if (copy_to_user(buf, &event, sizeof(event)))
                        break;
-                if (event == APM_SYS_SUSPEND || event == APM_USER_SUSPEND)
+                mutex_lock(&state_lock);
+                if (as->suspend_state == SUSPEND_PENDING &&
+                    (event == APM_SYS_SUSPEND || event == APM_USER_SUSPEND))
                        as->suspend_state = SUSPEND_READ;
+                mutex_unlock(&state_lock);
                buf += sizeof(event);
                i -= sizeof(event);
@@ -270,9 +302,13 @@ apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
        switch (cmd) {
        case APM_IOC_SUSPEND:
+                mutex_lock(&state_lock);
                as->suspend_result = -EINTR;
                if (as->suspend_state == SUSPEND_READ) {
+                        int pending;
                        /*
                         * If we read a suspend command from /dev/apm_bios,
                         * then the corresponding APM_IOC_SUSPEND ioctl is
@@ -280,47 +316,73 @@ apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
                         */
                        as->suspend_state = SUSPEND_ACKED;
                        suspends_pending--;
+                        pending = suspends_pending == 0;
+                        mutex_unlock(&state_lock);
+                        /*
+                         * If there are no further acknowledges required,
+                         * suspend the system.
+                         */
+                        if (pending)
+                                apm_suspend();
+                        /*
+                         * Wait for the suspend/resume to complete.  If there
+                         * are pending acknowledges, we wait here for them.
+                         *
+                         * Note: we need to ensure that the PM subsystem does
+                         * not kick us out of the wait when it suspends the
+                         * threads.
+                         */
+                        flags = current->flags;
+                        current->flags |= PF_NOFREEZE;
+                        wait_event(apm_suspend_waitqueue,
+                                   as->suspend_state == SUSPEND_DONE);
                } else {
+                        as->suspend_state = SUSPEND_WAIT;
+                        mutex_unlock(&state_lock);
                        /*
                         * Otherwise it is a request to suspend the system.
                         * Queue an event for all readers, and expect an
                         * acknowledge from all writers who haven't already
                         * acknowledged.
                         */
-                        queue_event(APM_USER_SUSPEND, as);
+                        err = queue_suspend_event(APM_USER_SUSPEND, as);
-                }
+                        if (err < 0) {
+                                /*
-                /*
+                                 * Avoid taking the lock here - this
-                 * If there are no further acknowledges required, suspend
+                                 * should be fine.
-                 * the system.
+                                 */
-                 */
+                                as->suspend_state = SUSPEND_NONE;
-                if (suspends_pending == 0)
+                                break;
-                        apm_suspend();
+                        }
+                        if (err > 0)
+                                apm_suspend();
-                /*
+                        /*
-                 * Wait for the suspend/resume to complete.  If there are
+                         * Wait for the suspend/resume to complete.  If there
-                 * pending acknowledges, we wait here for them.
+                         * are pending acknowledges, we wait here for them.
-                 *
+                         *
-                 * Note that we need to ensure that the PM subsystem does
+                         * Note: we need to ensure that the PM subsystem does
-                 * not kick us out of the wait when it suspends the threads.
+                         * not kick us out of the wait when it suspends the
-                 */
+                         * threads.
-                flags = current->flags;
+                         */
-                current->flags |= PF_NOFREEZE;
+                        flags = current->flags;
+                        current->flags |= PF_NOFREEZE;
-                /*
-                 * Note: do not allow a thread which is acking the suspend
-                 * to escape until the resume is complete.
-                 */
-                if (as->suspend_state == SUSPEND_ACKED)
-                        wait_event(apm_suspend_waitqueue,
-                                         as->suspend_state == SUSPEND_DONE);
-                else
                        wait_event_interruptible(apm_suspend_waitqueue,
                                         as->suspend_state == SUSPEND_DONE);
+                }
                current->flags = flags;
+                mutex_lock(&state_lock);
                err = as->suspend_result;
                as->suspend_state = SUSPEND_NONE;
+                mutex_unlock(&state_lock);
                break;
        }
@@ -330,6 +392,8 @@ apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
 static int apm_release(struct inode * inode, struct file * filp)
 {
        struct apm_user *as = filp->private_data;
+        int pending = 0;
        filp->private_data = NULL;
        down_write(&user_list_lock);
@@ -342,11 +406,14 @@ static int apm_release(struct inode * inode, struct file * filp)
         * need to balance suspends_pending, which means the
         * possibility of sleeping.
         */
+        mutex_lock(&state_lock);
        if (as->suspend_state != SUSPEND_NONE) {
                suspends_pending -= 1;
-                if (suspends_pending == 0)
+                pending = suspends_pending == 0;
-                        apm_suspend();
        }
+        mutex_unlock(&state_lock);
+        if (pending)
+                apm_suspend();
        kfree(as);
        return 0;
@@ -470,6 +537,7 @@ static int kapmd(void *arg)
 {
        do {
                apm_event_t event;
+                int ret;
                wait_event_interruptible(kapmd_wait,
                                !queue_empty(&kapmd_queue) || kthread_should_stop());
@@ -489,13 +557,20 @@ static int kapmd(void *arg)
                case APM_LOW_BATTERY:
                case APM_POWER_STATUS_CHANGE:
-                        queue_event(event, NULL);
+                        queue_event(event);
                        break;
                case APM_USER_SUSPEND:
                case APM_SYS_SUSPEND:
-                        queue_event(event, NULL);
+                        ret = queue_suspend_event(event, NULL);
-                        if (suspends_pending == 0)
+                        if (ret < 0) {
+                                /*
+                                 * We were busy.  Try again in 50ms.
+                                 */
+                                queue_add_event(&kapmd_queue, event);
+                                msleep(50);
+                        }
+                        if (ret > 0)
                                apm_suspend();
                        break;
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index cc2d58d028e1..3c078e346753 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -15,6 +15,7 @@
 #include <asm/mach/arch.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>
+#include <asm/procinfo.h>
 /*
 * Make sure that the compiler and target are compatible.
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index b27513a0f11e..a786f769035d 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -529,7 +529,7 @@ static void ecard_dump_irq_state(void)
        }
 }
-static void ecard_check_lockup(struct irqdesc *desc)
+static void ecard_check_lockup(struct irq_desc *desc)
 {
        static unsigned long last;
        static int lockup;
@@ -567,7 +567,7 @@ static void ecard_check_lockup(struct irqdesc *desc)
 }
 static void
-ecard_irq_handler(unsigned int irq, struct irqdesc *desc)
+ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        ecard_t *ec;
        int called = 0;
@@ -585,7 +585,7 @@ ecard_irq_handler(unsigned int irq, struct irqdesc *desc)
                        pending = ecard_default_ops.irqpending(ec);
                if (pending) {
-                        struct irqdesc *d = irq_desc + ec->irq;
+                        struct irq_desc *d = irq_desc + ec->irq;
                        desc_handle_irq(ec->irq, d);
                        called ++;
                }
@@ -609,7 +609,7 @@ static unsigned char first_set[] =
 };
 static void
-ecard_irqexp_handler(unsigned int irq, struct irqdesc *desc)
+ecard_irqexp_handler(unsigned int irq, struct irq_desc *desc)
 {
        const unsigned int statusmask = 15;
        unsigned int status;
@@ -1022,7 +1022,7 @@ ecard_probe(int slot, card_type_t type)
        if (slot < 8) {
                ec->irq = 32 + slot;
                set_irq_chip(ec->irq, &ecard_chip);
-                set_irq_handler(ec->irq, do_level_IRQ);
+                set_irq_handler(ec->irq, handle_level_irq);
                set_irq_flags(ec->irq, IRQF_VALID);
        }
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bd623b73445f..2db42b18f53f 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -589,10 +589,6 @@ ENTRY(__switch_to)
        strex   r5, r4, [ip]                    @ Clear exclusive monitor
 #endif
 #endif
-#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
-        mra     r4, r5, acc0
-        stmia   ip, {r4, r5}
-#endif
 #if defined(CONFIG_HAS_TLS_REG)
        mcr     p15, 0, r3, c13, c0, 3          @ set TLS register
 #elif !defined(CONFIG_TLS_REG_EMUL)
@@ -602,11 +598,6 @@ ENTRY(__switch_to)
 #ifdef CONFIG_MMU
        mcr     p15, 0, r6, c3, c0, 0           @ Set domain register
 #endif
-#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
-        add     r4, r2, #TI_CPU_DOMAIN + 40     @ cpu_context_save->extra
-        ldmib   r4, {r4, r5}
-        mar     acc0, r4, r5
-#endif
        mov     r5, r0
        add     r4, r2, #TI_CPU_SAVE
        ldr     r0, =thread_notify_head
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index f359a189dcf2..0119c0d5f978 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -16,7 +16,6 @@
 #include <asm/assembler.h>
 #include <asm/mach-types.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index ebc3e74a7947..bda0748ffb00 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -16,7 +16,6 @@
 #include <asm/assembler.h>
 #include <asm/domain.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 #include <asm/asm-offsets.h>
 #include <asm/memory.h>
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 2c4ff1cbe334..ec01f08f5642 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -112,7 +112,7 @@ static struct irq_desc bad_irq_desc = {
 asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
 {
        struct pt_regs *old_regs = set_irq_regs(regs);
-        struct irqdesc *desc = irq_desc + irq;
+        struct irq_desc *desc = irq_desc + irq;
        /*
         * Some hardware gives randomly wrong interrupts.  Rather
@@ -134,7 +134,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
 void set_irq_flags(unsigned int irq, unsigned int iflags)
 {
-        struct irqdesc *desc;
+        struct irq_desc *desc;
        unsigned long flags;
        if (irq >= NR_IRQS) {
@@ -171,7 +171,7 @@ void __init init_IRQ(void)
 #ifdef CONFIG_HOTPLUG_CPU
-static void route_irq(struct irqdesc *desc, unsigned int irq, unsigned int cpu)
+static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
 {
        pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu);
@@ -190,7 +190,7 @@ void migrate_irqs(void)
        unsigned int i, cpu = smp_processor_id();
        for (i = 0; i < NR_IRQS; i++) {
-                struct irqdesc *desc = irq_desc + i;
+                struct irq_desc *desc = irq_desc + i;
                if (desc->cpu == cpu) {
                        unsigned int newcpu = any_online_cpu(desc->affinity);
diff --git a/arch/arm/kernel/iwmmxt-notifier.c b/arch/arm/kernel/iwmmxt-notifier.c
deleted file mode 100644
index 0d1a1db40062..000000000000
--- a/arch/arm/kernel/iwmmxt-notifier.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- *  linux/arch/arm/kernel/iwmmxt-notifier.c
- *
- *  XScale iWMMXt (Concan) context switching and handling
- *
- *  Initial code:
- *  Copyright (c) 2003, Intel Corporation
- *
- *  Full lazy switching support, optimizations and more, by Nicolas Pitre
- *  Copyright (c) 2003-2004, MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <asm/thread_notify.h>
-#include <asm/io.h>
-static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
-{
-        struct thread_info *thread = t;
-        switch (cmd) {
-        case THREAD_NOTIFY_FLUSH:
-                /*
-                 * flush_thread() zeroes thread->fpstate, so no need
-                 * to do anything here.
-                 *
-                 * FALLTHROUGH: Ensure we don't try to overwrite our newly
-                 * initialised state information on the first fault.
-                 */
-        case THREAD_NOTIFY_RELEASE:
-                iwmmxt_task_release(thread);
-                break;
-        case THREAD_NOTIFY_SWITCH:
-                iwmmxt_task_switch(thread);
-                break;
-        }
-        return NOTIFY_DONE;
-}
-static struct notifier_block iwmmxt_notifier_block = {
-        .notifier_call  = iwmmxt_do,
-};
-static int __init iwmmxt_init(void)
-{
-        thread_register_notifier(&iwmmxt_notifier_block);
-        return 0;
-}
-late_initcall(iwmmxt_init);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index bf35c178a877..a9e8f7e55fd6 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -281,67 +281,6 @@ void show_fpregs(struct user_fp *regs)
 }
 /*
- * Task structure and kernel stack allocation.
- */
-struct thread_info_list {
-        unsigned long *head;
-        unsigned int nr;
-};
-static DEFINE_PER_CPU(struct thread_info_list, thread_info_list) = { NULL, 0 };
-#define EXTRA_TASK_STRUCT       4
-struct thread_info *alloc_thread_info(struct task_struct *task)
-{
-        struct thread_info *thread = NULL;
-        if (EXTRA_TASK_STRUCT) {
-                struct thread_info_list *th = &get_cpu_var(thread_info_list);
-                unsigned long *p = th->head;
-                if (p) {
-                        th->head = (unsigned long *)p[0];
-                        th->nr -= 1;
-                }
-                put_cpu_var(thread_info_list);
-                thread = (struct thread_info *)p;
-        }
-        if (!thread)
-                thread = (struct thread_info *)
-                           __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER);
-#ifdef CONFIG_DEBUG_STACK_USAGE
-        /*
-         * The stack must be cleared if you want SYSRQ-T to
-         * give sensible stack usage information
-         */
-        if (thread)
-                memzero(thread, THREAD_SIZE);
-#endif
-        return thread;
-}
-void free_thread_info(struct thread_info *thread)
-{
-        if (EXTRA_TASK_STRUCT) {
-                struct thread_info_list *th = &get_cpu_var(thread_info_list);
-                if (th->nr < EXTRA_TASK_STRUCT) {
-                        unsigned long *p = (unsigned long *)thread;
-                        p[0] = (unsigned long)th->head;
-                        th->head = p;
-                        th->nr += 1;
-                        put_cpu_var(thread_info_list);
-                        return;
-                }
-                put_cpu_var(thread_info_list);
-        }
-        free_pages((unsigned long)thread, THREAD_SIZE_ORDER);
-}
-/*
 * Free current thread data structures etc..
 */
 void exit_thread(void)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 29efc9f82057..238dd9b6db84 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -357,9 +357,6 @@ static void __init setup_processor(void)
 #ifndef CONFIG_VFP
        elf_hwcap &= ~HWCAP_VFP;
 #endif
-#ifndef CONFIG_IWMMXT
-        elf_hwcap &= ~HWCAP_IWMMXT;
-#endif
        cpu_proc_init();
 }
@@ -441,16 +438,19 @@ __early_param("initrd=", early_initrd);
 static void __init arm_add_memory(unsigned long start, unsigned long size)
 {
+        struct membank *bank;
        /*
         * Ensure that start/size are aligned to a page boundary.
         * Size is appropriately rounded down, start is rounded up.
         */
        size -= start & ~PAGE_MASK;
-        meminfo.bank[meminfo.nr_banks].start = PAGE_ALIGN(start);
+        bank = &meminfo.bank[meminfo.nr_banks++];
-        meminfo.bank[meminfo.nr_banks].size  = size & PAGE_MASK;
-        meminfo.bank[meminfo.nr_banks].node  = PHYS_TO_NID(start);
+        bank->start = PAGE_ALIGN(start);
-        meminfo.nr_banks += 1;
+        bank->size  = size & PAGE_MASK;
+        bank->node  = PHYS_TO_NID(start);
 }
 /*
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 48cf7fffddf2..f2b1d61fbc0e 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -12,6 +12,7 @@
 #include <linux/ptrace.h>
 #include <linux/personality.h>
+#include <asm/elf.h>
 #include <asm/cacheflush.h>
 #include <asm/ucontext.h>
 #include <asm/uaccess.h>
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index bede380c07a9..042a12982e98 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -631,12 +631,9 @@ baddataabort(int code, unsigned long instr, struct pt_regs *regs)
        notify_die("unknown data abort code", regs, &info, instr, 0);
 }
-void __attribute__((noreturn)) __bug(const char *file, int line, void *data)
+void __attribute__((noreturn)) __bug(const char *file, int line)
 {
-        printk(KERN_CRIT"kernel BUG at %s:%d!", file, line);
+        printk(KERN_CRIT"kernel BUG at %s:%d!\n", file, line);
-        if (data)
-                printk(" - extra data = %p", data);
-        printk("\n");
        *(int *)0 = 0;
        /* Avoid "noreturn function does return" */
diff --git a/arch/arm/kernel/xscale-cp0.c b/arch/arm/kernel/xscale-cp0.c
new file mode 100644
index 000000000000..180000bfdc8f
--- /dev/null
+++ b/arch/arm/kernel/xscale-cp0.c
@@ -0,0 +1,179 @@
+/*
+ * linux/arch/arm/kernel/xscale-cp0.c
+ *
+ * XScale DSP and iWMMXt coprocessor context switching and handling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <asm/thread_notify.h>
+#include <asm/io.h>
+static inline void dsp_save_state(u32 *state)
+{
+        __asm__ __volatile__ (
+                "mrrc   p0, 0, %0, %1, c0\n"
+                : "=r" (state[0]), "=r" (state[1]));
+}
+static inline void dsp_load_state(u32 *state)
+{
+        __asm__ __volatile__ (
+                "mcrr   p0, 0, %0, %1, c0\n"
+                : : "r" (state[0]), "r" (state[1]));
+}
+static int dsp_do(struct notifier_block *self, unsigned long cmd, void *t)
+{
+        struct thread_info *thread = t;
+        switch (cmd) {
+        case THREAD_NOTIFY_FLUSH:
+                thread->cpu_context.extra[0] = 0;
+                thread->cpu_context.extra[1] = 0;
+                break;
+        case THREAD_NOTIFY_SWITCH:
+                dsp_save_state(current_thread_info()->cpu_context.extra);
+                dsp_load_state(thread->cpu_context.extra);
+                break;
+        }
+        return NOTIFY_DONE;
+}
+static struct notifier_block dsp_notifier_block = {
+        .notifier_call  = dsp_do,
+};
+#ifdef CONFIG_IWMMXT
+static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
+{
+        struct thread_info *thread = t;
+        switch (cmd) {
+        case THREAD_NOTIFY_FLUSH:
+                /*
+                 * flush_thread() zeroes thread->fpstate, so no need
+                 * to do anything here.
+                 *
+                 * FALLTHROUGH: Ensure we don't try to overwrite our newly
+                 * initialised state information on the first fault.
+                 */
+        case THREAD_NOTIFY_RELEASE:
+                iwmmxt_task_release(thread);
+                break;
+        case THREAD_NOTIFY_SWITCH:
+                iwmmxt_task_switch(thread);
+                break;
+        }
+        return NOTIFY_DONE;
+}
+static struct notifier_block iwmmxt_notifier_block = {
+        .notifier_call  = iwmmxt_do,
+};
+#endif
+static u32 __init xscale_cp_access_read(void)
+{
+        u32 value;
+        __asm__ __volatile__ (
+                "mrc    p15, 0, %0, c15, c1, 0\n\t"
+                : "=r" (value));
+        return value;
+}
+static void __init xscale_cp_access_write(u32 value)
+{
+        u32 temp;
+        __asm__ __volatile__ (
+                "mcr    p15, 0, %1, c15, c1, 0\n\t"
+                "mrc    p15, 0, %0, c15, c1, 0\n\t"
+                "mov    %0, %0\n\t"
+                "sub    pc, pc, #4\n\t"
+                : "=r" (temp) : "r" (value));
+}
+/*
+ * Detect whether we have a MAC coprocessor (40 bit register) or an
+ * iWMMXt coprocessor (64 bit registers) by loading 00000100:00000000
+ * into a coprocessor register and reading it back, and checking
+ * whether the upper word survived intact.
+ */
+static int __init cpu_has_iwmmxt(void)
+{
+        u32 lo;
+        u32 hi;
+        /*
+         * This sequence is interpreted by the DSP coprocessor as:
+         *      mar     acc0, %2, %3
+         *      mra     %0, %1, acc0
+         *
+         * And by the iWMMXt coprocessor as:
+         *      tmcrr   wR0, %2, %3
+         *      tmrrc   %0, %1, wR0
+         */
+        __asm__ __volatile__ (
+                "mcrr   p0, 0, %2, %3, c0\n"
+                "mrrc   p0, 0, %0, %1, c0\n"
+                : "=r" (lo), "=r" (hi)
+                : "r" (0), "r" (0x100));
+        return !!hi;
+}
+/*
+ * If we detect that the CPU has iWMMXt (and CONFIG_IWMMXT=y), we
+ * disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
+ * switch code handle iWMMXt context switching.  If on the other
+ * hand the CPU has a DSP coprocessor, we keep access to CP0 enabled
+ * all the time, and save/restore acc0 on context switch in non-lazy
+ * fashion.
+ */
+static int __init xscale_cp0_init(void)
+{
+        u32 cp_access;
+        cp_access = xscale_cp_access_read() & ~3;
+        xscale_cp_access_write(cp_access | 1);
+        if (cpu_has_iwmmxt()) {
+#ifndef CONFIG_IWMMXT
+                printk(KERN_WARNING "CAUTION: XScale iWMMXt coprocessor "
+                        "detected, but kernel support is missing.\n");
+#else
+                printk(KERN_INFO "XScale iWMMXt coprocessor detected.\n");
+                elf_hwcap |= HWCAP_IWMMXT;
+                thread_register_notifier(&iwmmxt_notifier_block);
+#endif
+        } else {
+                printk(KERN_INFO "XScale DSP coprocessor detected.\n");
+                thread_register_notifier(&dsp_notifier_block);
+                cp_access |= 1;
+        }
+        xscale_cp_access_write(cp_access);
+        return 0;
+}
+late_initcall(xscale_cp0_init);
diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c
index fe3d297d682d..a950160fcfb6 100644
--- a/arch/arm/mach-aaec2000/core.c
+++ b/arch/arm/mach-aaec2000/core.c
@@ -82,7 +82,7 @@ static void aaec2000_int_unmask(unsigned int irq)
        IRQ_INTENS |= (1 << irq);
 }
-static struct irqchip aaec2000_irq_chip = {
+static struct irq_chip aaec2000_irq_chip = {
        .ack    = aaec2000_int_ack,
        .mask   = aaec2000_int_mask,
        .unmask = aaec2000_int_unmask,
@@ -93,7 +93,7 @@ void __init aaec2000_init_irq(void)
        unsigned int i;
        for (i = 0; i < NR_IRQS; i++) {
-                set_irq_handler(i, do_level_IRQ);
+                set_irq_handler(i, handle_level_irq);
                set_irq_chip(i, &aaec2000_irq_chip);
                set_irq_flags(i, IRQF_VALID);
        }
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
index e76422761db3..3f188508c391 100644
--- a/arch/arm/mach-at91rm9200/gpio.c
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -334,10 +334,10 @@ static struct irq_chip gpio_irqchip = {
        .set_wake       = gpio_irq_set_wake,
 };
-static void gpio_irq_handler(unsigned irq, struct irqdesc *desc)
+static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
        unsigned        pin;
-        struct irqdesc  *gpio;
+        struct irq_desc *gpio;
        void __iomem    *pio;
        u32             isr;
@@ -398,7 +398,7 @@ void __init at91_gpio_irq_setup(void)
                __raw_writel(~0, controller + PIO_IDR);
                set_irq_data(id, (void *) pin);
-                set_irq_chipdata(id, controller);
+                set_irq_chip_data(id, controller);
                for (i = 0; i < 32; i++, pin++) {
                        /*
@@ -406,7 +406,7 @@ void __init at91_gpio_irq_setup(void)
                         * shorter, and the AIC handles interupts sanely.
                         */
                        set_irq_chip(pin, &gpio_irqchip);
-                        set_irq_handler(pin, do_simple_IRQ);
+                        set_irq_handler(pin, handle_simple_irq);
                        set_irq_flags(pin, IRQF_VALID);
                }
diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c
index 2cea07a34a85..2148daafd29c 100644
--- a/arch/arm/mach-at91rm9200/irq.c
+++ b/arch/arm/mach-at91rm9200/irq.c
@@ -145,7 +145,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
                at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
                set_irq_chip(i, &at91_aic_chip);
-                set_irq_handler(i, do_level_IRQ);
+                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
index 7ee926e5bad2..ca102960f528 100644
--- a/arch/arm/mach-clps711x/irq.c
+++ b/arch/arm/mach-clps711x/irq.c
@@ -63,7 +63,7 @@ static void int1_unmask(unsigned int irq)
        clps_writel(intmr1, INTMR1);
 }
-static struct irqchip int1_chip = {
+static struct irq_chip int1_chip = {
        .ack    = int1_ack,
        .mask   = int1_mask,
        .unmask = int1_unmask,
@@ -100,7 +100,7 @@ static void int2_unmask(unsigned int irq)
        clps_writel(intmr2, INTMR2);
 }
-static struct irqchip int2_chip = {
+static struct irq_chip int2_chip = {
        .ack    = int2_ack,
        .mask   = int2_mask,
        .unmask = int2_unmask,
@@ -112,12 +112,12 @@ void __init clps711x_init_irq(void)
        for (i = 0; i < NR_IRQS; i++) {
                if (INT1_IRQS & (1 << i)) {
-                        set_irq_handler(i, do_level_IRQ);
+                        set_irq_handler(i, handle_level_irq);
                        set_irq_chip(i, &int1_chip);
                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                }
                if (INT2_IRQS & (1 << i)) {
-                        set_irq_handler(i, do_level_IRQ);
+                        set_irq_handler(i, handle_level_irq);
                        set_irq_chip(i, &int2_chip);
                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                }                       
diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c
index fb10cf252588..231b90004736 100644
--- a/arch/arm/mach-clps7500/core.c
+++ b/arch/arm/mach-clps7500/core.c
@@ -57,7 +57,7 @@ static void cl7500_unmask_irq_a(unsigned int irq)
        iomd_writeb(val | mask, IOMD_IRQMASKA);
 }
-static struct irqchip clps7500_a_chip = {
+static struct irq_chip clps7500_a_chip = {
        .ack    = cl7500_ack_irq_a,
        .mask   = cl7500_mask_irq_a,
        .unmask = cl7500_unmask_irq_a,
@@ -81,7 +81,7 @@ static void cl7500_unmask_irq_b(unsigned int irq)
        iomd_writeb(val | mask, IOMD_IRQMASKB);
 }
-static struct irqchip clps7500_b_chip = {
+static struct irq_chip clps7500_b_chip = {
        .ack    = cl7500_mask_irq_b,
        .mask   = cl7500_mask_irq_b,
        .unmask = cl7500_unmask_irq_b,
@@ -105,7 +105,7 @@ static void cl7500_unmask_irq_c(unsigned int irq)
        iomd_writeb(val | mask, IOMD_IRQMASKC);
 }
-static struct irqchip clps7500_c_chip = {
+static struct irq_chip clps7500_c_chip = {
        .ack    = cl7500_mask_irq_c,
        .mask   = cl7500_mask_irq_c,
        .unmask = cl7500_unmask_irq_c,
@@ -129,7 +129,7 @@ static void cl7500_unmask_irq_d(unsigned int irq)
        iomd_writeb(val | mask, IOMD_IRQMASKD);
 }
-static struct irqchip clps7500_d_chip = {
+static struct irq_chip clps7500_d_chip = {
        .ack    = cl7500_mask_irq_d,
        .mask   = cl7500_mask_irq_d,
        .unmask = cl7500_unmask_irq_d,
@@ -153,7 +153,7 @@ static void cl7500_unmask_irq_dma(unsigned int irq)
        iomd_writeb(val | mask, IOMD_DMAMASK);
 }
-static struct irqchip clps7500_dma_chip = {
+static struct irq_chip clps7500_dma_chip = {
        .ack    = cl7500_mask_irq_dma,
        .mask   = cl7500_mask_irq_dma,
        .unmask = cl7500_unmask_irq_dma,
@@ -177,7 +177,7 @@ static void cl7500_unmask_irq_fiq(unsigned int irq)
        iomd_writeb(val | mask, IOMD_FIQMASK);
 }
-static struct irqchip clps7500_fiq_chip = {
+static struct irq_chip clps7500_fiq_chip = {
        .ack    = cl7500_mask_irq_fiq,
        .mask   = cl7500_mask_irq_fiq,
        .unmask = cl7500_unmask_irq_fiq,
@@ -187,7 +187,7 @@ static void cl7500_no_action(unsigned int irq)
 {
 }
-static struct irqchip clps7500_no_chip = {
+static struct irq_chip clps7500_no_chip = {
        .ack    = cl7500_no_action,
        .mask   = cl7500_no_action,
        .unmask = cl7500_no_action,
@@ -214,43 +214,43 @@ static void __init clps7500_init_irq(void)
                switch (irq) {
                case 0 ... 7:
                        set_irq_chip(irq, &clps7500_a_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, flags);
                        break;
                case 8 ... 15:
                        set_irq_chip(irq, &clps7500_b_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, flags);
                        break;
                case 16 ... 22:
                        set_irq_chip(irq, &clps7500_dma_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, flags);
                        break;
                case 24 ... 31:
                        set_irq_chip(irq, &clps7500_c_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, flags);
                        break;
                case 40 ... 47:
                        set_irq_chip(irq, &clps7500_d_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, flags);
                        break;
                case 48 ... 55:
                        set_irq_chip(irq, &clps7500_no_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, flags);
                        break;
                case 64 ... 72:
                        set_irq_chip(irq, &clps7500_fiq_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, flags);
                        break;
                }
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 90103ab373a6..8459431cfd71 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -45,7 +45,7 @@ static void ebsa110_unmask_irq(unsigned int irq)
        __raw_writeb(1 << irq, IRQ_MSET);
 }
-static struct irqchip ebsa110_irq_chip = {
+static struct irq_chip ebsa110_irq_chip = {
        .ack    = ebsa110_mask_irq,
        .mask   = ebsa110_mask_irq,
        .unmask = ebsa110_unmask_irq,
@@ -67,7 +67,7 @@ static void __init ebsa110_init_irq(void)
        for (irq = 0; irq < NR_IRQS; irq++) {
                set_irq_chip(irq, &ebsa110_irq_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
 }
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index e346b03cd921..af7904b3d0a8 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -9,12 +9,24 @@ config CRUNCH
 comment "EP93xx Platforms"
+config MACH_ADSSPHERE
+        bool "Support ADS Sphere"
+        help
+          Say 'Y' here if you want your kernel to support the ADS
+          Sphere board.
 config MACH_EDB9302
        bool "Support Cirrus Logic EDB9302"
        help
          Say 'Y' here if you want your kernel to support the Cirrus
          Logic EDB9302 Evaluation Board.
+config MACH_EDB9302A
+        bool "Support Cirrus Logic EDB9302A"
+        help
+          Say 'Y' here if you want your kernel to support the Cirrus
+          Logic EDB9302A Evaluation Board.
 config MACH_EDB9312
        bool "Support Cirrus Logic EDB9312"
        help
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index c2eb18b530c2..b06641dd450d 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -6,7 +6,9 @@ obj-m			:=
 obj-n                   :=
 obj-                    :=
+obj-$(CONFIG_MACH_ADSSPHERE)    += adssphere.o
 obj-$(CONFIG_MACH_EDB9302)      += edb9302.o
+obj-$(CONFIG_MACH_EDB9302A)     += edb9302a.o
 obj-$(CONFIG_MACH_EDB9312)      += edb9312.o
 obj-$(CONFIG_MACH_EDB9315)      += edb9315.o
 obj-$(CONFIG_MACH_EDB9315A)     += edb9315a.o
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
new file mode 100644
index 000000000000..ac5d5818eb7b
--- /dev/null
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -0,0 +1,91 @@
+/*
+ * arch/arm/mach-ep93xx/adssphere.c
+ * ADS Sphere support.
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+static struct physmap_flash_data adssphere_flash_data = {
+        .width          = 4,
+};
+static struct resource adssphere_flash_resource = {
+        .start          = 0x60000000,
+        .end            = 0x61ffffff,
+        .flags          = IORESOURCE_MEM,
+};
+static struct platform_device adssphere_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &adssphere_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &adssphere_flash_resource,
+};
+static struct ep93xx_eth_data adssphere_eth_data = {
+        .phy_id         = 1,
+};
+static struct resource adssphere_eth_resource[] = {
+        {
+                .start  = EP93XX_ETHERNET_PHYS_BASE,
+                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_EP93XX_ETHERNET,
+                .end    = IRQ_EP93XX_ETHERNET,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+static struct platform_device adssphere_eth_device = {
+        .name           = "ep93xx-eth",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &adssphere_eth_data,
+        },
+        .num_resources  = 2,
+        .resource       = adssphere_eth_resource,
+};
+static void __init adssphere_init_machine(void)
+{
+        ep93xx_init_devices();
+        platform_device_register(&adssphere_flash);
+        memcpy(adssphere_eth_data.dev_addr,
+                (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
+        platform_device_register(&adssphere_eth_device);
+}
+MACHINE_START(ADSSPHERE, "ADS Sphere board")
+        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = adssphere_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index e3fd1ab6adcc..d649b39711d4 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -245,7 +245,7 @@ EXPORT_SYMBOL(gpio_line_set);
 * EP93xx IRQ handling
 *************************************************************************/
 static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
-                struct irqdesc *desc)
+                struct irq_desc *desc)
 {
        unsigned char status;
        int i;
@@ -335,7 +335,7 @@ static int ep93xx_gpio_ab_irq_type(unsigned int irq, unsigned int type)
        return 0;
 }
-static struct irqchip ep93xx_gpio_ab_irq_chip = {
+static struct irq_chip ep93xx_gpio_ab_irq_chip = {
        .ack            = ep93xx_gpio_ab_irq_mask_ack,
        .mask           = ep93xx_gpio_ab_irq_mask,
        .unmask         = ep93xx_gpio_ab_irq_unmask,
@@ -352,7 +352,7 @@ void __init ep93xx_init_irq(void)
        for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) {
                set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
        set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
diff --git a/arch/arm/mach-ep93xx/edb9302a.c b/arch/arm/mach-ep93xx/edb9302a.c
new file mode 100644
index 000000000000..62e064bab1d2
--- /dev/null
+++ b/arch/arm/mach-ep93xx/edb9302a.c
@@ -0,0 +1,91 @@
+/*
+ * arch/arm/mach-ep93xx/edb9302a.c
+ * Cirrus Logic EDB9302A support.
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+static struct physmap_flash_data edb9302a_flash_data = {
+        .width          = 2,
+};
+static struct resource edb9302a_flash_resource = {
+        .start          = 0x60000000,
+        .end            = 0x60ffffff,
+        .flags          = IORESOURCE_MEM,
+};
+static struct platform_device edb9302a_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &edb9302a_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &edb9302a_flash_resource,
+};
+static struct ep93xx_eth_data edb9302a_eth_data = {
+        .phy_id                 = 1,
+};
+static struct resource edb9302a_eth_resource[] = {
+        {
+                .start  = EP93XX_ETHERNET_PHYS_BASE,
+                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_EP93XX_ETHERNET,
+                .end    = IRQ_EP93XX_ETHERNET,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+static struct platform_device edb9302a_eth_device = {
+        .name           = "ep93xx-eth",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &edb9302a_eth_data,
+        },
+        .num_resources  = 2,
+        .resource       = edb9302a_eth_resource,
+};
+static void __init edb9302a_init_machine(void)
+{
+        ep93xx_init_devices();
+        platform_device_register(&edb9302a_flash);
+        memcpy(edb9302a_eth_data.dev_addr,
+                (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
+        platform_device_register(&edb9302a_eth_device);
+}
+MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
+        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0xc0000100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = edb9302a_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index af900f4755a4..ef29fc34ce65 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -78,7 +78,7 @@ static void fb_unmask_irq(unsigned int irq)
        *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)];
 }
-static struct irqchip fb_chip = {
+static struct irq_chip fb_chip = {
        .ack    = fb_mask_irq,
        .mask   = fb_mask_irq,
        .unmask = fb_unmask_irq,
@@ -96,7 +96,7 @@ static void __init __fb_init_irq(void)
        for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
                set_irq_chip(irq, &fb_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
 }
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index 888dedd501b9..79443ffc8916 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -49,7 +49,7 @@ static void isa_unmask_pic_lo_irq(unsigned int irq)
        outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO);
 }
-static struct irqchip isa_lo_chip = {
+static struct irq_chip isa_lo_chip = {
        .ack    = isa_ack_pic_lo_irq,
        .mask   = isa_mask_pic_lo_irq,
        .unmask = isa_unmask_pic_lo_irq,
@@ -78,14 +78,14 @@ static void isa_unmask_pic_hi_irq(unsigned int irq)
        outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI);
 }
-static struct irqchip isa_hi_chip = {
+static struct irq_chip isa_hi_chip = {
        .ack    = isa_ack_pic_hi_irq,
        .mask   = isa_mask_pic_hi_irq,
        .unmask = isa_unmask_pic_hi_irq,
 };
 static void
-isa_irq_handler(unsigned int irq, struct irqdesc *desc)
+isa_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
@@ -150,13 +150,13 @@ void __init isa_init_irq(unsigned int host_irq)
        if (host_irq != (unsigned int)-1) {
                for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
                        set_irq_chip(irq, &isa_lo_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
                }
                for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
                        set_irq_chip(irq, &isa_hi_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
                }
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index 4719229a1a78..7f31816896ad 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -101,7 +101,7 @@ static void inline unmask_gpio_irq(u32 irq)
 static void
 h720x_gpio_handler(unsigned int mask, unsigned int irq,
-                 struct irqdesc *desc)
+                 struct irq_desc *desc)
 {
        IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
        desc = irq_desc + irq;
@@ -117,7 +117,7 @@ h720x_gpio_handler(unsigned int mask, unsigned int irq,
 }
 static void
-h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 {
        unsigned int mask, irq;
@@ -128,7 +128,7 @@ h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 }
 static void
-h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 {
        unsigned int mask, irq;
        mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
@@ -138,7 +138,7 @@ h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 }
 static void
-h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 {
        unsigned int mask, irq;
@@ -149,7 +149,7 @@ h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 }
 static void
-h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 {
        unsigned int mask, irq;
@@ -161,7 +161,7 @@ h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 #ifdef CONFIG_CPU_H7202
 static void
-h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 {
        unsigned int mask, irq;
@@ -172,13 +172,13 @@ h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 }
 #endif
-static struct irqchip h720x_global_chip = {
+static struct irq_chip h720x_global_chip = {
        .ack = mask_global_irq,
        .mask = mask_global_irq,
        .unmask = unmask_global_irq,
 };
-static struct irqchip h720x_gpio_chip = {
+static struct irq_chip h720x_gpio_chip = {
        .ack = ack_gpio_irq,
        .mask = mask_gpio_irq,
        .unmask = unmask_gpio_irq,
@@ -203,14 +203,14 @@ void __init h720x_init_irq (void)
        /* Initialize global IRQ's, fast path */
        for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
                set_irq_chip(irq, &h720x_global_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
        /* Initialize multiplexed IRQ's, slow path */
        for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
                set_irq_chip(irq, &h720x_gpio_chip);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID );
        }
        set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
@@ -221,7 +221,7 @@ void __init h720x_init_irq (void)
 #ifdef CONFIG_CPU_H7202
        for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
                set_irq_chip(irq, &h720x_gpio_chip);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID );
        }
        set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index 06fecaefd8dc..703870f30adf 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -106,7 +106,7 @@ static struct platform_device *devices[] __initdata = {
 * we have to handle all timer interrupts in one place.
 */
 static void
-h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 {
        unsigned int mask, irq;
@@ -162,7 +162,7 @@ static void inline unmask_timerx_irq (u32 irq)
        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
 }
-static struct irqchip h7202_timerx_chip = {
+static struct irq_chip h7202_timerx_chip = {
        .ack = mask_timerx_irq,
        .mask = mask_timerx_irq,
        .unmask = unmask_timerx_irq,
@@ -202,7 +202,7 @@ void __init h7202_init_irq (void)
                          irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
                mask_timerx_irq(irq);
                set_irq_chip(irq, &h7202_timerx_chip);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID );
        }
        set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c
index 12ea58a3b84f..b5aa49d00ca3 100644
--- a/arch/arm/mach-imx/generic.c
+++ b/arch/arm/mach-imx/generic.c
@@ -104,6 +104,9 @@ EXPORT_SYMBOL(imx_gpio_mode);
 */
 static unsigned int imx_decode_pll(unsigned int pll)
 {
+        unsigned long long ll;
+        unsigned long quot;
        u32 mfi = (pll >> 10) & 0xf;
        u32 mfn = pll & 0x3ff;
        u32 mfd = (pll >> 16) & 0x3ff;
@@ -112,7 +115,11 @@ static unsigned int imx_decode_pll(unsigned int pll)
        mfi = mfi <= 5 ? 5 : mfi;
-        return (2 * (f_ref>>10) * ( (mfi<<10) + (mfn<<10) / (mfd+1) )) / (pd+1);
+        ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
+        quot = (pd+1) * (1<<16);
+        ll += quot / 2;
+        do_div(ll, quot);
+        return (unsigned int) ll;
 }
 unsigned int imx_get_system_clk(void)
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c
index 368b13b058ab..0791b56caecc 100644
--- a/arch/arm/mach-imx/irq.c
+++ b/arch/arm/mach-imx/irq.c
@@ -146,7 +146,7 @@ imx_gpio_unmask_irq(unsigned int irq)
 static void
 imx_gpio_handler(unsigned int mask, unsigned int irq,
-                 struct irqdesc *desc)
+                 struct irq_desc *desc)
 {
        desc = irq_desc + irq;
        while (mask) {
@@ -161,7 +161,7 @@ imx_gpio_handler(unsigned int mask, unsigned int irq,
 }
 static void
-imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 {
        unsigned int mask, irq;
@@ -171,7 +171,7 @@ imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 }
 static void
-imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 {
        unsigned int mask, irq;
@@ -181,7 +181,7 @@ imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 }
 static void
-imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 {
        unsigned int mask, irq;
@@ -191,7 +191,7 @@ imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 }
 static void
-imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 {
        unsigned int mask, irq;
@@ -230,13 +230,13 @@ imx_init_irq(void)
        for (irq = 0; irq < IMX_IRQS; irq++) {
                set_irq_chip(irq, &imx_internal_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
        for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
                set_irq_chip(irq, &imx_gpio_chip);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 8ae4a2c5066f..40039b2a90b3 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -14,6 +14,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/time.h>
+#include <linux/clocksource.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
@@ -24,33 +25,7 @@
 /* Use timer 1 as system timer */
 #define TIMER_BASE IMX_TIM1_BASE
-/*
+static unsigned long evt_diff;
- * Returns number of us since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long imx_gettimeoffset(void)
-{
-        unsigned long ticks;
-        /*
-         * Get the current number of ticks.  Note that there is a race
-         * condition between us reading the timer and checking for
-         * an interrupt.  We get around this by ensuring that the
-         * counter has not reloaded between our two reads.
-         */
-        ticks = IMX_TCN(TIMER_BASE);
-        /*
-         * Interrupt pending?  If so, we've reloaded once already.
-         */
-        if (IMX_TSTAT(TIMER_BASE) & TSTAT_COMP)
-                ticks += LATCH;
-        /*
-         * Convert the ticks to usecs
-         */
-        return (1000000 / CLK32) * ticks;
-}
 /*
 * IRQ handler for the timer
@@ -58,14 +33,23 @@ static unsigned long imx_gettimeoffset(void)
 static irqreturn_t
 imx_timer_interrupt(int irq, void *dev_id)
 {
-        write_seqlock(&xtime_lock);
+        uint32_t tstat;
        /* clear the interrupt */
-        if (IMX_TSTAT(TIMER_BASE))
+        tstat = IMX_TSTAT(TIMER_BASE);
-                IMX_TSTAT(TIMER_BASE) = 0;
+        IMX_TSTAT(TIMER_BASE) = 0;
+        if (tstat & TSTAT_COMP) {
+                do {
+                        write_seqlock(&xtime_lock);
+                        timer_tick();
+                        write_sequnlock(&xtime_lock);
+                        IMX_TCMP(TIMER_BASE) += evt_diff;
-        timer_tick();
+                } while (unlikely((int32_t)(IMX_TCMP(TIMER_BASE)
-        write_sequnlock(&xtime_lock);
+                                        - IMX_TCN(TIMER_BASE)) < 0));
+        }
        return IRQ_HANDLED;
 }
@@ -77,9 +61,9 @@ static struct irqaction imx_timer_irq = {
 };
 /*
- * Set up timer interrupt, and return the current time in seconds.
+ * Set up timer hardware into expected mode and state.
 */
-static void __init imx_timer_init(void)
+static void __init imx_timer_hardware_init(void)
 {
        /*
         * Initialise to a known state (all timers off, and timing reset)
@@ -87,7 +71,38 @@ static void __init imx_timer_init(void)
        IMX_TCTL(TIMER_BASE) = 0;
        IMX_TPRER(TIMER_BASE) = 0;
        IMX_TCMP(TIMER_BASE) = LATCH - 1;
-        IMX_TCTL(TIMER_BASE) = TCTL_CLK_32 | TCTL_IRQEN | TCTL_TEN;
+        IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_IRQEN | TCTL_TEN;
+        evt_diff = LATCH;
+}
+cycle_t imx_get_cycles(void)
+{
+        return IMX_TCN(TIMER_BASE);
+}
+static struct clocksource clocksource_imx = {
+        .name           = "imx_timer1",
+        .rating         = 200,
+        .read           = imx_get_cycles,
+        .mask           = 0xFFFFFFFF,
+        .shift          = 20,
+        .is_continuous  = 1,
+};
+static int __init imx_clocksource_init(void)
+{
+        clocksource_imx.mult =
+                clocksource_hz2mult(imx_get_perclk1(), clocksource_imx.shift);
+        clocksource_register(&clocksource_imx);
+        return 0;
+}
+static void __init imx_timer_init(void)
+{
+        imx_timer_hardware_init();
+        imx_clocksource_init();
        /*
         * Make irqs happen for the system timer
@@ -97,5 +112,4 @@ static void __init imx_timer_init(void)
 struct sys_timer imx_timer = {
        .init           = imx_timer_init,
-        .offset         = imx_gettimeoffset,
 };
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 191c57a3b997..72280754354d 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -183,7 +183,7 @@ static void __init ap_init_irq(void)
        for (i = 0; i < NR_IRQS; i++) {
                if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) {
                        set_irq_chip(i, &sc_chip);
-                        set_irq_handler(i, do_level_IRQ);
+                        set_irq_handler(i, handle_level_irq);
                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                }
        }
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 771b65bffe69..913f64b22405 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -202,7 +202,7 @@ static struct irq_chip sic_chip = {
 };
 static void
-sic_handle_irq(unsigned int irq, struct irqdesc *desc)
+sic_handle_irq(unsigned int irq, struct irq_desc *desc)
 {
        unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
@@ -238,7 +238,7 @@ static void __init intcp_init_irq(void)
                if (i == 29)
                        break;
                set_irq_chip(i, &pic_chip);
-                set_irq_handler(i, do_level_IRQ);
+                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
        }
@@ -247,7 +247,7 @@ static void __init intcp_init_irq(void)
        for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
                set_irq_chip(i, &cic_chip);
-                set_irq_handler(i, do_level_IRQ);
+                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID);
        }
@@ -256,7 +256,7 @@ static void __init intcp_init_irq(void)
        for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
                set_irq_chip(i, &sic_chip);
-                set_irq_handler(i, do_level_IRQ);
+                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
        }
diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c
index 1bc8534ef0c6..613b841a10f3 100644
--- a/arch/arm/mach-integrator/platsmp.c
+++ b/arch/arm/mach-integrator/platsmp.c
@@ -18,7 +18,6 @@
 #include <asm/cacheflush.h>
 #include <asm/delay.h>
 #include <asm/mmu_context.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 #include <asm/smp.h>
diff --git a/arch/arm/mach-iop13xx/Kconfig b/arch/arm/mach-iop13xx/Kconfig
new file mode 100644
index 000000000000..40c2d689f2eb
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Kconfig
@@ -0,0 +1,20 @@
+if ARCH_IOP13XX
+menu "IOP13XX Implementation Options"
+comment "IOP13XX Platform Support"
+config MACH_IQ81340SC
+        bool "Enable IQ81340SC Hardware Support"
+        help
+          Say Y here if you want to support running on the Intel IQ81340SC
+          evaluation kit.
+config MACH_IQ81340MC
+        bool "Enable IQ81340MC Hardware Support"
+        help
+          Say Y here if you want to support running on the Intel IQ81340MC
+          evaluation kit.
+endmenu
+endif
diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile
new file mode 100644
index 000000000000..c3d6c08f2d4c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Makefile
@@ -0,0 +1,12 @@
+obj-y                   :=
+obj-m                   :=
+obj-n                   :=
+obj-                    :=
+obj-$(CONFIG_ARCH_IOP13XX) += setup.o
+obj-$(CONFIG_ARCH_IOP13XX) += irq.o
+obj-$(CONFIG_ARCH_IOP13XX) += time.o
+obj-$(CONFIG_ARCH_IOP13XX) += pci.o
+obj-$(CONFIG_ARCH_IOP13XX) += io.o
+obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
+obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o
diff --git a/arch/arm/mach-iop13xx/Makefile.boot b/arch/arm/mach-iop13xx/Makefile.boot
new file mode 100644
index 000000000000..0b0e19fdfe6c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
new file mode 100644
index 000000000000..fbf9f88e46ea
--- /dev/null
+++ b/arch/arm/mach-iop13xx/io.c
@@ -0,0 +1,93 @@
+/*
+ * iop13xx custom ioremap implementation
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
+        unsigned long flags)
+{
+        void __iomem * retval;
+        switch (cookie) {
+        case IOP13XX_PCIX_LOWER_MEM_RA ... IOP13XX_PCIX_UPPER_MEM_RA:
+                if (unlikely(!iop13xx_atux_mem_base))
+                        retval = NULL;
+                else
+                        retval = (void *)(iop13xx_atux_mem_base +
+                                 (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
+                break;
+        case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
+                if (unlikely(!iop13xx_atue_mem_base))
+                        retval = NULL;
+                else
+                        retval = (void *)(iop13xx_atue_mem_base +
+                                 (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
+                break;
+        case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
+                retval = __ioremap(IOP13XX_PBI_LOWER_MEM_PA +
+                                  (cookie - IOP13XX_PBI_LOWER_MEM_RA),
+                                  size, flags);
+                break;
+        case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
+                retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
+                break;
+        case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
+                retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
+                break;
+        case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
+                retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
+                break;
+        default:
+                retval = __ioremap(cookie, size, flags);
+        }
+        return retval;
+}
+EXPORT_SYMBOL(__iop13xx_ioremap);
+void __iop13xx_iounmap(void __iomem *addr)
+{
+        extern void __iounmap(volatile void __iomem *addr);
+        if (iop13xx_atue_mem_base)
+                if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
+                    addr < (void __iomem *) (iop13xx_atue_mem_base +
+                                             iop13xx_atue_mem_size))
+                    goto skip;
+        if (iop13xx_atux_mem_base)
+                if (addr >= (void __iomem *) iop13xx_atux_mem_base &&
+                    addr < (void __iomem *) (iop13xx_atux_mem_base +
+                                             iop13xx_atux_mem_size))
+                    goto skip;
+        switch ((u32) addr) {
+        case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
+        case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
+        case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
+                goto skip;
+        }
+        __iounmap(addr);
+skip:
+        return;
+}
+EXPORT_SYMBOL(__iop13xx_iounmap);
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
new file mode 100644
index 000000000000..ee595786cd22
--- /dev/null
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -0,0 +1,98 @@
+/*
+ * iq81340mc board support
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#include <linux/pci.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/arch/pci.h>
+#include <asm/mach/time.h>
+extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
+static int __init
+iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+{
+        switch (idsel) {
+        case 1:
+                switch (pin) {
+                case 1: return ATUX_INTB;
+                case 2: return ATUX_INTC;
+                case 3: return ATUX_INTD;
+                case 4: return ATUX_INTA;
+                default: return -1;
+                }
+        case 2:
+                switch (pin) {
+                case 1: return ATUX_INTC;
+                case 2: return ATUX_INTD;
+                case 3: return ATUX_INTC;
+                case 4: return ATUX_INTD;
+                default: return -1;
+                }
+        default: return -1;
+        }
+}
+static struct hw_pci iq81340mc_pci __initdata = {
+        .swizzle        = pci_std_swizzle,
+        .nr_controllers = 0,
+        .setup          = iop13xx_pci_setup,
+        .map_irq        = iq81340mc_pcix_map_irq,
+        .scan           = iop13xx_scan_bus,
+        .preinit        = iop13xx_pci_init,
+};
+static int __init iq81340mc_pci_init(void)
+{
+        iop13xx_atu_select(&iq81340mc_pci);
+        pci_common_init(&iq81340mc_pci);
+        iop13xx_map_pci_memory();
+        return 0;
+}
+static void __init iq81340mc_init(void)
+{
+        iop13xx_platform_init();
+        iq81340mc_pci_init();
+}
+static void __init iq81340mc_timer_init(void)
+{
+        iop13xx_init_time(400000000);
+}
+static struct sys_timer iq81340mc_timer = {
+       .init       = iq81340mc_timer_init,
+       .offset     = iop13xx_gettimeoffset,
+};
+MACHINE_START(IQ81340MC, "Intel IQ81340MC")
+        /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
+        .phys_io        = PHYS_IO,
+        .io_pg_offst    = IO_PG_OFFSET,
+        .map_io         = iop13xx_map_io,
+        .init_irq       = iop13xx_init_irq,
+        .timer          = &iq81340mc_timer,
+        .boot_params    = BOOT_PARAM_OFFSET,
+        .init_machine   = iq81340mc_init,
+MACHINE_END
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
new file mode 100644
index 000000000000..6677e14b61bf
--- /dev/null
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -0,0 +1,100 @@
+/*
+ * iq81340sc board support
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#include <linux/pci.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/arch/pci.h>
+#include <asm/mach/time.h>
+extern int init_atu;
+static int __init
+iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+{
+        WARN_ON(idsel < 1 || idsel > 2);
+        switch (idsel) {
+        case 1:
+                switch (pin) {
+                case 1: return ATUX_INTB;
+                case 2: return ATUX_INTC;
+                case 3: return ATUX_INTD;
+                case 4: return ATUX_INTA;
+                default: return -1;
+                }
+        case 2:
+                switch (pin) {
+                case 1: return ATUX_INTC;
+                case 2: return ATUX_INTC;
+                case 3: return ATUX_INTC;
+                case 4: return ATUX_INTC;
+                default: return -1;
+                }
+        default: return -1;
+        }
+}
+static struct hw_pci iq81340sc_pci __initdata = {
+        .swizzle        = pci_std_swizzle,
+        .nr_controllers = 0,
+        .setup          = iop13xx_pci_setup,
+        .scan           = iop13xx_scan_bus,
+        .map_irq        = iq81340sc_atux_map_irq,
+        .preinit        = iop13xx_pci_init
+};
+static int __init iq81340sc_pci_init(void)
+{
+        iop13xx_atu_select(&iq81340sc_pci);
+        pci_common_init(&iq81340sc_pci);
+        iop13xx_map_pci_memory();
+        return 0;
+}
+static void __init iq81340sc_init(void)
+{
+        iop13xx_platform_init();
+        iq81340sc_pci_init();
+}
+static void __init iq81340sc_timer_init(void)
+{
+        iop13xx_init_time(400000000);
+}
+static struct sys_timer iq81340sc_timer = {
+       .init       = iq81340sc_timer_init,
+       .offset     = iop13xx_gettimeoffset,
+};
+MACHINE_START(IQ81340SC, "Intel IQ81340SC")
+        /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
+        .phys_io        = PHYS_IO,
+        .io_pg_offst    = IO_PG_OFFSET,
+        .map_io         = iop13xx_map_io,
+        .init_irq       = iop13xx_init_irq,
+        .timer          = &iq81340sc_timer,
+        .boot_params    = BOOT_PARAM_OFFSET,
+        .init_machine   = iq81340sc_init,
+MACHINE_END
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
new file mode 100644
index 000000000000..c4d9c8c5579c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -0,0 +1,286 @@
+/*
+ * iop13xx IRQ handling / support functions
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/sysctl.h>
+#include <asm/uaccess.h>
+#include <asm/mach/irq.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/arch/irqs.h>
+/* INTCTL0 CP6 R0 Page 4
+ */
+static inline u32 read_intctl_0(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
+        return val;
+}
+static inline void write_intctl_0(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
+}
+/* INTCTL1 CP6 R1 Page 4
+ */
+static inline u32 read_intctl_1(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
+        return val;
+}
+static inline void write_intctl_1(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
+}
+/* INTCTL2 CP6 R2 Page 4
+ */
+static inline u32 read_intctl_2(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
+        return val;
+}
+static inline void write_intctl_2(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
+}
+/* INTCTL3 CP6 R3 Page 4
+ */
+static inline u32 read_intctl_3(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
+        return val;
+}
+static inline void write_intctl_3(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
+}
+/* INTSTR0 CP6 R0 Page 5
+ */
+static inline u32 read_intstr_0(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
+        return val;
+}
+static inline void write_intstr_0(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
+}
+/* INTSTR1 CP6 R1 Page 5
+ */
+static inline u32 read_intstr_1(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
+        return val;
+}
+static void write_intstr_1(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
+}
+/* INTSTR2 CP6 R2 Page 5
+ */
+static inline u32 read_intstr_2(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
+        return val;
+}
+static void write_intstr_2(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
+}
+/* INTSTR3 CP6 R3 Page 5
+ */
+static inline u32 read_intstr_3(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
+        return val;
+}
+static void write_intstr_3(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
+}
+/* INTBASE CP6 R0 Page 2
+ */
+static inline u32 read_intbase(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
+        return val;
+}
+static void write_intbase(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
+}
+/* INTSIZE CP6 R2 Page 2
+ */
+static inline u32 read_intsize(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
+        return val;
+}
+static void write_intsize(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
+}
+/* 0 = Interrupt Masked and 1 = Interrupt not masked */
+static void
+iop13xx_irq_mask0 (unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
+        iop13xx_cp6_restore(cp_flags);
+}
+static void
+iop13xx_irq_mask1 (unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
+        iop13xx_cp6_restore(cp_flags);
+}
+static void
+iop13xx_irq_mask2 (unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
+        iop13xx_cp6_restore(cp_flags);
+}
+static void
+iop13xx_irq_mask3 (unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
+        iop13xx_cp6_restore(cp_flags);
+}
+static void
+iop13xx_irq_unmask0(unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
+        iop13xx_cp6_restore(cp_flags);
+}
+static void
+iop13xx_irq_unmask1(unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
+        iop13xx_cp6_restore(cp_flags);
+}
+static void
+iop13xx_irq_unmask2(unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
+        iop13xx_cp6_restore(cp_flags);
+}
+static void
+iop13xx_irq_unmask3(unsigned int irq)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
+        iop13xx_cp6_restore(cp_flags);
+}
+static struct irqchip iop13xx_irqchip0 = {
+        .ack    = iop13xx_irq_mask0,
+        .mask   = iop13xx_irq_mask0,
+        .unmask = iop13xx_irq_unmask0,
+};
+static struct irqchip iop13xx_irqchip1 = {
+        .ack    = iop13xx_irq_mask1,
+        .mask   = iop13xx_irq_mask1,
+        .unmask = iop13xx_irq_unmask1,
+};
+static struct irqchip iop13xx_irqchip2 = {
+        .ack    = iop13xx_irq_mask2,
+        .mask   = iop13xx_irq_mask2,
+        .unmask = iop13xx_irq_unmask2,
+};
+static struct irqchip iop13xx_irqchip3 = {
+        .ack    = iop13xx_irq_mask3,
+        .mask   = iop13xx_irq_mask3,
+        .unmask = iop13xx_irq_unmask3,
+};
+void __init iop13xx_init_irq(void)
+{
+        unsigned int i;
+        u32 cp_flags = iop13xx_cp6_save();
+        /* disable all interrupts */
+        write_intctl_0(0);
+        write_intctl_1(0);
+        write_intctl_2(0);
+        write_intctl_3(0);
+        /* treat all as IRQ */
+        write_intstr_0(0);
+        write_intstr_1(0);
+        write_intstr_2(0);
+        write_intstr_3(0);
+        /* initialize the interrupt vector generator */
+        write_intbase(INTBASE);
+        write_intsize(INTSIZE_4);
+        for(i = 0; i < NR_IOP13XX_IRQS; i++) {
+                if (i < 32)
+                        set_irq_chip(i, &iop13xx_irqchip0);
+                else if (i < 64)
+                        set_irq_chip(i, &iop13xx_irqchip1);
+                else if (i < 96)
+                        set_irq_chip(i, &iop13xx_irqchip2);
+                else
+                        set_irq_chip(i, &iop13xx_irqchip3);
+                set_irq_handler(i, do_level_IRQ);
+                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+        }
+        iop13xx_cp6_restore(cp_flags);
+}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
new file mode 100644
index 000000000000..89ec70ea3187
--- /dev/null
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -0,0 +1,1113 @@
+/*
+ * iop13xx PCI support
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/sizes.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/pci.h>
+#define IOP13XX_PCI_DEBUG 0
+#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
+u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
+u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
+static struct pci_bus *pci_bus_atux = 0;
+static struct pci_bus *pci_bus_atue = 0;
+u32 iop13xx_atue_mem_base;
+u32 iop13xx_atux_mem_base;
+size_t iop13xx_atue_mem_size;
+size_t iop13xx_atux_mem_size;
+unsigned long iop13xx_pcibios_min_io = 0;
+unsigned long iop13xx_pcibios_min_mem = 0;
+EXPORT_SYMBOL(iop13xx_atue_mem_base);
+EXPORT_SYMBOL(iop13xx_atux_mem_base);
+EXPORT_SYMBOL(iop13xx_atue_mem_size);
+EXPORT_SYMBOL(iop13xx_atux_mem_size);
+int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
+static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
+                                                 access */
+/* Scan the initialized busses and ioremap the requested memory range
+ */
+void iop13xx_map_pci_memory(void)
+{
+        int atu;
+        struct pci_bus *bus;
+        struct pci_dev *dev;
+        resource_size_t end = 0;
+        for (atu = 0; atu < 2; atu++) {
+                bus = atu ? pci_bus_atue : pci_bus_atux;
+                if (bus) {
+                        list_for_each_entry(dev, &bus->devices, bus_list) {
+                                int i;
+                                int max = 7;
+                                if (dev->subordinate)
+                                        max = DEVICE_COUNT_RESOURCE;
+                                for (i = 0; i < max; i++) {
+                                        struct resource *res = &dev->resource[i];
+                                        if (res->flags & IORESOURCE_MEM)
+                                                end = max(res->end, end);
+                                }
+                        }
+                        switch(atu) {
+                        case 0:
+                                iop13xx_atux_mem_size =
+                                        (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
+                                /* 16MB align the request */
+                                if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
+                                        iop13xx_atux_mem_size &= ~(SZ_16M - 1);
+                                        iop13xx_atux_mem_size += SZ_16M;
+                                }
+                                if (end) {
+                                        iop13xx_atux_mem_base =
+                                        (u32) __ioremap_pfn(
+                                        __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
+                                        , 0, iop13xx_atux_mem_size, 0);
+                                        if (!iop13xx_atux_mem_base) {
+                                                printk("%s: atux allocation "
+                                                       "failed\n", __FUNCTION__);
+                                                BUG();
+                                        }
+                                } else
+                                        iop13xx_atux_mem_size = 0;
+                                PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                                __FUNCTION__, atu, iop13xx_atux_mem_size,
+                                iop13xx_atux_mem_base);
+                                break;
+                        case 1:
+                                iop13xx_atue_mem_size =
+                                        (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
+                                /* 16MB align the request */
+                                if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
+                                        iop13xx_atue_mem_size &= ~(SZ_16M - 1);
+                                        iop13xx_atue_mem_size += SZ_16M;
+                                }
+                                if (end) {
+                                        iop13xx_atue_mem_base =
+                                        (u32) __ioremap_pfn(
+                                        __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
+                                        , 0, iop13xx_atue_mem_size, 0);
+                                        if (!iop13xx_atue_mem_base) {
+                                                printk("%s: atue allocation "
+                                                       "failed\n", __FUNCTION__);
+                                                BUG();
+                                        }
+                                } else
+                                        iop13xx_atue_mem_size = 0;
+                                PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                                __FUNCTION__, atu, iop13xx_atue_mem_size,
+                                iop13xx_atue_mem_base);
+                                break;
+                        }
+                        printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
+                        atu ? "ATUE" : "ATUX",
+                        (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
+                        SZ_1M,
+                        atu ? IOP13XX_PCIE_LOWER_MEM_RA :
+                        IOP13XX_PCIX_LOWER_MEM_RA,
+                        atu ? iop13xx_atue_mem_base :
+                        iop13xx_atux_mem_base);
+                        end = 0;
+                }
+        }
+}
+static inline int iop13xx_atu_function(int atu)
+{
+        int func = 0;
+        /* the function number depends on the value of the
+         * IOP13XX_INTERFACE_SEL_PCIX reset strap
+         * see C-Spec section 3.17
+         */
+        switch(atu) {
+        case IOP13XX_INIT_ATU_ATUX:
+                if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
+                        func = 5;
+                else
+                        func = 0;
+                break;
+        case IOP13XX_INIT_ATU_ATUE:
+                if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
+                        func = 0;
+                else
+                        func = 5;
+                break;
+        default:
+                BUG();
+        }
+        return func;
+}
+/* iop13xx_atux_cfg_address - format a configuration address for atux
+ * @bus: Target bus to access
+ * @devfn: Combined device number and function number
+ * @where: Desired register's address offset
+ *
+ * Convert the parameters to a configuration address formatted
+ * according the PCI-X 2.0 specification
+ */
+static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
+{
+        struct pci_sys_data *sys = bus->sysdata;
+        u32 addr;
+        if (sys->busnr == bus->number)
+                addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
+        else
+                addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
+        addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
+        addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
+        return addr;
+}
+/* iop13xx_atue_cfg_address - format a configuration address for atue
+ * @bus: Target bus to access
+ * @devfn: Combined device number and function number
+ * @where: Desired register's address offset
+ *
+ * Convert the parameters to an address usable by the ATUE_OCCAR
+ */
+static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
+{
+        struct pci_sys_data *sys = bus->sysdata;
+        u32 addr;
+        PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
+                bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
+        addr = ((u32) bus->number)     << IOP13XX_ATUE_OCCAR_BUS_NUM |
+                   ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
+                   ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
+                   (where & ~0x3);
+        if (sys->busnr != bus->number)
+                addr |= 1; /* type 1 access */
+        return addr;
+}
+/* This routine checks the status of the last configuration cycle.  If an error
+ * was detected it returns >0, else it returns a 0.  The errors being checked
+ * are parity, master abort, target abort (master and target).  These types of
+ * errors occure during a config cycle where there is no device, like during
+ * the discovery stage.
+ */
+static int iop13xx_atux_pci_status(int clear)
+{
+        unsigned int status;
+        int err = 0;
+        /*
+         * Check the status registers.
+         */
+        status = __raw_readw(IOP13XX_ATUX_ATUSR);
+        if (status & IOP_PCI_STATUS_ERROR)
+        {
+                PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
+                if(clear)
+                        __raw_writew(status & IOP_PCI_STATUS_ERROR,
+                                IOP13XX_ATUX_ATUSR);
+                err = 1;
+        }
+        status = __raw_readl(IOP13XX_ATUX_ATUISR);
+        if (status & IOP13XX_ATUX_ATUISR_ERROR)
+        {
+                PRINTK("\t\t\tPCI error interrupt:  ATUISR %#08x", status);
+                if(clear)
+                        __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
+                                IOP13XX_ATUX_ATUISR);
+                err = 1;
+        }
+        return err;
+}
+/* Simply write the address register and read the configuration
+ * data.  Note that the data dependency on %0 encourages an abort
+ * to be detected before we return.
+ */
+static inline u32 iop13xx_atux_read(unsigned long addr)
+{
+        u32 val;
+        __asm__ __volatile__(
+                "str    %1, [%2]\n\t"
+                "ldr    %0, [%3]\n\t"
+                "mov    %0, %0\n\t"
+                : "=r" (val)
+                : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
+        return val;
+}
+/* The read routines must check the error status of the last configuration
+ * cycle.  If there was an error, the routine returns all hex f's.
+ */
+static int
+iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+                int size, u32 *value)
+{
+        unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
+        u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
+        if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
+                __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
+                        IOP13XX_XBG_BECSR);
+                val = 0xffffffff;
+        }
+        *value = val;
+        return PCIBIOS_SUCCESSFUL;
+}
+static int
+iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+                int size, u32 value)
+{
+        unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
+        u32 val;
+        if (size != 4) {
+                val = iop13xx_atux_read(addr);
+                if (!iop13xx_atux_pci_status(1) == 0)
+                        return PCIBIOS_SUCCESSFUL;
+                where = (where & 3) * 8;
+                if (size == 1)
+                        val &= ~(0xff << where);
+                else
+                        val &= ~(0xffff << where);
+                __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
+        } else {
+                __raw_writel(addr, IOP13XX_ATUX_OCCAR);
+                __raw_writel(value, IOP13XX_ATUX_OCCDR);
+        }
+        return PCIBIOS_SUCCESSFUL;
+}
+static struct pci_ops iop13xx_atux_ops = {
+        .read   = iop13xx_atux_read_config,
+        .write  = iop13xx_atux_write_config,
+};
+/* This routine checks the status of the last configuration cycle.  If an error
+ * was detected it returns >0, else it returns a 0.  The errors being checked
+ * are parity, master abort, target abort (master and target).  These types of
+ * errors occure during a config cycle where there is no device, like during
+ * the discovery stage.
+ */
+static int iop13xx_atue_pci_status(int clear)
+{
+        unsigned int status;
+        int err = 0;
+        /*
+         * Check the status registers.
+         */
+        /* standard pci status register */
+        status = __raw_readw(IOP13XX_ATUE_ATUSR);
+        if (status & IOP_PCI_STATUS_ERROR) {
+                PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
+                if(clear)
+                        __raw_writew(status & IOP_PCI_STATUS_ERROR,
+                                IOP13XX_ATUE_ATUSR);
+                err++;
+        }
+        /* check the normal status bits in the ATUISR */
+        status = __raw_readl(IOP13XX_ATUE_ATUISR);
+        if (status & IOP13XX_ATUE_ATUISR_ERROR) {
+                PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
+                if (clear)
+                        __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
+                                IOP13XX_ATUE_ATUISR);
+                err++;
+                /* check the PCI-E status if the ATUISR reports an interface error */
+                if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
+                        /* get the unmasked errors */
+                        status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
+                                        ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
+                        if (status) {
+                                PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
+                                        __raw_readl(IOP13XX_ATUE_PIE_STS));
+                                err++;
+                        } else {
+                                PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
+                                        __raw_readl(IOP13XX_ATUE_PIE_STS));
+                                PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
+                                        __raw_readl(IOP13XX_ATUE_PIE_MSK));
+                                BUG();
+                        }
+                        if(clear)
+                                __raw_writel(status, IOP13XX_ATUE_PIE_STS);
+                }
+        }
+        return err;
+}
+static inline int __init
+iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+{
+        WARN_ON(idsel != 0);
+        switch (pin) {
+        case 1: return ATUE_INTA;
+        case 2: return ATUE_INTB;
+        case 3: return ATUE_INTC;
+        case 4: return ATUE_INTD;
+        default: return -1;
+        }
+}
+static inline u32 iop13xx_atue_read(unsigned long addr)
+{
+        u32 val;
+        __raw_writel(addr, IOP13XX_ATUE_OCCAR);
+        val = __raw_readl(IOP13XX_ATUE_OCCDR);
+        rmb();
+        return val;
+}
+/* The read routines must check the error status of the last configuration
+ * cycle.  If there was an error, the routine returns all hex f's.
+ */
+static int
+iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+                int size, u32 *value)
+{
+        u32 val;
+        unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
+        /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
+        if (!PCI_SLOT(devfn) || (addr & 1)) {
+                val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
+                if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
+                        __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
+                                IOP13XX_XBG_BECSR);
+                        val = 0xffffffff;
+                }
+                PRINTK("addr=%#0lx, val=%#010x", addr, val);
+        } else
+                val = 0xffffffff;
+        *value = val;
+        return PCIBIOS_SUCCESSFUL;
+}
+static int
+iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+                int size, u32 value)
+{
+        unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
+        u32 val;
+        if (size != 4) {
+                val = iop13xx_atue_read(addr);
+                if (!iop13xx_atue_pci_status(1) == 0)
+                        return PCIBIOS_SUCCESSFUL;
+                where = (where & 3) * 8;
+                if (size == 1)
+                        val &= ~(0xff << where);
+                else
+                        val &= ~(0xffff << where);
+                __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
+        } else {
+                __raw_writel(addr, IOP13XX_ATUE_OCCAR);
+                __raw_writel(value, IOP13XX_ATUE_OCCDR);
+        }
+        return PCIBIOS_SUCCESSFUL;
+}
+static struct pci_ops iop13xx_atue_ops = {
+        .read   = iop13xx_atue_read_config,
+        .write  = iop13xx_atue_write_config,
+};
+/* When a PCI device does not exist during config cycles, the XScale gets a
+ * bus error instead of returning 0xffffffff.  We can't rely on the ATU status
+ * bits to tell us that it was indeed a configuration cycle that caused this
+ * error especially in the case when the ATUE link is down.  Instead we rely
+ * on data from the south XSI bridge to validate the abort
+ */
+int
+iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+{
+        PRINTK("Data abort: address = 0x%08lx "
+                    "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
+                addr, fsr, regs->ARM_pc, regs->ARM_lr);
+        PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
+        PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
+        PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
+        /*  If it was an imprecise abort, then we need to correct the
+         *  return address to be _after_ the instruction.
+         */
+        if (fsr & (1 << 10))
+                regs->ARM_pc += 4;
+        if (is_atue_occdr_error() || is_atux_occdr_error())
+                return 0;
+        else
+                return 1;
+}
+/* Scan an IOP13XX PCI bus.  nr selects which ATU we use.
+ */
+struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        int which_atu;
+        struct pci_bus *bus = NULL;
+        switch (init_atu) {
+        case IOP13XX_INIT_ATU_ATUX:
+                which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
+                break;
+        case IOP13XX_INIT_ATU_ATUE:
+                which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
+                break;
+        case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
+                which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
+                break;
+        default:
+                which_atu = 0;
+        }
+        if (!which_atu) {
+                BUG();
+                return NULL;
+        }
+        switch (which_atu) {
+        case IOP13XX_INIT_ATU_ATUX:
+                if (time_after_eq(jiffies + msecs_to_jiffies(1000),
+                                  atux_trhfa_timeout))  /* ensure not wrap */
+                        while(time_before(jiffies, atux_trhfa_timeout))
+                                udelay(100);
+                bus = pci_bus_atux = pci_scan_bus(sys->busnr,
+                                                  &iop13xx_atux_ops,
+                                                  sys);
+                break;
+        case IOP13XX_INIT_ATU_ATUE:
+                bus = pci_bus_atue = pci_scan_bus(sys->busnr,
+                                                  &iop13xx_atue_ops,
+                                                  sys);
+                break;
+        }
+        return bus;
+}
+/* This function is called from iop13xx_pci_init() after assigning valid
+ * values to iop13xx_atue_pmmr_offset.  This is the location for common
+ * setup of ATUE for all IOP13XX implementations.
+ */
+void __init iop13xx_atue_setup(void)
+{
+        int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
+        u32 reg_val;
+        /* BAR 1 (1:1 mapping with Physical RAM) */
+        /* Set limit and enable */
+        __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
+                        IOP13XX_ATUE_IALR1);
+        __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
+        /* Set base at the top of the reserved address space */
+        __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
+                        PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
+        /* 1:1 mapping with physical ram
+         * (leave big endian byte swap disabled)
+         */
+         __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
+         __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
+        /* Outbound window 1 (PCIX/PCIE memory window) */
+        /* 32 bit Address Space */
+        __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
+        /* PA[35:32] */
+        __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
+                        (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
+                        IOP13XX_ATUE_OUMBAR1);
+        /* Setup the I/O Bar
+         * A[35-16] in 31-12
+         */
+        __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
+                IOP13XX_ATUE_OIOBAR);
+        __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
+        /* clear startup errors */
+        iop13xx_atue_pci_status(1);
+        /* OIOBAR function number
+         */
+        reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
+        reg_val &= ~0x7;
+        reg_val |= func;
+        __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
+        /* OUMBAR function numbers
+         */
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
+        /* Enable inbound and outbound cycles
+         */
+        reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
+        reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+                        PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
+        __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
+        reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
+        reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
+                        IOP13XX_ATUE_ATUCR_IVM;
+        __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
+}
+void __init iop13xx_atue_disable(void)
+{
+        u32 reg_val;
+        __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
+        __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
+        /* wait for cycles to quiesce */
+        while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
+                                             IOP13XX_ATUE_PCSR_IN_Q_BUSY |
+                                             IOP13XX_ATUE_PCSR_LLRB_BUSY))
+                cpu_relax();
+        /* BAR 0 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
+        __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
+        __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
+        __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
+        __raw_writel(0x0, IOP13XX_ATUE_IALR0);
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
+        reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
+        /* BAR 1 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
+        __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
+        __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
+        __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
+        __raw_writel(0x0, IOP13XX_ATUE_IALR1);
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
+        reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
+        /* BAR 2 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
+        __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
+        __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
+        __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
+        __raw_writel(0x0, IOP13XX_ATUE_IALR2);
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
+        reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
+        /* BAR 3 ( Disabled ) */
+        reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
+        reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
+        /* Setup the I/O Bar
+         * A[35-16] in 31-12
+         */
+        __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
+                        IOP13XX_ATUE_OIOBAR);
+        __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
+}
+/* This function is called from iop13xx_pci_init() after assigning valid
+ * values to iop13xx_atux_pmmr_offset.  This is the location for common
+ * setup of ATUX for all IOP13XX implementations.
+ */
+void __init iop13xx_atux_setup(void)
+{
+        u32 reg_val;
+        int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
+        /* Take PCI-X bus out of reset if bootloader hasn't already.
+         * According to spec, we should wait for 2^25 PCI clocks to meet
+         * the PCI timing parameter Trhfa (RST# high to first access).
+         * This is rarely necessary and often ignored.
+         */
+        reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
+        if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
+                int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
+                msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
+                __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
+                                IOP13XX_ATUX_PCSR);
+                atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
+        }
+        else
+                atux_trhfa_timeout = jiffies;
+        /* BAR 1 (1:1 mapping with Physical RAM) */
+        /* Set limit and enable */
+        __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
+                        IOP13XX_ATUX_IALR1);
+        __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
+        /* Set base at the top of the reserved address space */
+        __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
+                        PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
+        /* 1:1 mapping with physical ram
+         * (leave big endian byte swap disabled)
+         */
+        __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
+        __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
+        /* Outbound window 1 (PCIX/PCIE memory window) */
+        /* 32 bit Address Space */
+        __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
+        /* PA[35:32] */
+        __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
+                        IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
+                        IOP13XX_ATUX_OUMBAR1);
+        /* Setup the I/O Bar
+         * A[35-16] in 31-12
+         */
+        __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
+                IOP13XX_ATUX_OIOBAR);
+        __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
+        /* clear startup errors */
+        iop13xx_atux_pci_status(1);
+        /* OIOBAR function number
+         */
+        reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
+        reg_val &= ~0x7;
+        reg_val |= func;
+        __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
+        /* OUMBAR function numbers
+         */
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
+        reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
+                        IOP13XX_ATU_OUMBAR_FUNC_NUM);
+        reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
+        /* Enable inbound and outbound cycles
+         */
+        reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
+        reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+                        PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
+        __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
+        reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
+        reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
+        __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
+}
+void __init iop13xx_atux_disable(void)
+{
+        u32 reg_val;
+        __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
+        __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
+        /* wait for cycles to quiesce */
+        while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
+                                     IOP13XX_ATUX_PCSR_IN_Q_BUSY))
+                cpu_relax();
+        /* BAR 0 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
+        __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
+        __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
+        __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
+        __raw_writel(0x0, IOP13XX_ATUX_IALR0);
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
+        reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
+        /* BAR 1 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
+        __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
+        __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
+        __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
+        __raw_writel(0x0, IOP13XX_ATUX_IALR1);
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
+        reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
+        /* BAR 2 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
+        __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
+        __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
+        __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
+        __raw_writel(0x0, IOP13XX_ATUX_IALR2);
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
+        reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
+        /* BAR 3 ( Disabled ) */
+        __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
+        __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
+        __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
+        __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
+        __raw_writel(0x0, IOP13XX_ATUX_IALR3);
+        reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
+        reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
+        __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
+        /* Setup the I/O Bar
+        * A[35-16] in 31-12
+        */
+        __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
+                        IOP13XX_ATUX_OIOBAR);
+        __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
+}
+void __init iop13xx_set_atu_mmr_bases(void)
+{
+        /* Based on ESSR0, determine the ATU X/E offsets */
+        switch(__raw_readl(IOP13XX_ESSR0) &
+                (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
+        /* both asserted */
+        case 0:
+                iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
+                iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
+                break;
+        /* IOP13XX_CONTROLLER_ONLY = deasserted
+         * IOP13XX_INTERFACE_SEL_PCIX = asserted
+         */
+        case IOP13XX_CONTROLLER_ONLY:
+                iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
+                iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
+                break;
+        /* IOP13XX_CONTROLLER_ONLY = asserted
+         * IOP13XX_INTERFACE_SEL_PCIX = deasserted
+         */
+        case IOP13XX_INTERFACE_SEL_PCIX:
+                iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
+                iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
+                break;
+        /* both deasserted */
+        case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
+                iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
+                iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
+                break;
+        default:
+                BUG();
+        }
+}
+void __init iop13xx_atu_select(struct hw_pci *plat_pci)
+{
+        int i;
+        /* set system defaults
+         * note: if "iop13xx_init_atu=" is specified this autodetect
+         * sequence will be bypassed
+         */
+        if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
+                /* check for single/dual interface */
+                if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
+                        /* ATUE must be present check the device id
+                         * to see if ATUX is present.
+                         */
+                        init_atu |= IOP13XX_INIT_ATU_ATUE;
+                        switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
+                        case 0x70:
+                        case 0x80:
+                        case 0xc0:
+                                init_atu |= IOP13XX_INIT_ATU_ATUX;
+                                break;
+                        }
+                } else {
+                        /* ATUX must be present check the device id
+                         * to see if ATUE is present.
+                         */
+                        init_atu |= IOP13XX_INIT_ATU_ATUX;
+                        switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
+                        case 0x70:
+                        case 0x80:
+                        case 0xc0:
+                                init_atu |= IOP13XX_INIT_ATU_ATUE;
+                                break;
+                        }
+                }
+                /* check central resource and root complex capability */
+                if (init_atu & IOP13XX_INIT_ATU_ATUX)
+                        if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
+                                IOP13XX_ATUX_PCSR_CENTRAL_RES))
+                                init_atu &= ~IOP13XX_INIT_ATU_ATUX;
+                if (init_atu & IOP13XX_INIT_ATU_ATUE)
+                        if (__raw_readl(IOP13XX_ATUE_PCSR) &
+                                IOP13XX_ATUE_PCSR_END_POINT)
+                                init_atu &= ~IOP13XX_INIT_ATU_ATUE;
+        }
+        for (i = 0; i < 2; i++) {
+                if((init_atu & (1 << i)) == (1 << i))
+                        plat_pci->nr_controllers++;
+        }
+}
+void __init iop13xx_pci_init(void)
+{
+        /* clear pre-existing south bridge errors */
+        __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
+        /* Setup the Min Address for PCI memory... */
+        iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
+        /* if Linux is given control of an ATU
+         * clear out its prior configuration,
+         * otherwise do not touch the registers
+         */
+        if (init_atu & IOP13XX_INIT_ATU_ATUE) {
+                iop13xx_atue_disable();
+                iop13xx_atue_setup();
+        }
+        if (init_atu & IOP13XX_INIT_ATU_ATUX) {
+                iop13xx_atux_disable();
+                iop13xx_atux_setup();
+        }
+        hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS,
+                        "imprecise external abort");
+}
+/* intialize the pci memory space.  handle any combination of
+ * atue and atux enabled/disabled
+ */
+int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
+{
+        struct resource *res;
+        int which_atu;
+        u32 pcixsr, pcsr;
+        if (nr > 1)
+                return 0;
+        res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        if (!res)
+                panic("PCI: unable to alloc resources");
+        memset(res, 0, sizeof(struct resource) * 2);
+        /* 'nr' assumptions:
+         * ATUX is always 0
+         * ATUE is 1 when ATUX is also enabled
+         * ATUE is 0 when ATUX is disabled
+         */
+        switch(init_atu) {
+        case IOP13XX_INIT_ATU_ATUX:
+                which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
+                break;
+        case IOP13XX_INIT_ATU_ATUE:
+                which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
+                break;
+        case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
+                which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
+                break;
+        default:
+                which_atu = 0;
+        }
+        if (!which_atu)
+                return 0;
+        switch(which_atu) {
+        case IOP13XX_INIT_ATU_ATUX:
+                pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
+                pcixsr &= ~0xffff;
+                pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
+                          0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
+                          iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
+                                  << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
+                __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
+                res[0].start = IOP13XX_PCIX_LOWER_IO_PA;
+                res[0].end   = IOP13XX_PCIX_UPPER_IO_PA;
+                res[0].name  = "IQ81340 ATUX PCI I/O Space";
+                res[0].flags = IORESOURCE_IO;
+                res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
+                res[1].end   = IOP13XX_PCIX_UPPER_MEM_RA;
+                res[1].name  = "IQ81340 ATUX PCI Memory Space";
+                res[1].flags = IORESOURCE_MEM;
+                sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
+                sys->io_offset = IOP13XX_PCIX_IO_OFFSET;
+                break;
+        case IOP13XX_INIT_ATU_ATUE:
+                /* Note: the function number field in the PCSR is ro */
+                pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
+                pcsr &= ~(0xfff8 << 16);
+                pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
+                                0 << IOP13XX_ATUE_PCSR_DEV_NUM;
+                __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
+                res[0].start = IOP13XX_PCIE_LOWER_IO_PA;
+                res[0].end   = IOP13XX_PCIE_UPPER_IO_PA;
+                res[0].name  = "IQ81340 ATUE PCI I/O Space";
+                res[0].flags = IORESOURCE_IO;
+                res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
+                res[1].end   = IOP13XX_PCIE_UPPER_MEM_RA;
+                res[1].name  = "IQ81340 ATUE PCI Memory Space";
+                res[1].flags = IORESOURCE_MEM;
+                sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
+                sys->io_offset = IOP13XX_PCIE_IO_OFFSET;
+                sys->map_irq = iop13xx_pcie_map_irq;
+                break;
+        default:
+                return 0;
+        }
+        request_resource(&ioport_resource, &res[0]);
+        request_resource(&iomem_resource, &res[1]);
+        sys->resource[0] = &res[0];
+        sys->resource[1] = &res[1];
+        sys->resource[2] = NULL;
+        return 1;
+}
+u16 iop13xx_dev_id(void)
+{
+        if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
+                return __raw_readw(IOP13XX_ATUE_DID);
+        else
+                return __raw_readw(IOP13XX_ATUX_DID);
+}
+static int __init iop13xx_init_atu_setup(char *str)
+{
+        init_atu = IOP13XX_INIT_ATU_NONE;
+        if (str) {
+                while (*str != '\0') {
+                        switch (*str) {
+                        case 'x':
+                        case 'X':
+                                init_atu |= IOP13XX_INIT_ATU_ATUX;
+                                init_atu &= ~IOP13XX_INIT_ATU_NONE;
+                                break;
+                        case 'e':
+                        case 'E':
+                                init_atu |= IOP13XX_INIT_ATU_ATUE;
+                                init_atu &= ~IOP13XX_INIT_ATU_NONE;
+                                break;
+                        case ',':
+                        case '=':
+                                break;
+                        default:
+                                PRINTK("\"iop13xx_init_atu\" malformed at "
+                                            "character: \'%c\'", *str);
+                                *(str + 1) = '\0';
+                                init_atu = IOP13XX_INIT_ATU_DEFAULT;
+                        }
+                        str++;
+                }
+        }
+        return 1;
+}
+__setup("iop13xx_init_atu", iop13xx_init_atu_setup);
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
new file mode 100644
index 000000000000..3756d2ccb1a7
--- /dev/null
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -0,0 +1,406 @@
+/*
+ * iop13xx platform Initialization
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#include <linux/serial_8250.h>
+#ifdef CONFIG_MTD_PHYSMAP
+#include <linux/mtd/physmap.h>
+#endif
+#include <asm/mach/map.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#define IOP13XX_UART_XTAL 33334000
+#define IOP13XX_SETUP_DEBUG 0
+#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
+/* Standard IO mapping for all IOP13XX based systems
+ */
+static struct map_desc iop13xx_std_desc[] __initdata = {
+        {    /* mem mapped registers */
+                .virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
+                .pfn     = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
+                .length  = IOP13XX_PMMR_SIZE,
+                .type    = MT_DEVICE,
+        }, { /* PCIE IO space */
+                .virtual = IOP13XX_PCIE_LOWER_IO_VA,
+                .pfn     = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
+                .length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
+                .type    = MT_DEVICE,
+        }, { /* PCIX IO space */
+                .virtual = IOP13XX_PCIX_LOWER_IO_VA,
+                .pfn     = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
+                .length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
+                .type    = MT_DEVICE,
+        },
+};
+static struct resource iop13xx_uart0_resources[] = {
+        [0] = {
+                .start = IOP13XX_UART0_PHYS,
+                .end = IOP13XX_UART0_PHYS + 0x3f,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_UART0,
+                .end = IRQ_IOP13XX_UART0,
+                .flags = IORESOURCE_IRQ
+        }
+};
+static struct resource iop13xx_uart1_resources[] = {
+        [0] = {
+                .start = IOP13XX_UART1_PHYS,
+                .end = IOP13XX_UART1_PHYS + 0x3f,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_UART1,
+                .end = IRQ_IOP13XX_UART1,
+                .flags = IORESOURCE_IRQ
+        }
+};
+static struct plat_serial8250_port iop13xx_uart0_data[] = {
+        {
+       .membase     = (char*)(IOP13XX_UART0_VIRT),
+       .mapbase     = (IOP13XX_UART0_PHYS),
+       .irq         = IRQ_IOP13XX_UART0,
+       .uartclk     = IOP13XX_UART_XTAL,
+       .regshift    = 2,
+       .iotype      = UPIO_MEM,
+       .flags       = UPF_SKIP_TEST,
+        },
+        {  },
+};
+static struct plat_serial8250_port iop13xx_uart1_data[] = {
+        {
+       .membase     = (char*)(IOP13XX_UART1_VIRT),
+       .mapbase     = (IOP13XX_UART1_PHYS),
+       .irq         = IRQ_IOP13XX_UART1,
+       .uartclk     = IOP13XX_UART_XTAL,
+       .regshift    = 2,
+       .iotype      = UPIO_MEM,
+       .flags       = UPF_SKIP_TEST,
+        },
+        {  },
+};
+/* The ids are fixed up later in iop13xx_platform_init */
+static struct platform_device iop13xx_uart0 = {
+       .name = "serial8250",
+       .id = 0,
+       .dev.platform_data = iop13xx_uart0_data,
+       .num_resources = 2,
+       .resource = iop13xx_uart0_resources,
+};
+static struct platform_device iop13xx_uart1 = {
+       .name = "serial8250",
+       .id = 0,
+       .dev.platform_data = iop13xx_uart1_data,
+       .num_resources = 2,
+       .resource = iop13xx_uart1_resources
+};
+static struct resource iop13xx_i2c_0_resources[] = {
+        [0] = {
+                .start = IOP13XX_I2C0_PHYS,
+                .end = IOP13XX_I2C0_PHYS + 0x18,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_I2C_0,
+                .end = IRQ_IOP13XX_I2C_0,
+                .flags = IORESOURCE_IRQ
+        }
+};
+static struct resource iop13xx_i2c_1_resources[] = {
+        [0] = {
+                .start = IOP13XX_I2C1_PHYS,
+                .end = IOP13XX_I2C1_PHYS + 0x18,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_I2C_1,
+                .end = IRQ_IOP13XX_I2C_1,
+                .flags = IORESOURCE_IRQ
+        }
+};
+static struct resource iop13xx_i2c_2_resources[] = {
+        [0] = {
+                .start = IOP13XX_I2C2_PHYS,
+                .end = IOP13XX_I2C2_PHYS + 0x18,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_I2C_2,
+                .end = IRQ_IOP13XX_I2C_2,
+                .flags = IORESOURCE_IRQ
+        }
+};
+/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
+ * we just use the same device name.
+ */
+/* The ids are fixed up later in iop13xx_platform_init */
+static struct platform_device iop13xx_i2c_0_controller = {
+        .name = "IOP3xx-I2C",
+        .id = 0,
+        .num_resources = 2,
+        .resource = iop13xx_i2c_0_resources
+};
+static struct platform_device iop13xx_i2c_1_controller = {
+        .name = "IOP3xx-I2C",
+        .id = 0,
+        .num_resources = 2,
+        .resource = iop13xx_i2c_1_resources
+};
+static struct platform_device iop13xx_i2c_2_controller = {
+        .name = "IOP3xx-I2C",
+        .id = 0,
+        .num_resources = 2,
+        .resource = iop13xx_i2c_2_resources
+};
+#ifdef CONFIG_MTD_PHYSMAP
+/* PBI Flash Device
+ */
+static struct physmap_flash_data iq8134x_flash_data = {
+        .width = 2,
+};
+static struct resource iq8134x_flash_resource = {
+        .start = IQ81340_FLASHBASE,
+        .end   = 0,
+        .flags = IORESOURCE_MEM,
+};
+static struct platform_device iq8134x_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = { .platform_data  = &iq8134x_flash_data, },
+        .num_resources  = 1,
+        .resource       = &iq8134x_flash_resource,
+};
+static unsigned long iq8134x_probe_flash_size(void)
+{
+        uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
+        int i;
+        char query[3];
+        unsigned long size = 0;
+        int width = iq8134x_flash_data.width;
+        if (flash_addr) {
+                /* send CFI 'query' command */
+                writew(0x98, flash_addr);
+                /* check for CFI compliance */
+                for (i = 0; i < 3 * width; i += width)
+                        query[i / width] = readb(flash_addr + (0x10 * width) + i);
+                /* read the size */
+                if (memcmp(query, "QRY", 3) == 0)
+                        size = 1 << readb(flash_addr + (0x27 * width));
+                /* send CFI 'read array' command */
+                writew(0xff, flash_addr);
+                iounmap(flash_addr);
+        }
+        return size;
+}
+#endif
+void __init iop13xx_map_io(void)
+{
+        /* Initialize the Static Page Table maps */
+        iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
+}
+static int init_uart = 0;
+static int init_i2c = 0;
+void __init iop13xx_platform_init(void)
+{
+        int i;
+        u32 uart_idx, i2c_idx, plat_idx;
+        struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
+        /* set the bases so we can read the device id */
+        iop13xx_set_atu_mmr_bases();
+        memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
+        if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
+                switch (iop13xx_dev_id()) {
+                /* enable both uarts on iop341 and iop342 */
+                case 0x3380:
+                case 0x3384:
+                case 0x3388:
+                case 0x338c:
+                case 0x3382:
+                case 0x3386:
+                case 0x338a:
+                case 0x338e:
+                        init_uart |= IOP13XX_INIT_UART_0;
+                        init_uart |= IOP13XX_INIT_UART_1;
+                        break;
+                /* only enable uart 1 */
+                default:
+                        init_uart |= IOP13XX_INIT_UART_1;
+                }
+        }
+        if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
+                switch (iop13xx_dev_id()) {
+                /* enable all i2c units on iop341 and iop342 */
+                case 0x3380:
+                case 0x3384:
+                case 0x3388:
+                case 0x338c:
+                case 0x3382:
+                case 0x3386:
+                case 0x338a:
+                case 0x338e:
+                        init_i2c |= IOP13XX_INIT_I2C_0;
+                        init_i2c |= IOP13XX_INIT_I2C_1;
+                        init_i2c |= IOP13XX_INIT_I2C_2;
+                        break;
+                /* only enable i2c 1 and 2 */
+                default:
+                        init_i2c |= IOP13XX_INIT_I2C_1;
+                        init_i2c |= IOP13XX_INIT_I2C_2;
+                }
+        }
+        plat_idx = 0;
+        uart_idx = 0;
+        i2c_idx = 0;
+        /* uart 1 (if enabled) is ttyS0 */
+        if (init_uart & IOP13XX_INIT_UART_1) {
+                PRINTK("Adding uart1 to platform device list\n");
+                iop13xx_uart1.id = uart_idx++;
+                iop13xx_devices[plat_idx++] = &iop13xx_uart1;
+        }
+        if (init_uart & IOP13XX_INIT_UART_0) {
+                PRINTK("Adding uart0 to platform device list\n");
+                iop13xx_uart0.id = uart_idx++;
+                iop13xx_devices[plat_idx++] = &iop13xx_uart0;
+        }
+        for(i = 0; i < IQ81340_NUM_I2C; i++) {
+                if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
+                        printk("Adding i2c%d to platform device list\n", i);
+                switch(init_i2c & (1 << i)) {
+                case IOP13XX_INIT_I2C_0:
+                        iop13xx_i2c_0_controller.id = i2c_idx++;
+                        iop13xx_devices[plat_idx++] =
+                                &iop13xx_i2c_0_controller;
+                        break;
+                case IOP13XX_INIT_I2C_1:
+                        iop13xx_i2c_1_controller.id = i2c_idx++;
+                        iop13xx_devices[plat_idx++] =
+                                &iop13xx_i2c_1_controller;
+                        break;
+                case IOP13XX_INIT_I2C_2:
+                        iop13xx_i2c_2_controller.id = i2c_idx++;
+                        iop13xx_devices[plat_idx++] =
+                                &iop13xx_i2c_2_controller;
+                        break;
+                }
+        }
+#ifdef CONFIG_MTD_PHYSMAP
+        iq8134x_flash_resource.end = iq8134x_flash_resource.start +
+                                iq8134x_probe_flash_size();
+        if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
+                iop13xx_devices[plat_idx++] = &iq8134x_flash;
+        else
+                printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
+#endif
+        platform_add_devices(iop13xx_devices, plat_idx);
+}
+static int __init iop13xx_init_uart_setup(char *str)
+{
+        if (str) {
+                while (*str != '\0') {
+                        switch(*str) {
+                        case '0':
+                                init_uart |= IOP13XX_INIT_UART_0;
+                                break;
+                        case '1':
+                                init_uart |= IOP13XX_INIT_UART_1;
+                                break;
+                        case ',':
+                        case '=':
+                                break;
+                        default:
+                                PRINTK("\"iop13xx_init_uart\" malformed"
+                                            " at character: \'%c\'", *str);
+                                *(str + 1) = '\0';
+                                init_uart = IOP13XX_INIT_UART_DEFAULT;
+                        }
+                        str++;
+                }
+        }
+        return 1;
+}
+static int __init iop13xx_init_i2c_setup(char *str)
+{
+        if (str) {
+                while (*str != '\0') {
+                        switch(*str) {
+                        case '0':
+                                init_i2c |= IOP13XX_INIT_I2C_0;
+                                break;
+                        case '1':
+                                init_i2c |= IOP13XX_INIT_I2C_1;
+                                break;
+                        case '2':
+                                init_i2c |= IOP13XX_INIT_I2C_2;
+                                break;
+                        case ',':
+                        case '=':
+                                break;
+                        default:
+                                PRINTK("\"iop13xx_init_i2c\" malformed"
+                                            " at character: \'%c\'", *str);
+                                *(str + 1) = '\0';
+                                init_i2c = IOP13XX_INIT_I2C_DEFAULT;
+                        }
+                        str++;
+                }
+        }
+        return 1;
+}
+__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
+__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
diff --git a/arch/arm/mach-iop13xx/time.c b/arch/arm/mach-iop13xx/time.c
new file mode 100644
index 000000000000..8b21365f653f
--- /dev/null
+++ b/arch/arm/mach-iop13xx/time.c
@@ -0,0 +1,102 @@
+/*
+ * arch/arm/mach-iop13xx/time.c
+ *
+ * Timer code for IOP13xx (copied from IOP32x/IOP33x implementation)
+ *
+ * Author: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright 2002-2003 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/init.h>
+#include <linux/timex.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+static unsigned long ticks_per_jiffy;
+static unsigned long ticks_per_usec;
+static unsigned long next_jiffy_time;
+static inline u32 read_tcr1(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
+        return val;
+}
+unsigned long iop13xx_gettimeoffset(void)
+{
+        unsigned long offset;
+        u32 cp_flags;
+        cp_flags = iop13xx_cp6_save();
+        offset = next_jiffy_time - read_tcr1();
+        iop13xx_cp6_restore(cp_flags);
+        return offset / ticks_per_usec;
+}
+static irqreturn_t
+iop13xx_timer_interrupt(int irq, void *dev_id)
+{
+        u32 cp_flags = iop13xx_cp6_save();
+        write_seqlock(&xtime_lock);
+        asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1));
+        while ((signed long)(next_jiffy_time - read_tcr1())
+                                                        >= ticks_per_jiffy) {
+                timer_tick();
+                next_jiffy_time -= ticks_per_jiffy;
+        }
+        write_sequnlock(&xtime_lock);
+        iop13xx_cp6_restore(cp_flags);
+        return IRQ_HANDLED;
+}
+static struct irqaction iop13xx_timer_irq = {
+        .name           = "IOP13XX Timer Tick",
+        .handler        = iop13xx_timer_interrupt,
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+};
+void __init iop13xx_init_time(unsigned long tick_rate)
+{
+        u32 timer_ctl;
+        u32 cp_flags;
+        ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
+        ticks_per_usec = tick_rate / 1000000;
+        next_jiffy_time = 0xffffffff;
+        timer_ctl = IOP13XX_TMR_EN | IOP13XX_TMR_PRIVILEGED |
+                        IOP13XX_TMR_RELOAD | IOP13XX_TMR_RATIO_1_1;
+        /*
+         * We use timer 0 for our timer interrupt, and timer 1 as
+         * monotonic counter for tracking missed jiffies.
+         */
+        cp_flags = iop13xx_cp6_save();
+        asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1));
+        asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl));
+        asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff));
+        asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl));
+        iop13xx_cp6_restore(cp_flags);
+        setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq);
+}
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index 69d6302f40cf..3ec1cd5c4f99 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -70,7 +70,7 @@ void __init iop32x_init_irq(void)
        for (i = 0; i < NR_IRQS; i++) {
                set_irq_chip(i, &ext_chip);
-                set_irq_handler(i, do_level_IRQ);
+                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
        }
 }
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 63304b3d0d76..00b37f32d72e 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -121,7 +121,7 @@ void __init iop33x_init_irq(void)
        for (i = 0; i < NR_IRQS; i++) {
                set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
-                set_irq_handler(i, do_level_IRQ);
+                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
        }
 }
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 22c98e9dad28..27b7480f4afe 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -308,7 +308,7 @@ EXPORT_SYMBOL(gpio_line_config);
 /*************************************************************************
 * IRQ handling IXP2000
 *************************************************************************/
-static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc)
+static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
 {                               
        int i;
        unsigned long status = *IXP2000_GPIO_INST;
@@ -373,7 +373,7 @@ static void ixp2000_GPIO_irq_unmask(unsigned int irq)
        ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 }
-static struct irqchip ixp2000_GPIO_irq_chip = {
+static struct irq_chip ixp2000_GPIO_irq_chip = {
        .ack            = ixp2000_GPIO_irq_mask_ack,
        .mask           = ixp2000_GPIO_irq_mask,
        .unmask         = ixp2000_GPIO_irq_unmask,
@@ -401,7 +401,7 @@ static void ixp2000_pci_irq_unmask(unsigned int irq)
 /*
 * Error interrupts. These are used extensively by the microengine drivers
 */
-static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc)
+static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        int i;
        unsigned long status = *IXP2000_IRQ_ERR_STATUS;
@@ -426,13 +426,13 @@ static void ixp2000_err_irq_unmask(unsigned int irq)
                        (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
 }
-static struct irqchip ixp2000_err_irq_chip = {
+static struct irq_chip ixp2000_err_irq_chip = {
        .ack    = ixp2000_err_irq_mask,
        .mask   = ixp2000_err_irq_mask,
        .unmask = ixp2000_err_irq_unmask
 };
-static struct irqchip ixp2000_pci_irq_chip = {
+static struct irq_chip ixp2000_pci_irq_chip = {
        .ack    = ixp2000_pci_irq_mask,
        .mask   = ixp2000_pci_irq_mask,
        .unmask = ixp2000_pci_irq_unmask
@@ -448,7 +448,7 @@ static void ixp2000_irq_unmask(unsigned int irq)
        ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
 }
-static struct irqchip ixp2000_irq_chip = {
+static struct irq_chip ixp2000_irq_chip = {
        .ack    = ixp2000_irq_mask,
        .mask   = ixp2000_irq_mask,
        .unmask = ixp2000_irq_unmask
@@ -484,7 +484,7 @@ void __init ixp2000_init_irq(void)
        for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
                if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
                        set_irq_chip(irq, &ixp2000_irq_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, IRQF_VALID);
                } else set_irq_flags(irq, 0);
        }
@@ -493,7 +493,7 @@ void __init ixp2000_init_irq(void)
                if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
                                IXP2000_VALID_ERR_IRQ_MASK) {
                        set_irq_chip(irq, &ixp2000_err_irq_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, IRQF_VALID);
                }
                else
@@ -503,7 +503,7 @@ void __init ixp2000_init_irq(void)
        for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
                set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
        set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
@@ -516,7 +516,7 @@ void __init ixp2000_init_irq(void)
        ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
        for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
                set_irq_chip(irq, &ixp2000_pci_irq_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
 }
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index aa2655092d2d..52b368b34346 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -106,7 +106,7 @@ static void ixdp2x00_irq_unmask(unsigned int irq)
                ixp2000_release_slowport(&old_cfg);
 }
-static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
+static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        volatile u32 ex_interrupt = 0;
        static struct slowport_cfg old_cfg;
@@ -129,7 +129,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
        for(i = 0; i < board_irq_count; i++) {
                if(ex_interrupt & (1 << i))  {
-                        struct irqdesc *cpld_desc;
+                        struct irq_desc *cpld_desc;
                        int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
                        cpld_desc = irq_desc + cpld_irq;
                        desc_handle_irq(cpld_irq, cpld_desc);
@@ -139,7 +139,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
        desc->chip->unmask(irq);
 }
-static struct irqchip ixdp2x00_cpld_irq_chip = {
+static struct irq_chip ixdp2x00_cpld_irq_chip = {
        .ack    = ixdp2x00_irq_mask,
        .mask   = ixdp2x00_irq_mask,
        .unmask = ixdp2x00_irq_unmask
@@ -162,7 +162,7 @@ void ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long
        for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
                set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 9ccae9e63f70..3084a5fa751c 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -63,7 +63,7 @@ static void ixdp2x01_irq_unmask(unsigned int irq)
 static u32 valid_irq_mask;
-static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
+static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        u32 ex_interrupt;
        int i;
@@ -79,7 +79,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
        for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
                if (ex_interrupt & (1 << i)) {
-                        struct irqdesc *cpld_desc;
+                        struct irq_desc *cpld_desc;
                        int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
                        cpld_desc = irq_desc + cpld_irq;
                        desc_handle_irq(cpld_irq, cpld_desc);
@@ -89,7 +89,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
        desc->chip->unmask(irq);
 }
-static struct irqchip ixdp2x01_irq_chip = {
+static struct irq_chip ixdp2x01_irq_chip = {
        .mask   = ixdp2x01_irq_mask,
        .ack    = ixdp2x01_irq_mask,
        .unmask = ixdp2x01_irq_unmask
@@ -119,7 +119,7 @@ void __init ixdp2x01_init_irq(void)
        for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
                if (irq & valid_irq_mask) {
                        set_irq_chip(irq, &ixdp2x01_irq_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, IRQF_VALID);
                } else {
                        set_irq_flags(irq, 0);
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index d4bf1e1c0031..5a09a90c08fb 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -32,7 +32,7 @@
 #include <asm/mach/pci.h>
-static int pci_master_aborts = 0;
+static volatile int pci_master_aborts = 0;
 static int clear_master_aborts(void);
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index a704a1820048..ce6ad635a00c 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -224,14 +224,14 @@ static void ixp23xx_irq_edge_unmask(unsigned int irq)
        *intr_reg |= (1 << (irq % 32));
 }
-static struct irqchip ixp23xx_irq_level_chip = {
+static struct irq_chip ixp23xx_irq_level_chip = {
        .ack            = ixp23xx_irq_mask,
        .mask           = ixp23xx_irq_mask,
        .unmask         = ixp23xx_irq_level_unmask,
        .set_type       = ixp23xx_irq_set_type
 };
-static struct irqchip ixp23xx_irq_edge_chip = {
+static struct irq_chip ixp23xx_irq_edge_chip = {
        .ack            = ixp23xx_irq_ack,
        .mask           = ixp23xx_irq_mask,
        .unmask         = ixp23xx_irq_edge_unmask,
@@ -251,11 +251,11 @@ static void ixp23xx_pci_irq_unmask(unsigned int irq)
 /*
 * TODO: Should this just be done at ASM level?
 */
-static void pci_handler(unsigned int irq, struct irqdesc *desc)
+static void pci_handler(unsigned int irq, struct irq_desc *desc)
 {
        u32 pci_interrupt;
        unsigned int irqno;
-        struct irqdesc *int_desc;
+        struct irq_desc *int_desc;
        pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
@@ -276,7 +276,7 @@ static void pci_handler(unsigned int irq, struct irqdesc *desc)
        desc->chip->unmask(irq);
 }
-static struct irqchip ixp23xx_pci_irq_chip = {
+static struct irq_chip ixp23xx_pci_irq_chip = {
        .ack    = ixp23xx_pci_irq_mask,
        .mask   = ixp23xx_pci_irq_mask,
        .unmask = ixp23xx_pci_irq_unmask
@@ -287,11 +287,11 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
        switch (type) {
        case IXP23XX_IRQ_LEVEL:
                set_irq_chip(irq, &ixp23xx_irq_level_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                break;
        case IXP23XX_IRQ_EDGE:
                set_irq_chip(irq, &ixp23xx_irq_edge_chip);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                break;
        }
        set_irq_flags(irq, IRQF_VALID);
@@ -322,7 +322,7 @@ void __init ixp23xx_init_irq(void)
        for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
                set_irq_chip(irq, &ixp23xx_pci_irq_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index b6ab0e8bb5e8..7a86a2516eaa 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -60,7 +60,7 @@ static void ixdp2351_inta_unmask(unsigned int irq)
        *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
 }
-static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
+static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
 {
        u16 ex_interrupt =
                *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
@@ -70,7 +70,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
        for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
                if (ex_interrupt & (1 << i)) {
-                        struct irqdesc *cpld_desc;
+                        struct irq_desc *cpld_desc;
                        int cpld_irq =
                                IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
                        cpld_desc = irq_desc + cpld_irq;
@@ -81,7 +81,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
        desc->chip->unmask(irq);
 }
-static struct irqchip ixdp2351_inta_chip = {
+static struct irq_chip ixdp2351_inta_chip = {
        .ack    = ixdp2351_inta_mask,
        .mask   = ixdp2351_inta_mask,
        .unmask = ixdp2351_inta_unmask
@@ -97,7 +97,7 @@ static void ixdp2351_intb_unmask(unsigned int irq)
        *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
 }
-static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
+static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
 {
        u16 ex_interrupt =
                *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
@@ -107,7 +107,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
        for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
                if (ex_interrupt & (1 << i)) {
-                        struct irqdesc *cpld_desc;
+                        struct irq_desc *cpld_desc;
                        int cpld_irq =
                                IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
                        cpld_desc = irq_desc + cpld_irq;
@@ -118,7 +118,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
        desc->chip->unmask(irq);
 }
-static struct irqchip ixdp2351_intb_chip = {
+static struct irq_chip ixdp2351_intb_chip = {
        .ack    = ixdp2351_intb_mask,
        .mask   = ixdp2351_intb_mask,
        .unmask = ixdp2351_intb_unmask
@@ -142,7 +142,7 @@ void ixdp2351_init_irq(void)
             irq++) {
                if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
                        set_irq_flags(irq, IRQF_VALID);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_chip(irq, &ixdp2351_inta_chip);
                }
        }
@@ -153,7 +153,7 @@ void ixdp2351_init_irq(void)
             irq++) {
                if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
                        set_irq_flags(irq, IRQF_VALID);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_chip(irq, &ixdp2351_intb_chip);
                }
        }
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 3b34fa35e36b..ac7d43d23c28 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -36,7 +36,7 @@
 extern int (*external_fault) (unsigned long, struct pt_regs *);
-static int pci_master_aborts = 0;
+static volatile int pci_master_aborts = 0;
 #ifdef DEBUG
 #define DBG(x...)       printk(x)
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index fbe288a8da65..2ec9a9e9a04d 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -28,6 +28,7 @@
 #include <linux/timex.h>
 #include <linux/clocksource.h>
+#include <asm/arch/udc.h>
 #include <asm/hardware.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
@@ -39,6 +40,8 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
+static int __init ixp4xx_clocksource_init(void);
 /*************************************************************************
 * IXP4xx chipset I/O mapping
 *************************************************************************/
@@ -195,7 +198,7 @@ static void ixp4xx_irq_unmask(unsigned int irq)
                *IXP4XX_ICMR |= (1 << irq);
 }
-static struct irqchip ixp4xx_irq_chip = {
+static struct irq_chip ixp4xx_irq_chip = {
        .name           = "IXP4xx",
        .ack            = ixp4xx_irq_ack,
        .mask           = ixp4xx_irq_mask,
@@ -224,7 +227,7 @@ void __init ixp4xx_init_irq(void)
        /* Default to all level triggered */
        for(i = 0; i < NR_IRQS; i++) {
                set_irq_chip(i, &ixp4xx_irq_chip);
-                set_irq_handler(i, do_level_IRQ);
+                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID);
        }
 }
@@ -280,12 +283,52 @@ static void __init ixp4xx_timer_init(void)
        /* Connect the interrupt handler and enable the interrupt */
        setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
+        ixp4xx_clocksource_init();
 }
 struct sys_timer ixp4xx_timer = {
        .init           = ixp4xx_timer_init,
 };
+static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
+void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
+{
+        memcpy(&ixp4xx_udc_info, info, sizeof *info);
+}
+static struct resource ixp4xx_udc_resources[] = {
+        [0] = {
+                .start  = 0xc800b000,
+                .end    = 0xc800bfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_IXP4XX_USB,
+                .end    = IRQ_IXP4XX_USB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+/*
+ * USB device controller. The IXP4xx uses the same controller as PXA2XX,
+ * so we just use the same device.
+ */
+static struct platform_device ixp4xx_udc_device = {
+        .name           = "pxa2xx-udc",
+        .id             = -1,
+        .num_resources  = 2,
+        .resource       = ixp4xx_udc_resources,
+        .dev            = {
+                .platform_data = &ixp4xx_udc_info,
+        },
+};
+static struct platform_device *ixp4xx_devices[] __initdata = {
+        &ixp4xx_udc_device,
+};
 static struct resource ixp46x_i2c_resources[] = {
        [0] = {
                .start  = 0xc8011000,
@@ -321,6 +364,8 @@ void __init ixp4xx_sys_init(void)
 {
        ixp4xx_exp_bus_size = SZ_16M;
+        platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
        if (cpu_is_ixp46x()) {
                int region;
@@ -363,5 +408,3 @@ static int __init ixp4xx_clocksource_init(void)
        return 0;
 }
-device_initcall(ixp4xx_clocksource_init);
diff --git a/arch/arm/mach-l7200/core.c b/arch/arm/mach-l7200/core.c
index b7af5640ea7b..561a0fe7095d 100644
--- a/arch/arm/mach-l7200/core.c
+++ b/arch/arm/mach-l7200/core.c
@@ -55,7 +55,7 @@ static void l7200_unmask_irq(unsigned int irq)
        IRQ_ENABLE = 1 << irq;
 }
-static struct irqchip l7200_irq_chip = {
+static struct irq_chip l7200_irq_chip = {
        .ack            = l7200_mask_irq,
        .mask           = l7200_mask_irq,
        .unmask         = l7200_unmask_irq
@@ -71,7 +71,7 @@ static void __init l7200_init_irq(void)
        for (irq = 0; irq < NR_IRQS; irq++) {
                set_irq_chip(irq, &l7200_irq_chip);
                set_irq_flags(irq, IRQF_VALID);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
        }
        init_FIQ();
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c
index 15fbcc911fe7..6d26661d99f6 100644
--- a/arch/arm/mach-lh7a40x/arch-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c
@@ -71,7 +71,7 @@ static struct irq_chip kev7a400_cpld_chip = {
 };
-static void kev7a400_cpld_handler (unsigned int irq, struct irqdesc *desc)
+static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
 {
        u32 mask = CPLD_LATCHED_INTS;
        irq = IRQ_KEV7A400_CPLD;
@@ -88,7 +88,7 @@ void __init lh7a40x_init_board_irq (void)
        for (irq = IRQ_KEV7A400_CPLD;
             irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) {
                set_irq_chip (irq, &kev7a400_cpld_chip);
-                set_irq_handler (irq, do_edge_IRQ);
+                set_irq_handler (irq, handle_edge_irq);
                set_irq_flags (irq, IRQF_VALID);
        }
        set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
index 8441e0a156cb..fe64946f9e18 100644
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
@@ -207,7 +207,7 @@ static struct irq_chip lpd7a40x_cpld_chip = {
        .unmask = lh7a40x_unmask_cpld_irq,
 };
-static void lpd7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc)
+static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
 {
        unsigned int mask = CPLD_INTERRUPTS;
@@ -279,7 +279,7 @@ void __init lh7a40x_init_board_irq (void)
        for (irq = IRQ_BOARD_START;
             irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
                set_irq_chip (irq, &lpd7a40x_cpld_chip);
-                set_irq_handler (irq, do_level_IRQ);
+                set_irq_handler (irq, handle_level_irq);
                set_irq_flags (irq, IRQF_VALID);
        }
diff --git a/arch/arm/mach-lh7a40x/irq-kev7a400.c b/arch/arm/mach-lh7a40x/irq-kev7a400.c
index 646071334b8f..c7433b3c5812 100644
--- a/arch/arm/mach-lh7a40x/irq-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/irq-kev7a400.c
@@ -51,7 +51,7 @@ irq_chip lh7a400_cpld_chip = {
 };
 static void
-lh7a400_cpld_handler (unsigned int irq, struct irqdesc *desc)
+lh7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
 {
        u32 mask = CPLD_LATCHED_INTS;
        irq = IRQ_KEV_7A400_CPLD;
@@ -71,7 +71,7 @@ lh7a400_init_board_irq (void)
        for (irq = IRQ_KEV7A400_CPLD;
             irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) {
                set_irq_chip (irq, &lh7a400_cpld_chip);
-                set_irq_handler (irq, do_edge_IRQ);
+                set_irq_handler (irq, handle_edge_irq);
                set_irq_flags (irq, IRQF_VALID);
        }
        set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c
index 091b2dc58d25..0b938e8b4d98 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a400.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c
@@ -74,11 +74,11 @@ void __init lh7a400_init_irq (void)
                case IRQ_GPIO6INTR:
                case IRQ_GPIO7INTR:
                        set_irq_chip (irq, &lh7a400_gpio_chip);
-                        set_irq_handler (irq, do_level_IRQ); /* OK default */
+                        set_irq_handler (irq, handle_level_irq); /* OK default */
                        break;
                default:
                        set_irq_chip (irq, &lh7a400_internal_chip);
-                        set_irq_handler (irq, do_level_IRQ);
+                        set_irq_handler (irq, handle_level_irq);
                }
                set_irq_flags (irq, IRQF_VALID);
        }
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c
index 7059b983724f..5760f8c53e89 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a404.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c
@@ -161,13 +161,13 @@ void __init lh7a404_init_irq (void)
                        set_irq_chip (irq, irq < 32
                                      ? &lh7a404_gpio_vic1_chip
                                      : &lh7a404_gpio_vic2_chip);
-                        set_irq_handler (irq, do_level_IRQ); /* OK default */
+                        set_irq_handler (irq, handle_level_irq); /* OK default */
                        break;
                default:
                        set_irq_chip (irq, irq < 32
                                      ? &lh7a404_vic1_chip
                                      : &lh7a404_vic2_chip);
-                        set_irq_handler (irq, do_level_IRQ);
+                        set_irq_handler (irq, handle_level_irq);
                }
                set_irq_flags (irq, IRQF_VALID);
        }
diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
index b20376804bbb..15b9577023c9 100644
--- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
@@ -57,7 +57,7 @@ static struct irq_chip lh7a40x_cpld_chip = {
        .unmask = lh7a40x_unmask_cpld_irq,
 };
-static void lh7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc)
+static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
 {
        unsigned int mask = CPLD_INTERRUPTS;
@@ -118,7 +118,7 @@ void __init lh7a40x_init_board_irq (void)
        for (irq = IRQ_BOARD_START;
             irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
                set_irq_chip (irq, &lh7a40x_cpld_chip);
-                set_irq_handler (irq, do_edge_IRQ);
+                set_irq_handler (irq, handle_edge_irq);
                set_irq_flags (irq, IRQF_VALID);
        }
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index edbbbdc3b06b..b9ca8f98265d 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -69,7 +69,7 @@ static struct platform_device *devices[] __initdata = {
 #endif
 static void
-netx_hif_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 {
        unsigned int irq = NETX_IRQ_HIF_CHAINED(0);
        unsigned int stat;
@@ -160,7 +160,7 @@ netx_hif_unmask_irq(unsigned int _irq)
        DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq);
 }
-static struct irqchip netx_hif_chip = {
+static struct irq_chip netx_hif_chip = {
        .ack = netx_hif_ack_irq,
        .mask = netx_hif_mask_irq,
        .unmask = netx_hif_unmask_irq,
@@ -175,7 +175,7 @@ void __init netx_init_irq(void)
        for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
                set_irq_chip(irq, &netx_hif_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 8e40208b10bb..30e188109046 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -84,9 +84,9 @@ static void fpga_mask_ack_irq(unsigned int irq)
        fpga_ack_irq(irq);
 }
-void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc)
+void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
 {
-        struct irqdesc *d;
+        struct irq_desc *d;
        u32 stat;
        int fpga_irq;
@@ -168,7 +168,7 @@ void omap1510_fpga_init_irq(void)
                        set_irq_chip(i, &omap_fpga_irq);
                }
-                set_irq_handler(i, do_edge_IRQ);
+                set_irq_handler(i, handle_edge_irq);
                set_irq_flags(i, IRQF_VALID);
        }
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 3ea140bb9eba..6383a12ad970 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -229,7 +229,7 @@ void __init omap_init_irq(void)
                        omap_irq_set_cfg(j, 0, 0, irq_trigger);
                        set_irq_chip(j, &omap_irq_chip);
-                        set_irq_handler(j, do_level_IRQ);
+                        set_irq_handler(j, handle_level_irq);
                        set_irq_flags(j, IRQF_VALID);
                }
        }
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 11870093d7a1..a39d30680300 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -130,7 +130,7 @@ void __init omap_init_irq(void)
        for (i = 0; i < nr_irqs; i++) {
                set_irq_chip(i, &omap_irq_chip);
-                set_irq_handler(i, do_level_IRQ);
+                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID);
        }
 }
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 3a4bcf3d91fa..968d0b027597 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -59,22 +59,22 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
        case IRQT_RISING:
                __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq));        /*edge sensitive */
                __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq));        /*rising edge */
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                break;
        case IRQT_FALLING:
                __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq));        /*edge sensitive */
                __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq));       /*falling edge */
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                break;
        case IRQT_LOW:
                __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq));       /*level sensitive */
                __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq));       /*low level */
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                break;
        case IRQT_HIGH:
                __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq));       /*level sensitive */
                __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq));        /* high level */
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                break;
        /* IRQT_BOTHEDGE is not supported */
@@ -85,7 +85,7 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
        return 0;
 }
-static struct irqchip pnx4008_irq_chip = {
+static struct irq_chip pnx4008_irq_chip = {
        .ack = pnx4008_mask_ack_irq,
        .mask = pnx4008_mask_irq,
        .unmask = pnx4008_unmask_irq,
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 03d07cae26c8..9e3d0bdcba07 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -13,12 +13,10 @@ config ARCH_LUBBOCK
 config MACH_LOGICPD_PXA270
        bool "LogicPD PXA270 Card Engine Development Platform"
        select PXA27x
-        select IWMMXT
 config MACH_MAINSTONE
        bool "Intel HCDDBBVA0 Development Platform"
        select PXA27x
-        select IWMMXT
 config ARCH_PXA_IDP
        bool "Accelent Xscale IDP"
@@ -53,7 +51,6 @@ config PXA_SHARPSL_25x
 config PXA_SHARPSL_27x
        bool "Sharp PXA270 models (SL-Cxx00)"
        select PXA27x
-        select IWMMXT
 endchoice
@@ -129,11 +126,6 @@ config PXA27x
        help
          Select code specific to PXA27x variants
-config IWMMXT
-        bool
-        help
-          Enable support for iWMMXt
 config PXA_SHARP_C7xx
        bool
        select PXA_SSP
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 45fb2c3bcf82..6ae605857ca9 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -25,6 +25,10 @@
 #include <linux/pm.h>
 #include <linux/string.h>
+#include <linux/sched.h>
+#include <asm/cnt32_to_63.h>
+#include <asm/div64.h>
 #include <asm/hardware.h>
 #include <asm/irq.h>
 #include <asm/system.h>
@@ -41,6 +45,62 @@
 #include "generic.h"
 /*
+ * This is the PXA2xx sched_clock implementation. This has a resolution
+ * of at least 308ns and a maximum value that depends on the value of
+ * CLOCK_TICK_RATE.
+ *
+ * The return value is guaranteed to be monotonic in that range as
+ * long as there is always less than 582 seconds between successive
+ * calls to this function.
+ */
+unsigned long long sched_clock(void)
+{
+        unsigned long long v = cnt32_to_63(OSCR);
+        /* Note: top bit ov v needs cleared unless multiplier is even. */
+#if     CLOCK_TICK_RATE == 3686400
+        /* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */
+        /* The <<1 is used to get rid of tick.hi top bit */
+        v *= 78125<<1;
+        do_div(v, 288<<1);
+#elif   CLOCK_TICK_RATE == 3250000
+        /* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */
+        v *= 4000;
+        do_div(v, 13);
+#elif   CLOCK_TICK_RATE == 3249600
+        /* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */
+        v *= 625000;
+        do_div(v, 2031);
+#else
+#warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE"
+        /*
+         * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for
+         * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand
+         * years range which is nice, but with higher computation cost.
+         */
+        {
+                union {
+                        unsigned long long val;
+                        struct { unsigned long lo, hi; };
+                } x;
+                unsigned long long y;
+                x.val = v;
+                x.hi &= 0x7fffffff;
+                y = (unsigned long long)x.lo * NSEC_PER_SEC;
+                x.lo = y;
+                y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC;
+                x.hi = do_div(y, CLOCK_TICK_RATE);
+                do_div(x.val, CLOCK_TICK_RATE);
+                x.hi += y;
+                v = x.val;
+        }
+#endif
+        return v;
+}
+/*
 * Handy function to set GPIO alternate functions
 */
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index ab1a16025d51..f815678a9d63 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -143,7 +143,7 @@ static struct irq_chip pxa_low_gpio_chip = {
 * Demux handler for GPIO>=2 edge detect interrupts
 */
-static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc)
+static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
 {
        unsigned int mask;
        int loop;
@@ -286,27 +286,27 @@ void __init pxa_init_irq(void)
        for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
                set_irq_chip(irq, &pxa_internal_chip_low);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
 #if PXA_INTERNAL_IRQS > 32
        for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
                set_irq_chip(irq, &pxa_internal_chip_high);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
 #endif
        for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
                set_irq_chip(irq, &pxa_low_gpio_chip);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
        for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
                set_irq_chip(irq, &pxa_muxed_gpio_chip);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 5749f6b72e12..8e27a64fa9f4 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -75,7 +75,7 @@ static struct irq_chip lpd270_irq_chip = {
        .unmask         = lpd270_unmask_irq,
 };
-static void lpd270_irq_handler(unsigned int irq, struct irqdesc *desc)
+static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        unsigned long pending;
@@ -105,7 +105,7 @@ static void __init lpd270_init_irq(void)
        /* setup extra LogicPD PXA270 irqs */
        for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
                set_irq_chip(irq, &lpd270_irq_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
        set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 142c33c3dff5..055de7f4f00a 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -85,7 +85,7 @@ static struct irq_chip lubbock_irq_chip = {
        .unmask         = lubbock_unmask_irq,
 };
-static void lubbock_irq_handler(unsigned int irq, struct irqdesc *desc)
+static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
        do {
@@ -108,7 +108,7 @@ static void __init lubbock_init_irq(void)
        /* setup extra lubbock irqs */
        for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
                set_irq_chip(irq, &lubbock_irq_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 49c34d94a9fe..56d94d88d5ca 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -71,7 +71,7 @@ static struct irq_chip mainstone_irq_chip = {
        .unmask         = mainstone_unmask_irq,
 };
-static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc)
+static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
        do {
@@ -94,7 +94,7 @@ static void __init mainstone_init_irq(void)
        /* setup extra Mainstone irqs */
        for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
                set_irq_chip(irq, &mainstone_irq_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
                else
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 2112c414f0e2..b4d8276d6050 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -83,7 +83,8 @@ int pxa_pm_enter(suspend_state_t state)
 #ifdef CONFIG_IWMMXT
        /* force any iWMMXt context to ram **/
-        iwmmxt_task_disable(NULL);
+        if (elf_hwcap & HWCAP_IWMMXT)
+                iwmmxt_task_disable(NULL);
 #endif
        /* preserve current time */
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 3ac268fa419b..b91466861029 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -124,6 +124,7 @@ static struct irqaction pxa_timer_irq = {
 static void __init pxa_timer_init(void)
 {
        struct timespec tv;
+        unsigned long flags;
        set_rtc = pxa_set_rtc;
@@ -132,12 +133,12 @@ static void __init pxa_timer_init(void)
        do_settimeofday(&tv);
        OIER = 0;               /* disable any timer interrupts */
-        OSCR = LATCH*2;         /* push OSCR out of the way */
-        OSMR0 = LATCH;          /* set initial match */
        OSSR = 0xf;             /* clear status on all timers */
        setup_irq(IRQ_OST0, &pxa_timer_irq);
+        local_irq_save(flags);
        OIER = OIER_E0;         /* enable match on timer 0 to cause interrupts */
-        OSCR = 0;               /* initialize free-running timer */
+        OSMR0 = OSCR + LATCH;   /* set initial match */
+        local_irq_restore(flags);
 }
 #ifdef CONFIG_NO_IDLE_HZ
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 56b2716f8cf5..7a029621db43 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -34,7 +34,7 @@ static void iomd_unmask_irq_a(unsigned int irq)
        iomd_writeb(val | mask, IOMD_IRQMASKA);
 }
-static struct irqchip iomd_a_chip = {
+static struct irq_chip iomd_a_chip = {
        .ack    = iomd_ack_irq_a,
        .mask   = iomd_mask_irq_a,
        .unmask = iomd_unmask_irq_a,
@@ -58,7 +58,7 @@ static void iomd_unmask_irq_b(unsigned int irq)
        iomd_writeb(val | mask, IOMD_IRQMASKB);
 }
-static struct irqchip iomd_b_chip = {
+static struct irq_chip iomd_b_chip = {
        .ack    = iomd_mask_irq_b,
        .mask   = iomd_mask_irq_b,
        .unmask = iomd_unmask_irq_b,
@@ -82,7 +82,7 @@ static void iomd_unmask_irq_dma(unsigned int irq)
        iomd_writeb(val | mask, IOMD_DMAMASK);
 }
-static struct irqchip iomd_dma_chip = {
+static struct irq_chip iomd_dma_chip = {
        .ack    = iomd_mask_irq_dma,
        .mask   = iomd_mask_irq_dma,
        .unmask = iomd_unmask_irq_dma,
@@ -106,7 +106,7 @@ static void iomd_unmask_irq_fiq(unsigned int irq)
        iomd_writeb(val | mask, IOMD_FIQMASK);
 }
-static struct irqchip iomd_fiq_chip = {
+static struct irq_chip iomd_fiq_chip = {
        .ack    = iomd_mask_irq_fiq,
        .mask   = iomd_mask_irq_fiq,
        .unmask = iomd_unmask_irq_fiq,
@@ -134,19 +134,19 @@ void __init rpc_init_irq(void)
                switch (irq) {
                case 0 ... 7:
                        set_irq_chip(irq, &iomd_a_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, flags);
                        break;
                case 8 ... 15:
                        set_irq_chip(irq, &iomd_b_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, flags);
                        break;
                case 16 ... 21:
                        set_irq_chip(irq, &iomd_dma_chip);
-                        set_irq_handler(irq, do_level_IRQ);
+                        set_irq_handler(irq, handle_level_irq);
                        set_irq_flags(irq, flags);
                        break;
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 63965c78de8c..08b2f300eb79 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -41,9 +41,16 @@ config BAST_PC104_IRQ
          Say Y here to enable the PC104 IRQ routing on the
          Simtec BAST (EB2410ITX)
+config PM_H1940
+        bool
+        depends on PM
+        help
+          Internal node for H1940 and related PM
 config ARCH_H1940
        bool "IPAQ H1940"
        select CPU_S3C2410
+        select PM_H1940
        help
          Say Y here if you are using the HP IPAQ H1940
@@ -115,6 +122,7 @@ config MACH_VR1000
 config MACH_RX3715
        bool "HP iPAQ rx3715"
        select CPU_S3C2440
+        select PM_H1940
        help
          Say Y here if you are using the HP iPAQ rx3715.
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index d66013365b6b..27663e28cc88 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_S3C2410_DMA)	+= s3c2410-dma.o
 obj-$(CONFIG_PM)                += pm.o sleep.o
 obj-$(CONFIG_PM_SIMTEC)         += pm-simtec.o
+obj-$(CONFIG_PM_H1940)          += pm-h1940.o
 # S3C2412 support
 obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 23d5beea5568..379efe70778c 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -88,7 +88,7 @@ bast_pc104_mask(unsigned int irqno)
 static void
 bast_pc104_maskack(unsigned int irqno)
 {
-        struct irqdesc *desc = irq_desc + IRQ_ISA;
+        struct irq_desc *desc = irq_desc + IRQ_ISA;
        bast_pc104_mask(irqno);
        desc->chip->ack(IRQ_ISA);
@@ -104,7 +104,7 @@ bast_pc104_unmask(unsigned int irqno)
        __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
 }
-static struct irqchip  bast_pc104_chip = {
+static struct irq_chip  bast_pc104_chip = {
        .mask        = bast_pc104_mask,
        .unmask      = bast_pc104_unmask,
        .ack         = bast_pc104_maskack
@@ -112,7 +112,7 @@ static struct irqchip  bast_pc104_chip = {
 static void
 bast_irq_pc104_demux(unsigned int irq,
-                     struct irqdesc *desc)
+                     struct irq_desc *desc)
 {
        unsigned int stat;
        unsigned int irqno;
@@ -157,7 +157,7 @@ static __init int bast_irq_init(void)
                        unsigned int irqno = bast_pc104_irqs[i];
                        set_irq_chip(irqno, &bast_pc104_chip);
-                        set_irq_handler(irqno, do_level_IRQ);
+                        set_irq_handler(irqno, handle_level_irq);
                        set_irq_flags(irqno, IRQF_VALID);
                }
        }
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 683b3491ba3c..3c0ed7871c55 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -180,7 +180,7 @@ s3c_irq_unmask(unsigned int irqno)
        __raw_writel(mask, S3C2410_INTMSK);
 }
-struct irqchip s3c_irq_level_chip = {
+struct irq_chip s3c_irq_level_chip = {
        .name           = "s3c-level",
        .ack            = s3c_irq_maskack,
        .mask           = s3c_irq_mask,
@@ -188,7 +188,7 @@ struct irqchip s3c_irq_level_chip = {
        .set_wake       = s3c_irq_wake
 };
-static struct irqchip s3c_irq_chip = {
+static struct irq_chip s3c_irq_chip = {
        .name           = "s3c",
        .ack            = s3c_irq_ack,
        .mask           = s3c_irq_mask,
@@ -206,18 +206,6 @@ s3c_irqext_mask(unsigned int irqno)
        mask = __raw_readl(S3C24XX_EINTMASK);
        mask |= ( 1UL << irqno);
        __raw_writel(mask, S3C24XX_EINTMASK);
-        if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
-                /* check to see if all need masking */
-                if ((mask & (0xf << 4)) == (0xf << 4)) {
-                        /* all masked, mask the parent */
-                        s3c_irq_mask(IRQ_EINT4t7);
-                }
-        } else {
-                /* todo: the same check as above for the rest of the irq regs...*/
-        }
 }
 static void
@@ -229,7 +217,6 @@ s3c_irqext_ack(unsigned int irqno)
        bit = 1UL << (irqno - EXTINT_OFF);
        mask = __raw_readl(S3C24XX_EINTMASK);
        __raw_writel(bit, S3C24XX_EINTPEND);
@@ -258,8 +245,6 @@ s3c_irqext_unmask(unsigned int irqno)
        mask = __raw_readl(S3C24XX_EINTMASK);
        mask &= ~( 1UL << irqno);
        __raw_writel(mask, S3C24XX_EINTMASK);
-        s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
 }
 int
@@ -344,7 +329,7 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
        return 0;
 }
-static struct irqchip s3c_irqext_chip = {
+static struct irq_chip s3c_irqext_chip = {
        .name           = "s3c-ext",
        .mask           = s3c_irqext_mask,
        .unmask         = s3c_irqext_unmask,
@@ -353,7 +338,7 @@ static struct irqchip s3c_irqext_chip = {
        .set_wake       = s3c_irqext_wake
 };
-static struct irqchip s3c_irq_eint0t4 = {
+static struct irq_chip s3c_irq_eint0t4 = {
        .name           = "s3c-ext0",
        .ack            = s3c_irq_ack,
        .mask           = s3c_irq_mask,
@@ -390,7 +375,7 @@ s3c_irq_uart0_ack(unsigned int irqno)
        s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
 }
-static struct irqchip s3c_irq_uart0 = {
+static struct irq_chip s3c_irq_uart0 = {
        .name           = "s3c-uart0",
        .mask           = s3c_irq_uart0_mask,
        .unmask         = s3c_irq_uart0_unmask,
@@ -417,7 +402,7 @@ s3c_irq_uart1_ack(unsigned int irqno)
        s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
 }
-static struct irqchip s3c_irq_uart1 = {
+static struct irq_chip s3c_irq_uart1 = {
        .name           = "s3c-uart1",
        .mask           = s3c_irq_uart1_mask,
        .unmask         = s3c_irq_uart1_unmask,
@@ -444,7 +429,7 @@ s3c_irq_uart2_ack(unsigned int irqno)
        s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
 }
-static struct irqchip s3c_irq_uart2 = {
+static struct irq_chip s3c_irq_uart2 = {
        .name           = "s3c-uart2",
        .mask           = s3c_irq_uart2_mask,
        .unmask         = s3c_irq_uart2_unmask,
@@ -471,7 +456,7 @@ s3c_irq_adc_ack(unsigned int irqno)
        s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
 }
-static struct irqchip s3c_irq_adc = {
+static struct irq_chip s3c_irq_adc = {
        .name           = "s3c-adc",
        .mask           = s3c_irq_adc_mask,
        .unmask         = s3c_irq_adc_unmask,
@@ -480,11 +465,11 @@ static struct irqchip s3c_irq_adc = {
 /* irq demux for adc */
 static void s3c_irq_demux_adc(unsigned int irq,
-                              struct irqdesc *desc)
+                              struct irq_desc *desc)
 {
        unsigned int subsrc, submsk;
        unsigned int offset = 9;
-        struct irqdesc *mydesc;
+        struct irq_desc *mydesc;
        /* read the current pending interrupts, and the mask
         * for what it is available */
@@ -512,7 +497,7 @@ static void s3c_irq_demux_uart(unsigned int start)
 {
        unsigned int subsrc, submsk;
        unsigned int offset = start - IRQ_S3CUART_RX0;
-        struct irqdesc *desc;
+        struct irq_desc *desc;
        /* read the current pending interrupts, and the mask
         * for what it is available */
@@ -549,7 +534,7 @@ static void s3c_irq_demux_uart(unsigned int start)
 static void
 s3c_irq_demux_uart0(unsigned int irq,
-                    struct irqdesc *desc)
+                    struct irq_desc *desc)
 {
        irq = irq;
        s3c_irq_demux_uart(IRQ_S3CUART_RX0);
@@ -557,7 +542,7 @@ s3c_irq_demux_uart0(unsigned int irq,
 static void
 s3c_irq_demux_uart1(unsigned int irq,
-                    struct irqdesc *desc)
+                    struct irq_desc *desc)
 {
        irq = irq;
        s3c_irq_demux_uart(IRQ_S3CUART_RX1);
@@ -565,7 +550,7 @@ s3c_irq_demux_uart1(unsigned int irq,
 static void
 s3c_irq_demux_uart2(unsigned int irq,
-                    struct irqdesc *desc)
+                    struct irq_desc *desc)
 {
        irq = irq;
        s3c_irq_demux_uart(IRQ_S3CUART_RX2);
@@ -573,7 +558,7 @@ s3c_irq_demux_uart2(unsigned int irq,
 static void
 s3c_irq_demux_extint8(unsigned int irq,
-                      struct irqdesc *desc)
+                      struct irq_desc *desc)
 {
        unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
        unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -595,7 +580,7 @@ s3c_irq_demux_extint8(unsigned int irq,
 static void
 s3c_irq_demux_extint4t7(unsigned int irq,
-                        struct irqdesc *desc)
+                        struct irq_desc *desc)
 {
        unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
        unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -738,7 +723,7 @@ void __init s3c24xx_init_irq(void)
                case IRQ_UART2:
                case IRQ_ADCPARENT:
                        set_irq_chip(irqno, &s3c_irq_level_chip);
-                        set_irq_handler(irqno, do_level_IRQ);
+                        set_irq_handler(irqno, handle_level_irq);
                        break;
                case IRQ_RESERVED6:
@@ -749,7 +734,7 @@ void __init s3c24xx_init_irq(void)
                default:
                        //irqdbf("registering irq %d (s3c irq)\n", irqno);
                        set_irq_chip(irqno, &s3c_irq_chip);
-                        set_irq_handler(irqno, do_edge_IRQ);
+                        set_irq_handler(irqno, handle_edge_irq);
                        set_irq_flags(irqno, IRQF_VALID);
                }
        }
@@ -769,14 +754,14 @@ void __init s3c24xx_init_irq(void)
        for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
                irqdbf("registering irq %d (ext int)\n", irqno);
                set_irq_chip(irqno, &s3c_irq_eint0t4);
-                set_irq_handler(irqno, do_edge_IRQ);
+                set_irq_handler(irqno, handle_edge_irq);
                set_irq_flags(irqno, IRQF_VALID);
        }
        for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
                irqdbf("registering irq %d (extended s3c irq)\n", irqno);
                set_irq_chip(irqno, &s3c_irqext_chip);
-                set_irq_handler(irqno, do_edge_IRQ);
+                set_irq_handler(irqno, handle_edge_irq);
                set_irq_flags(irqno, IRQF_VALID);
        }
@@ -787,28 +772,28 @@ void __init s3c24xx_init_irq(void)
        for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
                irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
                set_irq_chip(irqno, &s3c_irq_uart0);
-                set_irq_handler(irqno, do_level_IRQ);
+                set_irq_handler(irqno, handle_level_irq);
                set_irq_flags(irqno, IRQF_VALID);
        }
        for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
                irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
                set_irq_chip(irqno, &s3c_irq_uart1);
-                set_irq_handler(irqno, do_level_IRQ);
+                set_irq_handler(irqno, handle_level_irq);
                set_irq_flags(irqno, IRQF_VALID);
        }
        for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
                irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
                set_irq_chip(irqno, &s3c_irq_uart2);
-                set_irq_handler(irqno, do_level_IRQ);
+                set_irq_handler(irqno, handle_level_irq);
                set_irq_flags(irqno, IRQF_VALID);
        }
        for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
                irqdbf("registering irq %d (s3c adc irq)\n", irqno);
                set_irq_chip(irqno, &s3c_irq_adc);
-                set_irq_handler(irqno, do_edge_IRQ);
+                set_irq_handler(irqno, handle_edge_irq);
                set_irq_flags(irqno, IRQF_VALID);
        }
diff --git a/arch/arm/mach-s3c2410/irq.h b/arch/arm/mach-s3c2410/irq.h
index 842a9f42c97b..3686a0082245 100644
--- a/arch/arm/mach-s3c2410/irq.h
+++ b/arch/arm/mach-s3c2410/irq.h
@@ -17,7 +17,7 @@
 #define EXTINT_OFF (IRQ_EINT4 - 4)
-extern struct irqchip s3c_irq_level_chip;
+extern struct irq_chip s3c_irq_level_chip;
 static inline void
 s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 8c895c077d22..f5b98099a5d9 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -33,6 +33,7 @@
 #include <asm/arch/regs-serial.h>
 #include <asm/arch/regs-lcd.h>
+#include <asm/arch/h1940.h>
 #include <asm/arch/h1940-latch.h>
 #include <asm/arch/fb.h>
@@ -41,6 +42,7 @@
 #include "clock.h"
 #include "devs.h"
 #include "cpu.h"
+#include "pm.h"
 static struct map_desc h1940_iodesc[] __initdata = {
        [0] = {
@@ -164,12 +166,16 @@ static void __init h1940_map_io(void)
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
        s3c24xx_set_board(&h1940_board);
+        /* setup PM */
+        memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
+        s3c2410_pm_init();
 }
 static void __init h1940_init_irq(void)
 {
        s3c24xx_init_irq();
 }
 static void __init h1940_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-osiris.c b/arch/arm/mach-s3c2410/mach-osiris.c
index e193ba69e652..a4ab144e7292 100644
--- a/arch/arm/mach-s3c2410/mach-osiris.c
+++ b/arch/arm/mach-s3c2410/mach-osiris.c
@@ -114,6 +114,15 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
                .clocks      = osiris_serial_clocks,
                .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+                .clocks      = osiris_serial_clocks,
+                .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
+        }
 };
 /* NAND Flash on Osiris board */
diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c
index 23d7c052013c..ecbcdf79d739 100644
--- a/arch/arm/mach-s3c2410/mach-rx3715.c
+++ b/arch/arm/mach-s3c2410/mach-rx3715.c
@@ -42,6 +42,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
+#include <asm/arch/h1940.h>
 #include <asm/arch/nand.h>
 #include <asm/arch/fb.h>
@@ -224,7 +225,9 @@ static void __init rx3715_init_irq(void)
 static void __init rx3715_init_machine(void)
 {
+        memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
        s3c2410_pm_init();
        s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
 }
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index a0d7692cdb2b..e2eda3937ab0 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -41,6 +41,7 @@
 #include <asm/arch/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
+#include <asm/arch/leds-gpio.h>
 #include "clock.h"
 #include "devs.h"
@@ -313,6 +314,50 @@ static struct platform_device vr1000_dm9k1 = {
        }
 };
+/* LEDS */
+static struct s3c24xx_led_platdata vr1000_led1_pdata = {
+        .name           = "led1",
+        .gpio           = S3C2410_GPB0,
+        .def_trigger    = "",
+};
+static struct s3c24xx_led_platdata vr1000_led2_pdata = {
+        .name           = "led2",
+        .gpio           = S3C2410_GPB1,
+        .def_trigger    = "",
+};
+static struct s3c24xx_led_platdata vr1000_led3_pdata = {
+        .name           = "led3",
+        .gpio           = S3C2410_GPB2,
+        .def_trigger    = "",
+};
+static struct platform_device vr1000_led1 = {
+        .name           = "s3c24xx_led",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &vr1000_led1_pdata,
+        },
+};
+static struct platform_device vr1000_led2 = {
+        .name           = "s3c24xx_led",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &vr1000_led2_pdata,
+        },
+};
+static struct platform_device vr1000_led3 = {
+        .name           = "s3c24xx_led",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &vr1000_led3_pdata,
+        },
+};
 /* devices for this board */
 static struct platform_device *vr1000_devices[] __initdata = {
@@ -325,7 +370,10 @@ static struct platform_device *vr1000_devices[] __initdata = {
        &serial_device,
        &vr1000_nor,
        &vr1000_dm9k0,
-        &vr1000_dm9k1
+        &vr1000_dm9k1,
+        &vr1000_led1,
+        &vr1000_led2,
+        &vr1000_led3,
 };
 static struct clk *vr1000_clocks[] = {
diff --git a/arch/arm/mach-s3c2410/pm-h1940.S b/arch/arm/mach-s3c2410/pm-h1940.S
new file mode 100644
index 000000000000..7d66de7ff7db
--- /dev/null
+++ b/arch/arm/mach-s3c2410/pm-h1940.S
@@ -0,0 +1,33 @@
+/* linux/arch/arm/mach-s3c2410/pm-h1940.S
+ *
+ * Copyright (c) 2006 Ben Dooks <ben-linux@fluff.org>
+ *
+ * H1940 Suspend to RAM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/hardware.h>
+#include <asm/arch/map.h>
+#include <asm/arch/regs-gpio.h>
+        .text
+        .global h1940_pm_return
+h1940_pm_return:
+        mov     r0, #S3C2410_PA_GPIO
+        ldr     pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ]
diff --git a/arch/arm/mach-s3c2410/s3c2410-pm.c b/arch/arm/mach-s3c2410/s3c2410-pm.c
index e51d76669512..77c6814c0f05 100644
--- a/arch/arm/mach-s3c2410/s3c2410-pm.c
+++ b/arch/arm/mach-s3c2410/s3c2410-pm.c
@@ -32,6 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/arch/regs-gpio.h>
+#include <asm/arch/h1940.h>
 #include "cpu.h"
 #include "pm.h"
@@ -52,6 +53,35 @@ static void s3c2410_pm_prepare(void)
        DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
        DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
+        if (machine_is_h1940()) {
+                void *base = phys_to_virt(H1940_SUSPEND_CHECK);
+                unsigned long ptr;
+                unsigned long calc = 0;
+                /* generate check for the bootloader to check on resume */
+                for (ptr = 0; ptr < 0x40000; ptr += 0x400)
+                        calc += __raw_readl(base+ptr);
+                __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
+        }
+        /* the RX3715 uses similar code and the same H1940 and the
+         * same offsets for resume and checksum pointers */
+        if (machine_is_rx3715()) {
+                void *base = phys_to_virt(H1940_SUSPEND_CHECK);
+                unsigned long ptr;
+                unsigned long calc = 0;
+                /* generate check for the bootloader to check on resume */
+                for (ptr = 0; ptr < 0x40000; ptr += 0x4)
+                        calc += __raw_readl(base+ptr);
+                __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
+        }
        if ( machine_is_aml_m5900() )
                s3c2410_gpio_setpin(S3C2410_GPF2, 1);
diff --git a/arch/arm/mach-s3c2410/s3c2412-irq.c b/arch/arm/mach-s3c2410/s3c2412-irq.c
index 7f741547658f..ffcc30b23a80 100644
--- a/arch/arm/mach-s3c2410/s3c2412-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2412-irq.c
@@ -98,7 +98,7 @@ s3c2412_irq_unmask(unsigned int irqno)
        __raw_writel(mask & ~bitval, S3C2410_INTMSK);
 }
-static struct irqchip s3c2412_irq_eint0t4 = {
+static struct irq_chip s3c2412_irq_eint0t4 = {
        .ack       = s3c2412_irq_ack,
        .mask      = s3c2412_irq_mask,
        .unmask    = s3c2412_irq_unmask,
@@ -112,7 +112,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
        for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
                set_irq_chip(irqno, &s3c2412_irq_eint0t4);
-                set_irq_handler(irqno, do_edge_IRQ);
+                set_irq_handler(irqno, handle_edge_irq);
                set_irq_flags(irqno, IRQF_VALID);
        }
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c
index 39db0752d53b..1ba19b27ab05 100644
--- a/arch/arm/mach-s3c2410/s3c2440-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2440-irq.c
@@ -42,10 +42,10 @@
 /* WDT/AC97 */
 static void s3c_irq_demux_wdtac97(unsigned int irq,
-                                  struct irqdesc *desc)
+                                  struct irq_desc *desc)
 {
        unsigned int subsrc, submsk;
-        struct irqdesc *mydesc;
+        struct irq_desc *mydesc;
        /* read the current pending interrupts, and the mask
         * for what it is available */
@@ -90,7 +90,7 @@ s3c_irq_wdtac97_ack(unsigned int irqno)
        s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
 }
-static struct irqchip s3c_irq_wdtac97 = {
+static struct irq_chip s3c_irq_wdtac97 = {
        .mask       = s3c_irq_wdtac97_mask,
        .unmask     = s3c_irq_wdtac97_unmask,
        .ack        = s3c_irq_wdtac97_ack,
@@ -105,12 +105,12 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
        /* add new chained handler for wdt, ac7 */
        set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
-        set_irq_handler(IRQ_WDT, do_level_IRQ);
+        set_irq_handler(IRQ_WDT, handle_level_irq);
        set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
        for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
                set_irq_chip(irqno, &s3c_irq_wdtac97);
-                set_irq_handler(irqno, do_level_IRQ);
+                set_irq_handler(irqno, handle_level_irq);
                set_irq_flags(irqno, IRQF_VALID);
        }
diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c
index 146f2109dd90..ede94636a72a 100644
--- a/arch/arm/mach-s3c2410/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2410/s3c244x-irq.c
@@ -42,10 +42,10 @@
 /* camera irq */
 static void s3c_irq_demux_cam(unsigned int irq,
-                              struct irqdesc *desc)
+                              struct irq_desc *desc)
 {
        unsigned int subsrc, submsk;
-        struct irqdesc *mydesc;
+        struct irq_desc *mydesc;
        /* read the current pending interrupts, and the mask
         * for what it is available */
@@ -89,7 +89,7 @@ s3c_irq_cam_ack(unsigned int irqno)
        s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
 }
-static struct irqchip s3c_irq_cam = {
+static struct irq_chip s3c_irq_cam = {
        .mask       = s3c_irq_cam_mask,
        .unmask     = s3c_irq_cam_unmask,
        .ack        = s3c_irq_cam_ack,
@@ -100,18 +100,18 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
        unsigned int irqno;
        set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
-        set_irq_handler(IRQ_NFCON, do_level_IRQ);
+        set_irq_handler(IRQ_NFCON, handle_level_irq);
        set_irq_flags(IRQ_NFCON, IRQF_VALID);
        /* add chained handler for camera */
        set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
-        set_irq_handler(IRQ_CAM, do_level_IRQ);
+        set_irq_handler(IRQ_CAM, handle_level_irq);
        set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
        for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
                set_irq_chip(irqno, &s3c_irq_cam);
-                set_irq_handler(irqno, do_level_IRQ);
+                set_irq_handler(irqno, handle_level_irq);
                set_irq_flags(irqno, IRQF_VALID);
        }
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 4575f316e141..e510295c2580 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -20,6 +20,7 @@
 #include <linux/platform_device.h>
 #include <asm/div64.h>
+#include <asm/cnt32_to_63.h>
 #include <asm/hardware.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -118,15 +119,21 @@ EXPORT_SYMBOL(cpufreq_get);
 /*
 * This is the SA11x0 sched_clock implementation.  This has
- * a resolution of 271ns, and a maximum value of 1165s.
+ * a resolution of 271ns, and a maximum value of 32025597s (370 days).
+ *
+ * The return value is guaranteed to be monotonic in that range as
+ * long as there is always less than 582 seconds between successive
+ * calls to this function.
+ *
 *  ( * 1E9 / 3686400 => * 78125 / 288)
 */
 unsigned long long sched_clock(void)
 {
-        unsigned long long v;
+        unsigned long long v = cnt32_to_63(OSCR);
-        v = (unsigned long long)OSCR * 78125;
+        /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
-        do_div(v, 288);
+        v *= 78125<<1;
+        do_div(v, 288<<1);
        return v;
 }
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index fa6dc71bd6ad..b034ad69a324 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -702,7 +702,7 @@ static u32 gpio_irq_mask[] = {
        GPIO2_SD_CON_SLT,
 };
-static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc)
+static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc)
 {
        int i;
@@ -719,14 +719,14 @@ static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc)
                if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq);
                for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++)
                        if (irq & kpio_irq_mask[j])
-                                do_edge_IRQ(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j);
+                                handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j);
                /* GPIO2 */
                irq = H3800_ASIC2_GPIINTFLAG;
                if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq);
                for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++)
                        if (irq & gpio_irq_mask[j])
-                                do_edge_IRQ(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j);
+                                handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j);
        }
        if (i >= MAX_ASIC_ISR_LOOPS)
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index f4c6322ca33e..5642aeca079e 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -110,7 +110,7 @@ static struct irq_chip sa1100_low_gpio_chip = {
 * and call the handler.
 */
 static void
-sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc)
+sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
 {
        unsigned int mask;
@@ -327,19 +327,19 @@ void __init sa1100_init_irq(void)
        for (irq = 0; irq <= 10; irq++) {
                set_irq_chip(irq, &sa1100_low_gpio_chip);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
        for (irq = 12; irq <= 31; irq++) {
                set_irq_chip(irq, &sa1100_normal_chip);
-                set_irq_handler(irq, do_level_IRQ);
+                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
        for (irq = 32; irq <= 48; irq++) {
                set_irq_chip(irq, &sa1100_high_gpio_chip);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 354d5e91da59..075d4d1d63be 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -29,12 +29,12 @@
 * is rather unfortunate.
 */
 static void
-neponset_irq_handler(unsigned int irq, struct irqdesc *desc)
+neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        unsigned int irr;
        while (1) {
-                struct irqdesc *d;
+                struct irq_desc *d;
                /*
                 * Acknowledge the parent IRQ.
@@ -168,9 +168,9 @@ static int neponset_probe(struct platform_device *dev)
         * Setup other Neponset IRQs.  SA1111 will be done by the
         * generic SA1111 code.
         */
-        set_irq_handler(IRQ_NEPONSET_SMC9196, do_simple_IRQ);
+        set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
        set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
-        set_irq_handler(IRQ_NEPONSET_USAR, do_simple_IRQ);
+        set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
        set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
        /*
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 4284bd6f7a1f..29c89f9eb2ce 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -118,6 +118,7 @@ static struct irqaction sa1100_timer_irq = {
 static void __init sa1100_timer_init(void)
 {
        struct timespec tv;
+        unsigned long flags;
        set_rtc = sa1100_set_rtc;
@@ -126,12 +127,12 @@ static void __init sa1100_timer_init(void)
        do_settimeofday(&tv);
        OIER = 0;               /* disable any timer interrupts */
-        OSCR = LATCH*2;         /* push OSCR out of the way */
-        OSMR0 = LATCH;          /* set initial match */
        OSSR = 0xf;             /* clear status on all timers */
        setup_irq(IRQ_OST0, &sa1100_timer_irq);
+        local_irq_save(flags);
        OIER = OIER_E0;         /* enable match on timer 0 to cause interrupts */
-        OSCR = 0;               /* initialize free-running timer */
+        OSMR0 = OSCR + LATCH;   /* set initial match */
+        local_irq_restore(flags);
 }
 #ifdef CONFIG_NO_IDLE_HZ
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c
index 297ecf130650..00a6c1466867 100644
--- a/arch/arm/mach-shark/irq.c
+++ b/arch/arm/mach-shark/irq.c
@@ -82,7 +82,7 @@ void __init shark_init_irq(void)
        for (irq = 0; irq < NR_IRQS; irq++) {
                set_irq_chip(irq, &fb_chip);
-                set_irq_handler(irq, do_edge_IRQ);
+                set_irq_handler(irq, handle_edge_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 3b8576111c16..57196947559f 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -27,6 +27,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <asm/cnt32_to_63.h>
 #include <asm/system.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
@@ -77,7 +78,7 @@ static struct irq_chip sic_chip = {
 };
 static void
-sic_handle_irq(unsigned int irq, struct irqdesc *desc)
+sic_handle_irq(unsigned int irq, struct irq_desc *desc)
 {
        unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
@@ -123,7 +124,7 @@ void __init versatile_init_irq(void)
        for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
                if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
                        set_irq_chip(i, &sic_chip);
-                        set_irq_handler(i, do_level_IRQ);
+                        set_irq_handler(i, handle_level_irq);
                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                }
        }
@@ -228,14 +229,19 @@ void __init versatile_map_io(void)
 /*
 * This is the Versatile sched_clock implementation.  This has
- * a resolution of 41.7ns, and a maximum value of about 179s.
+ * a resolution of 41.7ns, and a maximum value of about 35583 days.
+ *
+ * The return value is guaranteed to be monotonic in that range as
+ * long as there is always less than 89 seconds between successive
+ * calls to this function.
 */
 unsigned long long sched_clock(void)
 {
-        unsigned long long v;
+        unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
-        v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
+        /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
-        do_div(v, 3);
+        v *= 125<<1;
+        do_div(v, 3<<1);
        return v;
 }
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 503725b166fc..be439bb9d450 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -81,22 +81,18 @@ static struct amba_device *amba_devs[] __initdata = {
        &mmc1_device,
 };
-static int __init versatile_pb_init(void)
+static void __init versatile_pb_init(void)
 {
        int i;
-        if (machine_is_versatile_pb()) {
+        versatile_init();
-                for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-                        struct amba_device *d = amba_devs[i];
-                        amba_device_register(d, &iomem_resource);
-                }
-        }
-        return 0;
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
 }
-arch_initcall(versatile_pb_init);
 MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
        .phys_io        = 0x101f1000,
@@ -105,5 +101,5 @@ MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
        .map_io         = versatile_map_io,
        .init_irq       = versatile_init_irq,
        .timer          = &versatile_timer,
-        .init_machine   = versatile_init,
+        .init_machine   = versatile_pb_init,
 MACHINE_END
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c0bfb8212b77..125cb3ff5589 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -333,7 +333,7 @@ config CPU_XSCALE
 # XScale Core Version 3
 config CPU_XSC3
        bool
-        depends on ARCH_IXP23XX
+        depends on ARCH_IXP23XX || ARCH_IOP13XX
        default y
        select CPU_32v5
        select CPU_ABRT_EV5T
@@ -580,7 +580,7 @@ config CPU_CACHE_ROUND_ROBIN
 config CPU_BPREDICT_DISABLE
        bool "Disable branch prediction"
-        depends on CPU_ARM1020 || CPU_V6
+        depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3
        help
          Say Y here to disable branch prediction.  If unsure, say N.
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index bb2bc9ab6bd3..a44e30970635 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -1,4 +1,7 @@
 /* the upper-most page table pointer */
+#ifdef CONFIG_MMU
 extern pmd_t *top_pmd;
 #define TOP_PTE(x)      pte_offset_kernel(top_pmd, x)
@@ -13,6 +16,8 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
        return pmd_off(pgd_offset_k(virt), virt);
 }
+#endif
 struct map_desc;
 struct meminfo;
 struct pglist_data;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index f866bf6b97d4..b7f194af20b4 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -265,7 +265,7 @@ static void __init build_mem_type_table(void)
        if (arch_is_coherent()) {
                if (cpu_is_xsc3()) {
                        mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-                        mem_types[MT_MEMORY].prot_pte |= L_PTE_COHERENT;
+                        mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
                }
        }
@@ -619,6 +619,13 @@ void __init reserve_node_zero(pg_data_t *pgdat)
        if (machine_is_p720t())
                res_size = 0x00014000;
+        /* H1940 and RX3715 need to reserve this for suspend */
+        if (machine_is_h1940() || machine_is_rx3715()) {
+                reserve_bootmem_node(pgdat, 0x30003000, 0x1000);
+                reserve_bootmem_node(pgdat, 0x30081000, 0x1000);
+        }
 #ifdef CONFIG_SA1111
        /*
         * Because of the SA1111 DMA bug, we want to preserve our
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index d0e66424a597..05818fc0c705 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -6,10 +6,12 @@
 #include <linux/module.h>
 #include <linux/mm.h>
 #include <linux/pagemap.h>
+#include <linux/bootmem.h>
 #include <asm/cacheflush.h>
 #include <asm/io.h>
 #include <asm/page.h>
+#include <asm/mach/arch.h>
 #include "mm.h"
@@ -76,7 +78,7 @@ void __iomem *__ioremap(unsigned long phys_addr, size_t size,
 }
 EXPORT_SYMBOL(__ioremap);
-void __iounmap(void __iomem *addr)
+void __iounmap(volatile void __iomem *addr)
 {
 }
 EXPORT_SYMBOL(__iounmap);
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 1d8316f3cecf..289b8e6f504d 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -29,9 +29,9 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 89b1d6d3d7c0..bed9db6ba582 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -29,9 +29,9 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index a089528e6bce..d2a7c1b9cab9 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -18,9 +18,9 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index d6d84d92c7c7..3247ce5c0177 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -18,9 +18,9 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 0432e4806888..ce4f9eef763c 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -15,9 +15,9 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 ENTRY(cpu_arm6_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index c2f0705bfd49..c04c194da785 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -36,9 +36,9 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 40713818a87b..7069f495cf9b 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -12,9 +12,9 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
        .text
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 22d7e3100ea6..d091c2571823 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -12,9 +12,9 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
        .text
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 4adb46b3a4e0..65cbb2851bff 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -28,9 +28,9 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 571f082f0247..52761b70d735 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -29,9 +29,9 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 8d9a9f93b011..5b74339d1588 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -52,9 +52,9 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 44a7a652d625..8628ed29a955 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -28,9 +28,9 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 2397f4b6e151..786c593778f0 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -11,9 +11,9 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 /* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index e18617564421..a60c1421d450 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -13,9 +13,9 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 /*
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 918ebf65d4f6..4848eeac86b6 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -12,9 +12,9 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
        .text
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index c878064e9b88..cd7d865c9d19 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -17,7 +17,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/procinfo.h>
+#include <asm/elf.h>
 #include <asm/hardware.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index b23b66a6155a..b776653cc31c 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -22,7 +22,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/procinfo.h>
+#include <asm/elf.h>
 #include <asm/hardware.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 6f72549f8843..b440c8a1d345 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -13,8 +13,8 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/elf.h>
 #include <asm/hardware/arm_scu.h>
-#include <asm/procinfo.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 4ace2d8090c7..1ef564d0957f 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -27,7 +27,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/procinfo.h>
+#include <asm/elf.h>
 #include <asm/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/pgtable-hwdef.h>
@@ -57,11 +57,6 @@
 #define L2_CACHE_ENABLE 1
 /*
- * Enable the Branch Target Buffer (can cause crashes, see erratum #42.)
- */
-#define BTB_ENABLE      0
-/*
 * This macro is used to wait for a CP15 write and is needed
 * when we have to ensure that the last operation to the co-pro
 * was completed before continuing with operation.
@@ -371,8 +366,10 @@ ENTRY(cpu_xsc3_switch_mm)
 ENTRY(cpu_xsc3_set_pte)
        str     r1, [r0], #-2048                @ linux version
-        bic     r2, r1, #0xdf0                  @ Keep C, B, coherency bits
+        bic     r2, r1, #0xff0                  @ Keep C, B bits
        orr     r2, r2, #PTE_TYPE_EXT           @ extended page
+        tst     r1, #L_PTE_SHARED               @ Shared?
+        orrne   r2, r2, #0x200
        eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -432,9 +429,7 @@ __xsc3_setup:
        mrc     p15, 0, r0, c1, c0, 0           @ get control register
        bic     r0, r0, r5                      @ .... .... .... ..A.
        orr     r0, r0, r6                      @ .... .... .... .C.M
-#if BTB_ENABLE
        orr     r0, r0, #0x00000800             @ ..VI Z..S .... ....
-#endif
 #if L2_CACHE_ENABLE
        orr     r0, r0, #0x04000000             @ L2 enable
 #endif
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 2749c1f88d7d..cc1004b3e511 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -23,7 +23,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/procinfo.h>
+#include <asm/elf.h>
 #include <asm/pgtable.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/page.h>
@@ -491,12 +491,7 @@ __xscale_setup:
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I, D caches & BTB
        mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I, D TLBs
-#ifdef CONFIG_IWMMXT
+        mov     r0, #1 << 6                     @ cp6 for IOP3xx and Bulverde
-        mov     r0, #0                          @ initially disallow access to CP0/CP1
-#else
-        mov     r0, #1                          @ Allow access to CP0
-#endif
-        orr     r0, r0, #1 << 6                 @ cp6 for IOP3xx and Bulverde
        orr     r0, r0, #1 << 13                @ Its undefined whether this
        mcr     p15, 0, r0, c15, c1, 0          @ affects USR or SVC modes
@@ -909,7 +904,7 @@ __pxa270_proc_info:
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
-        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_IWMMXT
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
        .long   cpu_pxa270_name
        .long   xscale_processor_functions
        .long   v4wbi_tlb_fns
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 8162eed8b500..4f2fd5591337 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -410,7 +410,7 @@ static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int tr
                trigger & __IRQT_RISEDGE);
        MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
                trigger & __IRQT_FALEDGE);
-        /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
+        /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
         * triggering requested. */
 }
@@ -783,7 +783,7 @@ void omap_free_gpio(int gpio)
 * line's interrupt handler has been run, we may miss some nested
 * interrupts.
 */
-static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
+static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        void __iomem *isr_reg = NULL;
        u32 isr;
@@ -853,7 +853,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
                gpio_irq = bank->virtual_irq_start;
                for (; isr != 0; isr >>= 1, gpio_irq++) {
-                        struct irqdesc *d;
+                        struct irq_desc *d;
                        int irq_mask;
                        if (!(isr & 1))
                                continue;
@@ -1092,7 +1092,7 @@ static int __init _omap_gpio_init(void)
                                set_irq_chip(j, &mpuio_irq_chip);
                        else
                                set_irq_chip(j, &gpio_irq_chip);
-                        set_irq_handler(j, do_simple_IRQ);
+                        set_irq_handler(j, handle_simple_irq);
                        set_irq_flags(j, IRQF_VALID);
                }
                set_irq_chained_handler(bank->irq, gpio_irq_handler);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 579c69ae9ff7..8bcb838e5444 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Mon Oct 16 21:13:36 2006
+# Last update: Thu Dec 7 17:19:20 2006
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -79,7 +79,7 @@ psionw			ARCH_PSIONW		PSIONW			60
 aln                     SA1100_ALN              ALN                     61
 epxa                    ARCH_CAMELOT            CAMELOT                 62
 gds2200                 SA1100_GDS2200          GDS2200                 63
-psion_series7           SA1100_PSION_SERIES7    PSION_SERIES7           64
+netbook                 SA1100_PSION_SERIES7    PSION_SERIES7           64
 xfile                   SA1100_XFILE            XFILE                   65
 accelent_ep9312         ARCH_ACCELENT_EP9312    ACCELENT_EP9312         66
 ic200                   ARCH_IC200              IC200                   67
@@ -810,9 +810,9 @@ sb3010			MACH_SB3010		SB3010			795
 rm9200                  MACH_RM9200             RM9200                  796
 dma03                   MACH_DMA03              DMA03                   797
 road_s101               MACH_ROAD_S101          ROAD_S101               798
-iq_nextgen_a            MACH_IQ_NEXTGEN_A       IQ_NEXTGEN_A            799
+iq81340sc               MACH_IQ81340SC          IQ81340SC               799
 iq_nextgen_b            MACH_IQ_NEXTGEN_B       IQ_NEXTGEN_B            800
-iq_nextgen_c            MACH_IQ_NEXTGEN_C       IQ_NEXTGEN_C            801
+iq81340mc               MACH_IQ81340MC          IQ81340MC               801
 iq_nextgen_d            MACH_IQ_NEXTGEN_D       IQ_NEXTGEN_D            802
 iq_nextgen_e            MACH_IQ_NEXTGEN_E       IQ_NEXTGEN_E            803
 mallow_at91             MACH_MALLOW_AT91        MALLOW_AT91             804
@@ -1165,9 +1165,57 @@ pnx4010			MACH_PNX4010		PNX4010			1151
 oxnas                   MACH_OXNAS              OXNAS                   1152
 fiori                   MACH_FIORI              FIORI                   1153
 ml1200                  MACH_ML1200             ML1200                  1154
-cactus                  MACH_CACTUS             CACTUS                  1155
+pecos                   MACH_PECOS              PECOS                   1155
 nb2xxx                  MACH_NB2XXX             NB2XXX                  1156
 hw6900                  MACH_HW6900             HW6900                  1157
 cdcs_quoll              MACH_CDCS_QUOLL         CDCS_QUOLL              1158
 quicksilver             MACH_QUICKSILVER        QUICKSILVER             1159
 uplat926                MACH_UPLAT926           UPLAT926                1160
+dep2410_dep2410         MACH_DEP2410_THOMAS     DEP2410_THOMAS          1161
+dtk2410                 MACH_DTK2410            DTK2410                 1162
+chili                   MACH_CHILI              CHILI                   1163
+demeter                 MACH_DEMETER            DEMETER                 1164
+dionysus                MACH_DIONYSUS           DIONYSUS                1165
+as352x                  MACH_AS352X             AS352X                  1166
+service                 MACH_SERVICE            SERVICE                 1167
+cs_e9301                MACH_CS_E9301           CS_E9301                1168
+micro9m                 MACH_MICRO9M            MICRO9M                 1169
+ia_mospck               MACH_IA_MOSPCK          IA_MOSPCK               1170
+ql201b                  MACH_QL201B             QL201B                  1171
+bbm                     MACH_BBM                BBM                     1174
+exxx                    MACH_EXXX               EXXX                    1175
+wma11b                  MACH_WMA11B             WMA11B                  1176
+pelco_atlas             MACH_PELCO_ATLAS        PELCO_ATLAS             1177
+g500                    MACH_G500               G500                    1178
+bug                     MACH_BUG                BUG                     1179
+mx33ads                 MACH_MX33ADS            MX33ADS                 1180
+chub                    MACH_CHUB               CHUB                    1181
+gta01                   MACH_GTA01              GTA01                   1182
+w90n740                 MACH_W90N740            W90N740                 1183
+medallion_sa2410        MACH_MEDALLION_SA2410   MEDALLION_SA2410        1184
+ia_cpu_9200_2           MACH_IA_CPU_9200_2      IA_CPU_9200_2           1185
+dimmrm9200              MACH_DIMMRM9200         DIMMRM9200              1186
+pm9261                  MACH_PM9261             PM9261                  1187
+mx21                    MACH_MX21               MX21                    1188
+ml7304                  MACH_ML7304             ML7304                  1189
+ucp250                  MACH_UCP250             UCP250                  1190
+intboard                MACH_INTBOARD           INTBOARD                1191
+gulfstream              MACH_GULFSTREAM         GULFSTREAM              1192
+labquest                MACH_LABQUEST           LABQUEST                1193
+vcmx313                 MACH_VCMX313            VCMX313                 1194
+urg200                  MACH_URG200             URG200                  1195
+cpux255lcdnet           MACH_CPUX255LCDNET      CPUX255LCDNET           1196
+netdcu9                 MACH_NETDCU9            NETDCU9                 1197
+netdcu10                MACH_NETDCU10           NETDCU10                1198
+dspg_dga                MACH_DSPG_DGA           DSPG_DGA                1199
+dspg_dvw                MACH_DSPG_DVW           DSPG_DVW                1200
+solos                   MACH_SOLOS              SOLOS                   1201
+at91sam9263ek           MACH_AT91SAM9263EK      AT91SAM9263EK           1202
+osstbox                 MACH_OSSTBOX            OSSTBOX                 1203
+kbat9261                MACH_KBAT9261           KBAT9261                1204
+ct1100                  MACH_CT1100             CT1100                  1205
+akcppxa                 MACH_AKCPPXA            AKCPPXA                 1206
+zevio_1020              MACH_ZEVIO_1020         ZEVIO_1020              1207
+hitrack                 MACH_HITRACK            HITRACK                 1208
+syme1                   MACH_SYME1              SYME1                   1209
+syhl1                   MACH_SYHL1              SYHL1                   1210
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 9e3e2a69c03a..fd5475071acc 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -80,12 +80,38 @@ static int amba_resume(struct device *dev)
        return ret;
 }
+#define amba_attr_func(name,fmt,arg...)                                 \
+static ssize_t name##_show(struct device *_dev,                         \
+                           struct device_attribute *attr, char *buf)    \
+{                                                                       \
+        struct amba_device *dev = to_amba_device(_dev);                 \
+        return sprintf(buf, fmt, arg);                                  \
+}
+#define amba_attr(name,fmt,arg...)      \
+amba_attr_func(name,fmt,arg)            \
+static DEVICE_ATTR(name, S_IRUGO, name##_show, NULL)
+amba_attr_func(id, "%08x\n", dev->periphid);
+amba_attr(irq0, "%u\n", dev->irq[0]);
+amba_attr(irq1, "%u\n", dev->irq[1]);
+amba_attr_func(resource, "\t%016llx\t%016llx\t%016lx\n",
+         (unsigned long long)dev->res.start, (unsigned long long)dev->res.end,
+         dev->res.flags);
+static struct device_attribute amba_dev_attrs[] = {
+        __ATTR_RO(id),
+        __ATTR_RO(resource),
+        __ATTR_NULL,
+};
 /*
 * Primecells are part of the Advanced Microcontroller Bus Architecture,
 * so we call the bus "amba".
 */
 static struct bus_type amba_bustype = {
        .name           = "amba",
+        .dev_attrs      = amba_dev_attrs,
        .match          = amba_match,
        .uevent         = amba_uevent,
        .suspend        = amba_suspend,
@@ -169,21 +195,6 @@ static void amba_device_release(struct device *dev)
        kfree(d);
 }
-#define amba_attr(name,fmt,arg...)                              \
-static ssize_t show_##name(struct device *_dev, struct device_attribute *attr, char *buf)       \
-{                                                               \
-        struct amba_device *dev = to_amba_device(_dev);         \
-        return sprintf(buf, fmt, arg);                          \
-}                                                               \
-static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
-amba_attr(id, "%08x\n", dev->periphid);
-amba_attr(irq0, "%u\n", dev->irq[0]);
-amba_attr(irq1, "%u\n", dev->irq[1]);
-amba_attr(resource, "\t%016llx\t%016llx\t%016lx\n",
-         (unsigned long long)dev->res.start, (unsigned long long)dev->res.end,
-         dev->res.flags);
 /**
 *      amba_device_register - register an AMBA device
 *      @dev: AMBA device to register
@@ -208,40 +219,46 @@ int amba_device_register(struct amba_device *dev, struct resource *parent)
                dev_warn(&dev->dev, "coherent dma mask is unset\n");
        ret = request_resource(parent, &dev->res);
-        if (ret == 0) {
+        if (ret)
-                tmp = ioremap(dev->res.start, SZ_4K);
+                goto err_out;
-                if (!tmp) {
-                        ret = -ENOMEM;
+        tmp = ioremap(dev->res.start, SZ_4K);
-                        goto out;
+        if (!tmp) {
-                }
+                ret = -ENOMEM;
+                goto err_release;
-                for (pid = 0, i = 0; i < 4; i++)
-                        pid |= (readl(tmp + 0xfe0 + 4 * i) & 255) << (i * 8);
-                for (cid = 0, i = 0; i < 4; i++)
-                        cid |= (readl(tmp + 0xff0 + 4 * i) & 255) << (i * 8);
-                iounmap(tmp);
-                if (cid == 0xb105f00d)
-                        dev->periphid = pid;
-                if (dev->periphid)
-                        ret = device_register(&dev->dev);
-                else
-                        ret = -ENODEV;
-                if (ret == 0) {
-                        device_create_file(&dev->dev, &dev_attr_id);
-                        if (dev->irq[0] != NO_IRQ)
-                                device_create_file(&dev->dev, &dev_attr_irq0);
-                        if (dev->irq[1] != NO_IRQ)
-                                device_create_file(&dev->dev, &dev_attr_irq1);
-                        device_create_file(&dev->dev, &dev_attr_resource);
-                } else {
- out:
-                        release_resource(&dev->res);
-                }
        }
+        for (pid = 0, i = 0; i < 4; i++)
+                pid |= (readl(tmp + 0xfe0 + 4 * i) & 255) << (i * 8);
+        for (cid = 0, i = 0; i < 4; i++)
+                cid |= (readl(tmp + 0xff0 + 4 * i) & 255) << (i * 8);
+        iounmap(tmp);
+        if (cid == 0xb105f00d)
+                dev->periphid = pid;
+        if (!dev->periphid) {
+                ret = -ENODEV;
+                goto err_release;
+        }
+        ret = device_register(&dev->dev);
+        if (ret)
+                goto err_release;
+        if (dev->irq[0] != NO_IRQ)
+                ret = device_create_file(&dev->dev, &dev_attr_irq0);
+        if (ret == 0 && dev->irq[1] != NO_IRQ)
+                ret = device_create_file(&dev->dev, &dev_attr_irq1);
+        if (ret == 0)
+                return ret;
+        device_unregister(&dev->dev);
+ err_release:
+        release_resource(&dev->res);
+ err_out:
        return ret;
 }
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 510816c16da3..5cbf8b9d5141 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -195,11 +195,11 @@ config I2C_IBM_IIC
          will be called i2c-ibm_iic.
 config I2C_IOP3XX
-        tristate "Intel IOP3xx and IXP4xx on-chip I2C interface"
+        tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface"
-        depends on (ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX) && I2C
+        depends on (ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX) && I2C
        help
          Say Y here if you want to use the IIC bus controller on
-          the Intel IOP3xx I/O Processors or IXP4xx Network Processors.
+          the Intel IOPx3xx I/O Processors or IXP4xx Network Processors.
          This driver can also be built as a module.  If so, the module
          will be called i2c-iop3xx.
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index c95a6c154165..c3b1567c852a 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -358,133 +358,6 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
 #ifdef CONFIG_I2C_PXA_SLAVE
 /*
- * I2C EEPROM emulation.
- */
-static struct i2c_eeprom_emu eeprom = {
-        .size = I2C_EEPROM_EMU_SIZE,
-        .watch = LIST_HEAD_INIT(eeprom.watch),
-};
-struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void)
-{
-        return &eeprom;
-}
-int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *emu, void *data,
-                              unsigned int addr, unsigned int size,
-                              struct i2c_eeprom_emu_watcher *watcher)
-{
-        struct i2c_eeprom_emu_watch *watch;
-        unsigned long flags;
-        if (addr + size > emu->size)
-                return -EINVAL;
-        watch = kmalloc(sizeof(struct i2c_eeprom_emu_watch), GFP_KERNEL);
-        if (watch) {
-                watch->start = addr;
-                watch->end = addr + size - 1;
-                watch->ops = watcher;
-                watch->data = data;
-                local_irq_save(flags);
-                list_add(&watch->node, &emu->watch);
-                local_irq_restore(flags);
-        }
-        return watch ? 0 : -ENOMEM;
-}
-void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *emu, void *data,
-                               struct i2c_eeprom_emu_watcher *watcher)
-{
-        struct i2c_eeprom_emu_watch *watch, *n;
-        unsigned long flags;
-        list_for_each_entry_safe(watch, n, &emu->watch, node) {
-                if (watch->ops == watcher && watch->data == data) {
-                        local_irq_save(flags);
-                        list_del(&watch->node);
-                        local_irq_restore(flags);
-                        kfree(watch);
-                }
-        }
-}
-static void i2c_eeprom_emu_event(void *ptr, i2c_slave_event_t event)
-{
-        struct i2c_eeprom_emu *emu = ptr;
-        eedbg(3, "i2c_eeprom_emu_event: %d\n", event);
-        switch (event) {
-        case I2C_SLAVE_EVENT_START_WRITE:
-                emu->seen_start = 1;
-                eedbg(2, "i2c_eeprom: write initiated\n");
-                break;
-        case I2C_SLAVE_EVENT_START_READ:
-                emu->seen_start = 0;
-                eedbg(2, "i2c_eeprom: read initiated\n");
-                break;
-        case I2C_SLAVE_EVENT_STOP:
-                emu->seen_start = 0;
-                eedbg(2, "i2c_eeprom: received stop\n");
-                break;
-        default:
-                eedbg(0, "i2c_eeprom: unhandled event\n");
-                break;
-        }
-}
-static int i2c_eeprom_emu_read(void *ptr)
-{
-        struct i2c_eeprom_emu *emu = ptr;
-        int ret;
-        ret = emu->bytes[emu->ptr];
-        emu->ptr = (emu->ptr + 1) % emu->size;
-        return ret;
-}
-static void i2c_eeprom_emu_write(void *ptr, unsigned int val)
-{
-        struct i2c_eeprom_emu *emu = ptr;
-        struct i2c_eeprom_emu_watch *watch;
-        if (emu->seen_start != 0) {
-                eedbg(2, "i2c_eeprom_emu_write: setting ptr %02x\n", val);
-                emu->ptr = val;
-                emu->seen_start = 0;
-                return;
-        }
-        emu->bytes[emu->ptr] = val;
-        eedbg(1, "i2c_eeprom_emu_write: ptr=0x%02x, val=0x%02x\n",
-              emu->ptr, val);
-        list_for_each_entry(watch, &emu->watch, node) {
-                if (!watch->ops || !watch->ops->write)
-                        continue;
-                if (watch->start <= emu->ptr && watch->end >= emu->ptr)
-                        watch->ops->write(watch->data, emu->ptr, val);
-        }
-        emu->ptr = (emu->ptr + 1) % emu->size;
-}
-struct i2c_slave_client eeprom_client = {
-        .data   = &eeprom,
-        .event  = i2c_eeprom_emu_event,
-        .read   = i2c_eeprom_emu_read,
-        .write  = i2c_eeprom_emu_write
-};
-/*
 * PXA I2C Slave mode
 */
@@ -963,11 +836,9 @@ static int i2c_pxa_probe(struct platform_device *dev)
        i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
 #ifdef CONFIG_I2C_PXA_SLAVE
-        i2c->slave = &eeprom_client;
        if (plat) {
                i2c->slave_addr = plat->slave_addr;
-                if (plat->slave)
+                i2c->slave = plat->slave;
-                        i2c->slave = plat->slave;
        }
 #endif
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
index 24b51cccde8f..9eceb4148922 100644
--- a/include/asm-arm/arch-aaec2000/memory.h
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -17,8 +17,6 @@
 #define __virt_to_bus(x)        __virt_to_phys(x)
 #define __bus_to_virt(x)        __phys_to_virt(x)
-#ifdef CONFIG_DISCONTIGMEM
 /*
 * The nodes are the followings:
 *
@@ -27,42 +25,6 @@
 *   node 2: 0xf800.0000 - 0xfbff.ffff
 *   node 3: 0xfc00.0000 - 0xffff.ffff
 */
+#define NODE_MEM_SIZE_BITS      26
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) \
-        (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn) \
-        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and return the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-/*
- * Given a page frame number, find the owning node of the memory
- * and return the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-/*
- *  Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- *  and returns the index corresponding to the appropriate page in the
- *  node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
-#define NODE_MAX_MEM_SHIFT      26
-#define NODE_MAX_MEM_SIZE       (1 << NODE_MAX_MEM_SHIFT)
-#endif /* CONFIG_DISCONTIGMEM */
 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
index c6e8dcf674de..42768cc8bfb4 100644
--- a/include/asm-arm/arch-clps711x/memory.h
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -62,7 +62,15 @@
 * memory bank.  For those systems, simply undefine CONFIG_DISCONTIGMEM.
 */
-#ifdef CONFIG_DISCONTIGMEM
+/*
+ * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
+ * uses only one of the two banks (bank #1).  However, even within
+ * bank #1, memory is discontiguous.
+ *
+ * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
+ * them, so we use 24 for the node max shift to get 16MB node sizes.
+ */
 /*
 * Because of the wide memory address space between physical RAM banks on the 
 * SA1100, it's much more convenient to use Linux's NUMA support to implement
@@ -80,48 +88,7 @@
 *      node 2:  0xd0000000 - 0xd7ffffff
 *      node 3:  0xd8000000 - 0xdfffffff
 */
+#define NODE_MEM_SIZE_BITS      24
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) \
-                (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn) \
-        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr) \
-                        NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-/*
- * Given a kaddr, LOCAL_MAR_NR finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
-/*
- * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
- * uses only one of the two banks (bank #1).  However, even within
- * bank #1, memory is discontiguous.
- *
- * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
- * them, so we use 24 for the node max shift to get 16MB node sizes.
- */
-#define NODE_MAX_MEM_SHIFT      24
-#define NODE_MAX_MEM_SIZE       (1<<NODE_MAX_MEM_SHIFT)
-#endif /* CONFIG_DISCONTIGMEM */
 #endif
diff --git a/include/asm-arm/arch-imx/timex.h b/include/asm-arm/arch-imx/timex.h
index 8c91674706b1..e22ba789546c 100644
--- a/include/asm-arm/arch-imx/timex.h
+++ b/include/asm-arm/arch-imx/timex.h
@@ -21,7 +21,6 @@
 #ifndef __ASM_ARCH_TIMEX_H
 #define __ASM_ARCH_TIMEX_H
-#include <asm/hardware.h>
+#define CLOCK_TICK_RATE         (16000000)
-#define CLOCK_TICK_RATE         (CLK32)
 #endif
diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S
new file mode 100644
index 000000000000..788b4e386c16
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/debug-macro.S
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-iop13xx/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+        .macro  addruart, rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                 @ mmu enabled?
+        moveq   \rx, #0xff000000        @ physical
+        orreq   \rx, \rx, #0x00d80000
+        movne   \rx, #0xfe000000        @ virtual
+        orrne   \rx, \rx, #0x00e80000
+        orr     \rx, \rx, #0x00002300
+        orr     \rx, \rx, #0x00000040
+        .endm
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
new file mode 100644
index 000000000000..2e15da53ff79
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -0,0 +1,3 @@
+#ifndef _IOP13XX_DMA_H
+#define _IOP13XX_DMA_H_
+#endif
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S
new file mode 100644
index 000000000000..94c50283dc56
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * iop13xx low level irq macros
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+        .macro  disable_fiq
+        .endm
+        /*
+         * Note: a 1-cycle window exists where iintvec will return the value
+         * of iintbase, so we explicitly check for "bad zeros"
+         */
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        mrc     p15, 0, \tmp, c15, c1, 0
+        orr     \tmp, \tmp, #(1 << 6)
+        mcr     p15, 0, \tmp, c15, c1, 0        @ Enable cp6 access
+        mrc     p6, 0, \irqnr, c3, c2, 0        @ Read IINTVEC
+        cmp     \irqnr, #0
+        mrceq   p6, 0, \irqnr, c3, c2, 0        @ Re-read on potentially bad zero
+        adds    \irqstat, \irqnr, #1            @ Check for 0xffffffff
+        movne   \irqnr, \irqnr, lsr #2          @ Convert to irqnr
+        biceq   \tmp, \tmp, #(1 << 6)
+        mcreq   p15, 0, \tmp, c15, c1, 0        @ Disable cp6 access if no more interrupts
+        .endm
diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/include/asm-arm/arch-iop13xx/hardware.h
new file mode 100644
index 000000000000..8e1d56289846
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/hardware.h
@@ -0,0 +1,28 @@
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include <asm/types.h>
+#define pcibios_assign_all_busses() 1
+#ifndef __ASSEMBLY__
+extern unsigned long iop13xx_pcibios_min_io;
+extern unsigned long iop13xx_pcibios_min_mem;
+extern u16 iop13xx_dev_id(void);
+extern void iop13xx_set_atu_mmr_bases(void);
+#endif
+#define PCIBIOS_MIN_IO      (iop13xx_pcibios_min_io)
+#define PCIBIOS_MIN_MEM     (iop13xx_pcibios_min_mem)
+/*
+ * Generic chipset bits
+ *
+ */
+#include "iop13xx.h"
+/*
+ * Board specific bits
+ */
+#include "iq81340.h"
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h
new file mode 100644
index 000000000000..db6de2480a24
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/io.h
@@ -0,0 +1,41 @@
+/*
+ * iop13xx custom ioremap implementation
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+#define IO_SPACE_LIMIT 0xffffffff
+#define __io(a)      (a)
+#define __mem_pci(a) (a)
+#define __mem_isa(a) (a)
+extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
+extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
+        unsigned long flags);
+extern void __iop13xx_iounmap(void __iomem *addr);
+extern u32 iop13xx_atue_mem_base;
+extern u32 iop13xx_atux_mem_base;
+extern size_t iop13xx_atue_mem_size;
+extern size_t iop13xx_atux_mem_size;
+#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
+#define __arch_iounmap(a)        __iop13xx_iounmap(a)
+#endif
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
new file mode 100644
index 000000000000..a88522a0ff8e
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -0,0 +1,492 @@
+#ifndef _IOP13XX_HW_H_
+#define _IOP13XX_HW_H_
+#ifndef __ASSEMBLY__
+/* The ATU offsets can change based on the strapping */
+extern u32 iop13xx_atux_pmmr_offset;
+extern u32 iop13xx_atue_pmmr_offset;
+void iop13xx_init_irq(void);
+void iop13xx_map_io(void);
+void iop13xx_platform_init(void);
+void iop13xx_init_irq(void);
+void iop13xx_init_time(unsigned long tickrate);
+unsigned long iop13xx_gettimeoffset(void);
+/* handle cp6 access
+ * to do: handle access in entry-armv5.S and unify with
+ * the iop3xx implementation
+ * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
+ * when interrupts are enabled
+ */
+static inline unsigned long iop13xx_cp6_save(void)
+{
+        u32 temp, cp_flags;
+        asm volatile (
+                "mrc    p15, 0, %1, c15, c1, 0\n\t"
+                "orr    %0, %1, #(1 << 6)\n\t"
+                "mcr    p15, 0, %0, c15, c1, 0\n\t"
+                : "=r" (temp), "=r"(cp_flags));
+        return cp_flags;
+}
+static inline void iop13xx_cp6_restore(unsigned long cp_flags)
+{
+        asm volatile (
+                "mcr    p15, 0, %0, c15, c1, 0\n\t"
+                : : "r" (cp_flags) );
+}
+/* CPUID CP6 R0 Page 0 */
+static inline int iop13xx_cpu_id(void)
+{
+        int id;
+        asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
+        return id;
+}
+#endif
+/*
+ * IOP13XX I/O and Mem space regions for PCI autoconfiguration
+ */
+#define IOP13XX_MAX_RAM_SIZE    0x80000000UL  /* 2GB */
+#define IOP13XX_PCI_OFFSET       IOP13XX_MAX_RAM_SIZE
+/* PCI MAP
+ * 0x0000.0000 - 0x8000.0000           1:1 mapping with Physical RAM
+ * 0x8000.0000 - 0x8800.0000           PCIX/PCIE memory window (128MB)
+*/
+#define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
+#define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
+#define IOP13XX_PCIX_LOWER_IO_VA      0xfec60000UL
+#define IOP13XX_PCIX_LOWER_IO_BA      0x0fff0000UL
+#define IOP13XX_PCIX_UPPER_IO_PA      (IOP13XX_PCIX_LOWER_IO_PA +\
+                                       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_UPPER_IO_VA      (IOP13XX_PCIX_LOWER_IO_VA +\
+                                       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_IO_OFFSET        (IOP13XX_PCIX_LOWER_IO_VA -\
+                                       IOP13XX_PCIX_LOWER_IO_BA)
+#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
+                                           (IOP13XX_PCIX_LOWER_IO_PA\
+                                           - IOP13XX_PCIX_LOWER_IO_VA))
+#define IOP13XX_PCIX_MEM_PHYS_OFFSET  0x100000000ULL
+#define IOP13XX_PCIX_MEM_WINDOW_SIZE  0x3a000000UL
+#define IOP13XX_PCIX_LOWER_MEM_BA     (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
+#define IOP13XX_PCIX_LOWER_MEM_PA     (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
+                                       IOP13XX_PCIX_LOWER_MEM_BA)
+#define IOP13XX_PCIX_UPPER_MEM_PA     (IOP13XX_PCIX_LOWER_MEM_PA +\
+                                       IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_UPPER_MEM_BA     (IOP13XX_PCIX_LOWER_MEM_BA +\
+                                       IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_MEM_COOKIE        0x80000000UL
+#define IOP13XX_PCIX_LOWER_MEM_RA      IOP13XX_PCIX_MEM_COOKIE
+#define IOP13XX_PCIX_UPPER_MEM_RA      (IOP13XX_PCIX_LOWER_MEM_RA +\
+                                        IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIX_MEM_OFFSET        (IOP13XX_PCIX_MEM_COOKIE -\
+                                        IOP13XX_PCIX_LOWER_MEM_BA)
+/* PCI-E ranges */
+#define IOP13XX_PCIE_IO_WINDOW_SIZE      0x10000UL
+#define IOP13XX_PCIE_LOWER_IO_PA         0xfffd0000UL
+#define IOP13XX_PCIE_LOWER_IO_VA         0xfed70000UL
+#define IOP13XX_PCIE_LOWER_IO_BA         0x0fff0000UL
+#define IOP13XX_PCIE_UPPER_IO_PA         (IOP13XX_PCIE_LOWER_IO_PA +\
+                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_UPPER_IO_VA         (IOP13XX_PCIE_LOWER_IO_VA +\
+                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_UPPER_IO_BA         (IOP13XX_PCIE_LOWER_IO_BA +\
+                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_IO_OFFSET           (IOP13XX_PCIE_LOWER_IO_VA -\
+                                         IOP13XX_PCIE_LOWER_IO_BA)
+#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
+                                           (IOP13XX_PCIE_LOWER_IO_PA\
+                                           - IOP13XX_PCIE_LOWER_IO_VA))
+#define IOP13XX_PCIE_MEM_PHYS_OFFSET     0x200000000ULL
+#define IOP13XX_PCIE_MEM_WINDOW_SIZE     0x3a000000UL
+#define IOP13XX_PCIE_LOWER_MEM_BA        (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
+#define IOP13XX_PCIE_LOWER_MEM_PA        (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
+                                         IOP13XX_PCIE_LOWER_MEM_BA)
+#define IOP13XX_PCIE_UPPER_MEM_PA        (IOP13XX_PCIE_LOWER_MEM_PA +\
+                                         IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_UPPER_MEM_BA        (IOP13XX_PCIE_LOWER_MEM_BA +\
+                                         IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
+/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
+#define IOP13XX_PCIE_MEM_COOKIE          0xc0000000UL
+#define IOP13XX_PCIE_LOWER_MEM_RA        IOP13XX_PCIE_MEM_COOKIE
+#define IOP13XX_PCIE_UPPER_MEM_RA        (IOP13XX_PCIE_LOWER_MEM_RA +\
+                                         IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PCIE_MEM_OFFSET          (IOP13XX_PCIE_MEM_COOKIE -\
+                                         IOP13XX_PCIE_LOWER_MEM_BA)
+/* PBI Ranges */
+#define IOP13XX_PBI_LOWER_MEM_PA          0xf0000000UL
+#define IOP13XX_PBI_MEM_WINDOW_SIZE       0x04000000UL
+#define IOP13XX_PBI_MEM_COOKIE            0xfa000000UL
+#define IOP13XX_PBI_LOWER_MEM_RA          IOP13XX_PBI_MEM_COOKIE
+#define IOP13XX_PBI_UPPER_MEM_RA          (IOP13XX_PBI_LOWER_MEM_RA +\
+                                          IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
+/*
+ * IOP13XX chipset registers
+ */
+#define IOP13XX_PMMR_PHYS_MEM_BASE         0xffd80000UL  /* PMMR phys. address */
+#define IOP13XX_PMMR_VIRT_MEM_BASE         0xfee80000UL  /* PMMR phys. address */
+#define IOP13XX_PMMR_MEM_WINDOW_SIZE       0x80000
+#define IOP13XX_PMMR_UPPER_MEM_VA          (IOP13XX_PMMR_VIRT_MEM_BASE +\
+                                           IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PMMR_UPPER_MEM_PA          (IOP13XX_PMMR_PHYS_MEM_BASE +\
+                                           IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
+#define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (u32) ((u32) addr +\
+                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
+                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
+#define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (u32) ((u32) addr -\
+                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
+                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
+#define IOP13XX_REG_ADDR32(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR16(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR8(reg)             (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR32_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR16_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
+#define IOP13XX_REG_ADDR8_PHYS(reg)       (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
+#define IOP13XX_PMMR_SIZE                  0x00080000
+/*=================== Defines for Platform Devices =====================*/
+#define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
+#define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
+#define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
+#define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
+#define IOP13XX_I2C0_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
+#define IOP13XX_I2C1_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
+#define IOP13XX_I2C2_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
+#define IOP13XX_I2C0_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
+#define IOP13XX_I2C1_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
+#define IOP13XX_I2C2_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
+/* ATU selection flags */
+/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
+#define IOP13XX_INIT_ATU_DEFAULT     (0)
+#define IOP13XX_INIT_ATU_ATUX         (1 << 0)
+#define IOP13XX_INIT_ATU_ATUE         (1 << 1)
+#define IOP13XX_INIT_ATU_NONE         (1 << 2)
+/* UART selection flags */
+/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
+#define IOP13XX_INIT_UART_DEFAULT    (0)
+#define IOP13XX_INIT_UART_0           (1 << 0)
+#define IOP13XX_INIT_UART_1           (1 << 1)
+/* I2C selection flags */
+/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
+#define IOP13XX_INIT_I2C_DEFAULT     (0)
+#define IOP13XX_INIT_I2C_0            (1 << 0)
+#define IOP13XX_INIT_I2C_1            (1 << 1)
+#define IOP13XX_INIT_I2C_2            (1 << 2)
+#define IQ81340_NUM_UART     2
+#define IQ81340_NUM_I2C      3
+#define IQ81340_NUM_PHYS_MAP_FLASH 1
+#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
+                                IQ81340_NUM_I2C +\
+                                IQ81340_NUM_PHYS_MAP_FLASH)
+/*========================== PMMR offsets for key registers ============*/
+#define IOP13XX_ATU0_PMMR_OFFSET        0x00048000
+#define IOP13XX_ATU1_PMMR_OFFSET        0x0004c000
+#define IOP13XX_ATU2_PMMR_OFFSET        0x0004d000
+#define IOP13XX_ADMA0_PMMR_OFFSET       0x00000000
+#define IOP13XX_ADMA1_PMMR_OFFSET       0x00000200
+#define IOP13XX_ADMA2_PMMR_OFFSET       0x00000400
+#define IOP13XX_PBI_PMMR_OFFSET         0x00001580
+#define IOP13XX_ESSR0_PMMR_OFFSET       0x00002188
+#define IOP13XX_ESSR0                   IOP13XX_REG_ADDR32(0x00002188)
+#define IOP13XX_ESSR0_IFACE_MASK        0x00004000  /* Interface PCI-X / PCI-E */
+#define IOP13XX_CONTROLLER_ONLY         (1 << 14)
+#define IOP13XX_INTERFACE_SEL_PCIX      (1 << 15)
+#define IOP13XX_PMON_PMMR_OFFSET        0x0001A000
+#define IOP13XX_PMON_BASE               (IOP13XX_PMMR_VIRT_MEM_BASE +\
+                                        IOP13XX_PMON_PMMR_OFFSET)
+#define IOP13XX_PMON_PHYSBASE           (IOP13XX_PMMR_PHYS_MEM_BASE +\
+                                        IOP13XX_PMON_PMMR_OFFSET)
+#define IOP13XX_PMON_CMD0               (IOP13XX_PMON_BASE + 0x0)
+#define IOP13XX_PMON_EVR0               (IOP13XX_PMON_BASE + 0x4)
+#define IOP13XX_PMON_STS0               (IOP13XX_PMON_BASE + 0x8)
+#define IOP13XX_PMON_DATA0              (IOP13XX_PMON_BASE + 0xC)
+#define IOP13XX_PMON_CMD3               (IOP13XX_PMON_BASE + 0x30)
+#define IOP13XX_PMON_EVR3               (IOP13XX_PMON_BASE + 0x34)
+#define IOP13XX_PMON_STS3               (IOP13XX_PMON_BASE + 0x38)
+#define IOP13XX_PMON_DATA3              (IOP13XX_PMON_BASE + 0x3C)
+#define IOP13XX_PMON_CMD7               (IOP13XX_PMON_BASE + 0x70)
+#define IOP13XX_PMON_EVR7               (IOP13XX_PMON_BASE + 0x74)
+#define IOP13XX_PMON_STS7               (IOP13XX_PMON_BASE + 0x78)
+#define IOP13XX_PMON_DATA7              (IOP13XX_PMON_BASE + 0x7C)
+#define IOP13XX_PMONEN                  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
+#define IOP13XX_PMONSTAT                (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
+/*================================ATU===================================*/
+#define IOP13XX_ATUX_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
+                                        iop13xx_atux_pmmr_offset + (ofs))
+#define IOP13XX_ATUX_DID                IOP13XX_REG_ADDR16(\
+                                        iop13xx_atux_pmmr_offset + 0x2)
+#define IOP13XX_ATUX_ATUCMD             IOP13XX_REG_ADDR16(\
+                                        iop13xx_atux_pmmr_offset + 0x4)
+#define IOP13XX_ATUX_ATUSR              IOP13XX_REG_ADDR16(\
+                                        iop13xx_atux_pmmr_offset + 0x6)
+#define IOP13XX_ATUX_IABAR0             IOP13XX_ATUX_OFFSET(0x10)
+#define IOP13XX_ATUX_IAUBAR0            IOP13XX_ATUX_OFFSET(0x14)
+#define IOP13XX_ATUX_IABAR1             IOP13XX_ATUX_OFFSET(0x18)
+#define IOP13XX_ATUX_IAUBAR1            IOP13XX_ATUX_OFFSET(0x1c)
+#define IOP13XX_ATUX_IABAR2             IOP13XX_ATUX_OFFSET(0x20)
+#define IOP13XX_ATUX_IAUBAR2            IOP13XX_ATUX_OFFSET(0x24)
+#define IOP13XX_ATUX_IALR0              IOP13XX_ATUX_OFFSET(0x40)
+#define IOP13XX_ATUX_IATVR0             IOP13XX_ATUX_OFFSET(0x44)
+#define IOP13XX_ATUX_IAUTVR0            IOP13XX_ATUX_OFFSET(0x48)
+#define IOP13XX_ATUX_IALR1              IOP13XX_ATUX_OFFSET(0x4c)
+#define IOP13XX_ATUX_IATVR1             IOP13XX_ATUX_OFFSET(0x50)
+#define IOP13XX_ATUX_IAUTVR1            IOP13XX_ATUX_OFFSET(0x54)
+#define IOP13XX_ATUX_IALR2              IOP13XX_ATUX_OFFSET(0x58)
+#define IOP13XX_ATUX_IATVR2             IOP13XX_ATUX_OFFSET(0x5c)
+#define IOP13XX_ATUX_IAUTVR2            IOP13XX_ATUX_OFFSET(0x60)
+#define IOP13XX_ATUX_ATUCR              IOP13XX_ATUX_OFFSET(0x70)
+#define IOP13XX_ATUX_PCSR               IOP13XX_ATUX_OFFSET(0x74)
+#define IOP13XX_ATUX_ATUISR             IOP13XX_ATUX_OFFSET(0x78)
+#define IOP13XX_ATUX_PCIXSR             IOP13XX_ATUX_OFFSET(0xD4)
+#define IOP13XX_ATUX_IABAR3             IOP13XX_ATUX_OFFSET(0x200)
+#define IOP13XX_ATUX_IAUBAR3            IOP13XX_ATUX_OFFSET(0x204)
+#define IOP13XX_ATUX_IALR3              IOP13XX_ATUX_OFFSET(0x208)
+#define IOP13XX_ATUX_IATVR3             IOP13XX_ATUX_OFFSET(0x20c)
+#define IOP13XX_ATUX_IAUTVR3            IOP13XX_ATUX_OFFSET(0x210)
+#define IOP13XX_ATUX_OIOBAR             IOP13XX_ATUX_OFFSET(0x300)
+#define IOP13XX_ATUX_OIOWTVR            IOP13XX_ATUX_OFFSET(0x304)
+#define IOP13XX_ATUX_OUMBAR0            IOP13XX_ATUX_OFFSET(0x308)
+#define IOP13XX_ATUX_OUMWTVR0           IOP13XX_ATUX_OFFSET(0x30c)
+#define IOP13XX_ATUX_OUMBAR1            IOP13XX_ATUX_OFFSET(0x310)
+#define IOP13XX_ATUX_OUMWTVR1           IOP13XX_ATUX_OFFSET(0x314)
+#define IOP13XX_ATUX_OUMBAR2            IOP13XX_ATUX_OFFSET(0x318)
+#define IOP13XX_ATUX_OUMWTVR2           IOP13XX_ATUX_OFFSET(0x31c)
+#define IOP13XX_ATUX_OUMBAR3            IOP13XX_ATUX_OFFSET(0x320)
+#define IOP13XX_ATUX_OUMWTVR3           IOP13XX_ATUX_OFFSET(0x324)
+#define IOP13XX_ATUX_OUDMABAR           IOP13XX_ATUX_OFFSET(0x328)
+#define IOP13XX_ATUX_OUMSIBAR           IOP13XX_ATUX_OFFSET(0x32c)
+#define IOP13XX_ATUX_OCCAR              IOP13XX_ATUX_OFFSET(0x330)
+#define IOP13XX_ATUX_OCCDR              IOP13XX_ATUX_OFFSET(0x334)
+#define IOP13XX_ATUX_ATUCR_OUT_EN               (1 << 1)
+#define IOP13XX_ATUX_PCSR_CENTRAL_RES           (1 << 25)
+#define IOP13XX_ATUX_PCSR_P_RSTOUT              (1 << 21)
+#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY            (1 << 15)
+#define IOP13XX_ATUX_PCSR_IN_Q_BUSY             (1 << 14)
+#define IOP13XX_ATUX_PCSR_FREQ_OFFSET           (16)
+#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
+#define IOP13XX_ATUX_STAT_VPD_ADDR              (1 << 17)
+#define IOP13XX_ATUX_STAT_INT_PAR_ERR           (1 << 16)
+#define IOP13XX_ATUX_STAT_CFG_WRITE             (1 << 15)
+#define IOP13XX_ATUX_STAT_ERR_COR               (1 << 14)
+#define IOP13XX_ATUX_STAT_TX_SCEM               (1 << 13)
+#define IOP13XX_ATUX_STAT_REC_SCEM              (1 << 12)
+#define IOP13XX_ATUX_STAT_POWER_TRAN            (1 << 11)
+#define IOP13XX_ATUX_STAT_TX_SERR               (1 << 10)
+#define IOP13XX_ATUX_STAT_DET_PAR_ERR           (1 << 9 )
+#define IOP13XX_ATUX_STAT_BIST                  (1 << 8 )
+#define IOP13XX_ATUX_STAT_INT_REC_MABORT        (1 << 7 )
+#define IOP13XX_ATUX_STAT_REC_SERR              (1 << 4 )
+#define IOP13XX_ATUX_STAT_EXT_REC_MABORT        (1 << 3 )
+#define IOP13XX_ATUX_STAT_EXT_REC_TABORT        (1 << 2 )
+#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT        (1 << 1 )
+#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR       (1 << 0 )
+#define IOP13XX_ATUX_PCIXSR_BUS_NUM     (8)
+#define IOP13XX_ATUX_PCIXSR_DEV_NUM     (3)
+#define IOP13XX_ATUX_PCIXSR_FUNC_NUM    (0)
+#define IOP13XX_ATUX_IALR_DISABLE       0x00000001
+#define IOP13XX_ATUX_OUMBAR_ENABLE      0x80000000
+#define IOP13XX_ATUE_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
+                                        iop13xx_atue_pmmr_offset + (ofs))
+#define IOP13XX_ATUE_DID                IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0x2)
+#define IOP13XX_ATUE_ATUCMD             IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0x4)
+#define IOP13XX_ATUE_ATUSR              IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0x6)
+#define IOP13XX_ATUE_IABAR0             IOP13XX_ATUE_OFFSET(0x10)
+#define IOP13XX_ATUE_IAUBAR0            IOP13XX_ATUE_OFFSET(0x14)
+#define IOP13XX_ATUE_IABAR1             IOP13XX_ATUE_OFFSET(0x18)
+#define IOP13XX_ATUE_IAUBAR1            IOP13XX_ATUE_OFFSET(0x1c)
+#define IOP13XX_ATUE_IABAR2             IOP13XX_ATUE_OFFSET(0x20)
+#define IOP13XX_ATUE_IAUBAR2            IOP13XX_ATUE_OFFSET(0x24)
+#define IOP13XX_ATUE_IALR0              IOP13XX_ATUE_OFFSET(0x40)
+#define IOP13XX_ATUE_IATVR0             IOP13XX_ATUE_OFFSET(0x44)
+#define IOP13XX_ATUE_IAUTVR0            IOP13XX_ATUE_OFFSET(0x48)
+#define IOP13XX_ATUE_IALR1              IOP13XX_ATUE_OFFSET(0x4c)
+#define IOP13XX_ATUE_IATVR1             IOP13XX_ATUE_OFFSET(0x50)
+#define IOP13XX_ATUE_IAUTVR1            IOP13XX_ATUE_OFFSET(0x54)
+#define IOP13XX_ATUE_IALR2              IOP13XX_ATUE_OFFSET(0x58)
+#define IOP13XX_ATUE_IATVR2             IOP13XX_ATUE_OFFSET(0x5c)
+#define IOP13XX_ATUE_IAUTVR2            IOP13XX_ATUE_OFFSET(0x60)
+#define IOP13XX_ATUE_PE_LSTS            IOP13XX_REG_ADDR16(\
+                                        iop13xx_atue_pmmr_offset + 0xe2)
+#define IOP13XX_ATUE_OIOWTVR            IOP13XX_ATUE_OFFSET(0x304)
+#define IOP13XX_ATUE_OUMBAR0            IOP13XX_ATUE_OFFSET(0x308)
+#define IOP13XX_ATUE_OUMWTVR0           IOP13XX_ATUE_OFFSET(0x30c)
+#define IOP13XX_ATUE_OUMBAR1            IOP13XX_ATUE_OFFSET(0x310)
+#define IOP13XX_ATUE_OUMWTVR1           IOP13XX_ATUE_OFFSET(0x314)
+#define IOP13XX_ATUE_OUMBAR2            IOP13XX_ATUE_OFFSET(0x318)
+#define IOP13XX_ATUE_OUMWTVR2           IOP13XX_ATUE_OFFSET(0x31c)
+#define IOP13XX_ATUE_OUMBAR3            IOP13XX_ATUE_OFFSET(0x320)
+#define IOP13XX_ATUE_OUMWTVR3           IOP13XX_ATUE_OFFSET(0x324)
+#define IOP13XX_ATUE_ATUCR              IOP13XX_ATUE_OFFSET(0x70)
+#define IOP13XX_ATUE_PCSR               IOP13XX_ATUE_OFFSET(0x74)
+#define IOP13XX_ATUE_ATUISR             IOP13XX_ATUE_OFFSET(0x78)
+#define IOP13XX_ATUE_OIOBAR             IOP13XX_ATUE_OFFSET(0x300)
+#define IOP13XX_ATUE_OCCAR              IOP13XX_ATUE_OFFSET(0x32c)
+#define IOP13XX_ATUE_OCCDR              IOP13XX_ATUE_OFFSET(0x330)
+#define IOP13XX_ATUE_PIE_STS            IOP13XX_ATUE_OFFSET(0x384)
+#define IOP13XX_ATUE_PIE_MSK            IOP13XX_ATUE_OFFSET(0x388)
+#define IOP13XX_ATUE_ATUCR_IVM          (1 << 6)
+#define IOP13XX_ATUE_ATUCR_OUT_EN       (1 << 1)
+#define IOP13XX_ATUE_OCCAR_BUS_NUM      (24)
+#define IOP13XX_ATUE_OCCAR_DEV_NUM      (19)
+#define IOP13XX_ATUE_OCCAR_FUNC_NUM     (16)
+#define IOP13XX_ATUE_OCCAR_EXT_REG      (8)
+#define IOP13XX_ATUE_OCCAR_REG          (2)
+#define IOP13XX_ATUE_PCSR_BUS_NUM       (24)
+#define IOP13XX_ATUE_PCSR_DEV_NUM       (19)
+#define IOP13XX_ATUE_PCSR_FUNC_NUM      (16)
+#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY    (1 << 15)
+#define IOP13XX_ATUE_PCSR_IN_Q_BUSY     (1 << 14)
+#define IOP13XX_ATUE_PCSR_END_POINT     (1 << 13)
+#define IOP13XX_ATUE_PCSR_LLRB_BUSY     (1 << 12)
+#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK          (0xff)
+#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK          (0x1f)
+#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
+#define IOP13XX_ATUE_PCSR_CORE_RESET            (8)
+#define IOP13XX_ATUE_PCSR_FUNC_NUM              (16)
+#define IOP13XX_ATUE_LSTS_TRAINING              (1 << 11)
+#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG          (1 << 28)
+#define IOP13XX_ATUE_STAT_PME                   (1 << 27)
+#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG          (1 << 26)
+#define IOP13XX_ATUE_STAT_IVM                   (1 << 25)
+#define IOP13XX_ATUE_STAT_BIST                  (1 << 24)
+#define IOP13XX_ATUE_STAT_CFG_WRITE             (1 << 18)
+#define IOP13XX_ATUE_STAT_VPD_ADDR              (1 << 17)
+#define IOP13XX_ATUE_STAT_POWER_TRAN            (1 << 16)
+#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
+#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR          (1 << 12)
+#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG          (1 << 11)
+#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
+#define IOP13XX_ATUE_STAT_ERR_COR               (1 << 9 )
+#define IOP13XX_ATUE_STAT_ERR_UNCOR             (1 << 8 )
+#define IOP13XX_ATUE_STAT_CRS                   (1 << 7 )
+#define IOP13XX_ATUE_STAT_LNK_DWN               (1 << 6 )
+#define IOP13XX_ATUE_STAT_INT_REC_MABORT        (1 << 5 )
+#define IOP13XX_ATUE_STAT_DET_PAR_ERR           (1 << 4 )
+#define IOP13XX_ATUE_STAT_EXT_REC_MABORT        (1 << 3 )
+#define IOP13XX_ATUE_STAT_SIG_TABORT            (1 << 2 )
+#define IOP13XX_ATUE_STAT_EXT_REC_TABORT        (1 << 1 )
+#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR       (1 << 0 )
+#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ     (1 << 31)
+#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT          (1 << 30)
+#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP              (1 << 29)
+#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR                   (1 << 28)
+#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ          (1 << 20)
+#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR         (1 << 19)
+#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP            (1 << 18)
+#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
+#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP          (1 << 16)
+#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT               (1 << 15)
+#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT         (1 << 14)
+#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR             (1 << 13)
+#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP             (1 << 12)
+#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR         (1 << 4 )
+#define IOP13XX_ATUE_ESTAT_TRAINING_ERR         (1 << 0 )
+#define IOP13XX_ATUE_IALR_DISABLE               (0x00000001)
+#define IOP13XX_ATUE_OUMBAR_ENABLE              (0x80000000)
+#define IOP13XX_ATU_OUMBAR_FUNC_NUM             (28)
+#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK        (0x7)
+/*=======================================================================*/
+/*==============================ADMA UNITS===============================*/
+#define IOP13XX_ADMA_PHYS_BASE(chan)    IOP13XX_REG_ADDR32_PHYS((chan << 9))
+#define IOP13XX_ADMA_UPPER_PA(chan)     (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
+#define IOP13XX_ADMA_OFFSET(chan, ofs)  IOP13XX_REG_ADDR32((chan << 9) + (ofs))
+#define IOP13XX_ADMA_ACCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x0)
+#define IOP13XX_ADMA_ACSR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x4)
+#define IOP13XX_ADMA_ADAR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x8)
+#define IOP13XX_ADMA_IIPCR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x18)
+#define IOP13XX_ADMA_IIPAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x1c)
+#define IOP13XX_ADMA_IIPUAR(chan)    IOP13XX_ADMA_OFFSET(chan, 0x20)
+#define IOP13XX_ADMA_ANDAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x24)
+#define IOP13XX_ADMA_ADCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x28)
+#define IOP13XX_ADMA_CARMD(chan)     IOP13XX_ADMA_OFFSET(chan, 0x2c)
+#define IOP13XX_ADMA_ABCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x30)
+#define IOP13XX_ADMA_DLADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x34)
+#define IOP13XX_ADMA_DUADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x38)
+#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
+#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
+/*==============================XSI BRIDGE===============================*/
+#define IOP13XX_XBG_BECSR               IOP13XX_REG_ADDR32(0x178c)
+#define IOP13XX_XBG_BERAR               IOP13XX_REG_ADDR32(0x1790)
+#define IOP13XX_XBG_BERUAR              IOP13XX_REG_ADDR32(0x1794)
+#define is_atue_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
+                                        IOP13XX_PMMR_VIRT_TO_PHYS(\
+                                        IOP13XX_ATUE_OCCDR))\
+                                        && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
+#define is_atux_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
+                                        IOP13XX_PMMR_VIRT_TO_PHYS(\
+                                        IOP13XX_ATUX_OCCDR))\
+                                        && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
+/*=======================================================================*/
+#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
+                                                        (ofs))
+#define IOP13XX_PBI_CR                  IOP13XX_PBI_OFFSET(0x0)
+#define IOP13XX_PBI_SR                  IOP13XX_PBI_OFFSET(0x4)
+#define IOP13XX_PBI_BAR0                IOP13XX_PBI_OFFSET(0x8)
+#define IOP13XX_PBI_LR0                 IOP13XX_PBI_OFFSET(0xc)
+#define IOP13XX_PBI_BAR1                IOP13XX_PBI_OFFSET(0x10)
+#define IOP13XX_PBI_LR1                 IOP13XX_PBI_OFFSET(0x14)
+#define IOP13XX_TMR_TC                  0x01
+#define IOP13XX_TMR_EN                  0x02
+#define IOP13XX_TMR_RELOAD              0x04
+#define IOP13XX_TMR_PRIVILEGED          0x08
+#define IOP13XX_TMR_RATIO_1_1           0x00
+#define IOP13XX_TMR_RATIO_4_1           0x10
+#define IOP13XX_TMR_RATIO_8_1           0x20
+#define IOP13XX_TMR_RATIO_16_1          0x30
+#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/include/asm-arm/arch-iop13xx/iq81340.h
new file mode 100644
index 000000000000..b98f8f109c22
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iq81340.h
@@ -0,0 +1,31 @@
+#ifndef _IQ81340_H_
+#define _IQ81340_H_
+#define IQ81340_PCE_BAR0    IOP13XX_PBI_LOWER_MEM_RA
+#define IQ81340_PCE_BAR1    (IQ81340_PCE_BAR0 + 0x02000000)
+#define IQ81340_FLASHBASE   IQ81340_PCE_BAR0    /* Flash */
+#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
+#define IQ81340_PRD_CODE    IQ81340_PCE_BAR1_OFFSET(0)
+#define IQ81340_BRD_STEP    IQ81340_PCE_BAR1_OFFSET(0x10000)
+#define IQ81340_CPLD_REV    IQ81340_PCE_BAR1_OFFSET(0x20000)
+#define IQ81340_LED          IQ81340_PCE_BAR1_OFFSET(0x30000)
+#define IQ81340_LHEX         IQ81340_PCE_BAR1_OFFSET(0x40000)
+#define IQ81340_RHEX         IQ81340_PCE_BAR1_OFFSET(0x50000)
+#define IQ81340_BUZZER       IQ81340_PCE_BAR1_OFFSET(0x60000)
+#define IQ81340_32K_NVRAM   IQ81340_PCE_BAR1_OFFSET(0x70000)
+#define IQ81340_256K_NVRAM  IQ81340_PCE_BAR1_OFFSET(0x80000)
+#define IQ81340_ROTARY_SW   IQ81340_PCE_BAR1_OFFSET(0xd0000)
+#define IQ81340_BATT_STAT   IQ81340_PCE_BAR1_OFFSET(0xf0000)
+#define IQ81340_CMP_FLSH    IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
+#define PBI_CF_IDE_BASE     (IQ81340_CMP_FLSH)
+#define PBI_CF_BAR_ADDR     (IOP13XX_PBI_BAR1)
+/* These are the values used in the Machine description */
+#define PHYS_IO         0xfeffff00
+#define IO_PG_OFFSET    0xffffff00
+#define BOOT_PARAM_OFFSET  0x00000100
+#endif  /* _IQ81340_H_ */
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h
new file mode 100644
index 000000000000..442e35a40359
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/irqs.h
@@ -0,0 +1,207 @@
+#ifndef _IOP13XX_IRQS_H_
+#define _IOP13XX_IRQS_H_
+#ifndef __ASSEMBLER__
+#include <linux/types.h>
+#include <asm/system.h> /* local_irq_save */
+#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
+/* INTPND0 CP6 R0 Page 3
+ */
+static inline u32 read_intpnd_0(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
+        return val;
+}
+/* INTPND1 CP6 R1 Page 3
+ */
+static inline u32 read_intpnd_1(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
+        return val;
+}
+/* INTPND2 CP6 R2 Page 3
+ */
+static inline u32 read_intpnd_2(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
+        return val;
+}
+/* INTPND3 CP6 R3 Page 3
+ */
+static inline u32 read_intpnd_3(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
+        return val;
+}
+static inline void
+iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
+{
+        local_irq_save(*irq_flags);
+        *cp_flags = iop13xx_cp6_save();
+}
+static inline void
+iop13xx_cp6_irq_restore(unsigned long *cp_flags,
+        unsigned long *irq_flags)
+{
+        iop13xx_cp6_restore(*cp_flags);
+        local_irq_restore(*irq_flags);
+}
+#endif
+#define INTBASE 0
+#define INTSIZE_4 1
+/*
+ * iop34x chipset interrupts
+ */
+#define IOP13XX_IRQ(x)          (IOP13XX_IRQ_OFS + (x))
+/*
+ * On IRQ or FIQ register
+ */
+#define IRQ_IOP13XX_ADMA0_EOT   (0)
+#define IRQ_IOP13XX_ADMA0_EOC   (1)
+#define IRQ_IOP13XX_ADMA1_EOT   (2)
+#define IRQ_IOP13XX_ADMA1_EOC   (3)
+#define IRQ_IOP13XX_ADMA2_EOT   (4)
+#define IRQ_IOP13XX_ADMA2_EOC   (5)
+#define IRQ_IOP134_WATCHDOG     (6)
+#define IRQ_IOP13XX_RSVD_7      (7)
+#define IRQ_IOP13XX_TIMER0      (8)
+#define IRQ_IOP13XX_TIMER1      (9)
+#define IRQ_IOP13XX_I2C_0       (10)
+#define IRQ_IOP13XX_I2C_1       (11)
+#define IRQ_IOP13XX_MSG (12)
+#define IRQ_IOP13XX_MSGIBQ      (13)
+#define IRQ_IOP13XX_ATU_IM      (14)
+#define IRQ_IOP13XX_ATU_BIST    (15)
+#define IRQ_IOP13XX_PPMU        (16)
+#define IRQ_IOP13XX_COREPMU     (17)
+#define IRQ_IOP13XX_CORECACHE   (18)
+#define IRQ_IOP13XX_RSVD_19     (19)
+#define IRQ_IOP13XX_RSVD_20     (20)
+#define IRQ_IOP13XX_RSVD_21     (21)
+#define IRQ_IOP13XX_RSVD_22     (22)
+#define IRQ_IOP13XX_RSVD_23     (23)
+#define IRQ_IOP13XX_XINT0       (24)
+#define IRQ_IOP13XX_XINT1       (25)
+#define IRQ_IOP13XX_XINT2       (26)
+#define IRQ_IOP13XX_XINT3       (27)
+#define IRQ_IOP13XX_XINT4       (28)
+#define IRQ_IOP13XX_XINT5       (29)
+#define IRQ_IOP13XX_XINT6       (30)
+#define IRQ_IOP13XX_XINT7       (31)
+                                      /* IINTSRC1 bit */
+#define IRQ_IOP13XX_XINT8       (32)  /* 0  */
+#define IRQ_IOP13XX_XINT9       (33)  /* 1  */
+#define IRQ_IOP13XX_XINT10      (34)  /* 2  */
+#define IRQ_IOP13XX_XINT11      (35)  /* 3  */
+#define IRQ_IOP13XX_XINT12      (36)  /* 4  */
+#define IRQ_IOP13XX_XINT13      (37)  /* 5  */
+#define IRQ_IOP13XX_XINT14      (38)  /* 6  */
+#define IRQ_IOP13XX_XINT15      (39)  /* 7  */
+#define IRQ_IOP13XX_RSVD_40     (40)  /* 8  */
+#define IRQ_IOP13XX_RSVD_41     (41)  /* 9  */
+#define IRQ_IOP13XX_RSVD_42     (42)  /* 10 */
+#define IRQ_IOP13XX_RSVD_43     (43)  /* 11 */
+#define IRQ_IOP13XX_RSVD_44     (44)  /* 12 */
+#define IRQ_IOP13XX_RSVD_45     (45)  /* 13 */
+#define IRQ_IOP13XX_RSVD_46     (46)  /* 14 */
+#define IRQ_IOP13XX_RSVD_47     (47)  /* 15 */
+#define IRQ_IOP13XX_RSVD_48     (48)  /* 16 */
+#define IRQ_IOP13XX_RSVD_49     (49)  /* 17 */
+#define IRQ_IOP13XX_RSVD_50     (50)  /* 18 */
+#define IRQ_IOP13XX_UART0       (51)  /* 19 */
+#define IRQ_IOP13XX_UART1       (52)  /* 20 */
+#define IRQ_IOP13XX_PBIE        (53)  /* 21 */
+#define IRQ_IOP13XX_ATU_CRW     (54)  /* 22 */
+#define IRQ_IOP13XX_ATU_ERR     (55)  /* 23 */
+#define IRQ_IOP13XX_MCU_ERR     (56)  /* 24 */
+#define IRQ_IOP13XX_ADMA0_ERR   (57)  /* 25 */
+#define IRQ_IOP13XX_ADMA1_ERR   (58)  /* 26 */
+#define IRQ_IOP13XX_ADMA2_ERR   (59)  /* 27 */
+#define IRQ_IOP13XX_RSVD_60     (60)  /* 28 */
+#define IRQ_IOP13XX_RSVD_61     (61)  /* 29 */
+#define IRQ_IOP13XX_MSG_ERR     (62)  /* 30 */
+#define IRQ_IOP13XX_RSVD_63     (63)  /* 31 */
+                                      /* IINTSRC2 bit */
+#define IRQ_IOP13XX_INTERPROC   (64)  /* 0  */
+#define IRQ_IOP13XX_RSVD_65     (65)  /* 1  */
+#define IRQ_IOP13XX_RSVD_66     (66)  /* 2  */
+#define IRQ_IOP13XX_RSVD_67     (67)  /* 3  */
+#define IRQ_IOP13XX_RSVD_68     (68)  /* 4  */
+#define IRQ_IOP13XX_RSVD_69     (69)  /* 5  */
+#define IRQ_IOP13XX_RSVD_70     (70)  /* 6  */
+#define IRQ_IOP13XX_RSVD_71     (71)  /* 7  */
+#define IRQ_IOP13XX_RSVD_72     (72)  /* 8  */
+#define IRQ_IOP13XX_RSVD_73     (73)  /* 9  */
+#define IRQ_IOP13XX_RSVD_74     (74)  /* 10 */
+#define IRQ_IOP13XX_RSVD_75     (75)  /* 11 */
+#define IRQ_IOP13XX_RSVD_76     (76)  /* 12 */
+#define IRQ_IOP13XX_RSVD_77     (77)  /* 13 */
+#define IRQ_IOP13XX_RSVD_78     (78)  /* 14 */
+#define IRQ_IOP13XX_RSVD_79     (79)  /* 15 */
+#define IRQ_IOP13XX_RSVD_80     (80)  /* 16 */
+#define IRQ_IOP13XX_RSVD_81     (81)  /* 17 */
+#define IRQ_IOP13XX_RSVD_82     (82)  /* 18 */
+#define IRQ_IOP13XX_RSVD_83     (83)  /* 19 */
+#define IRQ_IOP13XX_RSVD_84     (84)  /* 20 */
+#define IRQ_IOP13XX_RSVD_85     (85)  /* 21 */
+#define IRQ_IOP13XX_RSVD_86     (86)  /* 22 */
+#define IRQ_IOP13XX_RSVD_87     (87)  /* 23 */
+#define IRQ_IOP13XX_RSVD_88     (88)  /* 24 */
+#define IRQ_IOP13XX_RSVD_89     (89)  /* 25 */
+#define IRQ_IOP13XX_RSVD_90     (90)  /* 26 */
+#define IRQ_IOP13XX_RSVD_91     (91)  /* 27 */
+#define IRQ_IOP13XX_RSVD_92     (92)  /* 28 */
+#define IRQ_IOP13XX_RSVD_93     (93)  /* 29 */
+#define IRQ_IOP13XX_SIB_ERR     (94)  /* 30 */
+#define IRQ_IOP13XX_SRAM_ERR    (95)  /* 31 */
+                                      /* IINTSRC3 bit */
+#define IRQ_IOP13XX_I2C_2       (96)  /* 0  */
+#define IRQ_IOP13XX_ATUE_BIST   (97)  /* 1  */
+#define IRQ_IOP13XX_ATUE_CRW    (98)  /* 2  */
+#define IRQ_IOP13XX_ATUE_ERR    (99)  /* 3  */
+#define IRQ_IOP13XX_IMU (100) /* 4  */
+#define IRQ_IOP13XX_RSVD_101    (101) /* 5  */
+#define IRQ_IOP13XX_RSVD_102    (102) /* 6  */
+#define IRQ_IOP13XX_TPMI0_OUT   (103) /* 7  */
+#define IRQ_IOP13XX_TPMI1_OUT   (104) /* 8  */
+#define IRQ_IOP13XX_TPMI2_OUT   (105) /* 9  */
+#define IRQ_IOP13XX_TPMI3_OUT   (106) /* 10 */
+#define IRQ_IOP13XX_ATUE_IMA    (107) /* 11 */
+#define IRQ_IOP13XX_ATUE_IMB    (108) /* 12 */
+#define IRQ_IOP13XX_ATUE_IMC    (109) /* 13 */
+#define IRQ_IOP13XX_ATUE_IMD    (110) /* 14 */
+#define IRQ_IOP13XX_MU_MSI_TB   (111) /* 15 */
+#define IRQ_IOP13XX_RSVD_112    (112) /* 16 */
+#define IRQ_IOP13XX_RSVD_113    (113) /* 17 */
+#define IRQ_IOP13XX_RSVD_114    (114) /* 18 */
+#define IRQ_IOP13XX_RSVD_115    (115) /* 19 */
+#define IRQ_IOP13XX_RSVD_116    (116) /* 20 */
+#define IRQ_IOP13XX_RSVD_117    (117) /* 21 */
+#define IRQ_IOP13XX_RSVD_118    (118) /* 22 */
+#define IRQ_IOP13XX_RSVD_119    (119) /* 23 */
+#define IRQ_IOP13XX_RSVD_120    (120) /* 24 */
+#define IRQ_IOP13XX_RSVD_121    (121) /* 25 */
+#define IRQ_IOP13XX_RSVD_122    (122) /* 26 */
+#define IRQ_IOP13XX_RSVD_123    (123) /* 27 */
+#define IRQ_IOP13XX_RSVD_124    (124) /* 28 */
+#define IRQ_IOP13XX_RSVD_125    (125) /* 29 */
+#define IRQ_IOP13XX_RSVD_126    (126) /* 30 */
+#define IRQ_IOP13XX_HPI (127) /* 31 */
+#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
+#define NR_IRQS         NR_IOP13XX_IRQS
+#endif /* _IOP13XX_IRQ_H_ */
diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h
new file mode 100644
index 000000000000..031a0fa78eff
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/memory.h
@@ -0,0 +1,64 @@
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+#include <asm/arch/hardware.h>
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+#define TASK_SIZE       UL(0x3f000000)
+#define PAGE_OFFSET     UL(0x40000000)
+#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_ARCH_IOP13XX)
+#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
+#define IOP13XX_PMMR_V_END   (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
+#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
+#define IOP13XX_PMMR_P_END   (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
+/*
+ * Virtual view <-> PCI DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+/* RAM has 1:1 mapping on the PCIe/x Busses */
+#define __virt_to_bus(x)        (__virt_to_phys(x))
+#define __bus_to_virt(x)    (__phys_to_virt(x))
+#define virt_to_lbus(x)                                            \
+(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) &&                  \
+((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ?                       \
+((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
+((x) - PAGE_OFFSET + PHYS_OFFSET))
+#define lbus_to_virt(x)                                            \
+(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
+((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
+((x) - PHYS_OFFSET + PAGE_OFFSET))
+/* Device is an lbus device if it is on the platform bus of the IOP13XX */
+#define is_lbus_device(dev) (dev &&\
+                             (strncmp(dev->bus->name, "platform", 8) == 0))
+#define __arch_page_to_dma(dev, page)                                   \
+({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
+(dma_addr_t)__virt_to_bus(page_address(page));})
+#define __arch_dma_to_virt(dev, addr) \
+({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
+#define __arch_virt_to_dma(dev, addr) \
+({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
+#endif /* CONFIG_ARCH_IOP13XX */
+#endif /* !ASSEMBLY */
+#define PFN_TO_NID(addr)        (0)
+#endif
diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h
new file mode 100644
index 000000000000..4041f30d4cd3
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/pci.h
@@ -0,0 +1,57 @@
+#ifndef _IOP13XX_PCI_H_
+#define _IOP13XX_PCI_H_
+#include <asm/arch/irqs.h>
+#include <asm/io.h>
+struct pci_sys_data;
+struct hw_pci;
+int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
+struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
+void iop13xx_atu_select(struct hw_pci *plat_pci);
+void iop13xx_pci_init(void);
+void iop13xx_map_pci_memory(void);
+#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY |            \
+                               PCI_STATUS_SIG_TARGET_ABORT | \
+                               PCI_STATUS_REC_TARGET_ABORT | \
+                               PCI_STATUS_REC_TARGET_ABORT | \
+                               PCI_STATUS_REC_MASTER_ABORT | \
+                               PCI_STATUS_SIG_SYSTEM_ERROR | \
+                               PCI_STATUS_DETECTED_PARITY)
+#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR |  \
+                                    IOP13XX_ATUE_STAT_ROOT_SYS_ERR |   \
+                                    IOP13XX_ATUE_STAT_PCI_IFACE_ERR |  \
+                                    IOP13XX_ATUE_STAT_ERR_COR |        \
+                                    IOP13XX_ATUE_STAT_ERR_UNCOR |      \
+                                    IOP13XX_ATUE_STAT_CRS |            \
+                                    IOP13XX_ATUE_STAT_DET_PAR_ERR |    \
+                                    IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
+                                    IOP13XX_ATUE_STAT_SIG_TABORT |     \
+                                    IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
+                                    IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
+#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM |        \
+                                    IOP13XX_ATUX_STAT_REC_SCEM |       \
+                                    IOP13XX_ATUX_STAT_TX_SERR |        \
+                                    IOP13XX_ATUX_STAT_DET_PAR_ERR |    \
+                                    IOP13XX_ATUX_STAT_INT_REC_MABORT | \
+                                    IOP13XX_ATUX_STAT_REC_SERR |       \
+                                    IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
+                                    IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
+                                    IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
+                                    IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
+/* PCI interrupts
+ */
+#define ATUX_INTA IRQ_IOP13XX_XINT0
+#define ATUX_INTB IRQ_IOP13XX_XINT1
+#define ATUX_INTC IRQ_IOP13XX_XINT2
+#define ATUX_INTD IRQ_IOP13XX_XINT3
+#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
+#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
+#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
+#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
+#endif /* _IOP13XX_PCI_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
new file mode 100644
index 000000000000..ee3a62530af2
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -0,0 +1,59 @@
+/*
+ * linux/include/asm-arm/arch-iop13xx/system.h
+ *
+ *  Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/arch/iop13xx.h>
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+/* WDTCR CP6 R7 Page 9 */
+static inline u32 read_wdtcr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtcr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
+}
+/* WDTSR CP6 R8 Page 9 */
+static inline u32 read_wdtsr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtsr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
+}
+#define IOP13XX_WDTCR_EN_ARM    0x1e1e1e1e
+#define IOP13XX_WDTCR_EN        0xe1e1e1e1
+#define IOP13XX_WDTCR_DIS_ARM   0x1f1f1f1f
+#define IOP13XX_WDTCR_DIS       0xf1f1f1f1
+#define IOP13XX_WDTSR_WRITE_EN  (1 << 31)
+#define IOP13XX_WDTCR_IB_RESET  (1 << 0)
+static inline void arch_reset(char mode)
+{
+        /*
+         * Reset the internal bus (warning both cores are reset)
+         */
+        u32 cp_flags = iop13xx_cp6_save();
+        write_wdtcr(IOP13XX_WDTCR_EN_ARM);
+        write_wdtcr(IOP13XX_WDTCR_EN);
+        write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
+        write_wdtcr(0x1000);
+        iop13xx_cp6_restore(cp_flags);
+        for(;;);
+}
diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h
new file mode 100644
index 000000000000..f0c51dd97ed8
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/timex.h
@@ -0,0 +1,3 @@
+#include <asm/hardware.h>
+#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
new file mode 100644
index 000000000000..b9525d59b7ad
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/uncompress.h
@@ -0,0 +1,24 @@
+#include <asm/types.h>
+#include <linux/serial_reg.h>
+#include <asm/hardware.h>
+#include <asm/processor.h>
+#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
+#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
+static inline void putc(char c)
+{
+        while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
+                cpu_relax();
+        UART_BASE[UART_TX] = c;
+}
+static inline void flush(void)
+{
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/include/asm-arm/arch-iop13xx/vmalloc.h
new file mode 100644
index 000000000000..c53456740345
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/vmalloc.h
@@ -0,0 +1,4 @@
+#ifndef _VMALLOC_H_
+#define _VMALLOC_H_
+#define VMALLOC_END     0xfa000000UL
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h
index 4281838873ef..6b437f7c9955 100644
--- a/include/asm-arm/arch-ixp4xx/nslu2.h
+++ b/include/asm-arm/arch-ixp4xx/nslu2.h
@@ -76,6 +76,7 @@
 #define NSLU2_GPIO_BUZZ         4
 #define NSLU2_BZ_BM             (1L << NSLU2_GPIO_BUZZ)
 /* LEDs */
 #define NSLU2_LED_RED           NSLU2_GPIO0
@@ -84,8 +85,8 @@
 #define NSLU2_LED_RED_BM        (1L << NSLU2_LED_RED)
 #define NSLU2_LED_GRN_BM        (1L << NSLU2_LED_GRN)
-#define NSLU2_LED_DISK1         NSLU2_GPIO2
+#define NSLU2_LED_DISK1         NSLU2_GPIO3
-#define NSLU2_LED_DISK2         NSLU2_GPIO3
+#define NSLU2_LED_DISK2         NSLU2_GPIO2
 #define NSLU2_LED_DISK1_BM      (1L << NSLU2_GPIO2)
 #define NSLU2_LED_DISK2_BM      (1L << NSLU2_GPIO3)
diff --git a/include/asm-arm/arch-ixp4xx/udc.h b/include/asm-arm/arch-ixp4xx/udc.h
new file mode 100644
index 000000000000..dbdec36ff0d1
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/udc.h
@@ -0,0 +1,8 @@
+/*
+ * linux/include/asm-arm/arch-ixp4xx/udc.h
+ *
+ */
+#include <asm/mach/udc_pxa2xx.h>
+extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index d744d97c18a5..645dbdfb3908 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -17,59 +17,11 @@
 /*
 * There are not real ISA nor PCI buses, so we fake it.
 */
-#define __io_pci(a)             ((void __iomem *)(PCIO_BASE + (a)))
+static inline void __iomem *__io(unsigned long addr)
-#define __mem_pci(a)            (a)
-#define __ioaddr(p)             __io_pci(p)
-/*
- * Generic virtual read/write
- */
-#define __arch_getb(a)          (*(volatile unsigned char *)(a))
-#define __arch_getl(a)          (*(volatile unsigned int  *)(a))
-static inline unsigned int __arch_getw(unsigned long a)
-{
-        unsigned int value;
-        __asm__ __volatile__("ldrh    %0, [%1, #0]    @ getw"
-                : "=&r" (value)
-                : "r" (a) : "cc");
-        return value;
-}
-#define __arch_putb(v,a)        (*(volatile unsigned char *)(a) = (v))
-#define __arch_putl(v,a)        (*(volatile unsigned int  *)(a) = (v))
-static inline void __arch_putw(unsigned int value, unsigned long a)
 {
-        __asm__ __volatile__("strh    %0, [%1, #0]    @ putw"
+        return (void __iomem *)addr;
-                : : "r" (value), "r" (a) : "cc");
 }
+#define __io(a) __io(a)
-/*
+#define __mem_pci(a)            (a)
- * Translated address IO functions
- *
- * IO address has already been translated to a virtual address
- */
-#define outb_t(v,p)             (*(volatile unsigned char *)(p) = (v))
-#define inb_t(p)                (*(volatile unsigned char *)(p))
-#define outw_t(v,p)             (*(volatile unsigned int *)(p) = (v))
-#define inw_t(p)                (*(volatile unsigned int *)(p))
-#define outl_t(v,p)             (*(volatile unsigned long *)(p) = (v))
-#define inl_t(p)                (*(volatile unsigned long *)(p))
-/*
- * FIXME - These are to allow for linking. On all the other
- *         ARM platforms, the entire IO space is contiguous.
- *         The 7200 has three separate IO spaces. The below
- *         macros will eventually become more involved. Use
- *         with caution and don't be surprised by kernel oopses!!!
- */
-#define inb(p)                  inb_t(p)
-#define inw(p)                  inw_t(p)
-#define inl(p)                  inl_t(p)
-#define outb(v,p)               outb_t(v,p)
-#define outw(v,p)               outw_t(v,p)
-#define outl(v,p)               outl_t(v,p)
 #endif
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
index 9f1a58cbf407..9b0c8012e713 100644
--- a/include/asm-arm/arch-lh7a40x/memory.h
+++ b/include/asm-arm/arch-lh7a40x/memory.h
@@ -58,18 +58,6 @@
 #endif
 /*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and return the mem_map of that node.
- */
-# define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-/*
- * Given a page frame number, find the owning node of the memory
- * and return the mem_map of that node.
- */
-# define PFN_TO_MAPBASE(pfn)    NODE_MEM_MAP(PFN_TO_NID(pfn))
-/*
 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
 * and returns the index corresponding to the appropriate page in the
 * node's mem_map.
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index eaf6d43939e9..e17f9881faf0 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -27,7 +27,6 @@
 #define __virt_to_bus(x)         __virt_to_phys(x)
 #define __bus_to_virt(x)         __phys_to_virt(x)
-#ifdef CONFIG_DISCONTIGMEM
 /*
 * The nodes are matched with the physical SDRAM banks as follows:
 *
@@ -35,38 +34,9 @@
 *      node 1:  0xa4000000-0xa7ffffff  -->  0xc4000000-0xc7ffffff
 *      node 2:  0xa8000000-0xabffffff  -->  0xc8000000-0xcbffffff
 *      node 3:  0xac000000-0xafffffff  -->  0xcc000000-0xcfffffff
+ *
+ * This needs a node mem size of 26 bits.
 */
+#define NODE_MEM_SIZE_BITS      26
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26)
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn)         (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-/*
- * Given a page frame number, find the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT)
-#endif
 #endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index cff752f35230..083e03c5639f 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -99,7 +99,7 @@
 #define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
 #define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
 #define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
-#define DCSR_ENRINTR    (1 << 9)        /* The end of Receive */
+#define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
 #endif
 #define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
 #define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
@@ -803,12 +803,11 @@
 #define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
 #define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCISR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
+#define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
-#define UDCISR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
+#define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
-#define UDCISR1_IERU    (1 << 29)       /* IntEn - Resume */
+#define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
-#define UDCISR1_IESU    (1 << 28)       /* IntEn - Suspend */
+#define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
-#define UDCISR1_IERS    (1 << 27)       /* IntEn - Reset */
+#define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
 #define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
 #define UDCOTGICR       __REG(0x40600018) /* UDC On-The-Go interrupt control */
diff --git a/include/asm-arm/arch-s3c2410/h1940.h b/include/asm-arm/arch-s3c2410/h1940.h
new file mode 100644
index 000000000000..6135592e60f2
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/h1940.h
@@ -0,0 +1,21 @@
+/* linux/include/asm-arm/arch-s3c2410/h1940.h
+ *
+ * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
+ *
+ * H1940 definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_H1940_H
+#define __ASM_ARCH_H1940_H
+#define H1940_SUSPEND_CHECKSUM          (0x30003ff8)
+#define H1940_SUSPEND_RESUMEAT          (0x30081000)
+#define H1940_SUSPEND_CHECK             (0x30080000)
+extern void h1940_pm_return(void);
+#endif /* __ASM_ARCH_H1940_H */
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 718246d85952..4f72a853a5cf 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -71,7 +71,7 @@ arch_reset(char mode)
        /* set the watchdog to go and reset... */
        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
-                     S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
+                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
        /* wait for reset to assert... */
        mdelay(5000);
diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h
deleted file mode 100644
index 3f37ca07806d..000000000000
--- a/include/asm-arm/arch-sa1100/jornada720.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/jornada720.h
- *
- * Created 2000/11/29 by John Ankcorn <jca@lcs.mit.edu>
- *
- * This file contains the hardware specific definitions for HP Jornada 720
- *
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "include <asm/hardware.h> instead"
-#endif
-#define SA1111_BASE             (0x40000000)
-#define GPIO_JORNADA720_KEYBOARD        GPIO_GPIO(0)
-#define GPIO_JORNADA720_MOUSE           GPIO_GPIO(9)
-#define GPIO_JORNADA720_KEYBOARD_IRQ    IRQ_GPIO0
-#define GPIO_JORNADA720_MOUSE_IRQ               IRQ_GPIO9
-/* MCU COMMANDS */
-#define MCU_GetBatteryData  0xc0
-#define MCU_GetScanKeyCode  0x90
-#define MCU_GetTouchSamples 0xa0
-#define MCU_GetContrast     0xD0
-#define MCU_SetContrast     0xD1
-#define MCU_GetBrightness   0xD2
-#define MCU_SetBrightness   0xD3
-#define MCU_ContrastOff     0xD8
-#define MCU_BrightnessOff   0xD9
-#define MCU_PWMOFF          0xDF
-#define MCU_TxDummy         0x11
-#define MCU_ErrorCode       0x00
-#ifndef __ASSEMBLY__
-void jornada720_mcu_init(void);
-void jornada_contrast(int arg_contrast);
-void jornada720_battery(void);
-int jornada720_getkey(unsigned char *data, int size);
-#endif
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
index 1ff172dc8e33..0e907fc6d42a 100644
--- a/include/asm-arm/arch-sa1100/memory.h
+++ b/include/asm-arm/arch-sa1100/memory.h
@@ -39,7 +39,6 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
 #define __virt_to_bus(x)         __virt_to_phys(x)
 #define __bus_to_virt(x)         __phys_to_virt(x)
-#ifdef CONFIG_DISCONTIGMEM
 /*
 * Because of the wide memory address space between physical RAM banks on the 
 * SA1100, it's much convenient to use Linux's NUMA support to implement our 
@@ -57,38 +56,7 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
 *      node 2:  0xd0000000 - 0xd7ffffff
 *      node 3:  0xd8000000 - 0xdfffffff
 */
+#define NODE_MEM_SIZE_BITS      27
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 27)
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn)         (((pfn) - PHYS_PFN_OFFSET) >> (27 - PAGE_SHIFT))
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and return the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-/*
- * Given a page frame number, find the owning node of the memory
- * and return the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & 0x07ffffff) >> PAGE_SHIFT)
-#endif
 /*
 * Cache flushing area - SA1100 zero bank
diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h
index 0e36fd5d87df..7b62351f097d 100644
--- a/include/asm-arm/bug.h
+++ b/include/asm-arm/bug.h
@@ -4,10 +4,10 @@
 #ifdef CONFIG_BUG
 #ifdef CONFIG_DEBUG_BUGVERBOSE
-extern void __bug(const char *file, int line, void *data) __attribute__((noreturn));
+extern void __bug(const char *file, int line) __attribute__((noreturn));
 /* give file/line information */
-#define BUG()           __bug(__FILE__, __LINE__, NULL)
+#define BUG()           __bug(__FILE__, __LINE__)
 #else
diff --git a/include/asm-arm/cnt32_to_63.h b/include/asm-arm/cnt32_to_63.h
new file mode 100644
index 000000000000..480c873fa746
--- /dev/null
+++ b/include/asm-arm/cnt32_to_63.h
@@ -0,0 +1,78 @@
+/*
+ *  include/asm/cnt32_to_63.h -- extend a 32-bit counter to 63 bits
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    December 3, 2006
+ *  Copyright:  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+#ifndef __INCLUDE_CNT32_TO_63_H__
+#define __INCLUDE_CNT32_TO_63_H__
+#include <linux/compiler.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+/*
+ * Prototype: u64 cnt32_to_63(u32 cnt)
+ * Many hardware clock counters are only 32 bits wide and therefore have
+ * a relatively short period making wrap-arounds rather frequent.  This
+ * is a problem when implementing sched_clock() for example, where a 64-bit
+ * non-wrapping monotonic value is expected to be returned.
+ *
+ * To overcome that limitation, let's extend a 32-bit counter to 63 bits
+ * in a completely lock free fashion. Bits 0 to 31 of the clock are provided
+ * by the hardware while bits 32 to 62 are stored in memory.  The top bit in
+ * memory is used to synchronize with the hardware clock half-period.  When
+ * the top bit of both counters (hardware and in memory) differ then the
+ * memory is updated with a new value, incrementing it when the hardware
+ * counter wraps around.
+ *
+ * Because a word store in memory is atomic then the incremented value will
+ * always be in synch with the top bit indicating to any potential concurrent
+ * reader if the value in memory is up to date or not with regards to the
+ * needed increment.  And any race in updating the value in memory is harmless
+ * as the same value would simply be stored more than once.
+ *
+ * The only restriction for the algorithm to work properly is that this
+ * code must be executed at least once per each half period of the 32-bit
+ * counter to properly update the state bit in memory. This is usually not a
+ * problem in practice, but if it is then a kernel timer could be scheduled
+ * to manage for this code to be executed often enough.
+ *
+ * Note that the top bit (bit 63) in the returned value should be considered
+ * as garbage.  It is not cleared here because callers are likely to use a
+ * multiplier on the returned value which can get rid of the top bit
+ * implicitly by making the multiplier even, therefore saving on a runtime
+ * clear-bit instruction. Otherwise caller must remember to clear the top
+ * bit explicitly.
+ */
+/* this is used only to give gcc a clue about good code generation */
+typedef union {
+        struct {
+#if defined(__LITTLE_ENDIAN)
+                u32 lo, hi;
+#elif defined(__BIG_ENDIAN)
+                u32 hi, lo;
+#endif
+        };
+        u64 val;
+} cnt32_to_63_t;
+#define cnt32_to_63(cnt_lo) \
+({ \
+        static volatile u32 __m_cnt_hi = 0; \
+        cnt32_to_63_t __x; \
+        __x.hi = __m_cnt_hi; \
+        __x.lo = (cnt_lo); \
+        if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \
+                __m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \
+        __x.val; \
+})
+#endif
diff --git a/include/asm-arm/div64.h b/include/asm-arm/div64.h
index 3682616804ca..37e0a96e8789 100644
--- a/include/asm-arm/div64.h
+++ b/include/asm-arm/div64.h
@@ -27,7 +27,7 @@
 #define __xh "r1"
 #endif
-#define do_div(n,base)                                          \
+#define __do_div_asm(n, base)                                   \
 ({                                                              \
        register unsigned int __base      asm("r4") = base;     \
        register unsigned long long __n   asm("r0") = n;        \
@@ -45,4 +45,182 @@
        __rem;                                                  \
 })
+#if __GNUC__ < 4
+/*
+ * gcc versions earlier than 4.0 are simply too problematic for the
+ * optimized implementation below. First there is gcc PR 15089 that
+ * tend to trig on more complex constructs, spurious .global __udivsi3
+ * are inserted even if none of those symbols are referenced in the
+ * generated code, and those gcc versions are not able to do constant
+ * propagation on long long values anyway.
+ */
+#define do_div(n, base) __do_div_asm(n, base)
+#elif __GNUC__ >= 4
+#include <asm/bug.h>
+/*
+ * If the divisor happens to be constant, we determine the appropriate
+ * inverse at compile time to turn the division into a few inline
+ * multiplications instead which is much faster. And yet only if compiling
+ * for ARMv4 or higher (we need umull/umlal) and if the gcc version is
+ * sufficiently recent to perform proper long long constant propagation.
+ * (It is unfortunate that gcc doesn't perform all this internally.)
+ */
+#define do_div(n, base)                                                 \
+({                                                                      \
+        unsigned int __r, __b = (base);                                 \
+        if (!__builtin_constant_p(__b) || __b == 0 ||                   \
+            (__LINUX_ARM_ARCH__ < 4 && (__b & (__b - 1)) != 0)) {       \
+                /* non-constant divisor (or zero): slow path */         \
+                __r = __do_div_asm(n, __b);                             \
+        } else if ((__b & (__b - 1)) == 0) {                            \
+                /* Trivial: __b is constant and a power of 2 */         \
+                /* gcc does the right thing with this code.  */         \
+                __r = n;                                                \
+                __r &= (__b - 1);                                       \
+                n /= __b;                                               \
+        } else {                                                        \
+                /* Multiply by inverse of __b: n/b = n*(p/b)/p       */ \
+                /* We rely on the fact that most of this code gets   */ \
+                /* optimized away at compile time due to constant    */ \
+                /* propagation and only a couple inline assembly     */ \
+                /* instructions should remain. Better avoid any      */ \
+                /* code construct that might prevent that.           */ \
+                unsigned long long __res, __x, __t, __m, __n = n;       \
+                unsigned int __c, __p, __z = 0;                         \
+                /* preserve low part of n for reminder computation */   \
+                __r = __n;                                              \
+                /* determine number of bits to represent __b */         \
+                __p = 1 << __div64_fls(__b);                            \
+                /* compute __m = ((__p << 64) + __b - 1) / __b */       \
+                __m = (~0ULL / __b) * __p;                              \
+                __m += (((~0ULL % __b + 1) * __p) + __b - 1) / __b;     \
+                /* compute __res = __m*(~0ULL/__b*__b-1)/(__p << 64) */ \
+                __x = ~0ULL / __b * __b - 1;                            \
+                __res = (__m & 0xffffffff) * (__x & 0xffffffff);        \
+                __res >>= 32;                                           \
+                __res += (__m & 0xffffffff) * (__x >> 32);              \
+                __t = __res;                                            \
+                __res += (__x & 0xffffffff) * (__m >> 32);              \
+                __t = (__res < __t) ? (1ULL << 32) : 0;                 \
+                __res = (__res >> 32) + __t;                            \
+                __res += (__m >> 32) * (__x >> 32);                     \
+                __res /= __p;                                           \
+                /* Now sanitize and optimize what we've got. */         \
+                if (~0ULL % (__b / (__b & -__b)) == 0) {                \
+                        /* those cases can be simplified with: */       \
+                        __n /= (__b & -__b);                            \
+                        __m = ~0ULL / (__b / (__b & -__b));             \
+                        __p = 1;                                        \
+                        __c = 1;                                        \
+                } else if (__res != __x / __b) {                        \
+                        /* We can't get away without a correction    */ \
+                        /* to compensate for bit truncation errors.  */ \
+                        /* To avoid it we'd need an additional bit   */ \
+                        /* to represent __m which would overflow it. */ \
+                        /* Instead we do m=p/b and n/b=(n*m+m)/p.    */ \
+                        __c = 1;                                        \
+                        /* Compute __m = (__p << 64) / __b */           \
+                        __m = (~0ULL / __b) * __p;                      \
+                        __m += ((~0ULL % __b + 1) * __p) / __b;         \
+                } else {                                                \
+                        /* Reduce __m/__p, and try to clear bit 31   */ \
+                        /* of __m when possible otherwise that'll    */ \
+                        /* need extra overflow handling later.       */ \
+                        unsigned int __bits = -(__m & -__m);            \
+                        __bits |= __m >> 32;                            \
+                        __bits = (~__bits) << 1;                        \
+                        /* If __bits == 0 then setting bit 31 is     */ \
+                        /* unavoidable.  Simply apply the maximum    */ \
+                        /* possible reduction in that case.          */ \
+                        /* Otherwise the MSB of __bits indicates the */ \
+                        /* best reduction we should apply.           */ \
+                        if (!__bits) {                                  \
+                                __p /= (__m & -__m);                    \
+                                __m /= (__m & -__m);                    \
+                        } else {                                        \
+                                __p >>= __div64_fls(__bits);            \
+                                __m >>= __div64_fls(__bits);            \
+                        }                                               \
+                        /* No correction needed. */                     \
+                        __c = 0;                                        \
+                }                                                       \
+                /* Now we have a combination of 2 conditions:        */ \
+                /* 1) whether or not we need a correction (__c), and */ \
+                /* 2) whether or not there might be an overflow in   */ \
+                /*    the cross product (__m & ((1<<63) | (1<<31)))  */ \
+                /* Select the best insn combination to perform the   */ \
+                /* actual __m * __n / (__p << 64) operation.         */ \
+                if (!__c) {                                             \
+                        asm (   "umull  %Q0, %R0, %1, %Q2\n\t"          \
+                                "mov    %Q0, #0"                        \
+                                : "=&r" (__res)                         \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                } else if (!(__m & ((1ULL << 63) | (1ULL << 31)))) {    \
+                        __res = __m;                                    \
+                        asm (   "umlal  %Q0, %R0, %Q1, %Q2\n\t"         \
+                                "mov    %Q0, #0"                        \
+                                : "+r" (__res)                          \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                } else {                                                \
+                        asm (   "umull  %Q0, %R0, %Q1, %Q2\n\t"         \
+                                "cmn    %Q0, %Q1\n\t"                   \
+                                "adcs   %R0, %R0, %R1\n\t"              \
+                                "adc    %Q0, %3, #0"                    \
+                                : "=&r" (__res)                         \
+                                : "r" (__m), "r" (__n), "r" (__z)       \
+                                : "cc" );                               \
+                }                                                       \
+                if (!(__m & ((1ULL << 63) | (1ULL << 31)))) {           \
+                        asm (   "umlal  %R0, %Q0, %R1, %Q2\n\t"         \
+                                "umlal  %R0, %Q0, %Q1, %R2\n\t"         \
+                                "mov    %R0, #0\n\t"                    \
+                                "umlal  %Q0, %R0, %R1, %R2"             \
+                                : "+r" (__res)                          \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                } else {                                                \
+                        asm (   "umlal  %R0, %Q0, %R2, %Q3\n\t"         \
+                                "umlal  %R0, %1, %Q2, %R3\n\t"          \
+                                "mov    %R0, #0\n\t"                    \
+                                "adds   %Q0, %1, %Q0\n\t"               \
+                                "adc    %R0, %R0, #0\n\t"               \
+                                "umlal  %Q0, %R0, %R2, %R3"             \
+                                : "+r" (__res), "+r" (__z)              \
+                                : "r" (__m), "r" (__n)                  \
+                                : "cc" );                               \
+                }                                                       \
+                __res /= __p;                                           \
+                /* The reminder can be computed with 32-bit regs     */ \
+                /* only, and gcc is good at that.                    */ \
+                {                                                       \
+                        unsigned int __res0 = __res;                    \
+                        unsigned int __b0 = __b;                        \
+                        __r -= __res0 * __b0;                           \
+                }                                                       \
+                /* BUG_ON(__r >= __b || __res * __b + __r != n); */     \
+                n = __res;                                              \
+        }                                                               \
+        __r;                                                            \
+})
+/* our own fls implementation to make sure constant propagation is fine */
+#define __div64_fls(bits)                                               \
+({                                                                      \
+        unsigned int __left = (bits), __nr = 0;                         \
+        if (__left & 0xffff0000) __nr += 16, __left >>= 16;             \
+        if (__left & 0x0000ff00) __nr +=  8, __left >>=  8;             \
+        if (__left & 0x000000f0) __nr +=  4, __left >>=  4;             \
+        if (__left & 0x0000000c) __nr +=  2, __left >>=  2;             \
+        if (__left & 0x00000002) __nr +=  1;                            \
+        __nr;                                                           \
+})
+#endif
 #endif
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index 17f0c656d272..642382d2c9f0 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -1,17 +1,22 @@
 #ifndef __ASMARM_ELF_H
 #define __ASMARM_ELF_H
+#ifndef __ASSEMBLY__
 /*
 * ELF register definitions..
 */
 #include <asm/ptrace.h>
 #include <asm/user.h>
 typedef unsigned long elf_greg_t;
 typedef unsigned long elf_freg_t[3];
+#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+typedef struct user_fp elf_fpregset_t;
+#endif
 #define EM_ARM  40
 #define EF_ARM_APCS26 0x08
 #define EF_ARM_SOFT_FLOAT 0x200
@@ -23,11 +28,6 @@ typedef unsigned long elf_freg_t[3];
 #define R_ARM_CALL      28
 #define R_ARM_JUMP24    29
-#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-typedef struct user_fp elf_fpregset_t;
 /*
 * These are used to set parameters in the core dumps.
 */
@@ -39,97 +39,99 @@ typedef struct user_fp elf_fpregset_t;
 #endif
 #define ELF_ARCH        EM_ARM
-#ifdef __KERNEL__
-#include <asm/procinfo.h>
 /*
- * This is used to ensure we don't load something for the wrong architecture.
+ * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
 */
-#define elf_check_arch(x) ( ((x)->e_machine == EM_ARM) && (ELF_PROC_OK((x))) )
+#define HWCAP_SWP       1
+#define HWCAP_HALF      2
-#define USE_ELF_CORE_DUMP
+#define HWCAP_THUMB     4
-#define ELF_EXEC_PAGESIZE       4096
+#define HWCAP_26BIT     8       /* Play it safe */
+#define HWCAP_FAST_MULT 16
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+#define HWCAP_FPA       32
-   use of this is to invoke "./ld.so someprog" to test out a new version of
+#define HWCAP_VFP       64
-   the loader.  We need to make sure that it is out of the way of the program
+#define HWCAP_EDSP      128
-   that it will "exec", and that there is sufficient room for the brk.  */
+#define HWCAP_JAVA      256
+#define HWCAP_IWMMXT    512
-#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
-/* When the program starts, a1 contains a pointer to a function to be 
-   registered with atexit, as per the SVR4 ABI.  A value of 0 means we 
-   have no such handler.  */
-#define ELF_PLAT_INIT(_r, load_addr)    (_r)->ARM_r0 = 0
-/* This yields a mask that user programs can use to figure out what
-   instruction set this cpu supports. */
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+/*
+ * This yields a mask that user programs can use to figure out what
+ * instruction set this cpu supports.
+ */
 #define ELF_HWCAP       (elf_hwcap)
+extern unsigned int elf_hwcap;
-/* This yields a string that ld.so will use to load implementation
+/*
-   specific libraries for optimization.  This is more specific in
+ * This yields a string that ld.so will use to load implementation
-   intent than poking at uname or /proc/cpuinfo. */
+ * specific libraries for optimization.  This is more specific in
+ * intent than poking at uname or /proc/cpuinfo.
-/* For now we just provide a fairly general string that describes the
+ *
-   processor family.  This could be made more specific later if someone
+ * For now we just provide a fairly general string that describes the
-   implemented optimisations that require it.  26-bit CPUs give you
+ * processor family.  This could be made more specific later if someone
-   "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't
+ * implemented optimisations that require it.  26-bit CPUs give you
-   supported).  32-bit CPUs give you "v3[lb]" for anything based on an
+ * "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't
-   ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1
+ * supported).  32-bit CPUs give you "v3[lb]" for anything based on an
-   core.  */
+ * ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1
+ * core.
+ */
 #define ELF_PLATFORM_SIZE 8
-extern char elf_platform[];
 #define ELF_PLATFORM    (elf_platform)
+extern char elf_platform[];
+#endif
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == EM_ARM && ELF_PROC_OK(x))
 /*
 * 32-bit code is always OK.  Some cpus can do 26-bit, some can't.
 */
 #define ELF_PROC_OK(x)  (ELF_THUMB_OK(x) && ELF_26BIT_OK(x))
 #define ELF_THUMB_OK(x) \
-        (( (elf_hwcap & HWCAP_THUMB) && ((x)->e_entry & 1) == 1) || \
+        ((elf_hwcap & HWCAP_THUMB && ((x)->e_entry & 1) == 1) || \
         ((x)->e_entry & 3) == 0)
 #define ELF_26BIT_OK(x) \
-        (( (elf_hwcap & HWCAP_26BIT) && (x)->e_flags & EF_ARM_APCS26) || \
+        ((elf_hwcap & HWCAP_26BIT && (x)->e_flags & EF_ARM_APCS26) || \
          ((x)->e_flags & EF_ARM_APCS26) == 0)
-#ifndef CONFIG_IWMMXT
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE       4096
-/* Old NetWinder binaries were compiled in such a way that the iBCS
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   heuristic always trips on them.  Until these binaries become uncommon
+   use of this is to invoke "./ld.so someprog" to test out a new version of
-   enough not to care, don't trust the `ibcs' flag here.  In any case
+   the loader.  We need to make sure that it is out of the way of the program
-   there is no other ELF system currently supported by iBCS.
+   that it will "exec", and that there is sufficient room for the brk.  */
-   @@ Could print a warning message to encourage users to upgrade.  */
-#define SET_PERSONALITY(ex,ibcs2) \
-        set_personality(((ex).e_flags&EF_ARM_APCS26 ?PER_LINUX :PER_LINUX_32BIT))
-#else
+#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
+/* When the program starts, a1 contains a pointer to a function to be 
+   registered with atexit, as per the SVR4 ABI.  A value of 0 means we 
+   have no such handler.  */
+#define ELF_PLAT_INIT(_r, load_addr)    (_r)->ARM_r0 = 0
 /*
- * All iWMMXt capable CPUs don't support 26-bit mode.  Yet they can run
+ * Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0
- * legacy binaries which used to contain FPA11 floating point instructions
+ * and CP1, we only enable access to the iWMMXt coprocessor if the
- * that have always been emulated by the kernel.  PFA11 and iWMMXt overlap
+ * binary is EABI or softfloat (and thus, guaranteed not to use
- * on coprocessor 1 space though.  We therefore must decide if given task
+ * FPA instructions.)
- * is allowed to use CP 0 and 1 for iWMMXt, or if they should be blocked
- * at all times for the prefetch exception handler to catch FPA11 opcodes
- * and emulate them.  The best indication to discriminate those two cases
- * is the SOFT_FLOAT flag in the ELF header.
 */
+#define SET_PERSONALITY(ex, ibcs2)                                      \
-#define SET_PERSONALITY(ex,ibcs2) \
+        do {                                                            \
-do { \
+                if ((ex).e_flags & EF_ARM_APCS26) {                     \
-        set_personality(PER_LINUX_32BIT); \
+                        set_personality(PER_LINUX);                     \
-        if (((ex).e_flags & EF_ARM_EABI_MASK) || \
+                } else {                                                \
-            ((ex).e_flags & EF_ARM_SOFT_FLOAT)) \
+                        set_personality(PER_LINUX_32BIT);               \
-                set_thread_flag(TIF_USING_IWMMXT); \
+                        if (elf_hwcap & HWCAP_IWMMXT && (ex).e_flags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) \
-        else \
+                                set_thread_flag(TIF_USING_IWMMXT);      \
-                clear_thread_flag(TIF_USING_IWMMXT); \
+                        else                                            \
-} while (0)
+                                clear_thread_flag(TIF_USING_IWMMXT);    \
+                }                                                       \
-#endif
+        } while (0)
 #endif
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index ae999fd5dc67..288f76b166d0 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -75,14 +75,6 @@ extern void __readwrite_bug(const char *fn);
 */
 #include <asm/arch/io.h>
-#ifdef __io_pci
-#warning machine class uses buggy __io_pci
-#endif
-#if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \
-    defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl)
-#warning machine class uses old __arch_putw or __arch_getw
-#endif
 /*
 *  IO port access primitives
 *  -------------------------
diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h
index 0e017ecf2096..eb0bfba6570d 100644
--- a/include/asm-arm/mach/irq.h
+++ b/include/asm-arm/mach/irq.h
@@ -22,12 +22,6 @@ extern void init_FIQ(void);
 extern int show_fiq_list(struct seq_file *, void *);
 /*
- * Function wrappers
- */
-#define set_irq_chipdata(irq, d)        set_irq_chip_data(irq, d)
-#define get_irq_chipdata(irq)           get_irq_chip_data(irq)
-/*
 * Obsolete inline function for calling irq descriptor handlers.
 */
 static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc)
@@ -44,12 +38,6 @@ void set_irq_flags(unsigned int irq, unsigned int flags);
 /*
 * This is for easy migration, but should be changed in the source
 */
-#define do_level_IRQ    handle_level_irq
-#define do_edge_IRQ     handle_edge_irq
-#define do_simple_IRQ   handle_simple_irq
-#define irqdesc         irq_desc
-#define irqchip         irq_chip
 #define do_bad_IRQ(irq,desc)                            \
 do {                                                    \
        spin_lock(&desc->lock);                         \
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index 91d536c215d7..d9bfb39adabf 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -215,6 +215,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 *  virt_addr_valid(k)  indicates whether a virtual address is valid
 */
 #ifndef CONFIG_DISCONTIGMEM
 #define ARCH_PFN_OFFSET         PHYS_PFN_OFFSET
 #define pfn_valid(pfn)          ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
@@ -230,6 +231,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 * around in memory.
 */
 #include <linux/numa.h>
 #define arch_pfn_to_nid(pfn)    PFN_TO_NID(pfn)
 #define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
@@ -256,6 +258,43 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 */
 #define PHYS_TO_NID(addr)       PFN_TO_NID((addr) >> PAGE_SHIFT)
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
+/*
+ * Given a page frame number, find the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
+#ifdef NODE_MEM_SIZE_BITS
+#define NODE_MEM_SIZE_MASK      ((1 << NODE_MEM_SIZE_BITS) - 1)
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) \
+        (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS)
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+#define PFN_TO_NID(pfn) \
+        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT))
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+#define LOCAL_MAP_NR(addr) \
+        (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT)
+#endif /* NODE_MEM_SIZE_BITS */
 #endif /* !CONFIG_DISCONTIGMEM */
 /*
diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h
index c1b264dff287..7b1c9acdf79a 100644
--- a/include/asm-arm/pgtable-nommu.h
+++ b/include/asm-arm/pgtable-nommu.h
@@ -44,7 +44,6 @@
 #define PAGE_READONLY   __pgprot(0)
 #define PAGE_KERNEL     __pgprot(0)
-//extern void paging_init(struct meminfo *, struct machine_desc *);
 #define swapper_pg_dir ((pgd_t *) 0)
 #define __swp_type(x)           (0)
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index ed8cb5963e99..88cd5c784ef0 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -169,8 +169,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 #define L_PTE_WRITE             (1 << 5)
 #define L_PTE_EXEC              (1 << 6)
 #define L_PTE_DIRTY             (1 << 7)
-#define L_PTE_COHERENT          (1 << 9)        /* I/O coherent (xsc3) */
+#define L_PTE_SHARED            (1 << 10)       /* shared(v6), coherent(xsc3) */
-#define L_PTE_SHARED            (1 << 10)       /* shared between CPUs (v6) */
 #define L_PTE_ASID              (1 << 11)       /* non-global (use ASID, v6) */
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h
index 04f4d34c6317..b442e8e2a809 100644
--- a/include/asm-arm/processor.h
+++ b/include/asm-arm/processor.h
@@ -20,7 +20,6 @@
 #ifdef __KERNEL__
 #include <asm/ptrace.h>
-#include <asm/procinfo.h>
 #include <asm/types.h>
 union debug_insn {
diff --git a/include/asm-arm/procinfo.h b/include/asm-arm/procinfo.h
index 91a31adfa8a8..4d3c685075e0 100644
--- a/include/asm-arm/procinfo.h
+++ b/include/asm-arm/procinfo.h
@@ -10,7 +10,7 @@
 #ifndef __ASM_PROCINFO_H
 #define __ASM_PROCINFO_H
-#ifndef __ASSEMBLY__
+#ifdef __KERNEL__
 struct cpu_tlb_fns;
 struct cpu_user_fns;
@@ -42,19 +42,8 @@ struct proc_info_list {
        struct cpu_cache_fns    *cache;
 };
-extern unsigned int elf_hwcap;
+#else   /* __KERNEL__ */
+#include <asm/elf.h>
-#endif  /* __ASSEMBLY__ */
+#warning "Please include asm/elf.h instead"
+#endif  /* __KERNEL__ */
-#define HWCAP_SWP       1
-#define HWCAP_HALF      2
-#define HWCAP_THUMB     4
-#define HWCAP_26BIT     8       /* Play it safe */
-#define HWCAP_FAST_MULT 16
-#define HWCAP_FPA       32
-#define HWCAP_VFP       64
-#define HWCAP_EDSP      128
-#define HWCAP_JAVA      256
-#define HWCAP_IWMMXT    512
 #endif
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index f28b236139ed..d9b8bddc8732 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -94,8 +94,18 @@ static inline struct thread_info *current_thread_info(void)
        return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
 }
-extern struct thread_info *alloc_thread_info(struct task_struct *task);
+/* thread information allocation */
-extern void free_thread_info(struct thread_info *);
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define alloc_thread_info(tsk) \
+        ((struct thread_info *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, \
+                THREAD_SIZE_ORDER))
+#else
+#define alloc_thread_info(tsk) \
+        ((struct thread_info *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER))
+#endif
+#define free_thread_info(info) \
+        free_pages((unsigned long)info, THREAD_SIZE_ORDER);
 #define thread_saved_pc(tsk)    \
        ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc)))
diff --git a/include/linux/i2c-pxa.h b/include/linux/i2c-pxa.h
index 5f3eaf802223..41dcdfe7f625 100644
--- a/include/linux/i2c-pxa.h
+++ b/include/linux/i2c-pxa.h
@@ -1,29 +1,6 @@
 #ifndef _LINUX_I2C_ALGO_PXA_H
 #define _LINUX_I2C_ALGO_PXA_H
-struct i2c_eeprom_emu_watcher {
-        void (*write)(void *, unsigned int addr, unsigned char newval);
-};
-struct i2c_eeprom_emu_watch {
-        struct list_head node;
-        unsigned int start;
-        unsigned int end;
-        struct i2c_eeprom_emu_watcher *ops;
-        void *data;
-};
-#define I2C_EEPROM_EMU_SIZE (256)
-struct i2c_eeprom_emu {
-        unsigned int size;
-        unsigned int ptr;
-        unsigned int seen_start;
-        struct list_head watch;
-        unsigned char bytes[I2C_EEPROM_EMU_SIZE];
-};
 typedef enum i2c_slave_event_e {
        I2C_SLAVE_EVENT_START_READ,
        I2C_SLAVE_EVENT_START_WRITE,
@@ -37,12 +14,4 @@ struct i2c_slave_client {
        void (*write)(void *ptr, unsigned int val);
 };
-extern int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *, void *data,
-                                     unsigned int addr, unsigned int size,
-                                     struct i2c_eeprom_emu_watcher *);
-extern void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *, void *data, struct i2c_eeprom_emu_watcher *watcher);
-extern struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void);
 #endif /* _LINUX_I2C_ALGO_PXA_H */