diff options
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 1957e3f14c04..f168b4030d40 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c | |||
| @@ -488,6 +488,7 @@ static void intel_pmu_enable_all(int added) | |||
| 488 | * Workaround for: | 488 | * Workaround for: |
| 489 | * Intel Errata AAK100 (model 26) | 489 | * Intel Errata AAK100 (model 26) |
| 490 | * Intel Errata AAP53 (model 30) | 490 | * Intel Errata AAP53 (model 30) |
| 491 | * Intel Errata BD53 (model 44) | ||
| 491 | * | 492 | * |
| 492 | * These chips need to be 'reset' when adding counters by programming | 493 | * These chips need to be 'reset' when adding counters by programming |
| 493 | * the magic three (non counting) events 0x4300D2, 0x4300B1 and 0x4300B5 | 494 | * the magic three (non counting) events 0x4300D2, 0x4300B1 and 0x4300B5 |
| @@ -980,6 +981,7 @@ static __init int intel_pmu_init(void) | |||
| 980 | intel_pmu_lbr_init_nhm(); | 981 | intel_pmu_lbr_init_nhm(); |
| 981 | 982 | ||
| 982 | x86_pmu.event_constraints = intel_westmere_event_constraints; | 983 | x86_pmu.event_constraints = intel_westmere_event_constraints; |
| 984 | x86_pmu.enable_all = intel_pmu_nhm_enable_all; | ||
| 983 | pr_cont("Westmere events, "); | 985 | pr_cont("Westmere events, "); |
| 984 | break; | 986 | break; |
| 985 | 987 | ||
