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-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-apbh.h151
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-apbx.h172
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h149
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-icoll.h55
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h211
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-power.h45
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-timrot.h59
7 files changed, 393 insertions, 449 deletions
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
index 3044c20ad90c..a323aa9a21f2 100644
--- a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * STMP APBH Register Definitions 2 * stmp37xx: APBH register definitions
3 * 3 *
4 * Copyright (c) 2008 Freescale Semiconductor 4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
@@ -18,85 +18,80 @@
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21#ifndef _INCLUDE_ASM_ARCH_REGS_APBH_H 21#ifndef _MACH_REGS_APBH
22#define _INCLUDE_ASM_ARCH_REGS_APBH_H 22#define _MACH_REGS_APBH
23 23
24#include <mach/stmp3xxx_regs.h> 24#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
25 25
26#ifndef REGS_APBH_BASE 26#define HW_APBH_CTRL0 0x0
27#define REGS_APBH_BASE (REGS_BASE + 0x00004000) 27#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
28#endif 28#define BP_APBH_CTRL0_RESET_CHANNEL 16
29#define BM_APBH_CTRL0_CLKGATE 0x40000000
30#define BM_APBH_CTRL0_SFTRST 0x80000000
31
32#define HW_APBH_CTRL1 0x10
33#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
34#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
35
36#define HW_APBH_DEVSEL 0x20
37
38#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
39#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
40#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
41#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
42#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
43#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
44#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
45#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
46#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
47#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
48#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
49#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
50#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
51#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
52#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
53#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
29 54
30HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00) 55#define HW_APBH_CHn_NXTCMDAR 0x50
31#define BP_APBH_CTRL0_SFTRST 31 56
32#define BM_APBH_CTRL0_SFTRST 0x80000000 57#define BM_APBH_CHn_CMD_MODE 0x00000003
33#define BP_APBH_CTRL0_CLKGATE 30 58#define BP_APBH_CHn_CMD_MODE 0x00000001
34#define BM_APBH_CTRL0_CLKGATE 0x40000000 59#define BV_APBH_CHn_CMD_MODE_NOOP 0
35#define BP_APBH_CTRL0_RESET_CHANNEL 16 60#define BV_APBH_CHn_CMD_MODE_WRITE 1
36#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 61#define BV_APBH_CHn_CMD_MODE_READ 2
37#define BF_APBH_CTRL0_RESET_CHANNEL(v) \ 62#define BV_APBH_CHn_CMD_MODE_SENSE 3
38 (((v) << BP_APBH_CTRL0_RESET_CHANNEL) & BM_APBH_CTRL0_RESET_CHANNEL)
39HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x10)
40#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 9
41#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00000200
42#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 8
43#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00000100
44#define BP_APBH_CTRL1_CH7_CMDCMPLT_IRQ 7
45#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080
46#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ 1
47#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002
48#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
49#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
50#define BP_APBH_CTRL1_CH1_ERR_IRQ 17
51#define BM_APBH_CTRL1_CH1_ERR_IRQ 0x00020000
52HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x20)
53HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x40, 0x70)
54HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x50, 0x70)
55#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0
56#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF
57#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v)
58HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x60, 0x70)
59#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
60#define BP_APBH_CHn_CMD_XFER_COUNT 16
61#define BF_APBH_CHn_CMD_XFER_COUNT(v) \
62 (((v) << BP_APBH_CHn_CMD_XFER_COUNT) & BM_APBH_CHn_CMD_XFER_COUNT)
63#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
64#define BP_APBH_CHn_CMD_CMDWORDS 12
65#define BF_APBH_CHn_CMD_CMDWORDS(v) \
66 (((v) << BP_APBH_CHn_CMD_CMDWORDS) & BM_APBH_CHn_CMD_CMDWORDS)
67#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
68#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
69#define BP_APBH_CHn_CMD_SEMAPHORE 6
70#define BF_APBH_CHn_CMD_SEMAPHORE(v) \
71 (((v) << BP_APBH_CHn_CMD_SEMAPHORE) & BM_APBH_CHn_CMD_SEMAPHORE)
72#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
73#define BP_APBH_CHn_CMD_NANDLOCK 4
74#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
75#define BF_APBH_CHn_CMD_NANDLOCK(v) \
76 (((v) << BP_APBH_CHn_CMD_NANDLOCK) & BM_APBH_CHn_CMD_NANDLOCK)
77#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
78#define BM_APBH_CHn_CMD_CHAIN 0x00000004 63#define BM_APBH_CHn_CMD_CHAIN 0x00000004
79#define BM_APBH_CHn_CMD_DMA_READ 0x00000003 64#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
80#define BP_APBH_CHn_CMD_DMA_READ 0 65#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
81#define BF_APBH_CHn_CMD_DMA_READ(v) \ 66#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
82 (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ) 67#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
83#define BF_APBH_CHn_CMD_COMMAND(v) \ 68#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
84 (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ) 69#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
85#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 70#define BP_APBH_CHn_CMD_CMDWORDS 12
86#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 71#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
87#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 72#define BP_APBH_CHn_CMD_XFER_COUNT 16
88#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 73
89HW_REGISTER_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x70, 0x70) 74#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
90HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x80, 0x70) 75#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
91#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 76#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
92#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF 77#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
93#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ 78#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
94 (((v) << BP_APBH_CHn_SEMA_INCREMENT_SEMA) & \ 79#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
95 BM_APBH_CHn_SEMA_INCREMENT_SEMA) 80#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
96#define BP_APBH_CHn_SEMA_PHORE 16 81#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
97#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 82#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
98HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x90, 0x70) 83#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
99HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0xA0, 0x70) 84#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
100HW_REGISTER_RO(HW_APBH_VERSION, REGS_APBH_BASE, 0x3F0) 85#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
86#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
87#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
88#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
89#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
101 90
102#endif /* _INCLUDE_ASM_ARCH_REGS_APBH_H */ 91#define HW_APBH_CHn_SEMA 0x80
92#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
93#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
94#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
95#define BP_APBH_CHn_SEMA_PHORE 16
96
97#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
index a14ddb97639a..6d080cd5b702 100644
--- a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * STMP APBX Register Definitions 2 * stmp37xx: APBX register definitions
3 * 3 *
4 * Copyright (c) 2008 Freescale Semiconductor 4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
@@ -18,92 +18,96 @@
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21#ifndef _INCLUDE_ASM_ARCH_REGS_APBX_H 21#ifndef _MACH_REGS_APBX
22#define _INCLUDE_ASM_ARCH_REGS_APBX_H 22#define _MACH_REGS_APBX
23 23
24#include <mach/stmp3xxx_regs.h> 24#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
25 25
26#ifndef REGS_APBX_BASE 26#define HW_APBX_CTRL0 0x0
27#define REGS_APBX_BASE (REGS_BASE + 0x00024000) 27#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000
28#endif 28#define BP_APBX_CTRL0_RESET_CHANNEL 16
29#define BM_APBX_CTRL0_CLKGATE 0x40000000
30#define BM_APBX_CTRL0_SFTRST 0x80000000
31
32#define HW_APBX_CTRL1 0x10
33
34#define HW_APBX_DEVSEL 0x20
35
36#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70)
37#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70)
38#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70)
39#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70)
40#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70)
41#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70)
42#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70)
43#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70)
44#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70)
45#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70)
46#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70)
47#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70)
48#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70)
49#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70)
50#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70)
51#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70)
29 52
30HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00) 53#define HW_APBX_CHn_NXTCMDAR 0x50
31#define BP_APBX_CTRL0_SFTRST 31 54#define BM_APBX_CHn_CMD_MODE 0x00000003
32#define BM_APBX_CTRL0_SFTRST 0x80000000 55#define BP_APBX_CHn_CMD_MODE 0x00000001
33#define BP_APBX_CTRL0_CLKGATE 30 56#define BV_APBX_CHn_CMD_MODE_NOOP 0
34#define BM_APBX_CTRL0_CLKGATE 0x40000000 57#define BV_APBX_CHn_CMD_MODE_WRITE 1
35#define BP_APBX_CTRL0_RESET_CHANNEL 16 58#define BV_APBX_CHn_CMD_MODE_READ 2
36#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000 59#define BV_APBX_CHn_CMD_MODE_SENSE 3
37#define BF_APBX_CTRL0_RESET_CHANNEL(v) \ 60#define BM_APBX_CHn_CMD_COMMAND 0x00000003
38 (((v) << BP_APBX_CTRL0_RESET_CHANNEL) & BM_APBX_CTRL0_RESET_CHANNEL) 61#define BP_APBX_CHn_CMD_COMMAND 0
39HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x10) 62#define BM_APBX_CHn_CMD_CHAIN 0x00000004
40HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x20) 63#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
41#define BP_APBX_DEVSEL_CH7 28 64#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
42#define BM_APBX_DEVSEL_CH7 0xF0000000 65#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
43#define BF_APBX_DEVSEL_CH7(v) \ 66#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
44 (((v) << BP_APBX_DEVSEL_CH7) & BM_APBX_DEVSEL_CH7) 67#define BP_APBX_CHn_CMD_CMDWORDS 12
45#define BV_APBX_DEVSEL_CH7__USE_UART 0x0 68#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
46#define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1 69#define BP_APBX_CHn_CMD_XFER_COUNT 16
47#define BP_APBX_DEVSEL_CH6 24
48#define BM_APBX_DEVSEL_CH6 0x0F000000
49#define BF_APBX_DEVSEL_CH6(v) \
50 (((v) << BP_APBX_DEVSEL_CH6) & BM_APBX_DEVSEL_CH6)
51#define BV_APBX_DEVSEL_CH6__USE_UART 0x0
52#define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1
53#define BP_APBX_CTRL1_CH7_AHB_ERROR_IRQ 23
54#define BM_APBX_CTRL1_CH7_AHB_ERROR_IRQ 0x00800000
55#define BP_APBX_CTRL1_CH6_AHB_ERROR_IRQ 22
56#define BM_APBX_CTRL1_CH6_AHB_ERROR_IRQ 0x00400000
57#define BP_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 15
58#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00008000
59#define BP_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 14
60#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00004000
61 70
62HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x40, 0x70) 71#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70)
63HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x50, 0x70) 72#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70)
64#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 73#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70)
65#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF 74#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70)
66#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v) 75#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70)
67HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x60, 0x70) 76#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70)
68#define BP_APBX_CHn_CMD_XFER_COUNT 16 77#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70)
69#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 78#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70)
70#define BF_APBX_CHn_CMD_XFER_COUNT(v) \ 79#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70)
71 (((v) << BP_APBX_CHn_CMD_XFER_COUNT) & BM_APBX_CHn_CMD_XFER_COUNT) 80#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70)
72#define BP_APBX_CHn_CMD_CMDWORDS 12 81#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70)
73#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 82#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70)
74#define BF_APBX_CHn_CMD_CMDWORDS(v) \ 83#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70)
75 (((v) << BP_APBX_CHn_CMD_CMDWORDS) & BM_APBX_CHn_CMD_CMDWORDS) 84#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70)
76#define BP_APBX_CHn_CMD_WAIT4ENDCMD 7 85#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70)
77#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 86#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70)
78#define BP_APBX_CHn_CMD_SEMAPHORE 6
79#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
80#define BP_APBX_CHn_CMD_IRQONCMPLT 3
81#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
82#define BP_APBX_CHn_CMD_CHAIN 2
83#define BM_APBX_CHn_CMD_CHAIN 0x00000004
84#define BM_APBX_CHn_CMD_DMA_READ 0x00000003
85#define BP_APBX_CHn_CMD_DMA_READ 0
86#define BF_APBX_CHn_CMD_DMA_READ(v) \
87 (((v) << BP_APBX_CHn_CMD_DMA_READ) & BM_APBX_CHn_CMD_DMA_READ)
88#define BP_APBX_CHn_CMD_COMMAND 0
89#define BM_APBX_CHn_CMD_COMMAND 0x00000003
90#define BF_APBX_CHn_CMD_COMMAND(v) \
91 (((v) << BP_APBX_CHn_CMD_COMMAND) & BM_APBX_CHn_CMD_COMMAND)
92#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
93#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1
94#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2
95 87
96HW_REGISTER_RO_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x70, 0x70) 88#define HW_APBX_CHn_BAR 0x70
97HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x80, 0x70)
98#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
99#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
100#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \
101 (((v) << BP_APBX_CHn_SEMA_INCREMENT_SEMA) & \
102 BM_APBX_CHn_SEMA_INCREMENT_SEMA)
103#define BP_APBX_CHn_SEMA_PHORE 16
104#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
105HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x90, 0x70)
106HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0xA0, 0x70)
107HW_REGISTER_RO(HW_APBX_VERSION, REGS_APBX_BASE, 0x3F0)
108 89
109#endif /* _INCLUDE_ASM_ARCH_REGS_APBX_H */ 90#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70)
91#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70)
92#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70)
93#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70)
94#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70)
95#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70)
96#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70)
97#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70)
98#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70)
99#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70)
100#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70)
101#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70)
102#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70)
103#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70)
104#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70)
105#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70)
106
107#define HW_APBX_CHn_SEMA 0x80
108#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
109#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
110#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
111#define BP_APBX_CHn_SEMA_PHORE 16
112
113#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
index 229ee75f90d9..47f5c92fdaf6 100644
--- a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
@@ -1,85 +1,72 @@
1#ifndef _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H 1/*
2#define _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H 2 * stmp37xx: CLKCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_CLKCTRL
22#define _MACH_REGS_CLKCTRL
3 23
4#include <mach/stmp3xxx_regs.h> 24#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
5 25
6#define REGS_CLKCTRL_BASE (REGS_BASE + 0x00040000) 26#define HW_CLKCTRL_PLLCTRL0 0x0
7
8#define HW_CLKCTRL_PLLCTRL0_ADDR (REGS_CLKCTRL_BASE + 0x00)
9HW_REGISTER(HW_CLKCTRL_PLLCTRL0, REGS_CLKCTRL_BASE, 0x00)
10#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 27#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
11#define HW_CLKCTRL_PLLCTRL1_ADDR (REGS_CLKCTRL_BASE + 0x10) 28
12HW_REGISTER(HW_CLKCTRL_PLLCTRL1, REGS_CLKCTRL_BASE, 0x10) 29#define HW_CLKCTRL_CPU 0x20
13 30#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
14#define HW_CLKCTRL_CPU_ADDR (REGS_CLKCTRL_BASE + 0x20) 31#define BP_CLKCTRL_CPU_DIV_CPU 0
15HW_REGISTER(HW_CLKCTRL_CPU, REGS_CLKCTRL_BASE, 0x20) 32
16#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F 33#define HW_CLKCTRL_HBUS 0x30
17#define BF_CLKCTRL_CPU_DIV_CPU(v) \ 34#define BM_CLKCTRL_HBUS_DIV 0x0000001F
18 (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) 35#define BP_CLKCTRL_HBUS_DIV 0
19 36
20#define HW_CLKCTRL_HBUS_ADDR (REGS_CLKCTRL_BASE + 0x30) 37#define HW_CLKCTRL_XBUS 0x40
21HW_REGISTER(HW_CLKCTRL_HBUS, REGS_CLKCTRL_BASE, 0x30) 38
22#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0 /* for compatitibility */ 39#define HW_CLKCTRL_XTAL 0x50
23#define BM_CLKCTRL_HBUS_DIV 0x0000001F 40
24#define BF_CLKCTRL_HBUS_DIV(v) \ 41#define HW_CLKCTRL_PIX 0x60
25 (((v) << 0) & BM_CLKCTRL_HBUS_DIV) 42#define BM_CLKCTRL_PIX_DIV 0x00007FFF
26#define HW_CLKCTRL_XBUS_ADDR (REGS_CLKCTRL_BASE + 0x40) 43#define BP_CLKCTRL_PIX_DIV 0
27HW_REGISTER(HW_CLKCTRL_XBUS, REGS_CLKCTRL_BASE, 0x40) 44#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
28#define HW_CLKCTRL_XTAL_ADDR (REGS_CLKCTRL_BASE + 0x50) 45
29HW_REGISTER(HW_CLKCTRL_XTAL, REGS_CLKCTRL_BASE, 0x50) 46#define HW_CLKCTRL_SSP 0x70
30#define HW_CLKCTRL_PIX_ADDR (REGS_CLKCTRL_BASE + 0x60) 47
31HW_REGISTER(HW_CLKCTRL_PIX, REGS_CLKCTRL_BASE, 0x60) 48#define HW_CLKCTRL_GPMI 0x80
32#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 49
33#define BM_CLKCTRL_PIX_BUSY 0x20000000 50#define HW_CLKCTRL_SPDIF 0x90
34#define BM_CLKCTRL_PIX_DIV 0x00007FFF 51
35#define BP_CLKCTRL_PIX_DIV 0 52#define HW_CLKCTRL_EMI 0xA0
36#define BF_CLKCTRL_PIX_DIV(v) \ 53
37 (((v) << BP_CLKCTRL_PIX_DIV) & BM_CLKCTRL_PIX_DIV) 54#define HW_CLKCTRL_IR 0xB0
38#define HW_CLKCTRL_SSP_ADDR (REGS_CLKCTRL_BASE + 0x70) 55
39HW_REGISTER(HW_CLKCTRL_SSP, REGS_CLKCTRL_BASE, 0x70) 56#define HW_CLKCTRL_SAIF 0xC0
40#define HW_CLKCTRL_GPMI_ADDR (REGS_CLKCTRL_BASE + 0x80) 57
41HW_REGISTER(HW_CLKCTRL_GPMI, REGS_CLKCTRL_BASE, 0x80) 58#define HW_CLKCTRL_FRAC 0xD0
42#define HW_CLKCTRL_SPDIF_ADDR (REGS_CLKCTRL_BASE + 0x90) 59#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
43HW_REGISTER(HW_CLKCTRL_SPDIF, REGS_CLKCTRL_BASE, 0x90) 60#define BP_CLKCTRL_FRAC_EMIFRAC 8
44#define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + 0xA0) 61#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
45HW_REGISTER(HW_CLKCTRL_EMI, REGS_CLKCTRL_BASE, 0xA0) 62#define BP_CLKCTRL_FRAC_PIXFRAC 16
46#define HW_CLKCTRL_IR_ADDR (REGS_CLKCTRL_BASE + 0xB0)
47HW_REGISTER(HW_CLKCTRL_IR, REGS_CLKCTRL_BASE, 0xB0)
48#define HW_CLKCTRL_SAIF_ADDR (REGS_CLKCTRL_BASE + 0xC0)
49HW_REGISTER(HW_CLKCTRL_SAIF, REGS_CLKCTRL_BASE, 0xC0)
50#define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + 0xD0)
51HW_REGISTER(HW_CLKCTRL_FRAC, REGS_CLKCTRL_BASE, 0xD0)
52#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
53#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
54#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
55#define BP_CLKCTRL_FRAC_IOFRAC 24
56#define BF_CLKCTRL_FRAC_IOFRAC(v) \
57 (((v) << BP_CLKCTRL_FRAC_IOFRAC) & BM_CLKCTRL_FRAC_IOFRAC)
58#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 63#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
59#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 64
60#define BP_CLKCTRL_FRAC_PIXFRAC 16 65#define HW_CLKCTRL_CLKSEQ 0xE0
61#define BF_CLKCTRL_FRAC_PIXFRAC(v) \ 66#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
62 (((v) << BP_CLKCTRL_FRAC_PIXFRAC) & BM_CLKCTRL_FRAC_PIXFRAC) 67
63#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000 68#define HW_CLKCTRL_RESET 0xF0
64#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 69#define BM_CLKCTRL_RESET_DIG 0x00000001
65#define BP_CLKCTRL_FRAC_EMIFRAC 8 70#define BP_CLKCTRL_RESET_DIG 0
66#define BF_CLKCTRL_FRAC_EMIFRAC(v) \ 71
67 (((v) << BP_CLKCTRL_FRAC_EMIFRAC) & BM_CLKCTRL_FRAC_EMIFRAC) 72#endif
68#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080
69#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
70#define BP_CLKCTRL_FRAC_CPUFRAC 0
71#define BF_CLKCTRL_FRAC_CPUFRAC(v) \
72 (((v) << BP_CLKCTRL_FRAC_CPUFRAC) & BM_CLKCTRL_FRAC_CPUFRAC)
73#define HW_CLKCTRL_CLKSEQ_ADDR (REGS_CLKCTRL_BASE + 0xE0)
74HW_REGISTER(HW_CLKCTRL_CLKSEQ, REGS_CLKCTRL_BASE, 0xE0)
75#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
76#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
77#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
78#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
79#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
80#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
81#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
82HW_REGISTER_WO(HW_CLKCTRL_RESET, REGS_CLKCTRL_BASE, 0xF0)
83#define BM_CLKCTRL_RESET_CHIP 0x00000002
84#define BM_CLKCTRL_RESET_DIG 0x00000001
85#endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
index 8a92f923f6bd..3b7c92239e20 100644
--- a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
@@ -1,36 +1,43 @@
1/* 1/*
2 * Freescale STMP378X: clock registers definitions 2 * stmp37xx: ICOLL register definitions
3 * 3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com> 4 * Copyright (c) 2008 Freescale Semiconductor
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 * 6 *
15 * http://www.opensource.org/licenses/gpl-license.html 7 * This program is free software; you can redistribute it and/or modify
16 * http://www.gnu.org/copyleft/gpl.html 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 20 */
21#ifndef _MACH_REGS_ICOLL
22#define _MACH_REGS_ICOLL
23
24#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
18 25
19#ifndef _INCLUDE_ASM_ARCH_REGS_ICOLL_H 26#define HW_ICOLL_VECTOR 0x0
20#define _INCLUDE_ASM_ARCH_REGS_ICOLL_H
21 27
28#define HW_ICOLL_LEVELACK 0x10
22 29
23#include <mach/stmp3xxx_regs.h> 30#define HW_ICOLL_CTRL 0x20
31#define BM_ICOLL_CTRL_CLKGATE 0x40000000
32#define BM_ICOLL_CTRL_SFTRST 0x80000000
24 33
25#define REGS_ICOLL_BASE (REGS_BASE + 0x00000000) 34#define HW_ICOLL_STAT 0x30
26 35
27HW_REGISTER(HW_ICOLL_VECTOR, REGS_ICOLL_BASE, 0x00) 36#define HW_ICOLL_PRIORITY0 (0x60 + 0 * 0x10)
28HW_REGISTER_WO(HW_ICOLL_LEVELACK, REGS_ICOLL_BASE, 0x10) 37#define HW_ICOLL_PRIORITY1 (0x60 + 1 * 0x10)
29HW_REGISTER(HW_ICOLL_CTRL, REGS_ICOLL_BASE, 0x20) 38#define HW_ICOLL_PRIORITY2 (0x60 + 2 * 0x10)
30#define BM_ICOLL_CTRL_CLKGATE 0x40000000 39#define HW_ICOLL_PRIORITY3 (0x60 + 3 * 0x10)
31#define BM_ICOLL_CTRL_SFTRST 0x80000000
32HW_REGISTER_RO(HW_ICOLL_STAT, REGS_ICOLL_BASE, 0x30)
33 40
34HW_REGISTER_INDEXED(HW_ICOLL_PRIORITYn, REGS_ICOLL_BASE, 0x60, 0x10) 41#define HW_ICOLL_PRIORITYn 0x60
35 42
36#endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */ 43#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
index b114ecd9a5eb..d5efce2388c7 100644
--- a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
@@ -1,7 +1,8 @@
1/* 1/*
2 * STMP pinmux register definitions 2 * stmp37xx: PINCTRL register definitions
3 * 3 *
4 * Copyright (c) 2008 Freescale Semiconductor 4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
@@ -17,143 +18,71 @@
17 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 20 */
20#ifndef _INCLUDE_ASM_ARCH_REGS_PINCTRL_H 21#ifndef _MACH_REGS_PINCTRL
21#define _INCLUDE_ASM_ARCH_REGS_PINCTRL_H 22#define _MACH_REGS_PINCTRL
22 23
23#include <mach/stmp3xxx_regs.h> 24#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
24 25
25#ifndef REGS_PINCTRL_BASE 26#define HW_PINCTRL_MUXSEL0 0x100
26#define REGS_PINCTRL_BASE (REGS_BASE + 0x00018000) 27#define HW_PINCTRL_MUXSEL1 0x110
27#endif /* REGS_PINCTRL_BASE */ 28#define HW_PINCTRL_MUXSEL2 0x120
28 29#define HW_PINCTRL_MUXSEL3 0x130
29HW_REGISTER(HW_PINCTRL_CTRL, REGS_PINCTRL_BASE, 0) 30#define HW_PINCTRL_MUXSEL4 0x140
30 31#define HW_PINCTRL_MUXSEL5 0x150
31#define HW_PINCTRL_MUXSEL0_ADDR (REGS_PINCTRL_BASE + 0x100) 32#define HW_PINCTRL_MUXSEL6 0x160
32HW_REGISTER(HW_PINCTRL_MUXSEL0, REGS_PINCTRL_BASE, 0x100) 33#define HW_PINCTRL_MUXSEL7 0x170
33#define HW_PINCTRL_MUXSEL1_ADDR (REGS_PINCTRL_BASE + 0x110) 34
34HW_REGISTER(HW_PINCTRL_MUXSEL1, REGS_PINCTRL_BASE, 0x110) 35#define HW_PINCTRL_DRIVE0 0x200
35#define HW_PINCTRL_MUXSEL2_ADDR (REGS_PINCTRL_BASE + 0x120) 36#define HW_PINCTRL_DRIVE1 0x210
36HW_REGISTER(HW_PINCTRL_MUXSEL2, REGS_PINCTRL_BASE, 0x120) 37#define HW_PINCTRL_DRIVE2 0x220
37#define HW_PINCTRL_MUXSEL3_ADDR (REGS_PINCTRL_BASE + 0x130) 38#define HW_PINCTRL_DRIVE3 0x230
38HW_REGISTER(HW_PINCTRL_MUXSEL3, REGS_PINCTRL_BASE, 0x130) 39#define HW_PINCTRL_DRIVE4 0x240
39#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000 40#define HW_PINCTRL_DRIVE5 0x250
40#define HW_PINCTRL_MUXSEL4_ADDR (REGS_PINCTRL_BASE + 0x140) 41#define HW_PINCTRL_DRIVE6 0x260
41HW_REGISTER(HW_PINCTRL_MUXSEL4, REGS_PINCTRL_BASE, 0x140) 42#define HW_PINCTRL_DRIVE7 0x270
42#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0 43#define HW_PINCTRL_DRIVE8 0x280
43#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300 44#define HW_PINCTRL_DRIVE9 0x290
44#define HW_PINCTRL_MUXSEL5_ADDR (REGS_PINCTRL_BASE + 0x150) 45#define HW_PINCTRL_DRIVE10 0x2A0
45HW_REGISTER(HW_PINCTRL_MUXSEL5, REGS_PINCTRL_BASE, 0x150) 46#define HW_PINCTRL_DRIVE11 0x2B0
46#define HW_PINCTRL_MUXSEL6_ADDR (REGS_PINCTRL_BASE + 0x160) 47#define HW_PINCTRL_DRIVE12 0x2C0
47HW_REGISTER(HW_PINCTRL_MUXSEL6, REGS_PINCTRL_BASE, 0x160) 48#define HW_PINCTRL_DRIVE13 0x2D0
48#define HW_PINCTRL_MUXSEL7_ADDR (REGS_PINCTRL_BASE + 0x170) 49#define HW_PINCTRL_DRIVE14 0x2E0
49HW_REGISTER(HW_PINCTRL_MUXSEL7, REGS_PINCTRL_BASE, 0x170) 50
50 51#define HW_PINCTRL_PULL0 0x300
51HW_REGISTER(HW_PINCTRL_DRIVE0, REGS_PINCTRL_BASE, 0x200) 52#define HW_PINCTRL_PULL1 0x310
52#define HW_PINCTRL_DRIVE0_ADDR (REGS_PINCTRL_BASE + 0x200) 53#define HW_PINCTRL_PULL2 0x320
53HW_REGISTER(HW_PINCTRL_DRIVE1, REGS_PINCTRL_BASE, 0x210) 54#define HW_PINCTRL_PULL3 0x330
54#define HW_PINCTRL_DRIVE1_ADDR (REGS_PINCTRL_BASE + 0x210) 55
55HW_REGISTER(HW_PINCTRL_DRIVE2, REGS_PINCTRL_BASE, 0x220) 56#define HW_PINCTRL_DOUT0 0x400
56#define HW_PINCTRL_DRIVE2_ADDR (REGS_PINCTRL_BASE + 0x220) 57#define HW_PINCTRL_DOUT1 0x410
57HW_REGISTER(HW_PINCTRL_DRIVE3, REGS_PINCTRL_BASE, 0x230) 58#define HW_PINCTRL_DOUT2 0x420
58#define HW_PINCTRL_DRIVE3_ADDR (REGS_PINCTRL_BASE + 0x230) 59
59HW_REGISTER(HW_PINCTRL_DRIVE4, REGS_PINCTRL_BASE, 0x240) 60#define HW_PINCTRL_DIN0 0x500
60#define HW_PINCTRL_DRIVE4_ADDR (REGS_PINCTRL_BASE + 0x240) 61#define HW_PINCTRL_DIN1 0x510
61HW_REGISTER(HW_PINCTRL_DRIVE5, REGS_PINCTRL_BASE, 0x250) 62#define HW_PINCTRL_DIN2 0x520
62#define HW_PINCTRL_DRIVE5_ADDR (REGS_PINCTRL_BASE + 0x250) 63
63HW_REGISTER(HW_PINCTRL_DRIVE6, REGS_PINCTRL_BASE, 0x260) 64#define HW_PINCTRL_DOE0 0x600
64#define HW_PINCTRL_DRIVE6_ADDR (REGS_PINCTRL_BASE + 0x260) 65#define HW_PINCTRL_DOE1 0x610
65HW_REGISTER(HW_PINCTRL_DRIVE7, REGS_PINCTRL_BASE, 0x270) 66#define HW_PINCTRL_DOE2 0x620
66#define HW_PINCTRL_DRIVE7_ADDR (REGS_PINCTRL_BASE + 0x270) 67
67HW_REGISTER(HW_PINCTRL_DRIVE8, REGS_PINCTRL_BASE, 0x280) 68#define HW_PINCTRL_PIN2IRQ0 0x700
68#define HW_PINCTRL_DRIVE8_ADDR (REGS_PINCTRL_BASE + 0x280) 69#define HW_PINCTRL_PIN2IRQ1 0x710
69HW_REGISTER(HW_PINCTRL_DRIVE9, REGS_PINCTRL_BASE, 0x290) 70#define HW_PINCTRL_PIN2IRQ2 0x720
70#define HW_PINCTRL_DRIVE9_ADDR (REGS_PINCTRL_BASE + 0x290) 71
71HW_REGISTER(HW_PINCTRL_DRIVE10, REGS_PINCTRL_BASE, 0x2a0) 72#define HW_PINCTRL_IRQEN0 0x800
72#define HW_PINCTRL_DRIVE10_ADDR (REGS_PINCTRL_BASE + 0x2a0) 73#define HW_PINCTRL_IRQEN1 0x810
73HW_REGISTER(HW_PINCTRL_DRIVE11, REGS_PINCTRL_BASE, 0x2b0) 74#define HW_PINCTRL_IRQEN2 0x820
74#define HW_PINCTRL_DRIVE11_ADDR (REGS_PINCTRL_BASE + 0x2b0) 75
75HW_REGISTER(HW_PINCTRL_DRIVE12, REGS_PINCTRL_BASE, 0x2c0) 76#define HW_PINCTRL_IRQLEVEL0 0x900
76#define HW_PINCTRL_DRIVE12_ADDR (REGS_PINCTRL_BASE + 0x2c0) 77#define HW_PINCTRL_IRQLEVEL1 0x910
77HW_REGISTER(HW_PINCTRL_DRIVE13, REGS_PINCTRL_BASE, 0x2d0) 78#define HW_PINCTRL_IRQLEVEL2 0x920
78#define HW_PINCTRL_DRIVE13_ADDR (REGS_PINCTRL_BASE + 0x2d0) 79
79HW_REGISTER(HW_PINCTRL_DRIVE14, REGS_PINCTRL_BASE, 0x2e0) 80#define HW_PINCTRL_IRQPOL0 0xA00
80#define HW_PINCTRL_DRIVE14_ADDR (REGS_PINCTRL_BASE + 0x2e0) 81#define HW_PINCTRL_IRQPOL1 0xA10
81 82#define HW_PINCTRL_IRQPOL2 0xA20
82 83
83HW_REGISTER(HW_PINCTRL_PULL0, REGS_PINCTRL_BASE, 0x300) 84#define HW_PINCTRL_IRQSTAT0 0xB00
84#define HW_PINCTRL_PULL0_ADDR (REGS_PINCTRL_BASE + 0x300) 85#define HW_PINCTRL_IRQSTAT1 0xB10
85#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002 86#define HW_PINCTRL_IRQSTAT2 0xB20
86#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004 87
87#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008 88#endif
88#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010
89#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000
90HW_REGISTER(HW_PINCTRL_PULL1, REGS_PINCTRL_BASE, 0x310)
91#define HW_PINCTRL_PULL1_ADDR (REGS_PINCTRL_BASE + 0x310)
92#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000
93#define BM_PINCTRL_PULL1_BANK1_PIN24 0x01000000
94#define BM_PINCTRL_PULL1_BANK1_PIN25 0x02000000
95#define BM_PINCTRL_PULL1_BANK1_PIN26 0x04000000
96#define BM_PINCTRL_PULL1_BANK1_PIN27 0x08000000
97HW_REGISTER(HW_PINCTRL_PULL2, REGS_PINCTRL_BASE, 0x320)
98#define HW_PINCTRL_PULL2_ADDR (REGS_PINCTRL_BASE + 0x320)
99HW_REGISTER(HW_PINCTRL_PULL3, REGS_PINCTRL_BASE, 0x330)
100#define HW_PINCTRL_PULL3_ADDR (REGS_PINCTRL_BASE + 0x330)
101
102#define HW_PINCTRL_DOUT0_ADDR (REGS_PINCTRL_BASE + 0x400)
103HW_REGISTER(HW_PINCTRL_DOUT0, REGS_PINCTRL_BASE, 0x400)
104#define HW_PINCTRL_DOUT1_ADDR (REGS_PINCTRL_BASE + 0x410)
105HW_REGISTER(HW_PINCTRL_DOUT1, REGS_PINCTRL_BASE, 0x410)
106#define HW_PINCTRL_DOUT2_ADDR (REGS_PINCTRL_BASE + 0x420)
107HW_REGISTER(HW_PINCTRL_DOUT2, REGS_PINCTRL_BASE, 0x420)
108
109#define HW_PINCTRL_DIN0_ADDR (REGS_PINCTRL_BASE + 0x500)
110HW_REGISTER_RO(HW_PINCTRL_DIN0, REGS_PINCTRL_BASE, 0x500)
111#define HW_PINCTRL_DIN1_ADDR (REGS_PINCTRL_BASE + 0x510)
112HW_REGISTER_RO(HW_PINCTRL_DIN1, REGS_PINCTRL_BASE, 0x510)
113#define HW_PINCTRL_DIN2_ADDR (REGS_PINCTRL_BASE + 0x520)
114HW_REGISTER_RO(HW_PINCTRL_DIN2, REGS_PINCTRL_BASE, 0x520)
115
116#define HW_PINCTRL_DOE0_ADDR (REGS_PINCTRL_BASE + 0x600)
117HW_REGISTER(HW_PINCTRL_DOE0, REGS_PINCTRL_BASE, 0x600)
118#define HW_PINCTRL_DOE1_ADDR (REGS_PINCTRL_BASE + 0x610)
119HW_REGISTER(HW_PINCTRL_DOE1, REGS_PINCTRL_BASE, 0x610)
120#define HW_PINCTRL_DOE2_ADDR (REGS_PINCTRL_BASE + 0x620)
121HW_REGISTER(HW_PINCTRL_DOE2, REGS_PINCTRL_BASE, 0x620)
122
123HW_REGISTER(HW_PINCTRL_PIN2IRQ0, REGS_PINCTRL_BASE, 0x700)
124#define HW_PINCTRL_PIN2IRQ0_ADDR (REGS_PINCTRL_BASE + 0x700)
125HW_REGISTER(HW_PINCTRL_PIN2IRQ1, REGS_PINCTRL_BASE, 0x710)
126#define HW_PINCTRL_PIN2IRQ1_ADDR (REGS_PINCTRL_BASE + 0x710)
127HW_REGISTER(HW_PINCTRL_PIN2IRQ2, REGS_PINCTRL_BASE, 0x720)
128#define HW_PINCTRL_PIN2IRQ2_ADDR (REGS_PINCTRL_BASE + 0x720)
129
130HW_REGISTER(HW_PINCTRL_IRQEN0, REGS_PINCTRL_BASE, 0x800)
131#define HW_PINCTRL_IRQEN0_ADDR (REGS_PINCTRL_BASE + 0x800)
132HW_REGISTER(HW_PINCTRL_IRQEN1, REGS_PINCTRL_BASE, 0x810)
133#define HW_PINCTRL_IRQEN1_ADDR (REGS_PINCTRL_BASE + 0x810)
134HW_REGISTER(HW_PINCTRL_IRQEN2, REGS_PINCTRL_BASE, 0x820)
135#define HW_PINCTRL_IRQEN2_ADDR (REGS_PINCTRL_BASE + 0x820)
136
137HW_REGISTER(HW_PINCTRL_IRQLEVEL0, REGS_PINCTRL_BASE, 0x900)
138#define HW_PINCTRL_IRQLEVEL0_ADDR (REGS_PINCTRL_BASE + 0x900)
139HW_REGISTER(HW_PINCTRL_IRQLEVEL1, REGS_PINCTRL_BASE, 0x910)
140#define HW_PINCTRL_IRQLEVEL1_ADDR (REGS_PINCTRL_BASE + 0x910)
141HW_REGISTER(HW_PINCTRL_IRQLEVEL2, REGS_PINCTRL_BASE, 0x920)
142#define HW_PINCTRL_IRQLEVEL2_ADDR (REGS_PINCTRL_BASE + 0x920)
143
144HW_REGISTER(HW_PINCTRL_IRQPOL0, REGS_PINCTRL_BASE, 0xA00)
145#define HW_PINCTRL_IRQPOL0_ADDR (REGS_PINCTRL_BASE + 0xa00)
146HW_REGISTER(HW_PINCTRL_IRQPOL1, REGS_PINCTRL_BASE, 0xA10)
147#define HW_PINCTRL_IRQPOL1_ADDR (REGS_PINCTRL_BASE + 0xa10)
148HW_REGISTER(HW_PINCTRL_IRQPOL2, REGS_PINCTRL_BASE, 0xA20)
149#define HW_PINCTRL_IRQPOL2_ADDR (REGS_PINCTRL_BASE + 0xa20)
150
151HW_REGISTER(HW_PINCTRL_IRQSTAT0, REGS_PINCTRL_BASE, 0xB00)
152#define HW_PINCTRL_IRQSTAT0_ADDR (REGS_PINCTRL_BASE + 0xb00)
153HW_REGISTER(HW_PINCTRL_IRQSTAT1, REGS_PINCTRL_BASE, 0xB10)
154#define HW_PINCTRL_IRQSTAT1_ADDR (REGS_PINCTRL_BASE + 0xb10)
155HW_REGISTER(HW_PINCTRL_IRQSTAT2, REGS_PINCTRL_BASE, 0xB20)
156#define HW_PINCTRL_IRQSTAT2_ADDR (REGS_PINCTRL_BASE + 0xb20)
157
158#endif /* _INCLUDE_ASM_ARCH_REGS_PINCTRL_H */
159
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-power.h b/arch/arm/mach-stmp37xx/include/mach/regs-power.h
index d15cd6601e7f..0e733d74a229 100644
--- a/arch/arm/mach-stmp37xx/include/mach/regs-power.h
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-power.h
@@ -1,7 +1,8 @@
1/* 1/*
2 * STMP POWER Register Definitions 2 * stmp37xx: POWER register definitions
3 * 3 *
4 * Copyright (c) 2008 Freescale Semiconductor 4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
@@ -17,15 +18,39 @@
17 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 20 */
21#ifndef _MACH_REGS_POWER
22#define _MACH_REGS_POWER
20 23
21#ifndef __ARCH_ARM___POWER_H 24#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
22#define __ARCH_ARM___POWER_H 1
23 25
24#include <mach/stmp3xxx_regs.h> 26#define HW_POWER_CTRL 0x0
27#define BM_POWER_CTRL_CLKGATE 0x40000000
25 28
26#define REGS_POWER_BASE (void __iomem *)(REGS_BASE + 0x44000) 29#define HW_POWER_5VCTRL 0x10
27#define REGS_POWER_BASE_PHYS (0x80044000) 30
28#define REGS_POWER_SIZE 0x00002000 31#define HW_POWER_MINPWR 0x20
29HW_REGISTER(HW_POWER_MINPWR, REGS_POWER_BASE, 0x00000020) 32
30HW_REGISTER(HW_POWER_CHARGE, REGS_POWER_BASE, 0x00000030) 33#define HW_POWER_CHARGE 0x30
31#endif /* __ARCH_ARM___POWER_H */ 34
35#define HW_POWER_VDDDCTRL 0x40
36
37#define HW_POWER_VDDACTRL 0x50
38
39#define HW_POWER_VDDIOCTRL 0x60
40#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
41#define BP_POWER_VDDIOCTRL_TRG 0
42
43#define HW_POWER_STS 0xB0
44#define BM_POWER_STS_VBUSVALID 0x00000002
45#define BM_POWER_STS_BVALID 0x00000004
46#define BM_POWER_STS_AVALID 0x00000008
47#define BM_POWER_STS_DC_OK 0x00000100
48
49#define HW_POWER_RESET 0xE0
50
51#define HW_POWER_DEBUG 0xF0
52#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
53#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
54#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
55
56#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
index 7f000306e890..4af0f6edfa78 100644
--- a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * include/asm-arm/arch-stmp3xxx/regstimer.h 2 * stmp37xx: TIMROT register definitions
3 * 3 *
4 * Copyright (c) 2008 SigmaTel Inc 4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright (c) 2008 Embedded Alley Solutions, Inc 5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
@@ -16,37 +16,34 @@
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21#ifndef __ARCH_ARM_REGS_TIMROT_H 21#ifndef _MACH_REGS_TIMROT
22#define __ARCH_ARM_REGS_TIMROT_H 22#define _MACH_REGS_TIMROT
23 23
24#include <mach/stmp3xxx_regs.h> 24#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
25 25
26#define REGS_TIMROT_BASE (REGS_BASE + 0x00068000) 26#define HW_TIMROT_ROTCTRL 0x0
27#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
28#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
27 29
28HW_REGISTER(HW_TIMROT_ROTCTRL, REGS_TIMROT_BASE, 0) 30#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
29#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 31#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
30#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 32#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
31 33
32HW_REGISTER_INDEXED(HW_TIMROT_TIMCTRLn, REGS_TIMROT_BASE, 0x20, 0x20) 34#define HW_TIMROT_TIMCTRLn 0x20
33#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F 35#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
34#define BF_TIMROT_TIMCTRLn_SELECT(v) (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) 36#define BP_TIMROT_TIMCTRLn_SELECT 0
35#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 37#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
36#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ 38#define BP_TIMROT_TIMCTRLn_PRESCALE 4
37 (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) 39#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
38#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 40#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
39#define BF_TIMROT_TIMCTRLn_RELOAD(v) (((v) << 6) & BM_TIMROT_TIMCTRLn_RELOAD) 41#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
40#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 42#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
41#define BF_TIMROT_TIMCTRLn_UPDATE(v) (((v) << 7) & BM_TIMROT_TIMCTRLn_UPDATE)
42#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100
43#define BF_TIMROT_TIMCTRLn_POLARITY(v) \
44 (((v) << 8) & BM_TIMROT_TIMCTRLn_POLARITY)
45#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
46#define BF_TIMROT_TIMCTRLn_IRQ_EN(v) \
47 (((v) << 14) & BM_TIMROT_TIMCTRLn_IRQ_EN)
48#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
49#define BF_TIMROT_TIMCTRLn_IRQ(v) (((v) << 15) & BM_TIMROT_TIMCTRLn_IRQ)
50HW_REGISTER_0_INDEXED(HW_TIMROT_TIMCOUNTn, REGS_TIMROT_BASE, 0x30, 0x20)
51 43
52#endif /* __ARCH_ARM_REGSTIMER_H */ 44#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
45#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
46#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
47
48#define HW_TIMROT_TIMCOUNTn 0x30
49#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-23 02:22:34 -0500