diff options
| -rw-r--r-- | drivers/staging/dt3155/allocator.c | 2 | ||||
| -rw-r--r-- | drivers/staging/dt3155/allocator.h | 2 | ||||
| -rw-r--r-- | drivers/staging/dt3155/dt3155.h | 24 | ||||
| -rw-r--r-- | drivers/staging/dt3155/dt3155_drv.c | 28 | ||||
| -rw-r--r-- | drivers/staging/dt3155/dt3155_io.c | 16 | ||||
| -rw-r--r-- | drivers/staging/dt3155/dt3155_io.h | 174 | ||||
| -rw-r--r-- | drivers/staging/dt3155/dt3155_isr.c | 54 | ||||
| -rw-r--r-- | drivers/staging/dt3155/dt3155_isr.h | 2 |
8 files changed, 151 insertions, 151 deletions
diff --git a/drivers/staging/dt3155/allocator.c b/drivers/staging/dt3155/allocator.c index 114e2a86fefa..c74234c66895 100644 --- a/drivers/staging/dt3155/allocator.c +++ b/drivers/staging/dt3155/allocator.c | |||
| @@ -195,7 +195,7 @@ int allocator_free_dma(unsigned long address) | |||
| 195 | * On cleanup everything is released. If the list is not empty, that a | 195 | * On cleanup everything is released. If the list is not empty, that a |
| 196 | * problem of our clients | 196 | * problem of our clients |
| 197 | */ | 197 | */ |
| 198 | int allocator_init(u64 *allocator_max) | 198 | int allocator_init(u32 *allocator_max) |
| 199 | { | 199 | { |
| 200 | /* check how much free memory is there */ | 200 | /* check how much free memory is there */ |
| 201 | void *remapped; | 201 | void *remapped; |
diff --git a/drivers/staging/dt3155/allocator.h b/drivers/staging/dt3155/allocator.h index 4cd81bdb3faa..bdf3268ca52d 100644 --- a/drivers/staging/dt3155/allocator.h +++ b/drivers/staging/dt3155/allocator.h | |||
| @@ -24,5 +24,5 @@ | |||
| 24 | 24 | ||
| 25 | void allocator_free_dma(unsigned long address); | 25 | void allocator_free_dma(unsigned long address); |
| 26 | unsigned long allocator_allocate_dma(unsigned long kilobytes, int priority); | 26 | unsigned long allocator_allocate_dma(unsigned long kilobytes, int priority); |
| 27 | int allocator_init(u64 *); | 27 | int allocator_init(u32 *); |
| 28 | void allocator_cleanup(void); | 28 | void allocator_cleanup(void); |
diff --git a/drivers/staging/dt3155/dt3155.h b/drivers/staging/dt3155/dt3155.h index 22292b102a33..1bf786364eec 100644 --- a/drivers/staging/dt3155/dt3155.h +++ b/drivers/staging/dt3155/dt3155.h | |||
| @@ -79,8 +79,8 @@ struct dt3155_config_s { | |||
| 79 | 79 | ||
| 80 | /* hold data for each frame */ | 80 | /* hold data for each frame */ |
| 81 | typedef struct { | 81 | typedef struct { |
| 82 | u64 addr; /* address of the buffer with the frame */ | 82 | u32 addr; /* address of the buffer with the frame */ |
| 83 | u64 tag; /* unique number for the frame */ | 83 | u32 tag; /* unique number for the frame */ |
| 84 | struct timeval time; /* time that capture took place */ | 84 | struct timeval time; /* time that capture took place */ |
| 85 | } frame_info_t; | 85 | } frame_info_t; |
| 86 | 86 | ||
| @@ -101,14 +101,14 @@ struct dt3155_fbuffer_s { | |||
| 101 | int locked_buf; /* Buffers used by user */ | 101 | int locked_buf; /* Buffers used by user */ |
| 102 | 102 | ||
| 103 | int ready_que[BOARD_MAX_BUFFS]; | 103 | int ready_que[BOARD_MAX_BUFFS]; |
| 104 | u64 ready_head; /* The most recent buffer located here */ | 104 | u32 ready_head; /* The most recent buffer located here */ |
| 105 | u64 ready_len; /* The number of ready buffers */ | 105 | u32 ready_len; /* The number of ready buffers */ |
| 106 | 106 | ||
| 107 | int even_happened; | 107 | int even_happened; |
| 108 | int even_stopped; | 108 | int even_stopped; |
| 109 | 109 | ||
| 110 | int stop_acquire; /* Flag to stop interrupts */ | 110 | int stop_acquire; /* Flag to stop interrupts */ |
| 111 | u64 frame_count; /* Counter for frames acquired by this card */ | 111 | u32 frame_count; /* Counter for frames acquired by this card */ |
| 112 | }; | 112 | }; |
| 113 | 113 | ||
| 114 | 114 | ||
| @@ -122,13 +122,13 @@ struct dt3155_fbuffer_s { | |||
| 122 | /* There is one status structure for each card. */ | 122 | /* There is one status structure for each card. */ |
| 123 | typedef struct dt3155_status_s { | 123 | typedef struct dt3155_status_s { |
| 124 | int fixed_mode; /* if 1, we are in fixed frame mode */ | 124 | int fixed_mode; /* if 1, we are in fixed frame mode */ |
| 125 | u64 reg_addr; /* Register address for a single card */ | 125 | u32 reg_addr; /* Register address for a single card */ |
| 126 | u64 mem_addr; /* Buffer start addr for this card */ | 126 | u32 mem_addr; /* Buffer start addr for this card */ |
| 127 | u64 mem_size; /* This is the amount of mem available */ | 127 | u32 mem_size; /* This is the amount of mem available */ |
| 128 | u32 irq; /* this card's irq */ | 128 | u32 irq; /* this card's irq */ |
| 129 | struct dt3155_config_s config; /* configuration struct */ | 129 | struct dt3155_config_s config; /* configuration struct */ |
| 130 | struct dt3155_fbuffer_s fbuffer; /* frame buffer state struct */ | 130 | struct dt3155_fbuffer_s fbuffer; /* frame buffer state struct */ |
| 131 | u64 state; /* this card's state */ | 131 | u32 state; /* this card's state */ |
| 132 | u32 device_installed; /* Flag if installed. 1=installed */ | 132 | u32 device_installed; /* Flag if installed. 1=installed */ |
| 133 | } dt3155_status_t; | 133 | } dt3155_status_t; |
| 134 | 134 | ||
| @@ -161,9 +161,9 @@ extern struct dt3155_status_s dt3155_status[MAXBOARDS]; | |||
| 161 | 161 | ||
| 162 | /* User code will probably want to declare one of these for each card */ | 162 | /* User code will probably want to declare one of these for each card */ |
| 163 | typedef struct dt3155_read_s { | 163 | typedef struct dt3155_read_s { |
| 164 | u64 offset; | 164 | u32 offset; |
| 165 | u64 frame_seq; | 165 | u32 frame_seq; |
| 166 | u64 state; | 166 | u32 state; |
| 167 | 167 | ||
| 168 | frame_info_t frame_info; | 168 | frame_info_t frame_info; |
| 169 | } dt3155_read_t; | 169 | } dt3155_read_t; |
diff --git a/drivers/staging/dt3155/dt3155_drv.c b/drivers/staging/dt3155/dt3155_drv.c index 930a3e666c0a..a67c622869d2 100644 --- a/drivers/staging/dt3155/dt3155_drv.c +++ b/drivers/staging/dt3155/dt3155_drv.c | |||
| @@ -137,7 +137,7 @@ u32 dt3155_dev_open[ MAXBOARDS ] = {0 | |||
| 137 | }; | 137 | }; |
| 138 | 138 | ||
| 139 | u32 ndevices = 0; | 139 | u32 ndevices = 0; |
| 140 | u64 unique_tag = 0;; | 140 | u32 unique_tag = 0;; |
| 141 | 141 | ||
| 142 | 142 | ||
| 143 | /* | 143 | /* |
| @@ -180,7 +180,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) | |||
| 180 | int minor = -1; | 180 | int minor = -1; |
| 181 | int index; | 181 | int index; |
| 182 | unsigned long flags; | 182 | unsigned long flags; |
| 183 | u64 buffer_addr; | 183 | u32 buffer_addr; |
| 184 | 184 | ||
| 185 | /* find out who issued the interrupt */ | 185 | /* find out who issued the interrupt */ |
| 186 | for ( index = 0; index < ndevices; index++ ) { | 186 | for ( index = 0; index < ndevices; index++ ) { |
| @@ -249,7 +249,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) | |||
| 249 | { | 249 | { |
| 250 | /* GCS (Aug 2, 2002) -- In field mode, dma the odd field | 250 | /* GCS (Aug 2, 2002) -- In field mode, dma the odd field |
| 251 | into the lower half of the buffer */ | 251 | into the lower half of the buffer */ |
| 252 | const u64 stride = dt3155_status[ minor ].config.cols; | 252 | const u32 stride = dt3155_status[ minor ].config.cols; |
| 253 | buffer_addr = dt3155_fbuffer[ minor ]-> | 253 | buffer_addr = dt3155_fbuffer[ minor ]-> |
| 254 | frame_info[ dt3155_fbuffer[ minor ]->active_buf ].addr | 254 | frame_info[ dt3155_fbuffer[ minor ]->active_buf ].addr |
| 255 | + (DT3155_MAX_ROWS / 2) * stride; | 255 | + (DT3155_MAX_ROWS / 2) * stride; |
| @@ -312,7 +312,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) | |||
| 312 | dt3155_fbuffer[ minor ]->even_stopped = 0; | 312 | dt3155_fbuffer[ minor ]->even_stopped = 0; |
| 313 | 313 | ||
| 314 | printk(KERN_DEBUG "dt3155: state is now %x\n", | 314 | printk(KERN_DEBUG "dt3155: state is now %x\n", |
| 315 | (u32)dt3155_status[minor].state); | 315 | dt3155_status[minor].state); |
| 316 | } | 316 | } |
| 317 | else | 317 | else |
| 318 | { | 318 | { |
| @@ -428,7 +428,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) | |||
| 428 | *****************************************************/ | 428 | *****************************************************/ |
| 429 | static void dt3155_init_isr(int minor) | 429 | static void dt3155_init_isr(int minor) |
| 430 | { | 430 | { |
| 431 | const u64 stride = dt3155_status[ minor ].config.cols; | 431 | const u32 stride = dt3155_status[ minor ].config.cols; |
| 432 | 432 | ||
| 433 | switch (dt3155_status[ minor ].state & DT3155_STATE_MODE) | 433 | switch (dt3155_status[ minor ].state & DT3155_STATE_MODE) |
| 434 | { | 434 | { |
| @@ -706,7 +706,7 @@ static int dt3155_open( struct inode* inode, struct file* filep) | |||
| 706 | 706 | ||
| 707 | if (dt3155_status[ minor ].state != DT3155_STATE_IDLE) { | 707 | if (dt3155_status[ minor ].state != DT3155_STATE_IDLE) { |
| 708 | printk ("DT3155: Not in idle state (state = %x)\n", | 708 | printk ("DT3155: Not in idle state (state = %x)\n", |
| 709 | (u32)dt3155_status[ minor ].state); | 709 | dt3155_status[ minor ].state); |
| 710 | return -EBUSY; | 710 | return -EBUSY; |
| 711 | } | 711 | } |
| 712 | 712 | ||
| @@ -762,7 +762,7 @@ static ssize_t dt3155_read(struct file *filep, char __user *buf, | |||
| 762 | { | 762 | { |
| 763 | /* which device are we reading from? */ | 763 | /* which device are we reading from? */ |
| 764 | int minor = MINOR(filep->f_dentry->d_inode->i_rdev); | 764 | int minor = MINOR(filep->f_dentry->d_inode->i_rdev); |
| 765 | u64 offset; | 765 | u32 offset; |
| 766 | int frame_index; | 766 | int frame_index; |
| 767 | frame_info_t *frame_info_p; | 767 | frame_info_t *frame_info_p; |
| 768 | 768 | ||
| @@ -820,11 +820,11 @@ static ssize_t dt3155_read(struct file *filep, char __user *buf, | |||
| 820 | offset = frame_info_p->addr - dt3155_status[minor].mem_addr; | 820 | offset = frame_info_p->addr - dt3155_status[minor].mem_addr; |
| 821 | 821 | ||
| 822 | put_user(offset, (unsigned int *) buf); | 822 | put_user(offset, (unsigned int *) buf); |
| 823 | buf += sizeof(u64); | 823 | buf += sizeof(u32); |
| 824 | put_user( dt3155_status[minor].fbuffer.frame_count, (unsigned int *) buf); | 824 | put_user( dt3155_status[minor].fbuffer.frame_count, (unsigned int *) buf); |
| 825 | buf += sizeof(u64); | 825 | buf += sizeof(u32); |
| 826 | put_user(dt3155_status[minor].state, (unsigned int *) buf); | 826 | put_user(dt3155_status[minor].state, (unsigned int *) buf); |
| 827 | buf += sizeof(u64); | 827 | buf += sizeof(u32); |
| 828 | if (copy_to_user(buf, frame_info_p, sizeof(frame_info_t))) | 828 | if (copy_to_user(buf, frame_info_p, sizeof(frame_info_t))) |
| 829 | return -EFAULT; | 829 | return -EFAULT; |
| 830 | 830 | ||
| @@ -931,7 +931,7 @@ static int find_PCI (void) | |||
| 931 | dt3155_status[ pci_index-1 ].device_installed = 1; | 931 | dt3155_status[ pci_index-1 ].device_installed = 1; |
| 932 | printk("DT3155: Installing device %d w/irq %d and address %p\n", | 932 | printk("DT3155: Installing device %d w/irq %d and address %p\n", |
| 933 | pci_index, | 933 | pci_index, |
| 934 | (u32)dt3155_status[pci_index-1].irq, | 934 | dt3155_status[pci_index-1].irq, |
| 935 | dt3155_lbase[pci_index-1]); | 935 | dt3155_lbase[pci_index-1]); |
| 936 | 936 | ||
| 937 | } | 937 | } |
| @@ -944,7 +944,7 @@ err: | |||
| 944 | return DT_3155_FAILURE; | 944 | return DT_3155_FAILURE; |
| 945 | } | 945 | } |
| 946 | 946 | ||
| 947 | u64 allocatorAddr = 0; | 947 | u32 allocatorAddr = 0; |
| 948 | 948 | ||
| 949 | /***************************************************** | 949 | /***************************************************** |
| 950 | * init_module() | 950 | * init_module() |
| @@ -1024,9 +1024,9 @@ int init_module(void) | |||
| 1024 | dt3155_status[ index ].config.rows); | 1024 | dt3155_status[ index ].config.rows); |
| 1025 | printk("DT3155: m_addr = 0x%x; m_size = %ld; " | 1025 | printk("DT3155: m_addr = 0x%x; m_size = %ld; " |
| 1026 | "state = %d; device_installed = %d\n", | 1026 | "state = %d; device_installed = %d\n", |
| 1027 | (u32)dt3155_status[ index ].mem_addr, | 1027 | dt3155_status[ index ].mem_addr, |
| 1028 | (long int)dt3155_status[ index ].mem_size, | 1028 | (long int)dt3155_status[ index ].mem_size, |
| 1029 | (u32)dt3155_status[ index ].state, | 1029 | dt3155_status[ index ].state, |
| 1030 | dt3155_status[ index ].device_installed); | 1030 | dt3155_status[ index ].device_installed); |
| 1031 | } | 1031 | } |
| 1032 | 1032 | ||
diff --git a/drivers/staging/dt3155/dt3155_io.c b/drivers/staging/dt3155/dt3155_io.c index 1c15604f4313..6b9c68501a61 100644 --- a/drivers/staging/dt3155/dt3155_io.c +++ b/drivers/staging/dt3155/dt3155_io.c | |||
| @@ -27,12 +27,12 @@ | |||
| 27 | 27 | ||
| 28 | 28 | ||
| 29 | /****** local copies of board's 32 bit registers ******/ | 29 | /****** local copies of board's 32 bit registers ******/ |
| 30 | u64 even_dma_start_r; /* bit 0 should always be 0 */ | 30 | u32 even_dma_start_r; /* bit 0 should always be 0 */ |
| 31 | u64 odd_dma_start_r; /* .. */ | 31 | u32 odd_dma_start_r; /* .. */ |
| 32 | u64 even_dma_stride_r; /* bits 0&1 should always be 0 */ | 32 | u32 even_dma_stride_r; /* bits 0&1 should always be 0 */ |
| 33 | u64 odd_dma_stride_r; /* .. */ | 33 | u32 odd_dma_stride_r; /* .. */ |
| 34 | u64 even_pixel_fmt_r; | 34 | u32 even_pixel_fmt_r; |
| 35 | u64 odd_pixel_fmt_r; | 35 | u32 odd_pixel_fmt_r; |
| 36 | 36 | ||
| 37 | FIFO_TRIGGER_R fifo_trigger_r; | 37 | FIFO_TRIGGER_R fifo_trigger_r; |
| 38 | XFER_MODE_R xfer_mode_r; | 38 | XFER_MODE_R xfer_mode_r; |
| @@ -40,8 +40,8 @@ CSR1_R csr1_r; | |||
| 40 | RETRY_WAIT_CNT_R retry_wait_cnt_r; | 40 | RETRY_WAIT_CNT_R retry_wait_cnt_r; |
| 41 | INT_CSR_R int_csr_r; | 41 | INT_CSR_R int_csr_r; |
| 42 | 42 | ||
| 43 | u64 even_fld_mask_r; | 43 | u32 even_fld_mask_r; |
| 44 | u64 odd_fld_mask_r; | 44 | u32 odd_fld_mask_r; |
| 45 | 45 | ||
| 46 | MASK_LENGTH_R mask_length_r; | 46 | MASK_LENGTH_R mask_length_r; |
| 47 | FIFO_FLAG_CNT_R fifo_flag_cnt_r; | 47 | FIFO_FLAG_CNT_R fifo_flag_cnt_r; |
diff --git a/drivers/staging/dt3155/dt3155_io.h b/drivers/staging/dt3155/dt3155_io.h index a135aada5902..d1a25100169f 100644 --- a/drivers/staging/dt3155/dt3155_io.h +++ b/drivers/staging/dt3155/dt3155_io.h | |||
| @@ -36,8 +36,8 @@ MA 02111-1307 USA | |||
| 36 | 36 | ||
| 37 | /* macros to access registers */ | 37 | /* macros to access registers */ |
| 38 | 38 | ||
| 39 | #define WriteMReg(Address, Data) (*((u64 *)(Address)) = Data) | 39 | #define WriteMReg(Address, Data) (*((u32 *)(Address)) = Data) |
| 40 | #define ReadMReg(Address, Data) (Data = *((u64 *)(Address))) | 40 | #define ReadMReg(Address, Data) (Data = *((u32 *)(Address))) |
| 41 | 41 | ||
| 42 | /***************** 32 bit register globals **************/ | 42 | /***************** 32 bit register globals **************/ |
| 43 | 43 | ||
| @@ -71,114 +71,114 @@ MA 02111-1307 USA | |||
| 71 | /******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/ | 71 | /******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/ |
| 72 | 72 | ||
| 73 | typedef union fifo_trigger_tag { | 73 | typedef union fifo_trigger_tag { |
| 74 | u64 reg; | 74 | u32 reg; |
| 75 | struct { | 75 | struct { |
| 76 | u64 PACKED:6; | 76 | u32 PACKED:6; |
| 77 | u64 :9; | 77 | u32 :9; |
| 78 | u64 PLANER:7; | 78 | u32 PLANER:7; |
| 79 | u64 :9; | 79 | u32 :9; |
| 80 | } fld; | 80 | } fld; |
| 81 | } FIFO_TRIGGER_R; | 81 | } FIFO_TRIGGER_R; |
| 82 | 82 | ||
| 83 | typedef union xfer_mode_tag { | 83 | typedef union xfer_mode_tag { |
| 84 | u64 reg; | 84 | u32 reg; |
| 85 | struct { | 85 | struct { |
| 86 | u64 :2; | 86 | u32 :2; |
| 87 | u64 FIELD_TOGGLE:1; | 87 | u32 FIELD_TOGGLE:1; |
| 88 | u64 :5; | 88 | u32 :5; |
| 89 | u64 :2; | 89 | u32 :2; |
| 90 | u64 :22; | 90 | u32 :22; |
| 91 | } fld; | 91 | } fld; |
| 92 | } XFER_MODE_R; | 92 | } XFER_MODE_R; |
| 93 | 93 | ||
| 94 | typedef union csr1_tag { | 94 | typedef union csr1_tag { |
| 95 | u64 reg; | 95 | u32 reg; |
| 96 | struct { | 96 | struct { |
| 97 | u64 CAP_CONT_EVE:1; | 97 | u32 CAP_CONT_EVE:1; |
| 98 | u64 CAP_CONT_ODD:1; | 98 | u32 CAP_CONT_ODD:1; |
| 99 | u64 CAP_SNGL_EVE:1; | 99 | u32 CAP_SNGL_EVE:1; |
| 100 | u64 CAP_SNGL_ODD:1; | 100 | u32 CAP_SNGL_ODD:1; |
| 101 | u64 FLD_DN_EVE :1; | 101 | u32 FLD_DN_EVE :1; |
| 102 | u64 FLD_DN_ODD :1; | 102 | u32 FLD_DN_ODD :1; |
| 103 | u64 SRST :1; | 103 | u32 SRST :1; |
| 104 | u64 FIFO_EN :1; | 104 | u32 FIFO_EN :1; |
| 105 | u64 FLD_CRPT_EVE:1; | 105 | u32 FLD_CRPT_EVE:1; |
| 106 | u64 FLD_CRPT_ODD:1; | 106 | u32 FLD_CRPT_ODD:1; |
| 107 | u64 ADDR_ERR_EVE:1; | 107 | u32 ADDR_ERR_EVE:1; |
| 108 | u64 ADDR_ERR_ODD:1; | 108 | u32 ADDR_ERR_ODD:1; |
| 109 | u64 CRPT_DIS :1; | 109 | u32 CRPT_DIS :1; |
| 110 | u64 RANGE_EN :1; | 110 | u32 RANGE_EN :1; |
| 111 | u64 :16; | 111 | u32 :16; |
| 112 | } fld; | 112 | } fld; |
| 113 | } CSR1_R; | 113 | } CSR1_R; |
| 114 | 114 | ||
| 115 | typedef union retry_wait_cnt_tag { | 115 | typedef union retry_wait_cnt_tag { |
| 116 | u64 reg; | 116 | u32 reg; |
| 117 | struct { | 117 | struct { |
| 118 | u64 RTRY_WAIT_CNT:8; | 118 | u32 RTRY_WAIT_CNT:8; |
| 119 | u64 :24; | 119 | u32 :24; |
| 120 | } fld; | 120 | } fld; |
| 121 | } RETRY_WAIT_CNT_R; | 121 | } RETRY_WAIT_CNT_R; |
| 122 | 122 | ||
| 123 | typedef union int_csr_tag { | 123 | typedef union int_csr_tag { |
| 124 | u64 reg; | 124 | u32 reg; |
| 125 | struct { | 125 | struct { |
| 126 | u64 FLD_END_EVE :1; | 126 | u32 FLD_END_EVE :1; |
| 127 | u64 FLD_END_ODD :1; | 127 | u32 FLD_END_ODD :1; |
| 128 | u64 FLD_START :1; | 128 | u32 FLD_START :1; |
| 129 | u64 :5; | 129 | u32 :5; |
| 130 | u64 FLD_END_EVE_EN:1; | 130 | u32 FLD_END_EVE_EN:1; |
| 131 | u64 FLD_END_ODD_EN:1; | 131 | u32 FLD_END_ODD_EN:1; |
| 132 | u64 FLD_START_EN :1; | 132 | u32 FLD_START_EN :1; |
| 133 | u64 :21; | 133 | u32 :21; |
| 134 | } fld; | 134 | } fld; |
| 135 | } INT_CSR_R; | 135 | } INT_CSR_R; |
| 136 | 136 | ||
| 137 | typedef union mask_length_tag { | 137 | typedef union mask_length_tag { |
| 138 | u64 reg; | 138 | u32 reg; |
| 139 | struct { | 139 | struct { |
| 140 | u64 MASK_LEN_EVE:5; | 140 | u32 MASK_LEN_EVE:5; |
| 141 | u64 :11; | 141 | u32 :11; |
| 142 | u64 MASK_LEN_ODD:5; | 142 | u32 MASK_LEN_ODD:5; |
| 143 | u64 :11; | 143 | u32 :11; |
| 144 | } fld; | 144 | } fld; |
| 145 | } MASK_LENGTH_R; | 145 | } MASK_LENGTH_R; |
| 146 | 146 | ||
| 147 | typedef union fifo_flag_cnt_tag { | 147 | typedef union fifo_flag_cnt_tag { |
| 148 | u64 reg; | 148 | u32 reg; |
| 149 | struct { | 149 | struct { |
| 150 | u64 AF_COUNT:7; | 150 | u32 AF_COUNT:7; |
| 151 | u64 :9; | 151 | u32 :9; |
| 152 | u64 AE_COUNT:7; | 152 | u32 AE_COUNT:7; |
| 153 | u64 :9; | 153 | u32 :9; |
| 154 | } fld; | 154 | } fld; |
| 155 | } FIFO_FLAG_CNT_R; | 155 | } FIFO_FLAG_CNT_R; |
| 156 | 156 | ||
| 157 | typedef union iic_clk_dur { | 157 | typedef union iic_clk_dur { |
| 158 | u64 reg; | 158 | u32 reg; |
| 159 | struct { | 159 | struct { |
| 160 | u64 PHASE_1:8; | 160 | u32 PHASE_1:8; |
| 161 | u64 PHASE_2:8; | 161 | u32 PHASE_2:8; |
| 162 | u64 PHASE_3:8; | 162 | u32 PHASE_3:8; |
| 163 | u64 PHASE_4:8; | 163 | u32 PHASE_4:8; |
| 164 | } fld; | 164 | } fld; |
| 165 | } IIC_CLK_DUR_R; | 165 | } IIC_CLK_DUR_R; |
| 166 | 166 | ||
| 167 | typedef union iic_csr1_tag { | 167 | typedef union iic_csr1_tag { |
| 168 | u64 reg; | 168 | u32 reg; |
| 169 | struct { | 169 | struct { |
| 170 | u64 AUTO_EN :1; | 170 | u32 AUTO_EN :1; |
| 171 | u64 BYPASS :1; | 171 | u32 BYPASS :1; |
| 172 | u64 SDA_OUT :1; | 172 | u32 SDA_OUT :1; |
| 173 | u64 SCL_OUT :1; | 173 | u32 SCL_OUT :1; |
| 174 | u64 :4; | 174 | u32 :4; |
| 175 | u64 AUTO_ABORT :1; | 175 | u32 AUTO_ABORT :1; |
| 176 | u64 DIRECT_ABORT:1; | 176 | u32 DIRECT_ABORT:1; |
| 177 | u64 SDA_IN :1; | 177 | u32 SDA_IN :1; |
| 178 | u64 SCL_IN :1; | 178 | u32 SCL_IN :1; |
| 179 | u64 :4; | 179 | u32 :4; |
| 180 | u64 AUTO_ADDR :8; | 180 | u32 AUTO_ADDR :8; |
| 181 | u64 RD_DATA :8; | 181 | u32 RD_DATA :8; |
| 182 | } fld; | 182 | } fld; |
| 183 | } IIC_CSR1_R; | 183 | } IIC_CSR1_R; |
| 184 | 184 | ||
| @@ -186,14 +186,14 @@ typedef union iic_csr1_tag { | |||
| 186 | * iic_csr2_tag | 186 | * iic_csr2_tag |
| 187 | */ | 187 | */ |
| 188 | typedef union iic_csr2_tag { | 188 | typedef union iic_csr2_tag { |
| 189 | u64 reg; | 189 | u32 reg; |
| 190 | struct { | 190 | struct { |
| 191 | u64 DIR_WR_DATA :8; | 191 | u32 DIR_WR_DATA :8; |
| 192 | u64 DIR_SUB_ADDR:8; | 192 | u32 DIR_SUB_ADDR:8; |
| 193 | u64 DIR_RD :1; | 193 | u32 DIR_RD :1; |
| 194 | u64 DIR_ADDR :7; | 194 | u32 DIR_ADDR :7; |
| 195 | u64 NEW_CYCLE :1; | 195 | u32 NEW_CYCLE :1; |
| 196 | u64 :7; | 196 | u32 :7; |
| 197 | } fld; | 197 | } fld; |
| 198 | } IIC_CSR2_R; | 198 | } IIC_CSR2_R; |
| 199 | 199 | ||
| @@ -203,10 +203,10 @@ typedef union iic_csr2_tag { | |||
| 203 | * dma_upper_lmt_tag | 203 | * dma_upper_lmt_tag |
| 204 | */ | 204 | */ |
| 205 | typedef union dma_upper_lmt_tag { | 205 | typedef union dma_upper_lmt_tag { |
| 206 | u64 reg; | 206 | u32 reg; |
| 207 | struct { | 207 | struct { |
| 208 | u64 DMA_UPPER_LMT_VAL:24; | 208 | u32 DMA_UPPER_LMT_VAL:24; |
| 209 | u64 :8; | 209 | u32 :8; |
| 210 | } fld; | 210 | } fld; |
| 211 | } DMA_UPPER_LMT_R; | 211 | } DMA_UPPER_LMT_R; |
| 212 | 212 | ||
| @@ -214,12 +214,12 @@ typedef union dma_upper_lmt_tag { | |||
| 214 | /* | 214 | /* |
| 215 | * Global declarations of local copies of boards' 32 bit registers | 215 | * Global declarations of local copies of boards' 32 bit registers |
| 216 | */ | 216 | */ |
| 217 | extern u64 even_dma_start_r; /* bit 0 should always be 0 */ | 217 | extern u32 even_dma_start_r; /* bit 0 should always be 0 */ |
| 218 | extern u64 odd_dma_start_r; /* .. */ | 218 | extern u32 odd_dma_start_r; /* .. */ |
| 219 | extern u64 even_dma_stride_r; /* bits 0&1 should always be 0 */ | 219 | extern u32 even_dma_stride_r; /* bits 0&1 should always be 0 */ |
| 220 | extern u64 odd_dma_stride_r; /* .. */ | 220 | extern u32 odd_dma_stride_r; /* .. */ |
| 221 | extern u64 even_pixel_fmt_r; | 221 | extern u32 even_pixel_fmt_r; |
| 222 | extern u64 odd_pixel_fmt_r; | 222 | extern u32 odd_pixel_fmt_r; |
| 223 | 223 | ||
| 224 | extern FIFO_TRIGGER_R fifo_trigger_r; | 224 | extern FIFO_TRIGGER_R fifo_trigger_r; |
| 225 | extern XFER_MODE_R xfer_mode_r; | 225 | extern XFER_MODE_R xfer_mode_r; |
| @@ -227,8 +227,8 @@ extern CSR1_R csr1_r; | |||
| 227 | extern RETRY_WAIT_CNT_R retry_wait_cnt_r; | 227 | extern RETRY_WAIT_CNT_R retry_wait_cnt_r; |
| 228 | extern INT_CSR_R int_csr_r; | 228 | extern INT_CSR_R int_csr_r; |
| 229 | 229 | ||
| 230 | extern u64 even_fld_mask_r; | 230 | extern u32 even_fld_mask_r; |
| 231 | extern u64 odd_fld_mask_r; | 231 | extern u32 odd_fld_mask_r; |
| 232 | 232 | ||
| 233 | extern MASK_LENGTH_R mask_length_r; | 233 | extern MASK_LENGTH_R mask_length_r; |
| 234 | extern FIFO_FLAG_CNT_R fifo_flag_cnt_r; | 234 | extern FIFO_FLAG_CNT_R fifo_flag_cnt_r; |
diff --git a/drivers/staging/dt3155/dt3155_isr.c b/drivers/staging/dt3155/dt3155_isr.c index 5b790867c292..fd7f93d6c33d 100644 --- a/drivers/staging/dt3155/dt3155_isr.c +++ b/drivers/staging/dt3155/dt3155_isr.c | |||
| @@ -220,7 +220,7 @@ inline void printques( int m ) | |||
| 220 | * the start address up to the beginning of the | 220 | * the start address up to the beginning of the |
| 221 | * next 4MB chunk (assuming bufsize < 4MB). | 221 | * next 4MB chunk (assuming bufsize < 4MB). |
| 222 | *****************************************************/ | 222 | *****************************************************/ |
| 223 | u64 adjust_4MB (u64 buf_addr, u64 bufsize) { | 223 | u32 adjust_4MB (u32 buf_addr, u32 bufsize) { |
| 224 | if (((buf_addr+bufsize) & UPPER_10_BITS) != (buf_addr & UPPER_10_BITS)) | 224 | if (((buf_addr+bufsize) & UPPER_10_BITS) != (buf_addr & UPPER_10_BITS)) |
| 225 | return (buf_addr+bufsize) & UPPER_10_BITS; | 225 | return (buf_addr+bufsize) & UPPER_10_BITS; |
| 226 | else | 226 | else |
| @@ -235,26 +235,26 @@ u64 adjust_4MB (u64 buf_addr, u64 bufsize) { | |||
| 235 | * buffers. If there is not enough free space | 235 | * buffers. If there is not enough free space |
| 236 | * try for less memory. | 236 | * try for less memory. |
| 237 | *****************************************************/ | 237 | *****************************************************/ |
| 238 | void allocate_buffers (u64 *buf_addr, u64* total_size_kbs, | 238 | void allocate_buffers (u32 *buf_addr, u32* total_size_kbs, |
| 239 | u64 bufsize) | 239 | u32 bufsize) |
| 240 | { | 240 | { |
| 241 | /* Compute the minimum amount of memory guaranteed to hold all | 241 | /* Compute the minimum amount of memory guaranteed to hold all |
| 242 | MAXBUFFERS such that no buffer crosses the 4MB boundary. | 242 | MAXBUFFERS such that no buffer crosses the 4MB boundary. |
| 243 | Store this value in the variable "full_size" */ | 243 | Store this value in the variable "full_size" */ |
| 244 | 244 | ||
| 245 | u64 allocator_max; | 245 | u32 allocator_max; |
| 246 | u64 bufs_per_chunk = (FOUR_MB / bufsize); | 246 | u32 bufs_per_chunk = (FOUR_MB / bufsize); |
| 247 | u64 filled_chunks = (MAXBUFFERS-1) / bufs_per_chunk; | 247 | u32 filled_chunks = (MAXBUFFERS-1) / bufs_per_chunk; |
| 248 | u64 leftover_bufs = MAXBUFFERS - filled_chunks * bufs_per_chunk; | 248 | u32 leftover_bufs = MAXBUFFERS - filled_chunks * bufs_per_chunk; |
| 249 | 249 | ||
| 250 | u64 full_size = bufsize /* possibly unusable part of 1st chunk */ | 250 | u32 full_size = bufsize /* possibly unusable part of 1st chunk */ |
| 251 | + filled_chunks * FOUR_MB /* max # of completely filled 4mb chunks */ | 251 | + filled_chunks * FOUR_MB /* max # of completely filled 4mb chunks */ |
| 252 | + leftover_bufs * bufsize; /* these buffs will be in a partly filled | 252 | + leftover_bufs * bufsize; /* these buffs will be in a partly filled |
| 253 | chunk at beginning or end */ | 253 | chunk at beginning or end */ |
| 254 | 254 | ||
| 255 | u64 full_size_kbs = 1 + (full_size-1) / 1024; | 255 | u32 full_size_kbs = 1 + (full_size-1) / 1024; |
| 256 | u64 min_size_kbs = 2*ndevices*bufsize / 1024; | 256 | u32 min_size_kbs = 2*ndevices*bufsize / 1024; |
| 257 | u64 size_kbs; | 257 | u32 size_kbs; |
| 258 | 258 | ||
| 259 | /* Now, try to allocate full_size. If this fails, keep trying for | 259 | /* Now, try to allocate full_size. If this fails, keep trying for |
| 260 | less & less memory until it succeeds. */ | 260 | less & less memory until it succeeds. */ |
| @@ -264,13 +264,13 @@ void allocate_buffers (u64 *buf_addr, u64* total_size_kbs, | |||
| 264 | #endif | 264 | #endif |
| 265 | size_kbs = full_size_kbs; | 265 | size_kbs = full_size_kbs; |
| 266 | *buf_addr = 0; | 266 | *buf_addr = 0; |
| 267 | printk ("DT3155: We would like to get: %d KB\n", (u32)(full_size_kbs)); | 267 | printk("DT3155: We would like to get: %d KB\n", full_size_kbs); |
| 268 | printk ("DT3155: ...but need at least: %d KB\n", (u32)(min_size_kbs)); | 268 | printk("DT3155: ...but need at least: %d KB\n", min_size_kbs); |
| 269 | printk ("DT3155: ...the allocator has: %d KB\n", (u32)(allocator_max)); | 269 | printk("DT3155: ...the allocator has: %d KB\n", allocator_max); |
| 270 | size_kbs = (full_size_kbs <= allocator_max ? full_size_kbs : allocator_max); | 270 | size_kbs = (full_size_kbs <= allocator_max ? full_size_kbs : allocator_max); |
| 271 | if (size_kbs > min_size_kbs) { | 271 | if (size_kbs > min_size_kbs) { |
| 272 | if ((*buf_addr = allocator_allocate_dma (size_kbs, GFP_KERNEL)) != 0) { | 272 | if ((*buf_addr = allocator_allocate_dma (size_kbs, GFP_KERNEL)) != 0) { |
| 273 | printk ("DT3155: Managed to allocate: %d KB\n", (u32)size_kbs); | 273 | printk("DT3155: Managed to allocate: %d KB\n", size_kbs); |
| 274 | *total_size_kbs = size_kbs; | 274 | *total_size_kbs = size_kbs; |
| 275 | return; | 275 | return; |
| 276 | } | 276 | } |
| @@ -298,17 +298,17 @@ void allocate_buffers (u64 *buf_addr, u64* total_size_kbs, | |||
| 298 | * 4MB boundary. Also, add error checking. This | 298 | * 4MB boundary. Also, add error checking. This |
| 299 | * function will return -ENOMEM when not enough memory. | 299 | * function will return -ENOMEM when not enough memory. |
| 300 | *****************************************************/ | 300 | *****************************************************/ |
| 301 | u64 dt3155_setup_buffers(u64 *allocatorAddr) | 301 | u32 dt3155_setup_buffers(u32 *allocatorAddr) |
| 302 | 302 | ||
| 303 | { | 303 | { |
| 304 | u64 index; | 304 | u32 index; |
| 305 | u64 rambuff_addr; /* start of allocation */ | 305 | u32 rambuff_addr; /* start of allocation */ |
| 306 | u64 rambuff_size; /* total size allocated to driver */ | 306 | u32 rambuff_size; /* total size allocated to driver */ |
| 307 | u64 rambuff_acm; /* accumlator, keep track of how much | 307 | u32 rambuff_acm; /* accumlator, keep track of how much |
| 308 | is left after being split up*/ | 308 | is left after being split up*/ |
| 309 | u64 rambuff_end; /* end of rambuff */ | 309 | u32 rambuff_end; /* end of rambuff */ |
| 310 | u64 numbufs; /* number of useful buffers allocated (per device) */ | 310 | u32 numbufs; /* number of useful buffers allocated (per device) */ |
| 311 | u64 bufsize = DT3155_MAX_ROWS * DT3155_MAX_COLS; | 311 | u32 bufsize = DT3155_MAX_ROWS * DT3155_MAX_COLS; |
| 312 | int m; /* minor # of device, looped for all devs */ | 312 | int m; /* minor # of device, looped for all devs */ |
| 313 | 313 | ||
| 314 | /* zero the fbuffer status and address structure */ | 314 | /* zero the fbuffer status and address structure */ |
| @@ -326,9 +326,9 @@ u64 dt3155_setup_buffers(u64 *allocatorAddr) | |||
| 326 | 326 | ||
| 327 | /* allocate a large contiguous chunk of RAM */ | 327 | /* allocate a large contiguous chunk of RAM */ |
| 328 | allocate_buffers (&rambuff_addr, &rambuff_size, bufsize); | 328 | allocate_buffers (&rambuff_addr, &rambuff_size, bufsize); |
| 329 | printk( "DT3155: mem info\n" ); | 329 | printk("DT3155: mem info\n"); |
| 330 | printk( " - rambuf_addr = 0x%x \n", (u32)rambuff_addr ); | 330 | printk(" - rambuf_addr = 0x%x \n", rambuff_addr); |
| 331 | printk( " - length (kb) = %u \n", (u32)rambuff_size ); | 331 | printk(" - length (kb) = %u \n", rambuff_size); |
| 332 | if( rambuff_addr == 0 ) | 332 | if( rambuff_addr == 0 ) |
| 333 | { | 333 | { |
| 334 | printk( KERN_INFO | 334 | printk( KERN_INFO |
| @@ -350,7 +350,7 @@ u64 dt3155_setup_buffers(u64 *allocatorAddr) | |||
| 350 | /* Following line is OK, will waste buffers if index | 350 | /* Following line is OK, will waste buffers if index |
| 351 | * not evenly divisible by ndevices -NJC*/ | 351 | * not evenly divisible by ndevices -NJC*/ |
| 352 | numbufs = index / ndevices; | 352 | numbufs = index / ndevices; |
| 353 | printk (" - numbufs = %u\n", (u32) numbufs); | 353 | printk(" - numbufs = %u\n", numbufs); |
| 354 | if (numbufs < 2) { | 354 | if (numbufs < 2) { |
| 355 | printk( KERN_INFO | 355 | printk( KERN_INFO |
| 356 | "DT3155: Error setup_buffers() couldn't allocate 2 bufs/board\n" ); | 356 | "DT3155: Error setup_buffers() couldn't allocate 2 bufs/board\n" ); |
diff --git a/drivers/staging/dt3155/dt3155_isr.h b/drivers/staging/dt3155/dt3155_isr.h index 7f27910eb941..7595cb16c988 100644 --- a/drivers/staging/dt3155/dt3155_isr.h +++ b/drivers/staging/dt3155/dt3155_isr.h | |||
| @@ -42,7 +42,7 @@ extern struct dt3155_fbuffer_s *dt3155_fbuffer[MAXBOARDS]; | |||
| 42 | /* Initialize the buffering system. This should */ | 42 | /* Initialize the buffering system. This should */ |
| 43 | /* be called prior to enabling interrupts */ | 43 | /* be called prior to enabling interrupts */ |
| 44 | 44 | ||
| 45 | u64 dt3155_setup_buffers(u64 *allocatorAddr); | 45 | u32 dt3155_setup_buffers(u32 *allocatorAddr); |
| 46 | 46 | ||
| 47 | /* Get the next frame of data if it is ready. Returns */ | 47 | /* Get the next frame of data if it is ready. Returns */ |
| 48 | /* zero if no data is ready. If there is data but */ | 48 | /* zero if no data is ready. If there is data but */ |
