diff options
| -rw-r--r-- | arch/sparc/kernel/perf_event.c | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 48375f694673..8abdc4d1baa5 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c | |||
| @@ -91,19 +91,19 @@ struct sparc_pmu { | |||
| 91 | int lower_nop; | 91 | int lower_nop; |
| 92 | }; | 92 | }; |
| 93 | 93 | ||
| 94 | static const struct perf_event_map ultra3i_perfmon_event_map[] = { | 94 | static const struct perf_event_map ultra3_perfmon_event_map[] = { |
| 95 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER }, | 95 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER }, |
| 96 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER }, | 96 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER }, |
| 97 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER }, | 97 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER }, |
| 98 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER }, | 98 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER }, |
| 99 | }; | 99 | }; |
| 100 | 100 | ||
| 101 | static const struct perf_event_map *ultra3i_event_map(int event_id) | 101 | static const struct perf_event_map *ultra3_event_map(int event_id) |
| 102 | { | 102 | { |
| 103 | return &ultra3i_perfmon_event_map[event_id]; | 103 | return &ultra3_perfmon_event_map[event_id]; |
| 104 | } | 104 | } |
| 105 | 105 | ||
| 106 | static const cache_map_t ultra3i_cache_map = { | 106 | static const cache_map_t ultra3_cache_map = { |
| 107 | [C(L1D)] = { | 107 | [C(L1D)] = { |
| 108 | [C(OP_READ)] = { | 108 | [C(OP_READ)] = { |
| 109 | [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, | 109 | [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, |
| @@ -190,10 +190,10 @@ static const cache_map_t ultra3i_cache_map = { | |||
| 190 | }, | 190 | }, |
| 191 | }; | 191 | }; |
| 192 | 192 | ||
| 193 | static const struct sparc_pmu ultra3i_pmu = { | 193 | static const struct sparc_pmu ultra3_pmu = { |
| 194 | .event_map = ultra3i_event_map, | 194 | .event_map = ultra3_event_map, |
| 195 | .cache_map = &ultra3i_cache_map, | 195 | .cache_map = &ultra3_cache_map, |
| 196 | .max_events = ARRAY_SIZE(ultra3i_perfmon_event_map), | 196 | .max_events = ARRAY_SIZE(ultra3_perfmon_event_map), |
| 197 | .upper_shift = 11, | 197 | .upper_shift = 11, |
| 198 | .lower_shift = 4, | 198 | .lower_shift = 4, |
| 199 | .event_mask = 0x3f, | 199 | .event_mask = 0x3f, |
| @@ -658,8 +658,11 @@ static __read_mostly struct notifier_block perf_event_nmi_notifier = { | |||
| 658 | 658 | ||
| 659 | static bool __init supported_pmu(void) | 659 | static bool __init supported_pmu(void) |
| 660 | { | 660 | { |
| 661 | if (!strcmp(sparc_pmu_type, "ultra3i")) { | 661 | if (!strcmp(sparc_pmu_type, "ultra3") || |
| 662 | sparc_pmu = &ultra3i_pmu; | 662 | !strcmp(sparc_pmu_type, "ultra3+") || |
| 663 | !strcmp(sparc_pmu_type, "ultra3i") || | ||
| 664 | !strcmp(sparc_pmu_type, "ultra4+")) { | ||
| 665 | sparc_pmu = &ultra3_pmu; | ||
| 663 | return true; | 666 | return true; |
| 664 | } | 667 | } |
| 665 | if (!strcmp(sparc_pmu_type, "niagara2")) { | 668 | if (!strcmp(sparc_pmu_type, "niagara2")) { |
