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-rw-r--r--Documentation/powerpc/booting-without-of.txt156
-rw-r--r--arch/powerpc/platforms/44x/Kconfig3
-rw-r--r--arch/powerpc/platforms/cell/Kconfig4
-rw-r--r--drivers/net/Kconfig71
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/ibm_emac/Kconfig70
-rw-r--r--drivers/net/ibm_newemac/Kconfig63
-rw-r--r--drivers/net/ibm_newemac/Makefile11
-rw-r--r--drivers/net/ibm_newemac/core.c2907
-rw-r--r--drivers/net/ibm_newemac/core.h355
-rw-r--r--drivers/net/ibm_newemac/debug.c238
-rw-r--r--drivers/net/ibm_newemac/debug.h78
-rw-r--r--drivers/net/ibm_newemac/emac.h268
-rw-r--r--drivers/net/ibm_newemac/mal.c728
-rw-r--r--drivers/net/ibm_newemac/mal.h276
-rw-r--r--drivers/net/ibm_newemac/phy.c373
-rw-r--r--drivers/net/ibm_newemac/phy.h80
-rw-r--r--drivers/net/ibm_newemac/rgmii.c323
-rw-r--r--drivers/net/ibm_newemac/rgmii.h76
-rw-r--r--drivers/net/ibm_newemac/tah.c173
-rw-r--r--drivers/net/ibm_newemac/tah.h90
-rw-r--r--drivers/net/ibm_newemac/zmii.c322
-rw-r--r--drivers/net/ibm_newemac/zmii.h73
23 files changed, 6668 insertions, 71 deletions
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 76733a3962f0..838fd323e797 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1824,6 +1824,162 @@ platforms are moved over to use the flattened-device-tree model.
1824 fsl,has-rstcr; 1824 fsl,has-rstcr;
1825 }; 1825 };
1826 1826
1827
1828 h) 4xx/Axon EMAC ethernet nodes
1829
1830 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
1831 the Axon bridge. To operate this needs to interact with a ths
1832 special McMAL DMA controller, and sometimes an RGMII or ZMII
1833 interface. In addition to the nodes and properties described
1834 below, the node for the OPB bus on which the EMAC sits must have a
1835 correct clock-frequency property.
1836
1837 i) The EMAC node itself
1838
1839 Required properties:
1840 - device_type : "network"
1841
1842 - compatible : compatible list, contains 2 entries, first is
1843 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
1844 405gp, Axon) and second is either "ibm,emac" or
1845 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
1846 "ibm,emac4"
1847 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
1848 - interrupt-parent : optional, if needed for interrupt mapping
1849 - reg : <registers mapping>
1850 - local-mac-address : 6 bytes, MAC address
1851 - mal-device : phandle of the associated McMAL node
1852 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
1853 with this EMAC
1854 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
1855 with this EMAC
1856 - cell-index : 1 cell, hardware index of the EMAC cell on a given
1857 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
1858 each Axon chip)
1859 - max-frame-size : 1 cell, maximum frame size supported in bytes
1860 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
1861 operations.
1862 For Axon, 2048
1863 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
1864 operations.
1865 For Axon, 2048.
1866 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
1867 thresholds).
1868 For Axon, 0x00000010
1869 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
1870 in bytes.
1871 For Axon, 0x00000100 (I think ...)
1872 - phy-mode : string, mode of operations of the PHY interface.
1873 Supported values are: "mii", "rmii", "smii", "rgmii",
1874 "tbi", "gmii", rtbi", "sgmii".
1875 For Axon on CAB, it is "rgmii"
1876 - mdio-device : 1 cell, required iff using shared MDIO registers
1877 (440EP). phandle of the EMAC to use to drive the
1878 MDIO lines for the PHY used by this EMAC.
1879 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
1880 the ZMII device node
1881 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
1882 channel or 0xffffffff if ZMII is only used for MDIO.
1883 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
1884 of the RGMII device node.
1885 For Axon: phandle of plb5/plb4/opb/rgmii
1886 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
1887 RGMII channel is used by this EMAC.
1888 Fox Axon: present, whatever value is appropriate for each
1889 EMAC, that is the content of the current (bogus) "phy-port"
1890 property.
1891
1892 Recommended properties:
1893 - linux,network-index : This is the intended "index" of this
1894 network device. This is used by the bootwrapper to interpret
1895 MAC addresses passed by the firmware when no information other
1896 than indices is available to associate an address with a device.
1897
1898 Optional properties:
1899 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
1900 a search is performed.
1901 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
1902 for, used if phy-address is absent. bit 0x00000001 is
1903 MDIO address 0.
1904 For Axon it can be absent, thouugh my current driver
1905 doesn't handle phy-address yet so for now, keep
1906 0x00ffffff in it.
1907 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
1908 operations (if absent the value is the same as
1909 rx-fifo-size). For Axon, either absent or 2048.
1910 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
1911 operations (if absent the value is the same as
1912 tx-fifo-size). For Axon, either absent or 2048.
1913 - tah-device : 1 cell, optional. If connected to a TAH engine for
1914 offload, phandle of the TAH device node.
1915 - tah-channel : 1 cell, optional. If appropriate, channel used on the
1916 TAH engine.
1917
1918 Example:
1919
1920 EMAC0: ethernet@40000800 {
1921 linux,network-index = <0>;
1922 device_type = "network";
1923 compatible = "ibm,emac-440gp", "ibm,emac";
1924 interrupt-parent = <&UIC1>;
1925 interrupts = <1c 4 1d 4>;
1926 reg = <40000800 70>;
1927 local-mac-address = [00 04 AC E3 1B 1E];
1928 mal-device = <&MAL0>;
1929 mal-tx-channel = <0 1>;
1930 mal-rx-channel = <0>;
1931 cell-index = <0>;
1932 max-frame-size = <5dc>;
1933 rx-fifo-size = <1000>;
1934 tx-fifo-size = <800>;
1935 phy-mode = "rmii";
1936 phy-map = <00000001>;
1937 zmii-device = <&ZMII0>;
1938 zmii-channel = <0>;
1939 };
1940
1941 ii) McMAL node
1942
1943 Required properties:
1944 - device_type : "dma-controller"
1945 - compatible : compatible list, containing 2 entries, first is
1946 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
1947 emac) and the second is either "ibm,mcmal" or
1948 "ibm,mcmal2".
1949 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
1950 - interrupts : <interrupt mapping for the MAL interrupts sources:
1951 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
1952 For Axon: This is _different_ from the current
1953 firmware. We use the "delayed" interrupts for txeob
1954 and rxeob. Thus we end up with mapping those 5 MPIC
1955 interrupts, all level positive sensitive: 10, 11, 32,
1956 33, 34 (in decimal)
1957 - dcr-reg : < DCR registers range >
1958 - dcr-parent : if needed for dcr-reg
1959 - num-tx-chans : 1 cell, number of Tx channels
1960 - num-rx-chans : 1 cell, number of Rx channels
1961
1962 iii) ZMII node
1963
1964 Required properties:
1965 - compatible : compatible list, containing 2 entries, first is
1966 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
1967 EMAC) and the second is "ibm,zmii".
1968 For Axon, there is no ZMII node.
1969 - reg : <registers mapping>
1970
1971 iv) RGMII node
1972
1973 Required properties:
1974 - compatible : compatible list, containing 2 entries, first is
1975 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
1976 EMAC) and the second is "ibm,rgmii".
1977 For Axon, "ibm,rgmii-axon","ibm,rgmii"
1978 - reg : <registers mapping>
1979 - revision : as provided by the RGMII new version register if
1980 available.
1981 For Axon: 0x0000012a
1982
1827 More devices will be defined as this spec matures. 1983 More devices will be defined as this spec matures.
1828 1984
1829VII - Specifying interrupt information for devices 1985VII - Specifying interrupt information for devices
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 1b3e008fd148..8e66949e7c67 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -38,8 +38,7 @@ config 440EP
38 38
39config 440GP 39config 440GP
40 bool 40 bool
41# Disabled until the new EMAC Driver is merged. 41 select IBM_NEW_EMAC_ZMII
42# select IBM_NEW_EMAC_ZMII
43 42
44config 440GX 43config 440GX
45 bool 44 bool
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
index ac8032034fb8..e1e2f6a43019 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -10,6 +10,10 @@ config PPC_CELL_NATIVE
10 select PPC_INDIRECT_IO 10 select PPC_INDIRECT_IO
11 select PPC_NATIVE 11 select PPC_NATIVE
12 select MPIC 12 select MPIC
13 select IBM_NEW_EMAC_EMAC4
14 select IBM_NEW_EMAC_RGMII
15 select IBM_NEW_EMAC_ZMII #test only
16 select IBM_NEW_EMAC_TAH #test only
13 default n 17 default n
14 18
15config PPC_IBM_CELL_BLADE 19config PPC_IBM_CELL_BLADE
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9dc4a80a6acd..cfa97f3fbebd 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1247,75 +1247,8 @@ config IBMVETH
1247 <file:Documentation/networking/net-modules.txt>. The module will 1247 <file:Documentation/networking/net-modules.txt>. The module will
1248 be called ibmveth. 1248 be called ibmveth.
1249 1249
1250config IBM_EMAC 1250source "drivers/net/ibm_emac/Kconfig"
1251 tristate "PowerPC 4xx on-chip Ethernet support" 1251source "drivers/net/ibm_newemac/Kconfig"
1252 depends on 4xx && !PPC_MERGE
1253 help
1254 This driver supports the PowerPC 4xx EMAC family of on-chip
1255 Ethernet controllers.
1256
1257config IBM_EMAC_RXB
1258 int "Number of receive buffers"
1259 depends on IBM_EMAC
1260 default "128"
1261
1262config IBM_EMAC_TXB
1263 int "Number of transmit buffers"
1264 depends on IBM_EMAC
1265 default "64"
1266
1267config IBM_EMAC_POLL_WEIGHT
1268 int "MAL NAPI polling weight"
1269 depends on IBM_EMAC
1270 default "32"
1271
1272config IBM_EMAC_RX_COPY_THRESHOLD
1273 int "RX skb copy threshold (bytes)"
1274 depends on IBM_EMAC
1275 default "256"
1276
1277config IBM_EMAC_RX_SKB_HEADROOM
1278 int "Additional RX skb headroom (bytes)"
1279 depends on IBM_EMAC
1280 default "0"
1281 help
1282 Additional receive skb headroom. Note, that driver
1283 will always reserve at least 2 bytes to make IP header
1284 aligned, so usually there is no need to add any additional
1285 headroom.
1286
1287 If unsure, set to 0.
1288
1289config IBM_EMAC_PHY_RX_CLK_FIX
1290 bool "PHY Rx clock workaround"
1291 depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR)
1292 help
1293 Enable this if EMAC attached to a PHY which doesn't generate
1294 RX clock if there is no link, if this is the case, you will
1295 see "TX disable timeout" or "RX disable timeout" in the system
1296 log.
1297
1298 If unsure, say N.
1299
1300config IBM_EMAC_DEBUG
1301 bool "Debugging"
1302 depends on IBM_EMAC
1303 default n
1304
1305config IBM_EMAC_ZMII
1306 bool
1307 depends on IBM_EMAC && (NP405H || NP405L || 44x)
1308 default y
1309
1310config IBM_EMAC_RGMII
1311 bool
1312 depends on IBM_EMAC && 440GX
1313 default y
1314
1315config IBM_EMAC_TAH
1316 bool
1317 depends on IBM_EMAC && 440GX
1318 default y
1319 1252
1320config NET_PCI 1253config NET_PCI
1321 bool "EISA, VLB, PCI and on board controllers" 1254 bool "EISA, VLB, PCI and on board controllers"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 2ab33e8b9159..9cbef5829870 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -5,6 +5,7 @@
5obj-$(CONFIG_E1000) += e1000/ 5obj-$(CONFIG_E1000) += e1000/
6obj-$(CONFIG_E1000E) += e1000e/ 6obj-$(CONFIG_E1000E) += e1000e/
7obj-$(CONFIG_IBM_EMAC) += ibm_emac/ 7obj-$(CONFIG_IBM_EMAC) += ibm_emac/
8obj-$(CONFIG_IBM_NEW_EMAC) += ibm_newemac/
8obj-$(CONFIG_IXGBE) += ixgbe/ 9obj-$(CONFIG_IXGBE) += ixgbe/
9obj-$(CONFIG_IXGB) += ixgb/ 10obj-$(CONFIG_IXGB) += ixgb/
10obj-$(CONFIG_IP1000) += ipg.o 11obj-$(CONFIG_IP1000) += ipg.o
diff --git a/drivers/net/ibm_emac/Kconfig b/drivers/net/ibm_emac/Kconfig
new file mode 100644
index 000000000000..f61c48047dc0
--- /dev/null
+++ b/drivers/net/ibm_emac/Kconfig
@@ -0,0 +1,70 @@
1config IBM_EMAC
2 tristate "PowerPC 4xx on-chip Ethernet support"
3 depends on 4xx && !PPC_MERGE
4 help
5 This driver supports the PowerPC 4xx EMAC family of on-chip
6 Ethernet controllers.
7
8config IBM_EMAC_RXB
9 int "Number of receive buffers"
10 depends on IBM_EMAC
11 default "128"
12
13config IBM_EMAC_TXB
14 int "Number of transmit buffers"
15 depends on IBM_EMAC
16 default "64"
17
18config IBM_EMAC_POLL_WEIGHT
19 int "MAL NAPI polling weight"
20 depends on IBM_EMAC
21 default "32"
22
23config IBM_EMAC_RX_COPY_THRESHOLD
24 int "RX skb copy threshold (bytes)"
25 depends on IBM_EMAC
26 default "256"
27
28config IBM_EMAC_RX_SKB_HEADROOM
29 int "Additional RX skb headroom (bytes)"
30 depends on IBM_EMAC
31 default "0"
32 help
33 Additional receive skb headroom. Note, that driver
34 will always reserve at least 2 bytes to make IP header
35 aligned, so usually there is no need to add any additional
36 headroom.
37
38 If unsure, set to 0.
39
40config IBM_EMAC_PHY_RX_CLK_FIX
41 bool "PHY Rx clock workaround"
42 depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR)
43 help
44 Enable this if EMAC attached to a PHY which doesn't generate
45 RX clock if there is no link, if this is the case, you will
46 see "TX disable timeout" or "RX disable timeout" in the system
47 log.
48
49 If unsure, say N.
50
51config IBM_EMAC_DEBUG
52 bool "Debugging"
53 depends on IBM_EMAC
54 default n
55
56config IBM_EMAC_ZMII
57 bool
58 depends on IBM_EMAC && (NP405H || NP405L || 44x)
59 default y
60
61config IBM_EMAC_RGMII
62 bool
63 depends on IBM_EMAC && 440GX
64 default y
65
66config IBM_EMAC_TAH
67 bool
68 depends on IBM_EMAC && 440GX
69 default y
70
diff --git a/drivers/net/ibm_newemac/Kconfig b/drivers/net/ibm_newemac/Kconfig
new file mode 100644
index 000000000000..0d3e7380bad0
--- /dev/null
+++ b/drivers/net/ibm_newemac/Kconfig
@@ -0,0 +1,63 @@
1config IBM_NEW_EMAC
2 tristate "IBM EMAC Ethernet support"
3 depends on PPC_DCR && PPC_MERGE
4 help
5 This driver supports the IBM EMAC family of Ethernet controllers
6 typically found on 4xx embedded PowerPC chips, but also on the
7 Axon southbridge for Cell.
8
9config IBM_NEW_EMAC_RXB
10 int "Number of receive buffers"
11 depends on IBM_NEW_EMAC
12 default "128"
13
14config IBM_NEW_EMAC_TXB
15 int "Number of transmit buffers"
16 depends on IBM_NEW_EMAC
17 default "64"
18
19config IBM_NEW_EMAC_POLL_WEIGHT
20 int "MAL NAPI polling weight"
21 depends on IBM_NEW_EMAC
22 default "32"
23
24config IBM_NEW_EMAC_RX_COPY_THRESHOLD
25 int "RX skb copy threshold (bytes)"
26 depends on IBM_NEW_EMAC
27 default "256"
28
29config IBM_NEW_EMAC_RX_SKB_HEADROOM
30 int "Additional RX skb headroom (bytes)"
31 depends on IBM_NEW_EMAC
32 default "0"
33 help
34 Additional receive skb headroom. Note, that driver
35 will always reserve at least 2 bytes to make IP header
36 aligned, so usually there is no need to add any additional
37 headroom.
38
39 If unsure, set to 0.
40
41config IBM_NEW_EMAC_DEBUG
42 bool "Debugging"
43 depends on IBM_NEW_EMAC
44 default n
45
46# The options below has to be select'ed by the respective
47# processor types or platforms
48
49config IBM_NEW_EMAC_ZMII
50 bool
51 default n
52
53config IBM_NEW_EMAC_RGMII
54 bool
55 default n
56
57config IBM_NEW_EMAC_TAH
58 bool
59 default n
60
61config IBM_NEW_EMAC_EMAC4
62 bool
63 default n
diff --git a/drivers/net/ibm_newemac/Makefile b/drivers/net/ibm_newemac/Makefile
new file mode 100644
index 000000000000..0b5c99512762
--- /dev/null
+++ b/drivers/net/ibm_newemac/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the PowerPC 4xx on-chip ethernet driver
3#
4
5obj-$(CONFIG_IBM_NEW_EMAC) += ibm_newemac.o
6
7ibm_newemac-y := mal.o core.o phy.o
8ibm_newemac-$(CONFIG_IBM_NEW_EMAC_ZMII) += zmii.o
9ibm_newemac-$(CONFIG_IBM_NEW_EMAC_RGMII) += rgmii.o
10ibm_newemac-$(CONFIG_IBM_NEW_EMAC_TAH) += tah.o
11ibm_newemac-$(CONFIG_IBM_NEW_EMAC_DEBUG) += debug.o
diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c
new file mode 100644
index 000000000000..653bfdc291e0
--- /dev/null
+++ b/drivers/net/ibm_newemac/core.c
@@ -0,0 +1,2907 @@
1/*
2 * drivers/net/ibm_newemac/core.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
12 * Armin Kuster <akuster@mvista.com>
13 * Johnnie Peters <jpeters@mvista.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 */
21
22#include <linux/sched.h>
23#include <linux/string.h>
24#include <linux/errno.h>
25#include <linux/delay.h>
26#include <linux/types.h>
27#include <linux/pci.h>
28#include <linux/etherdevice.h>
29#include <linux/skbuff.h>
30#include <linux/crc32.h>
31#include <linux/ethtool.h>
32#include <linux/mii.h>
33#include <linux/bitops.h>
34#include <linux/workqueue.h>
35
36#include <asm/processor.h>
37#include <asm/io.h>
38#include <asm/dma.h>
39#include <asm/uaccess.h>
40
41#include "core.h"
42
43/*
44 * Lack of dma_unmap_???? calls is intentional.
45 *
46 * API-correct usage requires additional support state information to be
47 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
48 * EMAC design (e.g. TX buffer passed from network stack can be split into
49 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
50 * maintaining such information will add additional overhead.
51 * Current DMA API implementation for 4xx processors only ensures cache coherency
52 * and dma_unmap_???? routines are empty and are likely to stay this way.
53 * I decided to omit dma_unmap_??? calls because I don't want to add additional
54 * complexity just for the sake of following some abstract API, when it doesn't
55 * add any real benefit to the driver. I understand that this decision maybe
56 * controversial, but I really tried to make code API-correct and efficient
57 * at the same time and didn't come up with code I liked :(. --ebs
58 */
59
60#define DRV_NAME "emac"
61#define DRV_VERSION "3.54"
62#define DRV_DESC "PPC 4xx OCP EMAC driver"
63
64MODULE_DESCRIPTION(DRV_DESC);
65MODULE_AUTHOR
66 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
67MODULE_LICENSE("GPL");
68
69/*
70 * PPC64 doesn't (yet) have a cacheable_memcpy
71 */
72#ifdef CONFIG_PPC64
73#define cacheable_memcpy(d,s,n) memcpy((d),(s),(n))
74#endif
75
76/* minimum number of free TX descriptors required to wake up TX process */
77#define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
78
79/* If packet size is less than this number, we allocate small skb and copy packet
80 * contents into it instead of just sending original big skb up
81 */
82#define EMAC_RX_COPY_THRESH CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD
83
84/* Since multiple EMACs share MDIO lines in various ways, we need
85 * to avoid re-using the same PHY ID in cases where the arch didn't
86 * setup precise phy_map entries
87 *
88 * XXX This is something that needs to be reworked as we can have multiple
89 * EMAC "sets" (multiple ASICs containing several EMACs) though we can
90 * probably require in that case to have explicit PHY IDs in the device-tree
91 */
92static u32 busy_phy_map;
93static DEFINE_MUTEX(emac_phy_map_lock);
94
95/* This is the wait queue used to wait on any event related to probe, that
96 * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc...
97 */
98static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait);
99
100/* Having stable interface names is a doomed idea. However, it would be nice
101 * if we didn't have completely random interface names at boot too :-) It's
102 * just a matter of making everybody's life easier. Since we are doing
103 * threaded probing, it's a bit harder though. The base idea here is that
104 * we make up a list of all emacs in the device-tree before we register the
105 * driver. Every emac will then wait for the previous one in the list to
106 * initialize before itself. We should also keep that list ordered by
107 * cell_index.
108 * That list is only 4 entries long, meaning that additional EMACs don't
109 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
110 */
111
112#define EMAC_BOOT_LIST_SIZE 4
113static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
114
115/* How long should I wait for dependent devices ? */
116#define EMAC_PROBE_DEP_TIMEOUT (HZ * 5)
117
118/* I don't want to litter system log with timeout errors
119 * when we have brain-damaged PHY.
120 */
121static inline void emac_report_timeout_error(struct emac_instance *dev,
122 const char *error)
123{
124 if (net_ratelimit())
125 printk(KERN_ERR "%s: %s\n", dev->ndev->name, error);
126}
127
128/* PHY polling intervals */
129#define PHY_POLL_LINK_ON HZ
130#define PHY_POLL_LINK_OFF (HZ / 5)
131
132/* Graceful stop timeouts in us.
133 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
134 */
135#define STOP_TIMEOUT_10 1230
136#define STOP_TIMEOUT_100 124
137#define STOP_TIMEOUT_1000 13
138#define STOP_TIMEOUT_1000_JUMBO 73
139
140/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
141static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
142 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
143 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
144 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
145 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
146 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
147 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
148 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
149 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
150 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
151 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
152 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
153 "tx_bd_excessive_collisions", "tx_bd_late_collision",
154 "tx_bd_multple_collisions", "tx_bd_single_collision",
155 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
156 "tx_errors"
157};
158
159static irqreturn_t emac_irq(int irq, void *dev_instance);
160static void emac_clean_tx_ring(struct emac_instance *dev);
161static void __emac_set_multicast_list(struct emac_instance *dev);
162
163static inline int emac_phy_supports_gige(int phy_mode)
164{
165 return phy_mode == PHY_MODE_GMII ||
166 phy_mode == PHY_MODE_RGMII ||
167 phy_mode == PHY_MODE_TBI ||
168 phy_mode == PHY_MODE_RTBI;
169}
170
171static inline int emac_phy_gpcs(int phy_mode)
172{
173 return phy_mode == PHY_MODE_TBI ||
174 phy_mode == PHY_MODE_RTBI;
175}
176
177static inline void emac_tx_enable(struct emac_instance *dev)
178{
179 struct emac_regs __iomem *p = dev->emacp;
180 u32 r;
181
182 DBG(dev, "tx_enable" NL);
183
184 r = in_be32(&p->mr0);
185 if (!(r & EMAC_MR0_TXE))
186 out_be32(&p->mr0, r | EMAC_MR0_TXE);
187}
188
189static void emac_tx_disable(struct emac_instance *dev)
190{
191 struct emac_regs __iomem *p = dev->emacp;
192 u32 r;
193
194 DBG(dev, "tx_disable" NL);
195
196 r = in_be32(&p->mr0);
197 if (r & EMAC_MR0_TXE) {
198 int n = dev->stop_timeout;
199 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
200 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
201 udelay(1);
202 --n;
203 }
204 if (unlikely(!n))
205 emac_report_timeout_error(dev, "TX disable timeout");
206 }
207}
208
209static void emac_rx_enable(struct emac_instance *dev)
210{
211 struct emac_regs __iomem *p = dev->emacp;
212 u32 r;
213
214 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
215 goto out;
216
217 DBG(dev, "rx_enable" NL);
218
219 r = in_be32(&p->mr0);
220 if (!(r & EMAC_MR0_RXE)) {
221 if (unlikely(!(r & EMAC_MR0_RXI))) {
222 /* Wait if previous async disable is still in progress */
223 int n = dev->stop_timeout;
224 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
225 udelay(1);
226 --n;
227 }
228 if (unlikely(!n))
229 emac_report_timeout_error(dev,
230 "RX disable timeout");
231 }
232 out_be32(&p->mr0, r | EMAC_MR0_RXE);
233 }
234 out:
235 ;
236}
237
238static void emac_rx_disable(struct emac_instance *dev)
239{
240 struct emac_regs __iomem *p = dev->emacp;
241 u32 r;
242
243 DBG(dev, "rx_disable" NL);
244
245 r = in_be32(&p->mr0);
246 if (r & EMAC_MR0_RXE) {
247 int n = dev->stop_timeout;
248 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
249 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
250 udelay(1);
251 --n;
252 }
253 if (unlikely(!n))
254 emac_report_timeout_error(dev, "RX disable timeout");
255 }
256}
257
258static inline void emac_netif_stop(struct emac_instance *dev)
259{
260 netif_tx_lock_bh(dev->ndev);
261 dev->no_mcast = 1;
262 netif_tx_unlock_bh(dev->ndev);
263 dev->ndev->trans_start = jiffies; /* prevent tx timeout */
264 mal_poll_disable(dev->mal, &dev->commac);
265 netif_tx_disable(dev->ndev);
266}
267
268static inline void emac_netif_start(struct emac_instance *dev)
269{
270 netif_tx_lock_bh(dev->ndev);
271 dev->no_mcast = 0;
272 if (dev->mcast_pending && netif_running(dev->ndev))
273 __emac_set_multicast_list(dev);
274 netif_tx_unlock_bh(dev->ndev);
275
276 netif_wake_queue(dev->ndev);
277
278 /* NOTE: unconditional netif_wake_queue is only appropriate
279 * so long as all callers are assured to have free tx slots
280 * (taken from tg3... though the case where that is wrong is
281 * not terribly harmful)
282 */
283 mal_poll_enable(dev->mal, &dev->commac);
284}
285
286static inline void emac_rx_disable_async(struct emac_instance *dev)
287{
288 struct emac_regs __iomem *p = dev->emacp;
289 u32 r;
290
291 DBG(dev, "rx_disable_async" NL);
292
293 r = in_be32(&p->mr0);
294 if (r & EMAC_MR0_RXE)
295 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
296}
297
298static int emac_reset(struct emac_instance *dev)
299{
300 struct emac_regs __iomem *p = dev->emacp;
301 int n = 20;
302
303 DBG(dev, "reset" NL);
304
305 if (!dev->reset_failed) {
306 /* 40x erratum suggests stopping RX channel before reset,
307 * we stop TX as well
308 */
309 emac_rx_disable(dev);
310 emac_tx_disable(dev);
311 }
312
313 out_be32(&p->mr0, EMAC_MR0_SRST);
314 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
315 --n;
316
317 if (n) {
318 dev->reset_failed = 0;
319 return 0;
320 } else {
321 emac_report_timeout_error(dev, "reset timeout");
322 dev->reset_failed = 1;
323 return -ETIMEDOUT;
324 }
325}
326
327static void emac_hash_mc(struct emac_instance *dev)
328{
329 struct emac_regs __iomem *p = dev->emacp;
330 u16 gaht[4] = { 0 };
331 struct dev_mc_list *dmi;
332
333 DBG(dev, "hash_mc %d" NL, dev->ndev->mc_count);
334
335 for (dmi = dev->ndev->mc_list; dmi; dmi = dmi->next) {
336 int bit;
337 DBG2(dev, "mc %02x:%02x:%02x:%02x:%02x:%02x" NL,
338 dmi->dmi_addr[0], dmi->dmi_addr[1], dmi->dmi_addr[2],
339 dmi->dmi_addr[3], dmi->dmi_addr[4], dmi->dmi_addr[5]);
340
341 bit = 63 - (ether_crc(ETH_ALEN, dmi->dmi_addr) >> 26);
342 gaht[bit >> 4] |= 0x8000 >> (bit & 0x0f);
343 }
344 out_be32(&p->gaht1, gaht[0]);
345 out_be32(&p->gaht2, gaht[1]);
346 out_be32(&p->gaht3, gaht[2]);
347 out_be32(&p->gaht4, gaht[3]);
348}
349
350static inline u32 emac_iff2rmr(struct net_device *ndev)
351{
352 struct emac_instance *dev = netdev_priv(ndev);
353 u32 r;
354
355 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
356
357 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
358 r |= EMAC4_RMR_BASE;
359 else
360 r |= EMAC_RMR_BASE;
361
362 if (ndev->flags & IFF_PROMISC)
363 r |= EMAC_RMR_PME;
364 else if (ndev->flags & IFF_ALLMULTI || ndev->mc_count > 32)
365 r |= EMAC_RMR_PMME;
366 else if (ndev->mc_count > 0)
367 r |= EMAC_RMR_MAE;
368
369 return r;
370}
371
372static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
373{
374 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
375
376 DBG2(dev, "__emac_calc_base_mr1" NL);
377
378 switch(tx_size) {
379 case 2048:
380 ret |= EMAC_MR1_TFS_2K;
381 break;
382 default:
383 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
384 dev->ndev->name, tx_size);
385 }
386
387 switch(rx_size) {
388 case 16384:
389 ret |= EMAC_MR1_RFS_16K;
390 break;
391 case 4096:
392 ret |= EMAC_MR1_RFS_4K;
393 break;
394 default:
395 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
396 dev->ndev->name, rx_size);
397 }
398
399 return ret;
400}
401
402static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
403{
404 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
405 EMAC4_MR1_OBCI(dev->opb_bus_freq);
406
407 DBG2(dev, "__emac4_calc_base_mr1" NL);
408
409 switch(tx_size) {
410 case 4096:
411 ret |= EMAC4_MR1_TFS_4K;
412 break;
413 case 2048:
414 ret |= EMAC4_MR1_TFS_2K;
415 break;
416 default:
417 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
418 dev->ndev->name, tx_size);
419 }
420
421 switch(rx_size) {
422 case 16384:
423 ret |= EMAC4_MR1_RFS_16K;
424 break;
425 case 4096:
426 ret |= EMAC4_MR1_RFS_4K;
427 break;
428 case 2048:
429 ret |= EMAC4_MR1_RFS_2K;
430 break;
431 default:
432 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
433 dev->ndev->name, rx_size);
434 }
435
436 return ret;
437}
438
439static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
440{
441 return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
442 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
443 __emac_calc_base_mr1(dev, tx_size, rx_size);
444}
445
446static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
447{
448 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
449 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
450 else
451 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
452}
453
454static inline u32 emac_calc_rwmr(struct emac_instance *dev,
455 unsigned int low, unsigned int high)
456{
457 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
458 return (low << 22) | ( (high & 0x3ff) << 6);
459 else
460 return (low << 23) | ( (high & 0x1ff) << 7);
461}
462
463static int emac_configure(struct emac_instance *dev)
464{
465 struct emac_regs __iomem *p = dev->emacp;
466 struct net_device *ndev = dev->ndev;
467 int tx_size, rx_size;
468 u32 r, mr1 = 0;
469
470 DBG(dev, "configure" NL);
471
472 if (emac_reset(dev) < 0)
473 return -ETIMEDOUT;
474
475 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
476 tah_reset(dev->tah_dev);
477
478 DBG(dev, " duplex = %d, pause = %d, asym_pause = %d\n",
479 dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
480
481 /* Default fifo sizes */
482 tx_size = dev->tx_fifo_size;
483 rx_size = dev->rx_fifo_size;
484
485 /* Check for full duplex */
486 if (dev->phy.duplex == DUPLEX_FULL)
487 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
488
489 /* Adjust fifo sizes, mr1 and timeouts based on link speed */
490 dev->stop_timeout = STOP_TIMEOUT_10;
491 switch (dev->phy.speed) {
492 case SPEED_1000:
493 if (emac_phy_gpcs(dev->phy.mode)) {
494 mr1 |= EMAC_MR1_MF_1000GPCS |
495 EMAC_MR1_MF_IPPA(dev->phy.address);
496
497 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
498 * identify this GPCS PHY later.
499 */
500 out_be32(&p->ipcr, 0xdeadbeef);
501 } else
502 mr1 |= EMAC_MR1_MF_1000;
503
504 /* Extended fifo sizes */
505 tx_size = dev->tx_fifo_size_gige;
506 rx_size = dev->rx_fifo_size_gige;
507
508 if (dev->ndev->mtu > ETH_DATA_LEN) {
509 mr1 |= EMAC_MR1_JPSM;
510 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
511 } else
512 dev->stop_timeout = STOP_TIMEOUT_1000;
513 break;
514 case SPEED_100:
515 mr1 |= EMAC_MR1_MF_100;
516 dev->stop_timeout = STOP_TIMEOUT_100;
517 break;
518 default: /* make gcc happy */
519 break;
520 }
521
522 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
523 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
524 dev->phy.speed);
525 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
526 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
527
528 /* on 40x erratum forces us to NOT use integrated flow control,
529 * let's hope it works on 44x ;)
530 */
531 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
532 dev->phy.duplex == DUPLEX_FULL) {
533 if (dev->phy.pause)
534 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
535 else if (dev->phy.asym_pause)
536 mr1 |= EMAC_MR1_APP;
537 }
538
539 /* Add base settings & fifo sizes & program MR1 */
540 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
541 out_be32(&p->mr1, mr1);
542
543 /* Set individual MAC address */
544 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
545 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
546 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
547 ndev->dev_addr[5]);
548
549 /* VLAN Tag Protocol ID */
550 out_be32(&p->vtpid, 0x8100);
551
552 /* Receive mode register */
553 r = emac_iff2rmr(ndev);
554 if (r & EMAC_RMR_MAE)
555 emac_hash_mc(dev);
556 out_be32(&p->rmr, r);
557
558 /* FIFOs thresholds */
559 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
560 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
561 tx_size / 2 / dev->fifo_entry_size);
562 else
563 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
564 tx_size / 2 / dev->fifo_entry_size);
565 out_be32(&p->tmr1, r);
566 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
567
568 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
569 there should be still enough space in FIFO to allow the our link
570 partner time to process this frame and also time to send PAUSE
571 frame itself.
572
573 Here is the worst case scenario for the RX FIFO "headroom"
574 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
575
576 1) One maximum-length frame on TX 1522 bytes
577 2) One PAUSE frame time 64 bytes
578 3) PAUSE frame decode time allowance 64 bytes
579 4) One maximum-length frame on RX 1522 bytes
580 5) Round-trip propagation delay of the link (100Mb) 15 bytes
581 ----------
582 3187 bytes
583
584 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
585 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
586 */
587 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
588 rx_size / 4 / dev->fifo_entry_size);
589 out_be32(&p->rwmr, r);
590
591 /* Set PAUSE timer to the maximum */
592 out_be32(&p->ptr, 0xffff);
593
594 /* IRQ sources */
595 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
596 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
597 EMAC_ISR_IRE | EMAC_ISR_TE;
598 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
599 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
600 EMAC4_ISR_RXOE | */;
601 out_be32(&p->iser, r);
602
603 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
604 if (emac_phy_gpcs(dev->phy.mode))
605 emac_mii_reset_phy(&dev->phy);
606
607 return 0;
608}
609
610static void emac_reinitialize(struct emac_instance *dev)
611{
612 DBG(dev, "reinitialize" NL);
613
614 emac_netif_stop(dev);
615 if (!emac_configure(dev)) {
616 emac_tx_enable(dev);
617 emac_rx_enable(dev);
618 }
619 emac_netif_start(dev);
620}
621
622static void emac_full_tx_reset(struct emac_instance *dev)
623{
624 DBG(dev, "full_tx_reset" NL);
625
626 emac_tx_disable(dev);
627 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
628 emac_clean_tx_ring(dev);
629 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
630
631 emac_configure(dev);
632
633 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
634 emac_tx_enable(dev);
635 emac_rx_enable(dev);
636}
637
638static void emac_reset_work(struct work_struct *work)
639{
640 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
641
642 DBG(dev, "reset_work" NL);
643
644 mutex_lock(&dev->link_lock);
645 emac_netif_stop(dev);
646 emac_full_tx_reset(dev);
647 emac_netif_start(dev);
648 mutex_unlock(&dev->link_lock);
649}
650
651static void emac_tx_timeout(struct net_device *ndev)
652{
653 struct emac_instance *dev = netdev_priv(ndev);
654
655 DBG(dev, "tx_timeout" NL);
656
657 schedule_work(&dev->reset_work);
658}
659
660
661static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
662{
663 int done = !!(stacr & EMAC_STACR_OC);
664
665 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
666 done = !done;
667
668 return done;
669};
670
671static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
672{
673 struct emac_regs __iomem *p = dev->emacp;
674 u32 r = 0;
675 int n, err = -ETIMEDOUT;
676
677 mutex_lock(&dev->mdio_lock);
678
679 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
680
681 /* Enable proper MDIO port */
682 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
683 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
684 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
685 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
686
687 /* Wait for management interface to become idle */
688 n = 10;
689 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
690 udelay(1);
691 if (!--n) {
692 DBG2(dev, " -> timeout wait idle\n");
693 goto bail;
694 }
695 }
696
697 /* Issue read command */
698 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
699 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
700 else
701 r = EMAC_STACR_BASE(dev->opb_bus_freq);
702 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
703 r |= EMAC_STACR_OC;
704 if (emac_has_feature(dev, EMAC_FTR_HAS_AXON_STACR))
705 r |= EMACX_STACR_STAC_READ;
706 else
707 r |= EMAC_STACR_STAC_READ;
708 r |= (reg & EMAC_STACR_PRA_MASK)
709 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
710 out_be32(&p->stacr, r);
711
712 /* Wait for read to complete */
713 n = 100;
714 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
715 udelay(1);
716 if (!--n) {
717 DBG2(dev, " -> timeout wait complete\n");
718 goto bail;
719 }
720 }
721
722 if (unlikely(r & EMAC_STACR_PHYE)) {
723 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
724 err = -EREMOTEIO;
725 goto bail;
726 }
727
728 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
729
730 DBG2(dev, "mdio_read -> %04x" NL, r);
731 err = 0;
732 bail:
733 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
734 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
735 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
736 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
737 mutex_unlock(&dev->mdio_lock);
738
739 return err == 0 ? r : err;
740}
741
742static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
743 u16 val)
744{
745 struct emac_regs __iomem *p = dev->emacp;
746 u32 r = 0;
747 int n, err = -ETIMEDOUT;
748
749 mutex_lock(&dev->mdio_lock);
750
751 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
752
753 /* Enable proper MDIO port */
754 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
755 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
756 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
757 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
758
759 /* Wait for management interface to be idle */
760 n = 10;
761 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
762 udelay(1);
763 if (!--n) {
764 DBG2(dev, " -> timeout wait idle\n");
765 goto bail;
766 }
767 }
768
769 /* Issue write command */
770 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
771 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
772 else
773 r = EMAC_STACR_BASE(dev->opb_bus_freq);
774 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
775 r |= EMAC_STACR_OC;
776 if (emac_has_feature(dev, EMAC_FTR_HAS_AXON_STACR))
777 r |= EMACX_STACR_STAC_WRITE;
778 else
779 r |= EMAC_STACR_STAC_WRITE;
780 r |= (reg & EMAC_STACR_PRA_MASK) |
781 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
782 (val << EMAC_STACR_PHYD_SHIFT);
783 out_be32(&p->stacr, r);
784
785 /* Wait for write to complete */
786 n = 100;
787 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
788 udelay(1);
789 if (!--n) {
790 DBG2(dev, " -> timeout wait complete\n");
791 goto bail;
792 }
793 }
794 err = 0;
795 bail:
796 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
797 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
798 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
799 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
800 mutex_unlock(&dev->mdio_lock);
801}
802
803static int emac_mdio_read(struct net_device *ndev, int id, int reg)
804{
805 struct emac_instance *dev = netdev_priv(ndev);
806 int res;
807
808 res = __emac_mdio_read(dev->mdio_instance ? dev->mdio_instance : dev,
809 (u8) id, (u8) reg);
810 return res;
811}
812
813static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
814{
815 struct emac_instance *dev = netdev_priv(ndev);
816
817 __emac_mdio_write(dev->mdio_instance ? dev->mdio_instance : dev,
818 (u8) id, (u8) reg, (u16) val);
819}
820
821/* Tx lock BH */
822static void __emac_set_multicast_list(struct emac_instance *dev)
823{
824 struct emac_regs __iomem *p = dev->emacp;
825 u32 rmr = emac_iff2rmr(dev->ndev);
826
827 DBG(dev, "__multicast %08x" NL, rmr);
828
829 /* I decided to relax register access rules here to avoid
830 * full EMAC reset.
831 *
832 * There is a real problem with EMAC4 core if we use MWSW_001 bit
833 * in MR1 register and do a full EMAC reset.
834 * One TX BD status update is delayed and, after EMAC reset, it
835 * never happens, resulting in TX hung (it'll be recovered by TX
836 * timeout handler eventually, but this is just gross).
837 * So we either have to do full TX reset or try to cheat here :)
838 *
839 * The only required change is to RX mode register, so I *think* all
840 * we need is just to stop RX channel. This seems to work on all
841 * tested SoCs. --ebs
842 *
843 * If we need the full reset, we might just trigger the workqueue
844 * and do it async... a bit nasty but should work --BenH
845 */
846 dev->mcast_pending = 0;
847 emac_rx_disable(dev);
848 if (rmr & EMAC_RMR_MAE)
849 emac_hash_mc(dev);
850 out_be32(&p->rmr, rmr);
851 emac_rx_enable(dev);
852}
853
854/* Tx lock BH */
855static void emac_set_multicast_list(struct net_device *ndev)
856{
857 struct emac_instance *dev = netdev_priv(ndev);
858
859 DBG(dev, "multicast" NL);
860
861 BUG_ON(!netif_running(dev->ndev));
862
863 if (dev->no_mcast) {
864 dev->mcast_pending = 1;
865 return;
866 }
867 __emac_set_multicast_list(dev);
868}
869
870static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
871{
872 int rx_sync_size = emac_rx_sync_size(new_mtu);
873 int rx_skb_size = emac_rx_skb_size(new_mtu);
874 int i, ret = 0;
875
876 mutex_lock(&dev->link_lock);
877 emac_netif_stop(dev);
878 emac_rx_disable(dev);
879 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
880
881 if (dev->rx_sg_skb) {
882 ++dev->estats.rx_dropped_resize;
883 dev_kfree_skb(dev->rx_sg_skb);
884 dev->rx_sg_skb = NULL;
885 }
886
887 /* Make a first pass over RX ring and mark BDs ready, dropping
888 * non-processed packets on the way. We need this as a separate pass
889 * to simplify error recovery in the case of allocation failure later.
890 */
891 for (i = 0; i < NUM_RX_BUFF; ++i) {
892 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
893 ++dev->estats.rx_dropped_resize;
894
895 dev->rx_desc[i].data_len = 0;
896 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
897 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
898 }
899
900 /* Reallocate RX ring only if bigger skb buffers are required */
901 if (rx_skb_size <= dev->rx_skb_size)
902 goto skip;
903
904 /* Second pass, allocate new skbs */
905 for (i = 0; i < NUM_RX_BUFF; ++i) {
906 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
907 if (!skb) {
908 ret = -ENOMEM;
909 goto oom;
910 }
911
912 BUG_ON(!dev->rx_skb[i]);
913 dev_kfree_skb(dev->rx_skb[i]);
914
915 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
916 dev->rx_desc[i].data_ptr =
917 dma_map_single(&dev->ofdev->dev, skb->data - 2, rx_sync_size,
918 DMA_FROM_DEVICE) + 2;
919 dev->rx_skb[i] = skb;
920 }
921 skip:
922 /* Check if we need to change "Jumbo" bit in MR1 */
923 if ((new_mtu > ETH_DATA_LEN) ^ (dev->ndev->mtu > ETH_DATA_LEN)) {
924 /* This is to prevent starting RX channel in emac_rx_enable() */
925 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
926
927 dev->ndev->mtu = new_mtu;
928 emac_full_tx_reset(dev);
929 }
930
931 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
932 oom:
933 /* Restart RX */
934 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
935 dev->rx_slot = 0;
936 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
937 emac_rx_enable(dev);
938 emac_netif_start(dev);
939 mutex_unlock(&dev->link_lock);
940
941 return ret;
942}
943
944/* Process ctx, rtnl_lock semaphore */
945static int emac_change_mtu(struct net_device *ndev, int new_mtu)
946{
947 struct emac_instance *dev = netdev_priv(ndev);
948 int ret = 0;
949
950 if (new_mtu < EMAC_MIN_MTU || new_mtu > dev->max_mtu)
951 return -EINVAL;
952
953 DBG(dev, "change_mtu(%d)" NL, new_mtu);
954
955 if (netif_running(ndev)) {
956 /* Check if we really need to reinitalize RX ring */
957 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
958 ret = emac_resize_rx_ring(dev, new_mtu);
959 }
960
961 if (!ret) {
962 ndev->mtu = new_mtu;
963 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
964 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
965 }
966
967 return ret;
968}
969
970static void emac_clean_tx_ring(struct emac_instance *dev)
971{
972 int i;
973
974 for (i = 0; i < NUM_TX_BUFF; ++i) {
975 if (dev->tx_skb[i]) {
976 dev_kfree_skb(dev->tx_skb[i]);
977 dev->tx_skb[i] = NULL;
978 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
979 ++dev->estats.tx_dropped;
980 }
981 dev->tx_desc[i].ctrl = 0;
982 dev->tx_desc[i].data_ptr = 0;
983 }
984}
985
986static void emac_clean_rx_ring(struct emac_instance *dev)
987{
988 int i;
989
990 for (i = 0; i < NUM_RX_BUFF; ++i)
991 if (dev->rx_skb[i]) {
992 dev->rx_desc[i].ctrl = 0;
993 dev_kfree_skb(dev->rx_skb[i]);
994 dev->rx_skb[i] = NULL;
995 dev->rx_desc[i].data_ptr = 0;
996 }
997
998 if (dev->rx_sg_skb) {
999 dev_kfree_skb(dev->rx_sg_skb);
1000 dev->rx_sg_skb = NULL;
1001 }
1002}
1003
1004static inline int emac_alloc_rx_skb(struct emac_instance *dev, int slot,
1005 gfp_t flags)
1006{
1007 struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
1008 if (unlikely(!skb))
1009 return -ENOMEM;
1010
1011 dev->rx_skb[slot] = skb;
1012 dev->rx_desc[slot].data_len = 0;
1013
1014 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1015 dev->rx_desc[slot].data_ptr =
1016 dma_map_single(&dev->ofdev->dev, skb->data - 2, dev->rx_sync_size,
1017 DMA_FROM_DEVICE) + 2;
1018 wmb();
1019 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1020 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1021
1022 return 0;
1023}
1024
1025static void emac_print_link_status(struct emac_instance *dev)
1026{
1027 if (netif_carrier_ok(dev->ndev))
1028 printk(KERN_INFO "%s: link is up, %d %s%s\n",
1029 dev->ndev->name, dev->phy.speed,
1030 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1031 dev->phy.pause ? ", pause enabled" :
1032 dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1033 else
1034 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1035}
1036
1037/* Process ctx, rtnl_lock semaphore */
1038static int emac_open(struct net_device *ndev)
1039{
1040 struct emac_instance *dev = netdev_priv(ndev);
1041 int err, i;
1042
1043 DBG(dev, "open" NL);
1044
1045 /* Setup error IRQ handler */
1046 err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev);
1047 if (err) {
1048 printk(KERN_ERR "%s: failed to request IRQ %d\n",
1049 ndev->name, dev->emac_irq);
1050 return err;
1051 }
1052
1053 /* Allocate RX ring */
1054 for (i = 0; i < NUM_RX_BUFF; ++i)
1055 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
1056 printk(KERN_ERR "%s: failed to allocate RX ring\n",
1057 ndev->name);
1058 goto oom;
1059 }
1060
1061 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1062 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1063 dev->rx_sg_skb = NULL;
1064
1065 mutex_lock(&dev->link_lock);
1066
1067 /* XXX Start PHY polling now. Shouldn't wr do like sungem instead and
1068 * always poll the PHY even when the iface is down ? That would allow
1069 * things like laptop-net to work. --BenH
1070 */
1071 if (dev->phy.address >= 0) {
1072 int link_poll_interval;
1073 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1074 dev->phy.def->ops->read_link(&dev->phy);
1075 netif_carrier_on(dev->ndev);
1076 link_poll_interval = PHY_POLL_LINK_ON;
1077 } else {
1078 netif_carrier_off(dev->ndev);
1079 link_poll_interval = PHY_POLL_LINK_OFF;
1080 }
1081 dev->link_polling = 1;
1082 wmb();
1083 schedule_delayed_work(&dev->link_work, link_poll_interval);
1084 emac_print_link_status(dev);
1085 } else
1086 netif_carrier_on(dev->ndev);
1087
1088 emac_configure(dev);
1089 mal_poll_add(dev->mal, &dev->commac);
1090 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1091 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1092 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1093 emac_tx_enable(dev);
1094 emac_rx_enable(dev);
1095 emac_netif_start(dev);
1096
1097 mutex_unlock(&dev->link_lock);
1098
1099 return 0;
1100 oom:
1101 emac_clean_rx_ring(dev);
1102 free_irq(dev->emac_irq, dev);
1103
1104 return -ENOMEM;
1105}
1106
1107/* BHs disabled */
1108#if 0
1109static int emac_link_differs(struct emac_instance *dev)
1110{
1111 u32 r = in_be32(&dev->emacp->mr1);
1112
1113 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1114 int speed, pause, asym_pause;
1115
1116 if (r & EMAC_MR1_MF_1000)
1117 speed = SPEED_1000;
1118 else if (r & EMAC_MR1_MF_100)
1119 speed = SPEED_100;
1120 else
1121 speed = SPEED_10;
1122
1123 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1124 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1125 pause = 1;
1126 asym_pause = 0;
1127 break;
1128 case EMAC_MR1_APP:
1129 pause = 0;
1130 asym_pause = 1;
1131 break;
1132 default:
1133 pause = asym_pause = 0;
1134 }
1135 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1136 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1137}
1138#endif
1139
1140static void emac_link_timer(struct work_struct *work)
1141{
1142 struct emac_instance *dev =
1143 container_of((struct delayed_work *)work,
1144 struct emac_instance, link_work);
1145 int link_poll_interval;
1146
1147 mutex_lock(&dev->link_lock);
1148
1149 DBG2(dev, "link timer" NL);
1150
1151 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1152 if (!netif_carrier_ok(dev->ndev)) {
1153 /* Get new link parameters */
1154 dev->phy.def->ops->read_link(&dev->phy);
1155
1156 netif_carrier_on(dev->ndev);
1157 emac_netif_stop(dev);
1158 emac_full_tx_reset(dev);
1159 emac_netif_start(dev);
1160 emac_print_link_status(dev);
1161 }
1162 link_poll_interval = PHY_POLL_LINK_ON;
1163 } else {
1164 if (netif_carrier_ok(dev->ndev)) {
1165 emac_reinitialize(dev);
1166 netif_carrier_off(dev->ndev);
1167 netif_tx_disable(dev->ndev);
1168 emac_print_link_status(dev);
1169 }
1170 link_poll_interval = PHY_POLL_LINK_OFF;
1171 }
1172 schedule_delayed_work(&dev->link_work, link_poll_interval);
1173
1174 mutex_unlock(&dev->link_lock);
1175}
1176
1177static void emac_force_link_update(struct emac_instance *dev)
1178{
1179 netif_carrier_off(dev->ndev);
1180 if (dev->link_polling) {
1181 cancel_rearming_delayed_work(&dev->link_work);
1182 if (dev->link_polling)
1183 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF);
1184 }
1185}
1186
1187/* Process ctx, rtnl_lock semaphore */
1188static int emac_close(struct net_device *ndev)
1189{
1190 struct emac_instance *dev = netdev_priv(ndev);
1191
1192 DBG(dev, "close" NL);
1193
1194 if (dev->phy.address >= 0)
1195 cancel_rearming_delayed_work(&dev->link_work);
1196
1197 emac_netif_stop(dev);
1198 flush_scheduled_work();
1199
1200 emac_rx_disable(dev);
1201 emac_tx_disable(dev);
1202 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1203 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1204 mal_poll_del(dev->mal, &dev->commac);
1205
1206 emac_clean_tx_ring(dev);
1207 emac_clean_rx_ring(dev);
1208
1209 free_irq(dev->emac_irq, dev);
1210
1211 return 0;
1212}
1213
1214static inline u16 emac_tx_csum(struct emac_instance *dev,
1215 struct sk_buff *skb)
1216{
1217 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH &&
1218 skb->ip_summed == CHECKSUM_PARTIAL)) {
1219 ++dev->stats.tx_packets_csum;
1220 return EMAC_TX_CTRL_TAH_CSUM;
1221 }
1222 return 0;
1223}
1224
1225static inline int emac_xmit_finish(struct emac_instance *dev, int len)
1226{
1227 struct emac_regs __iomem *p = dev->emacp;
1228 struct net_device *ndev = dev->ndev;
1229
1230 /* Send the packet out. If the if makes a significant perf
1231 * difference, then we can store the TMR0 value in "dev"
1232 * instead
1233 */
1234 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1235 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1236 else
1237 out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
1238
1239 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1240 netif_stop_queue(ndev);
1241 DBG2(dev, "stopped TX queue" NL);
1242 }
1243
1244 ndev->trans_start = jiffies;
1245 ++dev->stats.tx_packets;
1246 dev->stats.tx_bytes += len;
1247
1248 return 0;
1249}
1250
1251/* Tx lock BH */
1252static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1253{
1254 struct emac_instance *dev = netdev_priv(ndev);
1255 unsigned int len = skb->len;
1256 int slot;
1257
1258 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1259 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1260
1261 slot = dev->tx_slot++;
1262 if (dev->tx_slot == NUM_TX_BUFF) {
1263 dev->tx_slot = 0;
1264 ctrl |= MAL_TX_CTRL_WRAP;
1265 }
1266
1267 DBG2(dev, "xmit(%u) %d" NL, len, slot);
1268
1269 dev->tx_skb[slot] = skb;
1270 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1271 skb->data, len,
1272 DMA_TO_DEVICE);
1273 dev->tx_desc[slot].data_len = (u16) len;
1274 wmb();
1275 dev->tx_desc[slot].ctrl = ctrl;
1276
1277 return emac_xmit_finish(dev, len);
1278}
1279
1280#ifdef CONFIG_IBM_NEW_EMAC_TAH
1281static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1282 u32 pd, int len, int last, u16 base_ctrl)
1283{
1284 while (1) {
1285 u16 ctrl = base_ctrl;
1286 int chunk = min(len, MAL_MAX_TX_SIZE);
1287 len -= chunk;
1288
1289 slot = (slot + 1) % NUM_TX_BUFF;
1290
1291 if (last && !len)
1292 ctrl |= MAL_TX_CTRL_LAST;
1293 if (slot == NUM_TX_BUFF - 1)
1294 ctrl |= MAL_TX_CTRL_WRAP;
1295
1296 dev->tx_skb[slot] = NULL;
1297 dev->tx_desc[slot].data_ptr = pd;
1298 dev->tx_desc[slot].data_len = (u16) chunk;
1299 dev->tx_desc[slot].ctrl = ctrl;
1300 ++dev->tx_cnt;
1301
1302 if (!len)
1303 break;
1304
1305 pd += chunk;
1306 }
1307 return slot;
1308}
1309
1310/* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1311static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1312{
1313 struct emac_instance *dev = netdev_priv(ndev);
1314 int nr_frags = skb_shinfo(skb)->nr_frags;
1315 int len = skb->len, chunk;
1316 int slot, i;
1317 u16 ctrl;
1318 u32 pd;
1319
1320 /* This is common "fast" path */
1321 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1322 return emac_start_xmit(skb, ndev);
1323
1324 len -= skb->data_len;
1325
1326 /* Note, this is only an *estimation*, we can still run out of empty
1327 * slots because of the additional fragmentation into
1328 * MAL_MAX_TX_SIZE-sized chunks
1329 */
1330 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1331 goto stop_queue;
1332
1333 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1334 emac_tx_csum(dev, skb);
1335 slot = dev->tx_slot;
1336
1337 /* skb data */
1338 dev->tx_skb[slot] = NULL;
1339 chunk = min(len, MAL_MAX_TX_SIZE);
1340 dev->tx_desc[slot].data_ptr = pd =
1341 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1342 dev->tx_desc[slot].data_len = (u16) chunk;
1343 len -= chunk;
1344 if (unlikely(len))
1345 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1346 ctrl);
1347 /* skb fragments */
1348 for (i = 0; i < nr_frags; ++i) {
1349 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1350 len = frag->size;
1351
1352 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1353 goto undo_frame;
1354
1355 pd = dma_map_page(&dev->ofdev->dev, frag->page, frag->page_offset, len,
1356 DMA_TO_DEVICE);
1357
1358 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1359 ctrl);
1360 }
1361
1362 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1363
1364 /* Attach skb to the last slot so we don't release it too early */
1365 dev->tx_skb[slot] = skb;
1366
1367 /* Send the packet out */
1368 if (dev->tx_slot == NUM_TX_BUFF - 1)
1369 ctrl |= MAL_TX_CTRL_WRAP;
1370 wmb();
1371 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1372 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1373
1374 return emac_xmit_finish(dev, skb->len);
1375
1376 undo_frame:
1377 /* Well, too bad. Our previous estimation was overly optimistic.
1378 * Undo everything.
1379 */
1380 while (slot != dev->tx_slot) {
1381 dev->tx_desc[slot].ctrl = 0;
1382 --dev->tx_cnt;
1383 if (--slot < 0)
1384 slot = NUM_TX_BUFF - 1;
1385 }
1386 ++dev->estats.tx_undo;
1387
1388 stop_queue:
1389 netif_stop_queue(ndev);
1390 DBG2(dev, "stopped TX queue" NL);
1391 return 1;
1392}
1393#else
1394# define emac_start_xmit_sg emac_start_xmit
1395#endif /* !defined(CONFIG_IBM_NEW_EMAC_TAH) */
1396
1397/* Tx lock BHs */
1398static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1399{
1400 struct emac_error_stats *st = &dev->estats;
1401
1402 DBG(dev, "BD TX error %04x" NL, ctrl);
1403
1404 ++st->tx_bd_errors;
1405 if (ctrl & EMAC_TX_ST_BFCS)
1406 ++st->tx_bd_bad_fcs;
1407 if (ctrl & EMAC_TX_ST_LCS)
1408 ++st->tx_bd_carrier_loss;
1409 if (ctrl & EMAC_TX_ST_ED)
1410 ++st->tx_bd_excessive_deferral;
1411 if (ctrl & EMAC_TX_ST_EC)
1412 ++st->tx_bd_excessive_collisions;
1413 if (ctrl & EMAC_TX_ST_LC)
1414 ++st->tx_bd_late_collision;
1415 if (ctrl & EMAC_TX_ST_MC)
1416 ++st->tx_bd_multple_collisions;
1417 if (ctrl & EMAC_TX_ST_SC)
1418 ++st->tx_bd_single_collision;
1419 if (ctrl & EMAC_TX_ST_UR)
1420 ++st->tx_bd_underrun;
1421 if (ctrl & EMAC_TX_ST_SQE)
1422 ++st->tx_bd_sqe;
1423}
1424
1425static void emac_poll_tx(void *param)
1426{
1427 struct emac_instance *dev = param;
1428 u32 bad_mask;
1429
1430 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1431
1432 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1433 bad_mask = EMAC_IS_BAD_TX_TAH;
1434 else
1435 bad_mask = EMAC_IS_BAD_TX;
1436
1437 netif_tx_lock_bh(dev->ndev);
1438 if (dev->tx_cnt) {
1439 u16 ctrl;
1440 int slot = dev->ack_slot, n = 0;
1441 again:
1442 ctrl = dev->tx_desc[slot].ctrl;
1443 if (!(ctrl & MAL_TX_CTRL_READY)) {
1444 struct sk_buff *skb = dev->tx_skb[slot];
1445 ++n;
1446
1447 if (skb) {
1448 dev_kfree_skb(skb);
1449 dev->tx_skb[slot] = NULL;
1450 }
1451 slot = (slot + 1) % NUM_TX_BUFF;
1452
1453 if (unlikely(ctrl & bad_mask))
1454 emac_parse_tx_error(dev, ctrl);
1455
1456 if (--dev->tx_cnt)
1457 goto again;
1458 }
1459 if (n) {
1460 dev->ack_slot = slot;
1461 if (netif_queue_stopped(dev->ndev) &&
1462 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1463 netif_wake_queue(dev->ndev);
1464
1465 DBG2(dev, "tx %d pkts" NL, n);
1466 }
1467 }
1468 netif_tx_unlock_bh(dev->ndev);
1469}
1470
1471static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1472 int len)
1473{
1474 struct sk_buff *skb = dev->rx_skb[slot];
1475
1476 DBG2(dev, "recycle %d %d" NL, slot, len);
1477
1478 if (len)
1479 dma_map_single(&dev->ofdev->dev, skb->data - 2,
1480 EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
1481
1482 dev->rx_desc[slot].data_len = 0;
1483 wmb();
1484 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1485 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1486}
1487
1488static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1489{
1490 struct emac_error_stats *st = &dev->estats;
1491
1492 DBG(dev, "BD RX error %04x" NL, ctrl);
1493
1494 ++st->rx_bd_errors;
1495 if (ctrl & EMAC_RX_ST_OE)
1496 ++st->rx_bd_overrun;
1497 if (ctrl & EMAC_RX_ST_BP)
1498 ++st->rx_bd_bad_packet;
1499 if (ctrl & EMAC_RX_ST_RP)
1500 ++st->rx_bd_runt_packet;
1501 if (ctrl & EMAC_RX_ST_SE)
1502 ++st->rx_bd_short_event;
1503 if (ctrl & EMAC_RX_ST_AE)
1504 ++st->rx_bd_alignment_error;
1505 if (ctrl & EMAC_RX_ST_BFCS)
1506 ++st->rx_bd_bad_fcs;
1507 if (ctrl & EMAC_RX_ST_PTL)
1508 ++st->rx_bd_packet_too_long;
1509 if (ctrl & EMAC_RX_ST_ORE)
1510 ++st->rx_bd_out_of_range;
1511 if (ctrl & EMAC_RX_ST_IRE)
1512 ++st->rx_bd_in_range;
1513}
1514
1515static inline void emac_rx_csum(struct emac_instance *dev,
1516 struct sk_buff *skb, u16 ctrl)
1517{
1518#ifdef CONFIG_IBM_NEW_EMAC_TAH
1519 if (!ctrl && dev->tah_dev) {
1520 skb->ip_summed = CHECKSUM_UNNECESSARY;
1521 ++dev->stats.rx_packets_csum;
1522 }
1523#endif
1524}
1525
1526static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1527{
1528 if (likely(dev->rx_sg_skb != NULL)) {
1529 int len = dev->rx_desc[slot].data_len;
1530 int tot_len = dev->rx_sg_skb->len + len;
1531
1532 if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
1533 ++dev->estats.rx_dropped_mtu;
1534 dev_kfree_skb(dev->rx_sg_skb);
1535 dev->rx_sg_skb = NULL;
1536 } else {
1537 cacheable_memcpy(dev->rx_sg_skb->tail,
1538 dev->rx_skb[slot]->data, len);
1539 skb_put(dev->rx_sg_skb, len);
1540 emac_recycle_rx_skb(dev, slot, len);
1541 return 0;
1542 }
1543 }
1544 emac_recycle_rx_skb(dev, slot, 0);
1545 return -1;
1546}
1547
1548/* NAPI poll context */
1549static int emac_poll_rx(void *param, int budget)
1550{
1551 struct emac_instance *dev = param;
1552 int slot = dev->rx_slot, received = 0;
1553
1554 DBG2(dev, "poll_rx(%d)" NL, budget);
1555
1556 again:
1557 while (budget > 0) {
1558 int len;
1559 struct sk_buff *skb;
1560 u16 ctrl = dev->rx_desc[slot].ctrl;
1561
1562 if (ctrl & MAL_RX_CTRL_EMPTY)
1563 break;
1564
1565 skb = dev->rx_skb[slot];
1566 mb();
1567 len = dev->rx_desc[slot].data_len;
1568
1569 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1570 goto sg;
1571
1572 ctrl &= EMAC_BAD_RX_MASK;
1573 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1574 emac_parse_rx_error(dev, ctrl);
1575 ++dev->estats.rx_dropped_error;
1576 emac_recycle_rx_skb(dev, slot, 0);
1577 len = 0;
1578 goto next;
1579 }
1580
1581 if (len && len < EMAC_RX_COPY_THRESH) {
1582 struct sk_buff *copy_skb =
1583 alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
1584 if (unlikely(!copy_skb))
1585 goto oom;
1586
1587 skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
1588 cacheable_memcpy(copy_skb->data - 2, skb->data - 2,
1589 len + 2);
1590 emac_recycle_rx_skb(dev, slot, len);
1591 skb = copy_skb;
1592 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
1593 goto oom;
1594
1595 skb_put(skb, len);
1596 push_packet:
1597 skb->dev = dev->ndev;
1598 skb->protocol = eth_type_trans(skb, dev->ndev);
1599 emac_rx_csum(dev, skb, ctrl);
1600
1601 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1602 ++dev->estats.rx_dropped_stack;
1603 next:
1604 ++dev->stats.rx_packets;
1605 skip:
1606 dev->stats.rx_bytes += len;
1607 slot = (slot + 1) % NUM_RX_BUFF;
1608 --budget;
1609 ++received;
1610 continue;
1611 sg:
1612 if (ctrl & MAL_RX_CTRL_FIRST) {
1613 BUG_ON(dev->rx_sg_skb);
1614 if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
1615 DBG(dev, "rx OOM %d" NL, slot);
1616 ++dev->estats.rx_dropped_oom;
1617 emac_recycle_rx_skb(dev, slot, 0);
1618 } else {
1619 dev->rx_sg_skb = skb;
1620 skb_put(skb, len);
1621 }
1622 } else if (!emac_rx_sg_append(dev, slot) &&
1623 (ctrl & MAL_RX_CTRL_LAST)) {
1624
1625 skb = dev->rx_sg_skb;
1626 dev->rx_sg_skb = NULL;
1627
1628 ctrl &= EMAC_BAD_RX_MASK;
1629 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1630 emac_parse_rx_error(dev, ctrl);
1631 ++dev->estats.rx_dropped_error;
1632 dev_kfree_skb(skb);
1633 len = 0;
1634 } else
1635 goto push_packet;
1636 }
1637 goto skip;
1638 oom:
1639 DBG(dev, "rx OOM %d" NL, slot);
1640 /* Drop the packet and recycle skb */
1641 ++dev->estats.rx_dropped_oom;
1642 emac_recycle_rx_skb(dev, slot, 0);
1643 goto next;
1644 }
1645
1646 if (received) {
1647 DBG2(dev, "rx %d BDs" NL, received);
1648 dev->rx_slot = slot;
1649 }
1650
1651 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1652 mb();
1653 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1654 DBG2(dev, "rx restart" NL);
1655 received = 0;
1656 goto again;
1657 }
1658
1659 if (dev->rx_sg_skb) {
1660 DBG2(dev, "dropping partial rx packet" NL);
1661 ++dev->estats.rx_dropped_error;
1662 dev_kfree_skb(dev->rx_sg_skb);
1663 dev->rx_sg_skb = NULL;
1664 }
1665
1666 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1667 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1668 emac_rx_enable(dev);
1669 dev->rx_slot = 0;
1670 }
1671 return received;
1672}
1673
1674/* NAPI poll context */
1675static int emac_peek_rx(void *param)
1676{
1677 struct emac_instance *dev = param;
1678
1679 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1680}
1681
1682/* NAPI poll context */
1683static int emac_peek_rx_sg(void *param)
1684{
1685 struct emac_instance *dev = param;
1686
1687 int slot = dev->rx_slot;
1688 while (1) {
1689 u16 ctrl = dev->rx_desc[slot].ctrl;
1690 if (ctrl & MAL_RX_CTRL_EMPTY)
1691 return 0;
1692 else if (ctrl & MAL_RX_CTRL_LAST)
1693 return 1;
1694
1695 slot = (slot + 1) % NUM_RX_BUFF;
1696
1697 /* I'm just being paranoid here :) */
1698 if (unlikely(slot == dev->rx_slot))
1699 return 0;
1700 }
1701}
1702
1703/* Hard IRQ */
1704static void emac_rxde(void *param)
1705{
1706 struct emac_instance *dev = param;
1707
1708 ++dev->estats.rx_stopped;
1709 emac_rx_disable_async(dev);
1710}
1711
1712/* Hard IRQ */
1713static irqreturn_t emac_irq(int irq, void *dev_instance)
1714{
1715 struct emac_instance *dev = dev_instance;
1716 struct emac_regs __iomem *p = dev->emacp;
1717 struct emac_error_stats *st = &dev->estats;
1718 u32 isr;
1719
1720 spin_lock(&dev->lock);
1721
1722 isr = in_be32(&p->isr);
1723 out_be32(&p->isr, isr);
1724
1725 DBG(dev, "isr = %08x" NL, isr);
1726
1727 if (isr & EMAC4_ISR_TXPE)
1728 ++st->tx_parity;
1729 if (isr & EMAC4_ISR_RXPE)
1730 ++st->rx_parity;
1731 if (isr & EMAC4_ISR_TXUE)
1732 ++st->tx_underrun;
1733 if (isr & EMAC4_ISR_RXOE)
1734 ++st->rx_fifo_overrun;
1735 if (isr & EMAC_ISR_OVR)
1736 ++st->rx_overrun;
1737 if (isr & EMAC_ISR_BP)
1738 ++st->rx_bad_packet;
1739 if (isr & EMAC_ISR_RP)
1740 ++st->rx_runt_packet;
1741 if (isr & EMAC_ISR_SE)
1742 ++st->rx_short_event;
1743 if (isr & EMAC_ISR_ALE)
1744 ++st->rx_alignment_error;
1745 if (isr & EMAC_ISR_BFCS)
1746 ++st->rx_bad_fcs;
1747 if (isr & EMAC_ISR_PTLE)
1748 ++st->rx_packet_too_long;
1749 if (isr & EMAC_ISR_ORE)
1750 ++st->rx_out_of_range;
1751 if (isr & EMAC_ISR_IRE)
1752 ++st->rx_in_range;
1753 if (isr & EMAC_ISR_SQE)
1754 ++st->tx_sqe;
1755 if (isr & EMAC_ISR_TE)
1756 ++st->tx_errors;
1757
1758 spin_unlock(&dev->lock);
1759
1760 return IRQ_HANDLED;
1761}
1762
1763static struct net_device_stats *emac_stats(struct net_device *ndev)
1764{
1765 struct emac_instance *dev = netdev_priv(ndev);
1766 struct emac_stats *st = &dev->stats;
1767 struct emac_error_stats *est = &dev->estats;
1768 struct net_device_stats *nst = &dev->nstats;
1769 unsigned long flags;
1770
1771 DBG2(dev, "stats" NL);
1772
1773 /* Compute "legacy" statistics */
1774 spin_lock_irqsave(&dev->lock, flags);
1775 nst->rx_packets = (unsigned long)st->rx_packets;
1776 nst->rx_bytes = (unsigned long)st->rx_bytes;
1777 nst->tx_packets = (unsigned long)st->tx_packets;
1778 nst->tx_bytes = (unsigned long)st->tx_bytes;
1779 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1780 est->rx_dropped_error +
1781 est->rx_dropped_resize +
1782 est->rx_dropped_mtu);
1783 nst->tx_dropped = (unsigned long)est->tx_dropped;
1784
1785 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1786 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1787 est->rx_fifo_overrun +
1788 est->rx_overrun);
1789 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1790 est->rx_alignment_error);
1791 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1792 est->rx_bad_fcs);
1793 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1794 est->rx_bd_short_event +
1795 est->rx_bd_packet_too_long +
1796 est->rx_bd_out_of_range +
1797 est->rx_bd_in_range +
1798 est->rx_runt_packet +
1799 est->rx_short_event +
1800 est->rx_packet_too_long +
1801 est->rx_out_of_range +
1802 est->rx_in_range);
1803
1804 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1805 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1806 est->tx_underrun);
1807 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1808 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1809 est->tx_bd_excessive_collisions +
1810 est->tx_bd_late_collision +
1811 est->tx_bd_multple_collisions);
1812 spin_unlock_irqrestore(&dev->lock, flags);
1813 return nst;
1814}
1815
1816static struct mal_commac_ops emac_commac_ops = {
1817 .poll_tx = &emac_poll_tx,
1818 .poll_rx = &emac_poll_rx,
1819 .peek_rx = &emac_peek_rx,
1820 .rxde = &emac_rxde,
1821};
1822
1823static struct mal_commac_ops emac_commac_sg_ops = {
1824 .poll_tx = &emac_poll_tx,
1825 .poll_rx = &emac_poll_rx,
1826 .peek_rx = &emac_peek_rx_sg,
1827 .rxde = &emac_rxde,
1828};
1829
1830/* Ethtool support */
1831static int emac_ethtool_get_settings(struct net_device *ndev,
1832 struct ethtool_cmd *cmd)
1833{
1834 struct emac_instance *dev = netdev_priv(ndev);
1835
1836 cmd->supported = dev->phy.features;
1837 cmd->port = PORT_MII;
1838 cmd->phy_address = dev->phy.address;
1839 cmd->transceiver =
1840 dev->phy.address >= 0 ? XCVR_EXTERNAL : XCVR_INTERNAL;
1841
1842 mutex_lock(&dev->link_lock);
1843 cmd->advertising = dev->phy.advertising;
1844 cmd->autoneg = dev->phy.autoneg;
1845 cmd->speed = dev->phy.speed;
1846 cmd->duplex = dev->phy.duplex;
1847 mutex_unlock(&dev->link_lock);
1848
1849 return 0;
1850}
1851
1852static int emac_ethtool_set_settings(struct net_device *ndev,
1853 struct ethtool_cmd *cmd)
1854{
1855 struct emac_instance *dev = netdev_priv(ndev);
1856 u32 f = dev->phy.features;
1857
1858 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
1859 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1860
1861 /* Basic sanity checks */
1862 if (dev->phy.address < 0)
1863 return -EOPNOTSUPP;
1864 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1865 return -EINVAL;
1866 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1867 return -EINVAL;
1868 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1869 return -EINVAL;
1870
1871 if (cmd->autoneg == AUTONEG_DISABLE) {
1872 switch (cmd->speed) {
1873 case SPEED_10:
1874 if (cmd->duplex == DUPLEX_HALF
1875 && !(f & SUPPORTED_10baseT_Half))
1876 return -EINVAL;
1877 if (cmd->duplex == DUPLEX_FULL
1878 && !(f & SUPPORTED_10baseT_Full))
1879 return -EINVAL;
1880 break;
1881 case SPEED_100:
1882 if (cmd->duplex == DUPLEX_HALF
1883 && !(f & SUPPORTED_100baseT_Half))
1884 return -EINVAL;
1885 if (cmd->duplex == DUPLEX_FULL
1886 && !(f & SUPPORTED_100baseT_Full))
1887 return -EINVAL;
1888 break;
1889 case SPEED_1000:
1890 if (cmd->duplex == DUPLEX_HALF
1891 && !(f & SUPPORTED_1000baseT_Half))
1892 return -EINVAL;
1893 if (cmd->duplex == DUPLEX_FULL
1894 && !(f & SUPPORTED_1000baseT_Full))
1895 return -EINVAL;
1896 break;
1897 default:
1898 return -EINVAL;
1899 }
1900
1901 mutex_lock(&dev->link_lock);
1902 dev->phy.def->ops->setup_forced(&dev->phy, cmd->speed,
1903 cmd->duplex);
1904 mutex_unlock(&dev->link_lock);
1905
1906 } else {
1907 if (!(f & SUPPORTED_Autoneg))
1908 return -EINVAL;
1909
1910 mutex_lock(&dev->link_lock);
1911 dev->phy.def->ops->setup_aneg(&dev->phy,
1912 (cmd->advertising & f) |
1913 (dev->phy.advertising &
1914 (ADVERTISED_Pause |
1915 ADVERTISED_Asym_Pause)));
1916 mutex_unlock(&dev->link_lock);
1917 }
1918 emac_force_link_update(dev);
1919
1920 return 0;
1921}
1922
1923static void emac_ethtool_get_ringparam(struct net_device *ndev,
1924 struct ethtool_ringparam *rp)
1925{
1926 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
1927 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
1928}
1929
1930static void emac_ethtool_get_pauseparam(struct net_device *ndev,
1931 struct ethtool_pauseparam *pp)
1932{
1933 struct emac_instance *dev = netdev_priv(ndev);
1934
1935 mutex_lock(&dev->link_lock);
1936 if ((dev->phy.features & SUPPORTED_Autoneg) &&
1937 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
1938 pp->autoneg = 1;
1939
1940 if (dev->phy.duplex == DUPLEX_FULL) {
1941 if (dev->phy.pause)
1942 pp->rx_pause = pp->tx_pause = 1;
1943 else if (dev->phy.asym_pause)
1944 pp->tx_pause = 1;
1945 }
1946 mutex_unlock(&dev->link_lock);
1947}
1948
1949static u32 emac_ethtool_get_rx_csum(struct net_device *ndev)
1950{
1951 struct emac_instance *dev = netdev_priv(ndev);
1952
1953 return dev->tah_dev != 0;
1954}
1955
1956static int emac_get_regs_len(struct emac_instance *dev)
1957{
1958 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1959 return sizeof(struct emac_ethtool_regs_subhdr) +
1960 EMAC4_ETHTOOL_REGS_SIZE;
1961 else
1962 return sizeof(struct emac_ethtool_regs_subhdr) +
1963 EMAC_ETHTOOL_REGS_SIZE;
1964}
1965
1966static int emac_ethtool_get_regs_len(struct net_device *ndev)
1967{
1968 struct emac_instance *dev = netdev_priv(ndev);
1969 int size;
1970
1971 size = sizeof(struct emac_ethtool_regs_hdr) +
1972 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
1973 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
1974 size += zmii_get_regs_len(dev->zmii_dev);
1975 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
1976 size += rgmii_get_regs_len(dev->rgmii_dev);
1977 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1978 size += tah_get_regs_len(dev->tah_dev);
1979
1980 return size;
1981}
1982
1983static void *emac_dump_regs(struct emac_instance *dev, void *buf)
1984{
1985 struct emac_ethtool_regs_subhdr *hdr = buf;
1986
1987 hdr->index = dev->cell_index;
1988 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
1989 hdr->version = EMAC4_ETHTOOL_REGS_VER;
1990 memcpy_fromio(hdr + 1, dev->emacp, EMAC4_ETHTOOL_REGS_SIZE);
1991 return ((void *)(hdr + 1) + EMAC4_ETHTOOL_REGS_SIZE);
1992 } else {
1993 hdr->version = EMAC_ETHTOOL_REGS_VER;
1994 memcpy_fromio(hdr + 1, dev->emacp, EMAC_ETHTOOL_REGS_SIZE);
1995 return ((void *)(hdr + 1) + EMAC_ETHTOOL_REGS_SIZE);
1996 }
1997}
1998
1999static void emac_ethtool_get_regs(struct net_device *ndev,
2000 struct ethtool_regs *regs, void *buf)
2001{
2002 struct emac_instance *dev = netdev_priv(ndev);
2003 struct emac_ethtool_regs_hdr *hdr = buf;
2004
2005 hdr->components = 0;
2006 buf = hdr + 1;
2007
2008 buf = mal_dump_regs(dev->mal, buf);
2009 buf = emac_dump_regs(dev, buf);
2010 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2011 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2012 buf = zmii_dump_regs(dev->zmii_dev, buf);
2013 }
2014 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2015 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2016 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2017 }
2018 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2019 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2020 buf = tah_dump_regs(dev->tah_dev, buf);
2021 }
2022}
2023
2024static int emac_ethtool_nway_reset(struct net_device *ndev)
2025{
2026 struct emac_instance *dev = netdev_priv(ndev);
2027 int res = 0;
2028
2029 DBG(dev, "nway_reset" NL);
2030
2031 if (dev->phy.address < 0)
2032 return -EOPNOTSUPP;
2033
2034 mutex_lock(&dev->link_lock);
2035 if (!dev->phy.autoneg) {
2036 res = -EINVAL;
2037 goto out;
2038 }
2039
2040 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2041 out:
2042 mutex_unlock(&dev->link_lock);
2043 emac_force_link_update(dev);
2044 return res;
2045}
2046
2047static int emac_ethtool_get_stats_count(struct net_device *ndev)
2048{
2049 return EMAC_ETHTOOL_STATS_COUNT;
2050}
2051
2052static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2053 u8 * buf)
2054{
2055 if (stringset == ETH_SS_STATS)
2056 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2057}
2058
2059static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2060 struct ethtool_stats *estats,
2061 u64 * tmp_stats)
2062{
2063 struct emac_instance *dev = netdev_priv(ndev);
2064
2065 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2066 tmp_stats += sizeof(dev->stats) / sizeof(u64);
2067 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2068}
2069
2070static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2071 struct ethtool_drvinfo *info)
2072{
2073 struct emac_instance *dev = netdev_priv(ndev);
2074
2075 strcpy(info->driver, "ibm_emac");
2076 strcpy(info->version, DRV_VERSION);
2077 info->fw_version[0] = '\0';
2078 sprintf(info->bus_info, "PPC 4xx EMAC-%d %s",
2079 dev->cell_index, dev->ofdev->node->full_name);
2080 info->n_stats = emac_ethtool_get_stats_count(ndev);
2081 info->regdump_len = emac_ethtool_get_regs_len(ndev);
2082}
2083
2084static const struct ethtool_ops emac_ethtool_ops = {
2085 .get_settings = emac_ethtool_get_settings,
2086 .set_settings = emac_ethtool_set_settings,
2087 .get_drvinfo = emac_ethtool_get_drvinfo,
2088
2089 .get_regs_len = emac_ethtool_get_regs_len,
2090 .get_regs = emac_ethtool_get_regs,
2091
2092 .nway_reset = emac_ethtool_nway_reset,
2093
2094 .get_ringparam = emac_ethtool_get_ringparam,
2095 .get_pauseparam = emac_ethtool_get_pauseparam,
2096
2097 .get_rx_csum = emac_ethtool_get_rx_csum,
2098
2099 .get_strings = emac_ethtool_get_strings,
2100 .get_stats_count = emac_ethtool_get_stats_count,
2101 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2102
2103 .get_link = ethtool_op_get_link,
2104 .get_tx_csum = ethtool_op_get_tx_csum,
2105 .get_sg = ethtool_op_get_sg,
2106};
2107
2108static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2109{
2110 struct emac_instance *dev = netdev_priv(ndev);
2111 uint16_t *data = (uint16_t *) & rq->ifr_ifru;
2112
2113 DBG(dev, "ioctl %08x" NL, cmd);
2114
2115 if (dev->phy.address < 0)
2116 return -EOPNOTSUPP;
2117
2118 switch (cmd) {
2119 case SIOCGMIIPHY:
2120 case SIOCDEVPRIVATE:
2121 data[0] = dev->phy.address;
2122 /* Fall through */
2123 case SIOCGMIIREG:
2124 case SIOCDEVPRIVATE + 1:
2125 data[3] = emac_mdio_read(ndev, dev->phy.address, data[1]);
2126 return 0;
2127
2128 case SIOCSMIIREG:
2129 case SIOCDEVPRIVATE + 2:
2130 if (!capable(CAP_NET_ADMIN))
2131 return -EPERM;
2132 emac_mdio_write(ndev, dev->phy.address, data[1], data[2]);
2133 return 0;
2134 default:
2135 return -EOPNOTSUPP;
2136 }
2137}
2138
2139struct emac_depentry {
2140 u32 phandle;
2141 struct device_node *node;
2142 struct of_device *ofdev;
2143 void *drvdata;
2144};
2145
2146#define EMAC_DEP_MAL_IDX 0
2147#define EMAC_DEP_ZMII_IDX 1
2148#define EMAC_DEP_RGMII_IDX 2
2149#define EMAC_DEP_TAH_IDX 3
2150#define EMAC_DEP_MDIO_IDX 4
2151#define EMAC_DEP_PREV_IDX 5
2152#define EMAC_DEP_COUNT 6
2153
2154static int __devinit emac_check_deps(struct emac_instance *dev,
2155 struct emac_depentry *deps)
2156{
2157 int i, there = 0;
2158 struct device_node *np;
2159
2160 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2161 /* no dependency on that item, allright */
2162 if (deps[i].phandle == 0) {
2163 there++;
2164 continue;
2165 }
2166 /* special case for blist as the dependency might go away */
2167 if (i == EMAC_DEP_PREV_IDX) {
2168 np = *(dev->blist - 1);
2169 if (np == NULL) {
2170 deps[i].phandle = 0;
2171 there++;
2172 continue;
2173 }
2174 if (deps[i].node == NULL)
2175 deps[i].node = of_node_get(np);
2176 }
2177 if (deps[i].node == NULL)
2178 deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2179 if (deps[i].node == NULL)
2180 continue;
2181 if (deps[i].ofdev == NULL)
2182 deps[i].ofdev = of_find_device_by_node(deps[i].node);
2183 if (deps[i].ofdev == NULL)
2184 continue;
2185 if (deps[i].drvdata == NULL)
2186 deps[i].drvdata = dev_get_drvdata(&deps[i].ofdev->dev);
2187 if (deps[i].drvdata != NULL)
2188 there++;
2189 }
2190 return (there == EMAC_DEP_COUNT);
2191}
2192
2193static void emac_put_deps(struct emac_instance *dev)
2194{
2195 if (dev->mal_dev)
2196 of_dev_put(dev->mal_dev);
2197 if (dev->zmii_dev)
2198 of_dev_put(dev->zmii_dev);
2199 if (dev->rgmii_dev)
2200 of_dev_put(dev->rgmii_dev);
2201 if (dev->mdio_dev)
2202 of_dev_put(dev->mdio_dev);
2203 if (dev->tah_dev)
2204 of_dev_put(dev->tah_dev);
2205}
2206
2207static int __devinit emac_of_bus_notify(struct notifier_block *nb,
2208 unsigned long action, void *data)
2209{
2210 /* We are only intereted in device addition */
2211 if (action == BUS_NOTIFY_BOUND_DRIVER)
2212 wake_up_all(&emac_probe_wait);
2213 return 0;
2214}
2215
2216static struct notifier_block emac_of_bus_notifier = {
2217 .notifier_call = emac_of_bus_notify
2218};
2219
2220static int __devinit emac_wait_deps(struct emac_instance *dev)
2221{
2222 struct emac_depentry deps[EMAC_DEP_COUNT];
2223 int i, err;
2224
2225 memset(&deps, 0, sizeof(deps));
2226
2227 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2228 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2229 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2230 if (dev->tah_ph)
2231 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2232 if (dev->mdio_ph)
2233 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2234 if (dev->blist && dev->blist > emac_boot_list)
2235 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2236 bus_register_notifier(&of_platform_bus_type, &emac_of_bus_notifier);
2237 wait_event_timeout(emac_probe_wait,
2238 emac_check_deps(dev, deps),
2239 EMAC_PROBE_DEP_TIMEOUT);
2240 bus_unregister_notifier(&of_platform_bus_type, &emac_of_bus_notifier);
2241 err = emac_check_deps(dev, deps) ? 0 : -ENODEV;
2242 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2243 if (deps[i].node)
2244 of_node_put(deps[i].node);
2245 if (err && deps[i].ofdev)
2246 of_dev_put(deps[i].ofdev);
2247 }
2248 if (err == 0) {
2249 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2250 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2251 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2252 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2253 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2254 }
2255 if (deps[EMAC_DEP_PREV_IDX].ofdev)
2256 of_dev_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2257 return err;
2258}
2259
2260static int __devinit emac_read_uint_prop(struct device_node *np, const char *name,
2261 u32 *val, int fatal)
2262{
2263 int len;
2264 const u32 *prop = of_get_property(np, name, &len);
2265 if (prop == NULL || len < sizeof(u32)) {
2266 if (fatal)
2267 printk(KERN_ERR "%s: missing %s property\n",
2268 np->full_name, name);
2269 return -ENODEV;
2270 }
2271 *val = *prop;
2272 return 0;
2273}
2274
2275static int __devinit emac_init_phy(struct emac_instance *dev)
2276{
2277 struct device_node *np = dev->ofdev->node;
2278 struct net_device *ndev = dev->ndev;
2279 u32 phy_map, adv;
2280 int i;
2281
2282 dev->phy.dev = ndev;
2283 dev->phy.mode = dev->phy_mode;
2284
2285 /* PHY-less configuration.
2286 * XXX I probably should move these settings to the dev tree
2287 */
2288 if (dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) {
2289 emac_reset(dev);
2290
2291 /* PHY-less configuration.
2292 * XXX I probably should move these settings to the dev tree
2293 */
2294 dev->phy.address = -1;
2295 dev->phy.features = SUPPORTED_100baseT_Full | SUPPORTED_MII;
2296 dev->phy.pause = 1;
2297
2298 return 0;
2299 }
2300
2301 mutex_lock(&emac_phy_map_lock);
2302 phy_map = dev->phy_map | busy_phy_map;
2303
2304 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2305
2306 dev->phy.mdio_read = emac_mdio_read;
2307 dev->phy.mdio_write = emac_mdio_write;
2308
2309 /* Configure EMAC with defaults so we can at least use MDIO
2310 * This is needed mostly for 440GX
2311 */
2312 if (emac_phy_gpcs(dev->phy.mode)) {
2313 /* XXX
2314 * Make GPCS PHY address equal to EMAC index.
2315 * We probably should take into account busy_phy_map
2316 * and/or phy_map here.
2317 *
2318 * Note that the busy_phy_map is currently global
2319 * while it should probably be per-ASIC...
2320 */
2321 dev->phy.address = dev->cell_index;
2322 }
2323
2324 emac_configure(dev);
2325
2326 if (dev->phy_address != 0xffffffff)
2327 phy_map = ~(1 << dev->phy_address);
2328
2329 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2330 if (!(phy_map & 1)) {
2331 int r;
2332 busy_phy_map |= 1 << i;
2333
2334 /* Quick check if there is a PHY at the address */
2335 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2336 if (r == 0xffff || r < 0)
2337 continue;
2338 if (!emac_mii_phy_probe(&dev->phy, i))
2339 break;
2340 }
2341 mutex_unlock(&emac_phy_map_lock);
2342 if (i == 0x20) {
2343 printk(KERN_WARNING "%s: can't find PHY!\n", np->full_name);
2344 return -ENXIO;
2345 }
2346
2347 /* Init PHY */
2348 if (dev->phy.def->ops->init)
2349 dev->phy.def->ops->init(&dev->phy);
2350
2351 /* Disable any PHY features not supported by the platform */
2352 dev->phy.def->features &= ~dev->phy_feat_exc;
2353
2354 /* Setup initial link parameters */
2355 if (dev->phy.features & SUPPORTED_Autoneg) {
2356 adv = dev->phy.features;
2357 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2358 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2359 /* Restart autonegotiation */
2360 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2361 } else {
2362 u32 f = dev->phy.def->features;
2363 int speed = SPEED_10, fd = DUPLEX_HALF;
2364
2365 /* Select highest supported speed/duplex */
2366 if (f & SUPPORTED_1000baseT_Full) {
2367 speed = SPEED_1000;
2368 fd = DUPLEX_FULL;
2369 } else if (f & SUPPORTED_1000baseT_Half)
2370 speed = SPEED_1000;
2371 else if (f & SUPPORTED_100baseT_Full) {
2372 speed = SPEED_100;
2373 fd = DUPLEX_FULL;
2374 } else if (f & SUPPORTED_100baseT_Half)
2375 speed = SPEED_100;
2376 else if (f & SUPPORTED_10baseT_Full)
2377 fd = DUPLEX_FULL;
2378
2379 /* Force link parameters */
2380 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2381 }
2382 return 0;
2383}
2384
2385static int __devinit emac_init_config(struct emac_instance *dev)
2386{
2387 struct device_node *np = dev->ofdev->node;
2388 const void *p;
2389 unsigned int plen;
2390 const char *pm, *phy_modes[] = {
2391 [PHY_MODE_NA] = "",
2392 [PHY_MODE_MII] = "mii",
2393 [PHY_MODE_RMII] = "rmii",
2394 [PHY_MODE_SMII] = "smii",
2395 [PHY_MODE_RGMII] = "rgmii",
2396 [PHY_MODE_TBI] = "tbi",
2397 [PHY_MODE_GMII] = "gmii",
2398 [PHY_MODE_RTBI] = "rtbi",
2399 [PHY_MODE_SGMII] = "sgmii",
2400 };
2401
2402 /* Read config from device-tree */
2403 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2404 return -ENXIO;
2405 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2406 return -ENXIO;
2407 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2408 return -ENXIO;
2409 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2410 return -ENXIO;
2411 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2412 dev->max_mtu = 1500;
2413 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2414 dev->rx_fifo_size = 2048;
2415 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2416 dev->tx_fifo_size = 2048;
2417 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2418 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2419 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2420 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2421 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2422 dev->phy_address = 0xffffffff;
2423 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2424 dev->phy_map = 0xffffffff;
2425 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2426 return -ENXIO;
2427 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2428 dev->tah_ph = 0;
2429 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
2430 dev->tah_ph = 0;
2431 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2432 dev->mdio_ph = 0;
2433 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2434 dev->zmii_ph = 0;;
2435 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2436 dev->zmii_port = 0xffffffff;;
2437 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2438 dev->rgmii_ph = 0;;
2439 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2440 dev->rgmii_port = 0xffffffff;;
2441 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2442 dev->fifo_entry_size = 16;
2443 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2444 dev->mal_burst_size = 256;
2445
2446 /* PHY mode needs some decoding */
2447 dev->phy_mode = PHY_MODE_NA;
2448 pm = of_get_property(np, "phy-mode", &plen);
2449 if (pm != NULL) {
2450 int i;
2451 for (i = 0; i < ARRAY_SIZE(phy_modes); i++)
2452 if (!strcasecmp(pm, phy_modes[i])) {
2453 dev->phy_mode = i;
2454 break;
2455 }
2456 }
2457
2458 /* Backward compat with non-final DT */
2459 if (dev->phy_mode == PHY_MODE_NA && pm != NULL && plen == 4) {
2460 u32 nmode = *(const u32 *)pm;
2461 if (nmode > PHY_MODE_NA && nmode <= PHY_MODE_SGMII)
2462 dev->phy_mode = nmode;
2463 }
2464
2465 /* Check EMAC version */
2466 if (of_device_is_compatible(np, "ibm,emac4"))
2467 dev->features |= EMAC_FTR_EMAC4;
2468 if (of_device_is_compatible(np, "ibm,emac-axon")
2469 || of_device_is_compatible(np, "ibm,emac-440epx"))
2470 dev->features |= EMAC_FTR_HAS_AXON_STACR
2471 | EMAC_FTR_STACR_OC_INVERT;
2472 if (of_device_is_compatible(np, "ibm,emac-440spe"))
2473 dev->features |= EMAC_FTR_STACR_OC_INVERT;
2474
2475 /* Fixup some feature bits based on the device tree and verify
2476 * we have support for them compiled in
2477 */
2478 if (dev->tah_ph != 0) {
2479#ifdef CONFIG_IBM_NEW_EMAC_TAH
2480 dev->features |= EMAC_FTR_HAS_TAH;
2481#else
2482 printk(KERN_ERR "%s: TAH support not enabled !\n",
2483 np->full_name);
2484 return -ENXIO;
2485#endif
2486 }
2487
2488 if (dev->zmii_ph != 0) {
2489#ifdef CONFIG_IBM_NEW_EMAC_ZMII
2490 dev->features |= EMAC_FTR_HAS_ZMII;
2491#else
2492 printk(KERN_ERR "%s: ZMII support not enabled !\n",
2493 np->full_name);
2494 return -ENXIO;
2495#endif
2496 }
2497
2498 if (dev->rgmii_ph != 0) {
2499#ifdef CONFIG_IBM_NEW_EMAC_RGMII
2500 dev->features |= EMAC_FTR_HAS_RGMII;
2501#else
2502 printk(KERN_ERR "%s: RGMII support not enabled !\n",
2503 np->full_name);
2504 return -ENXIO;
2505#endif
2506 }
2507
2508 /* Read MAC-address */
2509 p = of_get_property(np, "local-mac-address", NULL);
2510 if (p == NULL) {
2511 printk(KERN_ERR "%s: Can't find local-mac-address property\n",
2512 np->full_name);
2513 return -ENXIO;
2514 }
2515 memcpy(dev->ndev->dev_addr, p, 6);
2516
2517 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
2518 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
2519 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
2520 DBG(dev, "max_mtu : %d\n", dev->max_mtu);
2521 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq);
2522
2523 return 0;
2524}
2525
2526static int __devinit emac_probe(struct of_device *ofdev,
2527 const struct of_device_id *match)
2528{
2529 struct net_device *ndev;
2530 struct emac_instance *dev;
2531 struct device_node *np = ofdev->node;
2532 struct device_node **blist = NULL;
2533 int err, i;
2534
2535 /* Find ourselves in the bootlist if we are there */
2536 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
2537 if (emac_boot_list[i] == np)
2538 blist = &emac_boot_list[i];
2539
2540 /* Allocate our net_device structure */
2541 err = -ENOMEM;
2542 ndev = alloc_etherdev(sizeof(struct emac_instance));
2543 if (!ndev) {
2544 printk(KERN_ERR "%s: could not allocate ethernet device!\n",
2545 np->full_name);
2546 goto err_gone;
2547 }
2548 dev = netdev_priv(ndev);
2549 dev->ndev = ndev;
2550 dev->ofdev = ofdev;
2551 dev->blist = blist;
2552 SET_MODULE_OWNER(ndev);
2553 SET_NETDEV_DEV(ndev, &ofdev->dev);
2554
2555 /* Initialize some embedded data structures */
2556 mutex_init(&dev->mdio_lock);
2557 mutex_init(&dev->link_lock);
2558 spin_lock_init(&dev->lock);
2559 INIT_WORK(&dev->reset_work, emac_reset_work);
2560
2561 /* Init various config data based on device-tree */
2562 err = emac_init_config(dev);
2563 if (err != 0)
2564 goto err_free;
2565
2566 /* Get interrupts. EMAC irq is mandatory, WOL irq is optional */
2567 dev->emac_irq = irq_of_parse_and_map(np, 0);
2568 dev->wol_irq = irq_of_parse_and_map(np, 1);
2569 if (dev->emac_irq == NO_IRQ) {
2570 printk(KERN_ERR "%s: Can't map main interrupt\n", np->full_name);
2571 goto err_free;
2572 }
2573 ndev->irq = dev->emac_irq;
2574
2575 /* Map EMAC regs */
2576 if (of_address_to_resource(np, 0, &dev->rsrc_regs)) {
2577 printk(KERN_ERR "%s: Can't get registers address\n",
2578 np->full_name);
2579 goto err_irq_unmap;
2580 }
2581 // TODO : request_mem_region
2582 dev->emacp = ioremap(dev->rsrc_regs.start, sizeof(struct emac_regs));
2583 if (dev->emacp == NULL) {
2584 printk(KERN_ERR "%s: Can't map device registers!\n",
2585 np->full_name);
2586 err = -ENOMEM;
2587 goto err_irq_unmap;
2588 }
2589
2590 /* Wait for dependent devices */
2591 err = emac_wait_deps(dev);
2592 if (err) {
2593 printk(KERN_ERR
2594 "%s: Timeout waiting for dependent devices\n",
2595 np->full_name);
2596 /* display more info about what's missing ? */
2597 goto err_reg_unmap;
2598 }
2599 dev->mal = dev_get_drvdata(&dev->mal_dev->dev);
2600 if (dev->mdio_dev != NULL)
2601 dev->mdio_instance = dev_get_drvdata(&dev->mdio_dev->dev);
2602
2603 /* Register with MAL */
2604 dev->commac.ops = &emac_commac_ops;
2605 dev->commac.dev = dev;
2606 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
2607 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
2608 err = mal_register_commac(dev->mal, &dev->commac);
2609 if (err) {
2610 printk(KERN_ERR "%s: failed to register with mal %s!\n",
2611 np->full_name, dev->mal_dev->node->full_name);
2612 goto err_rel_deps;
2613 }
2614 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
2615 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
2616
2617 /* Get pointers to BD rings */
2618 dev->tx_desc =
2619 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
2620 dev->rx_desc =
2621 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
2622
2623 DBG(dev, "tx_desc %p" NL, dev->tx_desc);
2624 DBG(dev, "rx_desc %p" NL, dev->rx_desc);
2625
2626 /* Clean rings */
2627 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
2628 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
2629
2630 /* Attach to ZMII, if needed */
2631 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
2632 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
2633 goto err_unreg_commac;
2634
2635 /* Attach to RGMII, if needed */
2636 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
2637 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
2638 goto err_detach_zmii;
2639
2640 /* Attach to TAH, if needed */
2641 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
2642 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
2643 goto err_detach_rgmii;
2644
2645 /* Set some link defaults before we can find out real parameters */
2646 dev->phy.speed = SPEED_100;
2647 dev->phy.duplex = DUPLEX_FULL;
2648 dev->phy.autoneg = AUTONEG_DISABLE;
2649 dev->phy.pause = dev->phy.asym_pause = 0;
2650 dev->stop_timeout = STOP_TIMEOUT_100;
2651 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
2652
2653 /* Find PHY if any */
2654 err = emac_init_phy(dev);
2655 if (err != 0)
2656 goto err_detach_tah;
2657
2658 /* Fill in the driver function table */
2659 ndev->open = &emac_open;
2660#ifdef CONFIG_IBM_NEW_EMAC_TAH
2661 if (dev->tah_dev) {
2662 ndev->hard_start_xmit = &emac_start_xmit_sg;
2663 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2664 } else
2665#endif
2666 ndev->hard_start_xmit = &emac_start_xmit;
2667 ndev->tx_timeout = &emac_tx_timeout;
2668 ndev->watchdog_timeo = 5 * HZ;
2669 ndev->stop = &emac_close;
2670 ndev->get_stats = &emac_stats;
2671 ndev->set_multicast_list = &emac_set_multicast_list;
2672 ndev->do_ioctl = &emac_ioctl;
2673 if (emac_phy_supports_gige(dev->phy_mode)) {
2674 ndev->change_mtu = &emac_change_mtu;
2675 dev->commac.ops = &emac_commac_sg_ops;
2676 }
2677 SET_ETHTOOL_OPS(ndev, &emac_ethtool_ops);
2678
2679 netif_carrier_off(ndev);
2680 netif_stop_queue(ndev);
2681
2682 err = register_netdev(ndev);
2683 if (err) {
2684 printk(KERN_ERR "%s: failed to register net device (%d)!\n",
2685 np->full_name, err);
2686 goto err_detach_tah;
2687 }
2688
2689 /* Set our drvdata last as we don't want them visible until we are
2690 * fully initialized
2691 */
2692 wmb();
2693 dev_set_drvdata(&ofdev->dev, dev);
2694
2695 /* There's a new kid in town ! Let's tell everybody */
2696 wake_up_all(&emac_probe_wait);
2697
2698
2699 printk(KERN_INFO
2700 "%s: EMAC-%d %s, MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2701 ndev->name, dev->cell_index, np->full_name,
2702 ndev->dev_addr[0], ndev->dev_addr[1], ndev->dev_addr[2],
2703 ndev->dev_addr[3], ndev->dev_addr[4], ndev->dev_addr[5]);
2704
2705 if (dev->phy.address >= 0)
2706 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
2707 dev->phy.def->name, dev->phy.address);
2708
2709 emac_dbg_register(dev);
2710
2711 /* Life is good */
2712 return 0;
2713
2714 /* I have a bad feeling about this ... */
2715
2716 err_detach_tah:
2717 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2718 tah_detach(dev->tah_dev, dev->tah_port);
2719 err_detach_rgmii:
2720 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2721 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2722 err_detach_zmii:
2723 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2724 zmii_detach(dev->zmii_dev, dev->zmii_port);
2725 err_unreg_commac:
2726 mal_unregister_commac(dev->mal, &dev->commac);
2727 err_rel_deps:
2728 emac_put_deps(dev);
2729 err_reg_unmap:
2730 iounmap(dev->emacp);
2731 err_irq_unmap:
2732 if (dev->wol_irq != NO_IRQ)
2733 irq_dispose_mapping(dev->wol_irq);
2734 if (dev->emac_irq != NO_IRQ)
2735 irq_dispose_mapping(dev->emac_irq);
2736 err_free:
2737 kfree(ndev);
2738 err_gone:
2739 /* if we were on the bootlist, remove us as we won't show up and
2740 * wake up all waiters to notify them in case they were waiting
2741 * on us
2742 */
2743 if (blist) {
2744 *blist = NULL;
2745 wake_up_all(&emac_probe_wait);
2746 }
2747 return err;
2748}
2749
2750static int __devexit emac_remove(struct of_device *ofdev)
2751{
2752 struct emac_instance *dev = dev_get_drvdata(&ofdev->dev);
2753
2754 DBG(dev, "remove" NL);
2755
2756 dev_set_drvdata(&ofdev->dev, NULL);
2757
2758 unregister_netdev(dev->ndev);
2759
2760 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2761 tah_detach(dev->tah_dev, dev->tah_port);
2762 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2763 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2764 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2765 zmii_detach(dev->zmii_dev, dev->zmii_port);
2766
2767 mal_unregister_commac(dev->mal, &dev->commac);
2768 emac_put_deps(dev);
2769
2770 emac_dbg_unregister(dev);
2771 iounmap(dev->emacp);
2772
2773 if (dev->wol_irq != NO_IRQ)
2774 irq_dispose_mapping(dev->wol_irq);
2775 if (dev->emac_irq != NO_IRQ)
2776 irq_dispose_mapping(dev->emac_irq);
2777
2778 kfree(dev->ndev);
2779
2780 return 0;
2781}
2782
2783/* XXX Features in here should be replaced by properties... */
2784static struct of_device_id emac_match[] =
2785{
2786 {
2787 .type = "network",
2788 .compatible = "ibm,emac",
2789 },
2790 {
2791 .type = "network",
2792 .compatible = "ibm,emac4",
2793 },
2794 {},
2795};
2796
2797static struct of_platform_driver emac_driver = {
2798 .name = "emac",
2799 .match_table = emac_match,
2800
2801 .probe = emac_probe,
2802 .remove = emac_remove,
2803};
2804
2805static void __init emac_make_bootlist(void)
2806{
2807 struct device_node *np = NULL;
2808 int j, max, i = 0, k;
2809 int cell_indices[EMAC_BOOT_LIST_SIZE];
2810
2811 /* Collect EMACs */
2812 while((np = of_find_all_nodes(np)) != NULL) {
2813 const u32 *idx;
2814
2815 if (of_match_node(emac_match, np) == NULL)
2816 continue;
2817 if (of_get_property(np, "unused", NULL))
2818 continue;
2819 idx = of_get_property(np, "cell-index", NULL);
2820 if (idx == NULL)
2821 continue;
2822 cell_indices[i] = *idx;
2823 emac_boot_list[i++] = of_node_get(np);
2824 if (i >= EMAC_BOOT_LIST_SIZE) {
2825 of_node_put(np);
2826 break;
2827 }
2828 }
2829 max = i;
2830
2831 /* Bubble sort them (doh, what a creative algorithm :-) */
2832 for (i = 0; max > 1 && (i < (max - 1)); i++)
2833 for (j = i; j < max; j++) {
2834 if (cell_indices[i] > cell_indices[j]) {
2835 np = emac_boot_list[i];
2836 emac_boot_list[i] = emac_boot_list[j];
2837 emac_boot_list[j] = np;
2838 k = cell_indices[i];
2839 cell_indices[i] = cell_indices[j];
2840 cell_indices[j] = k;
2841 }
2842 }
2843}
2844
2845static int __init emac_init(void)
2846{
2847 int rc;
2848
2849 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
2850
2851 /* Init debug stuff */
2852 emac_init_debug();
2853
2854 /* Build EMAC boot list */
2855 emac_make_bootlist();
2856
2857 /* Init submodules */
2858 rc = mal_init();
2859 if (rc)
2860 goto err;
2861 rc = zmii_init();
2862 if (rc)
2863 goto err_mal;
2864 rc = rgmii_init();
2865 if (rc)
2866 goto err_zmii;
2867 rc = tah_init();
2868 if (rc)
2869 goto err_rgmii;
2870 rc = of_register_platform_driver(&emac_driver);
2871 if (rc)
2872 goto err_tah;
2873
2874 return 0;
2875
2876 err_tah:
2877 tah_exit();
2878 err_rgmii:
2879 rgmii_exit();
2880 err_zmii:
2881 zmii_exit();
2882 err_mal:
2883 mal_exit();
2884 err:
2885 return rc;
2886}
2887
2888static void __exit emac_exit(void)
2889{
2890 int i;
2891
2892 of_unregister_platform_driver(&emac_driver);
2893
2894 tah_exit();
2895 rgmii_exit();
2896 zmii_exit();
2897 mal_exit();
2898 emac_fini_debug();
2899
2900 /* Destroy EMAC boot list */
2901 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
2902 if (emac_boot_list[i])
2903 of_node_put(emac_boot_list[i]);
2904}
2905
2906module_init(emac_init);
2907module_exit(emac_exit);
diff --git a/drivers/net/ibm_newemac/core.h b/drivers/net/ibm_newemac/core.h
new file mode 100644
index 000000000000..4011803117ca
--- /dev/null
+++ b/drivers/net/ibm_newemac/core.h
@@ -0,0 +1,355 @@
1/*
2 * drivers/net/ibm_newemac/core.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Johnnie Peters <jpeters@mvista.com>
12 * Copyright 2000, 2001 MontaVista Softare Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 */
20#ifndef __IBM_NEWEMAC_CORE_H
21#define __IBM_NEWEMAC_CORE_H
22
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/kernel.h>
27#include <linux/interrupt.h>
28#include <linux/netdevice.h>
29#include <linux/dma-mapping.h>
30#include <linux/spinlock.h>
31
32#include <asm/of_platform.h>
33#include <asm/io.h>
34#include <asm/dcr.h>
35
36#include "emac.h"
37#include "phy.h"
38#include "zmii.h"
39#include "rgmii.h"
40#include "mal.h"
41#include "tah.h"
42#include "debug.h"
43
44#define NUM_TX_BUFF CONFIG_IBM_NEW_EMAC_TXB
45#define NUM_RX_BUFF CONFIG_IBM_NEW_EMAC_RXB
46
47/* Simple sanity check */
48#if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
49#error Invalid number of buffer descriptors (greater than 256)
50#endif
51
52#define EMAC_MIN_MTU 46
53
54/* Maximum L2 header length (VLAN tagged, no FCS) */
55#define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4)
56
57/* RX BD size for the given MTU */
58static inline int emac_rx_size(int mtu)
59{
60 if (mtu > ETH_DATA_LEN)
61 return MAL_MAX_RX_SIZE;
62 else
63 return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
64}
65
66#define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment())
67
68#define EMAC_RX_SKB_HEADROOM \
69 EMAC_DMA_ALIGN(CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM)
70
71/* Size of RX skb for the given MTU */
72static inline int emac_rx_skb_size(int mtu)
73{
74 int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
75 return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM;
76}
77
78/* RX DMA sync size */
79static inline int emac_rx_sync_size(int mtu)
80{
81 return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2);
82}
83
84/* Driver statistcs is split into two parts to make it more cache friendly:
85 * - normal statistics (packet count, etc)
86 * - error statistics
87 *
88 * When statistics is requested by ethtool, these parts are concatenated,
89 * normal one goes first.
90 *
91 * Please, keep these structures in sync with emac_stats_keys.
92 */
93
94/* Normal TX/RX Statistics */
95struct emac_stats {
96 u64 rx_packets;
97 u64 rx_bytes;
98 u64 tx_packets;
99 u64 tx_bytes;
100 u64 rx_packets_csum;
101 u64 tx_packets_csum;
102};
103
104/* Error statistics */
105struct emac_error_stats {
106 u64 tx_undo;
107
108 /* Software RX Errors */
109 u64 rx_dropped_stack;
110 u64 rx_dropped_oom;
111 u64 rx_dropped_error;
112 u64 rx_dropped_resize;
113 u64 rx_dropped_mtu;
114 u64 rx_stopped;
115 /* BD reported RX errors */
116 u64 rx_bd_errors;
117 u64 rx_bd_overrun;
118 u64 rx_bd_bad_packet;
119 u64 rx_bd_runt_packet;
120 u64 rx_bd_short_event;
121 u64 rx_bd_alignment_error;
122 u64 rx_bd_bad_fcs;
123 u64 rx_bd_packet_too_long;
124 u64 rx_bd_out_of_range;
125 u64 rx_bd_in_range;
126 /* EMAC IRQ reported RX errors */
127 u64 rx_parity;
128 u64 rx_fifo_overrun;
129 u64 rx_overrun;
130 u64 rx_bad_packet;
131 u64 rx_runt_packet;
132 u64 rx_short_event;
133 u64 rx_alignment_error;
134 u64 rx_bad_fcs;
135 u64 rx_packet_too_long;
136 u64 rx_out_of_range;
137 u64 rx_in_range;
138
139 /* Software TX Errors */
140 u64 tx_dropped;
141 /* BD reported TX errors */
142 u64 tx_bd_errors;
143 u64 tx_bd_bad_fcs;
144 u64 tx_bd_carrier_loss;
145 u64 tx_bd_excessive_deferral;
146 u64 tx_bd_excessive_collisions;
147 u64 tx_bd_late_collision;
148 u64 tx_bd_multple_collisions;
149 u64 tx_bd_single_collision;
150 u64 tx_bd_underrun;
151 u64 tx_bd_sqe;
152 /* EMAC IRQ reported TX errors */
153 u64 tx_parity;
154 u64 tx_underrun;
155 u64 tx_sqe;
156 u64 tx_errors;
157};
158
159#define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \
160 sizeof(struct emac_error_stats)) \
161 / sizeof(u64))
162
163struct emac_instance {
164 struct net_device *ndev;
165 struct resource rsrc_regs;
166 struct emac_regs __iomem *emacp;
167 struct of_device *ofdev;
168 struct device_node **blist; /* bootlist entry */
169
170 /* MAL linkage */
171 u32 mal_ph;
172 struct of_device *mal_dev;
173 u32 mal_rx_chan;
174 u32 mal_tx_chan;
175 struct mal_instance *mal;
176 struct mal_commac commac;
177
178 /* PHY infos */
179 u32 phy_mode;
180 u32 phy_map;
181 u32 phy_address;
182 u32 phy_feat_exc;
183 struct mii_phy phy;
184 struct mutex link_lock;
185 struct delayed_work link_work;
186 int link_polling;
187
188 /* Shared MDIO if any */
189 u32 mdio_ph;
190 struct of_device *mdio_dev;
191 struct emac_instance *mdio_instance;
192 struct mutex mdio_lock;
193
194 /* ZMII infos if any */
195 u32 zmii_ph;
196 u32 zmii_port;
197 struct of_device *zmii_dev;
198
199 /* RGMII infos if any */
200 u32 rgmii_ph;
201 u32 rgmii_port;
202 struct of_device *rgmii_dev;
203
204 /* TAH infos if any */
205 u32 tah_ph;
206 u32 tah_port;
207 struct of_device *tah_dev;
208
209 /* IRQs */
210 int wol_irq;
211 int emac_irq;
212
213 /* OPB bus frequency in Mhz */
214 u32 opb_bus_freq;
215
216 /* Cell index within an ASIC (for clk mgmnt) */
217 u32 cell_index;
218
219 /* Max supported MTU */
220 u32 max_mtu;
221
222 /* Feature bits (from probe table) */
223 unsigned int features;
224
225 /* Tx and Rx fifo sizes & other infos in bytes */
226 u32 tx_fifo_size;
227 u32 tx_fifo_size_gige;
228 u32 rx_fifo_size;
229 u32 rx_fifo_size_gige;
230 u32 fifo_entry_size;
231 u32 mal_burst_size; /* move to MAL ? */
232
233 /* Descriptor management
234 */
235 struct mal_descriptor *tx_desc;
236 int tx_cnt;
237 int tx_slot;
238 int ack_slot;
239
240 struct mal_descriptor *rx_desc;
241 int rx_slot;
242 struct sk_buff *rx_sg_skb; /* 1 */
243 int rx_skb_size;
244 int rx_sync_size;
245
246 struct sk_buff *tx_skb[NUM_TX_BUFF];
247 struct sk_buff *rx_skb[NUM_RX_BUFF];
248
249 /* Stats
250 */
251 struct emac_error_stats estats;
252 struct net_device_stats nstats;
253 struct emac_stats stats;
254
255 /* Misc
256 */
257 int reset_failed;
258 int stop_timeout; /* in us */
259 int no_mcast;
260 int mcast_pending;
261 struct work_struct reset_work;
262 spinlock_t lock;
263};
264
265/*
266 * Features of various EMAC implementations
267 */
268
269/*
270 * No flow control on 40x according to the original driver
271 */
272#define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001
273/*
274 * Cell is an EMAC4
275 */
276#define EMAC_FTR_EMAC4 0x00000002
277/*
278 * For the 440SPe, AMCC inexplicably changed the polarity of
279 * the "operation complete" bit in the MII control register.
280 */
281#define EMAC_FTR_STACR_OC_INVERT 0x00000004
282/*
283 * Set if we have a TAH.
284 */
285#define EMAC_FTR_HAS_TAH 0x00000008
286/*
287 * Set if we have a ZMII.
288 */
289#define EMAC_FTR_HAS_ZMII 0x00000010
290/*
291 * Set if we have a RGMII.
292 */
293#define EMAC_FTR_HAS_RGMII 0x00000020
294/*
295 * Set if we have axon-type STACR
296 */
297#define EMAC_FTR_HAS_AXON_STACR 0x00000040
298
299
300/* Right now, we don't quite handle the always/possible masks on the
301 * most optimal way as we don't have a way to say something like
302 * always EMAC4. Patches welcome.
303 */
304enum {
305 EMAC_FTRS_ALWAYS = 0,
306
307 EMAC_FTRS_POSSIBLE =
308#ifdef CONFIG_IBM_NEW_EMAC_EMAC4
309 EMAC_FTR_EMAC4 | EMAC_FTR_HAS_AXON_STACR |
310 EMAC_FTR_STACR_OC_INVERT |
311#endif
312#ifdef CONFIG_IBM_NEW_EMAC_TAH
313 EMAC_FTR_HAS_TAH |
314#endif
315#ifdef CONFIG_IBM_NEW_EMAC_ZMII
316 EMAC_FTR_HAS_ZMII |
317#endif
318#ifdef CONFIG_IBM_NEW_EMAC_RGMII
319 EMAC_FTR_HAS_RGMII |
320#endif
321 0,
322};
323
324static inline int emac_has_feature(struct emac_instance *dev,
325 unsigned long feature)
326{
327 return (EMAC_FTRS_ALWAYS & feature) ||
328 (EMAC_FTRS_POSSIBLE & dev->features & feature);
329}
330
331
332/* Ethtool get_regs complex data.
333 * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
334 * when available.
335 *
336 * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
337 * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
338 * Each register component is preceded with emac_ethtool_regs_subhdr.
339 * Order of the optional headers follows their relative bit posititions
340 * in emac_ethtool_regs_hdr.components
341 */
342#define EMAC_ETHTOOL_REGS_ZMII 0x00000001
343#define EMAC_ETHTOOL_REGS_RGMII 0x00000002
344#define EMAC_ETHTOOL_REGS_TAH 0x00000004
345
346struct emac_ethtool_regs_hdr {
347 u32 components;
348};
349
350struct emac_ethtool_regs_subhdr {
351 u32 version;
352 u32 index;
353};
354
355#endif /* __IBM_NEWEMAC_CORE_H */
diff --git a/drivers/net/ibm_newemac/debug.c b/drivers/net/ibm_newemac/debug.c
new file mode 100644
index 000000000000..170524ee0f19
--- /dev/null
+++ b/drivers/net/ibm_newemac/debug.c
@@ -0,0 +1,238 @@
1/*
2 * drivers/net/ibm_newemac/debug.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, debug print routines.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/netdevice.h>
19#include <linux/sysrq.h>
20#include <asm/io.h>
21
22#include "core.h"
23
24static spinlock_t emac_dbg_lock = SPIN_LOCK_UNLOCKED;
25
26static void emac_desc_dump(struct emac_instance *p)
27{
28 int i;
29 printk("** EMAC %s TX BDs **\n"
30 " tx_cnt = %d tx_slot = %d ack_slot = %d\n",
31 p->ofdev->node->full_name,
32 p->tx_cnt, p->tx_slot, p->ack_slot);
33 for (i = 0; i < NUM_TX_BUFF / 2; ++i)
34 printk
35 ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
36 i, p->tx_desc[i].data_ptr, p->tx_skb[i] ? 'V' : ' ',
37 p->tx_desc[i].ctrl, p->tx_desc[i].data_len,
38 NUM_TX_BUFF / 2 + i,
39 p->tx_desc[NUM_TX_BUFF / 2 + i].data_ptr,
40 p->tx_skb[NUM_TX_BUFF / 2 + i] ? 'V' : ' ',
41 p->tx_desc[NUM_TX_BUFF / 2 + i].ctrl,
42 p->tx_desc[NUM_TX_BUFF / 2 + i].data_len);
43
44 printk("** EMAC %s RX BDs **\n"
45 " rx_slot = %d flags = 0x%lx rx_skb_size = %d rx_sync_size = %d\n"
46 " rx_sg_skb = 0x%p\n",
47 p->ofdev->node->full_name,
48 p->rx_slot, p->commac.flags, p->rx_skb_size,
49 p->rx_sync_size, p->rx_sg_skb);
50 for (i = 0; i < NUM_RX_BUFF / 2; ++i)
51 printk
52 ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
53 i, p->rx_desc[i].data_ptr, p->rx_skb[i] ? 'V' : ' ',
54 p->rx_desc[i].ctrl, p->rx_desc[i].data_len,
55 NUM_RX_BUFF / 2 + i,
56 p->rx_desc[NUM_RX_BUFF / 2 + i].data_ptr,
57 p->rx_skb[NUM_RX_BUFF / 2 + i] ? 'V' : ' ',
58 p->rx_desc[NUM_RX_BUFF / 2 + i].ctrl,
59 p->rx_desc[NUM_RX_BUFF / 2 + i].data_len);
60}
61
62static void emac_mac_dump(struct emac_instance *dev)
63{
64 struct emac_regs __iomem *p = dev->emacp;
65
66 printk("** EMAC %s registers **\n"
67 "MR0 = 0x%08x MR1 = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x\n"
68 "RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x\n"
69 "IAR = %04x%08x VTPID = 0x%04x VTCI = 0x%04x\n"
70 "IAHT: 0x%04x 0x%04x 0x%04x 0x%04x "
71 "GAHT: 0x%04x 0x%04x 0x%04x 0x%04x\n"
72 "LSA = %04x%08x IPGVR = 0x%04x\n"
73 "STACR = 0x%08x TRTR = 0x%08x RWMR = 0x%08x\n"
74 "OCTX = 0x%08x OCRX = 0x%08x IPCR = 0x%08x\n",
75 dev->ofdev->node->full_name, in_be32(&p->mr0), in_be32(&p->mr1),
76 in_be32(&p->tmr0), in_be32(&p->tmr1),
77 in_be32(&p->rmr), in_be32(&p->isr), in_be32(&p->iser),
78 in_be32(&p->iahr), in_be32(&p->ialr), in_be32(&p->vtpid),
79 in_be32(&p->vtci),
80 in_be32(&p->iaht1), in_be32(&p->iaht2), in_be32(&p->iaht3),
81 in_be32(&p->iaht4),
82 in_be32(&p->gaht1), in_be32(&p->gaht2), in_be32(&p->gaht3),
83 in_be32(&p->gaht4),
84 in_be32(&p->lsah), in_be32(&p->lsal), in_be32(&p->ipgvr),
85 in_be32(&p->stacr), in_be32(&p->trtr), in_be32(&p->rwmr),
86 in_be32(&p->octx), in_be32(&p->ocrx), in_be32(&p->ipcr)
87 );
88
89 emac_desc_dump(dev);
90}
91
92static void emac_mal_dump(struct mal_instance *mal)
93{
94 int i;
95
96 printk("** MAL %s Registers **\n"
97 "CFG = 0x%08x ESR = 0x%08x IER = 0x%08x\n"
98 "TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n"
99 "RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n",
100 mal->ofdev->node->full_name,
101 get_mal_dcrn(mal, MAL_CFG), get_mal_dcrn(mal, MAL_ESR),
102 get_mal_dcrn(mal, MAL_IER),
103 get_mal_dcrn(mal, MAL_TXCASR), get_mal_dcrn(mal, MAL_TXCARR),
104 get_mal_dcrn(mal, MAL_TXEOBISR), get_mal_dcrn(mal, MAL_TXDEIR),
105 get_mal_dcrn(mal, MAL_RXCASR), get_mal_dcrn(mal, MAL_RXCARR),
106 get_mal_dcrn(mal, MAL_RXEOBISR), get_mal_dcrn(mal, MAL_RXDEIR)
107 );
108
109 printk("TX|");
110 for (i = 0; i < mal->num_tx_chans; ++i) {
111 if (i && !(i % 4))
112 printk("\n ");
113 printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_TXCTPR(i)));
114 }
115 printk("\nRX|");
116 for (i = 0; i < mal->num_rx_chans; ++i) {
117 if (i && !(i % 4))
118 printk("\n ");
119 printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_RXCTPR(i)));
120 }
121 printk("\n ");
122 for (i = 0; i < mal->num_rx_chans; ++i) {
123 u32 r = get_mal_dcrn(mal, MAL_RCBS(i));
124 if (i && !(i % 3))
125 printk("\n ");
126 printk("RCBS%d = 0x%08x (%d) ", i, r, r * 16);
127 }
128 printk("\n");
129}
130
131static struct emac_instance *__emacs[4];
132static struct mal_instance *__mals[1];
133
134void emac_dbg_register(struct emac_instance *dev)
135{
136 unsigned long flags;
137 int i;
138
139 spin_lock_irqsave(&emac_dbg_lock, flags);
140 for (i = 0; i < ARRAY_SIZE(__emacs); i++)
141 if (__emacs[i] == NULL) {
142 __emacs[i] = dev;
143 break;
144 }
145 spin_unlock_irqrestore(&emac_dbg_lock, flags);
146}
147
148void emac_dbg_unregister(struct emac_instance *dev)
149{
150 unsigned long flags;
151 int i;
152
153 spin_lock_irqsave(&emac_dbg_lock, flags);
154 for (i = 0; i < ARRAY_SIZE(__emacs); i++)
155 if (__emacs[i] == dev) {
156 __emacs[i] = NULL;
157 break;
158 }
159 spin_unlock_irqrestore(&emac_dbg_lock, flags);
160}
161
162void mal_dbg_register(struct mal_instance *mal)
163{
164 unsigned long flags;
165 int i;
166
167 spin_lock_irqsave(&emac_dbg_lock, flags);
168 for (i = 0; i < ARRAY_SIZE(__mals); i++)
169 if (__mals[i] == NULL) {
170 __mals[i] = mal;
171 break;
172 }
173 spin_unlock_irqrestore(&emac_dbg_lock, flags);
174}
175
176void mal_dbg_unregister(struct mal_instance *mal)
177{
178 unsigned long flags;
179 int i;
180
181 spin_lock_irqsave(&emac_dbg_lock, flags);
182 for (i = 0; i < ARRAY_SIZE(__mals); i++)
183 if (__mals[i] == mal) {
184 __mals[i] = NULL;
185 break;
186 }
187 spin_unlock_irqrestore(&emac_dbg_lock, flags);
188}
189
190void emac_dbg_dump_all(void)
191{
192 unsigned int i;
193 unsigned long flags;
194
195 spin_lock_irqsave(&emac_dbg_lock, flags);
196
197 for (i = 0; i < ARRAY_SIZE(__mals); ++i)
198 if (__mals[i])
199 emac_mal_dump(__mals[i]);
200
201 for (i = 0; i < ARRAY_SIZE(__emacs); ++i)
202 if (__emacs[i])
203 emac_mac_dump(__emacs[i]);
204
205 spin_unlock_irqrestore(&emac_dbg_lock, flags);
206}
207
208#if defined(CONFIG_MAGIC_SYSRQ)
209static void emac_sysrq_handler(int key, struct tty_struct *tty)
210{
211 emac_dbg_dump_all();
212}
213
214static struct sysrq_key_op emac_sysrq_op = {
215 .handler = emac_sysrq_handler,
216 .help_msg = "emaC",
217 .action_msg = "Show EMAC(s) status",
218};
219
220int __init emac_init_debug(void)
221{
222 return register_sysrq_key('c', &emac_sysrq_op);
223}
224
225void __exit emac_fini_debug(void)
226{
227 unregister_sysrq_key('c', &emac_sysrq_op);
228}
229
230#else
231int __init emac_init_debug(void)
232{
233 return 0;
234}
235void __exit emac_fini_debug(void)
236{
237}
238#endif /* CONFIG_MAGIC_SYSRQ */
diff --git a/drivers/net/ibm_newemac/debug.h b/drivers/net/ibm_newemac/debug.h
new file mode 100644
index 000000000000..1dd2dcbc157f
--- /dev/null
+++ b/drivers/net/ibm_newemac/debug.h
@@ -0,0 +1,78 @@
1/*
2 * drivers/net/ibm_newemac/debug.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, debug print routines.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15#ifndef __IBM_NEWEMAC_DEBUG_H
16#define __IBM_NEWEMAC_DEBUG_H
17
18#include <linux/init.h>
19
20#include "core.h"
21
22#if defined(CONFIG_IBM_NEW_EMAC_DEBUG)
23
24struct emac_instance;
25struct mal_instance;
26
27extern void emac_dbg_register(struct emac_instance *dev);
28extern void emac_dbg_unregister(struct emac_instance *dev);
29extern void mal_dbg_register(struct mal_instance *mal);
30extern void mal_dbg_unregister(struct mal_instance *mal);
31extern int emac_init_debug(void) __init;
32extern void emac_fini_debug(void) __exit;
33extern void emac_dbg_dump_all(void);
34
35# define DBG_LEVEL 1
36
37#else
38
39# define emac_dbg_register(x) do { } while(0)
40# define emac_dbg_unregister(x) do { } while(0)
41# define mal_dbg_register(x) do { } while(0)
42# define mal_dbg_unregister(x) do { } while(0)
43# define emac_init_debug() do { } while(0)
44# define emac_fini_debug() do { } while(0)
45# define emac_dbg_dump_all() do { } while(0)
46
47# define DBG_LEVEL 0
48
49#endif
50
51#define EMAC_DBG(dev, name, fmt, arg...) \
52 printk(KERN_DEBUG #name "%s: " fmt, dev->ofdev->node->full_name, ## arg)
53
54#if DBG_LEVEL > 0
55# define DBG(d,f,x...) EMAC_DBG(d, emac, f, ##x)
56# define MAL_DBG(d,f,x...) EMAC_DBG(d, mal, f, ##x)
57# define ZMII_DBG(d,f,x...) EMAC_DBG(d, zmii, f, ##x)
58# define RGMII_DBG(d,f,x...) EMAC_DBG(d, rgmii, f, ##x)
59# define NL "\n"
60#else
61# define DBG(f,x...) ((void)0)
62# define MAL_DBG(d,f,x...) ((void)0)
63# define ZMII_DBG(d,f,x...) ((void)0)
64# define RGMII_DBG(d,f,x...) ((void)0)
65#endif
66#if DBG_LEVEL > 1
67# define DBG2(d,f,x...) DBG(d,f, ##x)
68# define MAL_DBG2(d,f,x...) MAL_DBG(d,f, ##x)
69# define ZMII_DBG2(d,f,x...) ZMII_DBG(d,f, ##x)
70# define RGMII_DBG2(d,f,x...) RGMII_DBG(d,f, ##x)
71#else
72# define DBG2(f,x...) ((void)0)
73# define MAL_DBG2(d,f,x...) ((void)0)
74# define ZMII_DBG2(d,f,x...) ((void)0)
75# define RGMII_DBG2(d,f,x...) ((void)0)
76#endif
77
78#endif /* __IBM_NEWEMAC_DEBUG_H */
diff --git a/drivers/net/ibm_newemac/emac.h b/drivers/net/ibm_newemac/emac.h
new file mode 100644
index 000000000000..bef92efeeadc
--- /dev/null
+++ b/drivers/net/ibm_newemac/emac.h
@@ -0,0 +1,268 @@
1/*
2 * drivers/net/ibm_newemac/emac.h
3 *
4 * Register definitions for PowerPC 4xx on-chip ethernet contoller
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * Armin Kuster <akuster@mvista.com>
12 * Copyright 2002-2004 MontaVista Software Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 */
20#ifndef __IBM_NEWEMAC_H
21#define __IBM_NEWEMAC_H
22
23#include <linux/types.h>
24
25/* EMAC registers Write Access rules */
26struct emac_regs {
27 u32 mr0; /* special */
28 u32 mr1; /* Reset */
29 u32 tmr0; /* special */
30 u32 tmr1; /* special */
31 u32 rmr; /* Reset */
32 u32 isr; /* Always */
33 u32 iser; /* Reset */
34 u32 iahr; /* Reset, R, T */
35 u32 ialr; /* Reset, R, T */
36 u32 vtpid; /* Reset, R, T */
37 u32 vtci; /* Reset, R, T */
38 u32 ptr; /* Reset, T */
39 u32 iaht1; /* Reset, R */
40 u32 iaht2; /* Reset, R */
41 u32 iaht3; /* Reset, R */
42 u32 iaht4; /* Reset, R */
43 u32 gaht1; /* Reset, R */
44 u32 gaht2; /* Reset, R */
45 u32 gaht3; /* Reset, R */
46 u32 gaht4; /* Reset, R */
47 u32 lsah;
48 u32 lsal;
49 u32 ipgvr; /* Reset, T */
50 u32 stacr; /* special */
51 u32 trtr; /* special */
52 u32 rwmr; /* Reset */
53 u32 octx;
54 u32 ocrx;
55 u32 ipcr;
56};
57
58/*
59 * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
60 */
61#define PHY_MODE_NA 0
62#define PHY_MODE_MII 1
63#define PHY_MODE_RMII 2
64#define PHY_MODE_SMII 3
65#define PHY_MODE_RGMII 4
66#define PHY_MODE_TBI 5
67#define PHY_MODE_GMII 6
68#define PHY_MODE_RTBI 7
69#define PHY_MODE_SGMII 8
70
71
72#define EMAC_ETHTOOL_REGS_VER 0
73#define EMAC_ETHTOOL_REGS_SIZE (sizeof(struct emac_regs) - sizeof(u32))
74#define EMAC4_ETHTOOL_REGS_VER 1
75#define EMAC4_ETHTOOL_REGS_SIZE sizeof(struct emac_regs)
76
77/* EMACx_MR0 */
78#define EMAC_MR0_RXI 0x80000000
79#define EMAC_MR0_TXI 0x40000000
80#define EMAC_MR0_SRST 0x20000000
81#define EMAC_MR0_TXE 0x10000000
82#define EMAC_MR0_RXE 0x08000000
83#define EMAC_MR0_WKE 0x04000000
84
85/* EMACx_MR1 */
86#define EMAC_MR1_FDE 0x80000000
87#define EMAC_MR1_ILE 0x40000000
88#define EMAC_MR1_VLE 0x20000000
89#define EMAC_MR1_EIFC 0x10000000
90#define EMAC_MR1_APP 0x08000000
91#define EMAC_MR1_IST 0x01000000
92
93#define EMAC_MR1_MF_MASK 0x00c00000
94#define EMAC_MR1_MF_10 0x00000000
95#define EMAC_MR1_MF_100 0x00400000
96#define EMAC_MR1_MF_1000 0x00800000
97#define EMAC_MR1_MF_1000GPCS 0x00c00000
98#define EMAC_MR1_MF_IPPA(id) (((id) & 0x1f) << 6)
99
100#define EMAC_MR1_RFS_4K 0x00300000
101#define EMAC_MR1_RFS_16K 0x00000000
102#define EMAC_MR1_TFS_2K 0x00080000
103#define EMAC_MR1_TR0_MULT 0x00008000
104#define EMAC_MR1_JPSM 0x00000000
105#define EMAC_MR1_MWSW_001 0x00000000
106#define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
107
108
109#define EMAC4_MR1_RFS_2K 0x00100000
110#define EMAC4_MR1_RFS_4K 0x00180000
111#define EMAC4_MR1_RFS_16K 0x00280000
112#define EMAC4_MR1_TFS_2K 0x00020000
113#define EMAC4_MR1_TFS_4K 0x00030000
114#define EMAC4_MR1_TR 0x00008000
115#define EMAC4_MR1_MWSW_001 0x00001000
116#define EMAC4_MR1_JPSM 0x00000800
117#define EMAC4_MR1_OBCI_MASK 0x00000038
118#define EMAC4_MR1_OBCI_50 0x00000000
119#define EMAC4_MR1_OBCI_66 0x00000008
120#define EMAC4_MR1_OBCI_83 0x00000010
121#define EMAC4_MR1_OBCI_100 0x00000018
122#define EMAC4_MR1_OBCI_100P 0x00000020
123#define EMAC4_MR1_OBCI(freq) ((freq) <= 50 ? EMAC4_MR1_OBCI_50 : \
124 (freq) <= 66 ? EMAC4_MR1_OBCI_66 : \
125 (freq) <= 83 ? EMAC4_MR1_OBCI_83 : \
126 (freq) <= 100 ? EMAC4_MR1_OBCI_100 : \
127 EMAC4_MR1_OBCI_100P)
128
129/* EMACx_TMR0 */
130#define EMAC_TMR0_GNP 0x80000000
131#define EMAC_TMR0_DEFAULT 0x00000000
132#define EMAC4_TMR0_TFAE_2_32 0x00000001
133#define EMAC4_TMR0_TFAE_4_64 0x00000002
134#define EMAC4_TMR0_TFAE_8_128 0x00000003
135#define EMAC4_TMR0_TFAE_16_256 0x00000004
136#define EMAC4_TMR0_TFAE_32_512 0x00000005
137#define EMAC4_TMR0_TFAE_64_1024 0x00000006
138#define EMAC4_TMR0_TFAE_128_2048 0x00000007
139#define EMAC4_TMR0_DEFAULT EMAC4_TMR0_TFAE_2_32
140#define EMAC_TMR0_XMIT (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
141#define EMAC4_TMR0_XMIT (EMAC_TMR0_GNP | EMAC4_TMR0_DEFAULT)
142
143/* EMACx_TMR1 */
144
145#define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0xff) << 16))
146#define EMAC4_TMR1(l,h) (((l) << 27) | (((h) & 0x3ff) << 14))
147
148/* EMACx_RMR */
149#define EMAC_RMR_SP 0x80000000
150#define EMAC_RMR_SFCS 0x40000000
151#define EMAC_RMR_RRP 0x20000000
152#define EMAC_RMR_RFP 0x10000000
153#define EMAC_RMR_ROP 0x08000000
154#define EMAC_RMR_RPIR 0x04000000
155#define EMAC_RMR_PPP 0x02000000
156#define EMAC_RMR_PME 0x01000000
157#define EMAC_RMR_PMME 0x00800000
158#define EMAC_RMR_IAE 0x00400000
159#define EMAC_RMR_MIAE 0x00200000
160#define EMAC_RMR_BAE 0x00100000
161#define EMAC_RMR_MAE 0x00080000
162#define EMAC_RMR_BASE 0x00000000
163#define EMAC4_RMR_RFAF_2_32 0x00000001
164#define EMAC4_RMR_RFAF_4_64 0x00000002
165#define EMAC4_RMR_RFAF_8_128 0x00000003
166#define EMAC4_RMR_RFAF_16_256 0x00000004
167#define EMAC4_RMR_RFAF_32_512 0x00000005
168#define EMAC4_RMR_RFAF_64_1024 0x00000006
169#define EMAC4_RMR_RFAF_128_2048 0x00000007
170#define EMAC4_RMR_BASE EMAC4_RMR_RFAF_128_2048
171
172/* EMACx_ISR & EMACx_ISER */
173#define EMAC4_ISR_TXPE 0x20000000
174#define EMAC4_ISR_RXPE 0x10000000
175#define EMAC4_ISR_TXUE 0x08000000
176#define EMAC4_ISR_RXOE 0x04000000
177#define EMAC_ISR_OVR 0x02000000
178#define EMAC_ISR_PP 0x01000000
179#define EMAC_ISR_BP 0x00800000
180#define EMAC_ISR_RP 0x00400000
181#define EMAC_ISR_SE 0x00200000
182#define EMAC_ISR_ALE 0x00100000
183#define EMAC_ISR_BFCS 0x00080000
184#define EMAC_ISR_PTLE 0x00040000
185#define EMAC_ISR_ORE 0x00020000
186#define EMAC_ISR_IRE 0x00010000
187#define EMAC_ISR_SQE 0x00000080
188#define EMAC_ISR_TE 0x00000040
189#define EMAC_ISR_MOS 0x00000002
190#define EMAC_ISR_MOF 0x00000001
191
192/* EMACx_STACR */
193#define EMAC_STACR_PHYD_MASK 0xffff
194#define EMAC_STACR_PHYD_SHIFT 16
195#define EMAC_STACR_OC 0x00008000
196#define EMAC_STACR_PHYE 0x00004000
197#define EMAC_STACR_STAC_MASK 0x00003000
198#define EMAC_STACR_STAC_READ 0x00001000
199#define EMAC_STACR_STAC_WRITE 0x00002000
200#define EMAC_STACR_OPBC_MASK 0x00000C00
201#define EMAC_STACR_OPBC_50 0x00000000
202#define EMAC_STACR_OPBC_66 0x00000400
203#define EMAC_STACR_OPBC_83 0x00000800
204#define EMAC_STACR_OPBC_100 0x00000C00
205#define EMAC_STACR_OPBC(freq) ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
206 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
207 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
208#define EMAC_STACR_BASE(opb) EMAC_STACR_OPBC(opb)
209#define EMAC4_STACR_BASE(opb) 0x00000000
210#define EMAC_STACR_PCDA_MASK 0x1f
211#define EMAC_STACR_PCDA_SHIFT 5
212#define EMAC_STACR_PRA_MASK 0x1f
213#define EMACX_STACR_STAC_MASK 0x00003800
214#define EMACX_STACR_STAC_READ 0x00001000
215#define EMACX_STACR_STAC_WRITE 0x00000800
216#define EMACX_STACR_STAC_IND_ADDR 0x00002000
217#define EMACX_STACR_STAC_IND_READ 0x00003800
218#define EMACX_STACR_STAC_IND_READINC 0x00003000
219#define EMACX_STACR_STAC_IND_WRITE 0x00002800
220
221
222/* EMACx_TRTR */
223#define EMAC_TRTR_SHIFT_EMAC4 27
224#define EMAC_TRTR_SHIFT 24
225
226/* EMAC specific TX descriptor control fields (write access) */
227#define EMAC_TX_CTRL_GFCS 0x0200
228#define EMAC_TX_CTRL_GP 0x0100
229#define EMAC_TX_CTRL_ISA 0x0080
230#define EMAC_TX_CTRL_RSA 0x0040
231#define EMAC_TX_CTRL_IVT 0x0020
232#define EMAC_TX_CTRL_RVT 0x0010
233#define EMAC_TX_CTRL_TAH_CSUM 0x000e
234
235/* EMAC specific TX descriptor status fields (read access) */
236#define EMAC_TX_ST_BFCS 0x0200
237#define EMAC_TX_ST_LCS 0x0080
238#define EMAC_TX_ST_ED 0x0040
239#define EMAC_TX_ST_EC 0x0020
240#define EMAC_TX_ST_LC 0x0010
241#define EMAC_TX_ST_MC 0x0008
242#define EMAC_TX_ST_SC 0x0004
243#define EMAC_TX_ST_UR 0x0002
244#define EMAC_TX_ST_SQE 0x0001
245#define EMAC_IS_BAD_TX (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
246 EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
247 EMAC_TX_ST_MC | EMAC_TX_ST_UR)
248#define EMAC_IS_BAD_TX_TAH (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
249 EMAC_TX_ST_EC | EMAC_TX_ST_LC)
250
251/* EMAC specific RX descriptor status fields (read access) */
252#define EMAC_RX_ST_OE 0x0200
253#define EMAC_RX_ST_PP 0x0100
254#define EMAC_RX_ST_BP 0x0080
255#define EMAC_RX_ST_RP 0x0040
256#define EMAC_RX_ST_SE 0x0020
257#define EMAC_RX_ST_AE 0x0010
258#define EMAC_RX_ST_BFCS 0x0008
259#define EMAC_RX_ST_PTL 0x0004
260#define EMAC_RX_ST_ORE 0x0002
261#define EMAC_RX_ST_IRE 0x0001
262#define EMAC_RX_TAH_BAD_CSUM 0x0003
263#define EMAC_BAD_RX_MASK (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
264 EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
265 EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
266 EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
267 EMAC_RX_ST_IRE )
268#endif /* __IBM_NEWEMAC_H */
diff --git a/drivers/net/ibm_newemac/mal.c b/drivers/net/ibm_newemac/mal.c
new file mode 100644
index 000000000000..c4335b7d308c
--- /dev/null
+++ b/drivers/net/ibm_newemac/mal.c
@@ -0,0 +1,728 @@
1/*
2 * drivers/net/ibm_newemac/mal.c
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
11 * David Gibson <hermes@gibson.dropbear.id.au>,
12 *
13 * Armin Kuster <akuster@mvista.com>
14 * Copyright 2002 MontaVista Softare Inc.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 */
22
23#include <linux/delay.h>
24
25#include "core.h"
26
27static int mal_count;
28
29int __devinit mal_register_commac(struct mal_instance *mal,
30 struct mal_commac *commac)
31{
32 unsigned long flags;
33
34 spin_lock_irqsave(&mal->lock, flags);
35
36 MAL_DBG(mal, "reg(%08x, %08x)" NL,
37 commac->tx_chan_mask, commac->rx_chan_mask);
38
39 /* Don't let multiple commacs claim the same channel(s) */
40 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
41 (mal->rx_chan_mask & commac->rx_chan_mask)) {
42 spin_unlock_irqrestore(&mal->lock, flags);
43 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
44 mal->index);
45 return -EBUSY;
46 }
47
48 mal->tx_chan_mask |= commac->tx_chan_mask;
49 mal->rx_chan_mask |= commac->rx_chan_mask;
50 list_add(&commac->list, &mal->list);
51
52 spin_unlock_irqrestore(&mal->lock, flags);
53
54 return 0;
55}
56
57void __devexit mal_unregister_commac(struct mal_instance *mal,
58 struct mal_commac *commac)
59{
60 unsigned long flags;
61
62 spin_lock_irqsave(&mal->lock, flags);
63
64 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
65 commac->tx_chan_mask, commac->rx_chan_mask);
66
67 mal->tx_chan_mask &= ~commac->tx_chan_mask;
68 mal->rx_chan_mask &= ~commac->rx_chan_mask;
69 list_del_init(&commac->list);
70
71 spin_unlock_irqrestore(&mal->lock, flags);
72}
73
74int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
75{
76 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
77 size > MAL_MAX_RX_SIZE);
78
79 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
80
81 if (size & 0xf) {
82 printk(KERN_WARNING
83 "mal%d: incorrect RX size %lu for the channel %d\n",
84 mal->index, size, channel);
85 return -EINVAL;
86 }
87
88 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
89 return 0;
90}
91
92int mal_tx_bd_offset(struct mal_instance *mal, int channel)
93{
94 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
95
96 return channel * NUM_TX_BUFF;
97}
98
99int mal_rx_bd_offset(struct mal_instance *mal, int channel)
100{
101 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
102 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
103}
104
105void mal_enable_tx_channel(struct mal_instance *mal, int channel)
106{
107 unsigned long flags;
108
109 spin_lock_irqsave(&mal->lock, flags);
110
111 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
112
113 set_mal_dcrn(mal, MAL_TXCASR,
114 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
115
116 spin_unlock_irqrestore(&mal->lock, flags);
117}
118
119void mal_disable_tx_channel(struct mal_instance *mal, int channel)
120{
121 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
122
123 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
124}
125
126void mal_enable_rx_channel(struct mal_instance *mal, int channel)
127{
128 unsigned long flags;
129
130 spin_lock_irqsave(&mal->lock, flags);
131
132 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
133
134 set_mal_dcrn(mal, MAL_RXCASR,
135 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
136
137 spin_unlock_irqrestore(&mal->lock, flags);
138}
139
140void mal_disable_rx_channel(struct mal_instance *mal, int channel)
141{
142 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
143
144 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
145}
146
147void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
148{
149 unsigned long flags;
150
151 spin_lock_irqsave(&mal->lock, flags);
152
153 MAL_DBG(mal, "poll_add(%p)" NL, commac);
154
155 /* starts disabled */
156 set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
157
158 list_add_tail(&commac->poll_list, &mal->poll_list);
159
160 spin_unlock_irqrestore(&mal->lock, flags);
161}
162
163void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&mal->lock, flags);
168
169 MAL_DBG(mal, "poll_del(%p)" NL, commac);
170
171 list_del(&commac->poll_list);
172
173 spin_unlock_irqrestore(&mal->lock, flags);
174}
175
176/* synchronized by mal_poll() */
177static inline void mal_enable_eob_irq(struct mal_instance *mal)
178{
179 MAL_DBG2(mal, "enable_irq" NL);
180
181 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
182 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
183}
184
185/* synchronized by __LINK_STATE_RX_SCHED bit in ndev->state */
186static inline void mal_disable_eob_irq(struct mal_instance *mal)
187{
188 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
189 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
190
191 MAL_DBG2(mal, "disable_irq" NL);
192}
193
194static irqreturn_t mal_serr(int irq, void *dev_instance)
195{
196 struct mal_instance *mal = dev_instance;
197
198 u32 esr = get_mal_dcrn(mal, MAL_ESR);
199
200 /* Clear the error status register */
201 set_mal_dcrn(mal, MAL_ESR, esr);
202
203 MAL_DBG(mal, "SERR %08x" NL, esr);
204
205 if (esr & MAL_ESR_EVB) {
206 if (esr & MAL_ESR_DE) {
207 /* We ignore Descriptor error,
208 * TXDE or RXDE interrupt will be generated anyway.
209 */
210 return IRQ_HANDLED;
211 }
212
213 if (esr & MAL_ESR_PEIN) {
214 /* PLB error, it's probably buggy hardware or
215 * incorrect physical address in BD (i.e. bug)
216 */
217 if (net_ratelimit())
218 printk(KERN_ERR
219 "mal%d: system error, "
220 "PLB (ESR = 0x%08x)\n",
221 mal->index, esr);
222 return IRQ_HANDLED;
223 }
224
225 /* OPB error, it's probably buggy hardware or incorrect
226 * EBC setup
227 */
228 if (net_ratelimit())
229 printk(KERN_ERR
230 "mal%d: system error, OPB (ESR = 0x%08x)\n",
231 mal->index, esr);
232 }
233 return IRQ_HANDLED;
234}
235
236static inline void mal_schedule_poll(struct mal_instance *mal)
237{
238 if (likely(netif_rx_schedule_prep(&mal->poll_dev))) {
239 MAL_DBG2(mal, "schedule_poll" NL);
240 mal_disable_eob_irq(mal);
241 __netif_rx_schedule(&mal->poll_dev);
242 } else
243 MAL_DBG2(mal, "already in poll" NL);
244}
245
246static irqreturn_t mal_txeob(int irq, void *dev_instance)
247{
248 struct mal_instance *mal = dev_instance;
249
250 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
251
252 MAL_DBG2(mal, "txeob %08x" NL, r);
253
254 mal_schedule_poll(mal);
255 set_mal_dcrn(mal, MAL_TXEOBISR, r);
256
257 return IRQ_HANDLED;
258}
259
260static irqreturn_t mal_rxeob(int irq, void *dev_instance)
261{
262 struct mal_instance *mal = dev_instance;
263
264 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
265
266 MAL_DBG2(mal, "rxeob %08x" NL, r);
267
268 mal_schedule_poll(mal);
269 set_mal_dcrn(mal, MAL_RXEOBISR, r);
270
271 return IRQ_HANDLED;
272}
273
274static irqreturn_t mal_txde(int irq, void *dev_instance)
275{
276 struct mal_instance *mal = dev_instance;
277
278 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
279 set_mal_dcrn(mal, MAL_TXDEIR, deir);
280
281 MAL_DBG(mal, "txde %08x" NL, deir);
282
283 if (net_ratelimit())
284 printk(KERN_ERR
285 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
286 mal->index, deir);
287
288 return IRQ_HANDLED;
289}
290
291static irqreturn_t mal_rxde(int irq, void *dev_instance)
292{
293 struct mal_instance *mal = dev_instance;
294 struct list_head *l;
295
296 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
297
298 MAL_DBG(mal, "rxde %08x" NL, deir);
299
300 list_for_each(l, &mal->list) {
301 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
302 if (deir & mc->rx_chan_mask) {
303 set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags);
304 mc->ops->rxde(mc->dev);
305 }
306 }
307
308 mal_schedule_poll(mal);
309 set_mal_dcrn(mal, MAL_RXDEIR, deir);
310
311 return IRQ_HANDLED;
312}
313
314void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
315{
316 /* Spinlock-type semantics: only one caller disable poll at a time */
317 while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags))
318 msleep(1);
319
320 /* Synchronize with the MAL NAPI poller. */
321 while (test_bit(__LINK_STATE_RX_SCHED, &mal->poll_dev.state))
322 msleep(1);
323}
324
325void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
326{
327 smp_wmb();
328 clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
329
330 // XXX might want to kick a poll now...
331}
332
333static int mal_poll(struct net_device *ndev, int *budget)
334{
335 struct mal_instance *mal = netdev_priv(ndev);
336 struct list_head *l;
337 int rx_work_limit = min(ndev->quota, *budget), received = 0, done;
338 unsigned long flags;
339
340 MAL_DBG2(mal, "poll(%d) %d ->" NL, *budget,
341 rx_work_limit);
342 again:
343 /* Process TX skbs */
344 list_for_each(l, &mal->poll_list) {
345 struct mal_commac *mc =
346 list_entry(l, struct mal_commac, poll_list);
347 mc->ops->poll_tx(mc->dev);
348 }
349
350 /* Process RX skbs.
351 *
352 * We _might_ need something more smart here to enforce polling
353 * fairness.
354 */
355 list_for_each(l, &mal->poll_list) {
356 struct mal_commac *mc =
357 list_entry(l, struct mal_commac, poll_list);
358 int n;
359 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
360 continue;
361 n = mc->ops->poll_rx(mc->dev, rx_work_limit);
362 if (n) {
363 received += n;
364 rx_work_limit -= n;
365 if (rx_work_limit <= 0) {
366 done = 0;
367 // XXX What if this is the last one ?
368 goto more_work;
369 }
370 }
371 }
372
373 /* We need to disable IRQs to protect from RXDE IRQ here */
374 spin_lock_irqsave(&mal->lock, flags);
375 __netif_rx_complete(ndev);
376 mal_enable_eob_irq(mal);
377 spin_unlock_irqrestore(&mal->lock, flags);
378
379 done = 1;
380
381 /* Check for "rotting" packet(s) */
382 list_for_each(l, &mal->poll_list) {
383 struct mal_commac *mc =
384 list_entry(l, struct mal_commac, poll_list);
385 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
386 continue;
387 if (unlikely(mc->ops->peek_rx(mc->dev) ||
388 test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) {
389 MAL_DBG2(mal, "rotting packet" NL);
390 if (netif_rx_reschedule(ndev, received))
391 mal_disable_eob_irq(mal);
392 else
393 MAL_DBG2(mal, "already in poll list" NL);
394
395 if (rx_work_limit > 0)
396 goto again;
397 else
398 goto more_work;
399 }
400 mc->ops->poll_tx(mc->dev);
401 }
402
403 more_work:
404 ndev->quota -= received;
405 *budget -= received;
406
407 MAL_DBG2(mal, "poll() %d <- %d" NL, *budget,
408 done ? 0 : 1);
409
410 return done ? 0 : 1;
411}
412
413static void mal_reset(struct mal_instance *mal)
414{
415 int n = 10;
416
417 MAL_DBG(mal, "reset" NL);
418
419 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
420
421 /* Wait for reset to complete (1 system clock) */
422 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
423 --n;
424
425 if (unlikely(!n))
426 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
427}
428
429int mal_get_regs_len(struct mal_instance *mal)
430{
431 return sizeof(struct emac_ethtool_regs_subhdr) +
432 sizeof(struct mal_regs);
433}
434
435void *mal_dump_regs(struct mal_instance *mal, void *buf)
436{
437 struct emac_ethtool_regs_subhdr *hdr = buf;
438 struct mal_regs *regs = (struct mal_regs *)(hdr + 1);
439 int i;
440
441 hdr->version = mal->version;
442 hdr->index = mal->index;
443
444 regs->tx_count = mal->num_tx_chans;
445 regs->rx_count = mal->num_rx_chans;
446
447 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
448 regs->esr = get_mal_dcrn(mal, MAL_ESR);
449 regs->ier = get_mal_dcrn(mal, MAL_IER);
450 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
451 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
452 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
453 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
454 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
455 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
456 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
457 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
458
459 for (i = 0; i < regs->tx_count; ++i)
460 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
461
462 for (i = 0; i < regs->rx_count; ++i) {
463 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
464 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
465 }
466 return regs + 1;
467}
468
469static int __devinit mal_probe(struct of_device *ofdev,
470 const struct of_device_id *match)
471{
472 struct mal_instance *mal;
473 int err = 0, i, bd_size;
474 int index = mal_count++;
475 const u32 *prop;
476 u32 cfg;
477
478 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
479 if (!mal) {
480 printk(KERN_ERR
481 "mal%d: out of memory allocating MAL structure!\n",
482 index);
483 return -ENOMEM;
484 }
485 mal->index = index;
486 mal->ofdev = ofdev;
487 mal->version = of_device_is_compatible(ofdev->node, "ibm,mcmal2") ? 2 : 1;
488
489 MAL_DBG(mal, "probe" NL);
490
491 prop = of_get_property(ofdev->node, "num-tx-chans", NULL);
492 if (prop == NULL) {
493 printk(KERN_ERR
494 "mal%d: can't find MAL num-tx-chans property!\n",
495 index);
496 err = -ENODEV;
497 goto fail;
498 }
499 mal->num_tx_chans = prop[0];
500
501 prop = of_get_property(ofdev->node, "num-rx-chans", NULL);
502 if (prop == NULL) {
503 printk(KERN_ERR
504 "mal%d: can't find MAL num-rx-chans property!\n",
505 index);
506 err = -ENODEV;
507 goto fail;
508 }
509 mal->num_rx_chans = prop[0];
510
511 mal->dcr_base = dcr_resource_start(ofdev->node, 0);
512 if (mal->dcr_base == 0) {
513 printk(KERN_ERR
514 "mal%d: can't find DCR resource!\n", index);
515 err = -ENODEV;
516 goto fail;
517 }
518 mal->dcr_host = dcr_map(ofdev->node, mal->dcr_base, 0x100);
519 if (!DCR_MAP_OK(mal->dcr_host)) {
520 printk(KERN_ERR
521 "mal%d: failed to map DCRs !\n", index);
522 err = -ENODEV;
523 goto fail;
524 }
525
526 mal->txeob_irq = irq_of_parse_and_map(ofdev->node, 0);
527 mal->rxeob_irq = irq_of_parse_and_map(ofdev->node, 1);
528 mal->serr_irq = irq_of_parse_and_map(ofdev->node, 2);
529 mal->txde_irq = irq_of_parse_and_map(ofdev->node, 3);
530 mal->rxde_irq = irq_of_parse_and_map(ofdev->node, 4);
531 if (mal->txeob_irq == NO_IRQ || mal->rxeob_irq == NO_IRQ ||
532 mal->serr_irq == NO_IRQ || mal->txde_irq == NO_IRQ ||
533 mal->rxde_irq == NO_IRQ) {
534 printk(KERN_ERR
535 "mal%d: failed to map interrupts !\n", index);
536 err = -ENODEV;
537 goto fail_unmap;
538 }
539
540 INIT_LIST_HEAD(&mal->poll_list);
541 set_bit(__LINK_STATE_START, &mal->poll_dev.state);
542 mal->poll_dev.weight = CONFIG_IBM_NEW_EMAC_POLL_WEIGHT;
543 mal->poll_dev.poll = mal_poll;
544 mal->poll_dev.priv = mal;
545 atomic_set(&mal->poll_dev.refcnt, 1);
546 INIT_LIST_HEAD(&mal->list);
547 spin_lock_init(&mal->lock);
548
549 /* Load power-on reset defaults */
550 mal_reset(mal);
551
552 /* Set the MAL configuration register */
553 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
554 cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA;
555
556 /* Current Axon is not happy with priority being non-0, it can
557 * deadlock, fix it up here
558 */
559 if (of_device_is_compatible(ofdev->node, "ibm,mcmal-axon"))
560 cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10);
561
562 /* Apply configuration */
563 set_mal_dcrn(mal, MAL_CFG, cfg);
564
565 /* Allocate space for BD rings */
566 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
567 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
568
569 bd_size = sizeof(struct mal_descriptor) *
570 (NUM_TX_BUFF * mal->num_tx_chans +
571 NUM_RX_BUFF * mal->num_rx_chans);
572 mal->bd_virt =
573 dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
574 GFP_KERNEL);
575 if (mal->bd_virt == NULL) {
576 printk(KERN_ERR
577 "mal%d: out of memory allocating RX/TX descriptors!\n",
578 index);
579 err = -ENOMEM;
580 goto fail_unmap;
581 }
582 memset(mal->bd_virt, 0, bd_size);
583
584 for (i = 0; i < mal->num_tx_chans; ++i)
585 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
586 sizeof(struct mal_descriptor) *
587 mal_tx_bd_offset(mal, i));
588
589 for (i = 0; i < mal->num_rx_chans; ++i)
590 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
591 sizeof(struct mal_descriptor) *
592 mal_rx_bd_offset(mal, i));
593
594 err = request_irq(mal->serr_irq, mal_serr, 0, "MAL SERR", mal);
595 if (err)
596 goto fail2;
597 err = request_irq(mal->txde_irq, mal_txde, 0, "MAL TX DE", mal);
598 if (err)
599 goto fail3;
600 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
601 if (err)
602 goto fail4;
603 err = request_irq(mal->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
604 if (err)
605 goto fail5;
606 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
607 if (err)
608 goto fail6;
609
610 /* Enable all MAL SERR interrupt sources */
611 if (mal->version == 2)
612 set_mal_dcrn(mal, MAL_IER, MAL2_IER_EVENTS);
613 else
614 set_mal_dcrn(mal, MAL_IER, MAL1_IER_EVENTS);
615
616 /* Enable EOB interrupt */
617 mal_enable_eob_irq(mal);
618
619 printk(KERN_INFO
620 "MAL v%d %s, %d TX channels, %d RX channels\n",
621 mal->version, ofdev->node->full_name,
622 mal->num_tx_chans, mal->num_rx_chans);
623
624 /* Advertise this instance to the rest of the world */
625 wmb();
626 dev_set_drvdata(&ofdev->dev, mal);
627
628 mal_dbg_register(mal);
629
630 return 0;
631
632 fail6:
633 free_irq(mal->rxde_irq, mal);
634 fail5:
635 free_irq(mal->txeob_irq, mal);
636 fail4:
637 free_irq(mal->txde_irq, mal);
638 fail3:
639 free_irq(mal->serr_irq, mal);
640 fail2:
641 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
642 fail_unmap:
643 dcr_unmap(mal->dcr_host, mal->dcr_base, 0x100);
644 fail:
645 kfree(mal);
646
647 return err;
648}
649
650static int __devexit mal_remove(struct of_device *ofdev)
651{
652 struct mal_instance *mal = dev_get_drvdata(&ofdev->dev);
653
654 MAL_DBG(mal, "remove" NL);
655
656 /* Syncronize with scheduled polling,
657 stolen from net/core/dev.c:dev_close()
658 */
659 clear_bit(__LINK_STATE_START, &mal->poll_dev.state);
660 netif_poll_disable(&mal->poll_dev);
661
662 if (!list_empty(&mal->list)) {
663 /* This is *very* bad */
664 printk(KERN_EMERG
665 "mal%d: commac list is not empty on remove!\n",
666 mal->index);
667 WARN_ON(1);
668 }
669
670 dev_set_drvdata(&ofdev->dev, NULL);
671
672 free_irq(mal->serr_irq, mal);
673 free_irq(mal->txde_irq, mal);
674 free_irq(mal->txeob_irq, mal);
675 free_irq(mal->rxde_irq, mal);
676 free_irq(mal->rxeob_irq, mal);
677
678 mal_reset(mal);
679
680 mal_dbg_unregister(mal);
681
682 dma_free_coherent(&ofdev->dev,
683 sizeof(struct mal_descriptor) *
684 (NUM_TX_BUFF * mal->num_tx_chans +
685 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
686 mal->bd_dma);
687 kfree(mal);
688
689 return 0;
690}
691
692static struct of_device_id mal_platform_match[] =
693{
694 {
695 .compatible = "ibm,mcmal",
696 },
697 {
698 .compatible = "ibm,mcmal2",
699 },
700 /* Backward compat */
701 {
702 .type = "mcmal-dma",
703 .compatible = "ibm,mcmal",
704 },
705 {
706 .type = "mcmal-dma",
707 .compatible = "ibm,mcmal2",
708 },
709 {},
710};
711
712static struct of_platform_driver mal_of_driver = {
713 .name = "mcmal",
714 .match_table = mal_platform_match,
715
716 .probe = mal_probe,
717 .remove = mal_remove,
718};
719
720int __init mal_init(void)
721{
722 return of_register_platform_driver(&mal_of_driver);
723}
724
725void mal_exit(void)
726{
727 of_unregister_platform_driver(&mal_of_driver);
728}
diff --git a/drivers/net/ibm_newemac/mal.h b/drivers/net/ibm_newemac/mal.h
new file mode 100644
index 000000000000..57b69dc32e9d
--- /dev/null
+++ b/drivers/net/ibm_newemac/mal.h
@@ -0,0 +1,276 @@
1/*
2 * drivers/net/ibm_newemac/mal.h
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2002 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#ifndef __IBM_NEWEMAC_MAL_H
20#define __IBM_NEWEMAC_MAL_H
21
22/*
23 * There are some variations on the MAL, we express them in this driver as
24 * MAL Version 1 and 2 though that doesn't match any IBM terminology.
25 *
26 * We call MAL 1 the version in 405GP, 405GPR, 405EP, 440EP, 440GR and
27 * NP405H.
28 *
29 * We call MAL 2 the version in 440GP, 440GX, 440SP, 440SPE and Axon
30 *
31 * The driver expects a "version" property in the emac node containing
32 * a number 1 or 2. New device-trees for EMAC capable platforms are thus
33 * required to include that when porting to arch/powerpc.
34 */
35
36/* MALx DCR registers */
37#define MAL_CFG 0x00
38#define MAL_CFG_SR 0x80000000
39#define MAL_CFG_PLBB 0x00004000
40#define MAL_CFG_OPBBL 0x00000080
41#define MAL_CFG_EOPIE 0x00000004
42#define MAL_CFG_LEA 0x00000002
43#define MAL_CFG_SD 0x00000001
44
45/* MAL V1 CFG bits */
46#define MAL1_CFG_PLBP_MASK 0x00c00000
47#define MAL1_CFG_PLBP_10 0x00800000
48#define MAL1_CFG_GA 0x00200000
49#define MAL1_CFG_OA 0x00100000
50#define MAL1_CFG_PLBLE 0x00080000
51#define MAL1_CFG_PLBT_MASK 0x00078000
52#define MAL1_CFG_DEFAULT (MAL1_CFG_PLBP_10 | MAL1_CFG_PLBT_MASK)
53
54/* MAL V2 CFG bits */
55#define MAL2_CFG_RPP_MASK 0x00c00000
56#define MAL2_CFG_RPP_10 0x00800000
57#define MAL2_CFG_RMBS_MASK 0x00300000
58#define MAL2_CFG_WPP_MASK 0x000c0000
59#define MAL2_CFG_WPP_10 0x00080000
60#define MAL2_CFG_WMBS_MASK 0x00030000
61#define MAL2_CFG_PLBLE 0x00008000
62#define MAL2_CFG_DEFAULT (MAL2_CFG_RMBS_MASK | MAL2_CFG_WMBS_MASK | \
63 MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10)
64
65#define MAL_ESR 0x01
66#define MAL_ESR_EVB 0x80000000
67#define MAL_ESR_CIDT 0x40000000
68#define MAL_ESR_CID_MASK 0x3e000000
69#define MAL_ESR_CID_SHIFT 25
70#define MAL_ESR_DE 0x00100000
71#define MAL_ESR_OTE 0x00040000
72#define MAL_ESR_OSE 0x00020000
73#define MAL_ESR_PEIN 0x00010000
74#define MAL_ESR_DEI 0x00000010
75#define MAL_ESR_OTEI 0x00000004
76#define MAL_ESR_OSEI 0x00000002
77#define MAL_ESR_PBEI 0x00000001
78
79/* MAL V1 ESR bits */
80#define MAL1_ESR_ONE 0x00080000
81#define MAL1_ESR_ONEI 0x00000008
82
83/* MAL V2 ESR bits */
84#define MAL2_ESR_PTE 0x00800000
85#define MAL2_ESR_PRE 0x00400000
86#define MAL2_ESR_PWE 0x00200000
87#define MAL2_ESR_PTEI 0x00000080
88#define MAL2_ESR_PREI 0x00000040
89#define MAL2_ESR_PWEI 0x00000020
90
91
92#define MAL_IER 0x02
93#define MAL_IER_DE 0x00000010
94#define MAL_IER_OTE 0x00000004
95#define MAL_IER_OE 0x00000002
96#define MAL_IER_PE 0x00000001
97/* MAL V1 IER bits */
98#define MAL1_IER_NWE 0x00000008
99#define MAL1_IER_SOC_EVENTS MAL1_IER_NWE
100#define MAL1_IER_EVENTS (MAL1_IER_SOC_EVENTS | MAL_IER_OTE | \
101 MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
102
103/* MAL V2 IER bits */
104#define MAL2_IER_PT 0x00000080
105#define MAL2_IER_PRE 0x00000040
106#define MAL2_IER_PWE 0x00000020
107#define MAL2_IER_SOC_EVENTS (MAL2_IER_PT | MAL2_IER_PRE | MAL2_IER_PWE)
108#define MAL2_IER_EVENTS (MAL2_IER_SOC_EVENTS | MAL_IER_OTE | \
109 MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
110
111
112#define MAL_TXCASR 0x04
113#define MAL_TXCARR 0x05
114#define MAL_TXEOBISR 0x06
115#define MAL_TXDEIR 0x07
116#define MAL_RXCASR 0x10
117#define MAL_RXCARR 0x11
118#define MAL_RXEOBISR 0x12
119#define MAL_RXDEIR 0x13
120#define MAL_TXCTPR(n) ((n) + 0x20)
121#define MAL_RXCTPR(n) ((n) + 0x40)
122#define MAL_RCBS(n) ((n) + 0x60)
123
124/* In reality MAL can handle TX buffers up to 4095 bytes long,
125 * but this isn't a good round number :) --ebs
126 */
127#define MAL_MAX_TX_SIZE 4080
128#define MAL_MAX_RX_SIZE 4080
129
130static inline int mal_rx_size(int len)
131{
132 len = (len + 0xf) & ~0xf;
133 return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len;
134}
135
136static inline int mal_tx_chunks(int len)
137{
138 return (len + MAL_MAX_TX_SIZE - 1) / MAL_MAX_TX_SIZE;
139}
140
141#define MAL_CHAN_MASK(n) (0x80000000 >> (n))
142
143/* MAL Buffer Descriptor structure */
144struct mal_descriptor {
145 u16 ctrl; /* MAL / Commac status control bits */
146 u16 data_len; /* Max length is 4K-1 (12 bits) */
147 u32 data_ptr; /* pointer to actual data buffer */
148};
149
150/* the following defines are for the MadMAL status and control registers. */
151/* MADMAL transmit and receive status/control bits */
152#define MAL_RX_CTRL_EMPTY 0x8000
153#define MAL_RX_CTRL_WRAP 0x4000
154#define MAL_RX_CTRL_CM 0x2000
155#define MAL_RX_CTRL_LAST 0x1000
156#define MAL_RX_CTRL_FIRST 0x0800
157#define MAL_RX_CTRL_INTR 0x0400
158#define MAL_RX_CTRL_SINGLE (MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
159#define MAL_IS_SINGLE_RX(ctrl) (((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)
160
161#define MAL_TX_CTRL_READY 0x8000
162#define MAL_TX_CTRL_WRAP 0x4000
163#define MAL_TX_CTRL_CM 0x2000
164#define MAL_TX_CTRL_LAST 0x1000
165#define MAL_TX_CTRL_INTR 0x0400
166
167struct mal_commac_ops {
168 void (*poll_tx) (void *dev);
169 int (*poll_rx) (void *dev, int budget);
170 int (*peek_rx) (void *dev);
171 void (*rxde) (void *dev);
172};
173
174struct mal_commac {
175 struct mal_commac_ops *ops;
176 void *dev;
177 struct list_head poll_list;
178 long flags;
179#define MAL_COMMAC_RX_STOPPED 0
180#define MAL_COMMAC_POLL_DISABLED 1
181 u32 tx_chan_mask;
182 u32 rx_chan_mask;
183 struct list_head list;
184};
185
186struct mal_instance {
187 int version;
188 int dcr_base;
189 dcr_host_t dcr_host;
190
191 int num_tx_chans; /* Number of TX channels */
192 int num_rx_chans; /* Number of RX channels */
193 int txeob_irq; /* TX End Of Buffer IRQ */
194 int rxeob_irq; /* RX End Of Buffer IRQ */
195 int txde_irq; /* TX Descriptor Error IRQ */
196 int rxde_irq; /* RX Descriptor Error IRQ */
197 int serr_irq; /* MAL System Error IRQ */
198
199 struct list_head poll_list;
200 struct net_device poll_dev;
201
202 struct list_head list;
203 u32 tx_chan_mask;
204 u32 rx_chan_mask;
205
206 dma_addr_t bd_dma;
207 struct mal_descriptor *bd_virt;
208
209 struct of_device *ofdev;
210 int index;
211 spinlock_t lock;
212};
213
214static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg)
215{
216 return dcr_read(mal->dcr_host, mal->dcr_base + reg);
217}
218
219static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val)
220{
221 dcr_write(mal->dcr_host, mal->dcr_base + reg, val);
222}
223
224/* Register MAL devices */
225int mal_init(void);
226void mal_exit(void);
227
228int mal_register_commac(struct mal_instance *mal,
229 struct mal_commac *commac);
230void mal_unregister_commac(struct mal_instance *mal,
231 struct mal_commac *commac);
232int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size);
233
234/* Returns BD ring offset for a particular channel
235 (in 'struct mal_descriptor' elements)
236*/
237int mal_tx_bd_offset(struct mal_instance *mal, int channel);
238int mal_rx_bd_offset(struct mal_instance *mal, int channel);
239
240void mal_enable_tx_channel(struct mal_instance *mal, int channel);
241void mal_disable_tx_channel(struct mal_instance *mal, int channel);
242void mal_enable_rx_channel(struct mal_instance *mal, int channel);
243void mal_disable_rx_channel(struct mal_instance *mal, int channel);
244
245void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac);
246void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac);
247
248/* Add/remove EMAC to/from MAL polling list */
249void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac);
250void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac);
251
252/* Ethtool MAL registers */
253struct mal_regs {
254 u32 tx_count;
255 u32 rx_count;
256
257 u32 cfg;
258 u32 esr;
259 u32 ier;
260 u32 tx_casr;
261 u32 tx_carr;
262 u32 tx_eobisr;
263 u32 tx_deir;
264 u32 rx_casr;
265 u32 rx_carr;
266 u32 rx_eobisr;
267 u32 rx_deir;
268 u32 tx_ctpr[32];
269 u32 rx_ctpr[32];
270 u32 rcbs[32];
271};
272
273int mal_get_regs_len(struct mal_instance *mal);
274void *mal_dump_regs(struct mal_instance *mal, void *buf);
275
276#endif /* __IBM_NEWEMAC_MAL_H */
diff --git a/drivers/net/ibm_newemac/phy.c b/drivers/net/ibm_newemac/phy.c
new file mode 100644
index 000000000000..aa1f0ddf1e3e
--- /dev/null
+++ b/drivers/net/ibm_newemac/phy.c
@@ -0,0 +1,373 @@
1/*
2 * drivers/net/ibm_newemac/phy.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
5 * Borrowed from sungem_phy.c, though I only kept the generic MII
6 * driver for now.
7 *
8 * This file should be shared with other drivers or eventually
9 * merged as the "low level" part of miilib
10 *
11 * (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org)
12 * (c) 2004-2005, Eugene Surovegin <ebs@ebshome.net>
13 *
14 */
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/netdevice.h>
19#include <linux/mii.h>
20#include <linux/ethtool.h>
21#include <linux/delay.h>
22
23#include "emac.h"
24#include "phy.h"
25
26static inline int phy_read(struct mii_phy *phy, int reg)
27{
28 return phy->mdio_read(phy->dev, phy->address, reg);
29}
30
31static inline void phy_write(struct mii_phy *phy, int reg, int val)
32{
33 phy->mdio_write(phy->dev, phy->address, reg, val);
34}
35
36int emac_mii_reset_phy(struct mii_phy *phy)
37{
38 int val;
39 int limit = 10000;
40
41 val = phy_read(phy, MII_BMCR);
42 val &= ~(BMCR_ISOLATE | BMCR_ANENABLE);
43 val |= BMCR_RESET;
44 phy_write(phy, MII_BMCR, val);
45
46 udelay(300);
47
48 while (limit--) {
49 val = phy_read(phy, MII_BMCR);
50 if (val >= 0 && (val & BMCR_RESET) == 0)
51 break;
52 udelay(10);
53 }
54 if ((val & BMCR_ISOLATE) && limit > 0)
55 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
56
57 return limit <= 0;
58}
59
60static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
61{
62 int ctl, adv;
63
64 phy->autoneg = AUTONEG_ENABLE;
65 phy->speed = SPEED_10;
66 phy->duplex = DUPLEX_HALF;
67 phy->pause = phy->asym_pause = 0;
68 phy->advertising = advertise;
69
70 ctl = phy_read(phy, MII_BMCR);
71 if (ctl < 0)
72 return ctl;
73 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
74
75 /* First clear the PHY */
76 phy_write(phy, MII_BMCR, ctl);
77
78 /* Setup standard advertise */
79 adv = phy_read(phy, MII_ADVERTISE);
80 if (adv < 0)
81 return adv;
82 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
83 ADVERTISE_PAUSE_ASYM);
84 if (advertise & ADVERTISED_10baseT_Half)
85 adv |= ADVERTISE_10HALF;
86 if (advertise & ADVERTISED_10baseT_Full)
87 adv |= ADVERTISE_10FULL;
88 if (advertise & ADVERTISED_100baseT_Half)
89 adv |= ADVERTISE_100HALF;
90 if (advertise & ADVERTISED_100baseT_Full)
91 adv |= ADVERTISE_100FULL;
92 if (advertise & ADVERTISED_Pause)
93 adv |= ADVERTISE_PAUSE_CAP;
94 if (advertise & ADVERTISED_Asym_Pause)
95 adv |= ADVERTISE_PAUSE_ASYM;
96 phy_write(phy, MII_ADVERTISE, adv);
97
98 if (phy->features &
99 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
100 adv = phy_read(phy, MII_CTRL1000);
101 if (adv < 0)
102 return adv;
103 adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
104 if (advertise & ADVERTISED_1000baseT_Full)
105 adv |= ADVERTISE_1000FULL;
106 if (advertise & ADVERTISED_1000baseT_Half)
107 adv |= ADVERTISE_1000HALF;
108 phy_write(phy, MII_CTRL1000, adv);
109 }
110
111 /* Start/Restart aneg */
112 ctl = phy_read(phy, MII_BMCR);
113 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
114 phy_write(phy, MII_BMCR, ctl);
115
116 return 0;
117}
118
119static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
120{
121 int ctl;
122
123 phy->autoneg = AUTONEG_DISABLE;
124 phy->speed = speed;
125 phy->duplex = fd;
126 phy->pause = phy->asym_pause = 0;
127
128 ctl = phy_read(phy, MII_BMCR);
129 if (ctl < 0)
130 return ctl;
131 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
132
133 /* First clear the PHY */
134 phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
135
136 /* Select speed & duplex */
137 switch (speed) {
138 case SPEED_10:
139 break;
140 case SPEED_100:
141 ctl |= BMCR_SPEED100;
142 break;
143 case SPEED_1000:
144 ctl |= BMCR_SPEED1000;
145 break;
146 default:
147 return -EINVAL;
148 }
149 if (fd == DUPLEX_FULL)
150 ctl |= BMCR_FULLDPLX;
151 phy_write(phy, MII_BMCR, ctl);
152
153 return 0;
154}
155
156static int genmii_poll_link(struct mii_phy *phy)
157{
158 int status;
159
160 /* Clear latched value with dummy read */
161 phy_read(phy, MII_BMSR);
162 status = phy_read(phy, MII_BMSR);
163 if (status < 0 || (status & BMSR_LSTATUS) == 0)
164 return 0;
165 if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE))
166 return 0;
167 return 1;
168}
169
170static int genmii_read_link(struct mii_phy *phy)
171{
172 if (phy->autoneg == AUTONEG_ENABLE) {
173 int glpa = 0;
174 int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
175 if (lpa < 0)
176 return lpa;
177
178 if (phy->features &
179 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
180 int adv = phy_read(phy, MII_CTRL1000);
181 glpa = phy_read(phy, MII_STAT1000);
182
183 if (glpa < 0 || adv < 0)
184 return adv;
185
186 glpa &= adv << 2;
187 }
188
189 phy->speed = SPEED_10;
190 phy->duplex = DUPLEX_HALF;
191 phy->pause = phy->asym_pause = 0;
192
193 if (glpa & (LPA_1000FULL | LPA_1000HALF)) {
194 phy->speed = SPEED_1000;
195 if (glpa & LPA_1000FULL)
196 phy->duplex = DUPLEX_FULL;
197 } else if (lpa & (LPA_100FULL | LPA_100HALF)) {
198 phy->speed = SPEED_100;
199 if (lpa & LPA_100FULL)
200 phy->duplex = DUPLEX_FULL;
201 } else if (lpa & LPA_10FULL)
202 phy->duplex = DUPLEX_FULL;
203
204 if (phy->duplex == DUPLEX_FULL) {
205 phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
206 phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
207 }
208 } else {
209 int bmcr = phy_read(phy, MII_BMCR);
210 if (bmcr < 0)
211 return bmcr;
212
213 if (bmcr & BMCR_FULLDPLX)
214 phy->duplex = DUPLEX_FULL;
215 else
216 phy->duplex = DUPLEX_HALF;
217 if (bmcr & BMCR_SPEED1000)
218 phy->speed = SPEED_1000;
219 else if (bmcr & BMCR_SPEED100)
220 phy->speed = SPEED_100;
221 else
222 phy->speed = SPEED_10;
223
224 phy->pause = phy->asym_pause = 0;
225 }
226 return 0;
227}
228
229/* Generic implementation for most 10/100/1000 PHYs */
230static struct mii_phy_ops generic_phy_ops = {
231 .setup_aneg = genmii_setup_aneg,
232 .setup_forced = genmii_setup_forced,
233 .poll_link = genmii_poll_link,
234 .read_link = genmii_read_link
235};
236
237static struct mii_phy_def genmii_phy_def = {
238 .phy_id = 0x00000000,
239 .phy_id_mask = 0x00000000,
240 .name = "Generic MII",
241 .ops = &generic_phy_ops
242};
243
244/* CIS8201 */
245#define MII_CIS8201_10BTCSR 0x16
246#define TENBTCSR_ECHO_DISABLE 0x2000
247#define MII_CIS8201_EPCR 0x17
248#define EPCR_MODE_MASK 0x3000
249#define EPCR_GMII_MODE 0x0000
250#define EPCR_RGMII_MODE 0x1000
251#define EPCR_TBI_MODE 0x2000
252#define EPCR_RTBI_MODE 0x3000
253#define MII_CIS8201_ACSR 0x1c
254#define ACSR_PIN_PRIO_SELECT 0x0004
255
256static int cis8201_init(struct mii_phy *phy)
257{
258 int epcr;
259
260 epcr = phy_read(phy, MII_CIS8201_EPCR);
261 if (epcr < 0)
262 return epcr;
263
264 epcr &= ~EPCR_MODE_MASK;
265
266 switch (phy->mode) {
267 case PHY_MODE_TBI:
268 epcr |= EPCR_TBI_MODE;
269 break;
270 case PHY_MODE_RTBI:
271 epcr |= EPCR_RTBI_MODE;
272 break;
273 case PHY_MODE_GMII:
274 epcr |= EPCR_GMII_MODE;
275 break;
276 case PHY_MODE_RGMII:
277 default:
278 epcr |= EPCR_RGMII_MODE;
279 }
280
281 phy_write(phy, MII_CIS8201_EPCR, epcr);
282
283 /* MII regs override strap pins */
284 phy_write(phy, MII_CIS8201_ACSR,
285 phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
286
287 /* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
288 phy_write(phy, MII_CIS8201_10BTCSR,
289 phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
290
291 return 0;
292}
293
294static struct mii_phy_ops cis8201_phy_ops = {
295 .init = cis8201_init,
296 .setup_aneg = genmii_setup_aneg,
297 .setup_forced = genmii_setup_forced,
298 .poll_link = genmii_poll_link,
299 .read_link = genmii_read_link
300};
301
302static struct mii_phy_def cis8201_phy_def = {
303 .phy_id = 0x000fc410,
304 .phy_id_mask = 0x000ffff0,
305 .name = "CIS8201 Gigabit Ethernet",
306 .ops = &cis8201_phy_ops
307};
308
309static struct mii_phy_def *mii_phy_table[] = {
310 &cis8201_phy_def,
311 &genmii_phy_def,
312 NULL
313};
314
315int emac_mii_phy_probe(struct mii_phy *phy, int address)
316{
317 struct mii_phy_def *def;
318 int i;
319 u32 id;
320
321 phy->autoneg = AUTONEG_DISABLE;
322 phy->advertising = 0;
323 phy->address = address;
324 phy->speed = SPEED_10;
325 phy->duplex = DUPLEX_HALF;
326 phy->pause = phy->asym_pause = 0;
327
328 /* Take PHY out of isolate mode and reset it. */
329 if (emac_mii_reset_phy(phy))
330 return -ENODEV;
331
332 /* Read ID and find matching entry */
333 id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2);
334 for (i = 0; (def = mii_phy_table[i]) != NULL; i++)
335 if ((id & def->phy_id_mask) == def->phy_id)
336 break;
337 /* Should never be NULL (we have a generic entry), but... */
338 if (!def)
339 return -ENODEV;
340
341 phy->def = def;
342
343 /* Determine PHY features if needed */
344 phy->features = def->features;
345 if (!phy->features) {
346 u16 bmsr = phy_read(phy, MII_BMSR);
347 if (bmsr & BMSR_ANEGCAPABLE)
348 phy->features |= SUPPORTED_Autoneg;
349 if (bmsr & BMSR_10HALF)
350 phy->features |= SUPPORTED_10baseT_Half;
351 if (bmsr & BMSR_10FULL)
352 phy->features |= SUPPORTED_10baseT_Full;
353 if (bmsr & BMSR_100HALF)
354 phy->features |= SUPPORTED_100baseT_Half;
355 if (bmsr & BMSR_100FULL)
356 phy->features |= SUPPORTED_100baseT_Full;
357 if (bmsr & BMSR_ESTATEN) {
358 u16 esr = phy_read(phy, MII_ESTATUS);
359 if (esr & ESTATUS_1000_TFULL)
360 phy->features |= SUPPORTED_1000baseT_Full;
361 if (esr & ESTATUS_1000_THALF)
362 phy->features |= SUPPORTED_1000baseT_Half;
363 }
364 phy->features |= SUPPORTED_MII;
365 }
366
367 /* Setup default advertising */
368 phy->advertising = phy->features;
369
370 return 0;
371}
372
373MODULE_LICENSE("GPL");
diff --git a/drivers/net/ibm_newemac/phy.h b/drivers/net/ibm_newemac/phy.h
new file mode 100644
index 000000000000..6feca26afedb
--- /dev/null
+++ b/drivers/net/ibm_newemac/phy.h
@@ -0,0 +1,80 @@
1/*
2 * drivers/net/ibm_newemac/phy.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support
5 *
6 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
7 * February 2003
8 *
9 * Minor additions by Eugene Surovegin <ebs@ebshome.net>, 2004
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This file basically duplicates sungem_phy.{c,h} with different PHYs
17 * supported. I'm looking into merging that in a single mii layer more
18 * flexible than mii.c
19 */
20
21#ifndef __IBM_NEWEMAC_PHY_H
22#define __IBM_NEWEMAC_PHY_H
23
24struct mii_phy;
25
26/* Operations supported by any kind of PHY */
27struct mii_phy_ops {
28 int (*init) (struct mii_phy * phy);
29 int (*suspend) (struct mii_phy * phy, int wol_options);
30 int (*setup_aneg) (struct mii_phy * phy, u32 advertise);
31 int (*setup_forced) (struct mii_phy * phy, int speed, int fd);
32 int (*poll_link) (struct mii_phy * phy);
33 int (*read_link) (struct mii_phy * phy);
34};
35
36/* Structure used to statically define an mii/gii based PHY */
37struct mii_phy_def {
38 u32 phy_id; /* Concatenated ID1 << 16 | ID2 */
39 u32 phy_id_mask; /* Significant bits */
40 u32 features; /* Ethtool SUPPORTED_* defines or
41 0 for autodetect */
42 int magic_aneg; /* Autoneg does all speed test for us */
43 const char *name;
44 const struct mii_phy_ops *ops;
45};
46
47/* An instance of a PHY, partially borrowed from mii_if_info */
48struct mii_phy {
49 struct mii_phy_def *def;
50 u32 advertising; /* Ethtool ADVERTISED_* defines */
51 u32 features; /* Copied from mii_phy_def.features
52 or determined automaticaly */
53 int address; /* PHY address */
54 int mode; /* PHY mode */
55
56 /* 1: autoneg enabled, 0: disabled */
57 int autoneg;
58
59 /* forced speed & duplex (no autoneg)
60 * partner speed & duplex & pause (autoneg)
61 */
62 int speed;
63 int duplex;
64 int pause;
65 int asym_pause;
66
67 /* Provided by host chip */
68 struct net_device *dev;
69 int (*mdio_read) (struct net_device * dev, int addr, int reg);
70 void (*mdio_write) (struct net_device * dev, int addr, int reg,
71 int val);
72};
73
74/* Pass in a struct mii_phy with dev, mdio_read and mdio_write
75 * filled, the remaining fields will be filled on return
76 */
77int emac_mii_phy_probe(struct mii_phy *phy, int address);
78int emac_mii_reset_phy(struct mii_phy *phy);
79
80#endif /* __IBM_NEWEMAC_PHY_H */
diff --git a/drivers/net/ibm_newemac/rgmii.c b/drivers/net/ibm_newemac/rgmii.c
new file mode 100644
index 000000000000..bcd7fc639c40
--- /dev/null
+++ b/drivers/net/ibm_newemac/rgmii.c
@@ -0,0 +1,323 @@
1/*
2 * drivers/net/ibm_newemac/rgmii.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, RGMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * Copyright 2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#include <linux/kernel.h>
20#include <linux/ethtool.h>
21#include <asm/io.h>
22
23#include "emac.h"
24#include "debug.h"
25
26// XXX FIXME: Axon seems to support a subset of the RGMII, we
27// thus need to take that into account and possibly change some
28// of the bit settings below that don't seem to quite match the
29// AXON spec
30
31/* RGMIIx_FER */
32#define RGMII_FER_MASK(idx) (0x7 << ((idx) * 4))
33#define RGMII_FER_RTBI(idx) (0x4 << ((idx) * 4))
34#define RGMII_FER_RGMII(idx) (0x5 << ((idx) * 4))
35#define RGMII_FER_TBI(idx) (0x6 << ((idx) * 4))
36#define RGMII_FER_GMII(idx) (0x7 << ((idx) * 4))
37
38/* RGMIIx_SSR */
39#define RGMII_SSR_MASK(idx) (0x7 << ((idx) * 8))
40#define RGMII_SSR_100(idx) (0x2 << ((idx) * 8))
41#define RGMII_SSR_1000(idx) (0x4 << ((idx) * 8))
42
43/* RGMII bridge supports only GMII/TBI and RGMII/RTBI PHYs */
44static inline int rgmii_valid_mode(int phy_mode)
45{
46 return phy_mode == PHY_MODE_GMII ||
47 phy_mode == PHY_MODE_RGMII ||
48 phy_mode == PHY_MODE_TBI ||
49 phy_mode == PHY_MODE_RTBI;
50}
51
52static inline const char *rgmii_mode_name(int mode)
53{
54 switch (mode) {
55 case PHY_MODE_RGMII:
56 return "RGMII";
57 case PHY_MODE_TBI:
58 return "TBI";
59 case PHY_MODE_GMII:
60 return "GMII";
61 case PHY_MODE_RTBI:
62 return "RTBI";
63 default:
64 BUG();
65 }
66}
67
68static inline u32 rgmii_mode_mask(int mode, int input)
69{
70 switch (mode) {
71 case PHY_MODE_RGMII:
72 return RGMII_FER_RGMII(input);
73 case PHY_MODE_TBI:
74 return RGMII_FER_TBI(input);
75 case PHY_MODE_GMII:
76 return RGMII_FER_GMII(input);
77 case PHY_MODE_RTBI:
78 return RGMII_FER_RTBI(input);
79 default:
80 BUG();
81 }
82}
83
84int __devinit rgmii_attach(struct of_device *ofdev, int input, int mode)
85{
86 struct rgmii_instance *dev = dev_get_drvdata(&ofdev->dev);
87 struct rgmii_regs *p = dev->base;
88
89 RGMII_DBG(dev, "attach(%d)" NL, input);
90
91 /* Check if we need to attach to a RGMII */
92 if (input < 0 || !rgmii_valid_mode(mode)) {
93 printk(KERN_ERR "%s: unsupported settings !\n",
94 ofdev->node->full_name);
95 return -ENODEV;
96 }
97
98 mutex_lock(&dev->lock);
99
100 /* Enable this input */
101 out_be32(&p->fer, in_be32(&p->fer) | rgmii_mode_mask(mode, input));
102
103 printk(KERN_NOTICE "%s: input %d in %s mode\n",
104 ofdev->node->full_name, input, rgmii_mode_name(mode));
105
106 ++dev->users;
107
108 mutex_unlock(&dev->lock);
109
110 return 0;
111}
112
113void rgmii_set_speed(struct of_device *ofdev, int input, int speed)
114{
115 struct rgmii_instance *dev = dev_get_drvdata(&ofdev->dev);
116 struct rgmii_regs *p = dev->base;
117 u32 ssr;
118
119 mutex_lock(&dev->lock);
120
121 ssr = in_be32(&p->ssr) & ~RGMII_SSR_MASK(input);
122
123 RGMII_DBG(dev, "speed(%d, %d)" NL, input, speed);
124
125 if (speed == SPEED_1000)
126 ssr |= RGMII_SSR_1000(input);
127 else if (speed == SPEED_100)
128 ssr |= RGMII_SSR_100(input);
129
130 out_be32(&p->ssr, ssr);
131
132 mutex_unlock(&dev->lock);
133}
134
135void rgmii_get_mdio(struct of_device *ofdev, int input)
136{
137 struct rgmii_instance *dev = dev_get_drvdata(&ofdev->dev);
138 struct rgmii_regs *p = dev->base;
139 u32 fer;
140
141 RGMII_DBG2(dev, "get_mdio(%d)" NL, input);
142
143 if (dev->type != RGMII_AXON)
144 return;
145
146 mutex_lock(&dev->lock);
147
148 fer = in_be32(&p->fer);
149 fer |= 0x00080000u >> input;
150 out_be32(&p->fer, fer);
151 (void)in_be32(&p->fer);
152
153 DBG2(dev, " fer = 0x%08x\n", fer);
154}
155
156void rgmii_put_mdio(struct of_device *ofdev, int input)
157{
158 struct rgmii_instance *dev = dev_get_drvdata(&ofdev->dev);
159 struct rgmii_regs *p = dev->base;
160 u32 fer;
161
162 RGMII_DBG2(dev, "put_mdio(%d)" NL, input);
163
164 if (dev->type != RGMII_AXON)
165 return;
166
167 fer = in_be32(&p->fer);
168 fer &= ~(0x00080000u >> input);
169 out_be32(&p->fer, fer);
170 (void)in_be32(&p->fer);
171
172 DBG2(dev, " fer = 0x%08x\n", fer);
173
174 mutex_unlock(&dev->lock);
175}
176
177void __devexit rgmii_detach(struct of_device *ofdev, int input)
178{
179 struct rgmii_instance *dev = dev_get_drvdata(&ofdev->dev);
180 struct rgmii_regs *p = dev->base;
181
182 mutex_lock(&dev->lock);
183
184 BUG_ON(!dev || dev->users == 0);
185
186 RGMII_DBG(dev, "detach(%d)" NL, input);
187
188 /* Disable this input */
189 out_be32(&p->fer, in_be32(&p->fer) & ~RGMII_FER_MASK(input));
190
191 --dev->users;
192
193 mutex_unlock(&dev->lock);
194}
195
196int rgmii_get_regs_len(struct of_device *ofdev)
197{
198 return sizeof(struct emac_ethtool_regs_subhdr) +
199 sizeof(struct rgmii_regs);
200}
201
202void *rgmii_dump_regs(struct of_device *ofdev, void *buf)
203{
204 struct rgmii_instance *dev = dev_get_drvdata(&ofdev->dev);
205 struct emac_ethtool_regs_subhdr *hdr = buf;
206 struct rgmii_regs *regs = (struct rgmii_regs *)(hdr + 1);
207
208 hdr->version = 0;
209 hdr->index = 0; /* for now, are there chips with more than one
210 * rgmii ? if yes, then we'll add a cell_index
211 * like we do for emac
212 */
213 memcpy_fromio(regs, dev->base, sizeof(struct rgmii_regs));
214 return regs + 1;
215}
216
217
218static int __devinit rgmii_probe(struct of_device *ofdev,
219 const struct of_device_id *match)
220{
221 struct device_node *np = ofdev->node;
222 struct rgmii_instance *dev;
223 struct resource regs;
224 int rc;
225
226 rc = -ENOMEM;
227 dev = kzalloc(sizeof(struct rgmii_instance), GFP_KERNEL);
228 if (dev == NULL) {
229 printk(KERN_ERR "%s: could not allocate RGMII device!\n",
230 np->full_name);
231 goto err_gone;
232 }
233
234 mutex_init(&dev->lock);
235 dev->ofdev = ofdev;
236
237 rc = -ENXIO;
238 if (of_address_to_resource(np, 0, &regs)) {
239 printk(KERN_ERR "%s: Can't get registers address\n",
240 np->full_name);
241 goto err_free;
242 }
243
244 rc = -ENOMEM;
245 dev->base = (struct rgmii_regs *)ioremap(regs.start,
246 sizeof(struct rgmii_regs));
247 if (dev->base == NULL) {
248 printk(KERN_ERR "%s: Can't map device registers!\n",
249 np->full_name);
250 goto err_free;
251 }
252
253 /* Check for RGMII type */
254 if (device_is_compatible(ofdev->node, "ibm,rgmii-axon"))
255 dev->type = RGMII_AXON;
256 else
257 dev->type = RGMII_STANDARD;
258
259 DBG2(dev, " Boot FER = 0x%08x, SSR = 0x%08x\n",
260 in_be32(&dev->base->fer), in_be32(&dev->base->ssr));
261
262 /* Disable all inputs by default */
263 out_be32(&dev->base->fer, 0);
264
265 printk(KERN_INFO
266 "RGMII %s %s initialized\n",
267 dev->type == RGMII_STANDARD ? "standard" : "axon",
268 ofdev->node->full_name);
269
270 wmb();
271 dev_set_drvdata(&ofdev->dev, dev);
272
273 return 0;
274
275 err_free:
276 kfree(dev);
277 err_gone:
278 return rc;
279}
280
281static int __devexit rgmii_remove(struct of_device *ofdev)
282{
283 struct rgmii_instance *dev = dev_get_drvdata(&ofdev->dev);
284
285 dev_set_drvdata(&ofdev->dev, NULL);
286
287 WARN_ON(dev->users != 0);
288
289 iounmap(dev->base);
290 kfree(dev);
291
292 return 0;
293}
294
295static struct of_device_id rgmii_match[] =
296{
297 {
298 .type = "rgmii-interface",
299 .compatible = "ibm,rgmii",
300 },
301 {
302 .type = "emac-rgmii",
303 },
304 {},
305};
306
307static struct of_platform_driver rgmii_driver = {
308 .name = "emac-rgmii",
309 .match_table = rgmii_match,
310
311 .probe = rgmii_probe,
312 .remove = rgmii_remove,
313};
314
315int __init rgmii_init(void)
316{
317 return of_register_platform_driver(&rgmii_driver);
318}
319
320void rgmii_exit(void)
321{
322 of_unregister_platform_driver(&rgmii_driver);
323}
diff --git a/drivers/net/ibm_newemac/rgmii.h b/drivers/net/ibm_newemac/rgmii.h
new file mode 100644
index 000000000000..57806833121e
--- /dev/null
+++ b/drivers/net/ibm_newemac/rgmii.h
@@ -0,0 +1,76 @@
1/*
2 * drivers/net/ibm_newemac/rgmii.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, RGMII bridge support.
5 *
6 * Based on ocp_zmii.h/ibm_emac_zmii.h
7 * Armin Kuster akuster@mvista.com
8 *
9 * Copyright 2004 MontaVista Software, Inc.
10 * Matt Porter <mporter@kernel.crashing.org>
11 *
12 * Copyright (c) 2004, 2005 Zultys Technologies.
13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifndef __IBM_NEWEMAC_RGMII_H
22#define __IBM_NEWEMAC_RGMII_H
23
24/* RGMII bridge type */
25#define RGMII_STANDARD 0
26#define RGMII_AXON 1
27
28/* RGMII bridge */
29struct rgmii_regs {
30 u32 fer; /* Function enable register */
31 u32 ssr; /* Speed select register */
32};
33
34/* RGMII device */
35struct rgmii_instance {
36 struct rgmii_regs __iomem *base;
37
38 /* Type of RGMII bridge */
39 int type;
40
41 /* Only one EMAC whacks us at a time */
42 struct mutex lock;
43
44 /* number of EMACs using this RGMII bridge */
45 int users;
46
47 /* OF device instance */
48 struct of_device *ofdev;
49};
50
51#ifdef CONFIG_IBM_NEW_EMAC_RGMII
52
53extern int rgmii_init(void);
54extern void rgmii_exit(void);
55extern int rgmii_attach(struct of_device *ofdev, int input, int mode);
56extern void rgmii_detach(struct of_device *ofdev, int input);
57extern void rgmii_get_mdio(struct of_device *ofdev, int input);
58extern void rgmii_put_mdio(struct of_device *ofdev, int input);
59extern void rgmii_set_speed(struct of_device *ofdev, int input, int speed);
60extern int rgmii_get_regs_len(struct of_device *ofdev);
61extern void *rgmii_dump_regs(struct of_device *ofdev, void *buf);
62
63#else
64
65# define rgmii_init() 0
66# define rgmii_exit() do { } while(0)
67# define rgmii_attach(x,y,z) (-ENXIO)
68# define rgmii_detach(x,y) do { } while(0)
69# define rgmii_get_mdio(o,i) do { } while (0)
70# define rgmii_put_mdio(o,i) do { } while (0)
71# define rgmii_set_speed(x,y,z) do { } while(0)
72# define rgmii_get_regs_len(x) 0
73# define rgmii_dump_regs(x,buf) (buf)
74#endif /* !CONFIG_IBM_NEW_EMAC_RGMII */
75
76#endif /* __IBM_NEWEMAC_RGMII_H */
diff --git a/drivers/net/ibm_newemac/tah.c b/drivers/net/ibm_newemac/tah.c
new file mode 100644
index 000000000000..e05c7e81efb6
--- /dev/null
+++ b/drivers/net/ibm_newemac/tah.c
@@ -0,0 +1,173 @@
1/*
2 * drivers/net/ibm_newemac/tah.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, TAH support.
5 *
6 * Copyright 2004 MontaVista Software, Inc.
7 * Matt Porter <mporter@kernel.crashing.org>
8 *
9 * Copyright (c) 2005 Eugene Surovegin <ebs@ebshome.net>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <asm/io.h>
17
18#include "emac.h"
19#include "core.h"
20
21int __devinit tah_attach(struct of_device *ofdev, int channel)
22{
23 struct tah_instance *dev = dev_get_drvdata(&ofdev->dev);
24
25 mutex_lock(&dev->lock);
26 /* Reset has been done at probe() time... nothing else to do for now */
27 ++dev->users;
28 mutex_unlock(&dev->lock);
29
30 return 0;
31}
32
33void __devexit tah_detach(struct of_device *ofdev, int channel)
34{
35 struct tah_instance *dev = dev_get_drvdata(&ofdev->dev);
36
37 mutex_lock(&dev->lock);
38 --dev->users;
39 mutex_unlock(&dev->lock);
40}
41
42void tah_reset(struct of_device *ofdev)
43{
44 struct tah_instance *dev = dev_get_drvdata(&ofdev->dev);
45 struct tah_regs *p = dev->base;
46 int n;
47
48 /* Reset TAH */
49 out_be32(&p->mr, TAH_MR_SR);
50 n = 100;
51 while ((in_be32(&p->mr) & TAH_MR_SR) && n)
52 --n;
53
54 if (unlikely(!n))
55 printk(KERN_ERR "%s: reset timeout\n", ofdev->node->full_name);
56
57 /* 10KB TAH TX FIFO accomodates the max MTU of 9000 */
58 out_be32(&p->mr,
59 TAH_MR_CVR | TAH_MR_ST_768 | TAH_MR_TFS_10KB | TAH_MR_DTFP |
60 TAH_MR_DIG);
61}
62
63int tah_get_regs_len(struct of_device *ofdev)
64{
65 return sizeof(struct emac_ethtool_regs_subhdr) +
66 sizeof(struct tah_regs);
67}
68
69void *tah_dump_regs(struct of_device *ofdev, void *buf)
70{
71 struct tah_instance *dev = dev_get_drvdata(&ofdev->dev);
72 struct emac_ethtool_regs_subhdr *hdr = buf;
73 struct tah_regs *regs = (struct tah_regs *)(hdr + 1);
74
75 hdr->version = 0;
76 hdr->index = 0; /* for now, are there chips with more than one
77 * zmii ? if yes, then we'll add a cell_index
78 * like we do for emac
79 */
80 memcpy_fromio(regs, dev->base, sizeof(struct tah_regs));
81 return regs + 1;
82}
83
84static int __devinit tah_probe(struct of_device *ofdev,
85 const struct of_device_id *match)
86{
87 struct device_node *np = ofdev->node;
88 struct tah_instance *dev;
89 struct resource regs;
90 int rc;
91
92 rc = -ENOMEM;
93 dev = kzalloc(sizeof(struct tah_instance), GFP_KERNEL);
94 if (dev == NULL) {
95 printk(KERN_ERR "%s: could not allocate TAH device!\n",
96 np->full_name);
97 goto err_gone;
98 }
99
100 mutex_init(&dev->lock);
101 dev->ofdev = ofdev;
102
103 rc = -ENXIO;
104 if (of_address_to_resource(np, 0, &regs)) {
105 printk(KERN_ERR "%s: Can't get registers address\n",
106 np->full_name);
107 goto err_free;
108 }
109
110 rc = -ENOMEM;
111 dev->base = (struct tah_regs *)ioremap(regs.start,
112 sizeof(struct tah_regs));
113 if (dev->base == NULL) {
114 printk(KERN_ERR "%s: Can't map device registers!\n",
115 np->full_name);
116 goto err_free;
117 }
118
119 /* Initialize TAH and enable IPv4 checksum verification, no TSO yet */
120 tah_reset(ofdev);
121
122 printk(KERN_INFO
123 "TAH %s initialized\n", ofdev->node->full_name);
124 wmb();
125 dev_set_drvdata(&ofdev->dev, dev);
126
127 return 0;
128
129 err_free:
130 kfree(dev);
131 err_gone:
132 return rc;
133}
134
135static int __devexit tah_remove(struct of_device *ofdev)
136{
137 struct tah_instance *dev = dev_get_drvdata(&ofdev->dev);
138
139 dev_set_drvdata(&ofdev->dev, NULL);
140
141 WARN_ON(dev->users != 0);
142
143 iounmap(dev->base);
144 kfree(dev);
145
146 return 0;
147}
148
149static struct of_device_id tah_match[] =
150{
151 {
152 .type = "tah",
153 },
154 {},
155};
156
157static struct of_platform_driver tah_driver = {
158 .name = "emac-tah",
159 .match_table = tah_match,
160
161 .probe = tah_probe,
162 .remove = tah_remove,
163};
164
165int __init tah_init(void)
166{
167 return of_register_platform_driver(&tah_driver);
168}
169
170void tah_exit(void)
171{
172 of_unregister_platform_driver(&tah_driver);
173}
diff --git a/drivers/net/ibm_newemac/tah.h b/drivers/net/ibm_newemac/tah.h
new file mode 100644
index 000000000000..bc41853b6e26
--- /dev/null
+++ b/drivers/net/ibm_newemac/tah.h
@@ -0,0 +1,90 @@
1/*
2 * drivers/net/ibm_newemac/tah.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, TAH support.
5 *
6 * Copyright 2004 MontaVista Software, Inc.
7 * Matt Porter <mporter@kernel.crashing.org>
8 *
9 * Copyright (c) 2005 Eugene Surovegin <ebs@ebshome.net>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#ifndef __IBM_NEWEMAC_TAH_H
18#define __IBM_NEWEMAC_TAH_H
19
20/* TAH */
21struct tah_regs {
22 u32 revid;
23 u32 pad[3];
24 u32 mr;
25 u32 ssr0;
26 u32 ssr1;
27 u32 ssr2;
28 u32 ssr3;
29 u32 ssr4;
30 u32 ssr5;
31 u32 tsr;
32};
33
34
35/* TAH device */
36struct tah_instance {
37 struct tah_regs __iomem *base;
38
39 /* Only one EMAC whacks us at a time */
40 struct mutex lock;
41
42 /* number of EMACs using this TAH */
43 int users;
44
45 /* OF device instance */
46 struct of_device *ofdev;
47};
48
49
50/* TAH engine */
51#define TAH_MR_CVR 0x80000000
52#define TAH_MR_SR 0x40000000
53#define TAH_MR_ST_256 0x01000000
54#define TAH_MR_ST_512 0x02000000
55#define TAH_MR_ST_768 0x03000000
56#define TAH_MR_ST_1024 0x04000000
57#define TAH_MR_ST_1280 0x05000000
58#define TAH_MR_ST_1536 0x06000000
59#define TAH_MR_TFS_16KB 0x00000000
60#define TAH_MR_TFS_2KB 0x00200000
61#define TAH_MR_TFS_4KB 0x00400000
62#define TAH_MR_TFS_6KB 0x00600000
63#define TAH_MR_TFS_8KB 0x00800000
64#define TAH_MR_TFS_10KB 0x00a00000
65#define TAH_MR_DTFP 0x00100000
66#define TAH_MR_DIG 0x00080000
67
68#ifdef CONFIG_IBM_NEW_EMAC_TAH
69
70extern int tah_init(void);
71extern void tah_exit(void);
72extern int tah_attach(struct of_device *ofdev, int channel);
73extern void tah_detach(struct of_device *ofdev, int channel);
74extern void tah_reset(struct of_device *ofdev);
75extern int tah_get_regs_len(struct of_device *ofdev);
76extern void *tah_dump_regs(struct of_device *ofdev, void *buf);
77
78#else
79
80# define tah_init() 0
81# define tah_exit() do { } while(0)
82# define tah_attach(x,y) (-ENXIO)
83# define tah_detach(x,y) do { } while(0)
84# define tah_reset(x) do { } while(0)
85# define tah_get_regs_len(x) 0
86# define tah_dump_regs(x,buf) (buf)
87
88#endif /* !CONFIG_IBM_NEW_EMAC_TAH */
89
90#endif /* __IBM_NEWEMAC_TAH_H */
diff --git a/drivers/net/ibm_newemac/zmii.c b/drivers/net/ibm_newemac/zmii.c
new file mode 100644
index 000000000000..d06312901848
--- /dev/null
+++ b/drivers/net/ibm_newemac/zmii.c
@@ -0,0 +1,322 @@
1/*
2 * drivers/net/ibm_newemac/zmii.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, ZMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2001 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#include <linux/kernel.h>
20#include <linux/ethtool.h>
21#include <asm/io.h>
22
23#include "emac.h"
24#include "core.h"
25
26/* ZMIIx_FER */
27#define ZMII_FER_MDI(idx) (0x80000000 >> ((idx) * 4))
28#define ZMII_FER_MDI_ALL (ZMII_FER_MDI(0) | ZMII_FER_MDI(1) | \
29 ZMII_FER_MDI(2) | ZMII_FER_MDI(3))
30
31#define ZMII_FER_SMII(idx) (0x40000000 >> ((idx) * 4))
32#define ZMII_FER_RMII(idx) (0x20000000 >> ((idx) * 4))
33#define ZMII_FER_MII(idx) (0x10000000 >> ((idx) * 4))
34
35/* ZMIIx_SSR */
36#define ZMII_SSR_SCI(idx) (0x40000000 >> ((idx) * 4))
37#define ZMII_SSR_FSS(idx) (0x20000000 >> ((idx) * 4))
38#define ZMII_SSR_SP(idx) (0x10000000 >> ((idx) * 4))
39
40/* ZMII only supports MII, RMII and SMII
41 * we also support autodetection for backward compatibility
42 */
43static inline int zmii_valid_mode(int mode)
44{
45 return mode == PHY_MODE_MII ||
46 mode == PHY_MODE_RMII ||
47 mode == PHY_MODE_SMII ||
48 mode == PHY_MODE_NA;
49}
50
51static inline const char *zmii_mode_name(int mode)
52{
53 switch (mode) {
54 case PHY_MODE_MII:
55 return "MII";
56 case PHY_MODE_RMII:
57 return "RMII";
58 case PHY_MODE_SMII:
59 return "SMII";
60 default:
61 BUG();
62 }
63}
64
65static inline u32 zmii_mode_mask(int mode, int input)
66{
67 switch (mode) {
68 case PHY_MODE_MII:
69 return ZMII_FER_MII(input);
70 case PHY_MODE_RMII:
71 return ZMII_FER_RMII(input);
72 case PHY_MODE_SMII:
73 return ZMII_FER_SMII(input);
74 default:
75 return 0;
76 }
77}
78
79int __devinit zmii_attach(struct of_device *ofdev, int input, int *mode)
80{
81 struct zmii_instance *dev = dev_get_drvdata(&ofdev->dev);
82 struct zmii_regs *p = dev->base;
83
84 ZMII_DBG(dev, "init(%d, %d)" NL, input, *mode);
85
86 if (!zmii_valid_mode(*mode))
87 /* Probably an EMAC connected to RGMII,
88 * but it still may need ZMII for MDIO so
89 * we don't fail here.
90 */
91 return 0;
92
93 mutex_lock(&dev->lock);
94
95 /* Autodetect ZMII mode if not specified.
96 * This is only for backward compatibility with the old driver.
97 * Please, always specify PHY mode in your board port to avoid
98 * any surprises.
99 */
100 if (dev->mode == PHY_MODE_NA) {
101 if (*mode == PHY_MODE_NA) {
102 u32 r = dev->fer_save;
103
104 ZMII_DBG(dev, "autodetecting mode, FER = 0x%08x" NL, r);
105
106 if (r & (ZMII_FER_MII(0) | ZMII_FER_MII(1)))
107 dev->mode = PHY_MODE_MII;
108 else if (r & (ZMII_FER_RMII(0) | ZMII_FER_RMII(1)))
109 dev->mode = PHY_MODE_RMII;
110 else
111 dev->mode = PHY_MODE_SMII;
112 } else
113 dev->mode = *mode;
114
115 printk(KERN_NOTICE "%s: bridge in %s mode\n",
116 ofdev->node->full_name, zmii_mode_name(dev->mode));
117 } else {
118 /* All inputs must use the same mode */
119 if (*mode != PHY_MODE_NA && *mode != dev->mode) {
120 printk(KERN_ERR
121 "%s: invalid mode %d specified for input %d\n",
122 ofdev->node->full_name, *mode, input);
123 mutex_unlock(&dev->lock);
124 return -EINVAL;
125 }
126 }
127
128 /* Report back correct PHY mode,
129 * it may be used during PHY initialization.
130 */
131 *mode = dev->mode;
132
133 /* Enable this input */
134 out_be32(&p->fer, in_be32(&p->fer) | zmii_mode_mask(dev->mode, input));
135 ++dev->users;
136
137 mutex_unlock(&dev->lock);
138
139 return 0;
140}
141
142void zmii_get_mdio(struct of_device *ofdev, int input)
143{
144 struct zmii_instance *dev = dev_get_drvdata(&ofdev->dev);
145 u32 fer;
146
147 ZMII_DBG2(dev, "get_mdio(%d)" NL, input);
148
149 mutex_lock(&dev->lock);
150
151 fer = in_be32(&dev->base->fer) & ~ZMII_FER_MDI_ALL;
152 out_be32(&dev->base->fer, fer | ZMII_FER_MDI(input));
153}
154
155void zmii_put_mdio(struct of_device *ofdev, int input)
156{
157 struct zmii_instance *dev = dev_get_drvdata(&ofdev->dev);
158
159 ZMII_DBG2(dev, "put_mdio(%d)" NL, input);
160 mutex_unlock(&dev->lock);
161}
162
163
164void zmii_set_speed(struct of_device *ofdev, int input, int speed)
165{
166 struct zmii_instance *dev = dev_get_drvdata(&ofdev->dev);
167 u32 ssr;
168
169 mutex_lock(&dev->lock);
170
171 ssr = in_be32(&dev->base->ssr);
172
173 ZMII_DBG(dev, "speed(%d, %d)" NL, input, speed);
174
175 if (speed == SPEED_100)
176 ssr |= ZMII_SSR_SP(input);
177 else
178 ssr &= ~ZMII_SSR_SP(input);
179
180 out_be32(&dev->base->ssr, ssr);
181
182 mutex_unlock(&dev->lock);
183}
184
185void __devexit zmii_detach(struct of_device *ofdev, int input)
186{
187 struct zmii_instance *dev = dev_get_drvdata(&ofdev->dev);
188
189 BUG_ON(!dev || dev->users == 0);
190
191 mutex_lock(&dev->lock);
192
193 ZMII_DBG(dev, "detach(%d)" NL, input);
194
195 /* Disable this input */
196 out_be32(&dev->base->fer,
197 in_be32(&dev->base->fer) & ~zmii_mode_mask(dev->mode, input));
198
199 --dev->users;
200
201 mutex_unlock(&dev->lock);
202}
203
204int zmii_get_regs_len(struct of_device *ofdev)
205{
206 return sizeof(struct emac_ethtool_regs_subhdr) +
207 sizeof(struct zmii_regs);
208}
209
210void *zmii_dump_regs(struct of_device *ofdev, void *buf)
211{
212 struct zmii_instance *dev = dev_get_drvdata(&ofdev->dev);
213 struct emac_ethtool_regs_subhdr *hdr = buf;
214 struct zmii_regs *regs = (struct zmii_regs *)(hdr + 1);
215
216 hdr->version = 0;
217 hdr->index = 0; /* for now, are there chips with more than one
218 * zmii ? if yes, then we'll add a cell_index
219 * like we do for emac
220 */
221 memcpy_fromio(regs, dev->base, sizeof(struct zmii_regs));
222 return regs + 1;
223}
224
225static int __devinit zmii_probe(struct of_device *ofdev,
226 const struct of_device_id *match)
227{
228 struct device_node *np = ofdev->node;
229 struct zmii_instance *dev;
230 struct resource regs;
231 int rc;
232
233 rc = -ENOMEM;
234 dev = kzalloc(sizeof(struct zmii_instance), GFP_KERNEL);
235 if (dev == NULL) {
236 printk(KERN_ERR "%s: could not allocate ZMII device!\n",
237 np->full_name);
238 goto err_gone;
239 }
240
241 mutex_init(&dev->lock);
242 dev->ofdev = ofdev;
243 dev->mode = PHY_MODE_NA;
244
245 rc = -ENXIO;
246 if (of_address_to_resource(np, 0, &regs)) {
247 printk(KERN_ERR "%s: Can't get registers address\n",
248 np->full_name);
249 goto err_free;
250 }
251
252 rc = -ENOMEM;
253 dev->base = (struct zmii_regs *)ioremap(regs.start,
254 sizeof(struct zmii_regs));
255 if (dev->base == NULL) {
256 printk(KERN_ERR "%s: Can't map device registers!\n",
257 np->full_name);
258 goto err_free;
259 }
260
261 /* We may need FER value for autodetection later */
262 dev->fer_save = in_be32(&dev->base->fer);
263
264 /* Disable all inputs by default */
265 out_be32(&dev->base->fer, 0);
266
267 printk(KERN_INFO
268 "ZMII %s initialized\n", ofdev->node->full_name);
269 wmb();
270 dev_set_drvdata(&ofdev->dev, dev);
271
272 return 0;
273
274 err_free:
275 kfree(dev);
276 err_gone:
277 return rc;
278}
279
280static int __devexit zmii_remove(struct of_device *ofdev)
281{
282 struct zmii_instance *dev = dev_get_drvdata(&ofdev->dev);
283
284 dev_set_drvdata(&ofdev->dev, NULL);
285
286 WARN_ON(dev->users != 0);
287
288 iounmap(dev->base);
289 kfree(dev);
290
291 return 0;
292}
293
294static struct of_device_id zmii_match[] =
295{
296 {
297 .compatible = "ibm,zmii",
298 },
299 /* For backward compat with old DT */
300 {
301 .type = "emac-zmii",
302 },
303 {},
304};
305
306static struct of_platform_driver zmii_driver = {
307 .name = "emac-zmii",
308 .match_table = zmii_match,
309
310 .probe = zmii_probe,
311 .remove = zmii_remove,
312};
313
314int __init zmii_init(void)
315{
316 return of_register_platform_driver(&zmii_driver);
317}
318
319void zmii_exit(void)
320{
321 of_unregister_platform_driver(&zmii_driver);
322}
diff --git a/drivers/net/ibm_newemac/zmii.h b/drivers/net/ibm_newemac/zmii.h
new file mode 100644
index 000000000000..82a9968b1f74
--- /dev/null
+++ b/drivers/net/ibm_newemac/zmii.h
@@ -0,0 +1,73 @@
1/*
2 * drivers/net/ibm_newemac/zmii.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, ZMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2001 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#ifndef __IBM_NEWEMAC_ZMII_H
20#define __IBM_NEWEMAC_ZMII_H
21
22/* ZMII bridge registers */
23struct zmii_regs {
24 u32 fer; /* Function enable reg */
25 u32 ssr; /* Speed select reg */
26 u32 smiirs; /* SMII status reg */
27};
28
29/* ZMII device */
30struct zmii_instance {
31 struct zmii_regs __iomem *base;
32
33 /* Only one EMAC whacks us at a time */
34 struct mutex lock;
35
36 /* subset of PHY_MODE_XXXX */
37 int mode;
38
39 /* number of EMACs using this ZMII bridge */
40 int users;
41
42 /* FER value left by firmware */
43 u32 fer_save;
44
45 /* OF device instance */
46 struct of_device *ofdev;
47};
48
49#ifdef CONFIG_IBM_NEW_EMAC_ZMII
50
51extern int zmii_init(void);
52extern void zmii_exit(void);
53extern int zmii_attach(struct of_device *ofdev, int input, int *mode);
54extern void zmii_detach(struct of_device *ofdev, int input);
55extern void zmii_get_mdio(struct of_device *ofdev, int input);
56extern void zmii_put_mdio(struct of_device *ofdev, int input);
57extern void zmii_set_speed(struct of_device *ofdev, int input, int speed);
58extern int zmii_get_regs_len(struct of_device *ocpdev);
59extern void *zmii_dump_regs(struct of_device *ofdev, void *buf);
60
61#else
62# define zmii_init() 0
63# define zmii_exit() do { } while(0)
64# define zmii_attach(x,y,z) (-ENXIO)
65# define zmii_detach(x,y) do { } while(0)
66# define zmii_get_mdio(x,y) do { } while(0)
67# define zmii_put_mdio(x,y) do { } while(0)
68# define zmii_set_speed(x,y,z) do { } while(0)
69# define zmii_get_regs_len(x) 0
70# define zmii_dump_regs(x,buf) (buf)
71#endif /* !CONFIG_IBM_NEW_EMAC_ZMII */
72
73#endif /* __IBM_NEWEMAC_ZMII_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-27 12:23:23 -0500