diff options
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 256b6611e718..d5111d165434 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c | |||
| @@ -867,12 +867,13 @@ static void __init probe_pcache(void) | |||
| 867 | /* Workaround for cache instruction bug of VR4131 */ | 867 | /* Workaround for cache instruction bug of VR4131 */ |
| 868 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || | 868 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || |
| 869 | c->processor_id == 0x0c82U) { | 869 | c->processor_id == 0x0c82U) { |
| 870 | config &= ~0x00000030U; | ||
| 871 | config |= 0x00400000U; | 870 | config |= 0x00400000U; |
| 872 | if (c->processor_id == 0x0c80U) | 871 | if (c->processor_id == 0x0c80U) |
| 873 | config |= VR41_CONF_BP; | 872 | config |= VR41_CONF_BP; |
| 874 | write_c0_config(config); | 873 | write_c0_config(config); |
| 875 | } | 874 | } else |
| 875 | c->options |= MIPS_CPU_CACHE_CDEX_P; | ||
| 876 | |||
| 876 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); | 877 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
| 877 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | 878 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); |
| 878 | c->icache.ways = 2; | 879 | c->icache.ways = 2; |
| @@ -882,8 +883,6 @@ static void __init probe_pcache(void) | |||
| 882 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | 883 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); |
| 883 | c->dcache.ways = 2; | 884 | c->dcache.ways = 2; |
| 884 | c->dcache.waybit = __ffs(dcache_size/2); | 885 | c->dcache.waybit = __ffs(dcache_size/2); |
| 885 | |||
| 886 | c->options |= MIPS_CPU_CACHE_CDEX_P; | ||
| 887 | break; | 886 | break; |
| 888 | 887 | ||
| 889 | case CPU_VR41XX: | 888 | case CPU_VR41XX: |
