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-rw-r--r--Documentation/cpu-freq/user-guide.txt1
-rw-r--r--arch/arm/Kconfig9
-rw-r--r--arch/arm/configs/colibri_defconfig1481
-rw-r--r--arch/arm/configs/eseries_pxa_defconfig1499
-rw-r--r--arch/arm/configs/littleton_defconfig783
-rw-r--r--arch/arm/configs/pcm027_defconfig1096
-rw-r--r--arch/arm/mach-omap1/board-fsample.c2
-rw-r--r--arch/arm/mach-omap1/board-h2.c2
-rw-r--r--arch/arm/mach-omap1/board-h3.c2
-rw-r--r--arch/arm/mach-omap1/board-innovator.c4
-rw-r--r--arch/arm/mach-omap1/board-osk.c2
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c2
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c2
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-apollon.c2
-rw-r--r--arch/arm/mach-pxa/Kconfig73
-rw-r--r--arch/arm/mach-pxa/Makefile15
-rw-r--r--arch/arm/mach-pxa/cm-x270.c7
-rw-r--r--arch/arm/mach-pxa/colibri.c134
-rw-r--r--arch/arm/mach-pxa/corgi.c189
-rw-r--r--arch/arm/mach-pxa/corgi_lcd.c299
-rw-r--r--arch/arm/mach-pxa/corgi_ssp.c1
-rw-r--r--arch/arm/mach-pxa/cpu-pxa.c294
-rw-r--r--arch/arm/mach-pxa/devices.c662
-rw-r--r--arch/arm/mach-pxa/devices.h12
-rw-r--r--arch/arm/mach-pxa/eseries.c101
-rw-r--r--arch/arm/mach-pxa/generic.c251
-rw-r--r--arch/arm/mach-pxa/idp.c2
-rw-r--r--arch/arm/mach-pxa/littleton.c325
-rw-r--r--arch/arm/mach-pxa/lpd270.c1
-rw-r--r--arch/arm/mach-pxa/lubbock.c30
-rw-r--r--arch/arm/mach-pxa/magician.c218
-rw-r--r--arch/arm/mach-pxa/mainstone.c79
-rw-r--r--arch/arm/mach-pxa/mfp.c261
-rw-r--r--arch/arm/mach-pxa/pcm027.c216
-rw-r--r--arch/arm/mach-pxa/pcm990-baseboard.c330
-rw-r--r--arch/arm/mach-pxa/pm.c33
-rw-r--r--arch/arm/mach-pxa/poodle.c6
-rw-r--r--arch/arm/mach-pxa/pxa25x.c22
-rw-r--r--arch/arm/mach-pxa/pxa27x.c59
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c241
-rw-r--r--arch/arm/mach-pxa/sharpsl.h19
-rw-r--r--arch/arm/mach-pxa/sleep.S9
-rw-r--r--arch/arm/mach-pxa/spitz.c112
-rw-r--r--arch/arm/mach-pxa/ssp.c384
-rw-r--r--arch/arm/mach-pxa/standby.S83
-rw-r--r--arch/arm/mach-pxa/time.c84
-rw-r--r--arch/arm/mach-pxa/tosa.c11
-rw-r--r--arch/arm/mach-pxa/trizeps4.c7
-rw-r--r--arch/arm/mach-pxa/zylonite.c96
-rw-r--r--arch/arm/mach-pxa/zylonite_pxa300.c65
-rw-r--r--arch/arm/mach-pxa/zylonite_pxa320.c45
-rw-r--r--arch/arm/plat-omap/debug-devices.c2
-rw-r--r--drivers/input/touchscreen/corgi_ts.c8
-rw-r--r--drivers/mmc/host/pxamci.c61
-rw-r--r--drivers/mmc/host/pxamci.h2
-rw-r--r--drivers/net/dm9000.c3
-rw-r--r--drivers/net/smc91x.c19
-rw-r--r--drivers/net/smc91x.h24
-rw-r--r--drivers/pcmcia/pxa2xx_base.c1
-rw-r--r--drivers/rtc/rtc-sa1100.c31
-rw-r--r--drivers/spi/Kconfig1
-rw-r--r--drivers/spi/pxa2xx_spi.c139
-rw-r--r--drivers/usb/Kconfig1
-rw-r--r--drivers/usb/host/ohci-hcd.c2
-rw-r--r--drivers/usb/host/ohci-pxa27x.c13
-rw-r--r--include/asm-arm/arch-pxa/colibri.h19
-rw-r--r--include/asm-arm/arch-pxa/corgi.h1
-rw-r--r--include/asm-arm/arch-pxa/irqs.h10
-rw-r--r--include/asm-arm/arch-pxa/littleton.h6
-rw-r--r--include/asm-arm/arch-pxa/magician.h111
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa300.h1
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa320.h1
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa3xx.h252
-rw-r--r--include/asm-arm/arch-pxa/mfp.h409
-rw-r--r--include/asm-arm/arch-pxa/mmc.h2
-rw-r--r--include/asm-arm/arch-pxa/pcm027.h75
-rw-r--r--include/asm-arm/arch-pxa/pcm990_baseboard.h275
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h370
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx-regs.h84
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx_spi.h24
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx-regs.h86
-rw-r--r--include/asm-arm/arch-pxa/regs-ssp.h112
-rw-r--r--include/asm-arm/arch-pxa/sharpsl.h2
-rw-r--r--include/asm-arm/arch-pxa/spitz.h2
-rw-r--r--include/asm-arm/arch-pxa/ssp.h36
-rw-r--r--include/asm-arm/arch-pxa/uncompress.h14
-rw-r--r--include/asm-arm/arch-pxa/zylonite.h9
88 files changed, 10029 insertions, 1844 deletions
diff --git a/Documentation/cpu-freq/user-guide.txt b/Documentation/cpu-freq/user-guide.txt
index 555c8cf3650a..af3b925ece08 100644
--- a/Documentation/cpu-freq/user-guide.txt
+++ b/Documentation/cpu-freq/user-guide.txt
@@ -45,6 +45,7 @@ The following ARM processors are supported by cpufreq:
45ARM Integrator 45ARM Integrator
46ARM-SA1100 46ARM-SA1100
47ARM-SA1110 47ARM-SA1110
48Intel PXA
48 49
49 50
501.2 x86 511.2 x86
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6835a4c8affa..de211ac3853e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -356,6 +356,7 @@ config ARCH_PXA
356 select GENERIC_GPIO 356 select GENERIC_GPIO
357 select GENERIC_TIME 357 select GENERIC_TIME
358 select GENERIC_CLOCKEVENTS 358 select GENERIC_CLOCKEVENTS
359 select TICK_ONESHOT
359 help 360 help
360 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 361 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
361 362
@@ -895,7 +896,7 @@ config KEXEC
895 896
896endmenu 897endmenu
897 898
898if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX ) 899if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
899 900
900menu "CPU Frequency scaling" 901menu "CPU Frequency scaling"
901 902
@@ -931,6 +932,12 @@ config CPU_FREQ_IMX
931 932
932 If in doubt, say N. 933 If in doubt, say N.
933 934
935config CPU_FREQ_PXA
936 bool
937 depends on CPU_FREQ && ARCH_PXA && PXA25x
938 default y
939 select CPU_FREQ_DEFAULT_GOV_USERSPACE
940
934endmenu 941endmenu
935 942
936endif 943endif
diff --git a/arch/arm/configs/colibri_defconfig b/arch/arm/configs/colibri_defconfig
new file mode 100644
index 000000000000..c3e3418ed4fe
--- /dev/null
+++ b/arch/arm/configs/colibri_defconfig
@@ -0,0 +1,1481 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24-rc3
4# Mon Dec 3 13:36:09 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_ARCH_MTD_XIP=y
26CONFIG_VECTORS_BASE=0xffff0000
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28
29#
30# General setup
31#
32CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y
34CONFIG_LOCK_KERNEL=y
35CONFIG_INIT_ENV_ARG_LIMIT=32
36CONFIG_LOCALVERSION=""
37CONFIG_LOCALVERSION_AUTO=y
38CONFIG_SWAP=y
39CONFIG_SYSVIPC=y
40CONFIG_SYSVIPC_SYSCTL=y
41CONFIG_POSIX_MQUEUE=y
42CONFIG_BSD_PROCESS_ACCT=y
43CONFIG_BSD_PROCESS_ACCT_V3=y
44# CONFIG_TASKSTATS is not set
45# CONFIG_USER_NS is not set
46# CONFIG_PID_NS is not set
47# CONFIG_AUDIT is not set
48CONFIG_IKCONFIG=y
49CONFIG_IKCONFIG_PROC=y
50CONFIG_LOG_BUF_SHIFT=14
51# CONFIG_CGROUPS is not set
52CONFIG_FAIR_GROUP_SCHED=y
53CONFIG_FAIR_USER_SCHED=y
54# CONFIG_FAIR_CGROUP_SCHED is not set
55CONFIG_SYSFS_DEPRECATED=y
56# CONFIG_RELAY is not set
57CONFIG_BLK_DEV_INITRD=y
58CONFIG_INITRAMFS_SOURCE=""
59CONFIG_CC_OPTIMIZE_FOR_SIZE=y
60CONFIG_SYSCTL=y
61CONFIG_EMBEDDED=y
62CONFIG_UID16=y
63CONFIG_SYSCTL_SYSCALL=y
64CONFIG_KALLSYMS=y
65# CONFIG_KALLSYMS_ALL is not set
66CONFIG_KALLSYMS_EXTRA_PASS=y
67CONFIG_HOTPLUG=y
68CONFIG_PRINTK=y
69CONFIG_BUG=y
70CONFIG_ELF_CORE=y
71CONFIG_BASE_FULL=y
72CONFIG_FUTEX=y
73CONFIG_ANON_INODES=y
74CONFIG_EPOLL=y
75CONFIG_SIGNALFD=y
76CONFIG_EVENTFD=y
77CONFIG_SHMEM=y
78CONFIG_VM_EVENT_COUNTERS=y
79CONFIG_SLAB=y
80# CONFIG_SLUB is not set
81# CONFIG_SLOB is not set
82CONFIG_RT_MUTEXES=y
83# CONFIG_TINY_SHMEM is not set
84CONFIG_BASE_SMALL=0
85CONFIG_MODULES=y
86CONFIG_MODULE_UNLOAD=y
87CONFIG_MODULE_FORCE_UNLOAD=y
88CONFIG_MODVERSIONS=y
89CONFIG_MODULE_SRCVERSION_ALL=y
90CONFIG_KMOD=y
91CONFIG_BLOCK=y
92CONFIG_LBD=y
93# CONFIG_BLK_DEV_IO_TRACE is not set
94CONFIG_LSF=y
95# CONFIG_BLK_DEV_BSG is not set
96
97#
98# IO Schedulers
99#
100CONFIG_IOSCHED_NOOP=y
101CONFIG_IOSCHED_AS=y
102CONFIG_IOSCHED_DEADLINE=y
103CONFIG_IOSCHED_CFQ=y
104CONFIG_DEFAULT_AS=y
105# CONFIG_DEFAULT_DEADLINE is not set
106# CONFIG_DEFAULT_CFQ is not set
107# CONFIG_DEFAULT_NOOP is not set
108CONFIG_DEFAULT_IOSCHED="anticipatory"
109
110#
111# System Type
112#
113# CONFIG_ARCH_AAEC2000 is not set
114# CONFIG_ARCH_INTEGRATOR is not set
115# CONFIG_ARCH_REALVIEW is not set
116# CONFIG_ARCH_VERSATILE is not set
117# CONFIG_ARCH_AT91 is not set
118# CONFIG_ARCH_CLPS7500 is not set
119# CONFIG_ARCH_CLPS711X is not set
120# CONFIG_ARCH_CO285 is not set
121# CONFIG_ARCH_EBSA110 is not set
122# CONFIG_ARCH_EP93XX is not set
123# CONFIG_ARCH_FOOTBRIDGE is not set
124# CONFIG_ARCH_NETX is not set
125# CONFIG_ARCH_H720X is not set
126# CONFIG_ARCH_IMX is not set
127# CONFIG_ARCH_IOP13XX is not set
128# CONFIG_ARCH_IOP32X is not set
129# CONFIG_ARCH_IOP33X is not set
130# CONFIG_ARCH_IXP23XX is not set
131# CONFIG_ARCH_IXP2000 is not set
132# CONFIG_ARCH_IXP4XX is not set
133# CONFIG_ARCH_L7200 is not set
134# CONFIG_ARCH_KS8695 is not set
135# CONFIG_ARCH_NS9XXX is not set
136# CONFIG_ARCH_MXC is not set
137# CONFIG_ARCH_PNX4008 is not set
138CONFIG_ARCH_PXA=y
139# CONFIG_ARCH_RPC is not set
140# CONFIG_ARCH_SA1100 is not set
141# CONFIG_ARCH_S3C2410 is not set
142# CONFIG_ARCH_SHARK is not set
143# CONFIG_ARCH_LH7A40X is not set
144# CONFIG_ARCH_DAVINCI is not set
145# CONFIG_ARCH_OMAP is not set
146
147#
148# Intel PXA2xx/PXA3xx Implementations
149#
150# CONFIG_ARCH_LUBBOCK is not set
151# CONFIG_MACH_LOGICPD_PXA270 is not set
152# CONFIG_MACH_MAINSTONE is not set
153# CONFIG_ARCH_PXA_IDP is not set
154# CONFIG_PXA_SHARPSL is not set
155# CONFIG_MACH_TRIZEPS4 is not set
156# CONFIG_MACH_EM_X270 is not set
157CONFIG_MACH_COLIBRI=y
158# CONFIG_MACH_ZYLONITE is not set
159# CONFIG_MACH_ARMCORE is not set
160CONFIG_PXA27x=y
161
162#
163# Boot options
164#
165
166#
167# Power management
168#
169
170#
171# Processor Type
172#
173CONFIG_CPU_32=y
174CONFIG_CPU_XSCALE=y
175CONFIG_CPU_32v5=y
176CONFIG_CPU_ABRT_EV5T=y
177CONFIG_CPU_CACHE_VIVT=y
178CONFIG_CPU_TLB_V4WBI=y
179CONFIG_CPU_CP15=y
180CONFIG_CPU_CP15_MMU=y
181
182#
183# Processor Features
184#
185CONFIG_ARM_THUMB=y
186# CONFIG_CPU_DCACHE_DISABLE is not set
187# CONFIG_OUTER_CACHE is not set
188CONFIG_IWMMXT=y
189CONFIG_XSCALE_PMU=y
190
191#
192# Bus support
193#
194# CONFIG_PCI_SYSCALL is not set
195# CONFIG_ARCH_SUPPORTS_MSI is not set
196# CONFIG_PCCARD is not set
197
198#
199# Kernel Features
200#
201# CONFIG_TICK_ONESHOT is not set
202# CONFIG_NO_HZ is not set
203# CONFIG_HIGH_RES_TIMERS is not set
204CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
205CONFIG_PREEMPT=y
206CONFIG_HZ=100
207CONFIG_AEABI=y
208CONFIG_OABI_COMPAT=y
209# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
210CONFIG_SELECT_MEMORY_MODEL=y
211CONFIG_FLATMEM_MANUAL=y
212# CONFIG_DISCONTIGMEM_MANUAL is not set
213# CONFIG_SPARSEMEM_MANUAL is not set
214CONFIG_FLATMEM=y
215CONFIG_FLAT_NODE_MEM_MAP=y
216# CONFIG_SPARSEMEM_STATIC is not set
217# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
218CONFIG_SPLIT_PTLOCK_CPUS=4096
219# CONFIG_RESOURCES_64BIT is not set
220CONFIG_ZONE_DMA_FLAG=1
221CONFIG_BOUNCE=y
222CONFIG_VIRT_TO_BUS=y
223CONFIG_ALIGNMENT_TRAP=y
224
225#
226# Boot options
227#
228CONFIG_ZBOOT_ROM_TEXT=0
229CONFIG_ZBOOT_ROM_BSS=0
230CONFIG_CMDLINE=""
231# CONFIG_XIP_KERNEL is not set
232# CONFIG_KEXEC is not set
233
234#
235# Floating point emulation
236#
237
238#
239# At least one emulation must be selected
240#
241CONFIG_FPE_NWFPE=y
242# CONFIG_FPE_NWFPE_XP is not set
243# CONFIG_FPE_FASTFPE is not set
244
245#
246# Userspace binary formats
247#
248CONFIG_BINFMT_ELF=y
249# CONFIG_BINFMT_AOUT is not set
250# CONFIG_BINFMT_MISC is not set
251
252#
253# Power management options
254#
255CONFIG_PM=y
256# CONFIG_PM_LEGACY is not set
257# CONFIG_PM_DEBUG is not set
258CONFIG_PM_SLEEP=y
259CONFIG_SUSPEND_UP_POSSIBLE=y
260CONFIG_SUSPEND=y
261# CONFIG_APM_EMULATION is not set
262
263#
264# Networking
265#
266CONFIG_NET=y
267
268#
269# Networking options
270#
271CONFIG_PACKET=y
272CONFIG_PACKET_MMAP=y
273CONFIG_UNIX=y
274CONFIG_XFRM=y
275CONFIG_XFRM_USER=m
276# CONFIG_XFRM_SUB_POLICY is not set
277# CONFIG_XFRM_MIGRATE is not set
278CONFIG_NET_KEY=y
279# CONFIG_NET_KEY_MIGRATE is not set
280CONFIG_INET=y
281# CONFIG_IP_MULTICAST is not set
282# CONFIG_IP_ADVANCED_ROUTER is not set
283CONFIG_IP_FIB_HASH=y
284CONFIG_IP_PNP=y
285CONFIG_IP_PNP_DHCP=y
286CONFIG_IP_PNP_BOOTP=y
287# CONFIG_IP_PNP_RARP is not set
288# CONFIG_NET_IPIP is not set
289# CONFIG_NET_IPGRE is not set
290# CONFIG_ARPD is not set
291# CONFIG_SYN_COOKIES is not set
292# CONFIG_INET_AH is not set
293# CONFIG_INET_ESP is not set
294# CONFIG_INET_IPCOMP is not set
295# CONFIG_INET_XFRM_TUNNEL is not set
296# CONFIG_INET_TUNNEL is not set
297CONFIG_INET_XFRM_MODE_TRANSPORT=y
298CONFIG_INET_XFRM_MODE_TUNNEL=y
299CONFIG_INET_XFRM_MODE_BEET=y
300# CONFIG_INET_LRO is not set
301CONFIG_INET_DIAG=y
302CONFIG_INET_TCP_DIAG=y
303# CONFIG_TCP_CONG_ADVANCED is not set
304CONFIG_TCP_CONG_CUBIC=y
305CONFIG_DEFAULT_TCP_CONG="cubic"
306# CONFIG_TCP_MD5SIG is not set
307# CONFIG_IP_VS is not set
308# CONFIG_IPV6 is not set
309# CONFIG_INET6_XFRM_TUNNEL is not set
310# CONFIG_INET6_TUNNEL is not set
311# CONFIG_NETLABEL is not set
312# CONFIG_NETWORK_SECMARK is not set
313CONFIG_NETFILTER=y
314# CONFIG_NETFILTER_DEBUG is not set
315
316#
317# Core Netfilter Configuration
318#
319# CONFIG_NETFILTER_NETLINK is not set
320# CONFIG_NF_CONNTRACK_ENABLED is not set
321# CONFIG_NF_CONNTRACK is not set
322# CONFIG_NETFILTER_XTABLES is not set
323
324#
325# IP: Netfilter Configuration
326#
327CONFIG_IP_NF_QUEUE=m
328# CONFIG_IP_NF_IPTABLES is not set
329# CONFIG_IP_NF_ARPTABLES is not set
330# CONFIG_IP_DCCP is not set
331# CONFIG_IP_SCTP is not set
332# CONFIG_TIPC is not set
333# CONFIG_ATM is not set
334# CONFIG_BRIDGE is not set
335CONFIG_VLAN_8021Q=m
336# CONFIG_DECNET is not set
337# CONFIG_LLC2 is not set
338# CONFIG_IPX is not set
339# CONFIG_ATALK is not set
340# CONFIG_X25 is not set
341# CONFIG_LAPB is not set
342# CONFIG_ECONET is not set
343# CONFIG_WAN_ROUTER is not set
344# CONFIG_NET_SCHED is not set
345
346#
347# Network testing
348#
349# CONFIG_NET_PKTGEN is not set
350# CONFIG_HAMRADIO is not set
351CONFIG_IRDA=m
352
353#
354# IrDA protocols
355#
356CONFIG_IRLAN=m
357CONFIG_IRCOMM=m
358CONFIG_IRDA_ULTRA=y
359
360#
361# IrDA options
362#
363CONFIG_IRDA_CACHE_LAST_LSAP=y
364CONFIG_IRDA_FAST_RR=y
365# CONFIG_IRDA_DEBUG is not set
366
367#
368# Infrared-port device drivers
369#
370
371#
372# SIR device drivers
373#
374CONFIG_IRTTY_SIR=m
375
376#
377# Dongle support
378#
379# CONFIG_DONGLE is not set
380# CONFIG_KINGSUN_DONGLE is not set
381# CONFIG_KSDAZZLE_DONGLE is not set
382# CONFIG_KS959_DONGLE is not set
383
384#
385# Old SIR device drivers
386#
387# CONFIG_IRPORT_SIR is not set
388
389#
390# Old Serial dongle support
391#
392
393#
394# FIR device drivers
395#
396# CONFIG_USB_IRDA is not set
397# CONFIG_SIGMATEL_FIR is not set
398# CONFIG_PXA_FICP is not set
399# CONFIG_MCS_FIR is not set
400CONFIG_BT=m
401CONFIG_BT_L2CAP=m
402CONFIG_BT_SCO=m
403CONFIG_BT_RFCOMM=m
404CONFIG_BT_RFCOMM_TTY=y
405CONFIG_BT_BNEP=m
406CONFIG_BT_BNEP_MC_FILTER=y
407CONFIG_BT_BNEP_PROTO_FILTER=y
408CONFIG_BT_HIDP=m
409
410#
411# Bluetooth device drivers
412#
413# CONFIG_BT_HCIUSB is not set
414# CONFIG_BT_HCIBTUSB is not set
415# CONFIG_BT_HCIBTSDIO is not set
416# CONFIG_BT_HCIUART is not set
417# CONFIG_BT_HCIBCM203X is not set
418# CONFIG_BT_HCIBPA10X is not set
419# CONFIG_BT_HCIBFUSB is not set
420# CONFIG_BT_HCIVHCI is not set
421# CONFIG_AF_RXRPC is not set
422
423#
424# Wireless
425#
426CONFIG_CFG80211=y
427CONFIG_NL80211=y
428CONFIG_WIRELESS_EXT=y
429# CONFIG_MAC80211 is not set
430CONFIG_IEEE80211=y
431# CONFIG_IEEE80211_DEBUG is not set
432CONFIG_IEEE80211_CRYPT_WEP=y
433CONFIG_IEEE80211_CRYPT_CCMP=m
434CONFIG_IEEE80211_CRYPT_TKIP=m
435CONFIG_IEEE80211_SOFTMAC=m
436# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
437# CONFIG_RFKILL is not set
438# CONFIG_NET_9P is not set
439
440#
441# Device Drivers
442#
443
444#
445# Generic Driver Options
446#
447CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
448CONFIG_STANDALONE=y
449CONFIG_PREVENT_FIRMWARE_BUILD=y
450CONFIG_FW_LOADER=y
451# CONFIG_DEBUG_DRIVER is not set
452# CONFIG_DEBUG_DEVRES is not set
453# CONFIG_SYS_HYPERVISOR is not set
454CONFIG_CONNECTOR=y
455CONFIG_PROC_EVENTS=y
456CONFIG_MTD=y
457# CONFIG_MTD_DEBUG is not set
458CONFIG_MTD_CONCAT=y
459CONFIG_MTD_PARTITIONS=y
460# CONFIG_MTD_REDBOOT_PARTS is not set
461# CONFIG_MTD_CMDLINE_PARTS is not set
462# CONFIG_MTD_AFS_PARTS is not set
463
464#
465# User Modules And Translation Layers
466#
467CONFIG_MTD_CHAR=y
468CONFIG_MTD_BLKDEVS=y
469CONFIG_MTD_BLOCK=y
470# CONFIG_FTL is not set
471# CONFIG_NFTL is not set
472# CONFIG_INFTL is not set
473# CONFIG_RFD_FTL is not set
474# CONFIG_SSFDC is not set
475# CONFIG_MTD_OOPS is not set
476
477#
478# RAM/ROM/Flash chip drivers
479#
480CONFIG_MTD_CFI=y
481CONFIG_MTD_JEDECPROBE=y
482CONFIG_MTD_GEN_PROBE=y
483CONFIG_MTD_CFI_ADV_OPTIONS=y
484# CONFIG_MTD_CFI_NOSWAP is not set
485# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
486CONFIG_MTD_CFI_LE_BYTE_SWAP=y
487CONFIG_MTD_CFI_GEOMETRY=y
488CONFIG_MTD_MAP_BANK_WIDTH_1=y
489CONFIG_MTD_MAP_BANK_WIDTH_2=y
490CONFIG_MTD_MAP_BANK_WIDTH_4=y
491# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
492# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
493# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
494CONFIG_MTD_CFI_I1=y
495CONFIG_MTD_CFI_I2=y
496# CONFIG_MTD_CFI_I4 is not set
497# CONFIG_MTD_CFI_I8 is not set
498# CONFIG_MTD_OTP is not set
499CONFIG_MTD_CFI_INTELEXT=y
500CONFIG_MTD_CFI_AMDSTD=y
501# CONFIG_MTD_CFI_STAA is not set
502CONFIG_MTD_CFI_UTIL=y
503# CONFIG_MTD_RAM is not set
504# CONFIG_MTD_ROM is not set
505# CONFIG_MTD_ABSENT is not set
506# CONFIG_MTD_XIP is not set
507
508#
509# Mapping drivers for chip access
510#
511CONFIG_MTD_COMPLEX_MAPPINGS=y
512CONFIG_MTD_PHYSMAP=y
513CONFIG_MTD_PHYSMAP_START=0x0
514CONFIG_MTD_PHYSMAP_LEN=0x0
515CONFIG_MTD_PHYSMAP_BANKWIDTH=2
516CONFIG_MTD_PXA2XX=y
517# CONFIG_MTD_ARM_INTEGRATOR is not set
518# CONFIG_MTD_IMPA7 is not set
519# CONFIG_MTD_SHARP_SL is not set
520# CONFIG_MTD_PLATRAM is not set
521
522#
523# Self-contained MTD device drivers
524#
525# CONFIG_MTD_SLRAM is not set
526# CONFIG_MTD_PHRAM is not set
527# CONFIG_MTD_MTDRAM is not set
528CONFIG_MTD_BLOCK2MTD=y
529
530#
531# Disk-On-Chip Device Drivers
532#
533# CONFIG_MTD_DOC2000 is not set
534# CONFIG_MTD_DOC2001 is not set
535# CONFIG_MTD_DOC2001PLUS is not set
536CONFIG_MTD_NAND=y
537# CONFIG_MTD_NAND_VERIFY_WRITE is not set
538# CONFIG_MTD_NAND_ECC_SMC is not set
539# CONFIG_MTD_NAND_MUSEUM_IDS is not set
540# CONFIG_MTD_NAND_H1900 is not set
541CONFIG_MTD_NAND_IDS=y
542CONFIG_MTD_NAND_DISKONCHIP=y
543CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
544CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
545CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
546CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
547# CONFIG_MTD_NAND_SHARPSL is not set
548# CONFIG_MTD_NAND_NANDSIM is not set
549# CONFIG_MTD_NAND_PLATFORM is not set
550# CONFIG_MTD_ALAUDA is not set
551CONFIG_MTD_ONENAND=y
552# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
553# CONFIG_MTD_ONENAND_GENERIC is not set
554# CONFIG_MTD_ONENAND_OTP is not set
555# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
556# CONFIG_MTD_ONENAND_SIM is not set
557
558#
559# UBI - Unsorted block images
560#
561# CONFIG_MTD_UBI is not set
562# CONFIG_PARPORT is not set
563CONFIG_BLK_DEV=y
564# CONFIG_BLK_DEV_COW_COMMON is not set
565CONFIG_BLK_DEV_LOOP=y
566CONFIG_BLK_DEV_CRYPTOLOOP=m
567CONFIG_BLK_DEV_NBD=y
568# CONFIG_BLK_DEV_UB is not set
569CONFIG_BLK_DEV_RAM=y
570CONFIG_BLK_DEV_RAM_COUNT=8
571CONFIG_BLK_DEV_RAM_SIZE=4096
572CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
573# CONFIG_CDROM_PKTCDVD is not set
574# CONFIG_ATA_OVER_ETH is not set
575CONFIG_MISC_DEVICES=y
576# CONFIG_EEPROM_93CX6 is not set
577CONFIG_IDE=y
578CONFIG_IDE_MAX_HWIFS=4
579CONFIG_BLK_DEV_IDE=y
580
581#
582# Please see Documentation/ide.txt for help/info on IDE drives
583#
584# CONFIG_BLK_DEV_IDE_SATA is not set
585CONFIG_BLK_DEV_IDEDISK=y
586CONFIG_IDEDISK_MULTI_MODE=y
587# CONFIG_BLK_DEV_IDECD is not set
588# CONFIG_BLK_DEV_IDETAPE is not set
589# CONFIG_BLK_DEV_IDEFLOPPY is not set
590# CONFIG_IDE_TASK_IOCTL is not set
591CONFIG_IDE_PROC_FS=y
592
593#
594# IDE chipset support/bugfixes
595#
596CONFIG_IDE_GENERIC=y
597# CONFIG_BLK_DEV_PLATFORM is not set
598# CONFIG_IDE_ARM is not set
599# CONFIG_BLK_DEV_IDEDMA is not set
600CONFIG_IDE_ARCH_OBSOLETE_INIT=y
601# CONFIG_BLK_DEV_HD is not set
602
603#
604# SCSI device support
605#
606# CONFIG_RAID_ATTRS is not set
607# CONFIG_SCSI is not set
608# CONFIG_SCSI_DMA is not set
609# CONFIG_SCSI_NETLINK is not set
610# CONFIG_ATA is not set
611# CONFIG_MD is not set
612CONFIG_NETDEVICES=y
613# CONFIG_NETDEVICES_MULTIQUEUE is not set
614# CONFIG_DUMMY is not set
615# CONFIG_BONDING is not set
616# CONFIG_MACVLAN is not set
617# CONFIG_EQUALIZER is not set
618# CONFIG_TUN is not set
619# CONFIG_VETH is not set
620CONFIG_PHYLIB=y
621
622#
623# MII PHY device drivers
624#
625# CONFIG_MARVELL_PHY is not set
626# CONFIG_DAVICOM_PHY is not set
627# CONFIG_QSEMI_PHY is not set
628# CONFIG_LXT_PHY is not set
629# CONFIG_CICADA_PHY is not set
630# CONFIG_VITESSE_PHY is not set
631# CONFIG_SMSC_PHY is not set
632# CONFIG_BROADCOM_PHY is not set
633# CONFIG_ICPLUS_PHY is not set
634# CONFIG_FIXED_PHY is not set
635# CONFIG_MDIO_BITBANG is not set
636CONFIG_NET_ETHERNET=y
637CONFIG_MII=y
638# CONFIG_AX88796 is not set
639# CONFIG_SMC91X is not set
640CONFIG_DM9000=y
641# CONFIG_SMC911X is not set
642# CONFIG_IBM_NEW_EMAC_ZMII is not set
643# CONFIG_IBM_NEW_EMAC_RGMII is not set
644# CONFIG_IBM_NEW_EMAC_TAH is not set
645# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
646# CONFIG_B44 is not set
647# CONFIG_NETDEV_1000 is not set
648# CONFIG_NETDEV_10000 is not set
649
650#
651# Wireless LAN
652#
653# CONFIG_WLAN_PRE80211 is not set
654CONFIG_WLAN_80211=y
655# CONFIG_LIBERTAS is not set
656# CONFIG_USB_ZD1201 is not set
657CONFIG_HOSTAP=y
658CONFIG_HOSTAP_FIRMWARE=y
659CONFIG_HOSTAP_FIRMWARE_NVRAM=y
660# CONFIG_ZD1211RW is not set
661
662#
663# USB Network Adapters
664#
665# CONFIG_USB_CATC is not set
666# CONFIG_USB_KAWETH is not set
667# CONFIG_USB_PEGASUS is not set
668# CONFIG_USB_RTL8150 is not set
669# CONFIG_USB_USBNET is not set
670# CONFIG_WAN is not set
671# CONFIG_PPP is not set
672# CONFIG_SLIP is not set
673# CONFIG_SHAPER is not set
674# CONFIG_NETCONSOLE is not set
675# CONFIG_NETPOLL is not set
676# CONFIG_NET_POLL_CONTROLLER is not set
677# CONFIG_ISDN is not set
678
679#
680# Input device support
681#
682CONFIG_INPUT=y
683# CONFIG_INPUT_FF_MEMLESS is not set
684# CONFIG_INPUT_POLLDEV is not set
685
686#
687# Userland interfaces
688#
689CONFIG_INPUT_MOUSEDEV=y
690CONFIG_INPUT_MOUSEDEV_PSAUX=y
691CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
692CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
693# CONFIG_INPUT_JOYDEV is not set
694CONFIG_INPUT_EVDEV=y
695# CONFIG_INPUT_EVBUG is not set
696
697#
698# Input Device Drivers
699#
700CONFIG_INPUT_KEYBOARD=y
701CONFIG_KEYBOARD_ATKBD=m
702# CONFIG_KEYBOARD_SUNKBD is not set
703# CONFIG_KEYBOARD_LKKBD is not set
704# CONFIG_KEYBOARD_XTKBD is not set
705# CONFIG_KEYBOARD_NEWTON is not set
706# CONFIG_KEYBOARD_STOWAWAY is not set
707# CONFIG_KEYBOARD_PXA27x is not set
708# CONFIG_KEYBOARD_GPIO is not set
709CONFIG_INPUT_MOUSE=y
710# CONFIG_MOUSE_PS2 is not set
711CONFIG_MOUSE_SERIAL=m
712# CONFIG_MOUSE_APPLETOUCH is not set
713# CONFIG_MOUSE_VSXXXAA is not set
714# CONFIG_MOUSE_GPIO is not set
715# CONFIG_INPUT_JOYSTICK is not set
716# CONFIG_INPUT_TABLET is not set
717CONFIG_INPUT_TOUCHSCREEN=y
718# CONFIG_TOUCHSCREEN_FUJITSU is not set
719# CONFIG_TOUCHSCREEN_GUNZE is not set
720# CONFIG_TOUCHSCREEN_ELO is not set
721# CONFIG_TOUCHSCREEN_MTOUCH is not set
722# CONFIG_TOUCHSCREEN_MK712 is not set
723# CONFIG_TOUCHSCREEN_PENMOUNT is not set
724# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
725# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
726CONFIG_TOUCHSCREEN_UCB1400=y
727# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
728CONFIG_INPUT_MISC=y
729# CONFIG_INPUT_ATI_REMOTE is not set
730# CONFIG_INPUT_ATI_REMOTE2 is not set
731# CONFIG_INPUT_KEYSPAN_REMOTE is not set
732# CONFIG_INPUT_POWERMATE is not set
733# CONFIG_INPUT_YEALINK is not set
734CONFIG_INPUT_UINPUT=m
735
736#
737# Hardware I/O ports
738#
739CONFIG_SERIO=y
740CONFIG_SERIO_SERPORT=y
741CONFIG_SERIO_LIBPS2=y
742# CONFIG_SERIO_RAW is not set
743# CONFIG_GAMEPORT is not set
744
745#
746# Character devices
747#
748CONFIG_VT=y
749CONFIG_VT_CONSOLE=y
750CONFIG_HW_CONSOLE=y
751# CONFIG_VT_HW_CONSOLE_BINDING is not set
752# CONFIG_SERIAL_NONSTANDARD is not set
753
754#
755# Serial drivers
756#
757# CONFIG_SERIAL_8250 is not set
758
759#
760# Non-8250 serial port support
761#
762CONFIG_SERIAL_PXA=y
763CONFIG_SERIAL_PXA_CONSOLE=y
764CONFIG_SERIAL_CORE=y
765CONFIG_SERIAL_CORE_CONSOLE=y
766CONFIG_UNIX98_PTYS=y
767CONFIG_LEGACY_PTYS=y
768CONFIG_LEGACY_PTY_COUNT=256
769# CONFIG_IPMI_HANDLER is not set
770CONFIG_HW_RANDOM=y
771# CONFIG_NVRAM is not set
772# CONFIG_R3964 is not set
773# CONFIG_RAW_DRIVER is not set
774# CONFIG_TCG_TPM is not set
775CONFIG_I2C=y
776CONFIG_I2C_BOARDINFO=y
777CONFIG_I2C_CHARDEV=y
778
779#
780# I2C Algorithms
781#
782# CONFIG_I2C_ALGOBIT is not set
783# CONFIG_I2C_ALGOPCF is not set
784# CONFIG_I2C_ALGOPCA is not set
785
786#
787# I2C Hardware Bus support
788#
789# CONFIG_I2C_GPIO is not set
790# CONFIG_I2C_PXA is not set
791# CONFIG_I2C_OCORES is not set
792# CONFIG_I2C_PARPORT_LIGHT is not set
793# CONFIG_I2C_SIMTEC is not set
794# CONFIG_I2C_TAOS_EVM is not set
795# CONFIG_I2C_STUB is not set
796# CONFIG_I2C_TINY_USB is not set
797
798#
799# Miscellaneous I2C Chip support
800#
801# CONFIG_SENSORS_DS1337 is not set
802# CONFIG_SENSORS_DS1374 is not set
803# CONFIG_DS1682 is not set
804# CONFIG_SENSORS_EEPROM is not set
805# CONFIG_SENSORS_PCF8574 is not set
806# CONFIG_SENSORS_PCA9539 is not set
807# CONFIG_SENSORS_PCF8591 is not set
808# CONFIG_SENSORS_MAX6875 is not set
809# CONFIG_SENSORS_TSL2550 is not set
810# CONFIG_I2C_DEBUG_CORE is not set
811# CONFIG_I2C_DEBUG_ALGO is not set
812# CONFIG_I2C_DEBUG_BUS is not set
813# CONFIG_I2C_DEBUG_CHIP is not set
814
815#
816# SPI support
817#
818# CONFIG_SPI is not set
819# CONFIG_SPI_MASTER is not set
820# CONFIG_W1 is not set
821# CONFIG_POWER_SUPPLY is not set
822CONFIG_HWMON=y
823# CONFIG_HWMON_VID is not set
824# CONFIG_SENSORS_AD7418 is not set
825# CONFIG_SENSORS_ADM1021 is not set
826# CONFIG_SENSORS_ADM1025 is not set
827# CONFIG_SENSORS_ADM1026 is not set
828# CONFIG_SENSORS_ADM1029 is not set
829# CONFIG_SENSORS_ADM1031 is not set
830# CONFIG_SENSORS_ADM9240 is not set
831# CONFIG_SENSORS_ADT7470 is not set
832# CONFIG_SENSORS_ATXP1 is not set
833# CONFIG_SENSORS_DS1621 is not set
834# CONFIG_SENSORS_F71805F is not set
835# CONFIG_SENSORS_F71882FG is not set
836# CONFIG_SENSORS_F75375S is not set
837# CONFIG_SENSORS_GL518SM is not set
838# CONFIG_SENSORS_GL520SM is not set
839# CONFIG_SENSORS_IT87 is not set
840# CONFIG_SENSORS_LM63 is not set
841# CONFIG_SENSORS_LM75 is not set
842# CONFIG_SENSORS_LM77 is not set
843# CONFIG_SENSORS_LM78 is not set
844# CONFIG_SENSORS_LM80 is not set
845# CONFIG_SENSORS_LM83 is not set
846# CONFIG_SENSORS_LM85 is not set
847# CONFIG_SENSORS_LM87 is not set
848# CONFIG_SENSORS_LM90 is not set
849# CONFIG_SENSORS_LM92 is not set
850# CONFIG_SENSORS_LM93 is not set
851# CONFIG_SENSORS_MAX1619 is not set
852# CONFIG_SENSORS_MAX6650 is not set
853# CONFIG_SENSORS_PC87360 is not set
854# CONFIG_SENSORS_PC87427 is not set
855# CONFIG_SENSORS_DME1737 is not set
856# CONFIG_SENSORS_SMSC47M1 is not set
857# CONFIG_SENSORS_SMSC47M192 is not set
858# CONFIG_SENSORS_SMSC47B397 is not set
859# CONFIG_SENSORS_THMC50 is not set
860# CONFIG_SENSORS_VT1211 is not set
861# CONFIG_SENSORS_W83781D is not set
862# CONFIG_SENSORS_W83791D is not set
863# CONFIG_SENSORS_W83792D is not set
864# CONFIG_SENSORS_W83793 is not set
865# CONFIG_SENSORS_W83L785TS is not set
866# CONFIG_SENSORS_W83627HF is not set
867# CONFIG_SENSORS_W83627EHF is not set
868# CONFIG_HWMON_DEBUG_CHIP is not set
869CONFIG_WATCHDOG=y
870# CONFIG_WATCHDOG_NOWAYOUT is not set
871
872#
873# Watchdog Device Drivers
874#
875# CONFIG_SOFT_WATCHDOG is not set
876# CONFIG_SA1100_WATCHDOG is not set
877
878#
879# USB-based Watchdog Cards
880#
881# CONFIG_USBPCWATCHDOG is not set
882
883#
884# Sonics Silicon Backplane
885#
886CONFIG_SSB_POSSIBLE=y
887# CONFIG_SSB is not set
888
889#
890# Multifunction device drivers
891#
892# CONFIG_MFD_SM501 is not set
893
894#
895# Multimedia devices
896#
897# CONFIG_VIDEO_DEV is not set
898# CONFIG_DVB_CORE is not set
899CONFIG_DAB=y
900# CONFIG_USB_DABUSB is not set
901
902#
903# Graphics support
904#
905# CONFIG_VGASTATE is not set
906# CONFIG_VIDEO_OUTPUT_CONTROL is not set
907CONFIG_FB=y
908CONFIG_FIRMWARE_EDID=y
909# CONFIG_FB_DDC is not set
910CONFIG_FB_CFB_FILLRECT=y
911CONFIG_FB_CFB_COPYAREA=y
912CONFIG_FB_CFB_IMAGEBLIT=y
913# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
914# CONFIG_FB_SYS_FILLRECT is not set
915# CONFIG_FB_SYS_COPYAREA is not set
916# CONFIG_FB_SYS_IMAGEBLIT is not set
917# CONFIG_FB_SYS_FOPS is not set
918CONFIG_FB_DEFERRED_IO=y
919# CONFIG_FB_SVGALIB is not set
920# CONFIG_FB_MACMODES is not set
921# CONFIG_FB_BACKLIGHT is not set
922# CONFIG_FB_MODE_HELPERS is not set
923# CONFIG_FB_TILEBLITTING is not set
924
925#
926# Frame buffer hardware drivers
927#
928# CONFIG_FB_UVESA is not set
929# CONFIG_FB_S1D13XXX is not set
930CONFIG_FB_PXA=y
931# CONFIG_FB_PXA_PARAMETERS is not set
932# CONFIG_FB_MBX is not set
933# CONFIG_FB_VIRTUAL is not set
934CONFIG_BACKLIGHT_LCD_SUPPORT=y
935CONFIG_LCD_CLASS_DEVICE=y
936CONFIG_BACKLIGHT_CLASS_DEVICE=y
937# CONFIG_BACKLIGHT_CORGI is not set
938
939#
940# Display device support
941#
942# CONFIG_DISPLAY_SUPPORT is not set
943
944#
945# Console display driver support
946#
947# CONFIG_VGA_CONSOLE is not set
948CONFIG_DUMMY_CONSOLE=y
949CONFIG_FRAMEBUFFER_CONSOLE=y
950# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
951CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
952CONFIG_FONTS=y
953CONFIG_FONT_8x8=y
954CONFIG_FONT_8x16=y
955# CONFIG_FONT_6x11 is not set
956# CONFIG_FONT_7x14 is not set
957# CONFIG_FONT_PEARL_8x8 is not set
958# CONFIG_FONT_ACORN_8x8 is not set
959# CONFIG_FONT_MINI_4x6 is not set
960# CONFIG_FONT_SUN8x16 is not set
961# CONFIG_FONT_SUN12x22 is not set
962# CONFIG_FONT_10x18 is not set
963CONFIG_LOGO=y
964CONFIG_LOGO_LINUX_MONO=y
965CONFIG_LOGO_LINUX_VGA16=y
966CONFIG_LOGO_LINUX_CLUT224=y
967
968#
969# Sound
970#
971# CONFIG_SOUND is not set
972CONFIG_AC97_BUS=y
973CONFIG_HID_SUPPORT=y
974CONFIG_HID=y
975# CONFIG_HID_DEBUG is not set
976# CONFIG_HIDRAW is not set
977
978#
979# USB Input Devices
980#
981# CONFIG_USB_HID is not set
982
983#
984# USB HID Boot Protocol drivers
985#
986# CONFIG_USB_KBD is not set
987# CONFIG_USB_MOUSE is not set
988CONFIG_USB_SUPPORT=y
989CONFIG_USB_ARCH_HAS_HCD=y
990CONFIG_USB_ARCH_HAS_OHCI=y
991# CONFIG_USB_ARCH_HAS_EHCI is not set
992CONFIG_USB=y
993# CONFIG_USB_DEBUG is not set
994
995#
996# Miscellaneous USB options
997#
998CONFIG_USB_DEVICEFS=y
999# CONFIG_USB_DEVICE_CLASS is not set
1000# CONFIG_USB_DYNAMIC_MINORS is not set
1001# CONFIG_USB_SUSPEND is not set
1002# CONFIG_USB_PERSIST is not set
1003# CONFIG_USB_OTG is not set
1004
1005#
1006# USB Host Controller Drivers
1007#
1008# CONFIG_USB_ISP116X_HCD is not set
1009# CONFIG_USB_OHCI_HCD is not set
1010# CONFIG_USB_SL811_HCD is not set
1011# CONFIG_USB_R8A66597_HCD is not set
1012
1013#
1014# USB Device Class drivers
1015#
1016# CONFIG_USB_ACM is not set
1017# CONFIG_USB_PRINTER is not set
1018
1019#
1020# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1021#
1022
1023#
1024# may also be needed; see USB_STORAGE Help for more information
1025#
1026# CONFIG_USB_LIBUSUAL is not set
1027
1028#
1029# USB Imaging devices
1030#
1031# CONFIG_USB_MDC800 is not set
1032# CONFIG_USB_MON is not set
1033
1034#
1035# USB port drivers
1036#
1037
1038#
1039# USB Serial Converter support
1040#
1041CONFIG_USB_SERIAL=m
1042# CONFIG_USB_SERIAL_GENERIC is not set
1043# CONFIG_USB_SERIAL_AIRCABLE is not set
1044# CONFIG_USB_SERIAL_AIRPRIME is not set
1045# CONFIG_USB_SERIAL_ARK3116 is not set
1046# CONFIG_USB_SERIAL_BELKIN is not set
1047# CONFIG_USB_SERIAL_CH341 is not set
1048# CONFIG_USB_SERIAL_WHITEHEAT is not set
1049# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1050# CONFIG_USB_SERIAL_CP2101 is not set
1051# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1052# CONFIG_USB_SERIAL_EMPEG is not set
1053# CONFIG_USB_SERIAL_FTDI_SIO is not set
1054# CONFIG_USB_SERIAL_FUNSOFT is not set
1055# CONFIG_USB_SERIAL_VISOR is not set
1056# CONFIG_USB_SERIAL_IPAQ is not set
1057# CONFIG_USB_SERIAL_IR is not set
1058# CONFIG_USB_SERIAL_EDGEPORT is not set
1059# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1060# CONFIG_USB_SERIAL_GARMIN is not set
1061# CONFIG_USB_SERIAL_IPW is not set
1062# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1063# CONFIG_USB_SERIAL_KEYSPAN is not set
1064# CONFIG_USB_SERIAL_KLSI is not set
1065# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1066# CONFIG_USB_SERIAL_MCT_U232 is not set
1067# CONFIG_USB_SERIAL_MOS7720 is not set
1068# CONFIG_USB_SERIAL_MOS7840 is not set
1069# CONFIG_USB_SERIAL_NAVMAN is not set
1070# CONFIG_USB_SERIAL_PL2303 is not set
1071# CONFIG_USB_SERIAL_OTI6858 is not set
1072# CONFIG_USB_SERIAL_HP4X is not set
1073# CONFIG_USB_SERIAL_SAFE is not set
1074# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1075# CONFIG_USB_SERIAL_TI is not set
1076# CONFIG_USB_SERIAL_CYBERJACK is not set
1077# CONFIG_USB_SERIAL_XIRCOM is not set
1078# CONFIG_USB_SERIAL_OPTION is not set
1079# CONFIG_USB_SERIAL_OMNINET is not set
1080# CONFIG_USB_SERIAL_DEBUG is not set
1081
1082#
1083# USB Miscellaneous drivers
1084#
1085# CONFIG_USB_EMI62 is not set
1086# CONFIG_USB_EMI26 is not set
1087# CONFIG_USB_ADUTUX is not set
1088# CONFIG_USB_AUERSWALD is not set
1089# CONFIG_USB_RIO500 is not set
1090# CONFIG_USB_LEGOTOWER is not set
1091# CONFIG_USB_LCD is not set
1092# CONFIG_USB_BERRY_CHARGE is not set
1093# CONFIG_USB_LED is not set
1094# CONFIG_USB_CYPRESS_CY7C63 is not set
1095# CONFIG_USB_CYTHERM is not set
1096# CONFIG_USB_PHIDGET is not set
1097# CONFIG_USB_IDMOUSE is not set
1098# CONFIG_USB_FTDI_ELAN is not set
1099# CONFIG_USB_APPLEDISPLAY is not set
1100# CONFIG_USB_LD is not set
1101# CONFIG_USB_TRANCEVIBRATOR is not set
1102# CONFIG_USB_IOWARRIOR is not set
1103# CONFIG_USB_TEST is not set
1104
1105#
1106# USB DSL modem support
1107#
1108
1109#
1110# USB Gadget Support
1111#
1112CONFIG_USB_GADGET=m
1113# CONFIG_USB_GADGET_DEBUG is not set
1114# CONFIG_USB_GADGET_DEBUG_FILES is not set
1115# CONFIG_USB_GADGET_DEBUG_FS is not set
1116CONFIG_USB_GADGET_SELECTED=y
1117# CONFIG_USB_GADGET_AMD5536UDC is not set
1118# CONFIG_USB_GADGET_ATMEL_USBA is not set
1119# CONFIG_USB_GADGET_FSL_USB2 is not set
1120# CONFIG_USB_GADGET_NET2280 is not set
1121# CONFIG_USB_GADGET_PXA2XX is not set
1122# CONFIG_USB_GADGET_M66592 is not set
1123# CONFIG_USB_GADGET_GOKU is not set
1124# CONFIG_USB_GADGET_LH7A40X is not set
1125# CONFIG_USB_GADGET_OMAP is not set
1126# CONFIG_USB_GADGET_S3C2410 is not set
1127# CONFIG_USB_GADGET_AT91 is not set
1128CONFIG_USB_GADGET_DUMMY_HCD=y
1129CONFIG_USB_DUMMY_HCD=m
1130CONFIG_USB_GADGET_DUALSPEED=y
1131# CONFIG_USB_ZERO is not set
1132# CONFIG_USB_ETH is not set
1133# CONFIG_USB_GADGETFS is not set
1134# CONFIG_USB_FILE_STORAGE is not set
1135# CONFIG_USB_G_SERIAL is not set
1136# CONFIG_USB_MIDI_GADGET is not set
1137CONFIG_MMC=y
1138# CONFIG_MMC_DEBUG is not set
1139# CONFIG_MMC_UNSAFE_RESUME is not set
1140
1141#
1142# MMC/SD Card Drivers
1143#
1144CONFIG_MMC_BLOCK=y
1145CONFIG_MMC_BLOCK_BOUNCE=y
1146# CONFIG_SDIO_UART is not set
1147
1148#
1149# MMC/SD Host Controller Drivers
1150#
1151# CONFIG_MMC_PXA is not set
1152CONFIG_NEW_LEDS=y
1153# CONFIG_LEDS_CLASS is not set
1154
1155#
1156# LED drivers
1157#
1158
1159#
1160# LED Triggers
1161#
1162CONFIG_LEDS_TRIGGERS=y
1163CONFIG_LEDS_TRIGGER_TIMER=y
1164# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
1165CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1166CONFIG_RTC_LIB=y
1167CONFIG_RTC_CLASS=y
1168# CONFIG_RTC_HCTOSYS is not set
1169# CONFIG_RTC_DEBUG is not set
1170
1171#
1172# RTC interfaces
1173#
1174CONFIG_RTC_INTF_SYSFS=y
1175CONFIG_RTC_INTF_PROC=y
1176CONFIG_RTC_INTF_DEV=y
1177# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1178# CONFIG_RTC_DRV_TEST is not set
1179
1180#
1181# I2C RTC drivers
1182#
1183# CONFIG_RTC_DRV_DS1307 is not set
1184# CONFIG_RTC_DRV_DS1374 is not set
1185# CONFIG_RTC_DRV_DS1672 is not set
1186# CONFIG_RTC_DRV_MAX6900 is not set
1187# CONFIG_RTC_DRV_RS5C372 is not set
1188# CONFIG_RTC_DRV_ISL1208 is not set
1189# CONFIG_RTC_DRV_X1205 is not set
1190# CONFIG_RTC_DRV_PCF8563 is not set
1191CONFIG_RTC_DRV_PCF8583=m
1192# CONFIG_RTC_DRV_M41T80 is not set
1193
1194#
1195# SPI RTC drivers
1196#
1197
1198#
1199# Platform RTC drivers
1200#
1201# CONFIG_RTC_DRV_CMOS is not set
1202# CONFIG_RTC_DRV_DS1553 is not set
1203# CONFIG_RTC_DRV_STK17TA8 is not set
1204# CONFIG_RTC_DRV_DS1742 is not set
1205# CONFIG_RTC_DRV_M48T86 is not set
1206# CONFIG_RTC_DRV_M48T59 is not set
1207# CONFIG_RTC_DRV_V3020 is not set
1208
1209#
1210# on-CPU RTC drivers
1211#
1212# CONFIG_RTC_DRV_SA1100 is not set
1213
1214#
1215# File systems
1216#
1217# CONFIG_EXT2_FS is not set
1218# CONFIG_EXT3_FS is not set
1219# CONFIG_EXT4DEV_FS is not set
1220# CONFIG_REISERFS_FS is not set
1221# CONFIG_JFS_FS is not set
1222CONFIG_FS_POSIX_ACL=y
1223# CONFIG_XFS_FS is not set
1224# CONFIG_GFS2_FS is not set
1225# CONFIG_OCFS2_FS is not set
1226# CONFIG_MINIX_FS is not set
1227# CONFIG_ROMFS_FS is not set
1228CONFIG_INOTIFY=y
1229CONFIG_INOTIFY_USER=y
1230# CONFIG_QUOTA is not set
1231CONFIG_DNOTIFY=y
1232# CONFIG_AUTOFS_FS is not set
1233CONFIG_AUTOFS4_FS=y
1234# CONFIG_FUSE_FS is not set
1235
1236#
1237# CD-ROM/DVD Filesystems
1238#
1239# CONFIG_ISO9660_FS is not set
1240# CONFIG_UDF_FS is not set
1241
1242#
1243# DOS/FAT/NT Filesystems
1244#
1245CONFIG_FAT_FS=m
1246CONFIG_MSDOS_FS=m
1247CONFIG_VFAT_FS=m
1248CONFIG_FAT_DEFAULT_CODEPAGE=437
1249CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
1250# CONFIG_NTFS_FS is not set
1251
1252#
1253# Pseudo filesystems
1254#
1255CONFIG_PROC_FS=y
1256CONFIG_PROC_SYSCTL=y
1257CONFIG_SYSFS=y
1258CONFIG_TMPFS=y
1259# CONFIG_TMPFS_POSIX_ACL is not set
1260# CONFIG_HUGETLB_PAGE is not set
1261CONFIG_CONFIGFS_FS=y
1262
1263#
1264# Miscellaneous filesystems
1265#
1266# CONFIG_ADFS_FS is not set
1267# CONFIG_AFFS_FS is not set
1268# CONFIG_ECRYPT_FS is not set
1269# CONFIG_HFS_FS is not set
1270# CONFIG_HFSPLUS_FS is not set
1271# CONFIG_BEFS_FS is not set
1272# CONFIG_BFS_FS is not set
1273# CONFIG_EFS_FS is not set
1274CONFIG_JFFS2_FS=y
1275CONFIG_JFFS2_FS_DEBUG=1
1276CONFIG_JFFS2_FS_WRITEBUFFER=y
1277CONFIG_JFFS2_FS_WBUF_VERIFY=y
1278# CONFIG_JFFS2_SUMMARY is not set
1279# CONFIG_JFFS2_FS_XATTR is not set
1280# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1281CONFIG_JFFS2_ZLIB=y
1282# CONFIG_JFFS2_LZO is not set
1283CONFIG_JFFS2_RTIME=y
1284# CONFIG_JFFS2_RUBIN is not set
1285# CONFIG_CRAMFS is not set
1286# CONFIG_VXFS_FS is not set
1287# CONFIG_HPFS_FS is not set
1288# CONFIG_QNX4FS_FS is not set
1289# CONFIG_SYSV_FS is not set
1290# CONFIG_UFS_FS is not set
1291CONFIG_NETWORK_FILESYSTEMS=y
1292CONFIG_NFS_FS=y
1293CONFIG_NFS_V3=y
1294# CONFIG_NFS_V3_ACL is not set
1295CONFIG_NFS_V4=y
1296# CONFIG_NFS_DIRECTIO is not set
1297CONFIG_NFSD=y
1298CONFIG_NFSD_V3=y
1299# CONFIG_NFSD_V3_ACL is not set
1300CONFIG_NFSD_V4=y
1301CONFIG_NFSD_TCP=y
1302CONFIG_ROOT_NFS=y
1303CONFIG_LOCKD=y
1304CONFIG_LOCKD_V4=y
1305CONFIG_EXPORTFS=y
1306CONFIG_NFS_COMMON=y
1307CONFIG_SUNRPC=y
1308CONFIG_SUNRPC_GSS=y
1309# CONFIG_SUNRPC_BIND34 is not set
1310CONFIG_RPCSEC_GSS_KRB5=y
1311# CONFIG_RPCSEC_GSS_SPKM3 is not set
1312# CONFIG_SMB_FS is not set
1313# CONFIG_CIFS is not set
1314# CONFIG_NCP_FS is not set
1315# CONFIG_CODA_FS is not set
1316# CONFIG_AFS_FS is not set
1317
1318#
1319# Partition Types
1320#
1321# CONFIG_PARTITION_ADVANCED is not set
1322CONFIG_MSDOS_PARTITION=y
1323CONFIG_NLS=y
1324CONFIG_NLS_DEFAULT="iso8859-15"
1325CONFIG_NLS_CODEPAGE_437=y
1326# CONFIG_NLS_CODEPAGE_737 is not set
1327# CONFIG_NLS_CODEPAGE_775 is not set
1328CONFIG_NLS_CODEPAGE_850=y
1329# CONFIG_NLS_CODEPAGE_852 is not set
1330# CONFIG_NLS_CODEPAGE_855 is not set
1331# CONFIG_NLS_CODEPAGE_857 is not set
1332# CONFIG_NLS_CODEPAGE_860 is not set
1333# CONFIG_NLS_CODEPAGE_861 is not set
1334# CONFIG_NLS_CODEPAGE_862 is not set
1335# CONFIG_NLS_CODEPAGE_863 is not set
1336# CONFIG_NLS_CODEPAGE_864 is not set
1337# CONFIG_NLS_CODEPAGE_865 is not set
1338# CONFIG_NLS_CODEPAGE_866 is not set
1339# CONFIG_NLS_CODEPAGE_869 is not set
1340# CONFIG_NLS_CODEPAGE_936 is not set
1341# CONFIG_NLS_CODEPAGE_950 is not set
1342# CONFIG_NLS_CODEPAGE_932 is not set
1343# CONFIG_NLS_CODEPAGE_949 is not set
1344# CONFIG_NLS_CODEPAGE_874 is not set
1345# CONFIG_NLS_ISO8859_8 is not set
1346# CONFIG_NLS_CODEPAGE_1250 is not set
1347# CONFIG_NLS_CODEPAGE_1251 is not set
1348CONFIG_NLS_ASCII=y
1349CONFIG_NLS_ISO8859_1=m
1350# CONFIG_NLS_ISO8859_2 is not set
1351# CONFIG_NLS_ISO8859_3 is not set
1352# CONFIG_NLS_ISO8859_4 is not set
1353# CONFIG_NLS_ISO8859_5 is not set
1354# CONFIG_NLS_ISO8859_6 is not set
1355# CONFIG_NLS_ISO8859_7 is not set
1356# CONFIG_NLS_ISO8859_9 is not set
1357# CONFIG_NLS_ISO8859_13 is not set
1358# CONFIG_NLS_ISO8859_14 is not set
1359CONFIG_NLS_ISO8859_15=m
1360# CONFIG_NLS_KOI8_R is not set
1361# CONFIG_NLS_KOI8_U is not set
1362CONFIG_NLS_UTF8=m
1363# CONFIG_DLM is not set
1364CONFIG_INSTRUMENTATION=y
1365# CONFIG_PROFILING is not set
1366# CONFIG_MARKERS is not set
1367
1368#
1369# Kernel hacking
1370#
1371CONFIG_PRINTK_TIME=y
1372CONFIG_ENABLE_WARN_DEPRECATED=y
1373CONFIG_ENABLE_MUST_CHECK=y
1374CONFIG_MAGIC_SYSRQ=y
1375# CONFIG_UNUSED_SYMBOLS is not set
1376CONFIG_DEBUG_FS=y
1377# CONFIG_HEADERS_CHECK is not set
1378CONFIG_DEBUG_KERNEL=y
1379# CONFIG_DEBUG_SHIRQ is not set
1380CONFIG_DETECT_SOFTLOCKUP=y
1381CONFIG_SCHED_DEBUG=y
1382# CONFIG_SCHEDSTATS is not set
1383# CONFIG_TIMER_STATS is not set
1384# CONFIG_DEBUG_SLAB is not set
1385CONFIG_DEBUG_PREEMPT=y
1386# CONFIG_DEBUG_RT_MUTEXES is not set
1387# CONFIG_RT_MUTEX_TESTER is not set
1388# CONFIG_DEBUG_SPINLOCK is not set
1389# CONFIG_DEBUG_MUTEXES is not set
1390# CONFIG_DEBUG_LOCK_ALLOC is not set
1391# CONFIG_PROVE_LOCKING is not set
1392# CONFIG_LOCK_STAT is not set
1393# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1394# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1395# CONFIG_DEBUG_KOBJECT is not set
1396CONFIG_DEBUG_BUGVERBOSE=y
1397CONFIG_DEBUG_INFO=y
1398# CONFIG_DEBUG_VM is not set
1399# CONFIG_DEBUG_LIST is not set
1400# CONFIG_DEBUG_SG is not set
1401CONFIG_FRAME_POINTER=y
1402CONFIG_FORCED_INLINING=y
1403# CONFIG_BOOT_PRINTK_DELAY is not set
1404# CONFIG_RCU_TORTURE_TEST is not set
1405# CONFIG_FAULT_INJECTION is not set
1406# CONFIG_SAMPLES is not set
1407CONFIG_DEBUG_USER=y
1408CONFIG_DEBUG_ERRORS=y
1409CONFIG_DEBUG_LL=y
1410# CONFIG_DEBUG_ICEDCC is not set
1411
1412#
1413# Security options
1414#
1415CONFIG_KEYS=y
1416CONFIG_KEYS_DEBUG_PROC_KEYS=y
1417CONFIG_SECURITY=y
1418# CONFIG_SECURITY_NETWORK is not set
1419CONFIG_SECURITY_CAPABILITIES=y
1420# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1421# CONFIG_SECURITY_ROOTPLUG is not set
1422CONFIG_CRYPTO=y
1423CONFIG_CRYPTO_ALGAPI=y
1424CONFIG_CRYPTO_BLKCIPHER=y
1425CONFIG_CRYPTO_MANAGER=y
1426# CONFIG_CRYPTO_HMAC is not set
1427# CONFIG_CRYPTO_XCBC is not set
1428# CONFIG_CRYPTO_NULL is not set
1429# CONFIG_CRYPTO_MD4 is not set
1430CONFIG_CRYPTO_MD5=y
1431CONFIG_CRYPTO_SHA1=m
1432CONFIG_CRYPTO_SHA256=m
1433CONFIG_CRYPTO_SHA512=m
1434# CONFIG_CRYPTO_WP512 is not set
1435# CONFIG_CRYPTO_TGR192 is not set
1436# CONFIG_CRYPTO_GF128MUL is not set
1437CONFIG_CRYPTO_ECB=y
1438CONFIG_CRYPTO_CBC=y
1439CONFIG_CRYPTO_PCBC=m
1440# CONFIG_CRYPTO_LRW is not set
1441# CONFIG_CRYPTO_XTS is not set
1442# CONFIG_CRYPTO_CRYPTD is not set
1443CONFIG_CRYPTO_DES=y
1444# CONFIG_CRYPTO_FCRYPT is not set
1445# CONFIG_CRYPTO_BLOWFISH is not set
1446# CONFIG_CRYPTO_TWOFISH is not set
1447# CONFIG_CRYPTO_SERPENT is not set
1448CONFIG_CRYPTO_AES=m
1449# CONFIG_CRYPTO_CAST5 is not set
1450# CONFIG_CRYPTO_CAST6 is not set
1451# CONFIG_CRYPTO_TEA is not set
1452CONFIG_CRYPTO_ARC4=y
1453# CONFIG_CRYPTO_KHAZAD is not set
1454# CONFIG_CRYPTO_ANUBIS is not set
1455# CONFIG_CRYPTO_SEED is not set
1456CONFIG_CRYPTO_DEFLATE=m
1457CONFIG_CRYPTO_MICHAEL_MIC=m
1458CONFIG_CRYPTO_CRC32C=y
1459# CONFIG_CRYPTO_CAMELLIA is not set
1460# CONFIG_CRYPTO_TEST is not set
1461# CONFIG_CRYPTO_AUTHENC is not set
1462CONFIG_CRYPTO_HW=y
1463
1464#
1465# Library routines
1466#
1467CONFIG_BITREVERSE=y
1468CONFIG_CRC_CCITT=y
1469CONFIG_CRC16=y
1470# CONFIG_CRC_ITU_T is not set
1471CONFIG_CRC32=y
1472# CONFIG_CRC7 is not set
1473CONFIG_LIBCRC32C=y
1474CONFIG_ZLIB_INFLATE=y
1475CONFIG_ZLIB_DEFLATE=y
1476CONFIG_REED_SOLOMON=y
1477CONFIG_REED_SOLOMON_DEC16=y
1478CONFIG_PLIST=y
1479CONFIG_HAS_IOMEM=y
1480CONFIG_HAS_IOPORT=y
1481CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig
new file mode 100644
index 000000000000..ed487b90dbed
--- /dev/null
+++ b/arch/arm/configs/eseries_pxa_defconfig
@@ -0,0 +1,1499 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.21-hh17
4# Fri Nov 9 20:23:03 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_MMU=y
11# CONFIG_NO_IOPORT is not set
12CONFIG_GENERIC_HARDIRQS=y
13CONFIG_TRACE_IRQFLAGS_SUPPORT=y
14CONFIG_HARDIRQS_SW_RESEND=y
15CONFIG_GENERIC_IRQ_PROBE=y
16CONFIG_RWSEM_GENERIC_SPINLOCK=y
17# CONFIG_ARCH_HAS_ILOG2_U32 is not set
18# CONFIG_ARCH_HAS_ILOG2_U64 is not set
19CONFIG_GENERIC_HWEIGHT=y
20CONFIG_GENERIC_CALIBRATE_DELAY=y
21CONFIG_ZONE_DMA=y
22CONFIG_ARCH_MTD_XIP=y
23CONFIG_VECTORS_BASE=0xffff0000
24CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
25
26#
27# Code maturity level options
28#
29CONFIG_EXPERIMENTAL=y
30CONFIG_BROKEN_ON_SMP=y
31CONFIG_INIT_ENV_ARG_LIMIT=32
32
33#
34# General setup
35#
36CONFIG_LOCALVERSION=""
37CONFIG_LOCALVERSION_AUTO=y
38CONFIG_SWAP=y
39CONFIG_SYSVIPC=y
40# CONFIG_IPC_NS is not set
41CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set
43# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set
45# CONFIG_UTS_NS is not set
46# CONFIG_AUDIT is not set
47# CONFIG_IKCONFIG is not set
48CONFIG_SYSFS_DEPRECATED=y
49# CONFIG_RELAY is not set
50CONFIG_BLK_DEV_INITRD=y
51CONFIG_INITRAMFS_SOURCE=""
52# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
53CONFIG_SYSCTL=y
54CONFIG_EMBEDDED=y
55CONFIG_UID16=y
56CONFIG_SYSCTL_SYSCALL=y
57# CONFIG_KALLSYMS is not set
58CONFIG_HOTPLUG=y
59CONFIG_PRINTK=y
60CONFIG_BUG=y
61CONFIG_ELF_CORE=y
62CONFIG_BASE_FULL=y
63CONFIG_FUTEX=y
64CONFIG_EPOLL=y
65CONFIG_SHMEM=y
66CONFIG_SLAB=y
67CONFIG_VM_EVENT_COUNTERS=y
68CONFIG_RT_MUTEXES=y
69# CONFIG_TINY_SHMEM is not set
70CONFIG_BASE_SMALL=0
71# CONFIG_SLOB is not set
72
73#
74# Loadable module support
75#
76CONFIG_MODULES=y
77CONFIG_MODULE_UNLOAD=y
78CONFIG_MODULE_FORCE_UNLOAD=y
79# CONFIG_MODVERSIONS is not set
80# CONFIG_MODULE_SRCVERSION_ALL is not set
81CONFIG_KMOD=y
82
83#
84# Block layer
85#
86CONFIG_BLOCK=y
87# CONFIG_LBD is not set
88# CONFIG_BLK_DEV_IO_TRACE is not set
89# CONFIG_LSF is not set
90
91#
92# IO Schedulers
93#
94CONFIG_IOSCHED_NOOP=y
95CONFIG_IOSCHED_AS=y
96CONFIG_IOSCHED_DEADLINE=y
97CONFIG_IOSCHED_CFQ=y
98CONFIG_DEFAULT_AS=y
99# CONFIG_DEFAULT_DEADLINE is not set
100# CONFIG_DEFAULT_CFQ is not set
101# CONFIG_DEFAULT_NOOP is not set
102CONFIG_DEFAULT_IOSCHED="anticipatory"
103
104#
105# System Type
106#
107# CONFIG_ARCH_AAEC2000 is not set
108# CONFIG_ARCH_INTEGRATOR is not set
109# CONFIG_ARCH_REALVIEW is not set
110# CONFIG_ARCH_VERSATILE is not set
111# CONFIG_ARCH_AT91 is not set
112# CONFIG_ARCH_CLPS7500 is not set
113# CONFIG_ARCH_CLPS711X is not set
114# CONFIG_ARCH_CO285 is not set
115# CONFIG_ARCH_EBSA110 is not set
116# CONFIG_ARCH_EP93XX is not set
117# CONFIG_ARCH_FOOTBRIDGE is not set
118# CONFIG_ARCH_NETX is not set
119# CONFIG_ARCH_H720X is not set
120# CONFIG_ARCH_IMX is not set
121# CONFIG_ARCH_IOP32X is not set
122# CONFIG_ARCH_IOP33X is not set
123# CONFIG_ARCH_IOP13XX is not set
124# CONFIG_ARCH_IXP4XX is not set
125# CONFIG_ARCH_IXP2000 is not set
126# CONFIG_ARCH_IXP23XX is not set
127# CONFIG_ARCH_L7200 is not set
128# CONFIG_ARCH_NS9XXX is not set
129# CONFIG_ARCH_PNX4008 is not set
130CONFIG_ARCH_PXA=y
131# CONFIG_ARCH_RPC is not set
132# CONFIG_ARCH_SA1100 is not set
133# CONFIG_ARCH_S3C2410 is not set
134# CONFIG_ARCH_SHARK is not set
135# CONFIG_ARCH_LH7A40X is not set
136# CONFIG_ARCH_OMAP is not set
137# CONFIG_BOARD_IRQ_MAP_SMALL is not set
138CONFIG_BOARD_IRQ_MAP_BIG=y
139CONFIG_DMABOUNCE=y
140
141#
142# Intel PXA2xx Implementations
143#
144# CONFIG_ARCH_LUBBOCK is not set
145# CONFIG_MACH_LOGICPD_PXA270 is not set
146# CONFIG_MACH_MAINSTONE is not set
147# CONFIG_ARCH_PXA_IDP is not set
148CONFIG_TOSHIBA_TMIO_OHCI=y
149CONFIG_ARCH_ESERIES=y
150CONFIG_MACH_E330=y
151CONFIG_MACH_E740=y
152CONFIG_MACH_E750=y
153CONFIG_MACH_E400=y
154CONFIG_MACH_E800=y
155CONFIG_E330_LCD=y
156CONFIG_E740_LCD=y
157CONFIG_E750_LCD=y
158CONFIG_E400_LCD=y
159CONFIG_E800_LCD=y
160CONFIG_ESERIES_UDC=y
161CONFIG_E330_TC6387XB=y
162CONFIG_E740_T7L66XB=y
163CONFIG_E400_T7L66XB=y
164CONFIG_E750_E800_TC6393XB=y
165CONFIG_E740_PCMCIA=m
166CONFIG_E750_PCMCIA=m
167CONFIG_E800_PCMCIA=m
168# CONFIG_MACH_A620 is not set
169# CONFIG_MACH_A716 is not set
170# CONFIG_MACH_A730 is not set
171# CONFIG_ARCH_H1900 is not set
172# CONFIG_ARCH_H2200 is not set
173# CONFIG_MACH_H3900 is not set
174# CONFIG_MACH_H4000 is not set
175# CONFIG_MACH_H4700 is not set
176# CONFIG_MACH_HX2750 is not set
177# CONFIG_ARCH_H5400 is not set
178# CONFIG_MACH_HIMALAYA is not set
179# CONFIG_MACH_HTCUNIVERSAL is not set
180# CONFIG_MACH_HTCALPINE is not set
181# CONFIG_MACH_MAGICIAN is not set
182# CONFIG_MACH_HTCAPACHE is not set
183# CONFIG_MACH_BLUEANGEL is not set
184
185#
186# HTC_HW6X00
187#
188# CONFIG_MACH_HTCBEETLES is not set
189# CONFIG_MACH_HW6900 is not set
190# CONFIG_MACH_HTCATHENA is not set
191# CONFIG_ARCH_AXIMX3 is not set
192# CONFIG_ARCH_AXIMX5 is not set
193# CONFIG_MACH_X50 is not set
194# CONFIG_ARCH_ROVERP1 is not set
195# CONFIG_ARCH_ROVERP5P is not set
196# CONFIG_MACH_XSCALE_PALMLD is not set
197# CONFIG_MACH_T3XSCALE is not set
198# CONFIG_MACH_RECON is not set
199# CONFIG_MACH_GHI270HG is not set
200# CONFIG_MACH_GHI270 is not set
201# CONFIG_MACH_LOOXC550 is not set
202# CONFIG_PXA_SHARPSL is not set
203# CONFIG_MACH_TRIZEPS4 is not set
204CONFIG_PXA25x=y
205
206#
207# Linux As Bootloader
208#
209# CONFIG_LAB is not set
210
211#
212# Processor Type
213#
214CONFIG_CPU_32=y
215CONFIG_CPU_XSCALE=y
216CONFIG_CPU_32v5=y
217CONFIG_CPU_ABRT_EV5T=y
218CONFIG_CPU_CACHE_VIVT=y
219CONFIG_CPU_TLB_V4WBI=y
220CONFIG_CPU_CP15=y
221CONFIG_CPU_CP15_MMU=y
222
223#
224# Processor Features
225#
226# CONFIG_ARM_THUMB is not set
227# CONFIG_CPU_DCACHE_DISABLE is not set
228# CONFIG_OUTER_CACHE is not set
229CONFIG_IWMMXT=y
230CONFIG_XSCALE_PMU=y
231
232#
233# Bus support
234#
235
236#
237# PCCARD (PCMCIA/CardBus) support
238#
239CONFIG_PCCARD=m
240# CONFIG_PCMCIA_DEBUG is not set
241CONFIG_PCMCIA=m
242CONFIG_PCMCIA_LOAD_CIS=y
243CONFIG_PCMCIA_IOCTL=y
244
245#
246# PC-card bridges
247#
248CONFIG_PCMCIA_PXA2XX=m
249
250#
251# Kernel Features
252#
253# CONFIG_PREEMPT is not set
254# CONFIG_NO_IDLE_HZ is not set
255CONFIG_HZ=100
256CONFIG_AEABI=y
257CONFIG_OABI_COMPAT=y
258# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
259CONFIG_SELECT_MEMORY_MODEL=y
260CONFIG_FLATMEM_MANUAL=y
261# CONFIG_DISCONTIGMEM_MANUAL is not set
262# CONFIG_SPARSEMEM_MANUAL is not set
263CONFIG_FLATMEM=y
264CONFIG_FLAT_NODE_MEM_MAP=y
265# CONFIG_SPARSEMEM_STATIC is not set
266CONFIG_SPLIT_PTLOCK_CPUS=4096
267# CONFIG_RESOURCES_64BIT is not set
268CONFIG_ZONE_DMA_FLAG=1
269CONFIG_ALIGNMENT_TRAP=y
270
271#
272# Boot options
273#
274CONFIG_ZBOOT_ROM_TEXT=0x0
275CONFIG_ZBOOT_ROM_BSS=0x0
276CONFIG_CMDLINE=""
277# CONFIG_XIP_KERNEL is not set
278CONFIG_KEXEC=y
279# CONFIG_TXTOFFSET_DELTA is not set
280
281#
282# CPU Frequency scaling
283#
284# CONFIG_CPU_FREQ is not set
285
286#
287# Floating point emulation
288#
289
290#
291# At least one emulation must be selected
292#
293CONFIG_FPE_NWFPE=y
294# CONFIG_FPE_NWFPE_XP is not set
295# CONFIG_FPE_FASTFPE is not set
296
297#
298# Userspace binary formats
299#
300CONFIG_BINFMT_ELF=y
301# CONFIG_BINFMT_AOUT is not set
302CONFIG_BINFMT_MISC=y
303
304#
305# Power management options
306#
307CONFIG_PM=y
308CONFIG_PM_LEGACY=y
309# CONFIG_PM_DEBUG is not set
310# CONFIG_DPM_DEBUG is not set
311# CONFIG_PM_SYSFS_DEPRECATED is not set
312# CONFIG_APM_EMULATION is not set
313
314#
315# Networking
316#
317CONFIG_NET=y
318
319#
320# Networking options
321#
322# CONFIG_NETDEBUG is not set
323# CONFIG_PACKET is not set
324CONFIG_UNIX=y
325CONFIG_XFRM=y
326# CONFIG_XFRM_USER is not set
327# CONFIG_XFRM_SUB_POLICY is not set
328# CONFIG_XFRM_MIGRATE is not set
329# CONFIG_NET_KEY is not set
330CONFIG_INET=y
331# CONFIG_IP_MULTICAST is not set
332# CONFIG_IP_ADVANCED_ROUTER is not set
333CONFIG_IP_FIB_HASH=y
334# CONFIG_IP_PNP is not set
335# CONFIG_NET_IPIP is not set
336# CONFIG_NET_IPGRE is not set
337# CONFIG_ARPD is not set
338# CONFIG_SYN_COOKIES is not set
339# CONFIG_INET_AH is not set
340# CONFIG_INET_ESP is not set
341# CONFIG_INET_IPCOMP is not set
342# CONFIG_INET_XFRM_TUNNEL is not set
343# CONFIG_INET_TUNNEL is not set
344CONFIG_INET_XFRM_MODE_TRANSPORT=y
345CONFIG_INET_XFRM_MODE_TUNNEL=y
346CONFIG_INET_XFRM_MODE_BEET=y
347CONFIG_INET_DIAG=y
348CONFIG_INET_TCP_DIAG=y
349# CONFIG_TCP_CONG_ADVANCED is not set
350CONFIG_TCP_CONG_CUBIC=y
351CONFIG_DEFAULT_TCP_CONG="cubic"
352# CONFIG_TCP_MD5SIG is not set
353# CONFIG_IPV6 is not set
354# CONFIG_INET6_XFRM_TUNNEL is not set
355# CONFIG_INET6_TUNNEL is not set
356# CONFIG_NETWORK_SECMARK is not set
357# CONFIG_NETFILTER is not set
358
359#
360# DCCP Configuration (EXPERIMENTAL)
361#
362# CONFIG_IP_DCCP is not set
363
364#
365# SCTP Configuration (EXPERIMENTAL)
366#
367# CONFIG_IP_SCTP is not set
368
369#
370# TIPC Configuration (EXPERIMENTAL)
371#
372# CONFIG_TIPC is not set
373# CONFIG_ATM is not set
374# CONFIG_BRIDGE is not set
375# CONFIG_VLAN_8021Q is not set
376# CONFIG_DECNET is not set
377# CONFIG_LLC2 is not set
378# CONFIG_IPX is not set
379# CONFIG_ATALK is not set
380# CONFIG_X25 is not set
381# CONFIG_LAPB is not set
382# CONFIG_ECONET is not set
383# CONFIG_WAN_ROUTER is not set
384
385#
386# QoS and/or fair queueing
387#
388# CONFIG_NET_SCHED is not set
389
390#
391# Network testing
392#
393# CONFIG_NET_PKTGEN is not set
394# CONFIG_HAMRADIO is not set
395# CONFIG_IRDA is not set
396# CONFIG_BT is not set
397CONFIG_IEEE80211=m
398# CONFIG_IEEE80211_DEBUG is not set
399CONFIG_IEEE80211_CRYPT_WEP=m
400# CONFIG_IEEE80211_CRYPT_CCMP is not set
401# CONFIG_IEEE80211_CRYPT_TKIP is not set
402# CONFIG_IEEE80211_SOFTMAC is not set
403CONFIG_WIRELESS_EXT=y
404
405#
406# Device Drivers
407#
408
409#
410# Generic Driver Options
411#
412# CONFIG_STANDALONE is not set
413CONFIG_PREVENT_FIRMWARE_BUILD=y
414CONFIG_FW_LOADER=y
415# CONFIG_SYS_HYPERVISOR is not set
416
417#
418# Connector - unified userspace <-> kernelspace linker
419#
420# CONFIG_CONNECTOR is not set
421
422#
423# Memory Technology Devices (MTD)
424#
425CONFIG_MTD=m
426# CONFIG_MTD_DEBUG is not set
427# CONFIG_MTD_CONCAT is not set
428CONFIG_MTD_PARTITIONS=y
429# CONFIG_MTD_REDBOOT_PARTS is not set
430# CONFIG_MTD_AFS_PARTS is not set
431
432#
433# User Modules And Translation Layers
434#
435CONFIG_MTD_CHAR=m
436CONFIG_MTD_BLKDEVS=m
437CONFIG_MTD_BLOCK=m
438# CONFIG_MTD_BLOCK_RO is not set
439# CONFIG_FTL is not set
440# CONFIG_NFTL is not set
441# CONFIG_INFTL is not set
442# CONFIG_RFD_FTL is not set
443# CONFIG_SSFDC is not set
444
445#
446# RAM/ROM/Flash chip drivers
447#
448# CONFIG_MTD_CFI is not set
449# CONFIG_MTD_JEDECPROBE is not set
450CONFIG_MTD_MAP_BANK_WIDTH_1=y
451CONFIG_MTD_MAP_BANK_WIDTH_2=y
452CONFIG_MTD_MAP_BANK_WIDTH_4=y
453# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
454# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
455# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
456CONFIG_MTD_CFI_I1=y
457CONFIG_MTD_CFI_I2=y
458# CONFIG_MTD_CFI_I4 is not set
459# CONFIG_MTD_CFI_I8 is not set
460# CONFIG_MTD_RAM is not set
461# CONFIG_MTD_ROM is not set
462# CONFIG_MTD_ABSENT is not set
463# CONFIG_MTD_OBSOLETE_CHIPS is not set
464
465#
466# Mapping drivers for chip access
467#
468# CONFIG_MTD_COMPLEX_MAPPINGS is not set
469# CONFIG_MTD_SHARP_SL is not set
470# CONFIG_MTD_PLATRAM is not set
471
472#
473# Self-contained MTD device drivers
474#
475# CONFIG_MTD_SLRAM is not set
476# CONFIG_MTD_PHRAM is not set
477# CONFIG_MTD_MTDRAM is not set
478# CONFIG_MTD_BLOCK2MTD is not set
479
480#
481# Disk-On-Chip Device Drivers
482#
483# CONFIG_MTD_DOC2000 is not set
484# CONFIG_MTD_DOC2001 is not set
485# CONFIG_MTD_DOC2001PLUS is not set
486
487#
488# NAND Flash Device Drivers
489#
490CONFIG_MTD_NAND=m
491CONFIG_MTD_NAND_VERIFY_WRITE=y
492# CONFIG_MTD_NAND_ECC_SMC is not set
493# CONFIG_MTD_NAND_H1900 is not set
494CONFIG_MTD_NAND_IDS=m
495# CONFIG_MTD_NAND_DISKONCHIP is not set
496# CONFIG_MTD_NAND_SHARPSL is not set
497# CONFIG_MTD_NAND_NANDSIM is not set
498
499#
500# OneNAND Flash Device Drivers
501#
502# CONFIG_MTD_ONENAND is not set
503
504#
505# Parallel port support
506#
507# CONFIG_PARPORT is not set
508
509#
510# Plug and Play support
511#
512# CONFIG_PNPACPI is not set
513
514#
515# Block devices
516#
517# CONFIG_BLK_DEV_COW_COMMON is not set
518CONFIG_BLK_DEV_LOOP=m
519# CONFIG_BLK_DEV_CRYPTOLOOP is not set
520# CONFIG_BLK_DEV_NBD is not set
521# CONFIG_BLK_DEV_UB is not set
522CONFIG_BLK_DEV_RAM=y
523CONFIG_BLK_DEV_RAM_COUNT=16
524CONFIG_BLK_DEV_RAM_SIZE=6144
525CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
526# CONFIG_CDROM_PKTCDVD is not set
527# CONFIG_ATA_OVER_ETH is not set
528
529#
530# ATA/ATAPI/MFM/RLL support
531#
532CONFIG_IDE=m
533CONFIG_IDE_MAX_HWIFS=4
534CONFIG_BLK_DEV_IDE=m
535
536#
537# Please see Documentation/ide.txt for help/info on IDE drives
538#
539# CONFIG_BLK_DEV_IDE_SATA is not set
540CONFIG_BLK_DEV_IDEDISK=m
541# CONFIG_IDEDISK_MULTI_MODE is not set
542# CONFIG_BLK_DEV_IDECS is not set
543# CONFIG_BLK_DEV_IDECD is not set
544# CONFIG_BLK_DEV_IDETAPE is not set
545# CONFIG_BLK_DEV_IDEFLOPPY is not set
546# CONFIG_BLK_DEV_IDESCSI is not set
547# CONFIG_IDE_TASK_IOCTL is not set
548
549#
550# IDE chipset support/bugfixes
551#
552# CONFIG_IDE_GENERIC is not set
553# CONFIG_IDE_ARM is not set
554# CONFIG_BLK_DEV_IDEDMA is not set
555# CONFIG_BLK_DEV_HD is not set
556
557#
558# SCSI device support
559#
560# CONFIG_RAID_ATTRS is not set
561CONFIG_SCSI=m
562# CONFIG_SCSI_TGT is not set
563# CONFIG_SCSI_NETLINK is not set
564# CONFIG_SCSI_PROC_FS is not set
565
566#
567# SCSI support type (disk, tape, CD-ROM)
568#
569# CONFIG_BLK_DEV_SD is not set
570# CONFIG_CHR_DEV_ST is not set
571# CONFIG_CHR_DEV_OSST is not set
572# CONFIG_BLK_DEV_SR is not set
573# CONFIG_CHR_DEV_SG is not set
574# CONFIG_CHR_DEV_SCH is not set
575
576#
577# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
578#
579# CONFIG_SCSI_MULTI_LUN is not set
580# CONFIG_SCSI_CONSTANTS is not set
581# CONFIG_SCSI_LOGGING is not set
582# CONFIG_SCSI_SCAN_ASYNC is not set
583
584#
585# SCSI Transports
586#
587# CONFIG_SCSI_SPI_ATTRS is not set
588# CONFIG_SCSI_FC_ATTRS is not set
589# CONFIG_SCSI_ISCSI_ATTRS is not set
590# CONFIG_SCSI_SAS_ATTRS is not set
591# CONFIG_SCSI_SAS_LIBSAS is not set
592
593#
594# SCSI low-level drivers
595#
596# CONFIG_ISCSI_TCP is not set
597# CONFIG_SCSI_DEBUG is not set
598
599#
600# PCMCIA SCSI adapter support
601#
602# CONFIG_PCMCIA_AHA152X is not set
603# CONFIG_PCMCIA_FDOMAIN is not set
604# CONFIG_PCMCIA_NINJA_SCSI is not set
605# CONFIG_PCMCIA_QLOGIC is not set
606# CONFIG_PCMCIA_SYM53C500 is not set
607
608#
609# Serial ATA (prod) and Parallel ATA (experimental) drivers
610#
611# CONFIG_ATA is not set
612
613#
614# Multi-device support (RAID and LVM)
615#
616# CONFIG_MD is not set
617
618#
619# Fusion MPT device support
620#
621# CONFIG_FUSION is not set
622
623#
624# IEEE 1394 (FireWire) support
625#
626
627#
628# I2O device support
629#
630
631#
632# Network device support
633#
634CONFIG_NETDEVICES=y
635# CONFIG_DUMMY is not set
636# CONFIG_BONDING is not set
637# CONFIG_EQUALIZER is not set
638# CONFIG_TUN is not set
639
640#
641# PHY device support
642#
643
644#
645# Ethernet (10 or 100Mbit)
646#
647# CONFIG_NET_ETHERNET is not set
648
649#
650# Ethernet (1000 Mbit)
651#
652
653#
654# Ethernet (10000 Mbit)
655#
656
657#
658# Token Ring devices
659#
660
661#
662# Wireless LAN (non-hamradio)
663#
664CONFIG_NET_RADIO=y
665# CONFIG_NET_WIRELESS_RTNETLINK is not set
666
667#
668# Obsolete Wireless cards support (pre-802.11)
669#
670# CONFIG_STRIP is not set
671# CONFIG_PCMCIA_WAVELAN is not set
672# CONFIG_PCMCIA_NETWAVE is not set
673
674#
675# Wireless 802.11 Frequency Hopping cards support
676#
677# CONFIG_PCMCIA_RAYCS is not set
678
679#
680# Wireless 802.11b ISA/PCI cards support
681#
682# CONFIG_HERMES is not set
683# CONFIG_ATMEL is not set
684
685#
686# Wireless 802.11b Pcmcia/Cardbus cards support
687#
688# CONFIG_AIRO_CS is not set
689# CONFIG_PCMCIA_WL3501 is not set
690# CONFIG_USB_ZD1201 is not set
691CONFIG_HOSTAP=m
692# CONFIG_HOSTAP_FIRMWARE is not set
693# CONFIG_HOSTAP_CS is not set
694# CONFIG_ACX is not set
695CONFIG_NET_WIRELESS=y
696
697#
698# PCMCIA network device support
699#
700# CONFIG_NET_PCMCIA is not set
701
702#
703# Wan interfaces
704#
705# CONFIG_WAN is not set
706# CONFIG_PPP is not set
707# CONFIG_SLIP is not set
708# CONFIG_SHAPER is not set
709# CONFIG_NETCONSOLE is not set
710# CONFIG_NETPOLL is not set
711# CONFIG_NET_POLL_CONTROLLER is not set
712
713#
714# ISDN subsystem
715#
716# CONFIG_ISDN is not set
717
718#
719# Input device support
720#
721CONFIG_INPUT=y
722# CONFIG_INPUT_FF_MEMLESS is not set
723
724#
725# Userland interfaces
726#
727# CONFIG_INPUT_MOUSEDEV is not set
728# CONFIG_INPUT_JOYDEV is not set
729CONFIG_INPUT_TSDEV=m
730CONFIG_INPUT_TSDEV_SCREEN_X=240
731CONFIG_INPUT_TSDEV_SCREEN_Y=320
732CONFIG_INPUT_EVDEV=m
733# CONFIG_INPUT_EVBUG is not set
734# CONFIG_INPUT_LED_TRIGGER is not set
735
736#
737# Input Device Drivers
738#
739# CONFIG_INPUT_KEYBOARD is not set
740# CONFIG_INPUT_MOUSE is not set
741# CONFIG_INPUT_JOYSTICK is not set
742CONFIG_INPUT_TOUCHSCREEN=y
743# CONFIG_TOUCHSCREEN_GUNZE is not set
744# CONFIG_TOUCHSCREEN_ELO is not set
745# CONFIG_TOUCHSCREEN_MTOUCH is not set
746# CONFIG_TOUCHSCREEN_MK712 is not set
747CONFIG_TOUCHSCREEN_WM97XX=m
748CONFIG_TOUCHSCREEN_WM9705=y
749CONFIG_TOUCHSCREEN_WM9712=y
750CONFIG_TOUCHSCREEN_WM9713=y
751# CONFIG_TOUCHSCREEN_PENMOUNT is not set
752# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
753# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
754# CONFIG_TOUCHSCREEN_UCB1400 is not set
755# CONFIG_INPUT_MISC is not set
756
757#
758# Hardware I/O ports
759#
760# CONFIG_SERIO is not set
761# CONFIG_GAMEPORT is not set
762
763#
764# Character devices
765#
766CONFIG_VT=y
767CONFIG_VT_CONSOLE=y
768CONFIG_HW_CONSOLE=y
769# CONFIG_VT_HW_CONSOLE_BINDING is not set
770# CONFIG_SERIAL_NONSTANDARD is not set
771
772#
773# Serial drivers
774#
775# CONFIG_SERIAL_8250 is not set
776
777#
778# Non-8250 serial port support
779#
780# CONFIG_SERIAL_PXA is not set
781# CONFIG_RS232_SERIAL is not set
782CONFIG_UNIX98_PTYS=y
783# CONFIG_LEGACY_PTYS is not set
784
785#
786# IPMI
787#
788# CONFIG_IPMI_HANDLER is not set
789
790#
791# Watchdog Cards
792#
793# CONFIG_WATCHDOG is not set
794CONFIG_HW_RANDOM=m
795# CONFIG_NVRAM is not set
796# CONFIG_SA1100_RTC is not set
797# CONFIG_DTLK is not set
798# CONFIG_R3964 is not set
799# CONFIG_TIHTC is not set
800
801#
802# PCMCIA character devices
803#
804# CONFIG_SYNCLINK_CS is not set
805# CONFIG_CARDMAN_4000 is not set
806# CONFIG_CARDMAN_4040 is not set
807# CONFIG_RAW_DRIVER is not set
808
809#
810# TPM devices
811#
812# CONFIG_TCG_TPM is not set
813
814#
815# I2C support
816#
817# CONFIG_I2C is not set
818
819#
820# SPI support
821#
822# CONFIG_SPI is not set
823# CONFIG_SPI_MASTER is not set
824
825#
826# Dallas's 1-wire bus
827#
828# CONFIG_W1 is not set
829
830#
831# Hardware Monitoring support
832#
833# CONFIG_HWMON is not set
834# CONFIG_HWMON_VID is not set
835# CONFIG_POWER_SUPPLY is not set
836
837#
838# L3 serial bus support
839#
840# CONFIG_L3 is not set
841
842#
843# Misc devices
844#
845
846#
847# Multimedia Capabilities Port drivers
848#
849# CONFIG_ADC is not set
850
851#
852# Compaq/iPAQ Drivers
853#
854
855#
856# Compaq/HP iPAQ Drivers
857#
858# CONFIG_IPAQ_SLEEVE is not set
859# CONFIG_SLEEVE_DEBUG is not set
860
861#
862# Multifunction device drivers
863#
864# CONFIG_MFD_SM501 is not set
865# CONFIG_HTC_ASIC2 is not set
866# CONFIG_HTC_ASIC3 is not set
867# CONFIG_HTC_PASIC3 is not set
868# CONFIG_HTC_EGPIO is not set
869# CONFIG_HTC_BBKEYS is not set
870# CONFIG_HTC_ASIC3_DS1WM is not set
871# CONFIG_SOC_SAMCOP is not set
872# CONFIG_SOC_HAMCOP is not set
873# CONFIG_SOC_MQ11XX is not set
874CONFIG_SOC_T7L66XB=y
875# CONFIG_SOC_TC6387XB is not set
876CONFIG_SOC_TC6393XB=y
877# CONFIG_SOC_TSC2101 is not set
878# CONFIG_SOC_TSC2200 is not set
879
880#
881# LED devices
882#
883# CONFIG_NEW_LEDS is not set
884
885#
886# LED drivers
887#
888
889#
890# LED Triggers
891#
892# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
893
894#
895# Multimedia devices
896#
897# CONFIG_VIDEO_DEV is not set
898
899#
900# Digital Video Broadcasting Devices
901#
902# CONFIG_DVB is not set
903# CONFIG_USB_DABUSB is not set
904
905#
906# Graphics support
907#
908CONFIG_BACKLIGHT_LCD_SUPPORT=y
909CONFIG_BACKLIGHT_CLASS_DEVICE=y
910CONFIG_LCD_CLASS_DEVICE=y
911CONFIG_BACKLIGHT_CORGI=y
912CONFIG_FB=y
913# CONFIG_FIRMWARE_EDID is not set
914# CONFIG_FB_DDC is not set
915CONFIG_FB_CFB_FILLRECT=y
916CONFIG_FB_CFB_COPYAREA=y
917CONFIG_FB_CFB_IMAGEBLIT=y
918# CONFIG_FB_SVGALIB is not set
919# CONFIG_FB_MACMODES is not set
920# CONFIG_FB_BACKLIGHT is not set
921# CONFIG_FB_MODE_HELPERS is not set
922# CONFIG_FB_TILEBLITTING is not set
923
924#
925# Frame buffer hardware drivers
926#
927# CONFIG_FB_IMAGEON is not set
928# CONFIG_FB_S1D13XXX is not set
929CONFIG_FB_PXA=y
930# CONFIG_FB_PXA_PARAMETERS is not set
931# CONFIG_FB_MBX is not set
932CONFIG_FB_W100=y
933# CONFIG_FB_VIRTUAL is not set
934# CONFIG_FB_VSFB is not set
935
936#
937# Console display driver support
938#
939# CONFIG_VGA_CONSOLE is not set
940CONFIG_DUMMY_CONSOLE=y
941CONFIG_FRAMEBUFFER_CONSOLE=y
942# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
943CONFIG_FONTS=y
944# CONFIG_FONT_8x8 is not set
945# CONFIG_FONT_8x16 is not set
946# CONFIG_FONT_6x11 is not set
947# CONFIG_FONT_7x14 is not set
948# CONFIG_FONT_PEARL_8x8 is not set
949CONFIG_FONT_ACORN_8x8=y
950# CONFIG_FONT_MINI_4x6 is not set
951# CONFIG_FONT_SUN8x16 is not set
952# CONFIG_FONT_SUN12x22 is not set
953# CONFIG_FONT_10x18 is not set
954
955#
956# Logo configuration
957#
958CONFIG_LOGO=y
959# CONFIG_LOGO_LINUX_MONO is not set
960# CONFIG_LOGO_LINUX_VGA16 is not set
961CONFIG_LOGO_LINUX_CLUT224=y
962
963#
964# Sound
965#
966CONFIG_SOUND=y
967
968#
969# Advanced Linux Sound Architecture
970#
971CONFIG_SND=m
972CONFIG_SND_TIMER=m
973CONFIG_SND_PCM=m
974# CONFIG_SND_SEQUENCER is not set
975CONFIG_SND_OSSEMUL=y
976CONFIG_SND_MIXER_OSS=m
977CONFIG_SND_PCM_OSS=m
978CONFIG_SND_PCM_OSS_PLUGINS=y
979CONFIG_SND_DYNAMIC_MINORS=y
980CONFIG_SND_SUPPORT_OLD_API=y
981CONFIG_SND_VERBOSE_PROCFS=y
982CONFIG_SND_VERBOSE_PRINTK=y
983# CONFIG_SND_DEBUG is not set
984
985#
986# Generic devices
987#
988# CONFIG_SND_DUMMY is not set
989# CONFIG_SND_MTPAV is not set
990# CONFIG_SND_SERIAL_U16550 is not set
991# CONFIG_SND_MPU401 is not set
992
993#
994# ALSA ARM devices
995#
996# CONFIG_SND_PXA2XX_AC97 is not set
997# CONFIG_SND_RECON is not set
998
999#
1000# USB devices
1001#
1002# CONFIG_SND_USB_AUDIO is not set
1003
1004#
1005# PCMCIA devices
1006#
1007# CONFIG_SND_VXPOCKET is not set
1008# CONFIG_SND_PDAUDIOCF is not set
1009
1010#
1011# SoC audio support
1012#
1013CONFIG_SND_SOC_AC97_BUS=y
1014CONFIG_SND_SOC=m
1015
1016#
1017# SoC Platforms
1018#
1019
1020#
1021# SoC Audio for the Atmel AT91
1022#
1023
1024#
1025# SoC Audio for the Intel PXA2xx
1026#
1027CONFIG_SND_PXA2XX_SOC=m
1028CONFIG_SND_PXA2XX_SOC_AC97=m
1029CONFIG_SND_PXA2XX_SOC_E740_WM9705=m
1030CONFIG_SND_PXA2XX_SOC_E750_WM9705=m
1031CONFIG_SND_PXA2XX_SOC_E800_WM9712=m
1032# CONFIG_SND_PXA2XX_SOC_MAGICIAN is not set
1033# CONFIG_SND_PXA2XX_SOC_BLUEANGEL is not set
1034# CONFIG_SND_PXA2XX_SOC_H5000 is not set
1035
1036#
1037# SoC Audio for the Freescale i.MX
1038#
1039
1040#
1041# SoC Audio for the Samsung S3C24XX
1042#
1043# CONFIG_SND_SOC_AC97_CODEC is not set
1044# CONFIG_SND_SOC_WM8711 is not set
1045# CONFIG_SND_SOC_WM8510 is not set
1046# CONFIG_SND_SOC_WM8731 is not set
1047# CONFIG_SND_SOC_WM8750 is not set
1048# CONFIG_SND_SOC_WM8753 is not set
1049# CONFIG_SND_SOC_WM8772 is not set
1050# CONFIG_SND_SOC_WM8971 is not set
1051# CONFIG_SND_SOC_WM8956 is not set
1052# CONFIG_SND_SOC_WM8960 is not set
1053# CONFIG_SND_SOC_WM8976 is not set
1054# CONFIG_SND_SOC_WM8974 is not set
1055# CONFIG_SND_SOC_WM8980 is not set
1056CONFIG_SND_SOC_WM9705=m
1057# CONFIG_SND_SOC_WM9713 is not set
1058CONFIG_SND_SOC_WM9712=m
1059# CONFIG_SND_SOC_UDA1380 is not set
1060# CONFIG_SND_SOC_AK4535 is not set
1061
1062#
1063# Open Sound System
1064#
1065# CONFIG_SOUND_PRIME is not set
1066CONFIG_AC97_BUS=m
1067
1068#
1069# HID Devices
1070#
1071CONFIG_HID=y
1072# CONFIG_HID_DEBUG is not set
1073
1074#
1075# USB support
1076#
1077CONFIG_USB_ARCH_HAS_HCD=y
1078CONFIG_USB_ARCH_HAS_OHCI=y
1079# CONFIG_USB_ARCH_HAS_EHCI is not set
1080CONFIG_USB=m
1081CONFIG_USB_DEBUG=y
1082
1083#
1084# Miscellaneous USB options
1085#
1086CONFIG_USB_DEVICEFS=y
1087CONFIG_USB_DYNAMIC_MINORS=y
1088# CONFIG_USB_SUSPEND is not set
1089# CONFIG_USB_OTG is not set
1090
1091#
1092# USB Host Controller Drivers
1093#
1094# CONFIG_USB_ISP116X_HCD is not set
1095# CONFIG_USB_OHCI_HCD is not set
1096# CONFIG_USB_SL811_HCD is not set
1097
1098#
1099# USB Device Class drivers
1100#
1101# CONFIG_USB_ACM is not set
1102# CONFIG_USB_PRINTER is not set
1103
1104#
1105# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1106#
1107
1108#
1109# may also be needed; see USB_STORAGE Help for more information
1110#
1111CONFIG_USB_STORAGE=m
1112# CONFIG_USB_STORAGE_DEBUG is not set
1113# CONFIG_USB_STORAGE_DATAFAB is not set
1114# CONFIG_USB_STORAGE_FREECOM is not set
1115# CONFIG_USB_STORAGE_ISD200 is not set
1116# CONFIG_USB_STORAGE_DPCM is not set
1117# CONFIG_USB_STORAGE_USBAT is not set
1118# CONFIG_USB_STORAGE_SDDR09 is not set
1119# CONFIG_USB_STORAGE_SDDR55 is not set
1120# CONFIG_USB_STORAGE_JUMPSHOT is not set
1121# CONFIG_USB_STORAGE_ALAUDA is not set
1122# CONFIG_USB_STORAGE_KARMA is not set
1123# CONFIG_USB_LIBUSUAL is not set
1124
1125#
1126# USB Input Devices
1127#
1128# CONFIG_USB_HID is not set
1129
1130#
1131# USB HID Boot Protocol drivers
1132#
1133# CONFIG_USB_KBD is not set
1134# CONFIG_USB_MOUSE is not set
1135# CONFIG_USB_AIPTEK is not set
1136# CONFIG_USB_WACOM is not set
1137# CONFIG_USB_ACECAD is not set
1138# CONFIG_USB_KBTAB is not set
1139# CONFIG_USB_POWERMATE is not set
1140# CONFIG_USB_TOUCHSCREEN is not set
1141# CONFIG_USB_YEALINK is not set
1142# CONFIG_USB_XPAD is not set
1143# CONFIG_USB_ATI_REMOTE is not set
1144# CONFIG_USB_ATI_REMOTE2 is not set
1145# CONFIG_USB_KEYSPAN_REMOTE is not set
1146# CONFIG_USB_APPLETOUCH is not set
1147# CONFIG_USB_GTCO is not set
1148
1149#
1150# USB Imaging devices
1151#
1152# CONFIG_USB_MDC800 is not set
1153# CONFIG_USB_MICROTEK is not set
1154
1155#
1156# USB Network Adapters
1157#
1158# CONFIG_USB_CATC is not set
1159# CONFIG_USB_KAWETH is not set
1160# CONFIG_USB_PEGASUS is not set
1161# CONFIG_USB_RTL8150 is not set
1162# CONFIG_USB_USBNET_MII is not set
1163# CONFIG_USB_USBNET is not set
1164# CONFIG_USB_MON is not set
1165
1166#
1167# USB port drivers
1168#
1169
1170#
1171# USB Serial Converter support
1172#
1173# CONFIG_USB_SERIAL is not set
1174
1175#
1176# USB Miscellaneous drivers
1177#
1178# CONFIG_USB_EMI62 is not set
1179# CONFIG_USB_EMI26 is not set
1180# CONFIG_USB_ADUTUX is not set
1181# CONFIG_USB_AUERSWALD is not set
1182# CONFIG_USB_RIO500 is not set
1183# CONFIG_USB_LEGOTOWER is not set
1184# CONFIG_USB_LCD is not set
1185# CONFIG_USB_BERRY_CHARGE is not set
1186# CONFIG_USB_LED is not set
1187# CONFIG_USB_CYPRESS_CY7C63 is not set
1188# CONFIG_USB_CYTHERM is not set
1189# CONFIG_USB_PHIDGET is not set
1190# CONFIG_USB_IDMOUSE is not set
1191# CONFIG_USB_FTDI_ELAN is not set
1192# CONFIG_USB_APPLEDISPLAY is not set
1193# CONFIG_USB_LD is not set
1194# CONFIG_USB_TRANCEVIBRATOR is not set
1195# CONFIG_USB_IOWARRIOR is not set
1196# CONFIG_USB_TEST is not set
1197
1198#
1199# USB DSL modem support
1200#
1201
1202#
1203# USB Gadget Support
1204#
1205CONFIG_USB_GADGET=y
1206# CONFIG_USB_GADGET_DEBUG_FILES is not set
1207CONFIG_USB_GADGET_SELECTED=y
1208# CONFIG_USB_GADGET_NET2280 is not set
1209CONFIG_USB_GADGET_PXA2XX=y
1210CONFIG_USB_PXA2XX=y
1211# CONFIG_USB_PXA2XX_SMALL is not set
1212# CONFIG_USB_GADGET_PXA27X is not set
1213# CONFIG_USB_GADGET_GOKU is not set
1214# CONFIG_USB_GADGET_MQ11XX is not set
1215# CONFIG_USB_GADGET_LH7A40X is not set
1216# CONFIG_USB_GADGET_S3C2410 is not set
1217# CONFIG_USB_GADGET_OMAP is not set
1218# CONFIG_USB_GADGET_AT91 is not set
1219# CONFIG_USB_GADGET_DUMMY_HCD is not set
1220# CONFIG_USB_GADGET_DUALSPEED is not set
1221# CONFIG_USB_ZERO is not set
1222CONFIG_USB_ETH=y
1223# CONFIG_USB_ETH_RNDIS is not set
1224# CONFIG_USB_GADGETFS is not set
1225# CONFIG_USB_FILE_STORAGE is not set
1226# CONFIG_USB_G_SERIAL is not set
1227# CONFIG_USB_MIDI_GADGET is not set
1228# CONFIG_USB_G_CHAR is not set
1229# CONFIG_USB_PXA2XX_GPIO is not set
1230
1231#
1232# MMC/SD Card support
1233#
1234CONFIG_MMC=y
1235# CONFIG_MMC_DEBUG is not set
1236CONFIG_MMC_BLOCK=y
1237# CONFIG_MMC_PXA is not set
1238CONFIG_MMC_TMIO=y
1239# CONFIG_MMC_SAMCOP is not set
1240
1241#
1242# Real Time Clock
1243#
1244CONFIG_RTC_LIB=y
1245# CONFIG_RTC_CLASS is not set
1246
1247#
1248# File systems
1249#
1250CONFIG_EXT2_FS=y
1251# CONFIG_EXT2_FS_XATTR is not set
1252# CONFIG_EXT2_FS_XIP is not set
1253# CONFIG_EXT3_FS is not set
1254# CONFIG_EXT4DEV_FS is not set
1255# CONFIG_REISERFS_FS is not set
1256# CONFIG_JFS_FS is not set
1257# CONFIG_FS_POSIX_ACL is not set
1258# CONFIG_XFS_FS is not set
1259# CONFIG_GFS2_FS is not set
1260# CONFIG_OCFS2_FS is not set
1261# CONFIG_MINIX_FS is not set
1262# CONFIG_ROMFS_FS is not set
1263CONFIG_INOTIFY=y
1264CONFIG_INOTIFY_USER=y
1265# CONFIG_QUOTA is not set
1266CONFIG_DNOTIFY=y
1267# CONFIG_AUTOFS_FS is not set
1268# CONFIG_AUTOFS4_FS is not set
1269# CONFIG_FUSE_FS is not set
1270
1271#
1272# CD-ROM/DVD Filesystems
1273#
1274# CONFIG_ISO9660_FS is not set
1275# CONFIG_UDF_FS is not set
1276
1277#
1278# DOS/FAT/NT Filesystems
1279#
1280CONFIG_FAT_FS=y
1281# CONFIG_MSDOS_FS is not set
1282CONFIG_VFAT_FS=y
1283CONFIG_FAT_DEFAULT_CODEPAGE=437
1284CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1285# CONFIG_NTFS_FS is not set
1286
1287#
1288# Pseudo filesystems
1289#
1290CONFIG_PROC_FS=y
1291CONFIG_PROC_SYSCTL=y
1292CONFIG_SYSFS=y
1293CONFIG_TMPFS=y
1294# CONFIG_TMPFS_POSIX_ACL is not set
1295# CONFIG_HUGETLB_PAGE is not set
1296CONFIG_RAMFS=y
1297# CONFIG_CONFIGFS_FS is not set
1298
1299#
1300# Miscellaneous filesystems
1301#
1302# CONFIG_ADFS_FS is not set
1303# CONFIG_AFFS_FS is not set
1304# CONFIG_HFS_FS is not set
1305# CONFIG_HFSPLUS_FS is not set
1306# CONFIG_BEFS_FS is not set
1307# CONFIG_BFS_FS is not set
1308# CONFIG_EFS_FS is not set
1309CONFIG_JFFS2_FS=m
1310CONFIG_JFFS2_FS_DEBUG=0
1311CONFIG_JFFS2_FS_WRITEBUFFER=y
1312# CONFIG_JFFS2_SUMMARY is not set
1313# CONFIG_JFFS2_FS_XATTR is not set
1314# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1315CONFIG_JFFS2_ZLIB=y
1316CONFIG_JFFS2_RTIME=y
1317# CONFIG_JFFS2_RUBIN is not set
1318# CONFIG_CRAMFS is not set
1319# CONFIG_VXFS_FS is not set
1320# CONFIG_HPFS_FS is not set
1321# CONFIG_QNX4FS_FS is not set
1322# CONFIG_SYSV_FS is not set
1323# CONFIG_UFS_FS is not set
1324
1325#
1326# Network File Systems
1327#
1328CONFIG_NFS_FS=y
1329CONFIG_NFS_V3=y
1330# CONFIG_NFS_V3_ACL is not set
1331# CONFIG_NFS_V4 is not set
1332# CONFIG_NFS_DIRECTIO is not set
1333# CONFIG_NFSD is not set
1334CONFIG_LOCKD=y
1335CONFIG_LOCKD_V4=y
1336CONFIG_NFS_COMMON=y
1337CONFIG_SUNRPC=y
1338# CONFIG_RPCSEC_GSS_KRB5 is not set
1339# CONFIG_RPCSEC_GSS_SPKM3 is not set
1340# CONFIG_SMB_FS is not set
1341# CONFIG_CIFS is not set
1342# CONFIG_NCP_FS is not set
1343# CONFIG_CODA_FS is not set
1344# CONFIG_AFS_FS is not set
1345# CONFIG_9P_FS is not set
1346
1347#
1348# Partition Types
1349#
1350CONFIG_PARTITION_ADVANCED=y
1351# CONFIG_ACORN_PARTITION is not set
1352# CONFIG_OSF_PARTITION is not set
1353# CONFIG_AMIGA_PARTITION is not set
1354# CONFIG_ATARI_PARTITION is not set
1355# CONFIG_MAC_PARTITION is not set
1356CONFIG_MSDOS_PARTITION=y
1357# CONFIG_BSD_DISKLABEL is not set
1358# CONFIG_MINIX_SUBPARTITION is not set
1359# CONFIG_SOLARIS_X86_PARTITION is not set
1360# CONFIG_UNIXWARE_DISKLABEL is not set
1361# CONFIG_LDM_PARTITION is not set
1362# CONFIG_SGI_PARTITION is not set
1363# CONFIG_ULTRIX_PARTITION is not set
1364# CONFIG_SUN_PARTITION is not set
1365# CONFIG_KARMA_PARTITION is not set
1366# CONFIG_EFI_PARTITION is not set
1367
1368#
1369# Native Language Support
1370#
1371CONFIG_NLS=y
1372CONFIG_NLS_DEFAULT="iso8859-1"
1373CONFIG_NLS_CODEPAGE_437=y
1374# CONFIG_NLS_CODEPAGE_737 is not set
1375# CONFIG_NLS_CODEPAGE_775 is not set
1376# CONFIG_NLS_CODEPAGE_850 is not set
1377# CONFIG_NLS_CODEPAGE_852 is not set
1378# CONFIG_NLS_CODEPAGE_855 is not set
1379# CONFIG_NLS_CODEPAGE_857 is not set
1380# CONFIG_NLS_CODEPAGE_860 is not set
1381# CONFIG_NLS_CODEPAGE_861 is not set
1382# CONFIG_NLS_CODEPAGE_862 is not set
1383# CONFIG_NLS_CODEPAGE_863 is not set
1384# CONFIG_NLS_CODEPAGE_864 is not set
1385# CONFIG_NLS_CODEPAGE_865 is not set
1386# CONFIG_NLS_CODEPAGE_866 is not set
1387# CONFIG_NLS_CODEPAGE_869 is not set
1388# CONFIG_NLS_CODEPAGE_936 is not set
1389# CONFIG_NLS_CODEPAGE_950 is not set
1390# CONFIG_NLS_CODEPAGE_932 is not set
1391# CONFIG_NLS_CODEPAGE_949 is not set
1392# CONFIG_NLS_CODEPAGE_874 is not set
1393# CONFIG_NLS_ISO8859_8 is not set
1394# CONFIG_NLS_CODEPAGE_1250 is not set
1395# CONFIG_NLS_CODEPAGE_1251 is not set
1396# CONFIG_NLS_ASCII is not set
1397CONFIG_NLS_ISO8859_1=y
1398# CONFIG_NLS_ISO8859_2 is not set
1399# CONFIG_NLS_ISO8859_3 is not set
1400# CONFIG_NLS_ISO8859_4 is not set
1401# CONFIG_NLS_ISO8859_5 is not set
1402# CONFIG_NLS_ISO8859_6 is not set
1403# CONFIG_NLS_ISO8859_7 is not set
1404# CONFIG_NLS_ISO8859_9 is not set
1405# CONFIG_NLS_ISO8859_13 is not set
1406# CONFIG_NLS_ISO8859_14 is not set
1407# CONFIG_NLS_ISO8859_15 is not set
1408# CONFIG_NLS_KOI8_R is not set
1409# CONFIG_NLS_KOI8_U is not set
1410# CONFIG_NLS_UTF8 is not set
1411
1412#
1413# Distributed Lock Manager
1414#
1415# CONFIG_DLM is not set
1416
1417#
1418# Profiling support
1419#
1420# CONFIG_PROFILING is not set
1421
1422#
1423# Kernel hacking
1424#
1425# CONFIG_PRINTK_TIME is not set
1426CONFIG_ENABLE_MUST_CHECK=y
1427# CONFIG_MAGIC_SYSRQ is not set
1428# CONFIG_UNUSED_SYMBOLS is not set
1429# CONFIG_DEBUG_FS is not set
1430# CONFIG_HEADERS_CHECK is not set
1431# CONFIG_DEBUG_KERNEL is not set
1432CONFIG_LOG_BUF_SHIFT=14
1433# CONFIG_DEBUG_BUGVERBOSE is not set
1434CONFIG_FRAME_POINTER=y
1435# CONFIG_DEBUG_USER is not set
1436
1437#
1438# Security options
1439#
1440# CONFIG_KEYS is not set
1441# CONFIG_SECURITY is not set
1442
1443#
1444# Cryptographic options
1445#
1446CONFIG_CRYPTO=y
1447CONFIG_CRYPTO_ALGAPI=m
1448CONFIG_CRYPTO_BLKCIPHER=m
1449CONFIG_CRYPTO_MANAGER=m
1450# CONFIG_CRYPTO_HMAC is not set
1451# CONFIG_CRYPTO_XCBC is not set
1452# CONFIG_CRYPTO_NULL is not set
1453# CONFIG_CRYPTO_MD4 is not set
1454# CONFIG_CRYPTO_MD5 is not set
1455# CONFIG_CRYPTO_SHA1 is not set
1456# CONFIG_CRYPTO_SHA256 is not set
1457# CONFIG_CRYPTO_SHA512 is not set
1458# CONFIG_CRYPTO_WP512 is not set
1459# CONFIG_CRYPTO_TGR192 is not set
1460# CONFIG_CRYPTO_GF128MUL is not set
1461CONFIG_CRYPTO_ECB=m
1462CONFIG_CRYPTO_CBC=m
1463CONFIG_CRYPTO_PCBC=m
1464# CONFIG_CRYPTO_LRW is not set
1465# CONFIG_CRYPTO_DES is not set
1466# CONFIG_CRYPTO_FCRYPT is not set
1467# CONFIG_CRYPTO_BLOWFISH is not set
1468# CONFIG_CRYPTO_TWOFISH is not set
1469# CONFIG_CRYPTO_SERPENT is not set
1470# CONFIG_CRYPTO_AES is not set
1471# CONFIG_CRYPTO_CAST5 is not set
1472# CONFIG_CRYPTO_CAST6 is not set
1473# CONFIG_CRYPTO_TEA is not set
1474CONFIG_CRYPTO_ARC4=m
1475# CONFIG_CRYPTO_KHAZAD is not set
1476# CONFIG_CRYPTO_ANUBIS is not set
1477# CONFIG_CRYPTO_DEFLATE is not set
1478# CONFIG_CRYPTO_MICHAEL_MIC is not set
1479# CONFIG_CRYPTO_CRC32C is not set
1480# CONFIG_CRYPTO_CAMELLIA is not set
1481# CONFIG_CRYPTO_TEST is not set
1482
1483#
1484# Hardware crypto devices
1485#
1486
1487#
1488# Library routines
1489#
1490CONFIG_BITREVERSE=y
1491# CONFIG_CRC_CCITT is not set
1492# CONFIG_CRC16 is not set
1493CONFIG_CRC32=y
1494# CONFIG_LIBCRC32C is not set
1495CONFIG_ZLIB_INFLATE=m
1496CONFIG_ZLIB_DEFLATE=m
1497CONFIG_PLIST=y
1498CONFIG_HAS_IOMEM=y
1499CONFIG_HAS_IOPORT=y
diff --git a/arch/arm/configs/littleton_defconfig b/arch/arm/configs/littleton_defconfig
new file mode 100644
index 000000000000..1db496908052
--- /dev/null
+++ b/arch/arm/configs/littleton_defconfig
@@ -0,0 +1,783 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24-rc5
4# Fri Dec 21 11:06:19 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_ARCH_MTD_XIP=y
26CONFIG_VECTORS_BASE=0xffff0000
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28
29#
30# General setup
31#
32CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y
34CONFIG_LOCK_KERNEL=y
35CONFIG_INIT_ENV_ARG_LIMIT=32
36CONFIG_LOCALVERSION=""
37CONFIG_LOCALVERSION_AUTO=y
38CONFIG_SWAP=y
39CONFIG_SYSVIPC=y
40CONFIG_SYSVIPC_SYSCTL=y
41# CONFIG_POSIX_MQUEUE is not set
42# CONFIG_BSD_PROCESS_ACCT is not set
43# CONFIG_TASKSTATS is not set
44# CONFIG_USER_NS is not set
45# CONFIG_PID_NS is not set
46# CONFIG_AUDIT is not set
47# CONFIG_IKCONFIG is not set
48CONFIG_LOG_BUF_SHIFT=14
49# CONFIG_CGROUPS is not set
50CONFIG_FAIR_GROUP_SCHED=y
51CONFIG_FAIR_USER_SCHED=y
52# CONFIG_FAIR_CGROUP_SCHED is not set
53CONFIG_SYSFS_DEPRECATED=y
54# CONFIG_RELAY is not set
55CONFIG_BLK_DEV_INITRD=y
56CONFIG_INITRAMFS_SOURCE=""
57CONFIG_CC_OPTIMIZE_FOR_SIZE=y
58CONFIG_SYSCTL=y
59# CONFIG_EMBEDDED is not set
60CONFIG_UID16=y
61CONFIG_SYSCTL_SYSCALL=y
62CONFIG_KALLSYMS=y
63# CONFIG_KALLSYMS_ALL is not set
64# CONFIG_KALLSYMS_EXTRA_PASS is not set
65CONFIG_HOTPLUG=y
66CONFIG_PRINTK=y
67CONFIG_BUG=y
68CONFIG_ELF_CORE=y
69CONFIG_BASE_FULL=y
70CONFIG_FUTEX=y
71CONFIG_ANON_INODES=y
72CONFIG_EPOLL=y
73CONFIG_SIGNALFD=y
74CONFIG_EVENTFD=y
75CONFIG_SHMEM=y
76CONFIG_VM_EVENT_COUNTERS=y
77CONFIG_SLAB=y
78# CONFIG_SLUB is not set
79# CONFIG_SLOB is not set
80CONFIG_RT_MUTEXES=y
81# CONFIG_TINY_SHMEM is not set
82CONFIG_BASE_SMALL=0
83CONFIG_MODULES=y
84CONFIG_MODULE_UNLOAD=y
85CONFIG_MODULE_FORCE_UNLOAD=y
86# CONFIG_MODVERSIONS is not set
87# CONFIG_MODULE_SRCVERSION_ALL is not set
88# CONFIG_KMOD is not set
89CONFIG_BLOCK=y
90# CONFIG_LBD is not set
91# CONFIG_BLK_DEV_IO_TRACE is not set
92# CONFIG_LSF is not set
93# CONFIG_BLK_DEV_BSG is not set
94
95#
96# IO Schedulers
97#
98CONFIG_IOSCHED_NOOP=y
99CONFIG_IOSCHED_AS=y
100CONFIG_IOSCHED_DEADLINE=y
101CONFIG_IOSCHED_CFQ=y
102# CONFIG_DEFAULT_AS is not set
103# CONFIG_DEFAULT_DEADLINE is not set
104CONFIG_DEFAULT_CFQ=y
105# CONFIG_DEFAULT_NOOP is not set
106CONFIG_DEFAULT_IOSCHED="cfq"
107
108#
109# System Type
110#
111# CONFIG_ARCH_AAEC2000 is not set
112# CONFIG_ARCH_INTEGRATOR is not set
113# CONFIG_ARCH_REALVIEW is not set
114# CONFIG_ARCH_VERSATILE is not set
115# CONFIG_ARCH_AT91 is not set
116# CONFIG_ARCH_CLPS7500 is not set
117# CONFIG_ARCH_CLPS711X is not set
118# CONFIG_ARCH_CO285 is not set
119# CONFIG_ARCH_EBSA110 is not set
120# CONFIG_ARCH_EP93XX is not set
121# CONFIG_ARCH_FOOTBRIDGE is not set
122# CONFIG_ARCH_NETX is not set
123# CONFIG_ARCH_H720X is not set
124# CONFIG_ARCH_IMX is not set
125# CONFIG_ARCH_IOP13XX is not set
126# CONFIG_ARCH_IOP32X is not set
127# CONFIG_ARCH_IOP33X is not set
128# CONFIG_ARCH_IXP23XX is not set
129# CONFIG_ARCH_IXP2000 is not set
130# CONFIG_ARCH_IXP4XX is not set
131# CONFIG_ARCH_L7200 is not set
132# CONFIG_ARCH_KS8695 is not set
133# CONFIG_ARCH_NS9XXX is not set
134# CONFIG_ARCH_MXC is not set
135# CONFIG_ARCH_PNX4008 is not set
136CONFIG_ARCH_PXA=y
137# CONFIG_ARCH_RPC is not set
138# CONFIG_ARCH_SA1100 is not set
139# CONFIG_ARCH_S3C2410 is not set
140# CONFIG_ARCH_SHARK is not set
141# CONFIG_ARCH_LH7A40X is not set
142# CONFIG_ARCH_DAVINCI is not set
143# CONFIG_ARCH_OMAP is not set
144
145#
146# Intel PXA2xx/PXA3xx Implementations
147#
148
149#
150# Supported PXA3xx Processor Variants
151#
152CONFIG_CPU_PXA300=y
153CONFIG_CPU_PXA310=y
154# CONFIG_CPU_PXA320 is not set
155# CONFIG_ARCH_LUBBOCK is not set
156# CONFIG_MACH_LOGICPD_PXA270 is not set
157# CONFIG_MACH_MAINSTONE is not set
158# CONFIG_ARCH_PXA_IDP is not set
159# CONFIG_PXA_SHARPSL is not set
160# CONFIG_MACH_TRIZEPS4 is not set
161# CONFIG_MACH_EM_X270 is not set
162# CONFIG_MACH_ZYLONITE is not set
163CONFIG_MACH_LITTLETON=y
164# CONFIG_MACH_ARMCORE is not set
165CONFIG_PXA3xx=y
166CONFIG_PXA_SSP=y
167
168#
169# Boot options
170#
171
172#
173# Power management
174#
175
176#
177# Processor Type
178#
179CONFIG_CPU_32=y
180CONFIG_CPU_XSC3=y
181CONFIG_CPU_32v5=y
182CONFIG_CPU_ABRT_EV5T=y
183CONFIG_CPU_CACHE_VIVT=y
184CONFIG_CPU_TLB_V4WBI=y
185CONFIG_CPU_CP15=y
186CONFIG_CPU_CP15_MMU=y
187CONFIG_IO_36=y
188
189#
190# Processor Features
191#
192# CONFIG_ARM_THUMB is not set
193# CONFIG_CPU_DCACHE_DISABLE is not set
194# CONFIG_CPU_BPREDICT_DISABLE is not set
195# CONFIG_OUTER_CACHE is not set
196CONFIG_IWMMXT=y
197
198#
199# Bus support
200#
201# CONFIG_PCI_SYSCALL is not set
202# CONFIG_ARCH_SUPPORTS_MSI is not set
203# CONFIG_PCCARD is not set
204
205#
206# Kernel Features
207#
208CONFIG_TICK_ONESHOT=y
209# CONFIG_NO_HZ is not set
210# CONFIG_HIGH_RES_TIMERS is not set
211CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
212CONFIG_PREEMPT=y
213CONFIG_HZ=100
214CONFIG_AEABI=y
215CONFIG_OABI_COMPAT=y
216# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
217CONFIG_SELECT_MEMORY_MODEL=y
218CONFIG_FLATMEM_MANUAL=y
219# CONFIG_DISCONTIGMEM_MANUAL is not set
220# CONFIG_SPARSEMEM_MANUAL is not set
221CONFIG_FLATMEM=y
222CONFIG_FLAT_NODE_MEM_MAP=y
223# CONFIG_SPARSEMEM_STATIC is not set
224# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
225CONFIG_SPLIT_PTLOCK_CPUS=4096
226# CONFIG_RESOURCES_64BIT is not set
227CONFIG_ZONE_DMA_FLAG=1
228CONFIG_BOUNCE=y
229CONFIG_VIRT_TO_BUS=y
230CONFIG_ALIGNMENT_TRAP=y
231
232#
233# Boot options
234#
235CONFIG_ZBOOT_ROM_TEXT=0x0
236CONFIG_ZBOOT_ROM_BSS=0x0
237CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=64M"
238# CONFIG_XIP_KERNEL is not set
239# CONFIG_KEXEC is not set
240
241#
242# CPU Frequency scaling
243#
244# CONFIG_CPU_FREQ is not set
245
246#
247# Floating point emulation
248#
249
250#
251# At least one emulation must be selected
252#
253CONFIG_FPE_NWFPE=y
254# CONFIG_FPE_NWFPE_XP is not set
255# CONFIG_FPE_FASTFPE is not set
256
257#
258# Userspace binary formats
259#
260CONFIG_BINFMT_ELF=y
261# CONFIG_BINFMT_AOUT is not set
262# CONFIG_BINFMT_MISC is not set
263
264#
265# Power management options
266#
267# CONFIG_PM is not set
268CONFIG_SUSPEND_UP_POSSIBLE=y
269
270#
271# Networking
272#
273CONFIG_NET=y
274
275#
276# Networking options
277#
278CONFIG_PACKET=y
279# CONFIG_PACKET_MMAP is not set
280CONFIG_UNIX=y
281CONFIG_XFRM=y
282# CONFIG_XFRM_USER is not set
283# CONFIG_XFRM_SUB_POLICY is not set
284# CONFIG_XFRM_MIGRATE is not set
285# CONFIG_NET_KEY is not set
286CONFIG_INET=y
287# CONFIG_IP_MULTICAST is not set
288# CONFIG_IP_ADVANCED_ROUTER is not set
289CONFIG_IP_FIB_HASH=y
290CONFIG_IP_PNP=y
291# CONFIG_IP_PNP_DHCP is not set
292# CONFIG_IP_PNP_BOOTP is not set
293# CONFIG_IP_PNP_RARP is not set
294# CONFIG_NET_IPIP is not set
295# CONFIG_NET_IPGRE is not set
296# CONFIG_ARPD is not set
297# CONFIG_SYN_COOKIES is not set
298# CONFIG_INET_AH is not set
299# CONFIG_INET_ESP is not set
300# CONFIG_INET_IPCOMP is not set
301# CONFIG_INET_XFRM_TUNNEL is not set
302# CONFIG_INET_TUNNEL is not set
303CONFIG_INET_XFRM_MODE_TRANSPORT=y
304CONFIG_INET_XFRM_MODE_TUNNEL=y
305CONFIG_INET_XFRM_MODE_BEET=y
306# CONFIG_INET_LRO is not set
307CONFIG_INET_DIAG=y
308CONFIG_INET_TCP_DIAG=y
309# CONFIG_TCP_CONG_ADVANCED is not set
310CONFIG_TCP_CONG_CUBIC=y
311CONFIG_DEFAULT_TCP_CONG="cubic"
312# CONFIG_TCP_MD5SIG is not set
313# CONFIG_IPV6 is not set
314# CONFIG_INET6_XFRM_TUNNEL is not set
315# CONFIG_INET6_TUNNEL is not set
316# CONFIG_NETWORK_SECMARK is not set
317# CONFIG_NETFILTER is not set
318# CONFIG_IP_DCCP is not set
319# CONFIG_IP_SCTP is not set
320# CONFIG_TIPC is not set
321# CONFIG_ATM is not set
322# CONFIG_BRIDGE is not set
323# CONFIG_VLAN_8021Q is not set
324# CONFIG_DECNET is not set
325# CONFIG_LLC2 is not set
326# CONFIG_IPX is not set
327# CONFIG_ATALK is not set
328# CONFIG_X25 is not set
329# CONFIG_LAPB is not set
330# CONFIG_ECONET is not set
331# CONFIG_WAN_ROUTER is not set
332# CONFIG_NET_SCHED is not set
333
334#
335# Network testing
336#
337# CONFIG_NET_PKTGEN is not set
338# CONFIG_HAMRADIO is not set
339# CONFIG_IRDA is not set
340# CONFIG_BT is not set
341# CONFIG_AF_RXRPC is not set
342
343#
344# Wireless
345#
346# CONFIG_CFG80211 is not set
347# CONFIG_WIRELESS_EXT is not set
348# CONFIG_MAC80211 is not set
349# CONFIG_IEEE80211 is not set
350# CONFIG_RFKILL is not set
351# CONFIG_NET_9P is not set
352
353#
354# Device Drivers
355#
356
357#
358# Generic Driver Options
359#
360CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
361# CONFIG_STANDALONE is not set
362# CONFIG_PREVENT_FIRMWARE_BUILD is not set
363CONFIG_FW_LOADER=y
364# CONFIG_DEBUG_DRIVER is not set
365# CONFIG_DEBUG_DEVRES is not set
366# CONFIG_SYS_HYPERVISOR is not set
367# CONFIG_CONNECTOR is not set
368# CONFIG_MTD is not set
369# CONFIG_PARPORT is not set
370# CONFIG_BLK_DEV is not set
371# CONFIG_MISC_DEVICES is not set
372# CONFIG_IDE is not set
373
374#
375# SCSI device support
376#
377# CONFIG_RAID_ATTRS is not set
378# CONFIG_SCSI is not set
379# CONFIG_SCSI_DMA is not set
380# CONFIG_SCSI_NETLINK is not set
381# CONFIG_ATA is not set
382# CONFIG_MD is not set
383CONFIG_NETDEVICES=y
384# CONFIG_NETDEVICES_MULTIQUEUE is not set
385# CONFIG_DUMMY is not set
386# CONFIG_BONDING is not set
387# CONFIG_MACVLAN is not set
388# CONFIG_EQUALIZER is not set
389# CONFIG_TUN is not set
390# CONFIG_VETH is not set
391# CONFIG_PHYLIB is not set
392CONFIG_NET_ETHERNET=y
393CONFIG_MII=y
394# CONFIG_AX88796 is not set
395CONFIG_SMC91X=y
396# CONFIG_DM9000 is not set
397# CONFIG_SMC911X is not set
398# CONFIG_IBM_NEW_EMAC_ZMII is not set
399# CONFIG_IBM_NEW_EMAC_RGMII is not set
400# CONFIG_IBM_NEW_EMAC_TAH is not set
401# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
402# CONFIG_B44 is not set
403# CONFIG_NETDEV_1000 is not set
404# CONFIG_NETDEV_10000 is not set
405
406#
407# Wireless LAN
408#
409# CONFIG_WLAN_PRE80211 is not set
410# CONFIG_WLAN_80211 is not set
411# CONFIG_WAN is not set
412# CONFIG_PPP is not set
413# CONFIG_SLIP is not set
414# CONFIG_SHAPER is not set
415# CONFIG_NETCONSOLE is not set
416# CONFIG_NETPOLL is not set
417# CONFIG_NET_POLL_CONTROLLER is not set
418# CONFIG_ISDN is not set
419
420#
421# Input device support
422#
423CONFIG_INPUT=y
424# CONFIG_INPUT_FF_MEMLESS is not set
425# CONFIG_INPUT_POLLDEV is not set
426
427#
428# Userland interfaces
429#
430CONFIG_INPUT_MOUSEDEV=y
431# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
432CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
433CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
434# CONFIG_INPUT_JOYDEV is not set
435# CONFIG_INPUT_EVDEV is not set
436# CONFIG_INPUT_EVBUG is not set
437
438#
439# Input Device Drivers
440#
441# CONFIG_INPUT_KEYBOARD is not set
442# CONFIG_INPUT_MOUSE is not set
443# CONFIG_INPUT_JOYSTICK is not set
444# CONFIG_INPUT_TABLET is not set
445# CONFIG_INPUT_TOUCHSCREEN is not set
446# CONFIG_INPUT_MISC is not set
447
448#
449# Hardware I/O ports
450#
451# CONFIG_SERIO is not set
452# CONFIG_GAMEPORT is not set
453
454#
455# Character devices
456#
457CONFIG_VT=y
458CONFIG_VT_CONSOLE=y
459CONFIG_HW_CONSOLE=y
460# CONFIG_VT_HW_CONSOLE_BINDING is not set
461# CONFIG_SERIAL_NONSTANDARD is not set
462
463#
464# Serial drivers
465#
466# CONFIG_SERIAL_8250 is not set
467
468#
469# Non-8250 serial port support
470#
471CONFIG_SERIAL_PXA=y
472CONFIG_SERIAL_PXA_CONSOLE=y
473CONFIG_SERIAL_CORE=y
474CONFIG_SERIAL_CORE_CONSOLE=y
475CONFIG_UNIX98_PTYS=y
476# CONFIG_LEGACY_PTYS is not set
477# CONFIG_IPMI_HANDLER is not set
478# CONFIG_HW_RANDOM is not set
479# CONFIG_NVRAM is not set
480# CONFIG_R3964 is not set
481# CONFIG_RAW_DRIVER is not set
482# CONFIG_TCG_TPM is not set
483# CONFIG_I2C is not set
484
485#
486# SPI support
487#
488# CONFIG_SPI is not set
489# CONFIG_SPI_MASTER is not set
490# CONFIG_W1 is not set
491# CONFIG_POWER_SUPPLY is not set
492# CONFIG_HWMON is not set
493# CONFIG_WATCHDOG is not set
494
495#
496# Sonics Silicon Backplane
497#
498CONFIG_SSB_POSSIBLE=y
499# CONFIG_SSB is not set
500
501#
502# Multifunction device drivers
503#
504# CONFIG_MFD_SM501 is not set
505
506#
507# Multimedia devices
508#
509# CONFIG_VIDEO_DEV is not set
510# CONFIG_DVB_CORE is not set
511# CONFIG_DAB is not set
512
513#
514# Graphics support
515#
516# CONFIG_VGASTATE is not set
517# CONFIG_VIDEO_OUTPUT_CONTROL is not set
518CONFIG_FB=y
519# CONFIG_FIRMWARE_EDID is not set
520# CONFIG_FB_DDC is not set
521CONFIG_FB_CFB_FILLRECT=y
522CONFIG_FB_CFB_COPYAREA=y
523CONFIG_FB_CFB_IMAGEBLIT=y
524# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
525# CONFIG_FB_SYS_FILLRECT is not set
526# CONFIG_FB_SYS_COPYAREA is not set
527# CONFIG_FB_SYS_IMAGEBLIT is not set
528# CONFIG_FB_SYS_FOPS is not set
529CONFIG_FB_DEFERRED_IO=y
530# CONFIG_FB_SVGALIB is not set
531# CONFIG_FB_MACMODES is not set
532# CONFIG_FB_BACKLIGHT is not set
533# CONFIG_FB_MODE_HELPERS is not set
534# CONFIG_FB_TILEBLITTING is not set
535
536#
537# Frame buffer hardware drivers
538#
539# CONFIG_FB_S1D13XXX is not set
540CONFIG_FB_PXA=y
541# CONFIG_FB_PXA_PARAMETERS is not set
542# CONFIG_FB_MBX is not set
543# CONFIG_FB_VIRTUAL is not set
544# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
545
546#
547# Display device support
548#
549# CONFIG_DISPLAY_SUPPORT is not set
550
551#
552# Console display driver support
553#
554# CONFIG_VGA_CONSOLE is not set
555CONFIG_DUMMY_CONSOLE=y
556CONFIG_FRAMEBUFFER_CONSOLE=y
557# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
558# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
559CONFIG_FONTS=y
560# CONFIG_FONT_8x8 is not set
561CONFIG_FONT_8x16=y
562# CONFIG_FONT_6x11 is not set
563# CONFIG_FONT_7x14 is not set
564# CONFIG_FONT_PEARL_8x8 is not set
565# CONFIG_FONT_ACORN_8x8 is not set
566# CONFIG_FONT_MINI_4x6 is not set
567# CONFIG_FONT_SUN8x16 is not set
568# CONFIG_FONT_SUN12x22 is not set
569# CONFIG_FONT_10x18 is not set
570CONFIG_LOGO=y
571CONFIG_LOGO_LINUX_MONO=y
572CONFIG_LOGO_LINUX_VGA16=y
573CONFIG_LOGO_LINUX_CLUT224=y
574
575#
576# Sound
577#
578# CONFIG_SOUND is not set
579# CONFIG_HID_SUPPORT is not set
580# CONFIG_USB_SUPPORT is not set
581# CONFIG_MMC is not set
582# CONFIG_NEW_LEDS is not set
583CONFIG_RTC_LIB=y
584# CONFIG_RTC_CLASS is not set
585
586#
587# File systems
588#
589# CONFIG_EXT2_FS is not set
590# CONFIG_EXT3_FS is not set
591# CONFIG_EXT4DEV_FS is not set
592# CONFIG_REISERFS_FS is not set
593# CONFIG_JFS_FS is not set
594CONFIG_FS_POSIX_ACL=y
595# CONFIG_XFS_FS is not set
596# CONFIG_GFS2_FS is not set
597# CONFIG_OCFS2_FS is not set
598# CONFIG_MINIX_FS is not set
599# CONFIG_ROMFS_FS is not set
600# CONFIG_INOTIFY is not set
601# CONFIG_QUOTA is not set
602# CONFIG_DNOTIFY is not set
603# CONFIG_AUTOFS_FS is not set
604# CONFIG_AUTOFS4_FS is not set
605# CONFIG_FUSE_FS is not set
606
607#
608# CD-ROM/DVD Filesystems
609#
610# CONFIG_ISO9660_FS is not set
611# CONFIG_UDF_FS is not set
612
613#
614# DOS/FAT/NT Filesystems
615#
616# CONFIG_MSDOS_FS is not set
617# CONFIG_VFAT_FS is not set
618# CONFIG_NTFS_FS is not set
619
620#
621# Pseudo filesystems
622#
623CONFIG_PROC_FS=y
624CONFIG_PROC_SYSCTL=y
625CONFIG_SYSFS=y
626# CONFIG_TMPFS is not set
627# CONFIG_HUGETLB_PAGE is not set
628# CONFIG_CONFIGFS_FS is not set
629
630#
631# Miscellaneous filesystems
632#
633# CONFIG_ADFS_FS is not set
634# CONFIG_AFFS_FS is not set
635# CONFIG_HFS_FS is not set
636# CONFIG_HFSPLUS_FS is not set
637# CONFIG_BEFS_FS is not set
638# CONFIG_BFS_FS is not set
639# CONFIG_EFS_FS is not set
640# CONFIG_CRAMFS is not set
641# CONFIG_VXFS_FS is not set
642# CONFIG_HPFS_FS is not set
643# CONFIG_QNX4FS_FS is not set
644# CONFIG_SYSV_FS is not set
645# CONFIG_UFS_FS is not set
646CONFIG_NETWORK_FILESYSTEMS=y
647CONFIG_NFS_FS=y
648CONFIG_NFS_V3=y
649CONFIG_NFS_V3_ACL=y
650CONFIG_NFS_V4=y
651CONFIG_NFS_DIRECTIO=y
652# CONFIG_NFSD is not set
653CONFIG_ROOT_NFS=y
654CONFIG_LOCKD=y
655CONFIG_LOCKD_V4=y
656CONFIG_NFS_ACL_SUPPORT=y
657CONFIG_NFS_COMMON=y
658CONFIG_SUNRPC=y
659CONFIG_SUNRPC_GSS=y
660# CONFIG_SUNRPC_BIND34 is not set
661CONFIG_RPCSEC_GSS_KRB5=y
662# CONFIG_RPCSEC_GSS_SPKM3 is not set
663# CONFIG_SMB_FS is not set
664# CONFIG_CIFS is not set
665# CONFIG_NCP_FS is not set
666# CONFIG_CODA_FS is not set
667# CONFIG_AFS_FS is not set
668
669#
670# Partition Types
671#
672# CONFIG_PARTITION_ADVANCED is not set
673CONFIG_MSDOS_PARTITION=y
674# CONFIG_NLS is not set
675# CONFIG_DLM is not set
676# CONFIG_INSTRUMENTATION is not set
677
678#
679# Kernel hacking
680#
681CONFIG_PRINTK_TIME=y
682CONFIG_ENABLE_WARN_DEPRECATED=y
683CONFIG_ENABLE_MUST_CHECK=y
684CONFIG_MAGIC_SYSRQ=y
685# CONFIG_UNUSED_SYMBOLS is not set
686# CONFIG_DEBUG_FS is not set
687# CONFIG_HEADERS_CHECK is not set
688CONFIG_DEBUG_KERNEL=y
689# CONFIG_DEBUG_SHIRQ is not set
690CONFIG_DETECT_SOFTLOCKUP=y
691CONFIG_SCHED_DEBUG=y
692# CONFIG_SCHEDSTATS is not set
693# CONFIG_TIMER_STATS is not set
694# CONFIG_DEBUG_SLAB is not set
695# CONFIG_DEBUG_PREEMPT is not set
696# CONFIG_DEBUG_RT_MUTEXES is not set
697# CONFIG_RT_MUTEX_TESTER is not set
698# CONFIG_DEBUG_SPINLOCK is not set
699# CONFIG_DEBUG_MUTEXES is not set
700# CONFIG_DEBUG_LOCK_ALLOC is not set
701# CONFIG_PROVE_LOCKING is not set
702# CONFIG_LOCK_STAT is not set
703# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
704# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
705# CONFIG_DEBUG_KOBJECT is not set
706CONFIG_DEBUG_BUGVERBOSE=y
707CONFIG_DEBUG_INFO=y
708# CONFIG_DEBUG_VM is not set
709# CONFIG_DEBUG_LIST is not set
710# CONFIG_DEBUG_SG is not set
711CONFIG_FRAME_POINTER=y
712CONFIG_FORCED_INLINING=y
713# CONFIG_BOOT_PRINTK_DELAY is not set
714# CONFIG_RCU_TORTURE_TEST is not set
715# CONFIG_FAULT_INJECTION is not set
716# CONFIG_SAMPLES is not set
717CONFIG_DEBUG_USER=y
718CONFIG_DEBUG_ERRORS=y
719CONFIG_DEBUG_LL=y
720# CONFIG_DEBUG_ICEDCC is not set
721
722#
723# Security options
724#
725# CONFIG_KEYS is not set
726# CONFIG_SECURITY is not set
727# CONFIG_SECURITY_FILE_CAPABILITIES is not set
728CONFIG_CRYPTO=y
729CONFIG_CRYPTO_ALGAPI=y
730CONFIG_CRYPTO_BLKCIPHER=y
731CONFIG_CRYPTO_MANAGER=y
732# CONFIG_CRYPTO_HMAC is not set
733# CONFIG_CRYPTO_XCBC is not set
734# CONFIG_CRYPTO_NULL is not set
735# CONFIG_CRYPTO_MD4 is not set
736CONFIG_CRYPTO_MD5=y
737# CONFIG_CRYPTO_SHA1 is not set
738# CONFIG_CRYPTO_SHA256 is not set
739# CONFIG_CRYPTO_SHA512 is not set
740# CONFIG_CRYPTO_WP512 is not set
741# CONFIG_CRYPTO_TGR192 is not set
742# CONFIG_CRYPTO_GF128MUL is not set
743# CONFIG_CRYPTO_ECB is not set
744CONFIG_CRYPTO_CBC=y
745# CONFIG_CRYPTO_PCBC is not set
746# CONFIG_CRYPTO_LRW is not set
747# CONFIG_CRYPTO_XTS is not set
748# CONFIG_CRYPTO_CRYPTD is not set
749CONFIG_CRYPTO_DES=y
750# CONFIG_CRYPTO_FCRYPT is not set
751# CONFIG_CRYPTO_BLOWFISH is not set
752# CONFIG_CRYPTO_TWOFISH is not set
753# CONFIG_CRYPTO_SERPENT is not set
754# CONFIG_CRYPTO_AES is not set
755# CONFIG_CRYPTO_CAST5 is not set
756# CONFIG_CRYPTO_CAST6 is not set
757# CONFIG_CRYPTO_TEA is not set
758# CONFIG_CRYPTO_ARC4 is not set
759# CONFIG_CRYPTO_KHAZAD is not set
760# CONFIG_CRYPTO_ANUBIS is not set
761# CONFIG_CRYPTO_SEED is not set
762# CONFIG_CRYPTO_DEFLATE is not set
763# CONFIG_CRYPTO_MICHAEL_MIC is not set
764# CONFIG_CRYPTO_CRC32C is not set
765# CONFIG_CRYPTO_CAMELLIA is not set
766# CONFIG_CRYPTO_TEST is not set
767# CONFIG_CRYPTO_AUTHENC is not set
768CONFIG_CRYPTO_HW=y
769
770#
771# Library routines
772#
773CONFIG_BITREVERSE=y
774CONFIG_CRC_CCITT=y
775# CONFIG_CRC16 is not set
776# CONFIG_CRC_ITU_T is not set
777CONFIG_CRC32=y
778# CONFIG_CRC7 is not set
779# CONFIG_LIBCRC32C is not set
780CONFIG_PLIST=y
781CONFIG_HAS_IOMEM=y
782CONFIG_HAS_IOPORT=y
783CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig
new file mode 100644
index 000000000000..17b9b2469570
--- /dev/null
+++ b/arch/arm/configs/pcm027_defconfig
@@ -0,0 +1,1096 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24-rc6
4# Fri Dec 21 10:52:09 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_ARCH_MTD_XIP=y
26CONFIG_VECTORS_BASE=0xffff0000
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28
29#
30# General setup
31#
32CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y
34CONFIG_LOCK_KERNEL=y
35CONFIG_INIT_ENV_ARG_LIMIT=32
36CONFIG_LOCALVERSION=""
37CONFIG_LOCALVERSION_AUTO=y
38# CONFIG_SWAP is not set
39CONFIG_SYSVIPC=y
40CONFIG_SYSVIPC_SYSCTL=y
41CONFIG_POSIX_MQUEUE=y
42CONFIG_BSD_PROCESS_ACCT=y
43# CONFIG_BSD_PROCESS_ACCT_V3 is not set
44# CONFIG_TASKSTATS is not set
45# CONFIG_USER_NS is not set
46# CONFIG_PID_NS is not set
47# CONFIG_AUDIT is not set
48CONFIG_IKCONFIG=y
49CONFIG_IKCONFIG_PROC=y
50CONFIG_LOG_BUF_SHIFT=14
51# CONFIG_CGROUPS is not set
52CONFIG_FAIR_GROUP_SCHED=y
53CONFIG_FAIR_USER_SCHED=y
54# CONFIG_FAIR_CGROUP_SCHED is not set
55CONFIG_SYSFS_DEPRECATED=y
56# CONFIG_RELAY is not set
57# CONFIG_BLK_DEV_INITRD is not set
58# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
59CONFIG_SYSCTL=y
60CONFIG_EMBEDDED=y
61CONFIG_UID16=y
62CONFIG_SYSCTL_SYSCALL=y
63# CONFIG_KALLSYMS is not set
64CONFIG_HOTPLUG=y
65CONFIG_PRINTK=y
66CONFIG_BUG=y
67CONFIG_ELF_CORE=y
68CONFIG_BASE_FULL=y
69CONFIG_FUTEX=y
70CONFIG_ANON_INODES=y
71CONFIG_EPOLL=y
72CONFIG_SIGNALFD=y
73CONFIG_EVENTFD=y
74CONFIG_SHMEM=y
75CONFIG_VM_EVENT_COUNTERS=y
76CONFIG_SLAB=y
77# CONFIG_SLUB is not set
78# CONFIG_SLOB is not set
79CONFIG_RT_MUTEXES=y
80# CONFIG_TINY_SHMEM is not set
81CONFIG_BASE_SMALL=0
82CONFIG_MODULES=y
83CONFIG_MODULE_UNLOAD=y
84CONFIG_MODULE_FORCE_UNLOAD=y
85# CONFIG_MODVERSIONS is not set
86# CONFIG_MODULE_SRCVERSION_ALL is not set
87# CONFIG_KMOD is not set
88CONFIG_BLOCK=y
89# CONFIG_LBD is not set
90# CONFIG_BLK_DEV_IO_TRACE is not set
91# CONFIG_LSF is not set
92# CONFIG_BLK_DEV_BSG is not set
93
94#
95# IO Schedulers
96#
97CONFIG_IOSCHED_NOOP=y
98# CONFIG_IOSCHED_AS is not set
99# CONFIG_IOSCHED_DEADLINE is not set
100# CONFIG_IOSCHED_CFQ is not set
101# CONFIG_DEFAULT_AS is not set
102# CONFIG_DEFAULT_DEADLINE is not set
103# CONFIG_DEFAULT_CFQ is not set
104CONFIG_DEFAULT_NOOP=y
105CONFIG_DEFAULT_IOSCHED="noop"
106
107#
108# System Type
109#
110# CONFIG_ARCH_AAEC2000 is not set
111# CONFIG_ARCH_INTEGRATOR is not set
112# CONFIG_ARCH_REALVIEW is not set
113# CONFIG_ARCH_VERSATILE is not set
114# CONFIG_ARCH_AT91 is not set
115# CONFIG_ARCH_CLPS7500 is not set
116# CONFIG_ARCH_CLPS711X is not set
117# CONFIG_ARCH_CO285 is not set
118# CONFIG_ARCH_EBSA110 is not set
119# CONFIG_ARCH_EP93XX is not set
120# CONFIG_ARCH_FOOTBRIDGE is not set
121# CONFIG_ARCH_NETX is not set
122# CONFIG_ARCH_H720X is not set
123# CONFIG_ARCH_IMX is not set
124# CONFIG_ARCH_IOP13XX is not set
125# CONFIG_ARCH_IOP32X is not set
126# CONFIG_ARCH_IOP33X is not set
127# CONFIG_ARCH_IXP23XX is not set
128# CONFIG_ARCH_IXP2000 is not set
129# CONFIG_ARCH_IXP4XX is not set
130# CONFIG_ARCH_L7200 is not set
131# CONFIG_ARCH_KS8695 is not set
132# CONFIG_ARCH_NS9XXX is not set
133# CONFIG_ARCH_MXC is not set
134# CONFIG_ARCH_PNX4008 is not set
135CONFIG_ARCH_PXA=y
136# CONFIG_ARCH_RPC is not set
137# CONFIG_ARCH_SA1100 is not set
138# CONFIG_ARCH_S3C2410 is not set
139# CONFIG_ARCH_SHARK is not set
140# CONFIG_ARCH_LH7A40X is not set
141# CONFIG_ARCH_DAVINCI is not set
142# CONFIG_ARCH_OMAP is not set
143
144#
145# Intel PXA2xx/PXA3xx Implementations
146#
147# CONFIG_ARCH_LUBBOCK is not set
148# CONFIG_MACH_LOGICPD_PXA270 is not set
149# CONFIG_MACH_MAINSTONE is not set
150# CONFIG_ARCH_PXA_IDP is not set
151# CONFIG_PXA_SHARPSL is not set
152# CONFIG_MACH_TRIZEPS4 is not set
153# CONFIG_MACH_EM_X270 is not set
154# CONFIG_MACH_ZYLONITE is not set
155# CONFIG_MACH_ARMCORE is not set
156CONFIG_MACH_PCM027=y
157CONFIG_MACH_PCM990_BASEBOARD=y
158CONFIG_PXA27x=y
159
160#
161# Boot options
162#
163
164#
165# Power management
166#
167
168#
169# Processor Type
170#
171CONFIG_CPU_32=y
172CONFIG_CPU_XSCALE=y
173CONFIG_CPU_32v5=y
174CONFIG_CPU_ABRT_EV5T=y
175CONFIG_CPU_CACHE_VIVT=y
176CONFIG_CPU_TLB_V4WBI=y
177CONFIG_CPU_CP15=y
178CONFIG_CPU_CP15_MMU=y
179
180#
181# Processor Features
182#
183CONFIG_ARM_THUMB=y
184# CONFIG_CPU_DCACHE_DISABLE is not set
185# CONFIG_OUTER_CACHE is not set
186CONFIG_IWMMXT=y
187CONFIG_XSCALE_PMU=y
188
189#
190# Bus support
191#
192# CONFIG_PCI_SYSCALL is not set
193# CONFIG_ARCH_SUPPORTS_MSI is not set
194# CONFIG_PCCARD is not set
195
196#
197# Kernel Features
198#
199CONFIG_TICK_ONESHOT=y
200CONFIG_NO_HZ=y
201CONFIG_HIGH_RES_TIMERS=y
202CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
203CONFIG_PREEMPT=y
204CONFIG_HZ=100
205CONFIG_AEABI=y
206# CONFIG_OABI_COMPAT is not set
207# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
208CONFIG_SELECT_MEMORY_MODEL=y
209CONFIG_FLATMEM_MANUAL=y
210# CONFIG_DISCONTIGMEM_MANUAL is not set
211# CONFIG_SPARSEMEM_MANUAL is not set
212CONFIG_FLATMEM=y
213CONFIG_FLAT_NODE_MEM_MAP=y
214# CONFIG_SPARSEMEM_STATIC is not set
215# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
216CONFIG_SPLIT_PTLOCK_CPUS=4096
217# CONFIG_RESOURCES_64BIT is not set
218CONFIG_ZONE_DMA_FLAG=1
219CONFIG_BOUNCE=y
220CONFIG_VIRT_TO_BUS=y
221CONFIG_ALIGNMENT_TRAP=y
222
223#
224# Boot options
225#
226CONFIG_ZBOOT_ROM_TEXT=0x0
227CONFIG_ZBOOT_ROM_BSS=0x0
228CONFIG_CMDLINE=""
229# CONFIG_XIP_KERNEL is not set
230# CONFIG_KEXEC is not set
231
232#
233# Floating point emulation
234#
235
236#
237# At least one emulation must be selected
238#
239
240#
241# Userspace binary formats
242#
243CONFIG_BINFMT_ELF=y
244# CONFIG_BINFMT_AOUT is not set
245# CONFIG_BINFMT_MISC is not set
246
247#
248# Power management options
249#
250# CONFIG_PM is not set
251CONFIG_SUSPEND_UP_POSSIBLE=y
252
253#
254# Networking
255#
256CONFIG_NET=y
257
258#
259# Networking options
260#
261CONFIG_PACKET=y
262CONFIG_PACKET_MMAP=y
263CONFIG_UNIX=y
264# CONFIG_NET_KEY is not set
265CONFIG_INET=y
266# CONFIG_IP_MULTICAST is not set
267# CONFIG_IP_ADVANCED_ROUTER is not set
268CONFIG_IP_FIB_HASH=y
269CONFIG_IP_PNP=y
270# CONFIG_IP_PNP_DHCP is not set
271# CONFIG_IP_PNP_BOOTP is not set
272# CONFIG_IP_PNP_RARP is not set
273# CONFIG_NET_IPIP is not set
274# CONFIG_NET_IPGRE is not set
275# CONFIG_ARPD is not set
276# CONFIG_SYN_COOKIES is not set
277# CONFIG_INET_AH is not set
278# CONFIG_INET_ESP is not set
279# CONFIG_INET_IPCOMP is not set
280# CONFIG_INET_XFRM_TUNNEL is not set
281# CONFIG_INET_TUNNEL is not set
282# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
283# CONFIG_INET_XFRM_MODE_TUNNEL is not set
284# CONFIG_INET_XFRM_MODE_BEET is not set
285# CONFIG_INET_LRO is not set
286# CONFIG_INET_DIAG is not set
287# CONFIG_TCP_CONG_ADVANCED is not set
288CONFIG_TCP_CONG_CUBIC=y
289CONFIG_DEFAULT_TCP_CONG="cubic"
290# CONFIG_TCP_MD5SIG is not set
291# CONFIG_IPV6 is not set
292# CONFIG_INET6_XFRM_TUNNEL is not set
293# CONFIG_INET6_TUNNEL is not set
294# CONFIG_NETWORK_SECMARK is not set
295# CONFIG_NETFILTER is not set
296# CONFIG_IP_DCCP is not set
297# CONFIG_IP_SCTP is not set
298# CONFIG_TIPC is not set
299# CONFIG_ATM is not set
300# CONFIG_BRIDGE is not set
301# CONFIG_VLAN_8021Q is not set
302# CONFIG_DECNET is not set
303# CONFIG_LLC2 is not set
304# CONFIG_IPX is not set
305# CONFIG_ATALK is not set
306# CONFIG_X25 is not set
307# CONFIG_LAPB is not set
308# CONFIG_ECONET is not set
309# CONFIG_WAN_ROUTER is not set
310# CONFIG_NET_SCHED is not set
311
312#
313# Network testing
314#
315# CONFIG_NET_PKTGEN is not set
316# CONFIG_HAMRADIO is not set
317# CONFIG_IRDA is not set
318# CONFIG_BT is not set
319# CONFIG_AF_RXRPC is not set
320
321#
322# Wireless
323#
324# CONFIG_CFG80211 is not set
325# CONFIG_WIRELESS_EXT is not set
326# CONFIG_MAC80211 is not set
327# CONFIG_IEEE80211 is not set
328# CONFIG_RFKILL is not set
329# CONFIG_NET_9P is not set
330
331#
332# Device Drivers
333#
334
335#
336# Generic Driver Options
337#
338CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
339CONFIG_STANDALONE=y
340CONFIG_PREVENT_FIRMWARE_BUILD=y
341CONFIG_FW_LOADER=y
342# CONFIG_SYS_HYPERVISOR is not set
343# CONFIG_CONNECTOR is not set
344CONFIG_MTD=y
345# CONFIG_MTD_DEBUG is not set
346# CONFIG_MTD_CONCAT is not set
347CONFIG_MTD_PARTITIONS=y
348# CONFIG_MTD_REDBOOT_PARTS is not set
349CONFIG_MTD_CMDLINE_PARTS=y
350# CONFIG_MTD_AFS_PARTS is not set
351
352#
353# User Modules And Translation Layers
354#
355CONFIG_MTD_CHAR=y
356CONFIG_MTD_BLKDEVS=y
357CONFIG_MTD_BLOCK=y
358# CONFIG_FTL is not set
359# CONFIG_NFTL is not set
360# CONFIG_INFTL is not set
361# CONFIG_RFD_FTL is not set
362# CONFIG_SSFDC is not set
363# CONFIG_MTD_OOPS is not set
364
365#
366# RAM/ROM/Flash chip drivers
367#
368CONFIG_MTD_CFI=y
369# CONFIG_MTD_JEDECPROBE is not set
370CONFIG_MTD_GEN_PROBE=y
371# CONFIG_MTD_CFI_ADV_OPTIONS is not set
372CONFIG_MTD_MAP_BANK_WIDTH_1=y
373CONFIG_MTD_MAP_BANK_WIDTH_2=y
374CONFIG_MTD_MAP_BANK_WIDTH_4=y
375# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
376# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
377# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
378CONFIG_MTD_CFI_I1=y
379CONFIG_MTD_CFI_I2=y
380# CONFIG_MTD_CFI_I4 is not set
381# CONFIG_MTD_CFI_I8 is not set
382CONFIG_MTD_CFI_INTELEXT=y
383# CONFIG_MTD_CFI_AMDSTD is not set
384# CONFIG_MTD_CFI_STAA is not set
385CONFIG_MTD_CFI_UTIL=y
386# CONFIG_MTD_RAM is not set
387# CONFIG_MTD_ROM is not set
388# CONFIG_MTD_ABSENT is not set
389# CONFIG_MTD_XIP is not set
390
391#
392# Mapping drivers for chip access
393#
394# CONFIG_MTD_COMPLEX_MAPPINGS is not set
395CONFIG_MTD_PHYSMAP=y
396CONFIG_MTD_PHYSMAP_START=0x00000000
397CONFIG_MTD_PHYSMAP_LEN=0x0
398CONFIG_MTD_PHYSMAP_BANKWIDTH=0
399# CONFIG_MTD_PXA2XX is not set
400# CONFIG_MTD_ARM_INTEGRATOR is not set
401# CONFIG_MTD_SHARP_SL is not set
402# CONFIG_MTD_PLATRAM is not set
403
404#
405# Self-contained MTD device drivers
406#
407# CONFIG_MTD_SLRAM is not set
408# CONFIG_MTD_PHRAM is not set
409# CONFIG_MTD_MTDRAM is not set
410# CONFIG_MTD_BLOCK2MTD is not set
411
412#
413# Disk-On-Chip Device Drivers
414#
415# CONFIG_MTD_DOC2000 is not set
416# CONFIG_MTD_DOC2001 is not set
417# CONFIG_MTD_DOC2001PLUS is not set
418# CONFIG_MTD_NAND is not set
419# CONFIG_MTD_ONENAND is not set
420
421#
422# UBI - Unsorted block images
423#
424# CONFIG_MTD_UBI is not set
425# CONFIG_PARPORT is not set
426# CONFIG_BLK_DEV is not set
427# CONFIG_MISC_DEVICES is not set
428# CONFIG_IDE is not set
429
430#
431# SCSI device support
432#
433# CONFIG_RAID_ATTRS is not set
434CONFIG_SCSI=y
435CONFIG_SCSI_DMA=y
436# CONFIG_SCSI_TGT is not set
437# CONFIG_SCSI_NETLINK is not set
438CONFIG_SCSI_PROC_FS=y
439
440#
441# SCSI support type (disk, tape, CD-ROM)
442#
443CONFIG_BLK_DEV_SD=y
444# CONFIG_CHR_DEV_ST is not set
445# CONFIG_CHR_DEV_OSST is not set
446# CONFIG_BLK_DEV_SR is not set
447# CONFIG_CHR_DEV_SG is not set
448# CONFIG_CHR_DEV_SCH is not set
449
450#
451# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
452#
453# CONFIG_SCSI_MULTI_LUN is not set
454# CONFIG_SCSI_CONSTANTS is not set
455# CONFIG_SCSI_LOGGING is not set
456# CONFIG_SCSI_SCAN_ASYNC is not set
457CONFIG_SCSI_WAIT_SCAN=m
458
459#
460# SCSI Transports
461#
462# CONFIG_SCSI_SPI_ATTRS is not set
463# CONFIG_SCSI_FC_ATTRS is not set
464# CONFIG_SCSI_ISCSI_ATTRS is not set
465# CONFIG_SCSI_SAS_LIBSAS is not set
466# CONFIG_SCSI_SRP_ATTRS is not set
467# CONFIG_SCSI_LOWLEVEL is not set
468# CONFIG_ATA is not set
469# CONFIG_MD is not set
470CONFIG_NETDEVICES=y
471# CONFIG_NETDEVICES_MULTIQUEUE is not set
472# CONFIG_DUMMY is not set
473# CONFIG_BONDING is not set
474# CONFIG_MACVLAN is not set
475# CONFIG_EQUALIZER is not set
476# CONFIG_TUN is not set
477# CONFIG_VETH is not set
478# CONFIG_PHYLIB is not set
479CONFIG_NET_ETHERNET=y
480CONFIG_MII=y
481# CONFIG_AX88796 is not set
482CONFIG_SMC91X=y
483# CONFIG_DM9000 is not set
484# CONFIG_SMC911X is not set
485# CONFIG_IBM_NEW_EMAC_ZMII is not set
486# CONFIG_IBM_NEW_EMAC_RGMII is not set
487# CONFIG_IBM_NEW_EMAC_TAH is not set
488# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
489# CONFIG_B44 is not set
490# CONFIG_NETDEV_1000 is not set
491# CONFIG_NETDEV_10000 is not set
492
493#
494# Wireless LAN
495#
496# CONFIG_WLAN_PRE80211 is not set
497# CONFIG_WLAN_80211 is not set
498
499#
500# USB Network Adapters
501#
502# CONFIG_USB_CATC is not set
503# CONFIG_USB_KAWETH is not set
504# CONFIG_USB_PEGASUS is not set
505# CONFIG_USB_RTL8150 is not set
506# CONFIG_USB_USBNET is not set
507# CONFIG_WAN is not set
508# CONFIG_PPP is not set
509# CONFIG_SLIP is not set
510# CONFIG_SHAPER is not set
511# CONFIG_NETCONSOLE is not set
512# CONFIG_NETPOLL is not set
513# CONFIG_NET_POLL_CONTROLLER is not set
514# CONFIG_ISDN is not set
515
516#
517# Input device support
518#
519CONFIG_INPUT=y
520# CONFIG_INPUT_FF_MEMLESS is not set
521# CONFIG_INPUT_POLLDEV is not set
522
523#
524# Userland interfaces
525#
526CONFIG_INPUT_MOUSEDEV=y
527# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
528CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
529CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
530# CONFIG_INPUT_JOYDEV is not set
531# CONFIG_INPUT_EVDEV is not set
532# CONFIG_INPUT_EVBUG is not set
533
534#
535# Input Device Drivers
536#
537# CONFIG_INPUT_KEYBOARD is not set
538# CONFIG_INPUT_MOUSE is not set
539# CONFIG_INPUT_JOYSTICK is not set
540# CONFIG_INPUT_TABLET is not set
541# CONFIG_INPUT_TOUCHSCREEN is not set
542# CONFIG_INPUT_MISC is not set
543
544#
545# Hardware I/O ports
546#
547# CONFIG_SERIO is not set
548# CONFIG_GAMEPORT is not set
549
550#
551# Character devices
552#
553CONFIG_VT=y
554CONFIG_VT_CONSOLE=y
555CONFIG_HW_CONSOLE=y
556# CONFIG_VT_HW_CONSOLE_BINDING is not set
557# CONFIG_SERIAL_NONSTANDARD is not set
558
559#
560# Serial drivers
561#
562# CONFIG_SERIAL_8250 is not set
563
564#
565# Non-8250 serial port support
566#
567CONFIG_SERIAL_PXA=y
568CONFIG_SERIAL_PXA_CONSOLE=y
569CONFIG_SERIAL_CORE=y
570CONFIG_SERIAL_CORE_CONSOLE=y
571CONFIG_UNIX98_PTYS=y
572# CONFIG_LEGACY_PTYS is not set
573# CONFIG_IPMI_HANDLER is not set
574# CONFIG_HW_RANDOM is not set
575# CONFIG_NVRAM is not set
576# CONFIG_R3964 is not set
577# CONFIG_RAW_DRIVER is not set
578# CONFIG_TCG_TPM is not set
579CONFIG_I2C=y
580CONFIG_I2C_BOARDINFO=y
581CONFIG_I2C_CHARDEV=y
582
583#
584# I2C Algorithms
585#
586# CONFIG_I2C_ALGOBIT is not set
587# CONFIG_I2C_ALGOPCF is not set
588# CONFIG_I2C_ALGOPCA is not set
589
590#
591# I2C Hardware Bus support
592#
593# CONFIG_I2C_GPIO is not set
594CONFIG_I2C_PXA=y
595# CONFIG_I2C_PXA_SLAVE is not set
596# CONFIG_I2C_OCORES is not set
597# CONFIG_I2C_PARPORT_LIGHT is not set
598# CONFIG_I2C_SIMTEC is not set
599# CONFIG_I2C_TAOS_EVM is not set
600# CONFIG_I2C_STUB is not set
601# CONFIG_I2C_TINY_USB is not set
602
603#
604# Miscellaneous I2C Chip support
605#
606# CONFIG_SENSORS_DS1337 is not set
607# CONFIG_SENSORS_DS1374 is not set
608# CONFIG_DS1682 is not set
609CONFIG_SENSORS_EEPROM=y
610# CONFIG_SENSORS_PCF8574 is not set
611# CONFIG_SENSORS_PCA9539 is not set
612# CONFIG_SENSORS_PCF8591 is not set
613# CONFIG_SENSORS_MAX6875 is not set
614# CONFIG_SENSORS_TSL2550 is not set
615# CONFIG_I2C_DEBUG_CORE is not set
616# CONFIG_I2C_DEBUG_ALGO is not set
617# CONFIG_I2C_DEBUG_BUS is not set
618# CONFIG_I2C_DEBUG_CHIP is not set
619
620#
621# SPI support
622#
623# CONFIG_SPI is not set
624# CONFIG_SPI_MASTER is not set
625# CONFIG_W1 is not set
626# CONFIG_POWER_SUPPLY is not set
627# CONFIG_HWMON is not set
628# CONFIG_WATCHDOG is not set
629
630#
631# Sonics Silicon Backplane
632#
633CONFIG_SSB_POSSIBLE=y
634# CONFIG_SSB is not set
635
636#
637# Multifunction device drivers
638#
639# CONFIG_MFD_SM501 is not set
640
641#
642# Multimedia devices
643#
644# CONFIG_VIDEO_DEV is not set
645# CONFIG_DVB_CORE is not set
646# CONFIG_DAB is not set
647
648#
649# Graphics support
650#
651# CONFIG_VGASTATE is not set
652# CONFIG_VIDEO_OUTPUT_CONTROL is not set
653# CONFIG_FB is not set
654# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
655
656#
657# Display device support
658#
659# CONFIG_DISPLAY_SUPPORT is not set
660
661#
662# Console display driver support
663#
664# CONFIG_VGA_CONSOLE is not set
665CONFIG_DUMMY_CONSOLE=y
666
667#
668# Sound
669#
670CONFIG_SOUND=y
671
672#
673# Advanced Linux Sound Architecture
674#
675CONFIG_SND=y
676CONFIG_SND_TIMER=y
677CONFIG_SND_PCM=y
678# CONFIG_SND_SEQUENCER is not set
679CONFIG_SND_OSSEMUL=y
680CONFIG_SND_MIXER_OSS=y
681CONFIG_SND_PCM_OSS=y
682CONFIG_SND_PCM_OSS_PLUGINS=y
683# CONFIG_SND_DYNAMIC_MINORS is not set
684CONFIG_SND_SUPPORT_OLD_API=y
685CONFIG_SND_VERBOSE_PROCFS=y
686# CONFIG_SND_VERBOSE_PRINTK is not set
687# CONFIG_SND_DEBUG is not set
688
689#
690# Generic devices
691#
692CONFIG_SND_AC97_CODEC=y
693# CONFIG_SND_DUMMY is not set
694# CONFIG_SND_MTPAV is not set
695# CONFIG_SND_SERIAL_U16550 is not set
696# CONFIG_SND_MPU401 is not set
697
698#
699# ALSA ARM devices
700#
701CONFIG_SND_PXA2XX_PCM=y
702CONFIG_SND_PXA2XX_AC97=y
703
704#
705# USB devices
706#
707# CONFIG_SND_USB_AUDIO is not set
708# CONFIG_SND_USB_CAIAQ is not set
709
710#
711# System on Chip audio support
712#
713# CONFIG_SND_SOC is not set
714
715#
716# SoC Audio support for SuperH
717#
718
719#
720# Open Sound System
721#
722# CONFIG_SOUND_PRIME is not set
723CONFIG_AC97_BUS=y
724# CONFIG_HID_SUPPORT is not set
725CONFIG_USB_SUPPORT=y
726CONFIG_USB_ARCH_HAS_HCD=y
727CONFIG_USB_ARCH_HAS_OHCI=y
728# CONFIG_USB_ARCH_HAS_EHCI is not set
729CONFIG_USB=y
730# CONFIG_USB_DEBUG is not set
731
732#
733# Miscellaneous USB options
734#
735CONFIG_USB_DEVICEFS=y
736CONFIG_USB_DEVICE_CLASS=y
737# CONFIG_USB_DYNAMIC_MINORS is not set
738# CONFIG_USB_OTG is not set
739
740#
741# USB Host Controller Drivers
742#
743# CONFIG_USB_ISP116X_HCD is not set
744CONFIG_USB_OHCI_HCD=y
745# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
746# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
747CONFIG_USB_OHCI_LITTLE_ENDIAN=y
748# CONFIG_USB_SL811_HCD is not set
749# CONFIG_USB_R8A66597_HCD is not set
750
751#
752# USB Device Class drivers
753#
754# CONFIG_USB_ACM is not set
755# CONFIG_USB_PRINTER is not set
756
757#
758# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
759#
760
761#
762# may also be needed; see USB_STORAGE Help for more information
763#
764CONFIG_USB_STORAGE=y
765# CONFIG_USB_STORAGE_DEBUG is not set
766# CONFIG_USB_STORAGE_DATAFAB is not set
767# CONFIG_USB_STORAGE_FREECOM is not set
768# CONFIG_USB_STORAGE_ISD200 is not set
769# CONFIG_USB_STORAGE_DPCM is not set
770# CONFIG_USB_STORAGE_USBAT is not set
771# CONFIG_USB_STORAGE_SDDR09 is not set
772# CONFIG_USB_STORAGE_SDDR55 is not set
773# CONFIG_USB_STORAGE_JUMPSHOT is not set
774# CONFIG_USB_STORAGE_ALAUDA is not set
775# CONFIG_USB_STORAGE_KARMA is not set
776# CONFIG_USB_LIBUSUAL is not set
777
778#
779# USB Imaging devices
780#
781# CONFIG_USB_MDC800 is not set
782# CONFIG_USB_MICROTEK is not set
783# CONFIG_USB_MON is not set
784
785#
786# USB port drivers
787#
788
789#
790# USB Serial Converter support
791#
792# CONFIG_USB_SERIAL is not set
793
794#
795# USB Miscellaneous drivers
796#
797# CONFIG_USB_EMI62 is not set
798# CONFIG_USB_EMI26 is not set
799# CONFIG_USB_ADUTUX is not set
800# CONFIG_USB_AUERSWALD is not set
801# CONFIG_USB_RIO500 is not set
802# CONFIG_USB_LEGOTOWER is not set
803# CONFIG_USB_LCD is not set
804# CONFIG_USB_BERRY_CHARGE is not set
805# CONFIG_USB_LED is not set
806# CONFIG_USB_CYPRESS_CY7C63 is not set
807# CONFIG_USB_CYTHERM is not set
808# CONFIG_USB_PHIDGET is not set
809# CONFIG_USB_IDMOUSE is not set
810# CONFIG_USB_FTDI_ELAN is not set
811# CONFIG_USB_APPLEDISPLAY is not set
812# CONFIG_USB_LD is not set
813# CONFIG_USB_TRANCEVIBRATOR is not set
814# CONFIG_USB_IOWARRIOR is not set
815# CONFIG_USB_TEST is not set
816
817#
818# USB DSL modem support
819#
820
821#
822# USB Gadget Support
823#
824# CONFIG_USB_GADGET is not set
825CONFIG_MMC=y
826# CONFIG_MMC_DEBUG is not set
827# CONFIG_MMC_UNSAFE_RESUME is not set
828
829#
830# MMC/SD Card Drivers
831#
832CONFIG_MMC_BLOCK=y
833CONFIG_MMC_BLOCK_BOUNCE=y
834# CONFIG_SDIO_UART is not set
835
836#
837# MMC/SD Host Controller Drivers
838#
839CONFIG_MMC_PXA=y
840# CONFIG_NEW_LEDS is not set
841CONFIG_RTC_LIB=y
842CONFIG_RTC_CLASS=y
843CONFIG_RTC_HCTOSYS=y
844CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
845# CONFIG_RTC_DEBUG is not set
846
847#
848# RTC interfaces
849#
850CONFIG_RTC_INTF_SYSFS=y
851CONFIG_RTC_INTF_PROC=y
852CONFIG_RTC_INTF_DEV=y
853# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
854# CONFIG_RTC_DRV_TEST is not set
855
856#
857# I2C RTC drivers
858#
859# CONFIG_RTC_DRV_DS1307 is not set
860# CONFIG_RTC_DRV_DS1374 is not set
861# CONFIG_RTC_DRV_DS1672 is not set
862# CONFIG_RTC_DRV_MAX6900 is not set
863# CONFIG_RTC_DRV_RS5C372 is not set
864# CONFIG_RTC_DRV_ISL1208 is not set
865# CONFIG_RTC_DRV_X1205 is not set
866CONFIG_RTC_DRV_PCF8563=m
867# CONFIG_RTC_DRV_PCF8583 is not set
868# CONFIG_RTC_DRV_M41T80 is not set
869
870#
871# SPI RTC drivers
872#
873
874#
875# Platform RTC drivers
876#
877# CONFIG_RTC_DRV_CMOS is not set
878# CONFIG_RTC_DRV_DS1553 is not set
879# CONFIG_RTC_DRV_STK17TA8 is not set
880# CONFIG_RTC_DRV_DS1742 is not set
881# CONFIG_RTC_DRV_M48T86 is not set
882# CONFIG_RTC_DRV_M48T59 is not set
883# CONFIG_RTC_DRV_V3020 is not set
884
885#
886# on-CPU RTC drivers
887#
888CONFIG_RTC_DRV_SA1100=m
889
890#
891# File systems
892#
893CONFIG_EXT2_FS=m
894# CONFIG_EXT2_FS_XATTR is not set
895# CONFIG_EXT2_FS_XIP is not set
896CONFIG_EXT3_FS=m
897CONFIG_EXT3_FS_XATTR=y
898# CONFIG_EXT3_FS_POSIX_ACL is not set
899# CONFIG_EXT3_FS_SECURITY is not set
900# CONFIG_EXT4DEV_FS is not set
901CONFIG_JBD=m
902CONFIG_FS_MBCACHE=m
903# CONFIG_REISERFS_FS is not set
904# CONFIG_JFS_FS is not set
905# CONFIG_FS_POSIX_ACL is not set
906# CONFIG_XFS_FS is not set
907# CONFIG_GFS2_FS is not set
908# CONFIG_OCFS2_FS is not set
909# CONFIG_MINIX_FS is not set
910# CONFIG_ROMFS_FS is not set
911# CONFIG_INOTIFY is not set
912# CONFIG_QUOTA is not set
913# CONFIG_DNOTIFY is not set
914# CONFIG_AUTOFS_FS is not set
915# CONFIG_AUTOFS4_FS is not set
916# CONFIG_FUSE_FS is not set
917
918#
919# CD-ROM/DVD Filesystems
920#
921# CONFIG_ISO9660_FS is not set
922# CONFIG_UDF_FS is not set
923
924#
925# DOS/FAT/NT Filesystems
926#
927CONFIG_FAT_FS=m
928# CONFIG_MSDOS_FS is not set
929CONFIG_VFAT_FS=m
930CONFIG_FAT_DEFAULT_CODEPAGE=850
931CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
932# CONFIG_NTFS_FS is not set
933
934#
935# Pseudo filesystems
936#
937CONFIG_PROC_FS=y
938CONFIG_PROC_SYSCTL=y
939CONFIG_SYSFS=y
940CONFIG_TMPFS=y
941# CONFIG_TMPFS_POSIX_ACL is not set
942# CONFIG_HUGETLB_PAGE is not set
943# CONFIG_CONFIGFS_FS is not set
944
945#
946# Miscellaneous filesystems
947#
948# CONFIG_ADFS_FS is not set
949# CONFIG_AFFS_FS is not set
950# CONFIG_HFS_FS is not set
951# CONFIG_HFSPLUS_FS is not set
952# CONFIG_BEFS_FS is not set
953# CONFIG_BFS_FS is not set
954# CONFIG_EFS_FS is not set
955CONFIG_JFFS2_FS=y
956CONFIG_JFFS2_FS_DEBUG=0
957CONFIG_JFFS2_FS_WRITEBUFFER=y
958# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
959# CONFIG_JFFS2_SUMMARY is not set
960# CONFIG_JFFS2_FS_XATTR is not set
961# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
962CONFIG_JFFS2_ZLIB=y
963# CONFIG_JFFS2_LZO is not set
964CONFIG_JFFS2_RTIME=y
965# CONFIG_JFFS2_RUBIN is not set
966# CONFIG_CRAMFS is not set
967# CONFIG_VXFS_FS is not set
968# CONFIG_HPFS_FS is not set
969# CONFIG_QNX4FS_FS is not set
970# CONFIG_SYSV_FS is not set
971# CONFIG_UFS_FS is not set
972CONFIG_NETWORK_FILESYSTEMS=y
973CONFIG_NFS_FS=y
974CONFIG_NFS_V3=y
975# CONFIG_NFS_V3_ACL is not set
976# CONFIG_NFS_V4 is not set
977CONFIG_NFS_DIRECTIO=y
978# CONFIG_NFSD is not set
979CONFIG_ROOT_NFS=y
980CONFIG_LOCKD=y
981CONFIG_LOCKD_V4=y
982CONFIG_NFS_COMMON=y
983CONFIG_SUNRPC=y
984# CONFIG_SUNRPC_BIND34 is not set
985# CONFIG_RPCSEC_GSS_KRB5 is not set
986# CONFIG_RPCSEC_GSS_SPKM3 is not set
987# CONFIG_SMB_FS is not set
988# CONFIG_CIFS is not set
989# CONFIG_NCP_FS is not set
990# CONFIG_CODA_FS is not set
991# CONFIG_AFS_FS is not set
992
993#
994# Partition Types
995#
996CONFIG_PARTITION_ADVANCED=y
997# CONFIG_ACORN_PARTITION is not set
998# CONFIG_OSF_PARTITION is not set
999# CONFIG_AMIGA_PARTITION is not set
1000# CONFIG_ATARI_PARTITION is not set
1001# CONFIG_MAC_PARTITION is not set
1002CONFIG_MSDOS_PARTITION=y
1003# CONFIG_BSD_DISKLABEL is not set
1004# CONFIG_MINIX_SUBPARTITION is not set
1005# CONFIG_SOLARIS_X86_PARTITION is not set
1006# CONFIG_UNIXWARE_DISKLABEL is not set
1007# CONFIG_LDM_PARTITION is not set
1008# CONFIG_SGI_PARTITION is not set
1009# CONFIG_ULTRIX_PARTITION is not set
1010# CONFIG_SUN_PARTITION is not set
1011# CONFIG_KARMA_PARTITION is not set
1012# CONFIG_EFI_PARTITION is not set
1013# CONFIG_SYSV68_PARTITION is not set
1014CONFIG_NLS=y
1015CONFIG_NLS_DEFAULT="iso8859-15"
1016# CONFIG_NLS_CODEPAGE_437 is not set
1017# CONFIG_NLS_CODEPAGE_737 is not set
1018# CONFIG_NLS_CODEPAGE_775 is not set
1019CONFIG_NLS_CODEPAGE_850=y
1020# CONFIG_NLS_CODEPAGE_852 is not set
1021# CONFIG_NLS_CODEPAGE_855 is not set
1022# CONFIG_NLS_CODEPAGE_857 is not set
1023# CONFIG_NLS_CODEPAGE_860 is not set
1024# CONFIG_NLS_CODEPAGE_861 is not set
1025# CONFIG_NLS_CODEPAGE_862 is not set
1026# CONFIG_NLS_CODEPAGE_863 is not set
1027# CONFIG_NLS_CODEPAGE_864 is not set
1028# CONFIG_NLS_CODEPAGE_865 is not set
1029# CONFIG_NLS_CODEPAGE_866 is not set
1030# CONFIG_NLS_CODEPAGE_869 is not set
1031# CONFIG_NLS_CODEPAGE_936 is not set
1032# CONFIG_NLS_CODEPAGE_950 is not set
1033# CONFIG_NLS_CODEPAGE_932 is not set
1034# CONFIG_NLS_CODEPAGE_949 is not set
1035# CONFIG_NLS_CODEPAGE_874 is not set
1036# CONFIG_NLS_ISO8859_8 is not set
1037# CONFIG_NLS_CODEPAGE_1250 is not set
1038# CONFIG_NLS_CODEPAGE_1251 is not set
1039# CONFIG_NLS_ASCII is not set
1040# CONFIG_NLS_ISO8859_1 is not set
1041# CONFIG_NLS_ISO8859_2 is not set
1042# CONFIG_NLS_ISO8859_3 is not set
1043# CONFIG_NLS_ISO8859_4 is not set
1044# CONFIG_NLS_ISO8859_5 is not set
1045# CONFIG_NLS_ISO8859_6 is not set
1046# CONFIG_NLS_ISO8859_7 is not set
1047# CONFIG_NLS_ISO8859_9 is not set
1048# CONFIG_NLS_ISO8859_13 is not set
1049# CONFIG_NLS_ISO8859_14 is not set
1050CONFIG_NLS_ISO8859_15=y
1051# CONFIG_NLS_KOI8_R is not set
1052# CONFIG_NLS_KOI8_U is not set
1053# CONFIG_NLS_UTF8 is not set
1054# CONFIG_DLM is not set
1055# CONFIG_INSTRUMENTATION is not set
1056
1057#
1058# Kernel hacking
1059#
1060# CONFIG_PRINTK_TIME is not set
1061CONFIG_ENABLE_WARN_DEPRECATED=y
1062CONFIG_ENABLE_MUST_CHECK=y
1063CONFIG_MAGIC_SYSRQ=y
1064# CONFIG_UNUSED_SYMBOLS is not set
1065# CONFIG_DEBUG_FS is not set
1066# CONFIG_HEADERS_CHECK is not set
1067# CONFIG_DEBUG_KERNEL is not set
1068# CONFIG_DEBUG_BUGVERBOSE is not set
1069CONFIG_FRAME_POINTER=y
1070# CONFIG_SAMPLES is not set
1071# CONFIG_DEBUG_USER is not set
1072
1073#
1074# Security options
1075#
1076# CONFIG_KEYS is not set
1077# CONFIG_SECURITY is not set
1078# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1079# CONFIG_CRYPTO is not set
1080
1081#
1082# Library routines
1083#
1084CONFIG_BITREVERSE=y
1085# CONFIG_CRC_CCITT is not set
1086# CONFIG_CRC16 is not set
1087# CONFIG_CRC_ITU_T is not set
1088CONFIG_CRC32=y
1089# CONFIG_CRC7 is not set
1090# CONFIG_LIBCRC32C is not set
1091CONFIG_ZLIB_INFLATE=y
1092CONFIG_ZLIB_DEFLATE=y
1093CONFIG_PLIST=y
1094CONFIG_HAS_IOMEM=y
1095CONFIG_HAS_IOPORT=y
1096CONFIG_HAS_DMA=y
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index d5f6ea14fc7b..f550b19e1ecd 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -76,7 +76,7 @@ static struct resource smc91x_resources[] = {
76 [1] = { 76 [1] = {
77 .start = INT_730_MPU_EXT_NIRQ, 77 .start = INT_730_MPU_EXT_NIRQ,
78 .end = 0, 78 .end = 0,
79 .flags = IORESOURCE_IRQ, 79 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
80 }, 80 },
81}; 81};
82 82
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 9393824cc150..bfa04fa25524 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -209,7 +209,7 @@ static struct resource h2_smc91x_resources[] = {
209 [1] = { 209 [1] = {
210 .start = OMAP_GPIO_IRQ(0), 210 .start = OMAP_GPIO_IRQ(0),
211 .end = OMAP_GPIO_IRQ(0), 211 .end = OMAP_GPIO_IRQ(0),
212 .flags = IORESOURCE_IRQ, 212 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
213 }, 213 },
214}; 214};
215 215
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 978cdab16535..056519860565 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -208,7 +208,7 @@ static struct resource smc91x_resources[] = {
208 [1] = { 208 [1] = {
209 .start = OMAP_GPIO_IRQ(40), 209 .start = OMAP_GPIO_IRQ(40),
210 .end = OMAP_GPIO_IRQ(40), 210 .end = OMAP_GPIO_IRQ(40),
211 .flags = IORESOURCE_IRQ, 211 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
212 }, 212 },
213}; 213};
214 214
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 7e63a41e37c6..7d2d8af155a3 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -202,7 +202,7 @@ static struct resource innovator1510_smc91x_resources[] = {
202 [1] = { 202 [1] = {
203 .start = OMAP1510_INT_ETHER, 203 .start = OMAP1510_INT_ETHER,
204 .end = OMAP1510_INT_ETHER, 204 .end = OMAP1510_INT_ETHER,
205 .flags = IORESOURCE_IRQ, 205 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
206 }, 206 },
207}; 207};
208 208
@@ -269,7 +269,7 @@ static struct resource innovator1610_smc91x_resources[] = {
269 [1] = { 269 [1] = {
270 .start = OMAP_GPIO_IRQ(0), 270 .start = OMAP_GPIO_IRQ(0),
271 .end = OMAP_GPIO_IRQ(0), 271 .end = OMAP_GPIO_IRQ(0),
272 .flags = IORESOURCE_IRQ, 272 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
273 }, 273 },
274}; 274};
275 275
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 4e016179f312..84333440008c 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -111,7 +111,7 @@ static struct resource osk5912_smc91x_resources[] = {
111 [1] = { 111 [1] = {
112 .start = OMAP_GPIO_IRQ(0), 112 .start = OMAP_GPIO_IRQ(0),
113 .end = OMAP_GPIO_IRQ(0), 113 .end = OMAP_GPIO_IRQ(0),
114 .flags = IORESOURCE_IRQ, 114 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
115 }, 115 },
116}; 116};
117 117
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index e44437e10eef..534dcfb9d263 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -75,7 +75,7 @@ static struct resource smc91x_resources[] = {
75 [1] = { 75 [1] = {
76 .start = INT_730_MPU_EXT_NIRQ, 76 .start = INT_730_MPU_EXT_NIRQ,
77 .end = 0, 77 .end = 0,
78 .flags = IORESOURCE_IRQ, 78 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
79 }, 79 },
80}; 80};
81 81
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 214dd19889ac..c82a1cd20ad4 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -117,7 +117,7 @@ static struct resource voiceblue_smc91x_resources[] = {
117 [1] = { 117 [1] = {
118 .start = OMAP_GPIO_IRQ(8), 118 .start = OMAP_GPIO_IRQ(8),
119 .end = OMAP_GPIO_IRQ(8), 119 .end = OMAP_GPIO_IRQ(8),
120 .flags = IORESOURCE_IRQ, 120 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
121 }, 121 },
122}; 122};
123 123
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 7e76fbf19b5d..64235dee5614 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -104,7 +104,7 @@ static struct resource sdp2430_smc91x_resources[] = {
104 [1] = { 104 [1] = {
105 .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), 105 .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
106 .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), 106 .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
107 .flags = IORESOURCE_IRQ, 107 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
108 }, 108 },
109}; 109};
110 110
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 94e38cc2bb6c..7846551f0575 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -126,7 +126,7 @@ static struct resource apollon_smc91x_resources[] = {
126 [1] = { 126 [1] = {
127 .start = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ), 127 .start = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
128 .end = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ), 128 .end = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
129 .flags = IORESOURCE_IRQ, 129 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
130 }, 130 },
131}; 131};
132 132
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 656d49661a29..0908bea0f609 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -51,6 +51,50 @@ config PXA_SHARPSL
51 SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) 51 SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
52 handheld computer. 52 handheld computer.
53 53
54config ARCH_PXA_ESERIES
55 bool "PXA based Toshiba e-series PDAs"
56 select PXA25x
57
58config MACH_E330
59 bool "Toshiba e330"
60 default y
61 depends on ARCH_PXA_ESERIES
62 help
63 Say Y here if you intend to run this kernel on a Toshiba
64 e330 family PDA.
65
66config MACH_E740
67 bool "Toshiba e740"
68 default y
69 depends on ARCH_PXA_ESERIES
70 help
71 Say Y here if you intend to run this kernel on a Toshiba
72 e740 family PDA.
73
74config MACH_E750
75 bool "Toshiba e750"
76 default y
77 depends on ARCH_PXA_ESERIES
78 help
79 Say Y here if you intend to run this kernel on a Toshiba
80 e750 family PDA.
81
82config MACH_E400
83 bool "Toshiba e400"
84 default y
85 depends on ARCH_PXA_ESERIES
86 help
87 Say Y here if you intend to run this kernel on a Toshiba
88 e400 family PDA.
89
90config MACH_E800
91 bool "Toshiba e800"
92 default y
93 depends on ARCH_PXA_ESERIES
94 help
95 Say Y here if you intend to run this kernel on a Toshiba
96 e800 family PDA.
97
54config MACH_TRIZEPS4 98config MACH_TRIZEPS4
55 bool "Keith und Koep Trizeps4 DIMM-Module" 99 bool "Keith und Koep Trizeps4 DIMM-Module"
56 select PXA27x 100 select PXA27x
@@ -59,15 +103,44 @@ config MACH_EM_X270
59 bool "CompuLab EM-x270 platform" 103 bool "CompuLab EM-x270 platform"
60 select PXA27x 104 select PXA27x
61 105
106config MACH_COLIBRI
107 bool "Toradex Colibri PX27x"
108 select PXA27x
109
62config MACH_ZYLONITE 110config MACH_ZYLONITE
63 bool "PXA3xx Development Platform" 111 bool "PXA3xx Development Platform"
64 select PXA3xx 112 select PXA3xx
65 113
114config MACH_LITTLETON
115 bool "PXA3xx Form Factor Platform (aka Littleton)"
116 select PXA3xx
117 select PXA_SSP
118
66config MACH_ARMCORE 119config MACH_ARMCORE
67 bool "CompuLab CM-X270 modules" 120 bool "CompuLab CM-X270 modules"
68 select PXA27x 121 select PXA27x
69 select IWMMXT 122 select IWMMXT
70 123
124config MACH_MAGICIAN
125 bool "Enable HTC Magician Support"
126 depends on ARCH_PXA
127 select PXA27x
128 select IWMMXT
129
130config MACH_PCM027
131 bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
132 select PXA27x
133 select IWMMXT
134
135endchoice
136
137choice
138 prompt "Used baseboard"
139 depends on MACH_PCM027
140
141config MACH_PCM990_BASEBOARD
142 bool "PHYTEC PCM-990 development board"
143
71endchoice 144endchoice
72 145
73if PXA_SHARPSL 146if PXA_SHARPSL
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 4263527e5123..b5c916c0747d 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support (must be linked before board specific support) 5# Common support (must be linked before board specific support)
6obj-y += clock.o generic.o irq.o dma.o time.o 6obj-y += clock.o devices.o generic.o irq.o dma.o time.o
7obj-$(CONFIG_PXA25x) += pxa25x.o 7obj-$(CONFIG_PXA25x) += pxa25x.o
8obj-$(CONFIG_PXA27x) += pxa27x.o 8obj-$(CONFIG_PXA27x) += pxa27x.o
9obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o 9obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o
@@ -16,18 +16,24 @@ obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
16obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o 16obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
17obj-$(CONFIG_ARCH_PXA_IDP) += idp.o 17obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
18obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o 18obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
19obj-$(CONFIG_MACH_COLIBRI) += colibri.o
19obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o 20obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
20obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o 21obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o
21obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o 22obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o
22obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o 23obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o
24obj-$(CONFIG_MACH_PCM027) += pcm027.o
25obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o
23obj-$(CONFIG_MACH_TOSA) += tosa.o 26obj-$(CONFIG_MACH_TOSA) += tosa.o
24obj-$(CONFIG_MACH_EM_X270) += em-x270.o 27obj-$(CONFIG_MACH_EM_X270) += em-x270.o
28obj-$(CONFIG_MACH_MAGICIAN) += magician.o
29obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o
25 30
26ifeq ($(CONFIG_MACH_ZYLONITE),y) 31ifeq ($(CONFIG_MACH_ZYLONITE),y)
27 obj-y += zylonite.o 32 obj-y += zylonite.o
28 obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o 33 obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o
29 obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o 34 obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o
30endif 35endif
36obj-$(CONFIG_MACH_LITTLETON) += littleton.o
31 37
32obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o 38obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o
33 39
@@ -41,13 +47,10 @@ led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
41obj-$(CONFIG_LEDS) += $(led-y) 47obj-$(CONFIG_LEDS) += $(led-y)
42 48
43# Misc features 49# Misc features
44obj-$(CONFIG_PM) += pm.o sleep.o 50obj-$(CONFIG_PM) += pm.o sleep.o standby.o
51obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
45obj-$(CONFIG_PXA_SSP) += ssp.o 52obj-$(CONFIG_PXA_SSP) += ssp.o
46 53
47ifeq ($(CONFIG_PXA27x),y)
48obj-$(CONFIG_PM) += standby.o
49endif
50
51ifeq ($(CONFIG_PCI),y) 54ifeq ($(CONFIG_PCI),y)
52obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o 55obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
53endif 56endif
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index a16349272f54..28cfd71c032d 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -487,18 +487,15 @@ static int cmx270_mci_init(struct device *dev,
487 487
488 /* card detect IRQ on GPIO 83 */ 488 /* card detect IRQ on GPIO 83 */
489 pxa_gpio_mode(IRQ_TO_GPIO(CMX270_MMC_IRQ)); 489 pxa_gpio_mode(IRQ_TO_GPIO(CMX270_MMC_IRQ));
490 set_irq_type(CMX270_MMC_IRQ, IRQT_FALLING);
491 490
492 err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int, 491 err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int,
493 IRQF_DISABLED | IRQF_TRIGGER_FALLING, 492 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
494 "MMC card detect", data); 493 "MMC card detect", data);
495 if (err) { 494 if (err)
496 printk(KERN_ERR "cmx270_mci_init: MMC/SD: can't" 495 printk(KERN_ERR "cmx270_mci_init: MMC/SD: can't"
497 " request MMC card detect IRQ\n"); 496 " request MMC card detect IRQ\n");
498 return -1;
499 }
500 497
501 return 0; 498 return err;
502} 499}
503 500
504static void cmx270_mci_setpower(struct device *dev, unsigned int vdd) 501static void cmx270_mci_setpower(struct device *dev, unsigned int vdd)
diff --git a/arch/arm/mach-pxa/colibri.c b/arch/arm/mach-pxa/colibri.c
new file mode 100644
index 000000000000..6db54e31c397
--- /dev/null
+++ b/arch/arm/mach-pxa/colibri.c
@@ -0,0 +1,134 @@
1/*
2 * linux/arch/arm/mach-pxa/colibri.c
3 *
4 * Support for Toradex PXA27x based Colibri module
5 * Daniel Mack <daniel@caiaq.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/sysdev.h>
16#include <linux/interrupt.h>
17#include <linux/bitops.h>
18#include <linux/ioport.h>
19#include <linux/delay.h>
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/partitions.h>
22#include <linux/mtd/physmap.h>
23#include <asm/mach-types.h>
24#include <asm/hardware.h>
25#include <asm/irq.h>
26#include <asm/sizes.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30#include <asm/mach/flash.h>
31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/colibri.h>
33
34#include "generic.h"
35#include "devices.h"
36
37/*
38 * Flash
39 */
40static struct mtd_partition colibri_partitions[] = {
41 {
42 .name = "Bootloader",
43 .offset = 0x00000000,
44 .size = 0x00040000,
45 .mask_flags = MTD_WRITEABLE /* force read-only */
46 }, {
47 .name = "Kernel",
48 .offset = 0x00040000,
49 .size = 0x00400000,
50 .mask_flags = 0
51 }, {
52 .name = "Rootfs",
53 .offset = 0x00440000,
54 .size = MTDPART_SIZ_FULL,
55 .mask_flags = 0
56 }
57};
58
59static struct physmap_flash_data colibri_flash_data[] = {
60 {
61 .width = 4, /* bankwidth in bytes */
62 .parts = colibri_partitions,
63 .nr_parts = ARRAY_SIZE(colibri_partitions)
64 }
65};
66
67static struct resource flash_resource = {
68 .start = PXA_CS0_PHYS,
69 .end = PXA_CS0_PHYS + SZ_32M - 1,
70 .flags = IORESOURCE_MEM,
71};
72
73static struct platform_device flash_device = {
74 .name = "physmap-flash",
75 .id = 0,
76 .dev = {
77 .platform_data = colibri_flash_data,
78 },
79 .resource = &flash_resource,
80 .num_resources = 1,
81};
82
83/*
84 * DM9000 Ethernet
85 */
86static struct resource dm9000_resources[] = {
87 [0] = {
88 .start = COLIBRI_ETH_PHYS,
89 .end = COLIBRI_ETH_PHYS + 3,
90 .flags = IORESOURCE_MEM,
91 },
92 [1] = {
93 .start = COLIBRI_ETH_PHYS + 4,
94 .end = COLIBRI_ETH_PHYS + 4 + 500,
95 .flags = IORESOURCE_MEM,
96 },
97 [2] = {
98 .start = COLIBRI_ETH_IRQ,
99 .end = COLIBRI_ETH_IRQ,
100 .flags = IORESOURCE_IRQ,
101 },
102};
103
104static struct platform_device dm9000_device = {
105 .name = "dm9000",
106 .id = -1,
107 .num_resources = ARRAY_SIZE(dm9000_resources),
108 .resource = dm9000_resources,
109};
110
111static struct platform_device *colibri_devices[] __initdata = {
112 &flash_device,
113 &dm9000_device,
114};
115
116static void __init colibri_init(void)
117{
118 /* DM9000 LAN */
119 pxa_gpio_mode(GPIO78_nCS_2_MD);
120 pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
121 set_irq_type(COLIBRI_ETH_IRQ, IRQT_FALLING);
122
123 platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices));
124}
125
126MACHINE_START(COLIBRI, "Toradex Colibri PXA27x")
127 .phys_io = 0x40000000,
128 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
129 .boot_params = COLIBRI_SDRAM_BASE + 0x100,
130 .init_machine = colibri_init,
131 .map_io = pxa_map_io,
132 .init_irq = pxa27x_init_irq,
133 .timer = &pxa_timer,
134MACHINE_END
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 2363cc64fe07..9292576b83b3 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -21,6 +21,7 @@
21#include <linux/mmc/host.h> 21#include <linux/mmc/host.h>
22#include <linux/pm.h> 22#include <linux/pm.h>
23#include <linux/backlight.h> 23#include <linux/backlight.h>
24#include <video/w100fb.h>
24 25
25#include <asm/setup.h> 26#include <asm/setup.h>
26#include <asm/memory.h> 27#include <asm/memory.h>
@@ -141,6 +142,136 @@ struct corgissp_machinfo corgi_ssp_machinfo = {
141 142
142 143
143/* 144/*
145 * LCD/Framebuffer
146 */
147static void w100_lcdtg_suspend(struct w100fb_par *par)
148{
149 corgi_lcdtg_suspend();
150}
151
152static void w100_lcdtg_init(struct w100fb_par *par)
153{
154 corgi_lcdtg_hw_init(par->xres);
155}
156
157
158static struct w100_tg_info corgi_lcdtg_info = {
159 .change = w100_lcdtg_init,
160 .suspend = w100_lcdtg_suspend,
161 .resume = w100_lcdtg_init,
162};
163
164static struct w100_mem_info corgi_fb_mem = {
165 .ext_cntl = 0x00040003,
166 .sdram_mode_reg = 0x00650021,
167 .ext_timing_cntl = 0x10002a4a,
168 .io_cntl = 0x7ff87012,
169 .size = 0x1fffff,
170};
171
172static struct w100_gen_regs corgi_fb_regs = {
173 .lcd_format = 0x00000003,
174 .lcdd_cntl1 = 0x01CC0000,
175 .lcdd_cntl2 = 0x0003FFFF,
176 .genlcd_cntl1 = 0x00FFFF0D,
177 .genlcd_cntl2 = 0x003F3003,
178 .genlcd_cntl3 = 0x000102aa,
179};
180
181static struct w100_gpio_regs corgi_fb_gpio = {
182 .init_data1 = 0x000000bf,
183 .init_data2 = 0x00000000,
184 .gpio_dir1 = 0x00000000,
185 .gpio_oe1 = 0x03c0feff,
186 .gpio_dir2 = 0x00000000,
187 .gpio_oe2 = 0x00000000,
188};
189
190static struct w100_mode corgi_fb_modes[] = {
191{
192 .xres = 480,
193 .yres = 640,
194 .left_margin = 0x56,
195 .right_margin = 0x55,
196 .upper_margin = 0x03,
197 .lower_margin = 0x00,
198 .crtc_ss = 0x82360056,
199 .crtc_ls = 0xA0280000,
200 .crtc_gs = 0x80280028,
201 .crtc_vpos_gs = 0x02830002,
202 .crtc_rev = 0x00400008,
203 .crtc_dclk = 0xA0000000,
204 .crtc_gclk = 0x8015010F,
205 .crtc_goe = 0x80100110,
206 .crtc_ps1_active = 0x41060010,
207 .pll_freq = 75,
208 .fast_pll_freq = 100,
209 .sysclk_src = CLK_SRC_PLL,
210 .sysclk_divider = 0,
211 .pixclk_src = CLK_SRC_PLL,
212 .pixclk_divider = 2,
213 .pixclk_divider_rotated = 6,
214},{
215 .xres = 240,
216 .yres = 320,
217 .left_margin = 0x27,
218 .right_margin = 0x2e,
219 .upper_margin = 0x01,
220 .lower_margin = 0x00,
221 .crtc_ss = 0x81170027,
222 .crtc_ls = 0xA0140000,
223 .crtc_gs = 0xC0140014,
224 .crtc_vpos_gs = 0x00010141,
225 .crtc_rev = 0x00400008,
226 .crtc_dclk = 0xA0000000,
227 .crtc_gclk = 0x8015010F,
228 .crtc_goe = 0x80100110,
229 .crtc_ps1_active = 0x41060010,
230 .pll_freq = 0,
231 .fast_pll_freq = 0,
232 .sysclk_src = CLK_SRC_XTAL,
233 .sysclk_divider = 0,
234 .pixclk_src = CLK_SRC_XTAL,
235 .pixclk_divider = 1,
236 .pixclk_divider_rotated = 1,
237},
238
239};
240
241static struct w100fb_mach_info corgi_fb_info = {
242 .tg = &corgi_lcdtg_info,
243 .init_mode = INIT_MODE_ROTATED,
244 .mem = &corgi_fb_mem,
245 .regs = &corgi_fb_regs,
246 .modelist = &corgi_fb_modes[0],
247 .num_modes = 2,
248 .gpio = &corgi_fb_gpio,
249 .xtal_freq = 12500000,
250 .xtal_dbl = 0,
251};
252
253static struct resource corgi_fb_resources[] = {
254 [0] = {
255 .start = 0x08000000,
256 .end = 0x08ffffff,
257 .flags = IORESOURCE_MEM,
258 },
259};
260
261static struct platform_device corgifb_device = {
262 .name = "w100fb",
263 .id = -1,
264 .num_resources = ARRAY_SIZE(corgi_fb_resources),
265 .resource = corgi_fb_resources,
266 .dev = {
267 .platform_data = &corgi_fb_info,
268 .parent = &corgissp_device.dev,
269 },
270
271};
272
273
274/*
144 * Corgi Backlight Device 275 * Corgi Backlight Device
145 */ 276 */
146static void corgi_bl_kick_battery(void) 277static void corgi_bl_kick_battery(void)
@@ -154,6 +285,21 @@ static void corgi_bl_kick_battery(void)
154 } 285 }
155} 286}
156 287
288static void corgi_bl_set_intensity(int intensity)
289{
290 if (intensity > 0x10)
291 intensity += 0x10;
292
293 /* Bits 0-4 are accessed via the SSP interface */
294 corgi_ssp_blduty_set(intensity & 0x1f);
295
296 /* Bit 5 is via SCOOP */
297 if (intensity & 0x0020)
298 set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
299 else
300 reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
301}
302
157static struct generic_bl_info corgi_bl_machinfo = { 303static struct generic_bl_info corgi_bl_machinfo = {
158 .name = "corgi-bl", 304 .name = "corgi-bl",
159 .max_intensity = 0x2f, 305 .max_intensity = 0x2f,
@@ -190,9 +336,40 @@ static struct platform_device corgiled_device = {
190 .id = -1, 336 .id = -1,
191}; 337};
192 338
339
193/* 340/*
194 * Corgi Touch Screen Device 341 * Corgi Touch Screen Device
195 */ 342 */
343static unsigned long (*get_hsync_invperiod)(struct device *dev);
344
345static void inline sharpsl_wait_sync(int gpio)
346{
347 while((GPLR(gpio) & GPIO_bit(gpio)) == 0);
348 while((GPLR(gpio) & GPIO_bit(gpio)) != 0);
349}
350
351static unsigned long corgi_get_hsync_invperiod(void)
352{
353 if (!get_hsync_invperiod)
354 get_hsync_invperiod = symbol_get(w100fb_get_hsynclen);
355 if (!get_hsync_invperiod)
356 return 0;
357
358 return get_hsync_invperiod(&corgifb_device.dev);
359}
360
361static void corgi_put_hsync(void)
362{
363 if (get_hsync_invperiod)
364 symbol_put(w100fb_get_hsynclen);
365 get_hsync_invperiod = NULL;
366}
367
368static void corgi_wait_hsync(void)
369{
370 sharpsl_wait_sync(CORGI_GPIO_HSYNC);
371}
372
196static struct resource corgits_resources[] = { 373static struct resource corgits_resources[] = {
197 [0] = { 374 [0] = {
198 .start = CORGI_IRQ_GPIO_TP_INT, 375 .start = CORGI_IRQ_GPIO_TP_INT,
@@ -202,9 +379,9 @@ static struct resource corgits_resources[] = {
202}; 379};
203 380
204static struct corgits_machinfo corgi_ts_machinfo = { 381static struct corgits_machinfo corgi_ts_machinfo = {
205 .get_hsync_len = corgi_get_hsync_len, 382 .get_hsync_invperiod = corgi_get_hsync_invperiod,
206 .put_hsync = corgi_put_hsync, 383 .put_hsync = corgi_put_hsync,
207 .wait_hsync = corgi_wait_hsync, 384 .wait_hsync = corgi_wait_hsync,
208}; 385};
209 386
210static struct platform_device corgits_device = { 387static struct platform_device corgits_device = {
@@ -242,12 +419,10 @@ static int corgi_mci_init(struct device *dev, irq_handler_t corgi_detect_int, vo
242 err = request_irq(CORGI_IRQ_GPIO_nSD_DETECT, corgi_detect_int, 419 err = request_irq(CORGI_IRQ_GPIO_nSD_DETECT, corgi_detect_int,
243 IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 420 IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
244 "MMC card detect", data); 421 "MMC card detect", data);
245 if (err) { 422 if (err)
246 printk(KERN_ERR "corgi_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); 423 printk(KERN_ERR "corgi_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
247 return -1;
248 }
249 424
250 return 0; 425 return err;
251} 426}
252 427
253static void corgi_mci_setpower(struct device *dev, unsigned int vdd) 428static void corgi_mci_setpower(struct device *dev, unsigned int vdd)
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c
index 365b9435f748..9328df37afd1 100644
--- a/arch/arm/mach-pxa/corgi_lcd.c
+++ b/arch/arm/mach-pxa/corgi_lcd.c
@@ -173,7 +173,7 @@ static void lcdtg_set_phadadj(int mode)
173 173
174static int lcd_inited; 174static int lcd_inited;
175 175
176static void lcdtg_hw_init(int mode) 176void corgi_lcdtg_hw_init(int mode)
177{ 177{
178 if (!lcd_inited) { 178 if (!lcd_inited) {
179 int comadj; 179 int comadj;
@@ -254,7 +254,7 @@ static void lcdtg_hw_init(int mode)
254 } 254 }
255} 255}
256 256
257static void lcdtg_suspend(void) 257void corgi_lcdtg_suspend(void)
258{ 258{
259 /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */ 259 /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
260 mdelay(34); 260 mdelay(34);
@@ -288,298 +288,3 @@ static void lcdtg_suspend(void)
288 lcd_inited = 0; 288 lcd_inited = 0;
289} 289}
290 290
291
292/*
293 * Corgi w100 Frame Buffer Device
294 */
295#ifdef CONFIG_PXA_SHARP_C7xx
296
297#include <video/w100fb.h>
298
299static void w100_lcdtg_suspend(struct w100fb_par *par)
300{
301 lcdtg_suspend();
302}
303
304static void w100_lcdtg_init(struct w100fb_par *par)
305{
306 lcdtg_hw_init(par->xres);
307}
308
309
310static struct w100_tg_info corgi_lcdtg_info = {
311 .change = w100_lcdtg_init,
312 .suspend = w100_lcdtg_suspend,
313 .resume = w100_lcdtg_init,
314};
315
316static struct w100_mem_info corgi_fb_mem = {
317 .ext_cntl = 0x00040003,
318 .sdram_mode_reg = 0x00650021,
319 .ext_timing_cntl = 0x10002a4a,
320 .io_cntl = 0x7ff87012,
321 .size = 0x1fffff,
322};
323
324static struct w100_gen_regs corgi_fb_regs = {
325 .lcd_format = 0x00000003,
326 .lcdd_cntl1 = 0x01CC0000,
327 .lcdd_cntl2 = 0x0003FFFF,
328 .genlcd_cntl1 = 0x00FFFF0D,
329 .genlcd_cntl2 = 0x003F3003,
330 .genlcd_cntl3 = 0x000102aa,
331};
332
333static struct w100_gpio_regs corgi_fb_gpio = {
334 .init_data1 = 0x000000bf,
335 .init_data2 = 0x00000000,
336 .gpio_dir1 = 0x00000000,
337 .gpio_oe1 = 0x03c0feff,
338 .gpio_dir2 = 0x00000000,
339 .gpio_oe2 = 0x00000000,
340};
341
342static struct w100_mode corgi_fb_modes[] = {
343{
344 .xres = 480,
345 .yres = 640,
346 .left_margin = 0x56,
347 .right_margin = 0x55,
348 .upper_margin = 0x03,
349 .lower_margin = 0x00,
350 .crtc_ss = 0x82360056,
351 .crtc_ls = 0xA0280000,
352 .crtc_gs = 0x80280028,
353 .crtc_vpos_gs = 0x02830002,
354 .crtc_rev = 0x00400008,
355 .crtc_dclk = 0xA0000000,
356 .crtc_gclk = 0x8015010F,
357 .crtc_goe = 0x80100110,
358 .crtc_ps1_active = 0x41060010,
359 .pll_freq = 75,
360 .fast_pll_freq = 100,
361 .sysclk_src = CLK_SRC_PLL,
362 .sysclk_divider = 0,
363 .pixclk_src = CLK_SRC_PLL,
364 .pixclk_divider = 2,
365 .pixclk_divider_rotated = 6,
366},{
367 .xres = 240,
368 .yres = 320,
369 .left_margin = 0x27,
370 .right_margin = 0x2e,
371 .upper_margin = 0x01,
372 .lower_margin = 0x00,
373 .crtc_ss = 0x81170027,
374 .crtc_ls = 0xA0140000,
375 .crtc_gs = 0xC0140014,
376 .crtc_vpos_gs = 0x00010141,
377 .crtc_rev = 0x00400008,
378 .crtc_dclk = 0xA0000000,
379 .crtc_gclk = 0x8015010F,
380 .crtc_goe = 0x80100110,
381 .crtc_ps1_active = 0x41060010,
382 .pll_freq = 0,
383 .fast_pll_freq = 0,
384 .sysclk_src = CLK_SRC_XTAL,
385 .sysclk_divider = 0,
386 .pixclk_src = CLK_SRC_XTAL,
387 .pixclk_divider = 1,
388 .pixclk_divider_rotated = 1,
389},
390
391};
392
393static struct w100fb_mach_info corgi_fb_info = {
394 .tg = &corgi_lcdtg_info,
395 .init_mode = INIT_MODE_ROTATED,
396 .mem = &corgi_fb_mem,
397 .regs = &corgi_fb_regs,
398 .modelist = &corgi_fb_modes[0],
399 .num_modes = 2,
400 .gpio = &corgi_fb_gpio,
401 .xtal_freq = 12500000,
402 .xtal_dbl = 0,
403};
404
405static struct resource corgi_fb_resources[] = {
406 [0] = {
407 .start = 0x08000000,
408 .end = 0x08ffffff,
409 .flags = IORESOURCE_MEM,
410 },
411};
412
413struct platform_device corgifb_device = {
414 .name = "w100fb",
415 .id = -1,
416 .num_resources = ARRAY_SIZE(corgi_fb_resources),
417 .resource = corgi_fb_resources,
418 .dev = {
419 .platform_data = &corgi_fb_info,
420 .parent = &corgissp_device.dev,
421 },
422
423};
424#endif
425
426
427/*
428 * Spitz PXA Frame Buffer Device
429 */
430#ifdef CONFIG_PXA_SHARP_Cxx00
431
432#include <asm/arch/pxafb.h>
433
434void spitz_lcd_power(int on, struct fb_var_screeninfo *var)
435{
436 if (on)
437 lcdtg_hw_init(var->xres);
438 else
439 lcdtg_suspend();
440}
441
442#endif
443
444
445/*
446 * Corgi/Spitz Touchscreen to LCD interface
447 */
448static unsigned long (*get_hsync_time)(struct device *dev);
449
450static void inline sharpsl_wait_sync(int gpio)
451{
452 while((GPLR(gpio) & GPIO_bit(gpio)) == 0);
453 while((GPLR(gpio) & GPIO_bit(gpio)) != 0);
454}
455
456#ifdef CONFIG_PXA_SHARP_C7xx
457unsigned long corgi_get_hsync_len(void)
458{
459 if (!get_hsync_time)
460 get_hsync_time = symbol_get(w100fb_get_hsynclen);
461 if (!get_hsync_time)
462 return 0;
463
464 return get_hsync_time(&corgifb_device.dev);
465}
466
467void corgi_put_hsync(void)
468{
469 if (get_hsync_time)
470 symbol_put(w100fb_get_hsynclen);
471 get_hsync_time = NULL;
472}
473
474void corgi_wait_hsync(void)
475{
476 sharpsl_wait_sync(CORGI_GPIO_HSYNC);
477}
478#endif
479
480#ifdef CONFIG_PXA_SHARP_Cxx00
481static struct device *spitz_pxafb_dev;
482
483static int is_pxafb_device(struct device * dev, void * data)
484{
485 struct platform_device *pdev = container_of(dev, struct platform_device, dev);
486
487 return (strncmp(pdev->name, "pxa2xx-fb", 9) == 0);
488}
489
490unsigned long spitz_get_hsync_len(void)
491{
492#ifdef CONFIG_FB_PXA
493 if (!spitz_pxafb_dev) {
494 spitz_pxafb_dev = bus_find_device(&platform_bus_type, NULL, NULL, is_pxafb_device);
495 if (!spitz_pxafb_dev)
496 return 0;
497 }
498 if (!get_hsync_time)
499 get_hsync_time = symbol_get(pxafb_get_hsync_time);
500 if (!get_hsync_time)
501#endif
502 return 0;
503
504 return pxafb_get_hsync_time(spitz_pxafb_dev);
505}
506
507void spitz_put_hsync(void)
508{
509 put_device(spitz_pxafb_dev);
510 if (get_hsync_time)
511 symbol_put(pxafb_get_hsync_time);
512 spitz_pxafb_dev = NULL;
513 get_hsync_time = NULL;
514}
515
516void spitz_wait_hsync(void)
517{
518 sharpsl_wait_sync(SPITZ_GPIO_HSYNC);
519}
520#endif
521
522/*
523 * Corgi/Spitz Backlight Power
524 */
525#ifdef CONFIG_PXA_SHARP_C7xx
526void corgi_bl_set_intensity(int intensity)
527{
528 if (intensity > 0x10)
529 intensity += 0x10;
530
531 /* Bits 0-4 are accessed via the SSP interface */
532 corgi_ssp_blduty_set(intensity & 0x1f);
533
534 /* Bit 5 is via SCOOP */
535 if (intensity & 0x0020)
536 set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
537 else
538 reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
539}
540#endif
541
542
543#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
544void spitz_bl_set_intensity(int intensity)
545{
546 if (intensity > 0x10)
547 intensity += 0x10;
548
549 /* Bits 0-4 are accessed via the SSP interface */
550 corgi_ssp_blduty_set(intensity & 0x1f);
551
552 /* Bit 5 is via SCOOP */
553 if (intensity & 0x0020)
554 reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
555 else
556 set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
557
558 if (intensity)
559 set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
560 else
561 reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
562}
563#endif
564
565#ifdef CONFIG_MACH_AKITA
566void akita_bl_set_intensity(int intensity)
567{
568 if (intensity > 0x10)
569 intensity += 0x10;
570
571 /* Bits 0-4 are accessed via the SSP interface */
572 corgi_ssp_blduty_set(intensity & 0x1f);
573
574 /* Bit 5 is via IO-Expander */
575 if (intensity & 0x0020)
576 akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
577 else
578 akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
579
580 if (intensity)
581 akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
582 else
583 akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
584}
585#endif
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c
index 40dea3d5142b..efba65edcd51 100644
--- a/arch/arm/mach-pxa/corgi_ssp.c
+++ b/arch/arm/mach-pxa/corgi_ssp.c
@@ -21,6 +21,7 @@
21 21
22#include <asm/arch/ssp.h> 22#include <asm/arch/ssp.h>
23#include <asm/arch/pxa-regs.h> 23#include <asm/arch/pxa-regs.h>
24#include <asm/arch/regs-ssp.h>
24#include "sharpsl.h" 25#include "sharpsl.h"
25 26
26static DEFINE_SPINLOCK(corgi_ssp_lock); 27static DEFINE_SPINLOCK(corgi_ssp_lock);
diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c
new file mode 100644
index 000000000000..cbc583beedc8
--- /dev/null
+++ b/arch/arm/mach-pxa/cpu-pxa.c
@@ -0,0 +1,294 @@
1/*
2 * linux/arch/arm/mach-pxa/cpu-pxa.c
3 *
4 * Copyright (C) 2002,2003 Intrinsyc Software
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * History:
21 * 31-Jul-2002 : Initial version [FB]
22 * 29-Jan-2003 : added PXA255 support [FB]
23 * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
24 *
25 * Note:
26 * This driver may change the memory bus clock rate, but will not do any
27 * platform specific access timing changes... for example if you have flash
28 * memory connected to CS0, you will need to register a platform specific
29 * notifier which will adjust the memory access strobes to maintain a
30 * minimum strobe width.
31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/sched.h>
37#include <linux/init.h>
38#include <linux/cpufreq.h>
39
40#include <asm/hardware.h>
41#include <asm/arch/pxa-regs.h>
42#include <asm/arch/pxa2xx-regs.h>
43
44#ifdef DEBUG
45static unsigned int freq_debug;
46MODULE_PARM(freq_debug, "i");
47MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
48#else
49#define freq_debug 0
50#endif
51
52typedef struct {
53 unsigned int khz;
54 unsigned int membus;
55 unsigned int cccr;
56 unsigned int div2;
57} pxa_freqs_t;
58
59/* Define the refresh period in mSec for the SDRAM and the number of rows */
60#define SDRAM_TREF 64 /* standard 64ms SDRAM */
61#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
62#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
63
64#define CCLKCFG_TURBO 0x1
65#define CCLKCFG_FCS 0x2
66#define PXA25x_MIN_FREQ 99500
67#define PXA25x_MAX_FREQ 398100
68#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
69#define MDREFR_DRI_MASK 0xFFF
70
71
72/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
73static pxa_freqs_t pxa255_run_freqs[] =
74{
75 /* CPU MEMBUS CCCR DIV2*/
76 { 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */
77 {132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */
78 {199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */
79 {265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */
80 {331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */
81 {398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */
82 {0,}
83};
84#define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
85
86static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
87
88/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
89static pxa_freqs_t pxa255_turbo_freqs[] =
90{
91 /* CPU MEMBUS CCCR DIV2*/
92 { 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */
93 {199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */
94 {298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */
95 {298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */
96 {398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */
97 {0,}
98};
99#define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
100
101static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
102
103extern unsigned get_clk_frequency_khz(int info);
104
105/* find a valid frequency point */
106static int pxa_verify_policy(struct cpufreq_policy *policy)
107{
108 struct cpufreq_frequency_table *pxa_freqs_table;
109 int ret;
110
111 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
112 pxa_freqs_table = pxa255_run_freq_table;
113 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
114 pxa_freqs_table = pxa255_turbo_freq_table;
115 } else {
116 printk("CPU PXA: Unknown policy found. "
117 "Using CPUFREQ_POLICY_PERFORMANCE\n");
118 pxa_freqs_table = pxa255_run_freq_table;
119 }
120
121 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
122
123 if (freq_debug)
124 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
125 policy->min, policy->max);
126
127 return ret;
128}
129
130static int pxa_set_target(struct cpufreq_policy *policy,
131 unsigned int target_freq,
132 unsigned int relation)
133{
134 struct cpufreq_frequency_table *pxa_freqs_table;
135 pxa_freqs_t *pxa_freq_settings;
136 struct cpufreq_freqs freqs;
137 int idx;
138 unsigned long flags;
139 unsigned int unused, preset_mdrefr, postset_mdrefr;
140 void *ramstart = phys_to_virt(0xa0000000);
141
142 /* Get the current policy */
143 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
144 pxa_freq_settings = pxa255_run_freqs;
145 pxa_freqs_table = pxa255_run_freq_table;
146 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
147 pxa_freq_settings = pxa255_turbo_freqs;
148 pxa_freqs_table = pxa255_turbo_freq_table;
149 } else {
150 printk("CPU PXA: Unknown policy found. "
151 "Using CPUFREQ_POLICY_PERFORMANCE\n");
152 pxa_freq_settings = pxa255_run_freqs;
153 pxa_freqs_table = pxa255_run_freq_table;
154 }
155
156 /* Lookup the next frequency */
157 if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
158 target_freq, relation, &idx)) {
159 return -EINVAL;
160 }
161
162 freqs.old = policy->cur;
163 freqs.new = pxa_freq_settings[idx].khz;
164 freqs.cpu = policy->cpu;
165
166 if (freq_debug)
167 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
168 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
169 (pxa_freq_settings[idx].membus / 2000) :
170 (pxa_freq_settings[idx].membus / 1000));
171
172 /*
173 * Tell everyone what we're about to do...
174 * you should add a notify client with any platform specific
175 * Vcc changing capability
176 */
177 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
178
179 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
180 * we need to preset the smaller DRI before the change. If we're speeding
181 * up we need to set the larger DRI value after the change.
182 */
183 preset_mdrefr = postset_mdrefr = MDREFR;
184 if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) {
185 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
186 MDREFR_DRI(pxa_freq_settings[idx].membus);
187 }
188 postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
189 MDREFR_DRI(pxa_freq_settings[idx].membus);
190
191 /* If we're dividing the memory clock by two for the SDRAM clock, this
192 * must be set prior to the change. Clearing the divide must be done
193 * after the change.
194 */
195 if (pxa_freq_settings[idx].div2) {
196 preset_mdrefr |= MDREFR_DB2_MASK;
197 postset_mdrefr |= MDREFR_DB2_MASK;
198 } else {
199 postset_mdrefr &= ~MDREFR_DB2_MASK;
200 }
201
202 local_irq_save(flags);
203
204 /* Set new the CCCR */
205 CCCR = pxa_freq_settings[idx].cccr;
206
207 asm volatile(" \n\
208 ldr r4, [%1] /* load MDREFR */ \n\
209 b 2f \n\
210 .align 5 \n\
2111: \n\
212 str %4, [%1] /* preset the MDREFR */ \n\
213 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
214 str %5, [%1] /* postset the MDREFR */ \n\
215 \n\
216 b 3f \n\
2172: b 1b \n\
2183: nop \n\
219 "
220 : "=&r" (unused)
221 : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart),
222 "r" (preset_mdrefr), "r" (postset_mdrefr)
223 : "r4", "r5");
224 local_irq_restore(flags);
225
226 /*
227 * Tell everyone what we've just done...
228 * you should add a notify client with any platform specific
229 * SDRAM refresh timer adjustments
230 */
231 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
232
233 return 0;
234}
235
236static int pxa_cpufreq_init(struct cpufreq_policy *policy)
237{
238 int i;
239
240 /* set default policy and cpuinfo */
241 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
242 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
243 policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
244 policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
245 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
246 policy->cur = get_clk_frequency_khz(0); /* current freq */
247 policy->min = policy->max = policy->cur;
248
249 /* Generate the run cpufreq_frequency_table struct */
250 for (i = 0; i < NUM_RUN_FREQS; i++) {
251 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
252 pxa255_run_freq_table[i].index = i;
253 }
254
255 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
256 /* Generate the turbo cpufreq_frequency_table struct */
257 for (i = 0; i < NUM_TURBO_FREQS; i++) {
258 pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz;
259 pxa255_turbo_freq_table[i].index = i;
260 }
261 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
262
263 printk(KERN_INFO "PXA CPU frequency change support initialized\n");
264
265 return 0;
266}
267
268static struct cpufreq_driver pxa_cpufreq_driver = {
269 .verify = pxa_verify_policy,
270 .target = pxa_set_target,
271 .init = pxa_cpufreq_init,
272 .name = "PXA25x",
273};
274
275static int __init pxa_cpu_init(void)
276{
277 int ret = -ENODEV;
278 if (cpu_is_pxa25x())
279 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
280 return ret;
281}
282
283static void __exit pxa_cpu_exit(void)
284{
285 if (cpu_is_pxa25x())
286 cpufreq_unregister_driver(&pxa_cpufreq_driver);
287}
288
289
290MODULE_AUTHOR ("Intrinsyc Software Inc.");
291MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture");
292MODULE_LICENSE("GPL");
293module_init(pxa_cpu_init);
294module_exit(pxa_cpu_exit);
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
new file mode 100644
index 000000000000..50ff453ad370
--- /dev/null
+++ b/arch/arm/mach-pxa/devices.c
@@ -0,0 +1,662 @@
1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/platform_device.h>
5#include <linux/dma-mapping.h>
6
7#include <asm/arch/gpio.h>
8#include <asm/arch/udc.h>
9#include <asm/arch/pxafb.h>
10#include <asm/arch/mmc.h>
11#include <asm/arch/irda.h>
12#include <asm/arch/i2c.h>
13
14#include "devices.h"
15
16void __init pxa_register_device(struct platform_device *dev, void *data)
17{
18 int ret;
19
20 dev->dev.platform_data = data;
21
22 ret = platform_device_register(dev);
23 if (ret)
24 dev_err(&dev->dev, "unable to register device: %d\n", ret);
25}
26
27static struct resource pxamci_resources[] = {
28 [0] = {
29 .start = 0x41100000,
30 .end = 0x41100fff,
31 .flags = IORESOURCE_MEM,
32 },
33 [1] = {
34 .start = IRQ_MMC,
35 .end = IRQ_MMC,
36 .flags = IORESOURCE_IRQ,
37 },
38 [2] = {
39 .start = 21,
40 .end = 21,
41 .flags = IORESOURCE_DMA,
42 },
43 [3] = {
44 .start = 22,
45 .end = 22,
46 .flags = IORESOURCE_DMA,
47 },
48};
49
50static u64 pxamci_dmamask = 0xffffffffUL;
51
52struct platform_device pxa_device_mci = {
53 .name = "pxa2xx-mci",
54 .id = 0,
55 .dev = {
56 .dma_mask = &pxamci_dmamask,
57 .coherent_dma_mask = 0xffffffff,
58 },
59 .num_resources = ARRAY_SIZE(pxamci_resources),
60 .resource = pxamci_resources,
61};
62
63void __init pxa_set_mci_info(struct pxamci_platform_data *info)
64{
65 pxa_register_device(&pxa_device_mci, info);
66}
67
68
69static struct pxa2xx_udc_mach_info pxa_udc_info;
70
71void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
72{
73 memcpy(&pxa_udc_info, info, sizeof *info);
74}
75
76static struct resource pxa2xx_udc_resources[] = {
77 [0] = {
78 .start = 0x40600000,
79 .end = 0x4060ffff,
80 .flags = IORESOURCE_MEM,
81 },
82 [1] = {
83 .start = IRQ_USB,
84 .end = IRQ_USB,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89static u64 udc_dma_mask = ~(u32)0;
90
91struct platform_device pxa_device_udc = {
92 .name = "pxa2xx-udc",
93 .id = -1,
94 .resource = pxa2xx_udc_resources,
95 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
96 .dev = {
97 .platform_data = &pxa_udc_info,
98 .dma_mask = &udc_dma_mask,
99 }
100};
101
102static struct resource pxafb_resources[] = {
103 [0] = {
104 .start = 0x44000000,
105 .end = 0x4400ffff,
106 .flags = IORESOURCE_MEM,
107 },
108 [1] = {
109 .start = IRQ_LCD,
110 .end = IRQ_LCD,
111 .flags = IORESOURCE_IRQ,
112 },
113};
114
115static u64 fb_dma_mask = ~(u64)0;
116
117struct platform_device pxa_device_fb = {
118 .name = "pxa2xx-fb",
119 .id = -1,
120 .dev = {
121 .dma_mask = &fb_dma_mask,
122 .coherent_dma_mask = 0xffffffff,
123 },
124 .num_resources = ARRAY_SIZE(pxafb_resources),
125 .resource = pxafb_resources,
126};
127
128void __init set_pxa_fb_info(struct pxafb_mach_info *info)
129{
130 pxa_register_device(&pxa_device_fb, info);
131}
132
133void __init set_pxa_fb_parent(struct device *parent_dev)
134{
135 pxa_device_fb.dev.parent = parent_dev;
136}
137
138static struct resource pxa_resource_ffuart[] = {
139 {
140 .start = __PREG(FFUART),
141 .end = __PREG(FFUART) + 35,
142 .flags = IORESOURCE_MEM,
143 }, {
144 .start = IRQ_FFUART,
145 .end = IRQ_FFUART,
146 .flags = IORESOURCE_IRQ,
147 }
148};
149
150struct platform_device pxa_device_ffuart= {
151 .name = "pxa2xx-uart",
152 .id = 0,
153 .resource = pxa_resource_ffuart,
154 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
155};
156
157static struct resource pxa_resource_btuart[] = {
158 {
159 .start = __PREG(BTUART),
160 .end = __PREG(BTUART) + 35,
161 .flags = IORESOURCE_MEM,
162 }, {
163 .start = IRQ_BTUART,
164 .end = IRQ_BTUART,
165 .flags = IORESOURCE_IRQ,
166 }
167};
168
169struct platform_device pxa_device_btuart = {
170 .name = "pxa2xx-uart",
171 .id = 1,
172 .resource = pxa_resource_btuart,
173 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
174};
175
176static struct resource pxa_resource_stuart[] = {
177 {
178 .start = __PREG(STUART),
179 .end = __PREG(STUART) + 35,
180 .flags = IORESOURCE_MEM,
181 }, {
182 .start = IRQ_STUART,
183 .end = IRQ_STUART,
184 .flags = IORESOURCE_IRQ,
185 }
186};
187
188struct platform_device pxa_device_stuart = {
189 .name = "pxa2xx-uart",
190 .id = 2,
191 .resource = pxa_resource_stuart,
192 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
193};
194
195static struct resource pxa_resource_hwuart[] = {
196 {
197 .start = __PREG(HWUART),
198 .end = __PREG(HWUART) + 47,
199 .flags = IORESOURCE_MEM,
200 }, {
201 .start = IRQ_HWUART,
202 .end = IRQ_HWUART,
203 .flags = IORESOURCE_IRQ,
204 }
205};
206
207struct platform_device pxa_device_hwuart = {
208 .name = "pxa2xx-uart",
209 .id = 3,
210 .resource = pxa_resource_hwuart,
211 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
212};
213
214static struct resource pxai2c_resources[] = {
215 {
216 .start = 0x40301680,
217 .end = 0x403016a3,
218 .flags = IORESOURCE_MEM,
219 }, {
220 .start = IRQ_I2C,
221 .end = IRQ_I2C,
222 .flags = IORESOURCE_IRQ,
223 },
224};
225
226struct platform_device pxa_device_i2c = {
227 .name = "pxa2xx-i2c",
228 .id = 0,
229 .resource = pxai2c_resources,
230 .num_resources = ARRAY_SIZE(pxai2c_resources),
231};
232
233void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
234{
235 pxa_register_device(&pxa_device_i2c, info);
236}
237
238static struct resource pxai2s_resources[] = {
239 {
240 .start = 0x40400000,
241 .end = 0x40400083,
242 .flags = IORESOURCE_MEM,
243 }, {
244 .start = IRQ_I2S,
245 .end = IRQ_I2S,
246 .flags = IORESOURCE_IRQ,
247 },
248};
249
250struct platform_device pxa_device_i2s = {
251 .name = "pxa2xx-i2s",
252 .id = -1,
253 .resource = pxai2s_resources,
254 .num_resources = ARRAY_SIZE(pxai2s_resources),
255};
256
257static u64 pxaficp_dmamask = ~(u32)0;
258
259struct platform_device pxa_device_ficp = {
260 .name = "pxa2xx-ir",
261 .id = -1,
262 .dev = {
263 .dma_mask = &pxaficp_dmamask,
264 .coherent_dma_mask = 0xffffffff,
265 },
266};
267
268void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
269{
270 pxa_register_device(&pxa_device_ficp, info);
271}
272
273struct platform_device pxa_device_rtc = {
274 .name = "sa1100-rtc",
275 .id = -1,
276};
277
278#ifdef CONFIG_PXA25x
279
280static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
281
282static struct resource pxa25x_resource_ssp[] = {
283 [0] = {
284 .start = 0x41000000,
285 .end = 0x4100001f,
286 .flags = IORESOURCE_MEM,
287 },
288 [1] = {
289 .start = IRQ_SSP,
290 .end = IRQ_SSP,
291 .flags = IORESOURCE_IRQ,
292 },
293 [2] = {
294 /* DRCMR for RX */
295 .start = 13,
296 .end = 13,
297 .flags = IORESOURCE_DMA,
298 },
299 [3] = {
300 /* DRCMR for TX */
301 .start = 14,
302 .end = 14,
303 .flags = IORESOURCE_DMA,
304 },
305};
306
307struct platform_device pxa25x_device_ssp = {
308 .name = "pxa25x-ssp",
309 .id = 0,
310 .dev = {
311 .dma_mask = &pxa25x_ssp_dma_mask,
312 .coherent_dma_mask = DMA_BIT_MASK(32),
313 },
314 .resource = pxa25x_resource_ssp,
315 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
316};
317
318static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
319
320static struct resource pxa25x_resource_nssp[] = {
321 [0] = {
322 .start = 0x41400000,
323 .end = 0x4140002f,
324 .flags = IORESOURCE_MEM,
325 },
326 [1] = {
327 .start = IRQ_NSSP,
328 .end = IRQ_NSSP,
329 .flags = IORESOURCE_IRQ,
330 },
331 [2] = {
332 /* DRCMR for RX */
333 .start = 15,
334 .end = 15,
335 .flags = IORESOURCE_DMA,
336 },
337 [3] = {
338 /* DRCMR for TX */
339 .start = 16,
340 .end = 16,
341 .flags = IORESOURCE_DMA,
342 },
343};
344
345struct platform_device pxa25x_device_nssp = {
346 .name = "pxa25x-nssp",
347 .id = 1,
348 .dev = {
349 .dma_mask = &pxa25x_nssp_dma_mask,
350 .coherent_dma_mask = DMA_BIT_MASK(32),
351 },
352 .resource = pxa25x_resource_nssp,
353 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
354};
355
356static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
357
358static struct resource pxa25x_resource_assp[] = {
359 [0] = {
360 .start = 0x41500000,
361 .end = 0x4150002f,
362 .flags = IORESOURCE_MEM,
363 },
364 [1] = {
365 .start = IRQ_ASSP,
366 .end = IRQ_ASSP,
367 .flags = IORESOURCE_IRQ,
368 },
369 [2] = {
370 /* DRCMR for RX */
371 .start = 23,
372 .end = 23,
373 .flags = IORESOURCE_DMA,
374 },
375 [3] = {
376 /* DRCMR for TX */
377 .start = 24,
378 .end = 24,
379 .flags = IORESOURCE_DMA,
380 },
381};
382
383struct platform_device pxa25x_device_assp = {
384 /* ASSP is basically equivalent to NSSP */
385 .name = "pxa25x-nssp",
386 .id = 2,
387 .dev = {
388 .dma_mask = &pxa25x_assp_dma_mask,
389 .coherent_dma_mask = DMA_BIT_MASK(32),
390 },
391 .resource = pxa25x_resource_assp,
392 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
393};
394#endif /* CONFIG_PXA25x */
395
396#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
397
398static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
399
400static struct resource pxa27x_resource_ohci[] = {
401 [0] = {
402 .start = 0x4C000000,
403 .end = 0x4C00ff6f,
404 .flags = IORESOURCE_MEM,
405 },
406 [1] = {
407 .start = IRQ_USBH1,
408 .end = IRQ_USBH1,
409 .flags = IORESOURCE_IRQ,
410 },
411};
412
413struct platform_device pxa27x_device_ohci = {
414 .name = "pxa27x-ohci",
415 .id = -1,
416 .dev = {
417 .dma_mask = &pxa27x_ohci_dma_mask,
418 .coherent_dma_mask = DMA_BIT_MASK(32),
419 },
420 .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
421 .resource = pxa27x_resource_ohci,
422};
423
424void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
425{
426 pxa_register_device(&pxa27x_device_ohci, info);
427}
428
429static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
430
431static struct resource pxa27x_resource_ssp1[] = {
432 [0] = {
433 .start = 0x41000000,
434 .end = 0x4100003f,
435 .flags = IORESOURCE_MEM,
436 },
437 [1] = {
438 .start = IRQ_SSP,
439 .end = IRQ_SSP,
440 .flags = IORESOURCE_IRQ,
441 },
442 [2] = {
443 /* DRCMR for RX */
444 .start = 13,
445 .end = 13,
446 .flags = IORESOURCE_DMA,
447 },
448 [3] = {
449 /* DRCMR for TX */
450 .start = 14,
451 .end = 14,
452 .flags = IORESOURCE_DMA,
453 },
454};
455
456struct platform_device pxa27x_device_ssp1 = {
457 .name = "pxa27x-ssp",
458 .id = 0,
459 .dev = {
460 .dma_mask = &pxa27x_ssp1_dma_mask,
461 .coherent_dma_mask = DMA_BIT_MASK(32),
462 },
463 .resource = pxa27x_resource_ssp1,
464 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
465};
466
467static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
468
469static struct resource pxa27x_resource_ssp2[] = {
470 [0] = {
471 .start = 0x41700000,
472 .end = 0x4170003f,
473 .flags = IORESOURCE_MEM,
474 },
475 [1] = {
476 .start = IRQ_SSP2,
477 .end = IRQ_SSP2,
478 .flags = IORESOURCE_IRQ,
479 },
480 [2] = {
481 /* DRCMR for RX */
482 .start = 15,
483 .end = 15,
484 .flags = IORESOURCE_DMA,
485 },
486 [3] = {
487 /* DRCMR for TX */
488 .start = 16,
489 .end = 16,
490 .flags = IORESOURCE_DMA,
491 },
492};
493
494struct platform_device pxa27x_device_ssp2 = {
495 .name = "pxa27x-ssp",
496 .id = 1,
497 .dev = {
498 .dma_mask = &pxa27x_ssp2_dma_mask,
499 .coherent_dma_mask = DMA_BIT_MASK(32),
500 },
501 .resource = pxa27x_resource_ssp2,
502 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
503};
504
505static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
506
507static struct resource pxa27x_resource_ssp3[] = {
508 [0] = {
509 .start = 0x41900000,
510 .end = 0x4190003f,
511 .flags = IORESOURCE_MEM,
512 },
513 [1] = {
514 .start = IRQ_SSP3,
515 .end = IRQ_SSP3,
516 .flags = IORESOURCE_IRQ,
517 },
518 [2] = {
519 /* DRCMR for RX */
520 .start = 66,
521 .end = 66,
522 .flags = IORESOURCE_DMA,
523 },
524 [3] = {
525 /* DRCMR for TX */
526 .start = 67,
527 .end = 67,
528 .flags = IORESOURCE_DMA,
529 },
530};
531
532struct platform_device pxa27x_device_ssp3 = {
533 .name = "pxa27x-ssp",
534 .id = 2,
535 .dev = {
536 .dma_mask = &pxa27x_ssp3_dma_mask,
537 .coherent_dma_mask = DMA_BIT_MASK(32),
538 },
539 .resource = pxa27x_resource_ssp3,
540 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
541};
542#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
543
544#ifdef CONFIG_PXA3xx
545static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
546
547static struct resource pxa3xx_resource_ssp4[] = {
548 [0] = {
549 .start = 0x41a00000,
550 .end = 0x41a0003f,
551 .flags = IORESOURCE_MEM,
552 },
553 [1] = {
554 .start = IRQ_SSP4,
555 .end = IRQ_SSP4,
556 .flags = IORESOURCE_IRQ,
557 },
558 [2] = {
559 /* DRCMR for RX */
560 .start = 2,
561 .end = 2,
562 .flags = IORESOURCE_DMA,
563 },
564 [3] = {
565 /* DRCMR for TX */
566 .start = 3,
567 .end = 3,
568 .flags = IORESOURCE_DMA,
569 },
570};
571
572struct platform_device pxa3xx_device_ssp4 = {
573 /* PXA3xx SSP is basically equivalent to PXA27x */
574 .name = "pxa27x-ssp",
575 .id = 3,
576 .dev = {
577 .dma_mask = &pxa3xx_ssp4_dma_mask,
578 .coherent_dma_mask = DMA_BIT_MASK(32),
579 },
580 .resource = pxa3xx_resource_ssp4,
581 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
582};
583
584static struct resource pxa3xx_resources_mci2[] = {
585 [0] = {
586 .start = 0x42000000,
587 .end = 0x42000fff,
588 .flags = IORESOURCE_MEM,
589 },
590 [1] = {
591 .start = IRQ_MMC2,
592 .end = IRQ_MMC2,
593 .flags = IORESOURCE_IRQ,
594 },
595 [2] = {
596 .start = 93,
597 .end = 93,
598 .flags = IORESOURCE_DMA,
599 },
600 [3] = {
601 .start = 94,
602 .end = 94,
603 .flags = IORESOURCE_DMA,
604 },
605};
606
607struct platform_device pxa3xx_device_mci2 = {
608 .name = "pxa2xx-mci",
609 .id = 1,
610 .dev = {
611 .dma_mask = &pxamci_dmamask,
612 .coherent_dma_mask = 0xffffffff,
613 },
614 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
615 .resource = pxa3xx_resources_mci2,
616};
617
618void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
619{
620 pxa_register_device(&pxa3xx_device_mci2, info);
621}
622
623static struct resource pxa3xx_resources_mci3[] = {
624 [0] = {
625 .start = 0x42500000,
626 .end = 0x42500fff,
627 .flags = IORESOURCE_MEM,
628 },
629 [1] = {
630 .start = IRQ_MMC3,
631 .end = IRQ_MMC3,
632 .flags = IORESOURCE_IRQ,
633 },
634 [2] = {
635 .start = 100,
636 .end = 100,
637 .flags = IORESOURCE_DMA,
638 },
639 [3] = {
640 .start = 101,
641 .end = 101,
642 .flags = IORESOURCE_DMA,
643 },
644};
645
646struct platform_device pxa3xx_device_mci3 = {
647 .name = "pxa2xx-mci",
648 .id = 2,
649 .dev = {
650 .dma_mask = &pxamci_dmamask,
651 .coherent_dma_mask = 0xffffffff,
652 },
653 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
654 .resource = pxa3xx_resources_mci3,
655};
656
657void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
658{
659 pxa_register_device(&pxa3xx_device_mci3, info);
660}
661
662#endif /* CONFIG_PXA3xx */
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 94c8d5cdd60a..96c7c8909068 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -1,4 +1,6 @@
1extern struct platform_device pxa_device_mci; 1extern struct platform_device pxa_device_mci;
2extern struct platform_device pxa3xx_device_mci2;
3extern struct platform_device pxa3xx_device_mci3;
2extern struct platform_device pxa_device_udc; 4extern struct platform_device pxa_device_udc;
3extern struct platform_device pxa_device_fb; 5extern struct platform_device pxa_device_fb;
4extern struct platform_device pxa_device_ffuart; 6extern struct platform_device pxa_device_ffuart;
@@ -12,3 +14,13 @@ extern struct platform_device pxa_device_rtc;
12 14
13extern struct platform_device pxa27x_device_i2c_power; 15extern struct platform_device pxa27x_device_i2c_power;
14extern struct platform_device pxa27x_device_ohci; 16extern struct platform_device pxa27x_device_ohci;
17
18extern struct platform_device pxa25x_device_ssp;
19extern struct platform_device pxa25x_device_nssp;
20extern struct platform_device pxa25x_device_assp;
21extern struct platform_device pxa27x_device_ssp1;
22extern struct platform_device pxa27x_device_ssp2;
23extern struct platform_device pxa27x_device_ssp3;
24extern struct platform_device pxa3xx_device_ssp4;
25
26void __init pxa_register_device(struct platform_device *dev, void *data);
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
new file mode 100644
index 000000000000..ee0ae93c876a
--- /dev/null
+++ b/arch/arm/mach-pxa/eseries.c
@@ -0,0 +1,101 @@
1/*
2 * Hardware definitions for the Toshiba eseries PDAs
3 *
4 * Copyright (c) 2003 Ian Molton <spyro@f2s.com>
5 *
6 * This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12
13#include <linux/init.h>
14
15#include <asm/setup.h>
16#include <asm/mach/arch.h>
17#include <asm/arch/hardware.h>
18#include <asm/mach-types.h>
19
20#include <generic.h>
21
22/* Only e800 has 128MB RAM */
23static void __init eseries_fixup(struct machine_desc *desc,
24 struct tag *tags, char **cmdline, struct meminfo *mi)
25{
26 mi->nr_banks=1;
27 mi->bank[0].start = 0xa0000000;
28 mi->bank[0].node = 0;
29 if (machine_is_e800())
30 mi->bank[0].size = (128*1024*1024);
31 else
32 mi->bank[0].size = (64*1024*1024);
33}
34
35/* e-series machine definitions */
36
37#ifdef CONFIG_MACH_E330
38MACHINE_START(E330, "Toshiba e330")
39 /* Maintainer: Ian Molton (spyro@f2s.com) */
40 .phys_io = 0x40000000,
41 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
42 .boot_params = 0xa0000100,
43 .map_io = pxa_map_io,
44 .init_irq = pxa25x_init_irq,
45 .fixup = eseries_fixup,
46 .timer = &pxa_timer,
47MACHINE_END
48#endif
49
50#ifdef CONFIG_MACH_E740
51MACHINE_START(E740, "Toshiba e740")
52 /* Maintainer: Ian Molton (spyro@f2s.com) */
53 .phys_io = 0x40000000,
54 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
55 .boot_params = 0xa0000100,
56 .map_io = pxa_map_io,
57 .init_irq = pxa25x_init_irq,
58 .fixup = eseries_fixup,
59 .timer = &pxa_timer,
60MACHINE_END
61#endif
62
63#ifdef CONFIG_MACH_E750
64MACHINE_START(E750, "Toshiba e750")
65 /* Maintainer: Ian Molton (spyro@f2s.com) */
66 .phys_io = 0x40000000,
67 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
68 .boot_params = 0xa0000100,
69 .map_io = pxa_map_io,
70 .init_irq = pxa25x_init_irq,
71 .fixup = eseries_fixup,
72 .timer = &pxa_timer,
73MACHINE_END
74#endif
75
76#ifdef CONFIG_MACH_E400
77MACHINE_START(E400, "Toshiba e400")
78 /* Maintainer: Ian Molton (spyro@f2s.com) */
79 .phys_io = 0x40000000,
80 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
81 .boot_params = 0xa0000100,
82 .map_io = pxa_map_io,
83 .init_irq = pxa25x_init_irq,
84 .fixup = eseries_fixup,
85 .timer = &pxa_timer,
86MACHINE_END
87#endif
88
89#ifdef CONFIG_MACH_E800
90MACHINE_START(E800, "Toshiba e800")
91 /* Maintainer: Ian Molton (spyro@f2s.com) */
92 .phys_io = 0x40000000,
93 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
94 .boot_params = 0xa0000100,
95 .map_io = pxa_map_io,
96 .init_irq = pxa25x_init_irq,
97 .fixup = eseries_fixup,
98 .timer = &pxa_timer,
99MACHINE_END
100#endif
101
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 1c34946ee16e..698aeec52961 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -20,7 +20,6 @@
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/platform_device.h>
24#include <linux/ioport.h> 23#include <linux/ioport.h>
25#include <linux/pm.h> 24#include <linux/pm.h>
26#include <linux/string.h> 25#include <linux/string.h>
@@ -33,13 +32,7 @@
33 32
34#include <asm/arch/pxa-regs.h> 33#include <asm/arch/pxa-regs.h>
35#include <asm/arch/gpio.h> 34#include <asm/arch/gpio.h>
36#include <asm/arch/udc.h>
37#include <asm/arch/pxafb.h>
38#include <asm/arch/mmc.h>
39#include <asm/arch/irda.h>
40#include <asm/arch/i2c.h>
41 35
42#include "devices.h"
43#include "generic.h" 36#include "generic.h"
44 37
45/* 38/*
@@ -203,7 +196,7 @@ static struct map_desc standard_io_desc[] __initdata = {
203 }, { /* Mem Ctl */ 196 }, { /* Mem Ctl */
204 .virtual = 0xf6000000, 197 .virtual = 0xf6000000,
205 .pfn = __phys_to_pfn(0x48000000), 198 .pfn = __phys_to_pfn(0x48000000),
206 .length = 0x00100000, 199 .length = 0x00200000,
207 .type = MT_DEVICE 200 .type = MT_DEVICE
208 }, { /* USB host */ 201 }, { /* USB host */
209 .virtual = 0xf8000000, 202 .virtual = 0xf8000000,
@@ -233,245 +226,3 @@ void __init pxa_map_io(void)
233 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 226 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
234 get_clk_frequency_khz(1); 227 get_clk_frequency_khz(1);
235} 228}
236
237
238static struct resource pxamci_resources[] = {
239 [0] = {
240 .start = 0x41100000,
241 .end = 0x41100fff,
242 .flags = IORESOURCE_MEM,
243 },
244 [1] = {
245 .start = IRQ_MMC,
246 .end = IRQ_MMC,
247 .flags = IORESOURCE_IRQ,
248 },
249};
250
251static u64 pxamci_dmamask = 0xffffffffUL;
252
253struct platform_device pxa_device_mci = {
254 .name = "pxa2xx-mci",
255 .id = -1,
256 .dev = {
257 .dma_mask = &pxamci_dmamask,
258 .coherent_dma_mask = 0xffffffff,
259 },
260 .num_resources = ARRAY_SIZE(pxamci_resources),
261 .resource = pxamci_resources,
262};
263
264void __init pxa_set_mci_info(struct pxamci_platform_data *info)
265{
266 pxa_device_mci.dev.platform_data = info;
267}
268
269
270static struct pxa2xx_udc_mach_info pxa_udc_info;
271
272void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
273{
274 memcpy(&pxa_udc_info, info, sizeof *info);
275}
276
277static struct resource pxa2xx_udc_resources[] = {
278 [0] = {
279 .start = 0x40600000,
280 .end = 0x4060ffff,
281 .flags = IORESOURCE_MEM,
282 },
283 [1] = {
284 .start = IRQ_USB,
285 .end = IRQ_USB,
286 .flags = IORESOURCE_IRQ,
287 },
288};
289
290static u64 udc_dma_mask = ~(u32)0;
291
292struct platform_device pxa_device_udc = {
293 .name = "pxa2xx-udc",
294 .id = -1,
295 .resource = pxa2xx_udc_resources,
296 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
297 .dev = {
298 .platform_data = &pxa_udc_info,
299 .dma_mask = &udc_dma_mask,
300 }
301};
302
303static struct resource pxafb_resources[] = {
304 [0] = {
305 .start = 0x44000000,
306 .end = 0x4400ffff,
307 .flags = IORESOURCE_MEM,
308 },
309 [1] = {
310 .start = IRQ_LCD,
311 .end = IRQ_LCD,
312 .flags = IORESOURCE_IRQ,
313 },
314};
315
316static u64 fb_dma_mask = ~(u64)0;
317
318struct platform_device pxa_device_fb = {
319 .name = "pxa2xx-fb",
320 .id = -1,
321 .dev = {
322 .dma_mask = &fb_dma_mask,
323 .coherent_dma_mask = 0xffffffff,
324 },
325 .num_resources = ARRAY_SIZE(pxafb_resources),
326 .resource = pxafb_resources,
327};
328
329void __init set_pxa_fb_info(struct pxafb_mach_info *info)
330{
331 pxa_device_fb.dev.platform_data = info;
332}
333
334void __init set_pxa_fb_parent(struct device *parent_dev)
335{
336 pxa_device_fb.dev.parent = parent_dev;
337}
338
339static struct resource pxa_resource_ffuart[] = {
340 {
341 .start = __PREG(FFUART),
342 .end = __PREG(FFUART) + 35,
343 .flags = IORESOURCE_MEM,
344 }, {
345 .start = IRQ_FFUART,
346 .end = IRQ_FFUART,
347 .flags = IORESOURCE_IRQ,
348 }
349};
350
351struct platform_device pxa_device_ffuart= {
352 .name = "pxa2xx-uart",
353 .id = 0,
354 .resource = pxa_resource_ffuart,
355 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
356};
357
358static struct resource pxa_resource_btuart[] = {
359 {
360 .start = __PREG(BTUART),
361 .end = __PREG(BTUART) + 35,
362 .flags = IORESOURCE_MEM,
363 }, {
364 .start = IRQ_BTUART,
365 .end = IRQ_BTUART,
366 .flags = IORESOURCE_IRQ,
367 }
368};
369
370struct platform_device pxa_device_btuart = {
371 .name = "pxa2xx-uart",
372 .id = 1,
373 .resource = pxa_resource_btuart,
374 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
375};
376
377static struct resource pxa_resource_stuart[] = {
378 {
379 .start = __PREG(STUART),
380 .end = __PREG(STUART) + 35,
381 .flags = IORESOURCE_MEM,
382 }, {
383 .start = IRQ_STUART,
384 .end = IRQ_STUART,
385 .flags = IORESOURCE_IRQ,
386 }
387};
388
389struct platform_device pxa_device_stuart = {
390 .name = "pxa2xx-uart",
391 .id = 2,
392 .resource = pxa_resource_stuart,
393 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
394};
395
396static struct resource pxa_resource_hwuart[] = {
397 {
398 .start = __PREG(HWUART),
399 .end = __PREG(HWUART) + 47,
400 .flags = IORESOURCE_MEM,
401 }, {
402 .start = IRQ_HWUART,
403 .end = IRQ_HWUART,
404 .flags = IORESOURCE_IRQ,
405 }
406};
407
408struct platform_device pxa_device_hwuart = {
409 .name = "pxa2xx-uart",
410 .id = 3,
411 .resource = pxa_resource_hwuart,
412 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
413};
414
415static struct resource pxai2c_resources[] = {
416 {
417 .start = 0x40301680,
418 .end = 0x403016a3,
419 .flags = IORESOURCE_MEM,
420 }, {
421 .start = IRQ_I2C,
422 .end = IRQ_I2C,
423 .flags = IORESOURCE_IRQ,
424 },
425};
426
427struct platform_device pxa_device_i2c = {
428 .name = "pxa2xx-i2c",
429 .id = 0,
430 .resource = pxai2c_resources,
431 .num_resources = ARRAY_SIZE(pxai2c_resources),
432};
433
434void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
435{
436 pxa_device_i2c.dev.platform_data = info;
437}
438
439static struct resource pxai2s_resources[] = {
440 {
441 .start = 0x40400000,
442 .end = 0x40400083,
443 .flags = IORESOURCE_MEM,
444 }, {
445 .start = IRQ_I2S,
446 .end = IRQ_I2S,
447 .flags = IORESOURCE_IRQ,
448 },
449};
450
451struct platform_device pxa_device_i2s = {
452 .name = "pxa2xx-i2s",
453 .id = -1,
454 .resource = pxai2s_resources,
455 .num_resources = ARRAY_SIZE(pxai2s_resources),
456};
457
458static u64 pxaficp_dmamask = ~(u32)0;
459
460struct platform_device pxa_device_ficp = {
461 .name = "pxa2xx-ir",
462 .id = -1,
463 .dev = {
464 .dma_mask = &pxaficp_dmamask,
465 .coherent_dma_mask = 0xffffffff,
466 },
467};
468
469void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
470{
471 pxa_device_ficp.dev.platform_data = info;
472}
473
474struct platform_device pxa_device_rtc = {
475 .name = "sa1100-rtc",
476 .id = -1,
477};
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 465108da2851..0a9434432c55 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -54,7 +54,7 @@ static struct resource smc91x_resources[] = {
54 [1] = { 54 [1] = {
55 .start = IRQ_GPIO(4), 55 .start = IRQ_GPIO(4),
56 .end = IRQ_GPIO(4), 56 .end = IRQ_GPIO(4),
57 .flags = IORESOURCE_IRQ, 57 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
58 } 58 }
59}; 59};
60 60
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
new file mode 100644
index 000000000000..0a4b54c21314
--- /dev/null
+++ b/arch/arm/mach-pxa/littleton.c
@@ -0,0 +1,325 @@
1/*
2 * linux/arch/arm/mach-pxa/littleton.c
3 *
4 * Support for the Marvell Littleton Development Platform.
5 *
6 * Author: Jason Chagas (largely modified code)
7 * Created: Nov 20, 2006
8 * Copyright: (C) Copyright 2006 Marvell International Ltd.
9 *
10 * 2007-11-22 modified to align with latest kernel
11 * eric miao <eric.miao@marvell.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * publishhed by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/platform_device.h>
22#include <linux/clk.h>
23
24#include <asm/types.h>
25#include <asm/setup.h>
26#include <asm/memory.h>
27#include <asm/mach-types.h>
28#include <asm/hardware.h>
29#include <asm/irq.h>
30
31#include <asm/mach/arch.h>
32#include <asm/mach/map.h>
33#include <asm/mach/irq.h>
34
35#include <asm/arch/pxa-regs.h>
36#include <asm/arch/mfp-pxa300.h>
37#include <asm/arch/gpio.h>
38#include <asm/arch/pxafb.h>
39#include <asm/arch/ssp.h>
40#include <asm/arch/littleton.h>
41
42#include "generic.h"
43
44#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
45
46/* Littleton MFP configurations */
47static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
48 /* LCD */
49 GPIO54_LCD_LDD_0,
50 GPIO55_LCD_LDD_1,
51 GPIO56_LCD_LDD_2,
52 GPIO57_LCD_LDD_3,
53 GPIO58_LCD_LDD_4,
54 GPIO59_LCD_LDD_5,
55 GPIO60_LCD_LDD_6,
56 GPIO61_LCD_LDD_7,
57 GPIO62_LCD_LDD_8,
58 GPIO63_LCD_LDD_9,
59 GPIO64_LCD_LDD_10,
60 GPIO65_LCD_LDD_11,
61 GPIO66_LCD_LDD_12,
62 GPIO67_LCD_LDD_13,
63 GPIO68_LCD_LDD_14,
64 GPIO69_LCD_LDD_15,
65 GPIO70_LCD_LDD_16,
66 GPIO71_LCD_LDD_17,
67 GPIO72_LCD_FCLK,
68 GPIO73_LCD_LCLK,
69 GPIO74_LCD_PCLK,
70 GPIO75_LCD_BIAS,
71
72 /* SSP2 */
73 GPIO25_SSP2_SCLK,
74 GPIO17_SSP2_FRM,
75 GPIO27_SSP2_TXD,
76
77 /* Debug Ethernet */
78 GPIO90_GPIO,
79};
80
81static struct resource smc91x_resources[] = {
82 [0] = {
83 .start = (LITTLETON_ETH_PHYS + 0x300),
84 .end = (LITTLETON_ETH_PHYS + 0xfffff),
85 .flags = IORESOURCE_MEM,
86 },
87 [1] = {
88 .start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
89 .end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
90 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
91 }
92};
93
94static struct platform_device smc91x_device = {
95 .name = "smc91x",
96 .id = 0,
97 .num_resources = ARRAY_SIZE(smc91x_resources),
98 .resource = smc91x_resources,
99};
100
101#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULES)
102/* use bit 30, 31 as the indicator of command parameter number */
103#define CMD0(x) ((0x00000000) | ((x) << 9))
104#define CMD1(x, x1) ((0x40000000) | ((x) << 9) | 0x100 | (x1))
105#define CMD2(x, x1, x2) ((0x80000000) | ((x) << 18) | 0x20000 |\
106 ((x1) << 9) | 0x100 | (x2))
107
108static uint32_t lcd_panel_reset[] = {
109 CMD0(0x1), /* reset */
110 CMD0(0x0), /* nop */
111 CMD0(0x0), /* nop */
112 CMD0(0x0), /* nop */
113};
114
115static uint32_t lcd_panel_on[] = {
116 CMD0(0x29), /* Display ON */
117 CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
118 CMD0(0x11), /* Sleep out */
119 CMD1(0xB0, 0x16), /* Wake */
120};
121
122static uint32_t lcd_panel_off[] = {
123 CMD0(0x28), /* Display OFF */
124 CMD2(0xB8, 0x80, 0x02), /* Output Control */
125 CMD0(0x10), /* Sleep in */
126 CMD1(0xB0, 0x00), /* Deep stand by in */
127};
128
129static uint32_t lcd_vga_pass_through[] = {
130 CMD1(0xB0, 0x16),
131 CMD1(0xBC, 0x80),
132 CMD1(0xE1, 0x00),
133 CMD1(0x36, 0x50),
134 CMD1(0x3B, 0x00),
135};
136
137static uint32_t lcd_qvga_pass_through[] = {
138 CMD1(0xB0, 0x16),
139 CMD1(0xBC, 0x81),
140 CMD1(0xE1, 0x00),
141 CMD1(0x36, 0x50),
142 CMD1(0x3B, 0x22),
143};
144
145static uint32_t lcd_vga_transfer[] = {
146 CMD1(0xcf, 0x02), /* Blanking period control (1) */
147 CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
148 CMD1(0xd1, 0x01), /* CKV timing control on/off */
149 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
150 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
151 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
152 CMD1(0xd5, 0x14), /* ASW timing control (2) */
153 CMD0(0x21), /* Invert for normally black display */
154 CMD0(0x29), /* Display on */
155};
156
157static uint32_t lcd_qvga_transfer[] = {
158 CMD1(0xd6, 0x02), /* Blanking period control (1) */
159 CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
160 CMD1(0xd8, 0x01), /* CKV timing control on/off */
161 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
162 CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
163 CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
164 CMD1(0xe0, 0x0a), /* ASW timing control (2) */
165 CMD0(0x21), /* Invert for normally black display */
166 CMD0(0x29), /* Display on */
167};
168
169static uint32_t lcd_panel_config[] = {
170 CMD2(0xb8, 0xff, 0xf9), /* Output control */
171 CMD0(0x11), /* sleep out */
172 CMD1(0xba, 0x01), /* Display mode (1) */
173 CMD1(0xbb, 0x00), /* Display mode (2) */
174 CMD1(0x3a, 0x60), /* Display mode 18-bit RGB */
175 CMD1(0xbf, 0x10), /* Drive system change control */
176 CMD1(0xb1, 0x56), /* Booster operation setup */
177 CMD1(0xb2, 0x33), /* Booster mode setup */
178 CMD1(0xb3, 0x11), /* Booster frequency setup */
179 CMD1(0xb4, 0x02), /* Op amp/system clock */
180 CMD1(0xb5, 0x35), /* VCS voltage */
181 CMD1(0xb6, 0x40), /* VCOM voltage */
182 CMD1(0xb7, 0x03), /* External display signal */
183 CMD1(0xbd, 0x00), /* ASW slew rate */
184 CMD1(0xbe, 0x00), /* Dummy data for QuadData operation */
185 CMD1(0xc0, 0x11), /* Sleep out FR count (A) */
186 CMD1(0xc1, 0x11), /* Sleep out FR count (B) */
187 CMD1(0xc2, 0x11), /* Sleep out FR count (C) */
188 CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */
189 CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */
190 CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */
191 CMD1(0xc6, 0xc0), /* Sleep out FR count (G) */
192 CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */
193 CMD1(0xc8, 0x44), /* Gamma 1 fine tuning (2) */
194 CMD1(0xc9, 0x33), /* Gamma 1 inclination adjustment */
195 CMD1(0xca, 0x00), /* Gamma 1 blue offset adjustment */
196 CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */
197};
198
199static void ssp_reconfig(struct ssp_dev *dev, int nparam)
200{
201 static int last_nparam = -1;
202
203 /* check if it is necessary to re-config SSP */
204 if (nparam == last_nparam)
205 return;
206
207 ssp_disable(dev);
208 ssp_config(dev, (nparam == 2) ? 0x0010058a : 0x00100581, 0x18, 0, 0);
209
210 last_nparam = nparam;
211}
212
213static void ssp_send_cmd(uint32_t *cmd, int num)
214{
215 static int ssp_initialized;
216 static struct ssp_dev ssp2;
217
218 int i;
219
220 if (!ssp_initialized) {
221 ssp_init(&ssp2, 2, SSP_NO_IRQ);
222 ssp_initialized = 1;
223 }
224
225 clk_enable(ssp2.ssp->clk);
226 for (i = 0; i < num; i++, cmd++) {
227 ssp_reconfig(&ssp2, (*cmd >> 30) & 0x3);
228 ssp_write_word(&ssp2, *cmd & 0x3fffffff);
229
230 /* FIXME: ssp_flush() is mandatory here to work */
231 ssp_flush(&ssp2);
232 }
233 clk_disable(ssp2.ssp->clk);
234}
235
236static void littleton_lcd_power(int on, struct fb_var_screeninfo *var)
237{
238 if (on) {
239 ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_on));
240 ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_reset));
241 if (var->xres > 240) {
242 /* VGA */
243 ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_pass_through));
244 ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
245 ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_transfer));
246 } else {
247 /* QVGA */
248 ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_pass_through));
249 ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
250 ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_transfer));
251 }
252 } else
253 ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_off));
254}
255
256static struct pxafb_mode_info tpo_tdo24mtea1_modes[] = {
257 [0] = {
258 /* VGA */
259 .pixclock = 38250,
260 .xres = 480,
261 .yres = 640,
262 .bpp = 16,
263 .hsync_len = 8,
264 .left_margin = 8,
265 .right_margin = 24,
266 .vsync_len = 2,
267 .upper_margin = 2,
268 .lower_margin = 4,
269 .sync = 0,
270 },
271 [1] = {
272 /* QVGA */
273 .pixclock = 153000,
274 .xres = 240,
275 .yres = 320,
276 .bpp = 16,
277 .hsync_len = 8,
278 .left_margin = 8,
279 .right_margin = 88,
280 .vsync_len = 2,
281 .upper_margin = 2,
282 .lower_margin = 2,
283 .sync = 0,
284 },
285};
286
287static struct pxafb_mach_info littleton_lcd_info = {
288 .modes = tpo_tdo24mtea1_modes,
289 .num_modes = 2,
290 .lccr0 = LCCR0_Act,
291 .lccr3 = LCCR3_HSP | LCCR3_VSP,
292 .pxafb_lcd_power = littleton_lcd_power,
293};
294
295static void littleton_init_lcd(void)
296{
297 set_pxa_fb_info(&littleton_lcd_info);
298}
299#else
300static inline void littleton_init_lcd(void) {};
301#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULES */
302
303static void __init littleton_init(void)
304{
305 /* initialize MFP configurations */
306 pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg));
307
308 /*
309 * Note: we depend bootloader set the correct
310 * value to MSC register for SMC91x.
311 */
312 platform_device_register(&smc91x_device);
313
314 littleton_init_lcd();
315}
316
317MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
318 .phys_io = 0x40000000,
319 .boot_params = 0xa0000100,
320 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
321 .map_io = pxa_map_io,
322 .init_irq = pxa3xx_init_irq,
323 .timer = &pxa_timer,
324 .init_machine = littleton_init,
325MACHINE_END
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 78ebad063cba..afa62ffe3ad5 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -38,6 +38,7 @@
38#include <asm/mach/flash.h> 38#include <asm/mach/flash.h>
39 39
40#include <asm/arch/pxa-regs.h> 40#include <asm/arch/pxa-regs.h>
41#include <asm/arch/pxa2xx-regs.h>
41#include <asm/arch/lpd270.h> 42#include <asm/arch/lpd270.h>
42#include <asm/arch/audio.h> 43#include <asm/arch/audio.h>
43#include <asm/arch/pxafb.h> 44#include <asm/arch/pxafb.h>
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 1d3112dc629e..e7ae4bb3e361 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -41,6 +41,7 @@
41#include <asm/hardware/sa1111.h> 41#include <asm/hardware/sa1111.h>
42 42
43#include <asm/arch/pxa-regs.h> 43#include <asm/arch/pxa-regs.h>
44#include <asm/arch/pxa2xx-regs.h>
44#include <asm/arch/lubbock.h> 45#include <asm/arch/lubbock.h>
45#include <asm/arch/udc.h> 46#include <asm/arch/udc.h>
46#include <asm/arch/irda.h> 47#include <asm/arch/irda.h>
@@ -136,9 +137,13 @@ static struct sys_device lubbock_irq_device = {
136 137
137static int __init lubbock_irq_device_init(void) 138static int __init lubbock_irq_device_init(void)
138{ 139{
139 int ret = sysdev_class_register(&lubbock_irq_sysclass); 140 int ret = -ENODEV;
140 if (ret == 0) 141
141 ret = sysdev_register(&lubbock_irq_device); 142 if (machine_is_lubbock()) {
143 ret = sysdev_class_register(&lubbock_irq_sysclass);
144 if (ret == 0)
145 ret = sysdev_register(&lubbock_irq_device);
146 }
142 return ret; 147 return ret;
143} 148}
144 149
@@ -191,7 +196,7 @@ static struct resource smc91x_resources[] = {
191 [1] = { 196 [1] = {
192 .start = LUBBOCK_ETH_IRQ, 197 .start = LUBBOCK_ETH_IRQ,
193 .end = LUBBOCK_ETH_IRQ, 198 .end = LUBBOCK_ETH_IRQ,
194 .flags = IORESOURCE_IRQ, 199 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
195 }, 200 },
196 [2] = { 201 [2] = {
197 .name = "smc91x-attrib", 202 .name = "smc91x-attrib",
@@ -206,30 +211,13 @@ static struct resource smc91x_resources[] = {
206 * (to J5) and poking board registers (as done below). Else it's only useful 211 * (to J5) and poking board registers (as done below). Else it's only useful
207 * for the temperature sensors. 212 * for the temperature sensors.
208 */ 213 */
209static struct resource pxa_ssp_resources[] = {
210 [0] = {
211 .start = __PREG(SSCR0_P(1)),
212 .end = __PREG(SSCR0_P(1)) + 0x14,
213 .flags = IORESOURCE_MEM,
214 },
215 [1] = {
216 .start = IRQ_SSP,
217 .end = IRQ_SSP,
218 .flags = IORESOURCE_IRQ,
219 },
220};
221
222static struct pxa2xx_spi_master pxa_ssp_master_info = { 214static struct pxa2xx_spi_master pxa_ssp_master_info = {
223 .ssp_type = PXA25x_SSP,
224 .clock_enable = CKEN_SSP,
225 .num_chipselect = 0, 215 .num_chipselect = 0,
226}; 216};
227 217
228static struct platform_device pxa_ssp = { 218static struct platform_device pxa_ssp = {
229 .name = "pxa2xx-spi", 219 .name = "pxa2xx-spi",
230 .id = 1, 220 .id = 1,
231 .resource = pxa_ssp_resources,
232 .num_resources = ARRAY_SIZE(pxa_ssp_resources),
233 .dev = { 221 .dev = {
234 .platform_data = &pxa_ssp_master_info, 222 .platform_data = &pxa_ssp_master_info,
235 }, 223 },
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
new file mode 100644
index 000000000000..d98ef7ada2f8
--- /dev/null
+++ b/arch/arm/mach-pxa/magician.c
@@ -0,0 +1,218 @@
1/*
2 * Support for HTC Magician PDA phones:
3 * i-mate JAM, O2 Xda mini, Orange SPV M500, Qtek s100, Qtek s110
4 * and T-Mobile MDA Compact.
5 *
6 * Copyright (c) 2006-2007 Philipp Zabel
7 *
8 * Based on hx4700.c, spitz.c and others.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/gpio_keys.h>
20#include <linux/input.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/map.h>
23#include <linux/mtd/physmap.h>
24
25#include <asm/gpio.h>
26#include <asm/hardware.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/arch/magician.h>
30#include <asm/arch/pxa-regs.h>
31#include <asm/arch/pxafb.h>
32#include <asm/arch/irda.h>
33#include <asm/arch/ohci.h>
34
35#include "generic.h"
36
37/*
38 * IRDA
39 */
40
41static void magician_irda_transceiver_mode(struct device *dev, int mode)
42{
43 gpio_set_value(GPIO83_MAGICIAN_nIR_EN, mode & IR_OFF);
44}
45
46static struct pxaficp_platform_data magician_ficp_info = {
47 .transceiver_cap = IR_SIRMODE | IR_OFF,
48 .transceiver_mode = magician_irda_transceiver_mode,
49};
50
51/*
52 * GPIO Keys
53 */
54
55static struct gpio_keys_button magician_button_table[] = {
56 {KEY_POWER, GPIO0_MAGICIAN_KEY_POWER, 0, "Power button"},
57 {KEY_ESC, GPIO37_MAGICIAN_KEY_HANGUP, 0, "Hangup button"},
58 {KEY_F10, GPIO38_MAGICIAN_KEY_CONTACTS, 0, "Contacts button"},
59 {KEY_CALENDAR, GPIO90_MAGICIAN_KEY_CALENDAR, 0, "Calendar button"},
60 {KEY_CAMERA, GPIO91_MAGICIAN_KEY_CAMERA, 0, "Camera button"},
61 {KEY_UP, GPIO93_MAGICIAN_KEY_UP, 0, "Up button"},
62 {KEY_DOWN, GPIO94_MAGICIAN_KEY_DOWN, 0, "Down button"},
63 {KEY_LEFT, GPIO95_MAGICIAN_KEY_LEFT, 0, "Left button"},
64 {KEY_RIGHT, GPIO96_MAGICIAN_KEY_RIGHT, 0, "Right button"},
65 {KEY_KPENTER, GPIO97_MAGICIAN_KEY_ENTER, 0, "Action button"},
66 {KEY_RECORD, GPIO98_MAGICIAN_KEY_RECORD, 0, "Record button"},
67 {KEY_VOLUMEUP, GPIO100_MAGICIAN_KEY_VOL_UP, 0, "Volume up"},
68 {KEY_VOLUMEDOWN, GPIO101_MAGICIAN_KEY_VOL_DOWN, 0, "Volume down"},
69 {KEY_PHONE, GPIO102_MAGICIAN_KEY_PHONE, 0, "Phone button"},
70 {KEY_PLAY, GPIO99_MAGICIAN_HEADPHONE_IN, 0, "Headset button"},
71};
72
73static struct gpio_keys_platform_data gpio_keys_data = {
74 .buttons = magician_button_table,
75 .nbuttons = ARRAY_SIZE(magician_button_table),
76};
77
78static struct platform_device gpio_keys = {
79 .name = "gpio-keys",
80 .dev = {
81 .platform_data = &gpio_keys_data,
82 },
83 .id = -1,
84};
85
86/*
87 * LCD - Toppoly TD028STEB1
88 */
89
90static struct pxafb_mode_info toppoly_modes[] = {
91 {
92 .pixclock = 96153,
93 .bpp = 16,
94 .xres = 240,
95 .yres = 320,
96 .hsync_len = 11,
97 .vsync_len = 3,
98 .left_margin = 19,
99 .upper_margin = 2,
100 .right_margin = 10,
101 .lower_margin = 2,
102 .sync = 0,
103 },
104};
105
106static struct pxafb_mach_info toppoly_info = {
107 .modes = toppoly_modes,
108 .num_modes = 1,
109 .fixed_modes = 1,
110 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
111 .lccr3 = LCCR3_PixRsEdg,
112};
113
114/*
115 * Backlight
116 */
117
118static void magician_set_bl_intensity(int intensity)
119{
120 if (intensity) {
121 PWM_CTRL0 = 1;
122 PWM_PERVAL0 = 0xc8;
123 PWM_PWDUTY0 = intensity;
124 pxa_set_cken(CKEN_PWM0, 1);
125 } else {
126 pxa_set_cken(CKEN_PWM0, 0);
127 }
128}
129
130static struct generic_bl_info backlight_info = {
131 .default_intensity = 0x64,
132 .limit_mask = 0x0b,
133 .max_intensity = 0xc7,
134 .set_bl_intensity = magician_set_bl_intensity,
135};
136
137static struct platform_device backlight = {
138 .name = "corgi-bl",
139 .dev = {
140 .platform_data = &backlight_info,
141 },
142 .id = -1,
143};
144
145
146/*
147 * USB OHCI
148 */
149
150static int magician_ohci_init(struct device *dev)
151{
152 UHCHR = (UHCHR | UHCHR_SSEP2 | UHCHR_PCPL | UHCHR_CGR) &
153 ~(UHCHR_SSEP1 | UHCHR_SSEP3 | UHCHR_SSE);
154
155 return 0;
156}
157
158static struct pxaohci_platform_data magician_ohci_info = {
159 .port_mode = PMM_PERPORT_MODE,
160 .init = magician_ohci_init,
161 .power_budget = 0,
162};
163
164
165/*
166 * StrataFlash
167 */
168
169#define PXA_CS_SIZE 0x04000000
170
171static struct resource strataflash_resource = {
172 .start = PXA_CS0_PHYS,
173 .end = PXA_CS0_PHYS + PXA_CS_SIZE - 1,
174 .flags = IORESOURCE_MEM,
175};
176
177static struct physmap_flash_data strataflash_data = {
178 .width = 4,
179};
180
181static struct platform_device strataflash = {
182 .name = "physmap-flash",
183 .id = -1,
184 .num_resources = 1,
185 .resource = &strataflash_resource,
186 .dev = {
187 .platform_data = &strataflash_data,
188 },
189};
190
191/*
192 * Platform devices
193 */
194
195static struct platform_device *devices[] __initdata = {
196 &gpio_keys,
197 &backlight,
198 &strataflash,
199};
200
201static void __init magician_init(void)
202{
203 platform_add_devices(devices, ARRAY_SIZE(devices));
204 pxa_set_ohci_info(&magician_ohci_info);
205 pxa_set_ficp_info(&magician_ficp_info);
206 set_pxa_fb_info(&toppoly_info);
207}
208
209
210MACHINE_START(MAGICIAN, "HTC Magician")
211 .phys_io = 0x40000000,
212 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
213 .boot_params = 0xa0000100,
214 .map_io = pxa_map_io,
215 .init_irq = pxa27x_init_irq,
216 .init_machine = magician_init,
217 .timer = &pxa_timer,
218MACHINE_END
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 41d8c6cea62b..345c3deeb02e 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -23,6 +23,7 @@
23#include <linux/ioport.h> 23#include <linux/ioport.h>
24#include <linux/mtd/mtd.h> 24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h> 25#include <linux/mtd/partitions.h>
26#include <linux/backlight.h>
26 27
27#include <asm/types.h> 28#include <asm/types.h>
28#include <asm/setup.h> 29#include <asm/setup.h>
@@ -38,6 +39,7 @@
38#include <asm/mach/flash.h> 39#include <asm/mach/flash.h>
39 40
40#include <asm/arch/pxa-regs.h> 41#include <asm/arch/pxa-regs.h>
42#include <asm/arch/pxa2xx-regs.h>
41#include <asm/arch/mainstone.h> 43#include <asm/arch/mainstone.h>
42#include <asm/arch/audio.h> 44#include <asm/arch/audio.h>
43#include <asm/arch/pxafb.h> 45#include <asm/arch/pxafb.h>
@@ -130,9 +132,13 @@ static struct sys_device mainstone_irq_device = {
130 132
131static int __init mainstone_irq_device_init(void) 133static int __init mainstone_irq_device_init(void)
132{ 134{
133 int ret = sysdev_class_register(&mainstone_irq_sysclass); 135 int ret = -ENODEV;
134 if (ret == 0) 136
135 ret = sysdev_register(&mainstone_irq_device); 137 if (machine_is_mainstone()) {
138 ret = sysdev_class_register(&mainstone_irq_sysclass);
139 if (ret == 0)
140 ret = sysdev_register(&mainstone_irq_device);
141 }
136 return ret; 142 return ret;
137} 143}
138 144
@@ -150,7 +156,7 @@ static struct resource smc91x_resources[] = {
150 [1] = { 156 [1] = {
151 .start = MAINSTONE_IRQ(3), 157 .start = MAINSTONE_IRQ(3),
152 .end = MAINSTONE_IRQ(3), 158 .end = MAINSTONE_IRQ(3),
153 .flags = IORESOURCE_IRQ, 159 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
154 } 160 }
155}; 161};
156 162
@@ -263,21 +269,60 @@ static struct platform_device mst_flash_device[2] = {
263 }, 269 },
264}; 270};
265 271
266static void mainstone_backlight_power(int on) 272#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
273static int mainstone_backlight_update_status(struct backlight_device *bl)
267{ 274{
268 if (on) { 275 int brightness = bl->props.brightness;
276
277 if (bl->props.power != FB_BLANK_UNBLANK ||
278 bl->props.fb_blank != FB_BLANK_UNBLANK)
279 brightness = 0;
280
281 if (brightness != 0) {
269 pxa_gpio_mode(GPIO16_PWM0_MD); 282 pxa_gpio_mode(GPIO16_PWM0_MD);
270 pxa_set_cken(CKEN_PWM0, 1); 283 pxa_set_cken(CKEN_PWM0, 1);
271 PWM_CTRL0 = 0; 284 }
272 PWM_PWDUTY0 = 0x3ff; 285 PWM_CTRL0 = 0;
273 PWM_PERVAL0 = 0x3ff; 286 PWM_PWDUTY0 = brightness;
274 } else { 287 PWM_PERVAL0 = bl->props.max_brightness;
275 PWM_CTRL0 = 0; 288 if (brightness == 0)
276 PWM_PWDUTY0 = 0x0;
277 PWM_PERVAL0 = 0x3FF;
278 pxa_set_cken(CKEN_PWM0, 0); 289 pxa_set_cken(CKEN_PWM0, 0);
290 return 0; /* pointless return value */
291}
292
293static int mainstone_backlight_get_brightness(struct backlight_device *bl)
294{
295 return PWM_PWDUTY0;
296}
297
298static /*const*/ struct backlight_ops mainstone_backlight_ops = {
299 .update_status = mainstone_backlight_update_status,
300 .get_brightness = mainstone_backlight_get_brightness,
301};
302
303static void __init mainstone_backlight_register(void)
304{
305 struct backlight_device *bl;
306
307 bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev,
308 NULL, &mainstone_backlight_ops);
309 if (IS_ERR(bl)) {
310 printk(KERN_ERR "mainstone: unable to register backlight: %ld\n",
311 PTR_ERR(bl));
312 return;
279 } 313 }
314
315 /*
316 * broken design - register-then-setup interfaces are
317 * utterly broken by definition.
318 */
319 bl->props.max_brightness = 1023;
320 bl->props.brightness = 1023;
321 backlight_update_status(bl);
280} 322}
323#else
324#define mainstone_backlight_register() do { } while (0)
325#endif
281 326
282static struct pxafb_mode_info toshiba_ltm04c380k_mode = { 327static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
283 .pixclock = 50000, 328 .pixclock = 50000,
@@ -311,7 +356,6 @@ static struct pxafb_mach_info mainstone_pxafb_info = {
311 .num_modes = 1, 356 .num_modes = 1,
312 .lccr0 = LCCR0_Act, 357 .lccr0 = LCCR0_Act,
313 .lccr3 = LCCR3_PCP, 358 .lccr3 = LCCR3_PCP,
314 .pxafb_backlight_power = mainstone_backlight_power,
315}; 359};
316 360
317static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data) 361static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data)
@@ -335,12 +379,10 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in
335 379
336 err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED, 380 err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
337 "MMC card detect", data); 381 "MMC card detect", data);
338 if (err) { 382 if (err)
339 printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); 383 printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
340 return -1;
341 }
342 384
343 return 0; 385 return err;
344} 386}
345 387
346static void mainstone_mci_setpower(struct device *dev, unsigned int vdd) 388static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
@@ -473,6 +515,7 @@ static void __init mainstone_init(void)
473 mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode; 515 mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;
474 516
475 set_pxa_fb_info(&mainstone_pxafb_info); 517 set_pxa_fb_info(&mainstone_pxafb_info);
518 mainstone_backlight_register();
476 519
477 pxa_set_mci_info(&mainstone_mci_platform_data); 520 pxa_set_mci_info(&mainstone_mci_platform_data);
478 pxa_set_ficp_info(&mainstone_ficp_platform_data); 521 pxa_set_ficp_info(&mainstone_ficp_platform_data);
diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp.c
index 436f96574964..ec1b2d8f61c4 100644
--- a/arch/arm/mach-pxa/mfp.c
+++ b/arch/arm/mach-pxa/mfp.c
@@ -17,9 +17,11 @@
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/sysdev.h>
20 21
21#include <asm/hardware.h> 22#include <asm/hardware.h>
22#include <asm/arch/mfp.h> 23#include <asm/arch/mfp.h>
24#include <asm/arch/mfp-pxa3xx.h>
23 25
24/* mfp_spin_lock is used to ensure that MFP register configuration 26/* mfp_spin_lock is used to ensure that MFP register configuration
25 * (most likely a read-modify-write operation) is atomic, and that 27 * (most likely a read-modify-write operation) is atomic, and that
@@ -28,43 +30,110 @@
28static DEFINE_SPINLOCK(mfp_spin_lock); 30static DEFINE_SPINLOCK(mfp_spin_lock);
29 31
30static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE); 32static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE);
33
34struct pxa3xx_mfp_pin {
35 unsigned long config; /* -1 for not configured */
36 unsigned long mfpr_off; /* MFPRxx Register offset */
37 unsigned long mfpr_run; /* Run-Mode Register Value */
38 unsigned long mfpr_lpm; /* Low Power Mode Register Value */
39};
40
31static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX]; 41static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX];
32 42
43/* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */
44const static unsigned long mfpr_lpm[] = {
45 MFPR_LPM_INPUT,
46 MFPR_LPM_DRIVE_LOW,
47 MFPR_LPM_DRIVE_HIGH,
48 MFPR_LPM_PULL_LOW,
49 MFPR_LPM_PULL_HIGH,
50 MFPR_LPM_FLOAT,
51};
52
53/* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */
54const static unsigned long mfpr_pull[] = {
55 MFPR_PULL_NONE,
56 MFPR_PULL_LOW,
57 MFPR_PULL_HIGH,
58 MFPR_PULL_BOTH,
59};
60
61/* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */
62const static unsigned long mfpr_edge[] = {
63 MFPR_EDGE_NONE,
64 MFPR_EDGE_RISE,
65 MFPR_EDGE_FALL,
66 MFPR_EDGE_BOTH,
67};
68
33#define mfpr_readl(off) \ 69#define mfpr_readl(off) \
34 __raw_readl(mfpr_mmio_base + (off)) 70 __raw_readl(mfpr_mmio_base + (off))
35 71
36#define mfpr_writel(off, val) \ 72#define mfpr_writel(off, val) \
37 __raw_writel(val, mfpr_mmio_base + (off)) 73 __raw_writel(val, mfpr_mmio_base + (off))
38 74
75#define mfp_configured(p) ((p)->config != -1)
76
39/* 77/*
40 * perform a read-back of any MFPR register to make sure the 78 * perform a read-back of any MFPR register to make sure the
41 * previous writings are finished 79 * previous writings are finished
42 */ 80 */
43#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0) 81#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0)
44 82
45static inline void __mfp_config(int pin, unsigned long val) 83static inline void __mfp_config_run(struct pxa3xx_mfp_pin *p)
46{ 84{
47 unsigned long off = mfp_table[pin].mfpr_off; 85 if (mfp_configured(p))
86 mfpr_writel(p->mfpr_off, p->mfpr_run);
87}
48 88
49 mfp_table[pin].mfpr_val = val; 89static inline void __mfp_config_lpm(struct pxa3xx_mfp_pin *p)
50 mfpr_writel(off, val); 90{
91 if (mfp_configured(p)) {
92 unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR;
93 if (mfpr_clr != p->mfpr_run)
94 mfpr_writel(p->mfpr_off, mfpr_clr);
95 if (p->mfpr_lpm != mfpr_clr)
96 mfpr_writel(p->mfpr_off, p->mfpr_lpm);
97 }
51} 98}
52 99
53void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num) 100void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num)
54{ 101{
55 int i, pin; 102 unsigned long flags;
56 unsigned long val, flags; 103 int i;
57 mfp_cfg_t *mfp_cfg = mfp_cfgs;
58 104
59 spin_lock_irqsave(&mfp_spin_lock, flags); 105 spin_lock_irqsave(&mfp_spin_lock, flags);
60 106
61 for (i = 0; i < num; i++, mfp_cfg++) { 107 for (i = 0; i < num; i++, mfp_cfgs++) {
62 pin = MFP_CFG_PIN(*mfp_cfg); 108 unsigned long tmp, c = *mfp_cfgs;
63 val = MFP_CFG_VAL(*mfp_cfg); 109 struct pxa3xx_mfp_pin *p;
110 int pin, af, drv, lpm, edge, pull;
64 111
112 pin = MFP_PIN(c);
65 BUG_ON(pin >= MFP_PIN_MAX); 113 BUG_ON(pin >= MFP_PIN_MAX);
66 114 p = &mfp_table[pin];
67 __mfp_config(pin, val); 115
116 af = MFP_AF(c);
117 drv = MFP_DS(c);
118 lpm = MFP_LPM_STATE(c);
119 edge = MFP_LPM_EDGE(c);
120 pull = MFP_PULL(c);
121
122 /* run-mode pull settings will conflict with MFPR bits of
123 * low power mode state, calculate mfpr_run and mfpr_lpm
124 * individually if pull != MFP_PULL_NONE
125 */
126 tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv);
127
128 if (likely(pull == MFP_PULL_NONE)) {
129 p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
130 p->mfpr_lpm = p->mfpr_run;
131 } else {
132 p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
133 p->mfpr_run = tmp | mfpr_pull[pull];
134 }
135
136 p->config = c; __mfp_config_run(p);
68 } 137 }
69 138
70 mfpr_sync(); 139 mfpr_sync();
@@ -96,140 +165,82 @@ void pxa3xx_mfp_write(int mfp, unsigned long val)
96 spin_unlock_irqrestore(&mfp_spin_lock, flags); 165 spin_unlock_irqrestore(&mfp_spin_lock, flags);
97} 166}
98 167
99void pxa3xx_mfp_set_afds(int mfp, int af, int ds) 168void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map)
100{
101 uint32_t mfpr_off, mfpr_val;
102 unsigned long flags;
103
104 BUG_ON(mfp >= MFP_PIN_MAX);
105
106 spin_lock_irqsave(&mfp_spin_lock, flags);
107 mfpr_off = mfp_table[mfp].mfpr_off;
108
109 mfpr_val = mfpr_readl(mfpr_off);
110 mfpr_val &= ~(MFPR_AF_MASK | MFPR_DRV_MASK);
111 mfpr_val |= (((af & 0x7) << MFPR_ALT_OFFSET) |
112 ((ds & 0x7) << MFPR_DRV_OFFSET));
113
114 mfpr_writel(mfpr_off, mfpr_val);
115 mfpr_sync();
116
117 spin_unlock_irqrestore(&mfp_spin_lock, flags);
118}
119
120void pxa3xx_mfp_set_rdh(int mfp, int rdh)
121{ 169{
122 uint32_t mfpr_off, mfpr_val; 170 struct pxa3xx_mfp_addr_map *p;
123 unsigned long flags; 171 unsigned long offset, flags;
124 172 int i;
125 BUG_ON(mfp >= MFP_PIN_MAX);
126 173
127 spin_lock_irqsave(&mfp_spin_lock, flags); 174 spin_lock_irqsave(&mfp_spin_lock, flags);
128 175
129 mfpr_off = mfp_table[mfp].mfpr_off; 176 for (p = map; p->start != MFP_PIN_INVALID; p++) {
130 177 offset = p->offset;
131 mfpr_val = mfpr_readl(mfpr_off); 178 i = p->start;
132 mfpr_val &= ~MFPR_RDH_MASK;
133
134 if (likely(rdh))
135 mfpr_val |= (1u << MFPR_SS_OFFSET);
136 179
137 mfpr_writel(mfpr_off, mfpr_val); 180 do {
138 mfpr_sync(); 181 mfp_table[i].mfpr_off = offset;
182 mfp_table[i].mfpr_run = 0;
183 mfp_table[i].mfpr_lpm = 0;
184 offset += 4; i++;
185 } while ((i <= p->end) && (p->end != -1));
186 }
139 187
140 spin_unlock_irqrestore(&mfp_spin_lock, flags); 188 spin_unlock_irqrestore(&mfp_spin_lock, flags);
141} 189}
142 190
143void pxa3xx_mfp_set_lpm(int mfp, int lpm) 191void __init pxa3xx_init_mfp(void)
144{ 192{
145 uint32_t mfpr_off, mfpr_val; 193 int i;
146 unsigned long flags;
147
148 BUG_ON(mfp >= MFP_PIN_MAX);
149
150 spin_lock_irqsave(&mfp_spin_lock, flags);
151
152 mfpr_off = mfp_table[mfp].mfpr_off;
153 mfpr_val = mfpr_readl(mfpr_off);
154 mfpr_val &= ~MFPR_LPM_MASK;
155
156 if (lpm & 0x1) mfpr_val |= 1u << MFPR_SON_OFFSET;
157 if (lpm & 0x2) mfpr_val |= 1u << MFPR_SD_OFFSET;
158 if (lpm & 0x4) mfpr_val |= 1u << MFPR_PU_OFFSET;
159 if (lpm & 0x8) mfpr_val |= 1u << MFPR_PD_OFFSET;
160 if (lpm &0x10) mfpr_val |= 1u << MFPR_PS_OFFSET;
161
162 mfpr_writel(mfpr_off, mfpr_val);
163 mfpr_sync();
164 194
165 spin_unlock_irqrestore(&mfp_spin_lock, flags); 195 for (i = 0; i < ARRAY_SIZE(mfp_table); i++)
196 mfp_table[i].config = -1;
166} 197}
167 198
168void pxa3xx_mfp_set_pull(int mfp, int pull) 199#ifdef CONFIG_PM
200/*
201 * Configure the MFPs appropriately for suspend/resume.
202 * FIXME: this should probably depend on which system state we're
203 * entering - for instance, we might not want to place MFP pins in
204 * a pull-down mode if they're an active low chip select, and we're
205 * just entering standby.
206 */
207static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state)
169{ 208{
170 uint32_t mfpr_off, mfpr_val; 209 int pin;
171 unsigned long flags;
172
173 BUG_ON(mfp >= MFP_PIN_MAX);
174
175 spin_lock_irqsave(&mfp_spin_lock, flags);
176 210
177 mfpr_off = mfp_table[mfp].mfpr_off; 211 for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) {
178 mfpr_val = mfpr_readl(mfpr_off); 212 struct pxa3xx_mfp_pin *p = &mfp_table[pin];
179 mfpr_val &= ~MFPR_PULL_MASK; 213 __mfp_config_lpm(p);
180 mfpr_val |= ((pull & 0x7u) << MFPR_PD_OFFSET); 214 }
181 215 return 0;
182 mfpr_writel(mfpr_off, mfpr_val);
183 mfpr_sync();
184
185 spin_unlock_irqrestore(&mfp_spin_lock, flags);
186} 216}
187 217
188void pxa3xx_mfp_set_edge(int mfp, int edge) 218static int pxa3xx_mfp_resume(struct sys_device *d)
189{ 219{
190 uint32_t mfpr_off, mfpr_val; 220 int pin;
191 unsigned long flags;
192
193 BUG_ON(mfp >= MFP_PIN_MAX);
194
195 spin_lock_irqsave(&mfp_spin_lock, flags);
196
197 mfpr_off = mfp_table[mfp].mfpr_off;
198 mfpr_val = mfpr_readl(mfpr_off);
199
200 mfpr_val &= ~MFPR_EDGE_MASK;
201 mfpr_val |= (edge & 0x3u) << MFPR_ERE_OFFSET;
202 mfpr_val |= (!edge & 0x1) << MFPR_EC_OFFSET;
203 221
204 mfpr_writel(mfpr_off, mfpr_val); 222 for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) {
205 mfpr_sync(); 223 struct pxa3xx_mfp_pin *p = &mfp_table[pin];
206 224 __mfp_config_run(p);
207 spin_unlock_irqrestore(&mfp_spin_lock, flags); 225 }
226 return 0;
208} 227}
209 228
210void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map) 229static struct sysdev_class mfp_sysclass = {
211{ 230 set_kset_name("mfp"),
212 struct pxa3xx_mfp_addr_map *p; 231 .suspend = pxa3xx_mfp_suspend,
213 unsigned long offset, flags; 232 .resume = pxa3xx_mfp_resume,
214 int i; 233};
215
216 spin_lock_irqsave(&mfp_spin_lock, flags);
217
218 for (p = map; p->start != MFP_PIN_INVALID; p++) {
219 offset = p->offset;
220 i = p->start;
221
222 do {
223 mfp_table[i].mfpr_off = offset;
224 mfp_table[i].mfpr_val = 0;
225 offset += 4; i++;
226 } while ((i <= p->end) && (p->end != -1));
227 }
228 234
229 spin_unlock_irqrestore(&mfp_spin_lock, flags); 235static struct sys_device mfp_device = {
230} 236 .id = 0,
237 .cls = &mfp_sysclass,
238};
231 239
232void __init pxa3xx_init_mfp(void) 240static int __init mfp_init_devicefs(void)
233{ 241{
234 memset(mfp_table, 0, sizeof(mfp_table)); 242 sysdev_class_register(&mfp_sysclass);
243 return sysdev_register(&mfp_device);
235} 244}
245device_initcall(mfp_init_devicefs);
246#endif
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
new file mode 100644
index 000000000000..540c3bba5f9a
--- /dev/null
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -0,0 +1,216 @@
1/*
2 * linux/arch/arm/mach-pxa/pcm027.c
3 * Support for the Phytec phyCORE-PXA270 CPU card (aka PCM-027).
4 *
5 * Refer
6 * http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-XScale-PXA270.html
7 * for additional hardware info
8 *
9 * Author: Juergen Kilb
10 * Created: April 05, 2005
11 * Copyright: Phytec Messtechnik GmbH
12 * e-Mail: armlinux@phytec.de
13 *
14 * based on Intel Mainstone Board
15 *
16 * Copyright 2007 Juergen Beisert @ Pengutronix (j.beisert@pengutronix.de)
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/mtd/physmap.h>
26#include <linux/spi/spi.h>
27#include <linux/leds.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30#include <asm/arch/hardware.h>
31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/pxa2xx_spi.h>
33#include <asm/arch/pcm027.h>
34#include "generic.h"
35
36/*
37 * ABSTRACT:
38 *
39 * The PXA270 processor comes with a bunch of hardware on its silicon.
40 * Not all of this hardware can be used at the same time and not all
41 * is routed to module's connectors. Also it depends on the baseboard, what
42 * kind of hardware can be used in which way.
43 * -> So this file supports the main devices on the CPU card only!
44 * Refer pcm990-baseboard.c how to extend this features to get a full
45 * blown system with many common interfaces.
46 *
47 * The PCM-027 supports the following interfaces through its connectors and
48 * will be used in pcm990-baseboard.c:
49 *
50 * - LCD support
51 * - MMC support
52 * - IDE/CF card
53 * - FFUART
54 * - BTUART
55 * - IRUART
56 * - AC97
57 * - SSP
58 * - SSP3
59 *
60 * Claimed GPIOs:
61 * GPIO0 -> IRQ input from RTC
62 * GPIO2 -> SYS_ENA*)
63 * GPIO3 -> PWR_SCL
64 * GPIO4 -> PWR_SDA
65 * GPIO5 -> PowerCap0*)
66 * GPIO6 -> PowerCap1*)
67 * GPIO7 -> PowerCap2*)
68 * GPIO8 -> PowerCap3*)
69 * GPIO15 -> /CS1
70 * GPIO20 -> /CS2
71 * GPIO21 -> /CS3
72 * GPIO33 -> /CS5 network controller select
73 * GPIO52 -> IRQ from network controller
74 * GPIO78 -> /CS2
75 * GPIO80 -> /CS4
76 * GPIO90 -> LED0
77 * GPIO91 -> LED1
78 * GPIO114 -> IRQ from CAN controller
79 * GPIO117 -> SCL
80 * GPIO118 -> SDA
81 *
82 * *) CPU internal use only
83 */
84
85/*
86 * SMC91x network controller specific stuff
87 */
88static struct resource smc91x_resources[] = {
89 [0] = {
90 .start = PCM027_ETH_PHYS + 0x300,
91 .end = PCM027_ETH_PHYS + PCM027_ETH_SIZE,
92 .flags = IORESOURCE_MEM,
93 },
94 [1] = {
95 .start = PCM027_ETH_IRQ,
96 .end = PCM027_ETH_IRQ,
97 /* note: smc91x's driver doesn't use the trigger bits yet */
98 .flags = IORESOURCE_IRQ | PCM027_ETH_IRQ_EDGE,
99 }
100};
101
102static struct platform_device smc91x_device = {
103 .name = "smc91x",
104 .id = 0,
105 .num_resources = ARRAY_SIZE(smc91x_resources),
106 .resource = smc91x_resources,
107};
108
109static struct physmap_flash_data pcm027_flash_data = {
110 .width = 4,
111};
112
113static struct resource pcm027_flash_resource = {
114 .start = PCM027_FLASH_PHYS,
115 .end = PCM027_FLASH_PHYS + PCM027_FLASH_SIZE - 1 ,
116 .flags = IORESOURCE_MEM,
117};
118
119static struct platform_device pcm027_flash = {
120 .name = "physmap-flash",
121 .id = 0,
122 .dev = {
123 .platform_data = &pcm027_flash_data,
124 },
125 .resource = &pcm027_flash_resource,
126 .num_resources = 1,
127};
128
129#ifdef CONFIG_LEDS_GPIO
130
131static struct gpio_led pcm027_led[] = {
132 {
133 .name = "led0:red", /* FIXME */
134 .gpio = PCM027_LED_CPU
135 },
136 {
137 .name = "led1:green", /* FIXME */
138 .gpio = PCM027_LED_HEARD_BEAT
139 },
140};
141
142static struct gpio_led_platform_data pcm027_led_data = {
143 .num_leds = ARRAY_SIZE(pcm027_led),
144 .leds = pcm027_led
145};
146
147static struct platform_device pcm027_led_dev = {
148 .name = "leds-gpio",
149 .id = 0,
150 .dev = {
151 .platform_data = &pcm027_led_data,
152 },
153};
154
155#endif /* CONFIG_LEDS_GPIO */
156
157/*
158 * declare the available device resources on this board
159 */
160static struct platform_device *devices[] __initdata = {
161 &smc91x_device,
162 &pcm027_flash,
163#ifdef CONFIG_LEDS_GPIO
164 &pcm027_led_dev
165#endif
166};
167
168/*
169 * pcm027_init - breath some life into the board
170 */
171static void __init pcm027_init(void)
172{
173 /* system bus arbiter setting
174 * - Core_Park
175 * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
176 */
177 ARB_CNTRL = ARB_CORE_PARK | 0x234;
178
179 platform_add_devices(devices, ARRAY_SIZE(devices));
180
181 /* LEDs (on demand only) */
182#ifdef CONFIG_LEDS_GPIO
183 pxa_gpio_mode(PCM027_LED_CPU | GPIO_OUT);
184 pxa_gpio_mode(PCM027_LED_HEARD_BEAT | GPIO_OUT);
185#endif /* CONFIG_LEDS_GPIO */
186
187 /* at last call the baseboard to initialize itself */
188#ifdef CONFIG_MACH_PCM990_BASEBOARD
189 pcm990_baseboard_init();
190#endif
191}
192
193static void __init pcm027_map_io(void)
194{
195 pxa_map_io();
196
197 /* initialize sleep mode regs (wake-up sources, etc) */
198 PGSR0 = 0x01308000;
199 PGSR1 = 0x00CF0002;
200 PGSR2 = 0x0E294000;
201 PGSR3 = 0x0000C000;
202 PWER = 0x40000000 | PWER_GPIO0 | PWER_GPIO1;
203 PRER = 0x00000000;
204 PFER = 0x00000003;
205}
206
207MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
208 /* Maintainer: Pengutronix */
209 .boot_params = 0xa0000100,
210 .phys_io = 0x40000000,
211 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
212 .map_io = pcm027_map_io,
213 .init_irq = pxa27x_init_irq,
214 .timer = &pxa_timer,
215 .init_machine = pcm027_init,
216MACHINE_END
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
new file mode 100644
index 000000000000..3dda16a20049
--- /dev/null
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -0,0 +1,330 @@
1/*
2 * arch/arm/mach-pxa/pcm990-baseboard.c
3 * Support for the Phytec phyCORE-PXA270 Development Platform (PCM-990).
4 *
5 * Refer
6 * http://www.phytec.com/products/rdk/ARM-XScale/phyCORE-XScale-PXA270.html
7 * for additional hardware info
8 *
9 * Author: Juergen Kilb
10 * Created: April 05, 2005
11 * Copyright: Phytec Messtechnik GmbH
12 * e-Mail: armlinux@phytec.de
13 *
14 * based on Intel Mainstone Board
15 *
16 * Copyright 2007 Juergen Beisert @ Pengutronix (j.beisert@pengutronix.de)
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/ide.h>
26#include <asm/mach/map.h>
27#include <asm/arch/pxa-regs.h>
28#include <asm/arch/mmc.h>
29#include <asm/arch/ohci.h>
30#include <asm/arch/pcm990_baseboard.h>
31
32/*
33 * The PCM-990 development baseboard uses PCM-027's hardeware in the
34 * following way:
35 *
36 * - LCD support is in use
37 * - GPIO16 is output for back light on/off with PWM
38 * - GPIO58 ... GPIO73 are outputs for display data
39 * - GPIO74 is output output for LCDFCLK
40 * - GPIO75 is output for LCDLCLK
41 * - GPIO76 is output for LCDPCLK
42 * - GPIO77 is output for LCDBIAS
43 * - MMC support is in use
44 * - GPIO32 is output for MMCCLK
45 * - GPIO92 is MMDAT0
46 * - GPIO109 is MMDAT1
47 * - GPIO110 is MMCS0
48 * - GPIO111 is MMCS1
49 * - GPIO112 is MMCMD
50 * - IDE/CF card is in use
51 * - GPIO48 is output /POE
52 * - GPIO49 is output /PWE
53 * - GPIO50 is output /PIOR
54 * - GPIO51 is output /PIOW
55 * - GPIO54 is output /PCE2
56 * - GPIO55 is output /PREG
57 * - GPIO56 is input /PWAIT
58 * - GPIO57 is output /PIOS16
59 * - GPIO79 is output PSKTSEL
60 * - GPIO85 is output /PCE1
61 * - FFUART is in use
62 * - GPIO34 is input FFRXD
63 * - GPIO35 is input FFCTS
64 * - GPIO36 is input FFDCD
65 * - GPIO37 is input FFDSR
66 * - GPIO38 is input FFRI
67 * - GPIO39 is output FFTXD
68 * - GPIO40 is output FFDTR
69 * - GPIO41 is output FFRTS
70 * - BTUART is in use
71 * - GPIO42 is input BTRXD
72 * - GPIO43 is output BTTXD
73 * - GPIO44 is input BTCTS
74 * - GPIO45 is output BTRTS
75 * - IRUART is in use
76 * - GPIO46 is input STDRXD
77 * - GPIO47 is output STDTXD
78 * - AC97 is in use*)
79 * - GPIO28 is input AC97CLK
80 * - GPIO29 is input AC97DatIn
81 * - GPIO30 is output AC97DatO
82 * - GPIO31 is output AC97SYNC
83 * - GPIO113 is output AC97_RESET
84 * - SSP is in use
85 * - GPIO23 is output SSPSCLK
86 * - GPIO24 is output chip select to Max7301
87 * - GPIO25 is output SSPTXD
88 * - GPIO26 is input SSPRXD
89 * - GPIO27 is input for Max7301 IRQ
90 * - GPIO53 is input SSPSYSCLK
91 * - SSP3 is in use
92 * - GPIO81 is output SSPTXD3
93 * - GPIO82 is input SSPRXD3
94 * - GPIO83 is output SSPSFRM
95 * - GPIO84 is output SSPCLK3
96 *
97 * Otherwise claimed GPIOs:
98 * GPIO1 -> IRQ from user switch
99 * GPIO9 -> IRQ from power management
100 * GPIO10 -> IRQ from WML9712 AC97 controller
101 * GPIO11 -> IRQ from IDE controller
102 * GPIO12 -> IRQ from CF controller
103 * GPIO13 -> IRQ from CF controller
104 * GPIO14 -> GPIO free
105 * GPIO15 -> /CS1 selects baseboard's Control CPLD (U7, 16 bit wide data path)
106 * GPIO19 -> GPIO free
107 * GPIO20 -> /SDCS2
108 * GPIO21 -> /CS3 PC card socket select
109 * GPIO33 -> /CS5 network controller select
110 * GPIO78 -> /CS2 (16 bit wide data path)
111 * GPIO80 -> /CS4 (16 bit wide data path)
112 * GPIO86 -> GPIO free
113 * GPIO87 -> GPIO free
114 * GPIO90 -> LED0 on CPU module
115 * GPIO91 -> LED1 on CPI module
116 * GPIO117 -> SCL
117 * GPIO118 -> SDA
118 */
119
120static unsigned long pcm990_irq_enabled;
121
122static void pcm990_mask_ack_irq(unsigned int irq)
123{
124 int pcm990_irq = (irq - PCM027_IRQ(0));
125 PCM990_INTMSKENA = (pcm990_irq_enabled &= ~(1 << pcm990_irq));
126}
127
128static void pcm990_unmask_irq(unsigned int irq)
129{
130 int pcm990_irq = (irq - PCM027_IRQ(0));
131 /* the irq can be acknowledged only if deasserted, so it's done here */
132 PCM990_INTSETCLR |= 1 << pcm990_irq;
133 PCM990_INTMSKENA = (pcm990_irq_enabled |= (1 << pcm990_irq));
134}
135
136static struct irq_chip pcm990_irq_chip = {
137 .mask_ack = pcm990_mask_ack_irq,
138 .unmask = pcm990_unmask_irq,
139};
140
141static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc)
142{
143 unsigned long pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
144
145 do {
146 GEDR(PCM990_CTRL_INT_IRQ_GPIO) =
147 GPIO_bit(PCM990_CTRL_INT_IRQ_GPIO);
148 if (likely(pending)) {
149 irq = PCM027_IRQ(0) + __ffs(pending);
150 desc = irq_desc + irq;
151 desc_handle_irq(irq, desc);
152 }
153 pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
154 } while (pending);
155}
156
157static void __init pcm990_init_irq(void)
158{
159 int irq;
160
161 /* setup extra PCM990 irqs */
162 for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
163 set_irq_chip(irq, &pcm990_irq_chip);
164 set_irq_handler(irq, handle_level_irq);
165 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
166 }
167
168 PCM990_INTMSKENA = 0x00; /* disable all Interrupts */
169 PCM990_INTSETCLR = 0xFF;
170
171 set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
172 set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
173}
174
175static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
176 void *data)
177{
178 int err;
179
180 /*
181 * enable GPIO for PXA27x MMC controller
182 */
183 pxa_gpio_mode(GPIO32_MMCCLK_MD);
184 pxa_gpio_mode(GPIO112_MMCCMD_MD);
185 pxa_gpio_mode(GPIO92_MMCDAT0_MD);
186 pxa_gpio_mode(GPIO109_MMCDAT1_MD);
187 pxa_gpio_mode(GPIO110_MMCDAT2_MD);
188 pxa_gpio_mode(GPIO111_MMCDAT3_MD);
189
190 err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, IRQF_DISABLED,
191 "MMC card detect", data);
192 if (err)
193 printk(KERN_ERR "pcm990_mci_init: MMC/SD: can't request MMC "
194 "card detect IRQ\n");
195
196 return err;
197}
198
199static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
200{
201 struct pxamci_platform_data *p_d = dev->platform_data;
202
203 if ((1 << vdd) & p_d->ocr_mask)
204 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) =
205 PCM990_CTRL_MMC2PWR;
206 else
207 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) =
208 ~PCM990_CTRL_MMC2PWR;
209}
210
211static void pcm990_mci_exit(struct device *dev, void *data)
212{
213 free_irq(PCM027_MMCDET_IRQ, data);
214}
215
216#define MSECS_PER_JIFFY (1000/HZ)
217
218static struct pxamci_platform_data pcm990_mci_platform_data = {
219 .detect_delay = 250 / MSECS_PER_JIFFY,
220 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
221 .init = pcm990_mci_init,
222 .setpower = pcm990_mci_setpower,
223 .exit = pcm990_mci_exit,
224};
225
226/*
227 * init OHCI hardware to work with
228 *
229 * Note: Only USB port 1 (host only) is connected
230 *
231 * GPIO88 (USBHPWR#1): overcurrent in, overcurrent when low
232 * GPIO89 (USBHPEN#1): power-on out, on when low
233 */
234static int pcm990_ohci_init(struct device *dev)
235{
236 pxa_gpio_mode(PCM990_USB_OVERCURRENT);
237 pxa_gpio_mode(PCM990_USB_PWR_EN);
238 /*
239 * disable USB port 2 and 3
240 * power sense is active low
241 */
242 UHCHR = ((UHCHR) | UHCHR_PCPL | UHCHR_PSPL | UHCHR_SSEP2 |
243 UHCHR_SSEP3) & ~(UHCHR_SSEP1 | UHCHR_SSE);
244 /*
245 * wait 10ms after Power on
246 * overcurrent per port
247 * power switch per port
248 */
249 UHCRHDA = (5<<24) | (1<<11) | (1<<8); /* FIXME: Required? */
250
251 return 0;
252}
253
254static struct pxaohci_platform_data pcm990_ohci_platform_data = {
255 .port_mode = PMM_PERPORT_MODE,
256 .init = pcm990_ohci_init,
257 .exit = NULL,
258};
259
260/*
261 * AC97 support
262 * Note: The connected AC97 mixer also reports interrupts at PCM990_AC97_IRQ
263 */
264static struct resource pxa27x_ac97_resources[] = {
265 [0] = {
266 .start = 0x40500000,
267 .end = 0x40500000 + 0xfff,
268 .flags = IORESOURCE_MEM,
269 },
270 [1] = {
271 .start = IRQ_AC97,
272 .end = IRQ_AC97,
273 .flags = IORESOURCE_IRQ,
274 },
275};
276
277static u64 pxa_ac97_dmamask = 0xffffffffUL;
278
279static struct platform_device pxa27x_device_ac97 = {
280 .name = "pxa2xx-ac97",
281 .id = -1,
282 .dev = {
283 .dma_mask = &pxa_ac97_dmamask,
284 .coherent_dma_mask = 0xffffffff,
285 },
286 .num_resources = ARRAY_SIZE(pxa27x_ac97_resources),
287 .resource = pxa27x_ac97_resources,
288};
289
290/*
291 * enable generic access to the base board control CPLDs U6 and U7
292 */
293static struct map_desc pcm990_io_desc[] __initdata = {
294 {
295 .virtual = PCM990_CTRL_BASE,
296 .pfn = __phys_to_pfn(PCM990_CTRL_PHYS),
297 .length = PCM990_CTRL_SIZE,
298 .type = MT_DEVICE /* CPLD */
299 }, {
300 .virtual = PCM990_CF_PLD_BASE,
301 .pfn = __phys_to_pfn(PCM990_CF_PLD_PHYS),
302 .length = PCM990_CF_PLD_SIZE,
303 .type = MT_DEVICE /* CPLD */
304 }
305};
306
307/*
308 * system init for baseboard usage. Will be called by pcm027 init.
309 *
310 * Add platform devices present on this baseboard and init
311 * them from CPU side as far as required to use them later on
312 */
313void __init pcm990_baseboard_init(void)
314{
315 /* register CPLD access */
316 iotable_init(pcm990_io_desc, ARRAY_SIZE(pcm990_io_desc));
317
318 /* register CPLD's IRQ controller */
319 pcm990_init_irq();
320
321 platform_device_register(&pxa27x_device_ac97);
322
323 /* MMC */
324 pxa_set_mci_info(&pcm990_mci_platform_data);
325
326 /* USB host */
327 pxa_set_ohci_info(&pcm990_ohci_platform_data);
328
329 printk(KERN_INFO"PCM-990 Evaluation baseboard initialized\n");
330}
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index a941c71c7d06..039194cbe477 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -38,34 +38,37 @@ int pxa_pm_enter(suspend_state_t state)
38 iwmmxt_task_disable(NULL); 38 iwmmxt_task_disable(NULL);
39#endif 39#endif
40 40
41 pxa_cpu_pm_fns->save(sleep_save); 41 /* skip registers saving for standby */
42 if (state != PM_SUSPEND_STANDBY) {
43 pxa_cpu_pm_fns->save(sleep_save);
44 /* before sleeping, calculate and save a checksum */
45 for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++)
46 sleep_save_checksum += sleep_save[i];
47 }
42 48
43 /* Clear sleep reset status */ 49 /* Clear sleep reset status */
44 RCSR = RCSR_SMR; 50 RCSR = RCSR_SMR;
45 51
46 /* before sleeping, calculate and save a checksum */
47 for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++)
48 sleep_save_checksum += sleep_save[i];
49
50 /* *** go zzz *** */ 52 /* *** go zzz *** */
51 pxa_cpu_pm_fns->enter(state); 53 pxa_cpu_pm_fns->enter(state);
52 cpu_init(); 54 cpu_init();
53 55
54 /* after sleeping, validate the checksum */ 56 if (state != PM_SUSPEND_STANDBY) {
55 for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++) 57 /* after sleeping, validate the checksum */
56 checksum += sleep_save[i]; 58 for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++)
59 checksum += sleep_save[i];
57 60
58 /* if invalid, display message and wait for a hardware reset */ 61 /* if invalid, display message and wait for a hardware reset */
59 if (checksum != sleep_save_checksum) { 62 if (checksum != sleep_save_checksum) {
60#ifdef CONFIG_ARCH_LUBBOCK 63#ifdef CONFIG_ARCH_LUBBOCK
61 LUB_HEXLED = 0xbadbadc5; 64 LUB_HEXLED = 0xbadbadc5;
62#endif 65#endif
63 while (1) 66 while (1)
64 pxa_cpu_pm_fns->enter(state); 67 pxa_cpu_pm_fns->enter(state);
68 }
69 pxa_cpu_pm_fns->restore(sleep_save);
65 } 70 }
66 71
67 pxa_cpu_pm_fns->restore(sleep_save);
68
69 pr_debug("*** made it back from resume\n"); 72 pr_debug("*** made it back from resume\n");
70 73
71 return 0; 74 return 0;
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 655668d4d0e9..dd54496083cb 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -215,12 +215,10 @@ static int poodle_mci_init(struct device *dev, irq_handler_t poodle_detect_int,
215 err = request_irq(POODLE_IRQ_GPIO_nSD_DETECT, poodle_detect_int, 215 err = request_irq(POODLE_IRQ_GPIO_nSD_DETECT, poodle_detect_int,
216 IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 216 IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
217 "MMC card detect", data); 217 "MMC card detect", data);
218 if (err) { 218 if (err)
219 printk(KERN_ERR "poodle_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); 219 printk(KERN_ERR "poodle_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
220 return -1;
221 }
222 220
223 return 0; 221 return err;
224} 222}
225 223
226static void poodle_mci_setpower(struct device *dev, unsigned int vdd) 224static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 006a6e09589c..ddd05bf78e02 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -123,12 +123,15 @@ static struct clk pxa25x_clks[] = {
123 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), 123 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
124 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), 124 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
125 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), 125 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
126
127 INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev),
128 INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
129 INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
130
126 /* 131 /*
127 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), 132 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
128 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), 133 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
129 INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL),
130 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), 134 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
131 INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL),
132 */ 135 */
133 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), 136 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
134}; 137};
@@ -216,8 +219,6 @@ static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
216 219
217static void pxa25x_cpu_pm_enter(suspend_state_t state) 220static void pxa25x_cpu_pm_enter(suspend_state_t state)
218{ 221{
219 CKEN = 0;
220
221 switch (state) { 222 switch (state) {
222 case PM_SUSPEND_MEM: 223 case PM_SUSPEND_MEM:
223 /* set resume return address */ 224 /* set resume return address */
@@ -239,6 +240,8 @@ static void __init pxa25x_init_pm(void)
239{ 240{
240 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; 241 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
241} 242}
243#else
244static inline void pxa25x_init_pm(void) {}
242#endif 245#endif
243 246
244/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm 247/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
@@ -290,16 +293,15 @@ void __init pxa25x_init_irq(void)
290} 293}
291 294
292static struct platform_device *pxa25x_devices[] __initdata = { 295static struct platform_device *pxa25x_devices[] __initdata = {
293 &pxa_device_mci,
294 &pxa_device_udc, 296 &pxa_device_udc,
295 &pxa_device_fb,
296 &pxa_device_ffuart, 297 &pxa_device_ffuart,
297 &pxa_device_btuart, 298 &pxa_device_btuart,
298 &pxa_device_stuart, 299 &pxa_device_stuart,
299 &pxa_device_i2c,
300 &pxa_device_i2s, 300 &pxa_device_i2s,
301 &pxa_device_ficp,
302 &pxa_device_rtc, 301 &pxa_device_rtc,
302 &pxa25x_device_ssp,
303 &pxa25x_device_nssp,
304 &pxa25x_device_assp,
303}; 305};
304 306
305static int __init pxa25x_init(void) 307static int __init pxa25x_init(void)
@@ -315,9 +317,9 @@ static int __init pxa25x_init(void)
315 317
316 if ((ret = pxa_init_dma(16))) 318 if ((ret = pxa_init_dma(16)))
317 return ret; 319 return ret;
318#ifdef CONFIG_PM 320
319 pxa25x_init_pm(); 321 pxa25x_init_pm();
320#endif 322
321 ret = platform_add_devices(pxa25x_devices, 323 ret = platform_add_devices(pxa25x_devices,
322 ARRAY_SIZE(pxa25x_devices)); 324 ARRAY_SIZE(pxa25x_devices));
323 } 325 }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 57efebdc4324..96cf274ec7cb 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -21,6 +21,7 @@
21#include <asm/irq.h> 21#include <asm/irq.h>
22#include <asm/arch/irqs.h> 22#include <asm/arch/irqs.h>
23#include <asm/arch/pxa-regs.h> 23#include <asm/arch/pxa-regs.h>
24#include <asm/arch/pxa2xx-regs.h>
24#include <asm/arch/ohci.h> 25#include <asm/arch/ohci.h>
25#include <asm/arch/pm.h> 26#include <asm/arch/pm.h>
26#include <asm/arch/dma.h> 27#include <asm/arch/dma.h>
@@ -151,11 +152,12 @@ static struct clk pxa27x_clks[] = {
151 INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), 152 INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
152 INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL), 153 INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
153 154
155 INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
156 INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
157 INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
158
154 /* 159 /*
155 INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL), 160 INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
156 INIT_CKEN("SSPCLK", SSP1, 13000000, 0, NULL),
157 INIT_CKEN("SSPCLK", SSP2, 13000000, 0, NULL),
158 INIT_CKEN("SSPCLK", SSP3, 13000000, 0, NULL),
159 INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), 161 INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
160 INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), 162 INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
161 INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), 163 INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
@@ -264,12 +266,6 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
264{ 266{
265 extern void pxa_cpu_standby(void); 267 extern void pxa_cpu_standby(void);
266 268
267 if (state == PM_SUSPEND_STANDBY)
268 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) |
269 (1 << CKEN_LCD) | (1 << CKEN_PWM0);
270 else
271 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER);
272
273 /* ensure voltage-change sequencer not initiated, which hangs */ 269 /* ensure voltage-change sequencer not initiated, which hangs */
274 PCFR &= ~PCFR_FVC; 270 PCFR &= ~PCFR_FVC;
275 271
@@ -305,6 +301,8 @@ static void __init pxa27x_init_pm(void)
305{ 301{
306 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; 302 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
307} 303}
304#else
305static inline void pxa27x_init_pm(void) {}
308#endif 306#endif
309 307
310/* PXA27x: Various gpios can issue wakeup events. This logic only 308/* PXA27x: Various gpios can issue wakeup events. This logic only
@@ -374,37 +372,6 @@ void __init pxa27x_init_irq(void)
374 * device registration specific to PXA27x. 372 * device registration specific to PXA27x.
375 */ 373 */
376 374
377static u64 pxa27x_dmamask = 0xffffffffUL;
378
379static struct resource pxa27x_ohci_resources[] = {
380 [0] = {
381 .start = 0x4C000000,
382 .end = 0x4C00ff6f,
383 .flags = IORESOURCE_MEM,
384 },
385 [1] = {
386 .start = IRQ_USBH1,
387 .end = IRQ_USBH1,
388 .flags = IORESOURCE_IRQ,
389 },
390};
391
392struct platform_device pxa27x_device_ohci = {
393 .name = "pxa27x-ohci",
394 .id = -1,
395 .dev = {
396 .dma_mask = &pxa27x_dmamask,
397 .coherent_dma_mask = 0xffffffff,
398 },
399 .num_resources = ARRAY_SIZE(pxa27x_ohci_resources),
400 .resource = pxa27x_ohci_resources,
401};
402
403void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
404{
405 pxa27x_device_ohci.dev.platform_data = info;
406}
407
408static struct resource i2c_power_resources[] = { 375static struct resource i2c_power_resources[] = {
409 { 376 {
410 .start = 0x40f00180, 377 .start = 0x40f00180,
@@ -430,18 +397,16 @@ void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
430} 397}
431 398
432static struct platform_device *devices[] __initdata = { 399static struct platform_device *devices[] __initdata = {
433 &pxa_device_mci,
434 &pxa_device_udc, 400 &pxa_device_udc,
435 &pxa_device_fb,
436 &pxa_device_ffuart, 401 &pxa_device_ffuart,
437 &pxa_device_btuart, 402 &pxa_device_btuart,
438 &pxa_device_stuart, 403 &pxa_device_stuart,
439 &pxa_device_i2c,
440 &pxa_device_i2s, 404 &pxa_device_i2s,
441 &pxa_device_ficp,
442 &pxa_device_rtc, 405 &pxa_device_rtc,
443 &pxa27x_device_i2c_power, 406 &pxa27x_device_i2c_power,
444 &pxa27x_device_ohci, 407 &pxa27x_device_ssp1,
408 &pxa27x_device_ssp2,
409 &pxa27x_device_ssp3,
445}; 410};
446 411
447static int __init pxa27x_init(void) 412static int __init pxa27x_init(void)
@@ -452,9 +417,9 @@ static int __init pxa27x_init(void)
452 417
453 if ((ret = pxa_init_dma(32))) 418 if ((ret = pxa_init_dma(32)))
454 return ret; 419 return ret;
455#ifdef CONFIG_PM 420
456 pxa27x_init_pm(); 421 pxa27x_init_pm();
457#endif 422
458 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 423 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
459 } 424 }
460 return ret; 425 return ret;
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 37e93f9ba8fc..5cbf057a1b32 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -19,6 +19,7 @@
19#include <linux/pm.h> 19#include <linux/pm.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <linux/io.h>
22 23
23#include <asm/hardware.h> 24#include <asm/hardware.h>
24#include <asm/arch/pxa3xx-regs.h> 25#include <asm/arch/pxa3xx-regs.h>
@@ -189,8 +190,237 @@ static struct clk pxa3xx_clks[] = {
189 190
190 PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), 191 PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
191 PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), 192 PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
193 PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
194
195 PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
196 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
197 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
198 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
199
200 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
201 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
202 PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
203};
204
205#ifdef CONFIG_PM
206#define SLEEP_SAVE_SIZE 4
207
208#define ISRAM_START 0x5c000000
209#define ISRAM_SIZE SZ_256K
210
211static void __iomem *sram;
212static unsigned long wakeup_src;
213
214static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
215{
216 pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB);
217
218 if (CKENA & (1 << CKEN_USBH)) {
219 printk(KERN_ERR "PM: USB host clock not stopped?\n");
220 CKENA &= ~(1 << CKEN_USBH);
221 }
222// CKENA |= 1 << (CKEN_ISC & 31);
223
224 /*
225 * Low power modes require the HSIO2 clock to be enabled.
226 */
227 CKENB |= 1 << (CKEN_HSIO2 & 31);
228}
229
230static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
231{
232 CKENB &= ~(1 << (CKEN_HSIO2 & 31));
233}
234
235/*
236 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
237 * memory controller has to be reinitialised, so we place some code
238 * in the SRAM to perform this function.
239 *
240 * We disable FIQs across the standby - otherwise, we might receive a
241 * FIQ while the SDRAM is unavailable.
242 */
243static void pxa3xx_cpu_standby(unsigned int pwrmode)
244{
245 extern const char pm_enter_standby_start[], pm_enter_standby_end[];
246 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
247
248 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
249 pm_enter_standby_end - pm_enter_standby_start);
250
251 AD2D0SR = ~0;
252 AD2D1SR = ~0;
253 AD2D0ER = wakeup_src;
254 AD2D1ER = 0;
255 ASCR = ASCR;
256 ARSR = ARSR;
257
258 local_fiq_disable();
259 fn(pwrmode);
260 local_fiq_enable();
261
262 AD2D0ER = 0;
263 AD2D1ER = 0;
264
265 printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
266}
267
268static void pxa3xx_cpu_pm_enter(suspend_state_t state)
269{
270 /*
271 * Don't sleep if no wakeup sources are defined
272 */
273 if (wakeup_src == 0)
274 return;
275
276 switch (state) {
277 case PM_SUSPEND_STANDBY:
278 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
279 break;
280
281 case PM_SUSPEND_MEM:
282 break;
283 }
284}
285
286static int pxa3xx_cpu_pm_valid(suspend_state_t state)
287{
288 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
289}
290
291static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
292 .save_size = SLEEP_SAVE_SIZE,
293 .save = pxa3xx_cpu_pm_save,
294 .restore = pxa3xx_cpu_pm_restore,
295 .valid = pxa3xx_cpu_pm_valid,
296 .enter = pxa3xx_cpu_pm_enter,
192}; 297};
193 298
299static void __init pxa3xx_init_pm(void)
300{
301 sram = ioremap(ISRAM_START, ISRAM_SIZE);
302 if (!sram) {
303 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
304 return;
305 }
306
307 /*
308 * Since we copy wakeup code into the SRAM, we need to ensure
309 * that it is preserved over the low power modes. Note: bit 8
310 * is undocumented in the developer manual, but must be set.
311 */
312 AD1R |= ADXR_L2 | ADXR_R0;
313 AD2R |= ADXR_L2 | ADXR_R0;
314 AD3R |= ADXR_L2 | ADXR_R0;
315
316 /*
317 * Clear the resume enable registers.
318 */
319 AD1D0ER = 0;
320 AD2D0ER = 0;
321 AD2D1ER = 0;
322 AD3ER = 0;
323
324 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
325}
326
327static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
328{
329 unsigned long flags, mask = 0;
330
331 switch (irq) {
332 case IRQ_SSP3:
333 mask = ADXER_MFP_WSSP3;
334 break;
335 case IRQ_MSL:
336 mask = ADXER_WMSL0;
337 break;
338 case IRQ_USBH2:
339 case IRQ_USBH1:
340 mask = ADXER_WUSBH;
341 break;
342 case IRQ_KEYPAD:
343 mask = ADXER_WKP;
344 break;
345 case IRQ_AC97:
346 mask = ADXER_MFP_WAC97;
347 break;
348 case IRQ_USIM:
349 mask = ADXER_WUSIM0;
350 break;
351 case IRQ_SSP2:
352 mask = ADXER_MFP_WSSP2;
353 break;
354 case IRQ_I2C:
355 mask = ADXER_MFP_WI2C;
356 break;
357 case IRQ_STUART:
358 mask = ADXER_MFP_WUART3;
359 break;
360 case IRQ_BTUART:
361 mask = ADXER_MFP_WUART2;
362 break;
363 case IRQ_FFUART:
364 mask = ADXER_MFP_WUART1;
365 break;
366 case IRQ_MMC:
367 mask = ADXER_MFP_WMMC1;
368 break;
369 case IRQ_SSP:
370 mask = ADXER_MFP_WSSP1;
371 break;
372 case IRQ_RTCAlrm:
373 mask = ADXER_WRTC;
374 break;
375 case IRQ_SSP4:
376 mask = ADXER_MFP_WSSP4;
377 break;
378 case IRQ_TSI:
379 mask = ADXER_WTSI;
380 break;
381 case IRQ_USIM2:
382 mask = ADXER_WUSIM1;
383 break;
384 case IRQ_MMC2:
385 mask = ADXER_MFP_WMMC2;
386 break;
387 case IRQ_NAND:
388 mask = ADXER_MFP_WFLASH;
389 break;
390 case IRQ_USB2:
391 mask = ADXER_WUSB2;
392 break;
393 case IRQ_WAKEUP0:
394 mask = ADXER_WEXTWAKE0;
395 break;
396 case IRQ_WAKEUP1:
397 mask = ADXER_WEXTWAKE1;
398 break;
399 case IRQ_MMC3:
400 mask = ADXER_MFP_GEN12;
401 break;
402 }
403
404 local_irq_save(flags);
405 if (on)
406 wakeup_src |= mask;
407 else
408 wakeup_src &= ~mask;
409 local_irq_restore(flags);
410
411 return 0;
412}
413
414static void pxa3xx_init_irq_pm(void)
415{
416 pxa_init_irq_set_wake(pxa3xx_set_wake);
417}
418
419#else
420static inline void pxa3xx_init_pm(void) {}
421static inline void pxa3xx_init_irq_pm(void) {}
422#endif
423
194void __init pxa3xx_init_irq(void) 424void __init pxa3xx_init_irq(void)
195{ 425{
196 /* enable CP6 access */ 426 /* enable CP6 access */
@@ -202,6 +432,7 @@ void __init pxa3xx_init_irq(void)
202 pxa_init_irq_low(); 432 pxa_init_irq_low();
203 pxa_init_irq_high(); 433 pxa_init_irq_high();
204 pxa_init_irq_gpio(128); 434 pxa_init_irq_gpio(128);
435 pxa3xx_init_irq_pm();
205} 436}
206 437
207/* 438/*
@@ -209,16 +440,16 @@ void __init pxa3xx_init_irq(void)
209 */ 440 */
210 441
211static struct platform_device *devices[] __initdata = { 442static struct platform_device *devices[] __initdata = {
212 &pxa_device_mci,
213 &pxa_device_udc, 443 &pxa_device_udc,
214 &pxa_device_fb,
215 &pxa_device_ffuart, 444 &pxa_device_ffuart,
216 &pxa_device_btuart, 445 &pxa_device_btuart,
217 &pxa_device_stuart, 446 &pxa_device_stuart,
218 &pxa_device_i2c,
219 &pxa_device_i2s, 447 &pxa_device_i2s,
220 &pxa_device_ficp,
221 &pxa_device_rtc, 448 &pxa_device_rtc,
449 &pxa27x_device_ssp1,
450 &pxa27x_device_ssp2,
451 &pxa27x_device_ssp3,
452 &pxa3xx_device_ssp4,
222}; 453};
223 454
224static int __init pxa3xx_init(void) 455static int __init pxa3xx_init(void)
@@ -231,6 +462,8 @@ static int __init pxa3xx_init(void)
231 if ((ret = pxa_init_dma(32))) 462 if ((ret = pxa_init_dma(32)))
232 return ret; 463 return ret;
233 464
465 pxa3xx_init_pm();
466
234 return platform_add_devices(devices, ARRAY_SIZE(devices)); 467 return platform_add_devices(devices, ARRAY_SIZE(devices));
235 } 468 }
236 return 0; 469 return 0;
diff --git a/arch/arm/mach-pxa/sharpsl.h b/arch/arm/mach-pxa/sharpsl.h
index da4769caaf72..047909a76651 100644
--- a/arch/arm/mach-pxa/sharpsl.h
+++ b/arch/arm/mach-pxa/sharpsl.h
@@ -26,28 +26,15 @@ void corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo);
26 26
27 27
28/* 28/*
29 * SharpSL Backlight 29 * SharpSL/Corgi LCD Driver
30 */ 30 */
31void corgi_bl_set_intensity(int intensity); 31void corgi_lcdtg_suspend(void);
32void spitz_bl_set_intensity(int intensity); 32void corgi_lcdtg_hw_init(int mode);
33void akita_bl_set_intensity(int intensity);
34
35
36/*
37 * SharpSL Touchscreen Driver
38 */
39unsigned long corgi_get_hsync_len(void);
40unsigned long spitz_get_hsync_len(void);
41void corgi_put_hsync(void);
42void spitz_put_hsync(void);
43void corgi_wait_hsync(void);
44void spitz_wait_hsync(void);
45 33
46 34
47/* 35/*
48 * SharpSL Battery/PM Driver 36 * SharpSL Battery/PM Driver
49 */ 37 */
50
51#define READ_GPIO_BIT(x) (GPLR(x) & GPIO_bit(x)) 38#define READ_GPIO_BIT(x) (GPLR(x) & GPIO_bit(x))
52 39
53/* MAX1111 Channel Definitions */ 40/* MAX1111 Channel Definitions */
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index d0447723b73a..14bb4a93ea52 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -16,6 +16,7 @@
16#include <asm/hardware.h> 16#include <asm/hardware.h>
17 17
18#include <asm/arch/pxa-regs.h> 18#include <asm/arch/pxa-regs.h>
19#include <asm/arch/pxa2xx-regs.h>
19 20
20#define MDREFR_KDIV 0x200a4000 // all banks 21#define MDREFR_KDIV 0x200a4000 // all banks
21#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 22#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
@@ -49,6 +50,7 @@ pxa_cpu_save_sp:
49 str r0, [r1] 50 str r0, [r1]
50 ldr pc, [sp], #4 51 ldr pc, [sp], #4
51 52
53#ifdef CONFIG_PXA27x
52/* 54/*
53 * pxa27x_cpu_suspend() 55 * pxa27x_cpu_suspend()
54 * 56 *
@@ -104,9 +106,11 @@ ENTRY(pxa27x_cpu_suspend)
104 106
105 @ align execution to a cache line 107 @ align execution to a cache line
106 b pxa_cpu_do_suspend 108 b pxa_cpu_do_suspend
109#endif
107 110
111#ifdef CONFIG_PXA25x
108/* 112/*
109 * pxa27x_cpu_suspend() 113 * pxa25x_cpu_suspend()
110 * 114 *
111 * Forces CPU into sleep state. 115 * Forces CPU into sleep state.
112 * 116 *
@@ -169,6 +173,7 @@ ENTRY(pxa25x_cpu_suspend)
169 mcr p14, 0, r0, c6, c0, 0 173 mcr p14, 0, r0, c6, c0, 0
170 orr r0, r0, #2 @ initiate change bit 174 orr r0, r0, #2 @ initiate change bit
171 b pxa_cpu_do_suspend 175 b pxa_cpu_do_suspend
176#endif
172 177
173 .ltorg 178 .ltorg
174 .align 5 179 .align 5
@@ -208,7 +213,7 @@ pxa_cpu_do_suspend:
20820: b 20b @ loop waiting for sleep 21320: b 20b @ loop waiting for sleep
209 214
210/* 215/*
211 * cpu_pxa_resume() 216 * pxa_cpu_resume()
212 * 217 *
213 * entry point from bootloader into kernel during resume 218 * entry point from bootloader into kernel during resume
214 * 219 *
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 2d78199d24af..5078edeadf96 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -271,6 +271,55 @@ static struct platform_device spitzled_device = {
271/* 271/*
272 * Spitz Touch Screen Device 272 * Spitz Touch Screen Device
273 */ 273 */
274
275static unsigned long (*get_hsync_invperiod)(struct device *dev);
276
277static void inline sharpsl_wait_sync(int gpio)
278{
279 while((GPLR(gpio) & GPIO_bit(gpio)) == 0);
280 while((GPLR(gpio) & GPIO_bit(gpio)) != 0);
281}
282
283static struct device *spitz_pxafb_dev;
284
285static int is_pxafb_device(struct device * dev, void * data)
286{
287 struct platform_device *pdev = container_of(dev, struct platform_device, dev);
288
289 return (strncmp(pdev->name, "pxa2xx-fb", 9) == 0);
290}
291
292static unsigned long spitz_get_hsync_invperiod(void)
293{
294#ifdef CONFIG_FB_PXA
295 if (!spitz_pxafb_dev) {
296 spitz_pxafb_dev = bus_find_device(&platform_bus_type, NULL, NULL, is_pxafb_device);
297 if (!spitz_pxafb_dev)
298 return 0;
299 }
300 if (!get_hsync_invperiod)
301 get_hsync_invperiod = symbol_get(pxafb_get_hsync_time);
302 if (!get_hsync_invperiod)
303#endif
304 return 0;
305
306 return get_hsync_invperiod(spitz_pxafb_dev);
307}
308
309static void spitz_put_hsync(void)
310{
311 put_device(spitz_pxafb_dev);
312 if (get_hsync_invperiod)
313 symbol_put(pxafb_get_hsync_time);
314 spitz_pxafb_dev = NULL;
315 get_hsync_invperiod = NULL;
316}
317
318static void spitz_wait_hsync(void)
319{
320 sharpsl_wait_sync(SPITZ_GPIO_HSYNC);
321}
322
274static struct resource spitzts_resources[] = { 323static struct resource spitzts_resources[] = {
275 [0] = { 324 [0] = {
276 .start = SPITZ_IRQ_GPIO_TP_INT, 325 .start = SPITZ_IRQ_GPIO_TP_INT,
@@ -280,9 +329,9 @@ static struct resource spitzts_resources[] = {
280}; 329};
281 330
282static struct corgits_machinfo spitz_ts_machinfo = { 331static struct corgits_machinfo spitz_ts_machinfo = {
283 .get_hsync_len = spitz_get_hsync_len, 332 .get_hsync_invperiod = spitz_get_hsync_invperiod,
284 .put_hsync = spitz_put_hsync, 333 .put_hsync = spitz_put_hsync,
285 .wait_hsync = spitz_wait_hsync, 334 .wait_hsync = spitz_wait_hsync,
286}; 335};
287 336
288static struct platform_device spitzts_device = { 337static struct platform_device spitzts_device = {
@@ -325,12 +374,10 @@ static int spitz_mci_init(struct device *dev, irq_handler_t spitz_detect_int, vo
325 err = request_irq(SPITZ_IRQ_GPIO_nSD_DETECT, spitz_detect_int, 374 err = request_irq(SPITZ_IRQ_GPIO_nSD_DETECT, spitz_detect_int,
326 IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 375 IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
327 "MMC card detect", data); 376 "MMC card detect", data);
328 if (err) { 377 if (err)
329 printk(KERN_ERR "spitz_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); 378 printk(KERN_ERR "spitz_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
330 return -1;
331 }
332 379
333 return 0; 380 return err;
334} 381}
335 382
336static void spitz_mci_setpower(struct device *dev, unsigned int vdd) 383static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
@@ -423,6 +470,14 @@ static struct pxaficp_platform_data spitz_ficp_platform_data = {
423 * Spitz PXA Framebuffer 470 * Spitz PXA Framebuffer
424 */ 471 */
425 472
473static void spitz_lcd_power(int on, struct fb_var_screeninfo *var)
474{
475 if (on)
476 corgi_lcdtg_hw_init(var->xres);
477 else
478 corgi_lcdtg_suspend();
479}
480
426static struct pxafb_mode_info spitz_pxafb_modes[] = { 481static struct pxafb_mode_info spitz_pxafb_modes[] = {
427{ 482{
428 .pixclock = 19231, 483 .pixclock = 19231,
@@ -520,6 +575,27 @@ static void __init common_init(void)
520 set_pxa_fb_info(&spitz_pxafb_info); 575 set_pxa_fb_info(&spitz_pxafb_info);
521} 576}
522 577
578#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
579static void spitz_bl_set_intensity(int intensity)
580{
581 if (intensity > 0x10)
582 intensity += 0x10;
583
584 /* Bits 0-4 are accessed via the SSP interface */
585 corgi_ssp_blduty_set(intensity & 0x1f);
586
587 /* Bit 5 is via SCOOP */
588 if (intensity & 0x0020)
589 reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
590 else
591 set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
592
593 if (intensity)
594 set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
595 else
596 reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
597}
598
523static void __init spitz_init(void) 599static void __init spitz_init(void)
524{ 600{
525 platform_scoop_config = &spitz_pcmcia_config; 601 platform_scoop_config = &spitz_pcmcia_config;
@@ -530,6 +606,7 @@ static void __init spitz_init(void)
530 606
531 platform_device_register(&spitzscoop2_device); 607 platform_device_register(&spitzscoop2_device);
532} 608}
609#endif
533 610
534#ifdef CONFIG_MACH_AKITA 611#ifdef CONFIG_MACH_AKITA
535/* 612/*
@@ -542,6 +619,26 @@ struct platform_device akitaioexp_device = {
542 619
543EXPORT_SYMBOL_GPL(akitaioexp_device); 620EXPORT_SYMBOL_GPL(akitaioexp_device);
544 621
622static void akita_bl_set_intensity(int intensity)
623{
624 if (intensity > 0x10)
625 intensity += 0x10;
626
627 /* Bits 0-4 are accessed via the SSP interface */
628 corgi_ssp_blduty_set(intensity & 0x1f);
629
630 /* Bit 5 is via IO-Expander */
631 if (intensity & 0x0020)
632 akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
633 else
634 akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
635
636 if (intensity)
637 akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
638 else
639 akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
640}
641
545static void __init akita_init(void) 642static void __init akita_init(void)
546{ 643{
547 spitz_ficp_platform_data.transceiver_mode = akita_irda_transceiver_mode; 644 spitz_ficp_platform_data.transceiver_mode = akita_irda_transceiver_mode;
@@ -558,7 +655,6 @@ static void __init akita_init(void)
558} 655}
559#endif 656#endif
560 657
561
562static void __init fixup_spitz(struct machine_desc *desc, 658static void __init fixup_spitz(struct machine_desc *desc,
563 struct tag *tags, char **cmdline, struct meminfo *mi) 659 struct tag *tags, char **cmdline, struct meminfo *mi)
564{ 660{
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c
index b2eb38543d1c..00af7f2fed66 100644
--- a/arch/arm/mach-pxa/ssp.c
+++ b/arch/arm/mach-pxa/ssp.c
@@ -32,45 +32,27 @@
32#include <linux/ioport.h> 32#include <linux/ioport.h>
33#include <linux/init.h> 33#include <linux/init.h>
34#include <linux/mutex.h> 34#include <linux/mutex.h>
35#include <linux/clk.h>
36#include <linux/err.h>
37#include <linux/platform_device.h>
38
35#include <asm/io.h> 39#include <asm/io.h>
36#include <asm/irq.h> 40#include <asm/irq.h>
37#include <asm/hardware.h> 41#include <asm/hardware.h>
38#include <asm/arch/ssp.h> 42#include <asm/arch/ssp.h>
39#include <asm/arch/pxa-regs.h> 43#include <asm/arch/pxa-regs.h>
40 44#include <asm/arch/regs-ssp.h>
41#define PXA_SSP_PORTS 3
42 45
43#define TIMEOUT 100000 46#define TIMEOUT 100000
44 47
45struct ssp_info_ {
46 int irq;
47 u32 clock;
48};
49
50/*
51 * SSP port clock and IRQ settings
52 */
53static const struct ssp_info_ ssp_info[PXA_SSP_PORTS] = {
54#if defined (CONFIG_PXA27x)
55 {IRQ_SSP, CKEN_SSP1},
56 {IRQ_SSP2, CKEN_SSP2},
57 {IRQ_SSP3, CKEN_SSP3},
58#else
59 {IRQ_SSP, CKEN_SSP},
60 {IRQ_NSSP, CKEN_NSSP},
61 {IRQ_ASSP, CKEN_ASSP},
62#endif
63};
64
65static DEFINE_MUTEX(mutex);
66static int use_count[PXA_SSP_PORTS] = {0, 0, 0};
67
68static irqreturn_t ssp_interrupt(int irq, void *dev_id) 48static irqreturn_t ssp_interrupt(int irq, void *dev_id)
69{ 49{
70 struct ssp_dev *dev = dev_id; 50 struct ssp_dev *dev = dev_id;
71 unsigned int status = SSSR_P(dev->port); 51 struct ssp_device *ssp = dev->ssp;
52 unsigned int status;
72 53
73 SSSR_P(dev->port) = status; /* clear status bits */ 54 status = __raw_readl(ssp->mmio_base + SSSR);
55 __raw_writel(status, ssp->mmio_base + SSSR);
74 56
75 if (status & SSSR_ROR) 57 if (status & SSSR_ROR)
76 printk(KERN_WARNING "SSP(%d): receiver overrun\n", dev->port); 58 printk(KERN_WARNING "SSP(%d): receiver overrun\n", dev->port);
@@ -99,15 +81,16 @@ static irqreturn_t ssp_interrupt(int irq, void *dev_id)
99 */ 81 */
100int ssp_write_word(struct ssp_dev *dev, u32 data) 82int ssp_write_word(struct ssp_dev *dev, u32 data)
101{ 83{
84 struct ssp_device *ssp = dev->ssp;
102 int timeout = TIMEOUT; 85 int timeout = TIMEOUT;
103 86
104 while (!(SSSR_P(dev->port) & SSSR_TNF)) { 87 while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_TNF)) {
105 if (!--timeout) 88 if (!--timeout)
106 return -ETIMEDOUT; 89 return -ETIMEDOUT;
107 cpu_relax(); 90 cpu_relax();
108 } 91 }
109 92
110 SSDR_P(dev->port) = data; 93 __raw_writel(data, ssp->mmio_base + SSDR);
111 94
112 return 0; 95 return 0;
113} 96}
@@ -129,15 +112,16 @@ int ssp_write_word(struct ssp_dev *dev, u32 data)
129 */ 112 */
130int ssp_read_word(struct ssp_dev *dev, u32 *data) 113int ssp_read_word(struct ssp_dev *dev, u32 *data)
131{ 114{
115 struct ssp_device *ssp = dev->ssp;
132 int timeout = TIMEOUT; 116 int timeout = TIMEOUT;
133 117
134 while (!(SSSR_P(dev->port) & SSSR_RNE)) { 118 while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE)) {
135 if (!--timeout) 119 if (!--timeout)
136 return -ETIMEDOUT; 120 return -ETIMEDOUT;
137 cpu_relax(); 121 cpu_relax();
138 } 122 }
139 123
140 *data = SSDR_P(dev->port); 124 *data = __raw_readl(ssp->mmio_base + SSDR);
141 return 0; 125 return 0;
142} 126}
143 127
@@ -151,17 +135,28 @@ int ssp_read_word(struct ssp_dev *dev, u32 *data)
151 */ 135 */
152int ssp_flush(struct ssp_dev *dev) 136int ssp_flush(struct ssp_dev *dev)
153{ 137{
138 struct ssp_device *ssp = dev->ssp;
154 int timeout = TIMEOUT * 2; 139 int timeout = TIMEOUT * 2;
155 140
141 /* ensure TX FIFO is empty instead of not full */
142 if (cpu_is_pxa3xx()) {
143 while (__raw_readl(ssp->mmio_base + SSSR) & 0xf00) {
144 if (!--timeout)
145 return -ETIMEDOUT;
146 cpu_relax();
147 }
148 timeout = TIMEOUT * 2;
149 }
150
156 do { 151 do {
157 while (SSSR_P(dev->port) & SSSR_RNE) { 152 while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE) {
158 if (!--timeout) 153 if (!--timeout)
159 return -ETIMEDOUT; 154 return -ETIMEDOUT;
160 (void) SSDR_P(dev->port); 155 (void)__raw_readl(ssp->mmio_base + SSDR);
161 } 156 }
162 if (!--timeout) 157 if (!--timeout)
163 return -ETIMEDOUT; 158 return -ETIMEDOUT;
164 } while (SSSR_P(dev->port) & SSSR_BSY); 159 } while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_BSY);
165 160
166 return 0; 161 return 0;
167} 162}
@@ -173,7 +168,12 @@ int ssp_flush(struct ssp_dev *dev)
173 */ 168 */
174void ssp_enable(struct ssp_dev *dev) 169void ssp_enable(struct ssp_dev *dev)
175{ 170{
176 SSCR0_P(dev->port) |= SSCR0_SSE; 171 struct ssp_device *ssp = dev->ssp;
172 uint32_t sscr0;
173
174 sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
175 sscr0 |= SSCR0_SSE;
176 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
177} 177}
178 178
179/** 179/**
@@ -183,7 +183,12 @@ void ssp_enable(struct ssp_dev *dev)
183 */ 183 */
184void ssp_disable(struct ssp_dev *dev) 184void ssp_disable(struct ssp_dev *dev)
185{ 185{
186 SSCR0_P(dev->port) &= ~SSCR0_SSE; 186 struct ssp_device *ssp = dev->ssp;
187 uint32_t sscr0;
188
189 sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
190 sscr0 &= ~SSCR0_SSE;
191 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
187} 192}
188 193
189/** 194/**
@@ -192,14 +197,16 @@ void ssp_disable(struct ssp_dev *dev)
192 * 197 *
193 * Save the configured SSP state for suspend. 198 * Save the configured SSP state for suspend.
194 */ 199 */
195void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp) 200void ssp_save_state(struct ssp_dev *dev, struct ssp_state *state)
196{ 201{
197 ssp->cr0 = SSCR0_P(dev->port); 202 struct ssp_device *ssp = dev->ssp;
198 ssp->cr1 = SSCR1_P(dev->port); 203
199 ssp->to = SSTO_P(dev->port); 204 state->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
200 ssp->psp = SSPSP_P(dev->port); 205 state->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
206 state->to = __raw_readl(ssp->mmio_base + SSTO);
207 state->psp = __raw_readl(ssp->mmio_base + SSPSP);
201 208
202 SSCR0_P(dev->port) &= ~SSCR0_SSE; 209 ssp_disable(dev);
203} 210}
204 211
205/** 212/**
@@ -208,16 +215,18 @@ void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp)
208 * 215 *
209 * Restore the SSP configuration saved previously by ssp_save_state. 216 * Restore the SSP configuration saved previously by ssp_save_state.
210 */ 217 */
211void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp) 218void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *state)
212{ 219{
213 SSSR_P(dev->port) = SSSR_ROR | SSSR_TUR | SSSR_BCE; 220 struct ssp_device *ssp = dev->ssp;
221 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
214 222
215 SSCR0_P(dev->port) = ssp->cr0 & ~SSCR0_SSE; 223 __raw_writel(sssr, ssp->mmio_base + SSSR);
216 SSCR1_P(dev->port) = ssp->cr1;
217 SSTO_P(dev->port) = ssp->to;
218 SSPSP_P(dev->port) = ssp->psp;
219 224
220 SSCR0_P(dev->port) = ssp->cr0; 225 __raw_writel(state->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
226 __raw_writel(state->cr1, ssp->mmio_base + SSCR1);
227 __raw_writel(state->to, ssp->mmio_base + SSTO);
228 __raw_writel(state->psp, ssp->mmio_base + SSPSP);
229 __raw_writel(state->cr0, ssp->mmio_base + SSCR0);
221} 230}
222 231
223/** 232/**
@@ -231,15 +240,17 @@ void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp)
231 */ 240 */
232int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed) 241int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed)
233{ 242{
243 struct ssp_device *ssp = dev->ssp;
244
234 dev->mode = mode; 245 dev->mode = mode;
235 dev->flags = flags; 246 dev->flags = flags;
236 dev->psp_flags = psp_flags; 247 dev->psp_flags = psp_flags;
237 dev->speed = speed; 248 dev->speed = speed;
238 249
239 /* set up port type, speed, port settings */ 250 /* set up port type, speed, port settings */
240 SSCR0_P(dev->port) = (dev->speed | dev->mode); 251 __raw_writel((dev->speed | dev->mode), ssp->mmio_base + SSCR0);
241 SSCR1_P(dev->port) = dev->flags; 252 __raw_writel(dev->flags, ssp->mmio_base + SSCR1);
242 SSPSP_P(dev->port) = dev->psp_flags; 253 __raw_writel(dev->psp_flags, ssp->mmio_base + SSPSP);
243 254
244 return 0; 255 return 0;
245} 256}
@@ -256,44 +267,32 @@ int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 spee
256 */ 267 */
257int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags) 268int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags)
258{ 269{
270 struct ssp_device *ssp;
259 int ret; 271 int ret;
260 272
261 if (port > PXA_SSP_PORTS || port == 0) 273 ssp = ssp_request(port, "SSP");
274 if (ssp == NULL)
262 return -ENODEV; 275 return -ENODEV;
263 276
264 mutex_lock(&mutex); 277 dev->ssp = ssp;
265 if (use_count[port - 1]) {
266 mutex_unlock(&mutex);
267 return -EBUSY;
268 }
269 use_count[port - 1]++;
270
271 if (!request_mem_region(__PREG(SSCR0_P(port)), 0x2c, "SSP")) {
272 use_count[port - 1]--;
273 mutex_unlock(&mutex);
274 return -EBUSY;
275 }
276 dev->port = port; 278 dev->port = port;
277 279
278 /* do we need to get irq */ 280 /* do we need to get irq */
279 if (!(init_flags & SSP_NO_IRQ)) { 281 if (!(init_flags & SSP_NO_IRQ)) {
280 ret = request_irq(ssp_info[port-1].irq, ssp_interrupt, 282 ret = request_irq(ssp->irq, ssp_interrupt,
281 0, "SSP", dev); 283 0, "SSP", dev);
282 if (ret) 284 if (ret)
283 goto out_region; 285 goto out_region;
284 dev->irq = ssp_info[port-1].irq; 286 dev->irq = ssp->irq;
285 } else 287 } else
286 dev->irq = 0; 288 dev->irq = 0;
287 289
288 /* turn on SSP port clock */ 290 /* turn on SSP port clock */
289 pxa_set_cken(ssp_info[port-1].clock, 1); 291 clk_enable(ssp->clk);
290 mutex_unlock(&mutex);
291 return 0; 292 return 0;
292 293
293out_region: 294out_region:
294 release_mem_region(__PREG(SSCR0_P(port)), 0x2c); 295 ssp_free(ssp);
295 use_count[port - 1]--;
296 mutex_unlock(&mutex);
297 return ret; 296 return ret;
298} 297}
299 298
@@ -304,23 +303,240 @@ out_region:
304 */ 303 */
305void ssp_exit(struct ssp_dev *dev) 304void ssp_exit(struct ssp_dev *dev)
306{ 305{
307 mutex_lock(&mutex); 306 struct ssp_device *ssp = dev->ssp;
308 SSCR0_P(dev->port) &= ~SSCR0_SSE; 307
308 ssp_disable(dev);
309 free_irq(dev->irq, dev);
310 clk_disable(ssp->clk);
311 ssp_free(ssp);
312}
313
314static DEFINE_MUTEX(ssp_lock);
315static LIST_HEAD(ssp_list);
316
317struct ssp_device *ssp_request(int port, const char *label)
318{
319 struct ssp_device *ssp = NULL;
320
321 mutex_lock(&ssp_lock);
322
323 list_for_each_entry(ssp, &ssp_list, node) {
324 if (ssp->port_id == port && ssp->use_count == 0) {
325 ssp->use_count++;
326 ssp->label = label;
327 break;
328 }
329 }
330
331 mutex_unlock(&ssp_lock);
332
333 if (ssp->port_id != port)
334 return NULL;
335
336 return ssp;
337}
338EXPORT_SYMBOL(ssp_request);
339
340void ssp_free(struct ssp_device *ssp)
341{
342 mutex_lock(&ssp_lock);
343 if (ssp->use_count) {
344 ssp->use_count--;
345 ssp->label = NULL;
346 } else
347 dev_err(&ssp->pdev->dev, "device already free\n");
348 mutex_unlock(&ssp_lock);
349}
350EXPORT_SYMBOL(ssp_free);
351
352static int __devinit ssp_probe(struct platform_device *pdev, int type)
353{
354 struct resource *res;
355 struct ssp_device *ssp;
356 int ret = 0;
357
358 ssp = kzalloc(sizeof(struct ssp_device), GFP_KERNEL);
359 if (ssp == NULL) {
360 dev_err(&pdev->dev, "failed to allocate memory");
361 return -ENOMEM;
362 }
363
364 ssp->clk = clk_get(&pdev->dev, "SSPCLK");
365 if (IS_ERR(ssp->clk)) {
366 ret = PTR_ERR(ssp->clk);
367 goto err_free;
368 }
369
370 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
371 if (res == NULL) {
372 dev_err(&pdev->dev, "no memory resource defined\n");
373 ret = -ENODEV;
374 goto err_free_clk;
375 }
376
377 res = request_mem_region(res->start, res->end - res->start + 1,
378 pdev->name);
379 if (res == NULL) {
380 dev_err(&pdev->dev, "failed to request memory resource\n");
381 ret = -EBUSY;
382 goto err_free_clk;
383 }
384
385 ssp->phys_base = res->start;
386
387 ssp->mmio_base = ioremap(res->start, res->end - res->start + 1);
388 if (ssp->mmio_base == NULL) {
389 dev_err(&pdev->dev, "failed to ioremap() registers\n");
390 ret = -ENODEV;
391 goto err_free_mem;
392 }
393
394 ssp->irq = platform_get_irq(pdev, 0);
395 if (ssp->irq < 0) {
396 dev_err(&pdev->dev, "no IRQ resource defined\n");
397 ret = -ENODEV;
398 goto err_free_io;
399 }
400
401 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
402 if (res == NULL) {
403 dev_err(&pdev->dev, "no SSP RX DRCMR defined\n");
404 ret = -ENODEV;
405 goto err_free_io;
406 }
407 ssp->drcmr_rx = res->start;
408
409 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
410 if (res == NULL) {
411 dev_err(&pdev->dev, "no SSP TX DRCMR defined\n");
412 ret = -ENODEV;
413 goto err_free_io;
414 }
415 ssp->drcmr_tx = res->start;
416
417 /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id
418 * starts from 0, do a translation here
419 */
420 ssp->port_id = pdev->id + 1;
421 ssp->use_count = 0;
422 ssp->type = type;
423
424 mutex_lock(&ssp_lock);
425 list_add(&ssp->node, &ssp_list);
426 mutex_unlock(&ssp_lock);
427
428 platform_set_drvdata(pdev, ssp);
429 return 0;
430
431err_free_io:
432 iounmap(ssp->mmio_base);
433err_free_mem:
434 release_mem_region(res->start, res->end - res->start + 1);
435err_free_clk:
436 clk_put(ssp->clk);
437err_free:
438 kfree(ssp);
439 return ret;
440}
441
442static int __devexit ssp_remove(struct platform_device *pdev)
443{
444 struct resource *res;
445 struct ssp_device *ssp;
446
447 ssp = platform_get_drvdata(pdev);
448 if (ssp == NULL)
449 return -ENODEV;
450
451 iounmap(ssp->mmio_base);
452
453 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
454 release_mem_region(res->start, res->end - res->start + 1);
455
456 clk_put(ssp->clk);
309 457
310 if (dev->port > PXA_SSP_PORTS || dev->port == 0) { 458 mutex_lock(&ssp_lock);
311 printk(KERN_WARNING "SSP: tried to close invalid port\n"); 459 list_del(&ssp->node);
312 mutex_unlock(&mutex); 460 mutex_unlock(&ssp_lock);
313 return; 461
462 kfree(ssp);
463 return 0;
464}
465
466static int __devinit pxa25x_ssp_probe(struct platform_device *pdev)
467{
468 return ssp_probe(pdev, PXA25x_SSP);
469}
470
471static int __devinit pxa25x_nssp_probe(struct platform_device *pdev)
472{
473 return ssp_probe(pdev, PXA25x_NSSP);
474}
475
476static int __devinit pxa27x_ssp_probe(struct platform_device *pdev)
477{
478 return ssp_probe(pdev, PXA27x_SSP);
479}
480
481static struct platform_driver pxa25x_ssp_driver = {
482 .driver = {
483 .name = "pxa25x-ssp",
484 },
485 .probe = pxa25x_ssp_probe,
486 .remove = __devexit_p(ssp_remove),
487};
488
489static struct platform_driver pxa25x_nssp_driver = {
490 .driver = {
491 .name = "pxa25x-nssp",
492 },
493 .probe = pxa25x_nssp_probe,
494 .remove = __devexit_p(ssp_remove),
495};
496
497static struct platform_driver pxa27x_ssp_driver = {
498 .driver = {
499 .name = "pxa27x-ssp",
500 },
501 .probe = pxa27x_ssp_probe,
502 .remove = __devexit_p(ssp_remove),
503};
504
505static int __init pxa_ssp_init(void)
506{
507 int ret = 0;
508
509 ret = platform_driver_register(&pxa25x_ssp_driver);
510 if (ret) {
511 printk(KERN_ERR "failed to register pxa25x_ssp_driver");
512 return ret;
513 }
514
515 ret = platform_driver_register(&pxa25x_nssp_driver);
516 if (ret) {
517 printk(KERN_ERR "failed to register pxa25x_nssp_driver");
518 return ret;
519 }
520
521 ret = platform_driver_register(&pxa27x_ssp_driver);
522 if (ret) {
523 printk(KERN_ERR "failed to register pxa27x_ssp_driver");
524 return ret;
314 } 525 }
315 526
316 pxa_set_cken(ssp_info[dev->port-1].clock, 0); 527 return ret;
317 if (dev->irq) 528}
318 free_irq(dev->irq, dev); 529
319 release_mem_region(__PREG(SSCR0_P(dev->port)), 0x2c); 530static void __exit pxa_ssp_exit(void)
320 use_count[dev->port - 1]--; 531{
321 mutex_unlock(&mutex); 532 platform_driver_unregister(&pxa25x_ssp_driver);
533 platform_driver_unregister(&pxa25x_nssp_driver);
534 platform_driver_unregister(&pxa27x_ssp_driver);
322} 535}
323 536
537arch_initcall(pxa_ssp_init);
538module_exit(pxa_ssp_exit);
539
324EXPORT_SYMBOL(ssp_write_word); 540EXPORT_SYMBOL(ssp_write_word);
325EXPORT_SYMBOL(ssp_read_word); 541EXPORT_SYMBOL(ssp_read_word);
326EXPORT_SYMBOL(ssp_flush); 542EXPORT_SYMBOL(ssp_flush);
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S
index d774430d02c0..167412e6bec8 100644
--- a/arch/arm/mach-pxa/standby.S
+++ b/arch/arm/mach-pxa/standby.S
@@ -17,6 +17,7 @@
17 17
18 .text 18 .text
19 19
20#ifdef CONFIG_PXA27x
20ENTRY(pxa_cpu_standby) 21ENTRY(pxa_cpu_standby)
21 ldr r0, =PSSR 22 ldr r0, =PSSR
22 mov r1, #(PSSR_PH | PSSR_STS) 23 mov r1, #(PSSR_PH | PSSR_STS)
@@ -29,3 +30,85 @@ ENTRY(pxa_cpu_standby)
291: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby 301: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
30 str r1, [r0] @ make sure PSSR_PH/STS are clear 31 str r1, [r0] @ make sure PSSR_PH/STS are clear
31 mov pc, lr 32 mov pc, lr
33
34#endif
35
36#ifdef CONFIG_PXA3xx
37
38#define MDCNFG 0x0000
39#define MDCNFG_DMCEN (1 << 30)
40#define DDR_HCAL 0x0060
41#define DDR_HCAL_HCRNG 0x1f
42#define DDR_HCAL_HCPROG (1 << 28)
43#define DDR_HCAL_HCEN (1 << 31)
44#define DMCIER 0x0070
45#define DMCIER_EDLP (1 << 29)
46#define DMCISR 0x0078
47#define RCOMP 0x0100
48#define RCOMP_SWEVAL (1 << 31)
49
50ENTRY(pm_enter_standby_start)
51 mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG)
52 add r1, r1, #0x00100000
53
54 /*
55 * Preload the TLB entry for accessing the dynamic memory
56 * controller registers. Note that page table lookups will
57 * fail until the dynamic memory controller has been
58 * reinitialised - and that includes MMU page table walks.
59 * This also means that only the dynamic memory controller
60 * can be reliably accessed in the code following standby.
61 */
62 ldr r2, [r1] @ Dummy read MDCNFG
63
64 mcr p14, 0, r0, c7, c0, 0
65 .rept 8
66 nop
67 .endr
68
69 ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN
70 bic r0, r0, #DDR_HCAL_HCEN
71 str r0, [r1, #DDR_HCAL]
721: ldr r0, [r1, #DDR_HCAL]
73 tst r0, #DDR_HCAL_HCEN
74 bne 1b
75
76 ldr r0, [r1, #RCOMP] @ Initiate RCOMP
77 orr r0, r0, #RCOMP_SWEVAL
78 str r0, [r1, #RCOMP]
79
80 mov r0, #~0 @ Clear interrupts
81 str r0, [r1, #DMCISR]
82
83 ldr r0, [r1, #DMCIER] @ set DMIER[EDLP]
84 orr r0, r0, #DMCIER_EDLP
85 str r0, [r1, #DMCIER]
86
87 ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
88 bic r0, r0, #DDR_HCAL_HCRNG
89 orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG
90 str r0, [r1, #DDR_HCAL]
91
921: ldr r0, [r1, #DMCISR]
93 tst r0, #DMCIER_EDLP
94 beq 1b
95
96 ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN]
97 orr r0, r0, #MDCNFG_DMCEN
98 str r0, [r1, #MDCNFG]
991: ldr r0, [r1, #MDCNFG]
100 tst r0, #MDCNFG_DMCEN
101 beq 1b
102
103 ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG]
104 orr r0, r0, #2 @ HCRNG
105 str r0, [r1, #DDR_HCAL]
106
107 ldr r0, [r1, #DMCIER] @ Clear the interrupt
108 bic r0, r0, #0x20000000
109 str r0, [r1, #DMCIER]
110
111 mov pc, lr
112ENTRY(pm_enter_standby_end)
113
114#endif
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index fbfa1920353d..7b7c0179795b 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -59,55 +59,17 @@ unsigned long long sched_clock(void)
59} 59}
60 60
61 61
62#define MIN_OSCR_DELTA 16
63
62static irqreturn_t 64static irqreturn_t
63pxa_ost0_interrupt(int irq, void *dev_id) 65pxa_ost0_interrupt(int irq, void *dev_id)
64{ 66{
65 int next_match;
66 struct clock_event_device *c = dev_id; 67 struct clock_event_device *c = dev_id;
67 68
68 if (c->mode == CLOCK_EVT_MODE_ONESHOT) { 69 /* Disarm the compare/match, signal the event. */
69 /* Disarm the compare/match, signal the event. */ 70 OIER &= ~OIER_E0;
70 OIER &= ~OIER_E0; 71 OSSR = OSSR_M0;
71 OSSR = OSSR_M0; 72 c->event_handler(c);
72 c->event_handler(c);
73 } else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
74 /* Call the event handler as many times as necessary
75 * to recover missed events, if any (if we update
76 * OSMR0 and OSCR0 is still ahead of us, we've missed
77 * the event). As we're dealing with that, re-arm the
78 * compare/match for the next event.
79 *
80 * HACK ALERT:
81 *
82 * There's a latency between the instruction that
83 * writes to OSMR0 and the actual commit to the
84 * physical hardware, because the CPU doesn't (have
85 * to) run at bus speed, there's a write buffer
86 * between the CPU and the bus, etc. etc. So if the
87 * target OSCR0 is "very close", to the OSMR0 load
88 * value, the update to OSMR0 might not get to the
89 * hardware in time and we'll miss that interrupt.
90 *
91 * To be safe, if the new OSMR0 is "very close" to the
92 * target OSCR0 value, we call the event_handler as
93 * though the event actually happened. According to
94 * Nico's comment in the previous version of this
95 * code, experience has shown that 6 OSCR ticks is
96 * "very close" but he went with 8. We will use 16,
97 * based on the results of testing on PXA270.
98 *
99 * To be doubly sure, we also tell clkevt via
100 * clockevents_register_device() not to ask for
101 * anything that might put us "very close".
102 */
103#define MIN_OSCR_DELTA 16
104 do {
105 OSSR = OSSR_M0;
106 next_match = (OSMR0 += LATCH);
107 c->event_handler(c);
108 } while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
109 && (c->mode == CLOCK_EVT_MODE_PERIODIC));
110 }
111 73
112 return IRQ_HANDLED; 74 return IRQ_HANDLED;
113} 75}
@@ -133,14 +95,6 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
133 unsigned long irqflags; 95 unsigned long irqflags;
134 96
135 switch (mode) { 97 switch (mode) {
136 case CLOCK_EVT_MODE_PERIODIC:
137 raw_local_irq_save(irqflags);
138 OSSR = OSSR_M0;
139 OIER |= OIER_E0;
140 OSMR0 = OSCR + LATCH;
141 raw_local_irq_restore(irqflags);
142 break;
143
144 case CLOCK_EVT_MODE_ONESHOT: 98 case CLOCK_EVT_MODE_ONESHOT:
145 raw_local_irq_save(irqflags); 99 raw_local_irq_save(irqflags);
146 OIER &= ~OIER_E0; 100 OIER &= ~OIER_E0;
@@ -158,13 +112,14 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
158 break; 112 break;
159 113
160 case CLOCK_EVT_MODE_RESUME: 114 case CLOCK_EVT_MODE_RESUME:
115 case CLOCK_EVT_MODE_PERIODIC:
161 break; 116 break;
162 } 117 }
163} 118}
164 119
165static struct clock_event_device ckevt_pxa_osmr0 = { 120static struct clock_event_device ckevt_pxa_osmr0 = {
166 .name = "osmr0", 121 .name = "osmr0",
167 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 122 .features = CLOCK_EVT_FEAT_ONESHOT,
168 .shift = 32, 123 .shift = 32,
169 .rating = 200, 124 .rating = 200,
170 .cpumask = CPU_MASK_CPU0, 125 .cpumask = CPU_MASK_CPU0,
@@ -214,7 +169,7 @@ static void __init pxa_timer_init(void)
214 ckevt_pxa_osmr0.max_delta_ns = 169 ckevt_pxa_osmr0.max_delta_ns =
215 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); 170 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
216 ckevt_pxa_osmr0.min_delta_ns = 171 ckevt_pxa_osmr0.min_delta_ns =
217 clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1; 172 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
218 173
219 cksrc_pxa_oscr0.mult = 174 cksrc_pxa_oscr0.mult =
220 clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift); 175 clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
@@ -226,7 +181,7 @@ static void __init pxa_timer_init(void)
226} 181}
227 182
228#ifdef CONFIG_PM 183#ifdef CONFIG_PM
229static unsigned long osmr[4], oier; 184static unsigned long osmr[4], oier, oscr;
230 185
231static void pxa_timer_suspend(void) 186static void pxa_timer_suspend(void)
232{ 187{
@@ -235,23 +190,26 @@ static void pxa_timer_suspend(void)
235 osmr[2] = OSMR2; 190 osmr[2] = OSMR2;
236 osmr[3] = OSMR3; 191 osmr[3] = OSMR3;
237 oier = OIER; 192 oier = OIER;
193 oscr = OSCR;
238} 194}
239 195
240static void pxa_timer_resume(void) 196static void pxa_timer_resume(void)
241{ 197{
198 /*
199 * Ensure that we have at least MIN_OSCR_DELTA between match
200 * register 0 and the OSCR, to guarantee that we will receive
201 * the one-shot timer interrupt. We adjust OSMR0 in preference
202 * to OSCR to guarantee that OSCR is monotonically incrementing.
203 */
204 if (osmr[0] - oscr < MIN_OSCR_DELTA)
205 osmr[0] += MIN_OSCR_DELTA;
206
242 OSMR0 = osmr[0]; 207 OSMR0 = osmr[0];
243 OSMR1 = osmr[1]; 208 OSMR1 = osmr[1];
244 OSMR2 = osmr[2]; 209 OSMR2 = osmr[2];
245 OSMR3 = osmr[3]; 210 OSMR3 = osmr[3];
246 OIER = oier; 211 OIER = oier;
247 212 OSCR = oscr;
248 /*
249 * OSCR0 is the system timer, which has to increase
250 * monotonically until it rolls over in hardware. The value
251 * (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
252 * which is a handy value to restore to OSCR0.
253 */
254 OSCR = OSMR0 - LATCH;
255} 213}
256#else 214#else
257#define pxa_timer_suspend NULL 215#define pxa_timer_suspend NULL
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 240fd042083d..1919756900f4 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -184,16 +184,13 @@ static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void
184 184
185 tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250); 185 tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250);
186 186
187 err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int, IRQF_DISABLED, 187 err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int,
188 IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
188 "MMC/SD card detect", data); 189 "MMC/SD card detect", data);
189 if (err) { 190 if (err)
190 printk(KERN_ERR "tosa_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); 191 printk(KERN_ERR "tosa_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
191 return -1;
192 }
193
194 set_irq_type(TOSA_IRQ_GPIO_nSD_DETECT, IRQT_BOTHEDGE);
195 192
196 return 0; 193 return err;
197} 194}
198 195
199static void tosa_mci_setpower(struct device *dev, unsigned int vdd) 196static void tosa_mci_setpower(struct device *dev, unsigned int vdd)
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index e4ba43bdf85d..853fc9433750 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -296,11 +296,10 @@ static int trizeps4_mci_init(struct device *dev, irq_handler_t mci_detect_int, v
296 err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int, 296 err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int,
297 IRQF_DISABLED | IRQF_TRIGGER_RISING, 297 IRQF_DISABLED | IRQF_TRIGGER_RISING,
298 "MMC card detect", data); 298 "MMC card detect", data);
299 if (err) { 299 if (err)
300 printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); 300 printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
301 return -1; 301
302 } 302 return err;
303 return 0;
304} 303}
305 304
306static void trizeps4_mci_exit(struct device *dev, void *data) 305static void trizeps4_mci_exit(struct device *dev, void *data)
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 743a87b2faa1..7731d50dd86c 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -25,9 +25,13 @@
25#include <asm/arch/gpio.h> 25#include <asm/arch/gpio.h>
26#include <asm/arch/pxafb.h> 26#include <asm/arch/pxafb.h>
27#include <asm/arch/zylonite.h> 27#include <asm/arch/zylonite.h>
28#include <asm/arch/mmc.h>
28 29
29#include "generic.h" 30#include "generic.h"
30 31
32#define MAX_SLOTS 3
33struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS];
34
31int gpio_backlight; 35int gpio_backlight;
32int gpio_eth_irq; 36int gpio_eth_irq;
33 37
@@ -43,7 +47,7 @@ static struct resource smc91x_resources[] = {
43 [1] = { 47 [1] = {
44 .start = -1, /* for run-time assignment */ 48 .start = -1, /* for run-time assignment */
45 .end = -1, 49 .end = -1,
46 .flags = IORESOURCE_IRQ, 50 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
47 } 51 }
48}; 52};
49 53
@@ -156,6 +160,95 @@ static void __init zylonite_init_lcd(void)
156static inline void zylonite_init_lcd(void) {} 160static inline void zylonite_init_lcd(void) {}
157#endif 161#endif
158 162
163#if defined(CONFIG_MMC)
164static int zylonite_mci_ro(struct device *dev)
165{
166 struct platform_device *pdev = to_platform_device(dev);
167
168 return gpio_get_value(zylonite_mmc_slot[pdev->id].gpio_wp);
169}
170
171static int zylonite_mci_init(struct device *dev,
172 irq_handler_t zylonite_detect_int,
173 void *data)
174{
175 struct platform_device *pdev = to_platform_device(dev);
176 int err, cd_irq, gpio_cd, gpio_wp;
177
178 cd_irq = gpio_to_irq(zylonite_mmc_slot[pdev->id].gpio_cd);
179 gpio_cd = zylonite_mmc_slot[pdev->id].gpio_cd;
180 gpio_wp = zylonite_mmc_slot[pdev->id].gpio_wp;
181
182 /*
183 * setup GPIO for Zylonite MMC controller
184 */
185 err = gpio_request(gpio_cd, "mmc card detect");
186 if (err)
187 goto err_request_cd;
188 gpio_direction_input(gpio_cd);
189
190 err = gpio_request(gpio_wp, "mmc write protect");
191 if (err)
192 goto err_request_wp;
193 gpio_direction_input(gpio_wp);
194
195 err = request_irq(cd_irq, zylonite_detect_int,
196 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
197 "MMC card detect", data);
198 if (err) {
199 printk(KERN_ERR "%s: MMC/SD/SDIO: "
200 "can't request card detect IRQ\n", __func__);
201 goto err_request_irq;
202 }
203
204 return 0;
205
206err_request_irq:
207 gpio_free(gpio_wp);
208err_request_wp:
209 gpio_free(gpio_cd);
210err_request_cd:
211 return err;
212}
213
214static void zylonite_mci_exit(struct device *dev, void *data)
215{
216 struct platform_device *pdev = to_platform_device(dev);
217 int cd_irq, gpio_cd, gpio_wp;
218
219 cd_irq = gpio_to_irq(zylonite_mmc_slot[pdev->id].gpio_cd);
220 gpio_cd = zylonite_mmc_slot[pdev->id].gpio_cd;
221 gpio_wp = zylonite_mmc_slot[pdev->id].gpio_wp;
222
223 free_irq(cd_irq, data);
224 gpio_free(gpio_cd);
225 gpio_free(gpio_wp);
226}
227
228static struct pxamci_platform_data zylonite_mci_platform_data = {
229 .detect_delay = 20,
230 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
231 .init = zylonite_mci_init,
232 .exit = zylonite_mci_exit,
233 .get_ro = zylonite_mci_ro,
234};
235
236static struct pxamci_platform_data zylonite_mci2_platform_data = {
237 .detect_delay = 20,
238 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
239};
240
241static void __init zylonite_init_mmc(void)
242{
243 pxa_set_mci_info(&zylonite_mci_platform_data);
244 pxa3xx_set_mci2_info(&zylonite_mci2_platform_data);
245 if (cpu_is_pxa310())
246 pxa3xx_set_mci3_info(&zylonite_mci_platform_data);
247}
248#else
249static inline void zylonite_init_mmc(void) {}
250#endif
251
159static void __init zylonite_init(void) 252static void __init zylonite_init(void)
160{ 253{
161 /* board-processor specific initialization */ 254 /* board-processor specific initialization */
@@ -171,6 +264,7 @@ static void __init zylonite_init(void)
171 platform_device_register(&smc91x_device); 264 platform_device_register(&smc91x_device);
172 265
173 zylonite_init_lcd(); 266 zylonite_init_lcd();
267 zylonite_init_mmc();
174} 268}
175 269
176MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") 270MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 1832bc316501..6ac04c09b0e9 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -53,13 +53,13 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
53 53
54 /* BTUART */ 54 /* BTUART */
55 GPIO111_UART2_RTS, 55 GPIO111_UART2_RTS,
56 GPIO112_UART2_RXD, 56 GPIO112_UART2_RXD | MFP_LPM_EDGE_FALL,
57 GPIO113_UART2_TXD, 57 GPIO113_UART2_TXD,
58 GPIO114_UART2_CTS, 58 GPIO114_UART2_CTS | MFP_LPM_EDGE_BOTH,
59 59
60 /* STUART */ 60 /* STUART */
61 GPIO109_UART3_TXD, 61 GPIO109_UART3_TXD,
62 GPIO110_UART3_RXD, 62 GPIO110_UART3_RXD | MFP_LPM_EDGE_FALL,
63 63
64 /* AC97 */ 64 /* AC97 */
65 GPIO23_AC97_nACRESET, 65 GPIO23_AC97_nACRESET,
@@ -70,16 +70,16 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
70 GPIO28_AC97_SYNC, 70 GPIO28_AC97_SYNC,
71 71
72 /* Keypad */ 72 /* Keypad */
73 GPIO107_KP_DKIN_0, 73 GPIO107_KP_DKIN_0 | MFP_LPM_EDGE_BOTH,
74 GPIO108_KP_DKIN_1, 74 GPIO108_KP_DKIN_1 | MFP_LPM_EDGE_BOTH,
75 GPIO115_KP_MKIN_0, 75 GPIO115_KP_MKIN_0 | MFP_LPM_EDGE_BOTH,
76 GPIO116_KP_MKIN_1, 76 GPIO116_KP_MKIN_1 | MFP_LPM_EDGE_BOTH,
77 GPIO117_KP_MKIN_2, 77 GPIO117_KP_MKIN_2 | MFP_LPM_EDGE_BOTH,
78 GPIO118_KP_MKIN_3, 78 GPIO118_KP_MKIN_3 | MFP_LPM_EDGE_BOTH,
79 GPIO119_KP_MKIN_4, 79 GPIO119_KP_MKIN_4 | MFP_LPM_EDGE_BOTH,
80 GPIO120_KP_MKIN_5, 80 GPIO120_KP_MKIN_5 | MFP_LPM_EDGE_BOTH,
81 GPIO2_2_KP_MKIN_6, 81 GPIO2_2_KP_MKIN_6 | MFP_LPM_EDGE_BOTH,
82 GPIO3_2_KP_MKIN_7, 82 GPIO3_2_KP_MKIN_7 | MFP_LPM_EDGE_BOTH,
83 GPIO121_KP_MKOUT_0, 83 GPIO121_KP_MKOUT_0,
84 GPIO122_KP_MKOUT_1, 84 GPIO122_KP_MKOUT_1,
85 GPIO123_KP_MKOUT_2, 85 GPIO123_KP_MKOUT_2,
@@ -88,16 +88,33 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
88 GPIO4_2_KP_MKOUT_5, 88 GPIO4_2_KP_MKOUT_5,
89 GPIO5_2_KP_MKOUT_6, 89 GPIO5_2_KP_MKOUT_6,
90 GPIO6_2_KP_MKOUT_7, 90 GPIO6_2_KP_MKOUT_7,
91
92 /* MMC1 */
93 GPIO3_MMC1_DAT0,
94 GPIO4_MMC1_DAT1 | MFP_LPM_EDGE_BOTH,
95 GPIO5_MMC1_DAT2,
96 GPIO6_MMC1_DAT3,
97 GPIO7_MMC1_CLK,
98 GPIO8_MMC1_CMD, /* CMD0 for slot 0 */
99 GPIO15_GPIO, /* CMD1 default as GPIO for slot 0 */
100
101 /* MMC2 */
102 GPIO9_MMC2_DAT0,
103 GPIO10_MMC2_DAT1 | MFP_LPM_EDGE_BOTH,
104 GPIO11_MMC2_DAT2,
105 GPIO12_MMC2_DAT3,
106 GPIO13_MMC2_CLK,
107 GPIO14_MMC2_CMD,
91}; 108};
92 109
93static mfp_cfg_t pxa300_mfp_cfg[] __initdata = { 110static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
94 /* FFUART */ 111 /* FFUART */
95 GPIO30_UART1_RXD, 112 GPIO30_UART1_RXD | MFP_LPM_EDGE_FALL,
96 GPIO31_UART1_TXD, 113 GPIO31_UART1_TXD,
97 GPIO32_UART1_CTS, 114 GPIO32_UART1_CTS,
98 GPIO37_UART1_RTS, 115 GPIO37_UART1_RTS,
99 GPIO33_UART1_DCD, 116 GPIO33_UART1_DCD,
100 GPIO34_UART1_DSR, 117 GPIO34_UART1_DSR | MFP_LPM_EDGE_FALL,
101 GPIO35_UART1_RI, 118 GPIO35_UART1_RI,
102 GPIO36_UART1_DTR, 119 GPIO36_UART1_DTR,
103 120
@@ -108,7 +125,7 @@ static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
108 125
109static mfp_cfg_t pxa310_mfp_cfg[] __initdata = { 126static mfp_cfg_t pxa310_mfp_cfg[] __initdata = {
110 /* FFUART */ 127 /* FFUART */
111 GPIO99_UART1_RXD, 128 GPIO99_UART1_RXD | MFP_LPM_EDGE_FALL,
112 GPIO100_UART1_TXD, 129 GPIO100_UART1_TXD,
113 GPIO101_UART1_CTS, 130 GPIO101_UART1_CTS,
114 GPIO106_UART1_RTS, 131 GPIO106_UART1_RTS,
@@ -116,6 +133,14 @@ static mfp_cfg_t pxa310_mfp_cfg[] __initdata = {
116 /* Ethernet */ 133 /* Ethernet */
117 GPIO2_nCS3, 134 GPIO2_nCS3,
118 GPIO102_GPIO, 135 GPIO102_GPIO,
136
137 /* MMC3 */
138 GPIO7_2_MMC3_DAT0,
139 GPIO8_2_MMC3_DAT1 | MFP_LPM_EDGE_BOTH,
140 GPIO9_2_MMC3_DAT2,
141 GPIO10_2_MMC3_DAT3,
142 GPIO103_MMC3_CLK,
143 GPIO105_MMC3_CMD,
119}; 144};
120 145
121#define NUM_LCD_DETECT_PINS 7 146#define NUM_LCD_DETECT_PINS 7
@@ -174,6 +199,10 @@ void __init zylonite_pxa300_init(void)
174 199
175 /* GPIO pin assignment */ 200 /* GPIO pin assignment */
176 gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20); 201 gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20);
202
203 /* MMC card detect & write protect for controller 0 */
204 zylonite_mmc_slot[0].gpio_cd = EXT_GPIO(0);
205 zylonite_mmc_slot[0].gpio_wp = EXT_GPIO(2);
177 } 206 }
178 207
179 if (cpu_is_pxa300()) { 208 if (cpu_is_pxa300()) {
@@ -184,5 +213,9 @@ void __init zylonite_pxa300_init(void)
184 if (cpu_is_pxa310()) { 213 if (cpu_is_pxa310()) {
185 pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg)); 214 pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg));
186 gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102); 215 gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102);
216
217 /* MMC card detect & write protect for controller 2 */
218 zylonite_mmc_slot[2].gpio_cd = EXT_GPIO(30);
219 zylonite_mmc_slot[2].gpio_wp = EXT_GPIO(31);
187 } 220 }
188} 221}
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index 94c715808b59..dfa79992b8ab 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -51,11 +51,11 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
51 GPIO17_2_LCD_BIAS, 51 GPIO17_2_LCD_BIAS,
52 52
53 /* FFUART */ 53 /* FFUART */
54 GPIO41_UART1_RXD, 54 GPIO41_UART1_RXD | MFP_LPM_EDGE_FALL,
55 GPIO42_UART1_TXD, 55 GPIO42_UART1_TXD,
56 GPIO43_UART1_CTS, 56 GPIO43_UART1_CTS,
57 GPIO44_UART1_DCD, 57 GPIO44_UART1_DCD,
58 GPIO45_UART1_DSR, 58 GPIO45_UART1_DSR | MFP_LPM_EDGE_FALL,
59 GPIO46_UART1_RI, 59 GPIO46_UART1_RI,
60 GPIO47_UART1_DTR, 60 GPIO47_UART1_DTR,
61 GPIO48_UART1_RTS, 61 GPIO48_UART1_RTS,
@@ -73,16 +73,16 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
73 GPIO33_I2C_SDA, 73 GPIO33_I2C_SDA,
74 74
75 /* Keypad */ 75 /* Keypad */
76 GPIO105_KP_DKIN_0, 76 GPIO105_KP_DKIN_0 | MFP_LPM_EDGE_BOTH,
77 GPIO106_KP_DKIN_1, 77 GPIO106_KP_DKIN_1 | MFP_LPM_EDGE_BOTH,
78 GPIO113_KP_MKIN_0, 78 GPIO113_KP_MKIN_0 | MFP_LPM_EDGE_BOTH,
79 GPIO114_KP_MKIN_1, 79 GPIO114_KP_MKIN_1 | MFP_LPM_EDGE_BOTH,
80 GPIO115_KP_MKIN_2, 80 GPIO115_KP_MKIN_2 | MFP_LPM_EDGE_BOTH,
81 GPIO116_KP_MKIN_3, 81 GPIO116_KP_MKIN_3 | MFP_LPM_EDGE_BOTH,
82 GPIO117_KP_MKIN_4, 82 GPIO117_KP_MKIN_4 | MFP_LPM_EDGE_BOTH,
83 GPIO118_KP_MKIN_5, 83 GPIO118_KP_MKIN_5 | MFP_LPM_EDGE_BOTH,
84 GPIO119_KP_MKIN_6, 84 GPIO119_KP_MKIN_6 | MFP_LPM_EDGE_BOTH,
85 GPIO120_KP_MKIN_7, 85 GPIO120_KP_MKIN_7 | MFP_LPM_EDGE_BOTH,
86 GPIO121_KP_MKOUT_0, 86 GPIO121_KP_MKOUT_0,
87 GPIO122_KP_MKOUT_1, 87 GPIO122_KP_MKOUT_1,
88 GPIO123_KP_MKOUT_2, 88 GPIO123_KP_MKOUT_2,
@@ -95,6 +95,23 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
95 /* Ethernet */ 95 /* Ethernet */
96 GPIO4_nCS3, 96 GPIO4_nCS3,
97 GPIO90_GPIO, 97 GPIO90_GPIO,
98
99 /* MMC1 */
100 GPIO18_MMC1_DAT0,
101 GPIO19_MMC1_DAT1 | MFP_LPM_EDGE_BOTH,
102 GPIO20_MMC1_DAT2,
103 GPIO21_MMC1_DAT3,
104 GPIO22_MMC1_CLK,
105 GPIO23_MMC1_CMD,/* CMD0 for slot 0 */
106 GPIO31_GPIO, /* CMD1 default as GPIO for slot 0 */
107
108 /* MMC2 */
109 GPIO24_MMC2_DAT0,
110 GPIO25_MMC2_DAT1 | MFP_LPM_EDGE_BOTH,
111 GPIO26_MMC2_DAT2,
112 GPIO27_MMC2_DAT3,
113 GPIO28_MMC2_CLK,
114 GPIO29_MMC2_CMD,
98}; 115};
99 116
100#define NUM_LCD_DETECT_PINS 7 117#define NUM_LCD_DETECT_PINS 7
@@ -169,5 +186,9 @@ void __init zylonite_pxa320_init(void)
169 /* GPIO pin assignment */ 186 /* GPIO pin assignment */
170 gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14); 187 gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14);
171 gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9); 188 gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9);
189
190 /* MMC card detect & write protect for controller 0 */
191 zylonite_mmc_slot[0].gpio_cd = mfp_to_gpio(MFP_PIN_GPIO1);
192 zylonite_mmc_slot[0].gpio_wp = mfp_to_gpio(MFP_PIN_GPIO5);
172 } 193 }
173} 194}
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index 83a5f8b91857..f455233af082 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -29,7 +29,7 @@ static struct resource smc91x_resources[] = {
29 .flags = IORESOURCE_MEM, 29 .flags = IORESOURCE_MEM,
30 }, 30 },
31 [1] = { 31 [1] = {
32 .flags = IORESOURCE_IRQ, 32 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
33 }, 33 },
34}; 34};
35 35
diff --git a/drivers/input/touchscreen/corgi_ts.c b/drivers/input/touchscreen/corgi_ts.c
index b1b2e07bf080..99d92f5c93d6 100644
--- a/drivers/input/touchscreen/corgi_ts.c
+++ b/drivers/input/touchscreen/corgi_ts.c
@@ -74,10 +74,10 @@ extern unsigned int get_clk_frequency_khz(int info);
74 74
75static unsigned long calc_waittime(struct corgi_ts *corgi_ts) 75static unsigned long calc_waittime(struct corgi_ts *corgi_ts)
76{ 76{
77 unsigned long hsync_len = corgi_ts->machinfo->get_hsync_len(); 77 unsigned long hsync_invperiod = corgi_ts->machinfo->get_hsync_invperiod();
78 78
79 if (hsync_len) 79 if (hsync_invperiod)
80 return get_clk_frequency_khz(0)*1000/hsync_len; 80 return get_clk_frequency_khz(0)*1000/hsync_invperiod;
81 else 81 else
82 return 0; 82 return 0;
83} 83}
@@ -114,7 +114,7 @@ static int sync_receive_data_send_cmd(struct corgi_ts *corgi_ts, int doRecive, i
114 if (timer2-timer1 > wait_time) { 114 if (timer2-timer1 > wait_time) {
115 /* too slow - timeout, try again */ 115 /* too slow - timeout, try again */
116 corgi_ts->machinfo->wait_hsync(); 116 corgi_ts->machinfo->wait_hsync();
117 /* get OSCR */ 117 /* get CCNT */
118 CCNT(timer1); 118 CCNT(timer1);
119 /* Wait after HSync */ 119 /* Wait after HSync */
120 CCNT(timer2); 120 CCNT(timer2);
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 1654a3330340..1ea8482037bb 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -65,6 +65,8 @@ struct pxamci_host {
65 unsigned int dma_len; 65 unsigned int dma_len;
66 66
67 unsigned int dma_dir; 67 unsigned int dma_dir;
68 unsigned int dma_drcmrrx;
69 unsigned int dma_drcmrtx;
68}; 70};
69 71
70static void pxamci_stop_clock(struct pxamci_host *host) 72static void pxamci_stop_clock(struct pxamci_host *host)
@@ -131,13 +133,13 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
131 if (data->flags & MMC_DATA_READ) { 133 if (data->flags & MMC_DATA_READ) {
132 host->dma_dir = DMA_FROM_DEVICE; 134 host->dma_dir = DMA_FROM_DEVICE;
133 dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG; 135 dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
134 DRCMRTXMMC = 0; 136 DRCMR(host->dma_drcmrtx) = 0;
135 DRCMRRXMMC = host->dma | DRCMR_MAPVLD; 137 DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD;
136 } else { 138 } else {
137 host->dma_dir = DMA_TO_DEVICE; 139 host->dma_dir = DMA_TO_DEVICE;
138 dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC; 140 dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
139 DRCMRRXMMC = 0; 141 DRCMR(host->dma_drcmrrx) = 0;
140 DRCMRTXMMC = host->dma | DRCMR_MAPVLD; 142 DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD;
141 } 143 }
142 144
143 dcmd |= DCMD_BURST32 | DCMD_WIDTH1; 145 dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
@@ -375,14 +377,23 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
375 if (host->clkrt == CLKRT_OFF) 377 if (host->clkrt == CLKRT_OFF)
376 clk_enable(host->clk); 378 clk_enable(host->clk);
377 379
378 /* 380 if (ios->clock == 26000000) {
379 * clk might result in a lower divisor than we 381 /* to support 26MHz on pxa300/pxa310 */
380 * desire. check for that condition and adjust 382 host->clkrt = 7;
381 * as appropriate. 383 } else {
382 */ 384 /* to handle (19.5MHz, 26MHz) */
383 if (rate / clk > ios->clock) 385 if (!clk)
384 clk <<= 1; 386 clk = 1;
385 host->clkrt = fls(clk) - 1; 387
388 /*
389 * clk might result in a lower divisor than we
390 * desire. check for that condition and adjust
391 * as appropriate.
392 */
393 if (rate / clk > ios->clock)
394 clk <<= 1;
395 host->clkrt = fls(clk) - 1;
396 }
386 397
387 /* 398 /*
388 * we write clkrt on the next command 399 * we write clkrt on the next command
@@ -459,7 +470,7 @@ static int pxamci_probe(struct platform_device *pdev)
459{ 470{
460 struct mmc_host *mmc; 471 struct mmc_host *mmc;
461 struct pxamci_host *host = NULL; 472 struct pxamci_host *host = NULL;
462 struct resource *r; 473 struct resource *r, *dmarx, *dmatx;
463 int ret, irq; 474 int ret, irq;
464 475
465 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 476 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -519,7 +530,8 @@ static int pxamci_probe(struct platform_device *pdev)
519 * Calculate minimum clock rate, rounding up. 530 * Calculate minimum clock rate, rounding up.
520 */ 531 */
521 mmc->f_min = (host->clkrate + 63) / 64; 532 mmc->f_min = (host->clkrate + 63) / 64;
522 mmc->f_max = host->clkrate; 533 mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000
534 : host->clkrate;
523 535
524 mmc->ocr_avail = host->pdata ? 536 mmc->ocr_avail = host->pdata ?
525 host->pdata->ocr_mask : 537 host->pdata->ocr_mask :
@@ -529,6 +541,9 @@ static int pxamci_probe(struct platform_device *pdev)
529 if (!cpu_is_pxa21x() && !cpu_is_pxa25x()) { 541 if (!cpu_is_pxa21x() && !cpu_is_pxa25x()) {
530 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 542 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
531 host->cmdat |= CMDAT_SDIO_INT_EN; 543 host->cmdat |= CMDAT_SDIO_INT_EN;
544 if (cpu_is_pxa300() || cpu_is_pxa310())
545 mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
546 MMC_CAP_SD_HIGHSPEED;
532 } 547 }
533 548
534 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL); 549 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
@@ -570,6 +585,20 @@ static int pxamci_probe(struct platform_device *pdev)
570 585
571 platform_set_drvdata(pdev, mmc); 586 platform_set_drvdata(pdev, mmc);
572 587
588 dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0);
589 if (!dmarx) {
590 ret = -ENXIO;
591 goto out;
592 }
593 host->dma_drcmrrx = dmarx->start;
594
595 dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1);
596 if (!dmatx) {
597 ret = -ENXIO;
598 goto out;
599 }
600 host->dma_drcmrtx = dmatx->start;
601
573 if (host->pdata && host->pdata->init) 602 if (host->pdata && host->pdata->init)
574 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); 603 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
575 604
@@ -613,8 +642,8 @@ static int pxamci_remove(struct platform_device *pdev)
613 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, 642 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
614 host->base + MMC_I_MASK); 643 host->base + MMC_I_MASK);
615 644
616 DRCMRRXMMC = 0; 645 DRCMR(host->dma_drcmrrx) = 0;
617 DRCMRTXMMC = 0; 646 DRCMR(host->dma_drcmrtx) = 0;
618 647
619 free_irq(host->irq, host); 648 free_irq(host->irq, host);
620 pxa_free_dma(host->dma); 649 pxa_free_dma(host->dma);
diff --git a/drivers/mmc/host/pxamci.h b/drivers/mmc/host/pxamci.h
index 748c7706f237..f6c2e2fcce37 100644
--- a/drivers/mmc/host/pxamci.h
+++ b/drivers/mmc/host/pxamci.h
@@ -68,7 +68,7 @@
68#define PRG_DONE (1 << 1) 68#define PRG_DONE (1 << 1)
69#define DATA_TRAN_DONE (1 << 0) 69#define DATA_TRAN_DONE (1 << 0)
70 70
71#ifdef CONFIG_PXA27x 71#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
72#define MMC_I_MASK_ALL 0x00001fff 72#define MMC_I_MASK_ALL 0x00001fff
73#else 73#else
74#define MMC_I_MASK_ALL 0x0000007f 74#define MMC_I_MASK_ALL 0x0000007f
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 3286d2a0a870..6a20a5491a96 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c
@@ -66,6 +66,7 @@
66#include <linux/dm9000.h> 66#include <linux/dm9000.h>
67#include <linux/delay.h> 67#include <linux/delay.h>
68#include <linux/platform_device.h> 68#include <linux/platform_device.h>
69#include <linux/irq.h>
69 70
70#include <asm/delay.h> 71#include <asm/delay.h>
71#include <asm/irq.h> 72#include <asm/irq.h>
@@ -113,7 +114,7 @@
113#define writesl outsl 114#define writesl outsl
114#define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQF_TRIGGER_HIGH) 115#define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQF_TRIGGER_HIGH)
115#else 116#else
116#define DM9000_IRQ_FLAGS IRQF_SHARED 117#define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQT_RISING)
117#endif 118#endif
118 119
119/* 120/*
diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c
index 7da7589d45dd..4020e9e955b3 100644
--- a/drivers/net/smc91x.c
+++ b/drivers/net/smc91x.c
@@ -1775,7 +1775,8 @@ static int __init smc_findirq(void __iomem *ioaddr)
1775 * o actually GRAB the irq. 1775 * o actually GRAB the irq.
1776 * o GRAB the region 1776 * o GRAB the region
1777 */ 1777 */
1778static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr) 1778static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
1779 unsigned long irq_flags)
1779{ 1780{
1780 struct smc_local *lp = netdev_priv(dev); 1781 struct smc_local *lp = netdev_priv(dev);
1781 static int version_printed = 0; 1782 static int version_printed = 0;
@@ -1941,7 +1942,7 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr)
1941 } 1942 }
1942 1943
1943 /* Grab the IRQ */ 1944 /* Grab the IRQ */
1944 retval = request_irq(dev->irq, &smc_interrupt, SMC_IRQ_FLAGS, dev->name, dev); 1945 retval = request_irq(dev->irq, &smc_interrupt, irq_flags, dev->name, dev);
1945 if (retval) 1946 if (retval)
1946 goto err_out; 1947 goto err_out;
1947 1948
@@ -2123,8 +2124,9 @@ static void smc_release_datacs(struct platform_device *pdev, struct net_device *
2123static int smc_drv_probe(struct platform_device *pdev) 2124static int smc_drv_probe(struct platform_device *pdev)
2124{ 2125{
2125 struct net_device *ndev; 2126 struct net_device *ndev;
2126 struct resource *res; 2127 struct resource *res, *ires;
2127 unsigned int __iomem *addr; 2128 unsigned int __iomem *addr;
2129 unsigned long irq_flags = SMC_IRQ_FLAGS;
2128 int ret; 2130 int ret;
2129 2131
2130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); 2132 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
@@ -2150,12 +2152,17 @@ static int smc_drv_probe(struct platform_device *pdev)
2150 SET_NETDEV_DEV(ndev, &pdev->dev); 2152 SET_NETDEV_DEV(ndev, &pdev->dev);
2151 2153
2152 ndev->dma = (unsigned char)-1; 2154 ndev->dma = (unsigned char)-1;
2153 ndev->irq = platform_get_irq(pdev, 0); 2155
2154 if (ndev->irq < 0) { 2156 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2157 if (!ires) {
2155 ret = -ENODEV; 2158 ret = -ENODEV;
2156 goto out_free_netdev; 2159 goto out_free_netdev;
2157 } 2160 }
2158 2161
2162 ndev->irq = ires->start;
2163 if (SMC_IRQ_FLAGS == -1)
2164 irq_flags = ires->flags & IRQF_TRIGGER_MASK;
2165
2159 ret = smc_request_attrib(pdev); 2166 ret = smc_request_attrib(pdev);
2160 if (ret) 2167 if (ret)
2161 goto out_free_netdev; 2168 goto out_free_netdev;
@@ -2181,7 +2188,7 @@ static int smc_drv_probe(struct platform_device *pdev)
2181#endif 2188#endif
2182 2189
2183 platform_set_drvdata(pdev, ndev); 2190 platform_set_drvdata(pdev, ndev);
2184 ret = smc_probe(ndev, addr); 2191 ret = smc_probe(ndev, addr, irq_flags);
2185 if (ret != 0) 2192 if (ret != 0)
2186 goto out_iounmap; 2193 goto out_iounmap;
2187 2194
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index 07b7f7120e37..271c28dc9baa 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -54,6 +54,7 @@
54#define SMC_outw(v, a, r) writew(v, (a) + (r)) 54#define SMC_outw(v, a, r) writew(v, (a) + (r))
55#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 55#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 56#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57#define SMC_IRQ_FLAGS (-1) /* from resource */
57 58
58#elif defined(CONFIG_BLACKFIN) 59#elif defined(CONFIG_BLACKFIN)
59 60
@@ -158,7 +159,7 @@
158#define SMC_outw(v, a, r) writew(v, (a) + (r)) 159#define SMC_outw(v, a, r) writew(v, (a) + (r))
159#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 160#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
160 161
161#define SMC_IRQ_FLAGS (0) 162#define SMC_IRQ_FLAGS (-1)
162 163
163#elif defined(CONFIG_SA1100_ASSABET) 164#elif defined(CONFIG_SA1100_ASSABET)
164 165
@@ -177,6 +178,7 @@
177#define SMC_outb(v, a, r) writeb(v, (a) + (r)) 178#define SMC_outb(v, a, r) writeb(v, (a) + (r))
178#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) 179#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
179#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) 180#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
181#define SMC_IRQ_FLAGS (-1) /* from resource */
180 182
181#elif defined(CONFIG_MACH_LOGICPD_PXA270) 183#elif defined(CONFIG_MACH_LOGICPD_PXA270)
182 184
@@ -194,7 +196,8 @@
194#elif defined(CONFIG_ARCH_INNOKOM) || \ 196#elif defined(CONFIG_ARCH_INNOKOM) || \
195 defined(CONFIG_MACH_MAINSTONE) || \ 197 defined(CONFIG_MACH_MAINSTONE) || \
196 defined(CONFIG_ARCH_PXA_IDP) || \ 198 defined(CONFIG_ARCH_PXA_IDP) || \
197 defined(CONFIG_ARCH_RAMSES) 199 defined(CONFIG_ARCH_RAMSES) || \
200 defined(CONFIG_ARCH_PCM027)
198 201
199#define SMC_CAN_USE_8BIT 1 202#define SMC_CAN_USE_8BIT 1
200#define SMC_CAN_USE_16BIT 1 203#define SMC_CAN_USE_16BIT 1
@@ -210,6 +213,7 @@
210#define SMC_outl(v, a, r) writel(v, (a) + (r)) 213#define SMC_outl(v, a, r) writel(v, (a) + (r))
211#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 214#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
212#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 215#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
216#define SMC_IRQ_FLAGS (-1) /* from resource */
213 217
214/* We actually can't write halfwords properly if not word aligned */ 218/* We actually can't write halfwords properly if not word aligned */
215static inline void 219static inline void
@@ -238,6 +242,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
238#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) 242#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
239#define SMC_outb(v, a, r) writeb(v, (a) + (r)) 243#define SMC_outb(v, a, r) writeb(v, (a) + (r))
240#define SMC_outw(v, a, r) writew(v, (a) + (r)) 244#define SMC_outw(v, a, r) writew(v, (a) + (r))
245#define SMC_IRQ_FLAGS (-1) /* from resource */
241 246
242#elif defined(CONFIG_ARCH_OMAP) 247#elif defined(CONFIG_ARCH_OMAP)
243 248
@@ -252,17 +257,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
252#define SMC_outw(v, a, r) writew(v, (a) + (r)) 257#define SMC_outw(v, a, r) writew(v, (a) + (r))
253#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 258#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
254#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 259#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
255 260#define SMC_IRQ_FLAGS (-1) /* from resource */
256#include <asm/mach-types.h>
257#include <asm/arch/cpu.h>
258
259#define SMC_IRQ_FLAGS (( \
260 machine_is_omap_h2() \
261 || machine_is_omap_h3() \
262 || machine_is_omap_h4() \
263 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
264 ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
265
266 261
267#elif defined(CONFIG_SH_SH4202_MICRODEV) 262#elif defined(CONFIG_SH_SH4202_MICRODEV)
268 263
@@ -453,8 +448,7 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
453#define SMC_outl(v, a, r) writel(v, (a) + (r)) 448#define SMC_outl(v, a, r) writel(v, (a) + (r))
454#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 449#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
455#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 450#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
456 451#define SMC_IRQ_FLAGS (-1) /* from resource */
457#define SMC_IRQ_FLAGS (0)
458 452
459#else 453#else
460 454
diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c
index 874923fcb2f9..e439044d88f2 100644
--- a/drivers/pcmcia/pxa2xx_base.c
+++ b/drivers/pcmcia/pxa2xx_base.c
@@ -29,6 +29,7 @@
29#include <asm/irq.h> 29#include <asm/irq.h>
30#include <asm/system.h> 30#include <asm/system.h>
31#include <asm/arch/pxa-regs.h> 31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/pxa2xx-regs.h>
32 33
33#include <pcmcia/cs_types.h> 34#include <pcmcia/cs_types.h>
34#include <pcmcia/ss.h> 35#include <pcmcia/ss.h>
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index 6f1e9a9804bc..2eb38520f0c8 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -337,6 +337,8 @@ static int sa1100_rtc_probe(struct platform_device *pdev)
337 if (IS_ERR(rtc)) 337 if (IS_ERR(rtc))
338 return PTR_ERR(rtc); 338 return PTR_ERR(rtc);
339 339
340 device_init_wakeup(&pdev->dev, 1);
341
340 platform_set_drvdata(pdev, rtc); 342 platform_set_drvdata(pdev, rtc);
341 343
342 return 0; 344 return 0;
@@ -352,9 +354,38 @@ static int sa1100_rtc_remove(struct platform_device *pdev)
352 return 0; 354 return 0;
353} 355}
354 356
357#ifdef CONFIG_PM
358static int sa1100_rtc_suspend(struct platform_device *pdev, pm_message_t state)
359{
360 if (pdev->dev.power.power_state.event != state.event) {
361 if (state.event == PM_EVENT_SUSPEND &&
362 device_may_wakeup(&pdev->dev))
363 enable_irq_wake(IRQ_RTCAlrm);
364
365 pdev->dev.power.power_state = state;
366 }
367 return 0;
368}
369
370static int sa1100_rtc_resume(struct platform_device *pdev)
371{
372 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
373 if (device_may_wakeup(&pdev->dev))
374 disable_irq_wake(IRQ_RTCAlrm);
375 pdev->dev.power.power_state = PMSG_ON;
376 }
377 return 0;
378}
379#else
380#define sa1100_rtc_suspend NULL
381#define sa1100_rtc_resume NULL
382#endif
383
355static struct platform_driver sa1100_rtc_driver = { 384static struct platform_driver sa1100_rtc_driver = {
356 .probe = sa1100_rtc_probe, 385 .probe = sa1100_rtc_probe,
357 .remove = sa1100_rtc_remove, 386 .remove = sa1100_rtc_remove,
387 .suspend = sa1100_rtc_suspend,
388 .resume = sa1100_rtc_resume,
358 .driver = { 389 .driver = {
359 .name = "sa1100-rtc", 390 .name = "sa1100-rtc",
360 }, 391 },
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index abf05048c638..aaaea81e412a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -153,6 +153,7 @@ config SPI_OMAP24XX
153config SPI_PXA2XX 153config SPI_PXA2XX
154 tristate "PXA2xx SSP SPI master" 154 tristate "PXA2xx SSP SPI master"
155 depends on SPI_MASTER && ARCH_PXA && EXPERIMENTAL 155 depends on SPI_MASTER && ARCH_PXA && EXPERIMENTAL
156 select PXA_SSP
156 help 157 help
157 This enables using a PXA2xx SSP port as a SPI master controller. 158 This enables using a PXA2xx SSP port as a SPI master controller.
158 The driver can be configured to use any SSP port and additional 159 The driver can be configured to use any SSP port and additional
diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c
index 1c2ab541d37d..eb817b8eb024 100644
--- a/drivers/spi/pxa2xx_spi.c
+++ b/drivers/spi/pxa2xx_spi.c
@@ -27,6 +27,7 @@
27#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
28#include <linux/workqueue.h> 28#include <linux/workqueue.h>
29#include <linux/delay.h> 29#include <linux/delay.h>
30#include <linux/clk.h>
30 31
31#include <asm/io.h> 32#include <asm/io.h>
32#include <asm/irq.h> 33#include <asm/irq.h>
@@ -36,6 +37,8 @@
36 37
37#include <asm/arch/hardware.h> 38#include <asm/arch/hardware.h>
38#include <asm/arch/pxa-regs.h> 39#include <asm/arch/pxa-regs.h>
40#include <asm/arch/regs-ssp.h>
41#include <asm/arch/ssp.h>
39#include <asm/arch/pxa2xx_spi.h> 42#include <asm/arch/pxa2xx_spi.h>
40 43
41MODULE_AUTHOR("Stephen Street"); 44MODULE_AUTHOR("Stephen Street");
@@ -80,6 +83,9 @@ struct driver_data {
80 /* Driver model hookup */ 83 /* Driver model hookup */
81 struct platform_device *pdev; 84 struct platform_device *pdev;
82 85
86 /* SSP Info */
87 struct ssp_device *ssp;
88
83 /* SPI framework hookup */ 89 /* SPI framework hookup */
84 enum pxa_ssp_type ssp_type; 90 enum pxa_ssp_type ssp_type;
85 struct spi_master *master; 91 struct spi_master *master;
@@ -778,6 +784,16 @@ int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi,
778 return retval; 784 return retval;
779} 785}
780 786
787static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
788{
789 unsigned long ssp_clk = clk_get_rate(ssp->clk);
790
791 if (ssp->type == PXA25x_SSP)
792 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
793 else
794 return ((ssp_clk / rate - 1) & 0xfff) << 8;
795}
796
781static void pump_transfers(unsigned long data) 797static void pump_transfers(unsigned long data)
782{ 798{
783 struct driver_data *drv_data = (struct driver_data *)data; 799 struct driver_data *drv_data = (struct driver_data *)data;
@@ -785,6 +801,7 @@ static void pump_transfers(unsigned long data)
785 struct spi_transfer *transfer = NULL; 801 struct spi_transfer *transfer = NULL;
786 struct spi_transfer *previous = NULL; 802 struct spi_transfer *previous = NULL;
787 struct chip_data *chip = NULL; 803 struct chip_data *chip = NULL;
804 struct ssp_device *ssp = drv_data->ssp;
788 void *reg = drv_data->ioaddr; 805 void *reg = drv_data->ioaddr;
789 u32 clk_div = 0; 806 u32 clk_div = 0;
790 u8 bits = 0; 807 u8 bits = 0;
@@ -866,12 +883,7 @@ static void pump_transfers(unsigned long data)
866 if (transfer->bits_per_word) 883 if (transfer->bits_per_word)
867 bits = transfer->bits_per_word; 884 bits = transfer->bits_per_word;
868 885
869 if (reg == SSP1_VIRT) 886 clk_div = ssp_get_clk_div(ssp, speed);
870 clk_div = SSP1_SerClkDiv(speed);
871 else if (reg == SSP2_VIRT)
872 clk_div = SSP2_SerClkDiv(speed);
873 else if (reg == SSP3_VIRT)
874 clk_div = SSP3_SerClkDiv(speed);
875 887
876 if (bits <= 8) { 888 if (bits <= 8) {
877 drv_data->n_bytes = 1; 889 drv_data->n_bytes = 1;
@@ -1074,6 +1086,7 @@ static int setup(struct spi_device *spi)
1074 struct pxa2xx_spi_chip *chip_info = NULL; 1086 struct pxa2xx_spi_chip *chip_info = NULL;
1075 struct chip_data *chip; 1087 struct chip_data *chip;
1076 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1088 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1089 struct ssp_device *ssp = drv_data->ssp;
1077 unsigned int clk_div; 1090 unsigned int clk_div;
1078 1091
1079 if (!spi->bits_per_word) 1092 if (!spi->bits_per_word)
@@ -1157,18 +1170,7 @@ static int setup(struct spi_device *spi)
1157 } 1170 }
1158 } 1171 }
1159 1172
1160 if (drv_data->ioaddr == SSP1_VIRT) 1173 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1161 clk_div = SSP1_SerClkDiv(spi->max_speed_hz);
1162 else if (drv_data->ioaddr == SSP2_VIRT)
1163 clk_div = SSP2_SerClkDiv(spi->max_speed_hz);
1164 else if (drv_data->ioaddr == SSP3_VIRT)
1165 clk_div = SSP3_SerClkDiv(spi->max_speed_hz);
1166 else
1167 {
1168 dev_err(&spi->dev, "failed setup: unknown IO address=0x%p\n",
1169 drv_data->ioaddr);
1170 return -ENODEV;
1171 }
1172 chip->speed_hz = spi->max_speed_hz; 1174 chip->speed_hz = spi->max_speed_hz;
1173 1175
1174 chip->cr0 = clk_div 1176 chip->cr0 = clk_div
@@ -1183,15 +1185,15 @@ static int setup(struct spi_device *spi)
1183 1185
1184 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1186 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1185 if (drv_data->ssp_type != PXA25x_SSP) 1187 if (drv_data->ssp_type != PXA25x_SSP)
1186 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n", 1188 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
1187 spi->bits_per_word, 1189 spi->bits_per_word,
1188 (CLOCK_SPEED_HZ) 1190 clk_get_rate(ssp->clk)
1189 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), 1191 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1190 spi->mode & 0x3); 1192 spi->mode & 0x3);
1191 else 1193 else
1192 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n", 1194 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
1193 spi->bits_per_word, 1195 spi->bits_per_word,
1194 (CLOCK_SPEED_HZ/2) 1196 clk_get_rate(ssp->clk)
1195 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), 1197 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1196 spi->mode & 0x3); 1198 spi->mode & 0x3);
1197 1199
@@ -1323,14 +1325,14 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1323 struct pxa2xx_spi_master *platform_info; 1325 struct pxa2xx_spi_master *platform_info;
1324 struct spi_master *master; 1326 struct spi_master *master;
1325 struct driver_data *drv_data = 0; 1327 struct driver_data *drv_data = 0;
1326 struct resource *memory_resource; 1328 struct ssp_device *ssp;
1327 int irq;
1328 int status = 0; 1329 int status = 0;
1329 1330
1330 platform_info = dev->platform_data; 1331 platform_info = dev->platform_data;
1331 1332
1332 if (platform_info->ssp_type == SSP_UNDEFINED) { 1333 ssp = ssp_request(pdev->id, pdev->name);
1333 dev_err(&pdev->dev, "undefined SSP\n"); 1334 if (ssp == NULL) {
1335 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1334 return -ENODEV; 1336 return -ENODEV;
1335 } 1337 }
1336 1338
@@ -1338,12 +1340,14 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1338 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 1340 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1339 if (!master) { 1341 if (!master) {
1340 dev_err(&pdev->dev, "can not alloc spi_master\n"); 1342 dev_err(&pdev->dev, "can not alloc spi_master\n");
1343 ssp_free(ssp);
1341 return -ENOMEM; 1344 return -ENOMEM;
1342 } 1345 }
1343 drv_data = spi_master_get_devdata(master); 1346 drv_data = spi_master_get_devdata(master);
1344 drv_data->master = master; 1347 drv_data->master = master;
1345 drv_data->master_info = platform_info; 1348 drv_data->master_info = platform_info;
1346 drv_data->pdev = pdev; 1349 drv_data->pdev = pdev;
1350 drv_data->ssp = ssp;
1347 1351
1348 master->bus_num = pdev->id; 1352 master->bus_num = pdev->id;
1349 master->num_chipselect = platform_info->num_chipselect; 1353 master->num_chipselect = platform_info->num_chipselect;
@@ -1351,21 +1355,13 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1351 master->setup = setup; 1355 master->setup = setup;
1352 master->transfer = transfer; 1356 master->transfer = transfer;
1353 1357
1354 drv_data->ssp_type = platform_info->ssp_type; 1358 drv_data->ssp_type = ssp->type;
1355 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data + 1359 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1356 sizeof(struct driver_data)), 8); 1360 sizeof(struct driver_data)), 8);
1357 1361
1358 /* Setup register addresses */ 1362 drv_data->ioaddr = ssp->mmio_base;
1359 memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1363 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1360 if (!memory_resource) { 1364 if (ssp->type == PXA25x_SSP) {
1361 dev_err(&pdev->dev, "memory resources not defined\n");
1362 status = -ENODEV;
1363 goto out_error_master_alloc;
1364 }
1365
1366 drv_data->ioaddr = (void *)io_p2v((unsigned long)(memory_resource->start));
1367 drv_data->ssdr_physical = memory_resource->start + 0x00000010;
1368 if (platform_info->ssp_type == PXA25x_SSP) {
1369 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1365 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1370 drv_data->dma_cr1 = 0; 1366 drv_data->dma_cr1 = 0;
1371 drv_data->clear_sr = SSSR_ROR; 1367 drv_data->clear_sr = SSSR_ROR;
@@ -1377,15 +1373,7 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1377 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1373 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1378 } 1374 }
1379 1375
1380 /* Attach to IRQ */ 1376 status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data);
1381 irq = platform_get_irq(pdev, 0);
1382 if (irq < 0) {
1383 dev_err(&pdev->dev, "irq resource not defined\n");
1384 status = -ENODEV;
1385 goto out_error_master_alloc;
1386 }
1387
1388 status = request_irq(irq, ssp_int, 0, dev->bus_id, drv_data);
1389 if (status < 0) { 1377 if (status < 0) {
1390 dev_err(&pdev->dev, "can not get IRQ\n"); 1378 dev_err(&pdev->dev, "can not get IRQ\n");
1391 goto out_error_master_alloc; 1379 goto out_error_master_alloc;
@@ -1418,29 +1406,12 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1418 goto out_error_dma_alloc; 1406 goto out_error_dma_alloc;
1419 } 1407 }
1420 1408
1421 if (drv_data->ioaddr == SSP1_VIRT) { 1409 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1422 DRCMRRXSSDR = DRCMR_MAPVLD 1410 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1423 | drv_data->rx_channel;
1424 DRCMRTXSSDR = DRCMR_MAPVLD
1425 | drv_data->tx_channel;
1426 } else if (drv_data->ioaddr == SSP2_VIRT) {
1427 DRCMRRXSS2DR = DRCMR_MAPVLD
1428 | drv_data->rx_channel;
1429 DRCMRTXSS2DR = DRCMR_MAPVLD
1430 | drv_data->tx_channel;
1431 } else if (drv_data->ioaddr == SSP3_VIRT) {
1432 DRCMRRXSS3DR = DRCMR_MAPVLD
1433 | drv_data->rx_channel;
1434 DRCMRTXSS3DR = DRCMR_MAPVLD
1435 | drv_data->tx_channel;
1436 } else {
1437 dev_err(dev, "bad SSP type\n");
1438 goto out_error_dma_alloc;
1439 }
1440 } 1411 }
1441 1412
1442 /* Enable SOC clock */ 1413 /* Enable SOC clock */
1443 pxa_set_cken(platform_info->clock_enable, 1); 1414 clk_enable(ssp->clk);
1444 1415
1445 /* Load default SSP configuration */ 1416 /* Load default SSP configuration */
1446 write_SSCR0(0, drv_data->ioaddr); 1417 write_SSCR0(0, drv_data->ioaddr);
@@ -1479,7 +1450,7 @@ out_error_queue_alloc:
1479 destroy_queue(drv_data); 1450 destroy_queue(drv_data);
1480 1451
1481out_error_clock_enabled: 1452out_error_clock_enabled:
1482 pxa_set_cken(platform_info->clock_enable, 0); 1453 clk_disable(ssp->clk);
1483 1454
1484out_error_dma_alloc: 1455out_error_dma_alloc:
1485 if (drv_data->tx_channel != -1) 1456 if (drv_data->tx_channel != -1)
@@ -1488,17 +1459,18 @@ out_error_dma_alloc:
1488 pxa_free_dma(drv_data->rx_channel); 1459 pxa_free_dma(drv_data->rx_channel);
1489 1460
1490out_error_irq_alloc: 1461out_error_irq_alloc:
1491 free_irq(irq, drv_data); 1462 free_irq(ssp->irq, drv_data);
1492 1463
1493out_error_master_alloc: 1464out_error_master_alloc:
1494 spi_master_put(master); 1465 spi_master_put(master);
1466 ssp_free(ssp);
1495 return status; 1467 return status;
1496} 1468}
1497 1469
1498static int pxa2xx_spi_remove(struct platform_device *pdev) 1470static int pxa2xx_spi_remove(struct platform_device *pdev)
1499{ 1471{
1500 struct driver_data *drv_data = platform_get_drvdata(pdev); 1472 struct driver_data *drv_data = platform_get_drvdata(pdev);
1501 int irq; 1473 struct ssp_device *ssp = drv_data->ssp;
1502 int status = 0; 1474 int status = 0;
1503 1475
1504 if (!drv_data) 1476 if (!drv_data)
@@ -1520,28 +1492,21 @@ static int pxa2xx_spi_remove(struct platform_device *pdev)
1520 1492
1521 /* Disable the SSP at the peripheral and SOC level */ 1493 /* Disable the SSP at the peripheral and SOC level */
1522 write_SSCR0(0, drv_data->ioaddr); 1494 write_SSCR0(0, drv_data->ioaddr);
1523 pxa_set_cken(drv_data->master_info->clock_enable, 0); 1495 clk_disable(ssp->clk);
1524 1496
1525 /* Release DMA */ 1497 /* Release DMA */
1526 if (drv_data->master_info->enable_dma) { 1498 if (drv_data->master_info->enable_dma) {
1527 if (drv_data->ioaddr == SSP1_VIRT) { 1499 DRCMR(ssp->drcmr_rx) = 0;
1528 DRCMRRXSSDR = 0; 1500 DRCMR(ssp->drcmr_tx) = 0;
1529 DRCMRTXSSDR = 0;
1530 } else if (drv_data->ioaddr == SSP2_VIRT) {
1531 DRCMRRXSS2DR = 0;
1532 DRCMRTXSS2DR = 0;
1533 } else if (drv_data->ioaddr == SSP3_VIRT) {
1534 DRCMRRXSS3DR = 0;
1535 DRCMRTXSS3DR = 0;
1536 }
1537 pxa_free_dma(drv_data->tx_channel); 1501 pxa_free_dma(drv_data->tx_channel);
1538 pxa_free_dma(drv_data->rx_channel); 1502 pxa_free_dma(drv_data->rx_channel);
1539 } 1503 }
1540 1504
1541 /* Release IRQ */ 1505 /* Release IRQ */
1542 irq = platform_get_irq(pdev, 0); 1506 free_irq(ssp->irq, drv_data);
1543 if (irq >= 0) 1507
1544 free_irq(irq, drv_data); 1508 /* Release SSP */
1509 ssp_free(ssp);
1545 1510
1546 /* Disconnect from the SPI framework */ 1511 /* Disconnect from the SPI framework */
1547 spi_unregister_master(drv_data->master); 1512 spi_unregister_master(drv_data->master);
@@ -1576,6 +1541,7 @@ static int suspend_devices(struct device *dev, void *pm_message)
1576static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) 1541static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1577{ 1542{
1578 struct driver_data *drv_data = platform_get_drvdata(pdev); 1543 struct driver_data *drv_data = platform_get_drvdata(pdev);
1544 struct ssp_device *ssp = drv_data->ssp;
1579 int status = 0; 1545 int status = 0;
1580 1546
1581 /* Check all childern for current power state */ 1547 /* Check all childern for current power state */
@@ -1588,7 +1554,7 @@ static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1588 if (status != 0) 1554 if (status != 0)
1589 return status; 1555 return status;
1590 write_SSCR0(0, drv_data->ioaddr); 1556 write_SSCR0(0, drv_data->ioaddr);
1591 pxa_set_cken(drv_data->master_info->clock_enable, 0); 1557 clk_disable(ssp->clk);
1592 1558
1593 return 0; 1559 return 0;
1594} 1560}
@@ -1596,10 +1562,11 @@ static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1596static int pxa2xx_spi_resume(struct platform_device *pdev) 1562static int pxa2xx_spi_resume(struct platform_device *pdev)
1597{ 1563{
1598 struct driver_data *drv_data = platform_get_drvdata(pdev); 1564 struct driver_data *drv_data = platform_get_drvdata(pdev);
1565 struct ssp_device *ssp = drv_data->ssp;
1599 int status = 0; 1566 int status = 0;
1600 1567
1601 /* Enable the SSP clock */ 1568 /* Enable the SSP clock */
1602 pxa_set_cken(drv_data->master_info->clock_enable, 1); 1569 clk_disable(ssp->clk);
1603 1570
1604 /* Start the queue running */ 1571 /* Start the queue running */
1605 status = start_queue(drv_data); 1572 status = start_queue(drv_data);
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 7580aa5da0f8..7a6499008b89 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -33,6 +33,7 @@ config USB_ARCH_HAS_OHCI
33 default y if ARCH_LH7A404 33 default y if ARCH_LH7A404
34 default y if ARCH_S3C2410 34 default y if ARCH_S3C2410
35 default y if PXA27x 35 default y if PXA27x
36 default y if PXA3xx
36 default y if ARCH_EP93XX 37 default y if ARCH_EP93XX
37 default y if ARCH_AT91 38 default y if ARCH_AT91
38 default y if ARCH_PNX4008 39 default y if ARCH_PNX4008
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index ecfe800fd720..ddd4ee1f2413 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -997,7 +997,7 @@ MODULE_LICENSE ("GPL");
997#define PLATFORM_DRIVER ohci_hcd_lh7a404_driver 997#define PLATFORM_DRIVER ohci_hcd_lh7a404_driver
998#endif 998#endif
999 999
1000#ifdef CONFIG_PXA27x 1000#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1001#include "ohci-pxa27x.c" 1001#include "ohci-pxa27x.c"
1002#define PLATFORM_DRIVER ohci_hcd_pxa27x_driver 1002#define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1003#endif 1003#endif
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index 23d2fe5a62f4..ff9a79843471 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -22,6 +22,7 @@
22#include <linux/device.h> 22#include <linux/device.h>
23#include <linux/signal.h> 23#include <linux/signal.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/clk.h>
25 26
26#include <asm/mach-types.h> 27#include <asm/mach-types.h>
27#include <asm/hardware.h> 28#include <asm/hardware.h>
@@ -32,6 +33,8 @@
32 33
33#define UHCRHPS(x) __REG2( 0x4C000050, (x)<<2 ) 34#define UHCRHPS(x) __REG2( 0x4C000050, (x)<<2 )
34 35
36static struct clk *usb_clk;
37
35/* 38/*
36 PMM_NPS_MODE -- PMM Non-power switching mode 39 PMM_NPS_MODE -- PMM Non-power switching mode
37 Ports are powered continuously. 40 Ports are powered continuously.
@@ -80,7 +83,7 @@ static int pxa27x_start_hc(struct device *dev)
80 83
81 inf = dev->platform_data; 84 inf = dev->platform_data;
82 85
83 pxa_set_cken(CKEN_USBHOST, 1); 86 clk_enable(usb_clk);
84 87
85 UHCHR |= UHCHR_FHR; 88 UHCHR |= UHCHR_FHR;
86 udelay(11); 89 udelay(11);
@@ -123,7 +126,7 @@ static void pxa27x_stop_hc(struct device *dev)
123 UHCCOMS |= 1; 126 UHCCOMS |= 1;
124 udelay(10); 127 udelay(10);
125 128
126 pxa_set_cken(CKEN_USBHOST, 0); 129 clk_disable(usb_clk);
127} 130}
128 131
129 132
@@ -158,6 +161,10 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
158 return -ENOMEM; 161 return -ENOMEM;
159 } 162 }
160 163
164 usb_clk = clk_get(&pdev->dev, "USBCLK");
165 if (IS_ERR(usb_clk))
166 return PTR_ERR(usb_clk);
167
161 hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x"); 168 hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
162 if (!hcd) 169 if (!hcd)
163 return -ENOMEM; 170 return -ENOMEM;
@@ -201,6 +208,7 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
201 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 208 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
202 err1: 209 err1:
203 usb_put_hcd(hcd); 210 usb_put_hcd(hcd);
211 clk_put(usb_clk);
204 return retval; 212 return retval;
205} 213}
206 214
@@ -225,6 +233,7 @@ void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
225 iounmap(hcd->regs); 233 iounmap(hcd->regs);
226 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 234 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
227 usb_put_hcd(hcd); 235 usb_put_hcd(hcd);
236 clk_put(usb_clk);
228} 237}
229 238
230/*-------------------------------------------------------------------------*/ 239/*-------------------------------------------------------------------------*/
diff --git a/include/asm-arm/arch-pxa/colibri.h b/include/asm-arm/arch-pxa/colibri.h
new file mode 100644
index 000000000000..2ae373fb5675
--- /dev/null
+++ b/include/asm-arm/arch-pxa/colibri.h
@@ -0,0 +1,19 @@
1#ifndef _COLIBRI_H_
2#define _COLIBRI_H_
3
4/* physical memory regions */
5#define COLIBRI_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
6#define COLIBRI_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
7#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */
8
9/* virtual memory regions */
10#define COLIBRI_DISK_VIRT 0xF0000000 /* Disk On Chip region */
11
12/* size of flash */
13#define COLIBRI_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
14
15/* Ethernet Controller Davicom DM9000 */
16#define GPIO_DM9000 114
17#define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
18
19#endif /* _COLIBRI_H_ */
diff --git a/include/asm-arm/arch-pxa/corgi.h b/include/asm-arm/arch-pxa/corgi.h
index e554caa0d18b..bf856503baf6 100644
--- a/include/asm-arm/arch-pxa/corgi.h
+++ b/include/asm-arm/arch-pxa/corgi.h
@@ -104,7 +104,6 @@
104 */ 104 */
105extern struct platform_device corgiscoop_device; 105extern struct platform_device corgiscoop_device;
106extern struct platform_device corgissp_device; 106extern struct platform_device corgissp_device;
107extern struct platform_device corgifb_device;
108 107
109#endif /* __ASM_ARCH_CORGI_H */ 108#endif /* __ASM_ARCH_CORGI_H */
110 109
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index b76ee6d1f5b4..c562b972a4a6 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -180,7 +180,8 @@
180#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) 180#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
181#elif defined(CONFIG_ARCH_LUBBOCK) || \ 181#elif defined(CONFIG_ARCH_LUBBOCK) || \
182 defined(CONFIG_MACH_LOGICPD_PXA270) || \ 182 defined(CONFIG_MACH_LOGICPD_PXA270) || \
183 defined(CONFIG_MACH_MAINSTONE) 183 defined(CONFIG_MACH_MAINSTONE) || \
184 defined(CONFIG_MACH_PCM027)
184#define NR_IRQS (IRQ_BOARD_END) 185#define NR_IRQS (IRQ_BOARD_END)
185#else 186#else
186#define NR_IRQS (IRQ_BOARD_START) 187#define NR_IRQS (IRQ_BOARD_START)
@@ -227,6 +228,13 @@
227#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) 228#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
228#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) 229#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
229 230
231/* phyCORE-PXA270 (PCM027) Interrupts */
232#define PCM027_IRQ(x) (IRQ_BOARD_START + (x))
233#define PCM027_BTDET_IRQ PCM027_IRQ(0)
234#define PCM027_FF_RI_IRQ PCM027_IRQ(1)
235#define PCM027_MMCDET_IRQ PCM027_IRQ(2)
236#define PCM027_PM_5V_IRQ PCM027_IRQ(3)
237
230/* ITE8152 irqs */ 238/* ITE8152 irqs */
231/* add IT8152 IRQs beyond BOARD_END */ 239/* add IT8152 IRQs beyond BOARD_END */
232#ifdef CONFIG_PCI_HOST_ITE8152 240#ifdef CONFIG_PCI_HOST_ITE8152
diff --git a/include/asm-arm/arch-pxa/littleton.h b/include/asm-arm/arch-pxa/littleton.h
new file mode 100644
index 000000000000..79d209b826f4
--- /dev/null
+++ b/include/asm-arm/arch-pxa/littleton.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_ARCH_ZYLONITE_H
2#define __ASM_ARCH_ZYLONITE_H
3
4#define LITTLETON_ETH_PHYS 0x30000000
5
6#endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/include/asm-arm/arch-pxa/magician.h b/include/asm-arm/arch-pxa/magician.h
new file mode 100644
index 000000000000..337f51f06b3a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/magician.h
@@ -0,0 +1,111 @@
1/*
2 * GPIO and IRQ definitions for HTC Magician PDA phones
3 *
4 * Copyright (c) 2007 Philipp Zabel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef _MAGICIAN_H_
13#define _MAGICIAN_H_
14
15#include <asm/arch/pxa-regs.h>
16
17/*
18 * PXA GPIOs
19 */
20
21#define GPIO0_MAGICIAN_KEY_POWER 0
22#define GPIO9_MAGICIAN_UNKNOWN 9
23#define GPIO10_MAGICIAN_GSM_IRQ 10
24#define GPIO11_MAGICIAN_GSM_OUT1 11
25#define GPIO13_MAGICIAN_CPLD_IRQ 13
26#define GPIO18_MAGICIAN_UNKNOWN 18
27#define GPIO22_MAGICIAN_VIBRA_EN 22
28#define GPIO26_MAGICIAN_GSM_POWER 26
29#define GPIO27_MAGICIAN_USBC_PUEN 27
30#define GPIO30_MAGICIAN_nCHARGE_EN 30
31#define GPIO37_MAGICIAN_KEY_HANGUP 37
32#define GPIO38_MAGICIAN_KEY_CONTACTS 38
33#define GPIO40_MAGICIAN_GSM_OUT2 40
34#define GPIO48_MAGICIAN_UNKNOWN 48
35#define GPIO56_MAGICIAN_UNKNOWN 56
36#define GPIO57_MAGICIAN_CAM_RESET 57
37#define GPIO83_MAGICIAN_nIR_EN 83
38#define GPIO86_MAGICIAN_GSM_RESET 86
39#define GPIO87_MAGICIAN_GSM_SELECT 87
40#define GPIO90_MAGICIAN_KEY_CALENDAR 90
41#define GPIO91_MAGICIAN_KEY_CAMERA 91
42#define GPIO93_MAGICIAN_KEY_UP 93
43#define GPIO94_MAGICIAN_KEY_DOWN 94
44#define GPIO95_MAGICIAN_KEY_LEFT 95
45#define GPIO96_MAGICIAN_KEY_RIGHT 96
46#define GPIO97_MAGICIAN_KEY_ENTER 97
47#define GPIO98_MAGICIAN_KEY_RECORD 98
48#define GPIO99_MAGICIAN_HEADPHONE_IN 99
49#define GPIO100_MAGICIAN_KEY_VOL_UP 100
50#define GPIO101_MAGICIAN_KEY_VOL_DOWN 101
51#define GPIO102_MAGICIAN_KEY_PHONE 102
52#define GPIO103_MAGICIAN_LED_KP 103
53#define GPIO104_MAGICIAN_LCD_POWER_1 104
54#define GPIO105_MAGICIAN_LCD_POWER_2 105
55#define GPIO106_MAGICIAN_LCD_POWER_3 106
56#define GPIO107_MAGICIAN_DS1WM_IRQ 107
57#define GPIO108_MAGICIAN_GSM_READY 108
58#define GPIO114_MAGICIAN_UNKNOWN 114
59#define GPIO115_MAGICIAN_nPEN_IRQ 115
60#define GPIO116_MAGICIAN_nCAM_EN 116
61#define GPIO119_MAGICIAN_UNKNOWN 119
62#define GPIO120_MAGICIAN_UNKNOWN 120
63
64/*
65 * PXA GPIO alternate function mode & direction
66 */
67
68#define GPIO0_MAGICIAN_KEY_POWER_MD (0 | GPIO_IN)
69#define GPIO9_MAGICIAN_UNKNOWN_MD (9 | GPIO_IN)
70#define GPIO10_MAGICIAN_GSM_IRQ_MD (10 | GPIO_IN)
71#define GPIO11_MAGICIAN_GSM_OUT1_MD (11 | GPIO_OUT)
72#define GPIO13_MAGICIAN_CPLD_IRQ_MD (13 | GPIO_IN)
73#define GPIO18_MAGICIAN_UNKNOWN_MD (18 | GPIO_OUT)
74#define GPIO22_MAGICIAN_VIBRA_EN_MD (22 | GPIO_OUT)
75#define GPIO26_MAGICIAN_GSM_POWER_MD (26 | GPIO_OUT)
76#define GPIO27_MAGICIAN_USBC_PUEN_MD (27 | GPIO_OUT)
77#define GPIO30_MAGICIAN_nCHARGE_EN_MD (30 | GPIO_OUT)
78#define GPIO37_MAGICIAN_KEY_HANGUP_MD (37 | GPIO_OUT)
79#define GPIO38_MAGICIAN_KEY_CONTACTS_MD (38 | GPIO_OUT)
80#define GPIO40_MAGICIAN_GSM_OUT2_MD (40 | GPIO_OUT)
81#define GPIO48_MAGICIAN_UNKNOWN_MD (48 | GPIO_OUT)
82#define GPIO56_MAGICIAN_UNKNOWN_MD (56 | GPIO_OUT)
83#define GPIO57_MAGICIAN_CAM_RESET_MD (57 | GPIO_OUT)
84#define GPIO83_MAGICIAN_nIR_EN_MD (83 | GPIO_OUT)
85#define GPIO86_MAGICIAN_GSM_RESET_MD (86 | GPIO_OUT)
86#define GPIO87_MAGICIAN_GSM_SELECT_MD (87 | GPIO_OUT)
87#define GPIO90_MAGICIAN_KEY_CALENDAR_MD (90 | GPIO_OUT)
88#define GPIO91_MAGICIAN_KEY_CAMERA_MD (91 | GPIO_OUT)
89#define GPIO93_MAGICIAN_KEY_UP_MD (93 | GPIO_IN)
90#define GPIO94_MAGICIAN_KEY_DOWN_MD (94 | GPIO_IN)
91#define GPIO95_MAGICIAN_KEY_LEFT_MD (95 | GPIO_IN)
92#define GPIO96_MAGICIAN_KEY_RIGHT_MD (96 | GPIO_IN)
93#define GPIO97_MAGICIAN_KEY_ENTER_MD (97 | GPIO_IN)
94#define GPIO98_MAGICIAN_KEY_RECORD_MD (98 | GPIO_IN)
95#define GPIO99_MAGICIAN_HEADPHONE_IN_MD (99 | GPIO_IN)
96#define GPIO100_MAGICIAN_KEY_VOL_UP_MD (100 | GPIO_IN)
97#define GPIO101_MAGICIAN_KEY_VOL_DOWN_MD (101 | GPIO_IN)
98#define GPIO102_MAGICIAN_KEY_PHONE_MD (102 | GPIO_IN)
99#define GPIO103_MAGICIAN_LED_KP_MD (103 | GPIO_OUT)
100#define GPIO104_MAGICIAN_LCD_POWER_1_MD (104 | GPIO_OUT)
101#define GPIO105_MAGICIAN_LCD_POWER_2_MD (105 | GPIO_OUT)
102#define GPIO106_MAGICIAN_LCD_POWER_3_MD (106 | GPIO_OUT)
103#define GPIO107_MAGICIAN_DS1WM_IRQ_MD (107 | GPIO_IN)
104#define GPIO108_MAGICIAN_GSM_READY_MD (108 | GPIO_IN)
105#define GPIO114_MAGICIAN_UNKNOWN_MD (114 | GPIO_OUT)
106#define GPIO115_MAGICIAN_nPEN_IRQ_MD (115 | GPIO_IN)
107#define GPIO116_MAGICIAN_nCAM_EN_MD (116 | GPIO_OUT)
108#define GPIO119_MAGICIAN_UNKNOWN_MD (119 | GPIO_OUT)
109#define GPIO120_MAGICIAN_UNKNOWN_MD (120 | GPIO_OUT)
110
111#endif /* _MAGICIAN_H_ */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h
index a20996649889..bb410313556f 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa300.h
+++ b/include/asm-arm/arch-pxa/mfp-pxa300.h
@@ -16,6 +16,7 @@
16#define __ASM_ARCH_MFP_PXA300_H 16#define __ASM_ARCH_MFP_PXA300_H
17 17
18#include <asm/arch/mfp.h> 18#include <asm/arch/mfp.h>
19#include <asm/arch/mfp-pxa3xx.h>
19 20
20/* GPIO */ 21/* GPIO */
21#define GPIO46_GPIO MFP_CFG(GPIO46, AF1) 22#define GPIO46_GPIO MFP_CFG(GPIO46, AF1)
diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h
index 52deedcaf3bd..576aa46d90fc 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa320.h
+++ b/include/asm-arm/arch-pxa/mfp-pxa320.h
@@ -16,6 +16,7 @@
16#define __ASM_ARCH_MFP_PXA320_H 16#define __ASM_ARCH_MFP_PXA320_H
17 17
18#include <asm/arch/mfp.h> 18#include <asm/arch/mfp.h>
19#include <asm/arch/mfp-pxa3xx.h>
19 20
20/* GPIO */ 21/* GPIO */
21#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) 22#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
diff --git a/include/asm-arm/arch-pxa/mfp-pxa3xx.h b/include/asm-arm/arch-pxa/mfp-pxa3xx.h
new file mode 100644
index 000000000000..1f6b35c015d0
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa3xx.h
@@ -0,0 +1,252 @@
1#ifndef __ASM_ARCH_MFP_PXA3XX_H
2#define __ASM_ARCH_MFP_PXA3XX_H
3
4#define MFPR_BASE (0x40e10000)
5#define MFPR_SIZE (PAGE_SIZE)
6
7/* MFPR register bit definitions */
8#define MFPR_PULL_SEL (0x1 << 15)
9#define MFPR_PULLUP_EN (0x1 << 14)
10#define MFPR_PULLDOWN_EN (0x1 << 13)
11#define MFPR_SLEEP_SEL (0x1 << 9)
12#define MFPR_SLEEP_OE_N (0x1 << 7)
13#define MFPR_EDGE_CLEAR (0x1 << 6)
14#define MFPR_EDGE_FALL_EN (0x1 << 5)
15#define MFPR_EDGE_RISE_EN (0x1 << 4)
16
17#define MFPR_SLEEP_DATA(x) ((x) << 8)
18#define MFPR_DRIVE(x) (((x) & 0x7) << 10)
19#define MFPR_AF_SEL(x) (((x) & 0x7) << 0)
20
21#define MFPR_EDGE_NONE (0)
22#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN)
23#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN)
24#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
25
26/*
27 * Table that determines the low power modes outputs, with actual settings
28 * used in parentheses for don't-care values. Except for the float output,
29 * the configured driven and pulled levels match, so if there is a need for
30 * non-LPM pulled output, the same configuration could probably be used.
31 *
32 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
33 * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
34 *
35 * Input 0 X(0) X(0) X(0) 0
36 * Drive 0 0 0 0 X(1) 0
37 * Drive 1 0 1 X(1) 0 0
38 * Pull hi (1) 1 X(1) 1 0 0
39 * Pull lo (0) 1 X(0) 0 1 0
40 * Z (float) 1 X(0) 0 0 0
41 */
42#define MFPR_LPM_INPUT (0)
43#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
44#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
45#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N)
46#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
47#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N)
48#define MFPR_LPM_MASK (0xe080)
49
50/*
51 * The pullup and pulldown state of the MFP pin at run mode is by default
52 * determined by the selected alternate function. In case that some buggy
53 * devices need to override this default behavior, the definitions below
54 * indicates the setting of corresponding MFPR bits
55 *
56 * Definition pull_sel pullup_en pulldown_en
57 * MFPR_PULL_NONE 0 0 0
58 * MFPR_PULL_LOW 1 0 1
59 * MFPR_PULL_HIGH 1 1 0
60 * MFPR_PULL_BOTH 1 1 1
61 */
62#define MFPR_PULL_NONE (0)
63#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
64#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN)
65#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN)
66
67/* PXA3xx common MFP configurations - processor specific ones defined
68 * in mfp-pxa300.h and mfp-pxa320.h
69 */
70#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
71#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
72#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
73#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
74#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
75#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
76#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
77#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
78#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
79#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
80#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
81#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
82#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
83#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
84#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
85#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
86#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
87#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
88#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
89#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
90#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
91#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
92#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
93#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
94#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
95#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
96#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
97#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
98#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
99#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
100#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
101#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
102#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
103#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
104#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
105#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
106#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
107#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
108#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
109#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
110#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
111#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
112#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
113#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
114#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
115#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
116
117#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
118#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
119
120#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
121#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
122#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
123
124#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
125
126#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
127#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
128#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
129#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
130#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
131#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
132#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
133#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
134#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
135#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
136#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
137#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
138#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
139#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
140#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
141#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
142#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
143#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
144#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
145#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
146#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
147#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
148#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
149#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
150#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
151#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
152#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
153#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
154#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
155#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
156#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
157#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
158#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
159#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
160#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
161#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
162#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
163#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
164#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
165#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
166#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
167#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
168#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
169#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
170#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
171#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
172#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
173#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
174#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
175#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
176#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
177#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
178#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
179#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
180#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
181#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
182#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
183#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
184#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
185#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
186#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
187#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
188#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
189#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
190#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
191
192#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
193#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
194#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
195#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
196#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
197#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
198#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
199
200/*
201 * each MFP pin will have a MFPR register, since the offset of the
202 * register varies between processors, the processor specific code
203 * should initialize the pin offsets by pxa3xx_mfp_init_addr()
204 *
205 * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
206 * structure, which represents a range of MFP pins from "start" to
207 * "end", with the offset begining at "offset", to define a single
208 * pin, let "end" = -1
209 *
210 * use
211 *
212 * MFP_ADDR_X() to define a range of pins
213 * MFP_ADDR() to define a single pin
214 * MFP_ADDR_END to signal the end of pin offset definitions
215 */
216struct pxa3xx_mfp_addr_map {
217 unsigned int start;
218 unsigned int end;
219 unsigned long offset;
220};
221
222#define MFP_ADDR_X(start, end, offset) \
223 { MFP_PIN_##start, MFP_PIN_##end, offset }
224
225#define MFP_ADDR(pin, offset) \
226 { MFP_PIN_##pin, -1, offset }
227
228#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
229
230/*
231 * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
232 * to the MFPR register
233 */
234unsigned long pxa3xx_mfp_read(int mfp);
235void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
236
237/*
238 * pxa3xx_mfp_config - configure the MFPR registers
239 *
240 * used by board specific initialization code
241 */
242void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num);
243
244/*
245 * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
246 * index and MFPR register offset
247 *
248 * used by processor specific code
249 */
250void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
251void __init pxa3xx_init_mfp(void);
252#endif /* __ASM_ARCH_MFP_PXA3XX_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
index 03c508d94f0e..02f6157396d3 100644
--- a/include/asm-arm/arch-pxa/mfp.h
+++ b/include/asm-arm/arch-pxa/mfp.h
@@ -16,9 +16,6 @@
16#ifndef __ASM_ARCH_MFP_H 16#ifndef __ASM_ARCH_MFP_H
17#define __ASM_ARCH_MFP_H 17#define __ASM_ARCH_MFP_H
18 18
19#define MFPR_BASE (0x40e10000)
20#define MFPR_SIZE (PAGE_SIZE)
21
22#define mfp_to_gpio(m) ((m) % 128) 19#define mfp_to_gpio(m) ((m) % 128)
23 20
24/* list of all the configurable MFP pins */ 21/* list of all the configurable MFP pins */
@@ -217,114 +214,21 @@ enum {
217}; 214};
218 215
219/* 216/*
220 * Table that determines the low power modes outputs, with actual settings
221 * used in parentheses for don't-care values. Except for the float output,
222 * the configured driven and pulled levels match, so if there is a need for
223 * non-LPM pulled output, the same configuration could probably be used.
224 *
225 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
226 * (bit 7) (bit 8) (bit 14d) (bit 13d)
227 *
228 * Drive 0 0 0 0 X (1) 0
229 * Drive 1 0 1 X (1) 0 0
230 * Pull hi (1) 1 X(1) 1 0 0
231 * Pull lo (0) 1 X(0) 0 1 0
232 * Z (float) 1 X(0) 0 0 0
233 */
234#define MFP_LPM_DRIVE_LOW 0x8
235#define MFP_LPM_DRIVE_HIGH 0x6
236#define MFP_LPM_PULL_HIGH 0x7
237#define MFP_LPM_PULL_LOW 0x9
238#define MFP_LPM_FLOAT 0x1
239#define MFP_LPM_PULL_NEITHER 0x0
240
241/*
242 * The pullup and pulldown state of the MFP pin is by default determined by
243 * selected alternate function. In case some buggy devices need to override
244 * this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of
245 * the following definition as the parameter.
246 *
247 * Definition pull_sel pullup_en pulldown_en
248 * MFP_PULL_HIGH 1 1 0
249 * MFP_PULL_LOW 1 0 1
250 * MFP_PULL_BOTH 1 1 1
251 * MFP_PULL_NONE 1 0 0
252 * MFP_PULL_DEFAULT 0 X X
253 *
254 * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN
255 * bits, which will cause potential conflicts with the low power mode
256 * setting, device drivers should take care of this
257 */
258#define MFP_PULL_BOTH (0x7u)
259#define MFP_PULL_HIGH (0x6u)
260#define MFP_PULL_LOW (0x5u)
261#define MFP_PULL_NONE (0x4u)
262#define MFP_PULL_DEFAULT (0x0u)
263
264#define MFP_AF0 (0)
265#define MFP_AF1 (1)
266#define MFP_AF2 (2)
267#define MFP_AF3 (3)
268#define MFP_AF4 (4)
269#define MFP_AF5 (5)
270#define MFP_AF6 (6)
271#define MFP_AF7 (7)
272
273#define MFP_DS01X (0)
274#define MFP_DS02X (1)
275#define MFP_DS03X (2)
276#define MFP_DS04X (3)
277#define MFP_DS06X (4)
278#define MFP_DS08X (5)
279#define MFP_DS10X (6)
280#define MFP_DS12X (7)
281
282#define MFP_EDGE_BOTH 0x3
283#define MFP_EDGE_RISE 0x2
284#define MFP_EDGE_FALL 0x1
285#define MFP_EDGE_NONE 0x0
286
287#define MFPR_AF_MASK 0x0007
288#define MFPR_DRV_MASK 0x1c00
289#define MFPR_RDH_MASK 0x0200
290#define MFPR_LPM_MASK 0xe180
291#define MFPR_PULL_MASK 0xe000
292#define MFPR_EDGE_MASK 0x0070
293
294#define MFPR_ALT_OFFSET 0
295#define MFPR_ERE_OFFSET 4
296#define MFPR_EFE_OFFSET 5
297#define MFPR_EC_OFFSET 6
298#define MFPR_SON_OFFSET 7
299#define MFPR_SD_OFFSET 8
300#define MFPR_SS_OFFSET 9
301#define MFPR_DRV_OFFSET 10
302#define MFPR_PD_OFFSET 13
303#define MFPR_PU_OFFSET 14
304#define MFPR_PS_OFFSET 15
305
306#define MFPR(af, drv, rdh, lpm, edge) \
307 (((af) & 0x7) | (((drv) & 0x7) << 10) |\
308 (((rdh) & 0x1) << 9) |\
309 (((lpm) & 0x3) << 7) |\
310 (((lpm) & 0x4) << 12)|\
311 (((lpm) & 0x8) << 10)|\
312 ((!(edge)) << 6) |\
313 (((edge) & 0x1) << 5) |\
314 (((edge) & 0x2) << 3))
315
316/*
317 * a possible MFP configuration is represented by a 32-bit integer 217 * a possible MFP configuration is represented by a 32-bit integer
318 * bit 0..15 - MFPR value (16-bit) 218 *
319 * bit 16..31 - mfp pin index (used to obtain the MFPR offset) 219 * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
220 * bit 10..12 - Alternate Function Selection
221 * bit 13..15 - Drive Strength
222 * bit 16..18 - Low Power Mode State
223 * bit 19..20 - Low Power Mode Edge Detection
224 * bit 21..22 - Run Mode Pull State
320 * 225 *
321 * to facilitate the definition, the following macros are provided 226 * to facilitate the definition, the following macros are provided
322 * 227 *
323 * MFPR_DEFAULT - default MFPR value, with 228 * MFP_CFG_DEFAULT - default MFP configuration value, with
324 * alternate function = 0, 229 * alternate function = 0,
325 * drive strength = fast 1mA (MFP_DS01X) 230 * drive strength = fast 3mA (MFP_DS03X)
326 * low power mode = default 231 * low power mode = default
327 * release dalay hold = false (RDH bit)
328 * edge detection = none 232 * edge detection = none
329 * 233 *
330 * MFP_CFG - default MFPR value with alternate function 234 * MFP_CFG - default MFPR value with alternate function
@@ -334,251 +238,74 @@ enum {
334 * low power mode 238 * low power mode
335 * MFP_CFG_X - default MFPR value with alternate function, 239 * MFP_CFG_X - default MFPR value with alternate function,
336 * pin drive strength and low power mode 240 * pin drive strength and low power mode
337 *
338 * use
339 *
340 * MFP_CFG_PIN - to get the MFP pin index
341 * MFP_CFG_VAL - to get the corresponding MFPR value
342 */ 241 */
343 242
344typedef uint32_t mfp_cfg_t; 243typedef unsigned long mfp_cfg_t;
345 244
346#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff) 245#define MFP_PIN(x) ((x) & 0x3ff)
347#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff) 246
348 247#define MFP_AF0 (0x0 << 10)
349/* 248#define MFP_AF1 (0x1 << 10)
350 * MFP register defaults to 249#define MFP_AF2 (0x2 << 10)
351 * drive strength fast 3mA (010'b) 250#define MFP_AF3 (0x3 << 10)
352 * edge detection logic disabled 251#define MFP_AF4 (0x4 << 10)
353 * alternate function 0 252#define MFP_AF5 (0x5 << 10)
354 */ 253#define MFP_AF6 (0x6 << 10)
355#define MFPR_DEFAULT (0x0840) 254#define MFP_AF7 (0x7 << 10)
255#define MFP_AF_MASK (0x7 << 10)
256#define MFP_AF(x) (((x) >> 10) & 0x7)
257
258#define MFP_DS01X (0x0 << 13)
259#define MFP_DS02X (0x1 << 13)
260#define MFP_DS03X (0x2 << 13)
261#define MFP_DS04X (0x3 << 13)
262#define MFP_DS06X (0x4 << 13)
263#define MFP_DS08X (0x5 << 13)
264#define MFP_DS10X (0x6 << 13)
265#define MFP_DS13X (0x7 << 13)
266#define MFP_DS_MASK (0x7 << 13)
267#define MFP_DS(x) (((x) >> 13) & 0x7)
268
269#define MFP_LPM_INPUT (0x0 << 16)
270#define MFP_LPM_DRIVE_LOW (0x1 << 16)
271#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
272#define MFP_LPM_PULL_LOW (0x3 << 16)
273#define MFP_LPM_PULL_HIGH (0x4 << 16)
274#define MFP_LPM_FLOAT (0x5 << 16)
275#define MFP_LPM_STATE_MASK (0x7 << 16)
276#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
277
278#define MFP_LPM_EDGE_NONE (0x0 << 19)
279#define MFP_LPM_EDGE_RISE (0x1 << 19)
280#define MFP_LPM_EDGE_FALL (0x2 << 19)
281#define MFP_LPM_EDGE_BOTH (0x3 << 19)
282#define MFP_LPM_EDGE_MASK (0x3 << 19)
283#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3)
284
285#define MFP_PULL_NONE (0x0 << 21)
286#define MFP_PULL_LOW (0x1 << 21)
287#define MFP_PULL_HIGH (0x2 << 21)
288#define MFP_PULL_BOTH (0x3 << 21)
289#define MFP_PULL_MASK (0x3 << 21)
290#define MFP_PULL(x) (((x) >> 21) & 0x3)
291
292#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
293 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
356 294
357#define MFP_CFG(pin, af) \ 295#define MFP_CFG(pin, af) \
358 ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af)) 296 ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
297 (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
359 298
360#define MFP_CFG_DRV(pin, af, drv) \ 299#define MFP_CFG_DRV(pin, af, drv) \
361 ((MFP_PIN_##pin << 16) | (MFPR_DEFAULT & ~MFPR_DRV_MASK) |\ 300 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
362 ((MFP_##drv) << 10) | (MFP_##af)) 301 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
363 302
364#define MFP_CFG_LPM(pin, af, lpm) \ 303#define MFP_CFG_LPM(pin, af, lpm) \
365 ((MFP_PIN_##pin << 16) | (MFPR_DEFAULT & ~MFPR_LPM_MASK) |\ 304 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
366 (((MFP_LPM_##lpm) & 0x3) << 7) |\ 305 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
367 (((MFP_LPM_##lpm) & 0x4) << 12) |\
368 (((MFP_LPM_##lpm) & 0x8) << 10) |\
369 (MFP_##af))
370 306
371#define MFP_CFG_X(pin, af, drv, lpm) \ 307#define MFP_CFG_X(pin, af, drv, lpm) \
372 ((MFP_PIN_##pin << 16) |\ 308 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
373 (MFPR_DEFAULT & ~(MFPR_DRV_MASK | MFPR_LPM_MASK)) |\ 309 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
374 ((MFP_##drv) << 10) | (MFP_##af) |\
375 (((MFP_LPM_##lpm) & 0x3) << 7) |\
376 (((MFP_LPM_##lpm) & 0x4) << 12) |\
377 (((MFP_LPM_##lpm) & 0x8) << 10))
378
379/* common MFP configurations - processor specific ones defined
380 * in mfp-pxa3xx.h
381 */
382#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
383#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
384#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
385#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
386#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
387#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
388#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
389#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
390#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
391#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
392#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
393#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
394#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
395#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
396#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
397#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
398#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
399#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
400#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
401#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
402#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
403#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
404#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
405#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
406#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
407#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
408#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
409#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
410#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
411#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
412#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
413#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
414#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
415#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
416#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
417#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
418#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
419#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
420#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
421#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
422#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
423#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
424#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
425#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
426#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
427#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
428
429#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
430#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
431
432#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
433#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
434#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
435
436#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
437
438#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
439#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
440#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
441#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
442#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
443#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
444#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
445#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
446#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
447#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
448#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
449#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
450#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
451#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
452#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
453#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
454#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
455#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
456#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
457#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
458#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
459#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
460#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
461#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
462#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
463#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
464#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
465#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
466#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
467#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
468#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
469#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
470#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
471#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
472#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
473#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
474#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
475#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
476#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
477#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
478#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
479#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
480#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
481#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
482#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
483#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
484#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
485#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
486#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
487#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
488#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
489#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
490#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
491#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
492#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
493#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
494#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
495#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
496#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
497#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
498#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
499#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
500#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
501#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
502#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
503
504#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
505#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
506#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
507#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
508#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
509#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
510#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
511
512/*
513 * each MFP pin will have a MFPR register, since the offset of the
514 * register varies between processors, the processor specific code
515 * should initialize the pin offsets by pxa3xx_mfp_init_addr()
516 *
517 * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
518 * structure, which represents a range of MFP pins from "start" to
519 * "end", with the offset begining at "offset", to define a single
520 * pin, let "end" = -1
521 *
522 * use
523 *
524 * MFP_ADDR_X() to define a range of pins
525 * MFP_ADDR() to define a single pin
526 * MFP_ADDR_END to signal the end of pin offset definitions
527 */
528struct pxa3xx_mfp_addr_map {
529 unsigned int start;
530 unsigned int end;
531 unsigned long offset;
532};
533
534#define MFP_ADDR_X(start, end, offset) \
535 { MFP_PIN_##start, MFP_PIN_##end, offset }
536
537#define MFP_ADDR(pin, offset) \
538 { MFP_PIN_##pin, -1, offset }
539
540#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
541
542struct pxa3xx_mfp_pin {
543 unsigned long mfpr_off; /* MFPRxx register offset */
544 unsigned long mfpr_val; /* MFPRxx register value */
545};
546
547/*
548 * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
549 * to the MFPR register
550 */
551unsigned long pxa3xx_mfp_read(int mfp);
552void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
553
554/*
555 * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength
556 * pxa3xx_mfp_set_rdh - set MFP release delay hold on/off
557 * pxa3xx_mfp_set_lpm - set MFP low power mode state
558 * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode
559 *
560 * use these functions to override/change the default configuration
561 * done by pxa3xx_mfp_set_config(s)
562 */
563void pxa3xx_mfp_set_afds(int mfp, int af, int ds);
564void pxa3xx_mfp_set_rdh(int mfp, int rdh);
565void pxa3xx_mfp_set_lpm(int mfp, int lpm);
566void pxa3xx_mfp_set_edge(int mfp, int edge);
567
568/*
569 * pxa3xx_mfp_config - configure the MFPR registers
570 *
571 * used by board specific initialization code
572 */
573void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num);
574
575/*
576 * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
577 * index and MFPR register offset
578 *
579 * used by processor specific code
580 */
581void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
582void __init pxa3xx_init_mfp(void);
583 310
584#endif /* __ASM_ARCH_MFP_H */ 311#endif /* __ASM_ARCH_MFP_H */
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
index ef4f570381d1..6d1304c9270f 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -17,5 +17,7 @@ struct pxamci_platform_data {
17}; 17};
18 18
19extern void pxa_set_mci_info(struct pxamci_platform_data *info); 19extern void pxa_set_mci_info(struct pxamci_platform_data *info);
20extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info);
21extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info);
20 22
21#endif 23#endif
diff --git a/include/asm-arm/arch-pxa/pcm027.h b/include/asm-arm/arch-pxa/pcm027.h
new file mode 100644
index 000000000000..7beae1472c3e
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pcm027.h
@@ -0,0 +1,75 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pcm027.h
3 *
4 * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
5 * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
23 * Definitions of CPU card resources only
24 */
25
26/* I2C RTC */
27#define PCM027_RTC_IRQ_GPIO 0
28#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
29#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
30#define ADR_PCM027_RTC 0x51 /* I2C address */
31
32/* I2C EEPROM */
33#define ADR_PCM027_EEPROM 0x54 /* I2C address */
34
35/* Ethernet chip (SMSC91C111) */
36#define PCM027_ETH_IRQ_GPIO 52
37#define PCM027_ETH_IRQ IRQ_GPIO(PCM027_ETH_IRQ_GPIO)
38#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING
39#define PCM027_ETH_PHYS PXA_CS5_PHYS
40#define PCM027_ETH_SIZE (1*1024*1024)
41
42/* CAN controller SJA1000 (unsupported yet) */
43#define PCM027_CAN_IRQ_GPIO 114
44#define PCM027_CAN_IRQ IRQ_GPIO(PCM027_CAN_IRQ_GPIO)
45#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
46#define PCM027_CAN_PHYS 0x22000000
47#define PCM027_CAN_SIZE 0x100
48
49/* SPI GPIO expander (unsupported yet) */
50#define PCM027_EGPIO_IRQ_GPIO 27
51#define PCM027_EGPIO_IRQ IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO)
52#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
53#define PCM027_EGPIO_CS 24
54/*
55 * TODO: Switch this pin from dedicated usage to GPIO if
56 * more than the MAX7301 device is connected to this SPI bus
57 */
58#define PCM027_EGPIO_CS_MODE GPIO24_SFRM_MD
59
60/* Flash memory */
61#define PCM027_FLASH_PHYS 0x00000000
62#define PCM027_FLASH_SIZE 0x02000000
63
64/* onboard LEDs connected to GPIO */
65#define PCM027_LED_CPU 90
66#define PCM027_LED_HEARD_BEAT 91
67
68/*
69 * This CPU module needs a baseboard to work. After basic initializing
70 * its own devices, it calls baseboard's init function.
71 * TODO: Add your own basebaord init function and call it from
72 * inside pcm027_init(). This example here is for the developmen board.
73 * Refer pcm990-baseboard.c
74 */
75extern void pcm990_baseboard_init(void);
diff --git a/include/asm-arm/arch-pxa/pcm990_baseboard.h b/include/asm-arm/arch-pxa/pcm990_baseboard.h
new file mode 100644
index 000000000000..b699d0d7bdb2
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pcm990_baseboard.h
@@ -0,0 +1,275 @@
1/*
2 * include/asm-arm/arch-pxa/pcm990_baseboard.h
3 *
4 * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
5 * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <asm/arch/pcm027.h>
23
24/*
25 * definitions relevant only when the PCM-990
26 * development base board is in use
27 */
28
29/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
30#define PCM990_CTRL_INT_IRQ_GPIO 9
31#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
32#define PCM990_CTRL_INT_IRQ_EDGE IRQT_RISING
33#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
34#define PCM990_CTRL_BASE 0xea000000
35#define PCM990_CTRL_SIZE (1*1024*1024)
36
37#define PCM990_CTRL_PWR_IRQ_GPIO 14
38#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
39#define PCM990_CTRL_PWR_IRQ_EDGE IRQT_RISING
40
41/* visible CPLD (U7) registers */
42#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
43#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
44#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
45#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
46
47#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
48#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
49#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
50#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
51
52#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
53#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
54#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */
55#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */
56
57#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */
58#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */
59#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */
60#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */
61#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */
62
63#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */
64#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */
65
66#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */
67#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */
68#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */
69#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */
70#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */
71
72#define PCM990_CTRL_REG6 0x000C /* Interrupt Clear REGISTER */
73#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */
74#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */
75#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */
76#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */
77
78#define PCM990_CTRL_REG7 0x000E /* Interrupt Enable REGISTER */
79#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */
80#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */
81#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */
82#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */
83
84#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */
85#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */
86#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */
87#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */
88#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */
89
90#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */
91#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */
92#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */
93#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */
94
95#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */
96#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */
97#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */
98
99#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */
100#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */
101#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */
102#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */
103#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */
104
105#define PCM990_CTRL_P2V(x) ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
106#define PCM990_CTRL_V2P(x) ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
107
108#ifndef __ASSEMBLY__
109# define __PCM990_CTRL_REG(x) \
110 (*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
111#else
112# define __PCM990_CTRL_REG(x) PCM990_CTRL_P2V(x)
113#endif
114
115#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
116#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
117#define PCM990_CTRL0 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
118#define PCM990_CTRL1 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
119#define PCM990_CTRL2 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
120#define PCM990_CTRL3 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
121#define PCM990_CTRL4 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
122#define PCM990_CTRL5 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
123#define PCM990_CTRL6 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
124#define PCM990_CTRL7 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
125#define PCM990_CTRL8 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
126#define PCM990_CTRL9 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
127#define PCM990_CTRL10 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
128#define PCM990_CTRL11 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
129
130
131/*
132 * IDE
133 */
134#define PCM990_IDE_IRQ_GPIO 13
135#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
136#define PCM990_IDE_IRQ_EDGE IRQT_RISING
137#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
138#define PCM990_IDE_PLD_BASE 0xee000000
139#define PCM990_IDE_PLD_SIZE (1*1024*1024)
140
141/* visible CPLD (U6) registers */
142#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */
143#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */
144#define PCM990_IDE_STBY 0x0008 /* R System StandBy */
145
146#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */
147#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */
148#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */
149#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */
150
151#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */
152#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */
153#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */
154#define PCM990_IDE_RDY 0x0008 /* RDY */
155
156#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */
157#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */
158#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */
159#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */
160
161#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */
162#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */
163#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */
164#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */
165
166#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
167#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
168
169#ifndef __ASSEMBLY__
170# define __PCM990_IDE_PLD_REG(x) \
171 (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
172#else
173# define __PCM990_IDE_PLD_REG(x) PCM990_IDE_PLD_P2V(x)
174#endif
175
176#define PCM990_IDE0 \
177 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
178#define PCM990_IDE1 \
179 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
180#define PCM990_IDE2 \
181 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
182#define PCM990_IDE3 \
183 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
184#define PCM990_IDE4 \
185 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
186
187/*
188 * Compact Flash
189 */
190#define PCM990_CF_IRQ_GPIO 11
191#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO)
192#define PCM990_CF_IRQ_EDGE IRQT_RISING
193
194#define PCM990_CF_CD_GPIO 12
195#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO)
196#define PCM990_CF_CD_EDGE IRQT_RISING
197
198#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
199#define PCM990_CF_PLD_BASE 0xef000000
200#define PCM990_CF_PLD_SIZE (1*1024*1024)
201#define PCM990_CF_PLD_P2V(x) ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
202#define PCM990_CF_PLD_V2P(x) ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
203
204/* visible CPLD (U6) registers */
205#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */
206#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */
207#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */
208#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */
209#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */
210
211#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */
212#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */
213#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */
214
215#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */
216#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */
217#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */
218#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */
219
220#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */
221#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */
222#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */
223#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */
224#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */
225
226#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */
227#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */
228#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
229#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */
230#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */
231
232#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */
233#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */
234#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */
235#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */
236#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */
237
238#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */
239#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */
240#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */
241
242#ifndef __ASSEMBLY__
243# define __PCM990_CF_PLD_REG(x) \
244 (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
245#else
246# define __PCM990_CF_PLD_REG(x) PCM990_CF_PLD_P2V(x)
247#endif
248
249#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
250#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
251#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
252#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
253#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
254#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
255#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
256
257/*
258 * Wolfson AC97 Touch
259 */
260#define PCM990_AC97_IRQ_GPIO 10
261#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
262#define PCM990_AC97_IRQ_EDGE IRQT_RISING
263
264/*
265 * MMC phyCORE
266 */
267#define PCM990_MMC0_IRQ_GPIO 9
268#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
269#define PCM990_MMC0_IRQ_EDGE IRQT_FALLING
270
271/*
272 * USB phyCore
273 */
274#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
275#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 1bd398da07da..442494d71f12 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1597,176 +1597,10 @@
1597#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ 1597#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1598#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ 1598#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1599 1599
1600
1601/* 1600/*
1602 * SSP Serial Port Registers 1601 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
1603 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
1604 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
1605 */ 1602 */
1606 1603
1607 /* Common PXA2xx bits first */
1608#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
1609#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
1610#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
1611#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
1612#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
1613#define SSCR0_National (0x2 << 4) /* National Microwire */
1614#define SSCR0_ECS (1 << 6) /* External clock select */
1615#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
1616#if defined(CONFIG_PXA25x)
1617#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
1618#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
1619#elif defined(CONFIG_PXA27x)
1620#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
1621#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
1622#define SSCR0_EDSS (1 << 20) /* Extended data size select */
1623#define SSCR0_NCS (1 << 21) /* Network clock select */
1624#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
1625#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
1626#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
1627#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
1628#define SSCR0_ADC (1 << 30) /* Audio clock select */
1629#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
1630#endif
1631
1632#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
1633#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
1634#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
1635#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
1636#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
1637#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
1638#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
1639#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
1640#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
1641#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
1642
1643#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
1644#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
1645#define SSSR_BSY (1 << 4) /* SSP Busy */
1646#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
1647#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
1648#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
1649
1650#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
1651#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
1652#define SSCR0_NCS (1 << 21) /* Network Clock Select */
1653#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
1654
1655/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
1656#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
1657#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
1658#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
1659#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
1660#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
1661#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
1662#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
1663#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
1664#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
1665#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
1666#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
1667#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
1668#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
1669#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
1670#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
1671#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
1672#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
1673#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
1674
1675#define SSSR_BCE (1 << 23) /* Bit Count Error */
1676#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
1677#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
1678#define SSSR_EOC (1 << 20) /* End Of Chain */
1679#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
1680#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
1681
1682#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
1683#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
1684#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
1685#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
1686#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
1687#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
1688#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
1689#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
1690#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
1691
1692#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
1693#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
1694#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
1695
1696#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
1697#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
1698#define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
1699#define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
1700#define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
1701
1702/* Support existing PXA25x drivers */
1703#define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
1704#define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
1705#define SSSR SSSR_P1 /* SSP Status Register */
1706#define SSITR SSITR_P1 /* SSP Interrupt Test Register */
1707#define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
1708
1709/* PXA27x ports */
1710#if defined (CONFIG_PXA27x)
1711#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
1712#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
1713#define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */
1714#define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */
1715#define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */
1716#define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */
1717#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
1718#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
1719#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
1720#define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
1721#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
1722#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
1723#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
1724#define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */
1725#define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */
1726#define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */
1727#define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */
1728#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
1729#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
1730#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
1731#define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
1732#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
1733#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
1734#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
1735#define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */
1736#define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */
1737#define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */
1738#define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */
1739#else /* PXA255 (only port 2) and PXA26x ports*/
1740#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
1741#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
1742#define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
1743#define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
1744#define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
1745#define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
1746#define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
1747#define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
1748#define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
1749#define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
1750#define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
1751#define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
1752#define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
1753#define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
1754#define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
1755#define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
1756#endif
1757
1758#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
1759#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
1760#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
1761#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
1762#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
1763#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
1764#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
1765#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
1766#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
1767#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
1768#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
1769
1770/* 1604/*
1771 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h 1605 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
1772 */ 1606 */
@@ -2014,71 +1848,8 @@
2014 1848
2015#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ 1849#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
2016 1850
2017/*
2018 * Memory controller
2019 */
2020
2021#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
2022#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
2023#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
2024#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
2025#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
2026#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
2027#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
2028#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
2029#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
2030#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
2031#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
2032#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
2033#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
2034#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
2035#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
2036#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
2037#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
2038
2039/*
2040 * More handy macros for PCMCIA
2041 *
2042 * Arg is socket number
2043 */
2044#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
2045#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
2046#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
2047
2048/* MECR register defines */
2049#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
2050#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
2051
2052#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
2053#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
2054#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
2055#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
2056#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
2057#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
2058#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
2059#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
2060#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
2061#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
2062#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
2063#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
2064#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
2065#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
2066
2067
2068#ifdef CONFIG_PXA27x 1851#ifdef CONFIG_PXA27x
2069 1852
2070#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
2071
2072#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
2073#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
2074#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
2075#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
2076#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
2077#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
2078#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
2079#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
2080#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
2081
2082/* 1853/*
2083 * Keypad 1854 * Keypad
2084 */ 1855 */
@@ -2135,74 +1906,6 @@
2135#define KPAS_SO (0x1 << 31) 1906#define KPAS_SO (0x1 << 31)
2136#define KPASMKPx_SO (0x1 << 31) 1907#define KPASMKPx_SO (0x1 << 31)
2137 1908
2138/*
2139 * UHC: USB Host Controller (OHCI-like) register definitions
2140 */
2141#define UHC_BASE_PHYS (0x4C000000)
2142#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
2143#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
2144#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
2145#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
2146#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
2147#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
2148#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
2149#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
2150#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
2151#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
2152#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
2153#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
2154#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
2155#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
2156#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
2157#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
2158#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
2159#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
2160
2161#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
2162#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
2163
2164#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
2165#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
2166#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
2167#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
2168#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
2169
2170#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
2171#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
2172#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
2173#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
2174#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
2175#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
2176#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
2177#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
2178#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
2179#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
2180
2181#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
2182#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
2183#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
2184#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
2185#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
2186#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
2187#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
2188#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
2189#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
2190#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
2191#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
2192#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
2193
2194#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
2195#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
2196#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
2197#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
2198#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
2199#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
2200 Interrupt Enable*/
2201#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
2202#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
2203
2204#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
2205
2206/* Camera Interface */ 1909/* Camera Interface */
2207#define CICR0 __REG(0x50000000) 1910#define CICR0 __REG(0x50000000)
2208#define CICR1 __REG(0x50000004) 1911#define CICR1 __REG(0x50000004)
@@ -2350,6 +2053,77 @@
2350 2053
2351#endif 2054#endif
2352 2055
2056#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
2057/*
2058 * UHC: USB Host Controller (OHCI-like) register definitions
2059 */
2060#define UHC_BASE_PHYS (0x4C000000)
2061#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
2062#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
2063#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
2064#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
2065#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
2066#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
2067#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
2068#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
2069#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
2070#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
2071#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
2072#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
2073#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
2074#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
2075#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
2076#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
2077#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
2078#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
2079
2080#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
2081#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
2082
2083#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
2084#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
2085#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
2086#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
2087#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
2088
2089#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
2090#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
2091#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
2092#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
2093#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
2094#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
2095#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
2096#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
2097#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
2098#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
2099
2100#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
2101#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
2102#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
2103#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
2104#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
2105#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
2106#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
2107#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
2108#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
2109#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
2110#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
2111#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
2112
2113#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
2114#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
2115#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
2116#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
2117#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
2118#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
2119 Interrupt Enable*/
2120#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
2121#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
2122
2123#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
2124
2125#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
2126
2353/* PWRMODE register M field values */ 2127/* PWRMODE register M field values */
2354 2128
2355#define PWRMODE_IDLE 0x1 2129#define PWRMODE_IDLE 0x1
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
new file mode 100644
index 000000000000..9553b54fa5bc
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -0,0 +1,84 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pxa2xx-regs.h
3 *
4 * Taken from pxa-regs.h by Russell King
5 *
6 * Author: Nicolas Pitre
7 * Copyright: MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __PXA2XX_REGS_H
15#define __PXA2XX_REGS_H
16
17/*
18 * Memory controller
19 */
20
21#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
22#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
23#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
24#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
25#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
26#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
27#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
28#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
29#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
30#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
31#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
32#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
33#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
34#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
35#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
36#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
37#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
38
39/*
40 * More handy macros for PCMCIA
41 *
42 * Arg is socket number
43 */
44#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
45#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
46#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
47
48/* MECR register defines */
49#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
50#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
51
52#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
53#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
54#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
55#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
56#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
57#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
58#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
59#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
60#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
61#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
62#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
63#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
64#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
65#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
66
67
68#ifdef CONFIG_PXA27x
69
70#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
71
72#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
73#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
74#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
75#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
76#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
77#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
78#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
79#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
80#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
81
82#endif
83
84#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h
index acc7ec7a84a1..3459fb26ce97 100644
--- a/include/asm-arm/arch-pxa/pxa2xx_spi.h
+++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h
@@ -22,32 +22,8 @@
22#define PXA2XX_CS_ASSERT (0x01) 22#define PXA2XX_CS_ASSERT (0x01)
23#define PXA2XX_CS_DEASSERT (0x02) 23#define PXA2XX_CS_DEASSERT (0x02)
24 24
25#if defined(CONFIG_PXA25x)
26#define CLOCK_SPEED_HZ 3686400
27#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00)
28#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
29#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
30#elif defined(CONFIG_PXA27x)
31#define CLOCK_SPEED_HZ 13000000
32#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
33#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
34#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
35#endif
36
37#define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1)))))
38#define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2)))))
39#define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3)))))
40
41enum pxa_ssp_type {
42 SSP_UNDEFINED = 0,
43 PXA25x_SSP, /* pxa 210, 250, 255, 26x */
44 PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
45 PXA27x_SSP,
46};
47
48/* device.platform_data for SSP controller devices */ 25/* device.platform_data for SSP controller devices */
49struct pxa2xx_spi_master { 26struct pxa2xx_spi_master {
50 enum pxa_ssp_type ssp_type;
51 u32 clock_enable; 27 u32 clock_enable;
52 u16 num_chipselect; 28 u16 num_chipselect;
53 u8 enable_dma; 29 u8 enable_dma;
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
index 3900a0ca0bc0..66d54119757c 100644
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -14,6 +14,92 @@
14#define __ASM_ARCH_PXA3XX_REGS_H 14#define __ASM_ARCH_PXA3XX_REGS_H
15 15
16/* 16/*
17 * Slave Power Managment Unit
18 */
19#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
20#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
21#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
22#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
23#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
24#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
25#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
26#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */
27#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */
28#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */
29#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */
30#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */
31#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */
32#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */
33
34/*
35 * Application Subsystem Configuration bits.
36 */
37#define ASCR_RDH (1 << 31)
38#define ASCR_D1S (1 << 2)
39#define ASCR_D2S (1 << 1)
40#define ASCR_D3S (1 << 0)
41
42/*
43 * Application Reset Status bits.
44 */
45#define ARSR_GPR (1 << 3)
46#define ARSR_LPMR (1 << 2)
47#define ARSR_WDT (1 << 1)
48#define ARSR_HWR (1 << 0)
49
50/*
51 * Application Subsystem Wake-Up bits.
52 */
53#define ADXER_WRTC (1 << 31) /* RTC */
54#define ADXER_WOST (1 << 30) /* OS Timer */
55#define ADXER_WTSI (1 << 29) /* Touchscreen */
56#define ADXER_WUSBH (1 << 28) /* USB host */
57#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */
58#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/
59#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */
60#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */
61#define ADXER_WKP (1 << 21) /* Keypad */
62#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */
63#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */
64#define ADXER_WOTG (1 << 16) /* USBOTG input */
65#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */
66#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */
67#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */
68#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */
69#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */
70#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */
71#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */
72#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */
73#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */
74#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */
75#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */
76#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */
77#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */
78#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */
79#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */
80#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */
81
82/*
83 * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320.
84 */
85#define ADXR_L2 (1 << 8)
86#define ADXR_R5 (1 << 5)
87#define ADXR_R4 (1 << 4)
88#define ADXR_R3 (1 << 3)
89#define ADXR_R2 (1 << 2)
90#define ADXR_R1 (1 << 1)
91#define ADXR_R0 (1 << 0)
92
93/*
94 * Values for PWRMODE CP15 register
95 */
96#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */
97#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */
98#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */
99#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */
100#define PXA3xx_PM_S0D0C1 0x01
101
102/*
17 * Application Subsystem Clock 103 * Application Subsystem Clock
18 */ 104 */
19#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ 105#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
new file mode 100644
index 000000000000..991cb688db75
--- /dev/null
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -0,0 +1,112 @@
1#ifndef __ASM_ARCH_REGS_SSP_H
2#define __ASM_ARCH_REGS_SSP_H
3
4/*
5 * SSP Serial Port Registers
6 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
7 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
8 */
9
10#define SSCR0 (0x00) /* SSP Control Register 0 */
11#define SSCR1 (0x04) /* SSP Control Register 1 */
12#define SSSR (0x08) /* SSP Status Register */
13#define SSITR (0x0C) /* SSP Interrupt Test Register */
14#define SSDR (0x10) /* SSP Data Write/Data Read Register */
15
16#define SSTO (0x28) /* SSP Time Out Register */
17#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
18#define SSTSA (0x30) /* SSP Tx Timeslot Active */
19#define SSRSA (0x34) /* SSP Rx Timeslot Active */
20#define SSTSS (0x38) /* SSP Timeslot Status */
21#define SSACD (0x3C) /* SSP Audio Clock Divider */
22
23/* Common PXA2xx bits first */
24#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
25#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
26#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
27#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
28#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
29#define SSCR0_National (0x2 << 4) /* National Microwire */
30#define SSCR0_ECS (1 << 6) /* External clock select */
31#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
32#if defined(CONFIG_PXA25x)
33#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
34#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
35#elif defined(CONFIG_PXA27x)
36#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
37#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
38#define SSCR0_EDSS (1 << 20) /* Extended data size select */
39#define SSCR0_NCS (1 << 21) /* Network clock select */
40#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
41#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
42#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
43#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
44#define SSCR0_ADC (1 << 30) /* Audio clock select */
45#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
46#endif
47
48#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
49#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
50#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
51#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
52#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
53#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
54#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
55#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
56#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
57#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
58
59#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
60#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
61#define SSSR_BSY (1 << 4) /* SSP Busy */
62#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
63#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
64#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
65
66#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
67#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
68#define SSCR0_NCS (1 << 21) /* Network Clock Select */
69#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
70
71/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
72#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
73#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
74#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
75#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
76#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
77#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
78#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
79#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
80#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
81#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
82#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
83#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
84#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
85#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
86#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
87#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
88#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
89#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
90
91#define SSSR_BCE (1 << 23) /* Bit Count Error */
92#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
93#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
94#define SSSR_EOC (1 << 20) /* End Of Chain */
95#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
96#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
97
98#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
99#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
100#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
101#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
102#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
103#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
104#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
105#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
106#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
107
108#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
109#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
110#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
111
112#endif /* __ASM_ARCH_REGS_SSP_H */
diff --git a/include/asm-arm/arch-pxa/sharpsl.h b/include/asm-arm/arch-pxa/sharpsl.h
index 2b0fe773213a..3b1d4a72d4d1 100644
--- a/include/asm-arm/arch-pxa/sharpsl.h
+++ b/include/asm-arm/arch-pxa/sharpsl.h
@@ -16,7 +16,7 @@ int corgi_ssp_max1111_get(unsigned long data);
16 */ 16 */
17 17
18struct corgits_machinfo { 18struct corgits_machinfo {
19 unsigned long (*get_hsync_len)(void); 19 unsigned long (*get_hsync_invperiod)(void);
20 void (*put_hsync)(void); 20 void (*put_hsync)(void);
21 void (*wait_hsync)(void); 21 void (*wait_hsync)(void);
22}; 22};
diff --git a/include/asm-arm/arch-pxa/spitz.h b/include/asm-arm/arch-pxa/spitz.h
index 4953dd324d4d..bd14365f7ed5 100644
--- a/include/asm-arm/arch-pxa/spitz.h
+++ b/include/asm-arm/arch-pxa/spitz.h
@@ -156,5 +156,3 @@ extern struct platform_device spitzscoop_device;
156extern struct platform_device spitzscoop2_device; 156extern struct platform_device spitzscoop2_device;
157extern struct platform_device spitzssp_device; 157extern struct platform_device spitzssp_device;
158extern struct sharpsl_charger_machinfo spitz_pm_machinfo; 158extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
159
160extern void spitz_lcd_power(int on, struct fb_var_screeninfo *var);
diff --git a/include/asm-arm/arch-pxa/ssp.h b/include/asm-arm/arch-pxa/ssp.h
index ea200551a75f..a012882c9ee6 100644
--- a/include/asm-arm/arch-pxa/ssp.h
+++ b/include/asm-arm/arch-pxa/ssp.h
@@ -13,10 +13,37 @@
13 * PXA255 SSP, NSSP 13 * PXA255 SSP, NSSP
14 * PXA26x SSP, NSSP, ASSP 14 * PXA26x SSP, NSSP, ASSP
15 * PXA27x SSP1, SSP2, SSP3 15 * PXA27x SSP1, SSP2, SSP3
16 * PXA3xx SSP1, SSP2, SSP3, SSP4
16 */ 17 */
17 18
18#ifndef SSP_H 19#ifndef __ASM_ARCH_SSP_H
19#define SSP_H 20#define __ASM_ARCH_SSP_H
21
22#include <linux/list.h>
23
24enum pxa_ssp_type {
25 SSP_UNDEFINED = 0,
26 PXA25x_SSP, /* pxa 210, 250, 255, 26x */
27 PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
28 PXA27x_SSP,
29};
30
31struct ssp_device {
32 struct platform_device *pdev;
33 struct list_head node;
34
35 struct clk *clk;
36 void __iomem *mmio_base;
37 unsigned long phys_base;
38
39 const char *label;
40 int port_id;
41 int type;
42 int use_count;
43 int irq;
44 int drcmr_rx;
45 int drcmr_tx;
46};
20 47
21/* 48/*
22 * SSP initialisation flags 49 * SSP initialisation flags
@@ -31,6 +58,7 @@ struct ssp_state {
31}; 58};
32 59
33struct ssp_dev { 60struct ssp_dev {
61 struct ssp_device *ssp;
34 u32 port; 62 u32 port;
35 u32 mode; 63 u32 mode;
36 u32 flags; 64 u32 flags;
@@ -50,4 +78,6 @@ int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
50int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); 78int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
51void ssp_exit(struct ssp_dev *dev); 79void ssp_exit(struct ssp_dev *dev);
52 80
53#endif 81struct ssp_device *ssp_request(int port, const char *label);
82void ssp_free(struct ssp_device *);
83#endif /* __ASM_ARCH_SSP_H */
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index 178aa2e073ac..dadf4c20b622 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -9,19 +9,21 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#define FFUART ((volatile unsigned long *)0x40100000) 12#include <linux/serial_reg.h>
13#define BTUART ((volatile unsigned long *)0x40200000) 13#include <asm/arch/pxa-regs.h>
14#define STUART ((volatile unsigned long *)0x40700000) 14
15#define HWUART ((volatile unsigned long *)0x41600000) 15#define __REG(x) ((volatile unsigned long *)x)
16 16
17#define UART FFUART 17#define UART FFUART
18 18
19 19
20static inline void putc(char c) 20static inline void putc(char c)
21{ 21{
22 while (!(UART[5] & 0x20)) 22 if (!(UART[UART_IER] & IER_UUE))
23 return;
24 while (!(UART[UART_LSR] & LSR_TDRQ))
23 barrier(); 25 barrier();
24 UART[0] = c; 26 UART[UART_TX] = c;
25} 27}
26 28
27/* 29/*
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index f58b59162b82..5f717d64ea7d 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -3,9 +3,18 @@
3 3
4#define ZYLONITE_ETH_PHYS 0x14000000 4#define ZYLONITE_ETH_PHYS 0x14000000
5 5
6#define EXT_GPIO(x) (128 + (x))
7
6/* the following variables are processor specific and initialized 8/* the following variables are processor specific and initialized
7 * by the corresponding zylonite_pxa3xx_init() 9 * by the corresponding zylonite_pxa3xx_init()
8 */ 10 */
11struct platform_mmc_slot {
12 int gpio_cd;
13 int gpio_wp;
14};
15
16extern struct platform_mmc_slot zylonite_mmc_slot[];
17
9extern int gpio_backlight; 18extern int gpio_backlight;
10extern int gpio_eth_irq; 19extern int gpio_eth_irq;
11 20
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-02 02:29:07 -0400