diff options
| -rw-r--r-- | drivers/staging/comedi/drivers/ni_660x.c | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/drivers/staging/comedi/drivers/ni_660x.c b/drivers/staging/comedi/drivers/ni_660x.c index 404d3c516ed1..df61e5a03ae1 100644 --- a/drivers/staging/comedi/drivers/ni_660x.c +++ b/drivers/staging/comedi/drivers/ni_660x.c | |||
| @@ -52,7 +52,8 @@ enum ni_660x_constants { | |||
| 52 | }; | 52 | }; |
| 53 | 53 | ||
| 54 | #define NUM_PFI_CHANNELS 40 | 54 | #define NUM_PFI_CHANNELS 40 |
| 55 | /* really there are only up to 3 dma channels, but the register layout allows for 4 */ | 55 | /* really there are only up to 3 dma channels, but the register layout allows |
| 56 | for 4 */ | ||
| 56 | #define MAX_DMA_CHANNEL 4 | 57 | #define MAX_DMA_CHANNEL 4 |
| 57 | 58 | ||
| 58 | /* See Register-Level Programmer Manual page 3.1 */ | 59 | /* See Register-Level Programmer Manual page 3.1 */ |
| @@ -198,7 +199,7 @@ struct NI_660xRegisterData { | |||
| 198 | const char *name; /* Register Name */ | 199 | const char *name; /* Register Name */ |
| 199 | int offset; /* Offset from base address from GPCT chip */ | 200 | int offset; /* Offset from base address from GPCT chip */ |
| 200 | enum ni_660x_register_direction direction; | 201 | enum ni_660x_register_direction direction; |
| 201 | enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */ | 202 | enum ni_660x_register_width size; /*1 byte, 2 bytes, or 4 bytes*/ |
| 202 | }; | 203 | }; |
| 203 | 204 | ||
| 204 | static const struct NI_660xRegisterData registerData[NumRegisters] = { | 205 | static const struct NI_660xRegisterData registerData[NumRegisters] = { |
| @@ -382,8 +383,8 @@ enum global_interrupt_config_register_bits { | |||
| 382 | }; | 383 | }; |
| 383 | 384 | ||
| 384 | /* Offset of the GPCT chips from the base-adress of the card */ | 385 | /* Offset of the GPCT chips from the base-adress of the card */ |
| 385 | static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 }; /* First chip is at base-address + | 386 | /* First chip is at base-address + 0x00, etc. */ |
| 386 | 0x00, etc. */ | 387 | static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 }; |
| 387 | 388 | ||
| 388 | /* Board description*/ | 389 | /* Board description*/ |
| 389 | struct ni_660x_board { | 390 | struct ni_660x_board { |
| @@ -993,9 +994,9 @@ static int ni_660x_allocate_private(struct comedi_device *dev) | |||
| 993 | spin_lock_init(&private(dev)->mite_channel_lock); | 994 | spin_lock_init(&private(dev)->mite_channel_lock); |
| 994 | spin_lock_init(&private(dev)->interrupt_lock); | 995 | spin_lock_init(&private(dev)->interrupt_lock); |
| 995 | spin_lock_init(&private(dev)->soft_reg_copy_lock); | 996 | spin_lock_init(&private(dev)->soft_reg_copy_lock); |
| 996 | for (i = 0; i < NUM_PFI_CHANNELS; ++i) { | 997 | for (i = 0; i < NUM_PFI_CHANNELS; ++i) |
| 997 | private(dev)->pfi_output_selects[i] = pfi_output_select_counter; | 998 | private(dev)->pfi_output_selects[i] = pfi_output_select_counter; |
| 998 | } | 999 | |
| 999 | return 0; | 1000 | return 0; |
| 1000 | } | 1001 | } |
| 1001 | 1002 | ||
| @@ -1008,9 +1009,8 @@ static int ni_660x_alloc_mite_rings(struct comedi_device *dev) | |||
| 1008 | for (j = 0; j < counters_per_chip; ++j) { | 1009 | for (j = 0; j < counters_per_chip; ++j) { |
| 1009 | private(dev)->mite_rings[i][j] = | 1010 | private(dev)->mite_rings[i][j] = |
| 1010 | mite_alloc_ring(private(dev)->mite); | 1011 | mite_alloc_ring(private(dev)->mite); |
| 1011 | if (private(dev)->mite_rings[i][j] == NULL) { | 1012 | if (private(dev)->mite_rings[i][j] == NULL) |
| 1012 | return -ENOMEM; | 1013 | return -ENOMEM; |
| 1013 | } | ||
| 1014 | } | 1014 | } |
| 1015 | } | 1015 | } |
| 1016 | return 0; | 1016 | return 0; |
| @@ -1022,9 +1022,8 @@ static void ni_660x_free_mite_rings(struct comedi_device *dev) | |||
| 1022 | unsigned j; | 1022 | unsigned j; |
| 1023 | 1023 | ||
| 1024 | for (i = 0; i < board(dev)->n_chips; ++i) { | 1024 | for (i = 0; i < board(dev)->n_chips; ++i) { |
| 1025 | for (j = 0; j < counters_per_chip; ++j) { | 1025 | for (j = 0; j < counters_per_chip; ++j) |
| 1026 | mite_free_ring(private(dev)->mite_rings[i][j]); | 1026 | mite_free_ring(private(dev)->mite_rings[i][j]); |
| 1027 | } | ||
| 1028 | } | 1027 | } |
| 1029 | } | 1028 | } |
| 1030 | 1029 | ||
| @@ -1078,15 +1077,16 @@ static int ni_660x_attach(struct comedi_device *dev, | |||
| 1078 | s->insn_bits = ni_660x_dio_insn_bits; | 1077 | s->insn_bits = ni_660x_dio_insn_bits; |
| 1079 | s->insn_config = ni_660x_dio_insn_config; | 1078 | s->insn_config = ni_660x_dio_insn_config; |
| 1080 | s->io_bits = 0; /* all bits default to input */ | 1079 | s->io_bits = 0; /* all bits default to input */ |
| 1081 | /* we use the ioconfig registers to control dio direction, so zero output enables in stc dio control reg */ | 1080 | /* we use the ioconfig registers to control dio direction, so zero |
| 1081 | output enables in stc dio control reg */ | ||
| 1082 | ni_660x_write_register(dev, 0, 0, STCDIOControl); | 1082 | ni_660x_write_register(dev, 0, 0, STCDIOControl); |
| 1083 | 1083 | ||
| 1084 | private(dev)->counter_dev = ni_gpct_device_construct(dev, | 1084 | private(dev)->counter_dev = ni_gpct_device_construct(dev, |
| 1085 | &ni_gpct_write_register, | 1085 | &ni_gpct_write_register, |
| 1086 | &ni_gpct_read_register, | 1086 | &ni_gpct_read_register, |
| 1087 | ni_gpct_variant_660x, | 1087 | ni_gpct_variant_660x, |
| 1088 | ni_660x_num_counters | 1088 | ni_660x_num_counters |
| 1089 | (dev)); | 1089 | (dev)); |
| 1090 | if (private(dev)->counter_dev == NULL) | 1090 | if (private(dev)->counter_dev == NULL) |
| 1091 | return -ENOMEM; | 1091 | return -ENOMEM; |
| 1092 | for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) { | 1092 | for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) { |
| @@ -1118,12 +1118,12 @@ static int ni_660x_attach(struct comedi_device *dev, | |||
| 1118 | s->type = COMEDI_SUBD_UNUSED; | 1118 | s->type = COMEDI_SUBD_UNUSED; |
| 1119 | } | 1119 | } |
| 1120 | } | 1120 | } |
| 1121 | for (i = 0; i < board(dev)->n_chips; ++i) { | 1121 | for (i = 0; i < board(dev)->n_chips; ++i) |
| 1122 | init_tio_chip(dev, i); | 1122 | init_tio_chip(dev, i); |
| 1123 | } | 1123 | |
| 1124 | for (i = 0; i < ni_660x_num_counters(dev); ++i) { | 1124 | for (i = 0; i < ni_660x_num_counters(dev); ++i) |
| 1125 | ni_tio_init_counter(&private(dev)->counter_dev->counters[i]); | 1125 | ni_tio_init_counter(&private(dev)->counter_dev->counters[i]); |
| 1126 | } | 1126 | |
| 1127 | for (i = 0; i < NUM_PFI_CHANNELS; ++i) { | 1127 | for (i = 0; i < NUM_PFI_CHANNELS; ++i) { |
| 1128 | if (i < min_counter_pfi_chan) | 1128 | if (i < min_counter_pfi_chan) |
| 1129 | ni_660x_set_pfi_routing(dev, i, pfi_output_select_do); | 1129 | ni_660x_set_pfi_routing(dev, i, pfi_output_select_do); |
| @@ -1134,9 +1134,9 @@ static int ni_660x_attach(struct comedi_device *dev, | |||
| 1134 | } | 1134 | } |
| 1135 | /* to be safe, set counterswap bits on tio chips after all the counter | 1135 | /* to be safe, set counterswap bits on tio chips after all the counter |
| 1136 | outputs have been set to high impedance mode */ | 1136 | outputs have been set to high impedance mode */ |
| 1137 | for (i = 0; i < board(dev)->n_chips; ++i) { | 1137 | for (i = 0; i < board(dev)->n_chips; ++i) |
| 1138 | set_tio_counterswap(dev, i); | 1138 | set_tio_counterswap(dev, i); |
| 1139 | } | 1139 | |
| 1140 | ret = request_irq(mite_irq(private(dev)->mite), ni_660x_interrupt, | 1140 | ret = request_irq(mite_irq(private(dev)->mite), ni_660x_interrupt, |
| 1141 | IRQF_SHARED, "ni_660x", dev); | 1141 | IRQF_SHARED, "ni_660x", dev); |
| 1142 | if (ret < 0) { | 1142 | if (ret < 0) { |
| @@ -1193,9 +1193,9 @@ static void init_tio_chip(struct comedi_device *dev, int chipset) | |||
| 1193 | private(dev)-> | 1193 | private(dev)-> |
| 1194 | dma_configuration_soft_copies[chipset], | 1194 | dma_configuration_soft_copies[chipset], |
| 1195 | DMAConfigRegister); | 1195 | DMAConfigRegister); |
| 1196 | for (i = 0; i < NUM_PFI_CHANNELS; ++i) { | 1196 | for (i = 0; i < NUM_PFI_CHANNELS; ++i) |
| 1197 | ni_660x_write_register(dev, chipset, 0, IOConfigReg(i)); | 1197 | ni_660x_write_register(dev, chipset, 0, IOConfigReg(i)); |
| 1198 | } | 1198 | |
| 1199 | } | 1199 | } |
| 1200 | 1200 | ||
| 1201 | static int | 1201 | static int |
