2 files changed, 138 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index ec779072a0a3..4adc28039c30 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -120,6 +120,37 @@
                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
                 >;
         };
+
+        nand_flash_x16: nand_flash_x16 {
+                /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+                 * So NAND flash requires following switch settings:
+                 * SW5.9 (GPMC_WPN) = LOW
+                 * SW5.1 (NAND_BOOTn) = HIGH */
+                pinctrl-single,pins = <
+                        0x0     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad0     */
+                        0x4     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad1     */
+                        0x8     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad2     */
+                        0xc     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad3     */
+                        0x10    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad4     */
+                        0x14    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad5     */
+                        0x18    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad6     */
+                        0x1c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad7     */
+                        0x20    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad8     */
+                        0x24    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad9     */
+                        0x28    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad10    */
+                        0x2c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad11    */
+                        0x30    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad12    */
+                        0x34    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad13    */
+                        0x38    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad14    */
+                        0x3c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad15    */
+                        0xd8    (PIN_INPUT_PULLUP  | MUX_MODE0) /* gpmc_wait0   */
+                        0xcc    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_wen     */
+                        0xb4    (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0    */
+                        0xc4    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_advn_ale */
+                        0xc8    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_oen_ren  */
+                        0xd0    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_be0n_cle */
+                >;
+        };
 };
 
 &i2c1 {
@@ -377,3 +408,90 @@
         pinctrl-names = "default";
         pinctrl-0 = <&usb2_pins>;
 };
+
+&elm {
+        status = "okay";
+};
+
+&gpmc {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&nand_flash_x16>;
+        ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
+        nand@0,0 {
+                reg = <0 0 4>;          /* device IO registers */
+                ti,nand-ecc-opt = "bch8";
+                ti,elm-id = <&elm>;
+                nand-bus-width = <16>;
+                gpmc,device-width = <2>;
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <40>;
+                gpmc,cs-wr-off-ns = <40>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <30>;
+                gpmc,adv-wr-off-ns = <30>;
+                gpmc,we-on-ns = <5>;
+                gpmc,we-off-ns = <25>;
+                gpmc,oe-on-ns = <2>;
+                gpmc,oe-off-ns = <20>;
+                gpmc,access-ns = <20>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,rd-cycle-ns = <40>;
+                gpmc,wr-cycle-ns = <40>;
+                gpmc,wait-pin = <0>;
+                gpmc,wait-on-read;
+                gpmc,wait-on-write;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                /* MTD partition table */
+                /* All SPL-* partitions are sized to minimal length
+                 * which can be independently programmable. For
+                 * NAND flash this is equal to size of erase-block */
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "NAND.SPL";
+                        reg = <0x00000000 0x000020000>;
+                };
+                partition@1 {
+                        label = "NAND.SPL.backup1";
+                        reg = <0x00020000 0x00020000>;
+                };
+                partition@2 {
+                        label = "NAND.SPL.backup2";
+                        reg = <0x00040000 0x00020000>;
+                };
+                partition@3 {
+                        label = "NAND.SPL.backup3";
+                        reg = <0x00060000 0x00020000>;
+                };
+                partition@4 {
+                        label = "NAND.u-boot-spl-os";
+                        reg = <0x00080000 0x00040000>;
+                };
+                partition@5 {
+                        label = "NAND.u-boot";
+                        reg = <0x000c0000 0x00100000>;
+                };
+                partition@6 {
+                        label = "NAND.u-boot-env";
+                        reg = <0x001c0000 0x00020000>;
+                };
+                partition@7 {
+                        label = "NAND.u-boot-env";
+                        reg = <0x001e0000 0x00020000>;
+                };
+                partition@8 {
+                        label = "NAND.kernel";
+                        reg = <0x00200000 0x00800000>;
+                };
+                partition@9 {
+                        label = "NAND.file-system";
+                        reg = <0x00a00000 0x0f600000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 6af8b080ea6d..a8a0ceec6775 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -964,6 +964,26 @@
                                 dr_mode = "otg";
                         };
                 };
+
+                elm: elm@48078000 {
+                        compatible = "ti,am3352-elm";
+                        reg = <0x48078000 0xfc0>;      /* device IO registers */
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "elm";
+                        status = "disabled";
+                };
+
+                gpmc: gpmc@50000000 {
+                        compatible = "ti,am3352-gpmc";
+                        ti,hwmods = "gpmc";
+                        reg = <0x50000000 0x37c>;      /* device IO registers */
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        gpmc,num-cs = <8>;
+                        gpmc,num-waitpins = <2>;
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                };
         };
 };